Xilinx FX60

Xilinx FX60

[Robert Woodworth]

After achieving complete success with my Linux kernel on the ML403, I've
now started to build a kernel for my real target board with a
Virtex4-FX60 (dual PPC cores)

Has anyone built a kernel for a dual core PPC Virtex?  I have found very
little docs on how to architect software for the dual-core PPC's.  
Will SMP Linux work on this platform?  What would the bus setup be?



My kernel is partially booting, some of the time... I'm mystified by the
situation.  One time, I get all the happy boot messages through the
UARTLite port, then the next reboot it stops at "Now booting the kernel"
I'm only getting about 10% successful boots......


My EDK setup is as follows;  I've disconnected the second PPC from the
PLB to have a single PPC system, 32MB DDR on PLB, TEMAC on PLB, UARTLite
on OPB.

RE: Xilinx FX60

[Wood, Robert (GE Indust, GE Fanuc)]

We've been using Virtex 2 PRO with dual cores. We found it necessary to
very tightly constrain clocks and resets. Also, constrain the reset
block to adjacent to the ports on the PPC.

Another lightly documented feature is that the core clock must be an
integer multiple of the PLB clock, say 300MHz/100MHz.

Robert Wood
GEFanuc Sensor Processing
5430 Canotek Road
Ottawa, Ontario
Canada K1J 9G2
613-749-9241 x270
=20

-----Original Message-----
From: linuxppc-embedded-bounces+rwood=3Dics-ltd.com@ozlabs.org
[mailto:linuxppc-embedded-bounces+rwood=3Dics-ltd.com@ozlabs.org] On
Behalf Of Robert Woodworth
Sent: Wednesday, September 05, 2007 2:42 PM
To: linuxppc-embedded@ozlabs.org
Subject: Xilinx FX60

After achieving complete success with my Linux kernel on the ML403, I've
now started to build a kernel for my real target board with a
Virtex4-FX60 (dual PPC cores)

Has anyone built a kernel for a dual core PPC Virtex?  I have found very
little docs on how to architect software for the dual-core PPC's. =20
Will SMP Linux work on this platform?  What would the bus setup be?



My kernel is partially booting, some of the time... I'm mystified by the
situation.  One time, I get all the happy boot messages through the
UARTLite port, then the next reboot it stops at "Now booting the kernel"
I'm only getting about 10% successful boots......


My EDK setup is as follows;  I've disconnected the second PPC from the
PLB to have a single PPC system, 32MB DDR on PLB, TEMAC on PLB, UARTLite
on OPB.

_______________________________________________
Linuxppc-embedded mailing list
Linuxppc-embedded@ozlabs.org
https://ozlabs.org/mailman/listinfo/linuxppc-embedded

RE: Xilinx FX60

[Robert Woodworth]

On Wed, 2007-09-05 at 14:56 -0400, Wood, Robert (GE Indust, GE Fanuc)
wrote:
> We've been using Virtex 2 PRO with dual cores. We found it necessary to
> very tightly constrain clocks and resets. Also, constrain the reset
> block to adjacent to the ports on the PPC.

What constraints did you tighten?? EDK or ISE?


> Another lightly documented feature is that the core clock must be an
> integer multiple of the PLB clock, say 300MHz/100MHz.
> 
> Robert Wood
> GEFanuc Sensor Processing
> 5430 Canotek Road
> Ottawa, Ontario
> Canada K1J 9G2
> 613-749-9241 x270
>  
> 
> -----Original Message-----
> From: linuxppc-embedded-bounces+rwood=ics-ltd.com@ozlabs.org
> [mailto:linuxppc-embedded-bounces+rwood=ics-ltd.com@ozlabs.org] On
> Behalf Of Robert Woodworth
> Sent: Wednesday, September 05, 2007 2:42 PM
> To: linuxppc-embedded@ozlabs.org
> Subject: Xilinx FX60
> 
> After achieving complete success with my Linux kernel on the ML403, I've
> now started to build a kernel for my real target board with a
> Virtex4-FX60 (dual PPC cores)
> 
> Has anyone built a kernel for a dual core PPC Virtex?  I have found very
> little docs on how to architect software for the dual-core PPC's.  
> Will SMP Linux work on this platform?  What would the bus setup be?
> 
> 
> 
> My kernel is partially booting, some of the time... I'm mystified by the
> situation.  One time, I get all the happy boot messages through the
> UARTLite port, then the next reboot it stops at "Now booting the kernel"
> I'm only getting about 10% successful boots......
> 
> 
> My EDK setup is as follows;  I've disconnected the second PPC from the
> PLB to have a single PPC system, 32MB DDR on PLB, TEMAC on PLB, UARTLite
> on OPB.
> 
> _______________________________________________
> Linuxppc-embedded mailing list
> Linuxppc-embedded@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-embedded

Re: Xilinx FX60

[Sergey Temerkhanov]

On Wednesday 05 September 2007 22:42:28 Robert Woodworth wrote:
> After achieving complete success with my Linux kernel on the ML403, I've
> now started to build a kernel for my real target board with a
> Virtex4-FX60 (dual PPC cores)
>
> Has anyone built a kernel for a dual core PPC Virtex?  I have found very
> little docs on how to architect software for the dual-core PPC's.
> Will SMP Linux work on this platform?  What would the bus setup be?

It won't. There is no hardware cache coherency on Virtex.

RE: Xilinx FX60

[Wood, Robert (GE Indust, GE Fanuc)]

In the UCF we tightened up the spec for the core clock by around 15%
rather than 10%.

The resets were given a max delay constraint and physical location.

Some examples taken from our UCF file.

NET EC_FPGA_RESET_N TIG;


NET "RSTC405RESETSYS" TPTHRU =3D RST_GRP;
NET "RSTC405RESETCHIP" TPTHRU =3D RST_GRP;
NET "RSTC405RESETCORE" TPTHRU =3D RST_GRP;
NET "C405RSTSYSRESETREQ" TPTHRU =3D RST_GRP;
NET "C405RSTCHIPRESETREQ" TPTHRU =3D RST_GRP;
NET "C405RSTCORERESETREQ" TPTHRU =3D RST_GRP;
TIMESPEC "TS_RST1" =3D FROM CPUS THRU RST_GRP TO FFS TIG;=20

# Constrain Placement on PPC:
INST "ppc405_0/ppc405_0/PPC405_i" LOC =3D PPC405_X1Y0;

# Constrain the Xilinx IP reset block close to the PPC:
INST reset_block* AREA_GROUP=3D"RESET_BLOCK_GRP";
AREA_GROUP "RESET_BLOCK_GRP" RANGE=3DSLICE_X94Y81:SLICE_X109Y72;

INST "reset_block/reset_block/Rstc405resetcore" TNM =3D
"reset_block/reset_block/Rstc405resetcore";
INST "reset_block/reset_block/Rstc405resetsys"  TNM =3D
"reset_block/reset_block/Rstc405resetsys";
INST "reset_block/reset_block/Rstc405resetchip" TNM =3D
"reset_block/reset_block/Rstc405resetchip";
INST "ppc405_0/ppc405_0/PPC405_i" TNM =3D "ppc405_0/ppc405_0/PPC405_i";
TIMESPEC "TS_reset_core" =3D FROM
"reset_block/reset_block/Rstc405resetcore" TO
"ppc405_0/ppc405_0/PPC405_i" 2.0 ns;
TIMESPEC "TS_reset_sys"  =3D FROM
"reset_block/reset_block/Rstc405resetsys"  TO
"ppc405_0/ppc405_0/PPC405_i" 2.0 ns;
TIMESPEC "TS_reset_chip" =3D FROM
"reset_block/reset_block/Rstc405resetchip" TO
"ppc405_0/ppc405_0/PPC405_i" 2.0 ns;

Robert Wood
GEFanuc Sensor Processing
5430 Canotek Road
Ottawa, Ontario
Canada K1J 9G2
613-749-9241 x270
=20
-----Original Message-----
From: Robert Woodworth [mailto:rwoodworth@securics.com]=20
Sent: Wednesday, September 05, 2007 3:31 PM
To: Wood, Robert (GE Indust, GE Fanuc)
Cc: linuxppc-embedded@ozlabs.org
Subject: RE: Xilinx FX60

On Wed, 2007-09-05 at 14:56 -0400, Wood, Robert (GE Indust, GE Fanuc)
wrote:
> We've been using Virtex 2 PRO with dual cores. We found it necessary
to
> very tightly constrain clocks and resets. Also, constrain the reset
> block to adjacent to the ports on the PPC.

What constraints did you tighten?? EDK or ISE?


> Another lightly documented feature is that the core clock must be an
> integer multiple of the PLB clock, say 300MHz/100MHz.
>=20
> Robert Wood
> GEFanuc Sensor Processing
> 5430 Canotek Road
> Ottawa, Ontario
> Canada K1J 9G2
> 613-749-9241 x270
> =20
>=20
> -----Original Message-----
> From: linuxppc-embedded-bounces+rwood=3Dics-ltd.com@ozlabs.org
> [mailto:linuxppc-embedded-bounces+rwood=3Dics-ltd.com@ozlabs.org] On
> Behalf Of Robert Woodworth
> Sent: Wednesday, September 05, 2007 2:42 PM
> To: linuxppc-embedded@ozlabs.org
> Subject: Xilinx FX60
>=20
> After achieving complete success with my Linux kernel on the ML403,
I've
> now started to build a kernel for my real target board with a
> Virtex4-FX60 (dual PPC cores)
>=20
> Has anyone built a kernel for a dual core PPC Virtex?  I have found
very
> little docs on how to architect software for the dual-core PPC's. =20
> Will SMP Linux work on this platform?  What would the bus setup be?
>=20
>=20
>=20
> My kernel is partially booting, some of the time... I'm mystified by
the
> situation.  One time, I get all the happy boot messages through the
> UARTLite port, then the next reboot it stops at "Now booting the
kernel"
> I'm only getting about 10% successful boots......
>=20
>=20
> My EDK setup is as follows;  I've disconnected the second PPC from the
> PLB to have a single PPC system, 32MB DDR on PLB, TEMAC on PLB,
UARTLite
> on OPB.
>=20
> _______________________________________________
> Linuxppc-embedded mailing list
> Linuxppc-embedded@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-embedded

Re: Xilinx FX60

[Robert Woodworth]

On Wed, 2007-09-05 at 23:42 +0400, Sergey Temerkhanov wrote:
> On Wednesday 05 September 2007 22:42:28 Robert Woodworth wrote:
> > After achieving complete success with my Linux kernel on the ML403, I've
> > now started to build a kernel for my real target board with a
> > Virtex4-FX60 (dual PPC cores)
> >
> > Has anyone built a kernel for a dual core PPC Virtex?  I have found very
> > little docs on how to architect software for the dual-core PPC's.
> > Will SMP Linux work on this platform?  What would the bus setup be?
> 
> It won't. There is no hardware cache coherency on Virtex.
> 
> 

Is it then possible to run two independent kernels, one on each PPC??



> 
> 
> 
> _______________________________________________
> Linuxppc-embedded mailing list
> Linuxppc-embedded@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-embedded

Re: Xilinx FX60

[Grant Likely]

On 9/5/07, Robert Woodworth <rwoodworth@securics.com> wrote:
> > > Has anyone built a kernel for a dual core PPC Virtex?  I have found very
> > > little docs on how to architect software for the dual-core PPC's.
> > > Will SMP Linux work on this platform?  What would the bus setup be?
> >
> > It won't. There is no hardware cache coherency on Virtex.
> >
> >
>
> Is it then possible to run two independent kernels, one on each PPC??

Absolutely.

Cheers
g.



-- 
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.
grant.likely@secretlab.ca
(403) 399-0195

Re: Xilinx FX60

[Ming Liu]

> > Is it then possible to run two independent kernels, one on each PPC??
>
>Absolutely.

Are you meaning two entirely seperate systems, or two ones which share a 
common HW such as memory space? Is that possible without any memory 
confliction?

BR
Ming

_________________________________________________________________
享用世界上最大的电子邮件系统― MSN Hotmail。  http://www.hotmail.com  

Re: Xilinx FX60

[Ming Liu]

>It won't. There is no hardware cache coherency on Virtex.

Is that possible if we turn off the cache?

BR
Ming

_________________________________________________________________
享用世界上最大的电子邮件系统― MSN Hotmail。  http://www.hotmail.com  

Re: Xilinx FX60

[Sergey Temerkhanov]

On Thursday 06 September 2007 00:20:28 Robert Woodworth wrote:
> Is it then possible to run two independent kernels, one on each PPC??
AMP must work there.

>
> > _______________________________________________
> > Linuxppc-embedded mailing list
> > Linuxppc-embedded@ozlabs.org
> > https://ozlabs.org/mailman/listinfo/linuxppc-embedded

Re: Xilinx FX60

[Sergey Temerkhanov]

On Thursday 06 September 2007 00:40:33 Ming Liu wrote:
> >It won't. There is no hardware cache coherency on Virtex.
>
> Is that possible if we turn off the cache?

Not in current versions. Implementation of SMP will require implementing 
functions from struct smp_ops_t (defined in include/asm-ppc/machdep.h) and 
some additional work. Maybe PIC redesign/modification will be needed. And 
after all there will be significant performance hit with caches disabled.

Re: Xilinx FX60

[Grant Likely]

On 9/5/07, Ming Liu <eemingliu@hotmail.com> wrote:
>
> > > Is it then possible to run two independent kernels, one on each PPC??
> >
> >Absolutely.
>
> Are you meaning two entirely seperate systems, or two ones which share a
> common HW such as memory space? Is that possible without any memory
> confliction?

You can share physical memory as long as each processor is dedicated
to separate regions.  However, Linux on power expects memory to be
based at 0.  Therefore you need to tweak the memory design so that the
second processor sees a different area of the ram based at zero.

You can even setup a shared memory region between the two processors,
but you that region should be cache-inhibited.

Cheers,
g.

-- 
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.
grant.likely@secretlab.ca
(403) 399-0195

Xilinx FX60

[Robert Woodworth]

I'm back trying to get the kernel on my Xilinx FX60 without success. 
Now I have more information:


Using the Xilinx GDB, I'm getting either a "Bad Page fault exception" or
a kernel "oops"


The text in the _log_buf is as follows: 
(this happens before serial console init)

Data machine check in kernel mode..
Oops: machine check, sig: 7 [#1].
<register dump>



Any Ideas what would cause this?  Memory problem?  
I've run several different embedded memory test programs on the PPC and
they all pass fine.

I've synthesized my FX60 with the exact same memory map as my FX12 on
the ML403 and used the same kernel config.  ML403 works great.


The only difference is that the FX60 board only has 32MB DDR, I have
made sure that the correct memory size is in the kernel.



??
RJW

Re: Xilinx FX60

[Grant Likely]

On 9/18/07, Robert Woodworth <rwoodworth@securics.com> wrote:
> I'm back trying to get the kernel on my Xilinx FX60 without success.
> Now I have more information:
>
> Using the Xilinx GDB, I'm getting either a "Bad Page fault exception" or
> a kernel "oops"
>
> The text in the _log_buf is as follows:
> (this happens before serial console init)
>
> Data machine check in kernel mode..
> Oops: machine check, sig: 7 [#1].
> <register dump>
>
>
>
> Any Ideas what would cause this?  Memory problem?
> I've run several different embedded memory test programs on the PPC and
> they all pass fine.

You might still be having memory issues.  Memory tests in general
don't hit memory as hard and fast as running code with caches enabled.

>
> I've synthesized my FX60 with the exact same memory map as my FX12 on
> the ML403 and used the same kernel config.  ML403 works great.

>
> The only difference is that the FX60 board only has 32MB DDR, I have
> made sure that the correct memory size is in the kernel.

How are you booting your kernel?  .ace? u-boot? load via debugger?

Cheers,
g.

-- 
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.
grant.likely@secretlab.ca
(403) 399-0195

Re: Xilinx FX60

[Robert Woodworth]

On Tue, 2007-09-18 at 15:02 -0600, Grant Likely wrote:
> >
> > The only difference is that the FX60 board only has 32MB DDR, I have
> > made sure that the correct memory size is in the kernel.
> 
> How are you booting your kernel?  .ace? u-boot? load via debugger?

load via debugger (Xilinx xmd)

FYI: the board I'm using is the
TB-4V-FX60
http://www.hitechglobal.com/TED/V4PowerPC.htm

> Cheers,
> g.
> 

RE: Xilinx FX60

[Koss, Mike (Mission Systems)]

Rob,

I have working image for that board that uses the MPMC2 that I've
successfully loaded our version of linux on. It uses a hacked-together
ll_temac driver. We did a lot of integration on that board before
finally moving to the ML410 because of not being able to get the SoDIMM
port to work.

-- Mike=20

-----Original Message-----
From: Robert Woodworth [mailto:rwoodworth@securics.com]=20
Sent: Tuesday, September 18, 2007 5:15 PM
To: Grant Likely
Cc: linuxppc-embedded@ozlabs.org
Subject: Re: Xilinx FX60

On Tue, 2007-09-18 at 15:02 -0600, Grant Likely wrote:
> >
> > The only difference is that the FX60 board only has 32MB DDR, I have

> > made sure that the correct memory size is in the kernel.
>=20
> How are you booting your kernel?  .ace? u-boot? load via debugger?

load via debugger (Xilinx xmd)

FYI: the board I'm using is the
TB-4V-FX60
http://www.hitechglobal.com/TED/V4PowerPC.htm

> Cheers,
> g.
>=20