[NEWBIE] Interrupt-problem mpc5200

[NEWBIE] Interrupt-problem mpc5200

[S. Fricke]

[-- Attachment #1: Type: text/plain, Size: 1262 bytes --]

Hello all.

What are the steps to configure an MPC500B-Board to react on an IRQ (2)?

I have written a test-driver with this code-snippets, but the prozessor
hangs when loading the driver.

my __init-function looks like:

static int __init mod_init( void ) 
{
    volatile static struct mpc52xx_intr __iomem *intr;
    u32 intr_ctrl;

    // ...

    printk( "intmod.ko: interrupt init ");
    if (request_irq(MPC52xx_IRQ2, intmod_isr, IRQF_SHARED , "intmod",
                INTMOD_IRQ_BOARD) == -EBUSY)
        printk("KO\n");
    else
        printk("OK\n");

    intr = ioremap(MPC52xx_MBAR+MPC52xx_INTR_OFFSET, MPC52xx_INTR_SIZE);

    // read - modify - write
    intr_ctrl = in_be32(&intr->ctrl);
    intr_ctrl &= 0xfff3ffff;
    intr_ctrl |= 0x00080200;
    out_be32(&intr->ctrl, intr_ctrl);       // ERROR!

    if(intr) iounmap(intr);

    // ...
}

On the Line, marked with "ERROR!" the prozessor hangs and the kernel drops
out.

TIA: Silvio

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Re: [NEWBIE] Interrupt-problem mpc5200

[S. Fricke]

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Dear Linux-enthusiasts,

I'm still at the same problem.

I have now implemented a irq_chip for the hardwired IRQ2. Now I have:


--==>
volatile static struct mpc52xx_intr __iomem *intr;
unsigned long flags;
static DEFINE_SPINLOCK(my_irq_controller_lock);

/*
 * HELPER-Function
 */
static inline void io_be_setbit(u32 __iomem *addr, int bitno)
{
    out_be32(addr, in_be32(addr) | (1 << bitno));
}

static inline void io_be_clrbit(u32 __iomem *addr, int bitno)
{
    out_be32(addr, in_be32(addr) & ~(1 << bitno));
}

/*
 * IRQ-Zeugs
 */
static void my_irq_ack(unsigned int irq)
{
    printk("%s(%s/%d):\n", __FILE__, __FUNCTION__, __LINE__);
    spin_lock_irqsave(&my_irq_controller_lock, flags);
    if(intr)
        io_be_setbit(&intr->ctrl, 25);
    spin_unlock_irqrestore(&my_irq_controller_lock, flags);
    printk("%s(%s/%d):\n", __FILE__, __FUNCTION__, __LINE__);
}

/* irq - disabled */
static void my_irq_mask(unsigned int irq)
{
    printk("%s(%s/%d):\n", __FILE__, __FUNCTION__, __LINE__);
    spin_lock_irqsave(&my_irq_controller_lock, flags);
    if(intr)
        io_be_clrbit(&intr->ctrl, 9); 
    spin_unlock_irqrestore(&my_irq_controller_lock, flags);
    printk("%s(%s/%d):\n", __FILE__, __FUNCTION__, __LINE__);
}

/* irq - enable */
static void my_irq_unmask(unsigned int irq)
{
    printk("%s(%s/%d):\n", __FILE__, __FUNCTION__, __LINE__);
    spin_lock_irqsave(&my_irq_controller_lock, flags);
    if(intr)
        io_be_setbit(&intr->ctrl, 9);
    spin_unlock_irqrestore(&my_irq_controller_lock, flags);
    printk("%s(%s/%d):\n", __FILE__, __FUNCTION__, __LINE__);
}

static struct irq_chip my_irq_chip = { 
    .typename   = "MY_IRQ_TEST",
    .ack        = my_irq_ack,
    .mask       = my_irq_mask,
    .unmask     = my_irq_unmask,
};

static int __init mod_init( void )
{
    // ...

    intr = mpc52xx_find_and_map("mpc52xx-pic");
    if(!intr) {
        panic(__FILE__ ": mpc52xx-pic - MAP failed");
    }

    set_irq_chip(MPC52xx_IRQ2, &my_irq_chip);
    a = request_irq(2, intmod_isr, IRQF_DISABLED , "intmod", INTMOD_IRQ_BOARD);
    printk("a: 0x%08x\n", a);

    // ...
}

<==--

Now my code hangs on the my_irq_unmask(...)-function on "io_be_setbit". Why?
Can anyone help me, or point me to the right newsgroup/forum?

So long!

Silvio


-- 
-- S. Fricke ----------------------------- MAILTO:silvio.fricke@gmail.com --
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Re: [NEWBIE] Interrupt-problem mpc5200

[Grant Likely]

On 9/11/07, S. Fricke <silvio.fricke@googlemail.com> wrote:
>
> Dear Linux-enthusiasts,
>
> I'm still at the same problem.
>
> I have now implemented a irq_chip for the hardwired IRQ2. Now I have:
>
>
> --==>
> volatile static struct mpc52xx_intr __iomem *intr;
> unsigned long flags;
> static DEFINE_SPINLOCK(my_irq_controller_lock);
>
> /*
>  * HELPER-Function
>  */
> static inline void io_be_setbit(u32 __iomem *addr, int bitno)
> {
>     out_be32(addr, in_be32(addr) | (1 << bitno));
> }
>
> static inline void io_be_clrbit(u32 __iomem *addr, int bitno)
> {
>     out_be32(addr, in_be32(addr) & ~(1 << bitno));
> }
>
> /*
>  * IRQ-Zeugs
>  */
> static void my_irq_ack(unsigned int irq)
> {
>     printk("%s(%s/%d):\n", __FILE__, __FUNCTION__, __LINE__);
>     spin_lock_irqsave(&my_irq_controller_lock, flags);
>     if(intr)
>         io_be_setbit(&intr->ctrl, 25);
>     spin_unlock_irqrestore(&my_irq_controller_lock, flags);
>     printk("%s(%s/%d):\n", __FILE__, __FUNCTION__, __LINE__);
> }
>
> /* irq - disabled */
> static void my_irq_mask(unsigned int irq)
> {
>     printk("%s(%s/%d):\n", __FILE__, __FUNCTION__, __LINE__);
>     spin_lock_irqsave(&my_irq_controller_lock, flags);
>     if(intr)
>         io_be_clrbit(&intr->ctrl, 9);
>     spin_unlock_irqrestore(&my_irq_controller_lock, flags);
>     printk("%s(%s/%d):\n", __FILE__, __FUNCTION__, __LINE__);
> }
>
> /* irq - enable */
> static void my_irq_unmask(unsigned int irq)
> {
>     printk("%s(%s/%d):\n", __FILE__, __FUNCTION__, __LINE__);
>     spin_lock_irqsave(&my_irq_controller_lock, flags);
>     if(intr)
>         io_be_setbit(&intr->ctrl, 9);
>     spin_unlock_irqrestore(&my_irq_controller_lock, flags);
>     printk("%s(%s/%d):\n", __FILE__, __FUNCTION__, __LINE__);
> }
>
> static struct irq_chip my_irq_chip = {
>     .typename   = "MY_IRQ_TEST",
>     .ack        = my_irq_ack,
>     .mask       = my_irq_mask,
>     .unmask     = my_irq_unmask,
> };
>
> static int __init mod_init( void )
> {
>     // ...
>
>     intr = mpc52xx_find_and_map("mpc52xx-pic");
>     if(!intr) {
>         panic(__FILE__ ": mpc52xx-pic - MAP failed");
>     }
>
>     set_irq_chip(MPC52xx_IRQ2, &my_irq_chip);

You probably don't want to do this (unless you are cascading IRQs to
custom external hardware).  All you should need is the call to
request_irq() to register your irq handler, and code in your ISR
handler to clear the interrupt condition.

You do *NOT* want to program the interrupt controller directly.  The
mpc5200 interrupt controller already has a driver.  Don't go twiddling
the registers manually.

Cheers,
g.

-- 
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.
grant.likely@secretlab.ca
(403) 399-0195

Re: [NEWBIE] Interrupt-problem mpc5200

[S. Fricke]

[-- Attachment #1: Type: text/plain, Size: 1477 bytes --]

Hello,

> >[...]
> >     intr = mpc52xx_find_and_map("mpc52xx-pic");
> >     if(!intr) {
> >         panic(__FILE__ ": mpc52xx-pic - MAP failed");
> >     }
> >
> >     set_irq_chip(MPC52xx_IRQ2, &my_irq_chip);
> 
> You probably don't want to do this (unless you are cascading IRQs to
> custom external hardware).  All you should need is the call to
> request_irq() to register your irq handler, and code in your ISR
> handler to clear the interrupt condition.
> 
> You do *NOT* want to program the interrupt controller directly.  The
> mpc5200 interrupt controller already has a driver.  Don't go twiddling
> the registers manually.

OK!

I have tried it before and i get a "-ENOSYS" returned.

My code was/is now:
--==>
request_irq(MPC52xx_IRQ2, intmod_isr, IRQF_DISABLED , "intmod",
            INTMOD_IRQ_BOARD);
<==--

I have looked up "kernel/irq/manage.c". "-ENOSYS" is returned on function
"setup_irq" because the used irq(MPC52xx_IRQ2) is the same as no_irq_chip.

THE MPC52xx_IRQ2 is a excerpt from "include/ppc/mpc52xx.h" (per copy
paste), but mpc52xx is (now) a powerpc-arch. What is the desired value for
IRQ-2 on a mpc5200b?

best regards,
Silvio Fricke


-- 
-- S. Fricke ----------------------------- MAILTO:silvio.fricke@gmail.com --
   Diplom-Informatiker (FH)
   Linux-Entwicklung                       JABBER:      fricke@jabber.org
----------------------------------------------------------------------------


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Re: [NEWBIE] Interrupt-problem mpc5200

[Grant Likely]

On 9/11/07, S. Fricke <silvio.fricke@googlemail.com> wrote:
> Hello,
>
> > >[...]
> > >     intr = mpc52xx_find_and_map("mpc52xx-pic");
> > >     if(!intr) {
> > >         panic(__FILE__ ": mpc52xx-pic - MAP failed");
> > >     }
> > >
> > >     set_irq_chip(MPC52xx_IRQ2, &my_irq_chip);
> >
> > You probably don't want to do this (unless you are cascading IRQs to
> > custom external hardware).  All you should need is the call to
> > request_irq() to register your irq handler, and code in your ISR
> > handler to clear the interrupt condition.
> >
> > You do *NOT* want to program the interrupt controller directly.  The
> > mpc5200 interrupt controller already has a driver.  Don't go twiddling
> > the registers manually.
>
> OK!
>
> I have tried it before and i get a "-ENOSYS" returned.
>
> My code was/is now:
> --==>
> request_irq(MPC52xx_IRQ2, intmod_isr, IRQF_DISABLED , "intmod",
>             INTMOD_IRQ_BOARD);
> <==--
>
> I have looked up "kernel/irq/manage.c". "-ENOSYS" is returned on function
> "setup_irq" because the used irq(MPC52xx_IRQ2) is the same as no_irq_chip.
>
> THE MPC52xx_IRQ2 is a excerpt from "include/ppc/mpc52xx.h" (per copy
> paste), but mpc52xx is (now) a powerpc-arch. What is the desired value for
> IRQ-2 on a mpc5200b?

The irq number you pass into request_irq is a system-wide irq number;
it doesn't necessarily map directly onto the MPC52xx irq number.
Typically, you'd have a node for your device in the device tree which
has a phandle back to the interrupt node and you would use
irq_of_parse_and_map() to map it back to a system-wide irq number.

Otherwise, you need to call of_irq_map_raw with the pointer to the
52xx interrupt controller node and the interrupt number in the form
expected by the device tree.  (But adding a device tree node for your
device is far easier).

Cheers,
g.

-- 
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.
grant.likely@secretlab.ca
(403) 399-0195

Re: [NEWBIE] Interrupt-problem mpc5200

[S. Fricke]

[-- Attachment #1: Type: text/plain, Size: 1205 bytes --]

Hello,

> > I have looked up "kernel/irq/manage.c". "-ENOSYS" is returned on function
> > "setup_irq" because the used irq(MPC52xx_IRQ2) is the same as no_irq_chip.
> >
> > THE MPC52xx_IRQ2 is a excerpt from "include/ppc/mpc52xx.h" (per copy
> > paste), but mpc52xx is (now) a powerpc-arch. What is the desired value for
> > IRQ-2 on a mpc5200b?
> 
> The irq number you pass into request_irq is a system-wide irq number;
> it doesn't necessarily map directly onto the MPC52xx irq number.
> Typically, you'd have a node for your device in the device tree which
> has a phandle back to the interrupt node and you would use
> irq_of_parse_and_map() to map it back to a system-wide irq number.

The IRQ-pin-2 belongs to "PIN-configuration-nodes" described in
"booting-without-of.txt"? Than, what is the QE for my MPC5200B?

Can u give me an example with a single IRQ of a configuration-node for a
dts?


TIA:
Silvio

-- 
-- S. Fricke ----------------------------- MAILTO:silvio.fricke@gmail.com --
   Diplom-Informatiker (FH)
   Linux-Entwicklung                       JABBER:      fricke@jabber.org
----------------------------------------------------------------------------


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Re: [NEWBIE] Interrupt-problem mpc5200

[Grant Likely]

On 9/12/07, S. Fricke <silvio.fricke@googlemail.com> wrote:
> Hello,
>
> > > I have looked up "kernel/irq/manage.c". "-ENOSYS" is returned on function
> > > "setup_irq" because the used irq(MPC52xx_IRQ2) is the same as no_irq_chip.
> > >
> > > THE MPC52xx_IRQ2 is a excerpt from "include/ppc/mpc52xx.h" (per copy
> > > paste), but mpc52xx is (now) a powerpc-arch. What is the desired value for
> > > IRQ-2 on a mpc5200b?
> >
> > The irq number you pass into request_irq is a system-wide irq number;
> > it doesn't necessarily map directly onto the MPC52xx irq number.
> > Typically, you'd have a node for your device in the device tree which
> > has a phandle back to the interrupt node and you would use
> > irq_of_parse_and_map() to map it back to a system-wide irq number.
>
> The IRQ-pin-2 belongs to "PIN-configuration-nodes" described in
> "booting-without-of.txt"? Than, what is the QE for my MPC5200B?
>
> Can u give me an example with a single IRQ of a configuration-node for a
> dts?

myreallycooldevice@0 {
        interrupts = <1 2 3>;
        interrupt-parent = <&mpc5200_pic>;
};

The interrupts property matches the size of the #interrupt-cells
property in the interrupt controller node.  For the 5200-intc, each
interrupt is described by 3 cells; l1, l2 and sense which is a
reflection of the interrupt controller architecture.  For IRQ0, l1=0,
l2=0; IRQ1, l1=1, l2=1; IRQ2, l1=1 and l2=2; IRQ3, l1=1, l2=3 Sense is
described in mpc52xx-device-tree-bindings.txt

Cheers,
g.

-- 
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.
grant.likely@secretlab.ca
(403) 399-0195

Re: [NEWBIE] Interrupt-problem mpc5200

[S. Fricke]

[-- Attachment #1: Type: text/plain, Size: 1740 bytes --]

Hello,

> > Can u give me an example with a single IRQ of a configuration-node for a
> > dts?
> 
> myreallycooldevice@0 {
>         interrupts = <1 2 3>;
>         interrupt-parent = <&mpc5200_pic>;
> };

Ahh - oh weh - so simple! Thank you!

> The interrupts property matches the size of the #interrupt-cells
> property in the interrupt controller node.  For the 5200-intc, each
> interrupt is described by 3 cells; l1, l2 and sense which is a
> reflection of the interrupt controller architecture.  For IRQ0, l1=0,
> l2=0; IRQ1, l1=1, l2=1; IRQ2, l1=1 and l2=2; IRQ3, l1=1, l2=3 Sense is
> described in mpc52xx-device-tree-bindings.txt

OK, my dts is now:

    / {
        /* ... */
        soc5200@f0000000 {
            /* ... */
            intpin@0 {
                interrupt-parent = <500>;
                interrupts = <1 2 2>;
            };
            /* ... */
        };
        /* ... */
    };

And the corresponding code is:

struct intmod_priv {
    /** Interrupt-Number */
    int own_irq;

    /** The of-device-node */
    struct device_node *intmod_dev_node;
};

static int __init mod_init( void )
{
    // ...
    priv.intmod_dev_node = NULL;
    priv.intmod_dev_node = of_find_node_by_name(NULL, "intpin");

    priv.own_irq = irq_of_parse_and_map(priv.intmod_dev_node, 0);
    request_irq(priv.own_irq, intmod_isr, IRQF_DISABLED , "intmod", INTMOD_IRQ_BOARD);
    // ...


Thank you and bye, my next question is following :-)

Silvio Fricke

-- 
-- S. Fricke ----------------------------- MAILTO:silvio.fricke@gmail.com --
   Diplom-Informatiker (FH)
   Linux-Entwicklung
----------------------------------------------------------------------------


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Re: [NEWBIE] Interrupt-problem mpc5200

[Grant Likely]

On 9/19/07, S. Fricke <silvio.fricke@googlemail.com> wrote:
> OK, my dts is now:
>
>     / {
>         /* ... */
>         soc5200@f0000000 {
>             /* ... */
>             intpin@0 {
>                 interrupt-parent = <500>;
>                 interrupts = <1 2 2>;
>             };
>             /* ... */
>         };
>         /* ... */
>     };

Note: your intpin node does not (and probably should not) need to be a
child of the soc node.

Cheers,
g.

-- 
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.
grant.likely@secretlab.ca
(403) 399-0195

Re: [NEWBIE] Interrupt-problem mpc5200

[Matt Sealey]

Grant!

I have a newbie question which I never had properly answered. On the
MPC52xx and specifically regarding the device tree, how are interrupt
numbers assigned?

On Efika (and in the DT docs) it's basically the X Y Z where X is the
type (critical, main, peripheral, sdma), Y is the number of the
interrupt, and Z is it's sense level.

However while X and Z are easy to derive, how do you work out what Y
is meant to be given a device? Is it a bit number in the interrupt
register, or the value of the encoded interrupt register or something
else algorithmically determined?

I am just finding the code in Linux that derives this number fairly
elusive (the irq setup function for the mpc52xx platform is truly
sparse, irq_of_find_and_map isn't much help). Maybe I am just not
looking in the right place but not being an MPC52xx PIC Expert I
wouldn't even know where to start...

-- 
Matt Sealey <matt@genesi-usa.com>
Genesi, Manager, Developer Relations

Grant Likely wrote:
> On 9/11/07, S. Fricke <silvio.fricke@googlemail.com> wrote:
>> Hello,
>>
>>>> [...]
>>>>     intr = mpc52xx_find_and_map("mpc52xx-pic");
>>>>     if(!intr) {
>>>>         panic(__FILE__ ": mpc52xx-pic - MAP failed");
>>>>     }
>>>>
>>>>     set_irq_chip(MPC52xx_IRQ2, &my_irq_chip);
>>> You probably don't want to do this (unless you are cascading IRQs to
>>> custom external hardware).  All you should need is the call to
>>> request_irq() to register your irq handler, and code in your ISR
>>> handler to clear the interrupt condition.
>>>
>>> You do *NOT* want to program the interrupt controller directly.  The
>>> mpc5200 interrupt controller already has a driver.  Don't go twiddling
>>> the registers manually.
>> OK!
>>
>> I have tried it before and i get a "-ENOSYS" returned.
>>
>> My code was/is now:
>> --==>
>> request_irq(MPC52xx_IRQ2, intmod_isr, IRQF_DISABLED , "intmod",
>>             INTMOD_IRQ_BOARD);
>> <==--
>>
>> I have looked up "kernel/irq/manage.c". "-ENOSYS" is returned on function
>> "setup_irq" because the used irq(MPC52xx_IRQ2) is the same as no_irq_chip.
>>
>> THE MPC52xx_IRQ2 is a excerpt from "include/ppc/mpc52xx.h" (per copy
>> paste), but mpc52xx is (now) a powerpc-arch. What is the desired value for
>> IRQ-2 on a mpc5200b?
> 
> The irq number you pass into request_irq is a system-wide irq number;
> it doesn't necessarily map directly onto the MPC52xx irq number.
> Typically, you'd have a node for your device in the device tree which
> has a phandle back to the interrupt node and you would use
> irq_of_parse_and_map() to map it back to a system-wide irq number.
> 
> Otherwise, you need to call of_irq_map_raw with the pointer to the
> 52xx interrupt controller node and the interrupt number in the form
> expected by the device tree.  (But adding a device tree node for your
> device is far easier).
> 
> Cheers,
> g.
> 

Re: [NEWBIE] Interrupt-problem mpc5200

[Grant Likely]

On 9/14/07, Matt Sealey <matt@genesi-usa.com> wrote:
> Grant!
>
> I have a newbie question which I never had properly answered. On the
> MPC52xx and specifically regarding the device tree, how are interrupt
> numbers assigned?
>
> On Efika (and in the DT docs) it's basically the X Y Z where X is the
> type (critical, main, peripheral, sdma), Y is the number of the
> interrupt, and Z is it's sense level.
>
> However while X and Z are easy to derive, how do you work out what Y
> is meant to be given a device? Is it a bit number in the interrupt
> register, or the value of the encoded interrupt register or something
> else algorithmically determined?
>
> I am just finding the code in Linux that derives this number fairly
> elusive (the irq setup function for the mpc52xx platform is truly
> sparse, irq_of_find_and_map isn't much help). Maybe I am just not
> looking in the right place but not being an MPC52xx PIC Expert I
> wouldn't even know where to start...

The l2 irq numbers map directly to the interrupt numbers listed in the
5200b user guide.  For example, on p7-11, the masks are listed for
main interrupts 0 through 16.  and on p7-17,18, the peripherial
interrupts are listed as numbered from 0 to 23 (but notice that it
does *not* line up with bit positions).

However, it is interesting to note that other than in the register
definitions, I don't think there is anywhere in the 5200b user manual
that simple lists the interrupt numbers for each interrupt type.

Cheers,
g.
>
> --
> Matt Sealey <matt@genesi-usa.com>
> Genesi, Manager, Developer Relations
>
> Grant Likely wrote:
> > On 9/11/07, S. Fricke <silvio.fricke@googlemail.com> wrote:
> >> Hello,
> >>
> >>>> [...]
> >>>>     intr = mpc52xx_find_and_map("mpc52xx-pic");
> >>>>     if(!intr) {
> >>>>         panic(__FILE__ ": mpc52xx-pic - MAP failed");
> >>>>     }
> >>>>
> >>>>     set_irq_chip(MPC52xx_IRQ2, &my_irq_chip);
> >>> You probably don't want to do this (unless you are cascading IRQs to
> >>> custom external hardware).  All you should need is the call to
> >>> request_irq() to register your irq handler, and code in your ISR
> >>> handler to clear the interrupt condition.
> >>>
> >>> You do *NOT* want to program the interrupt controller directly.  The
> >>> mpc5200 interrupt controller already has a driver.  Don't go twiddling
> >>> the registers manually.
> >> OK!
> >>
> >> I have tried it before and i get a "-ENOSYS" returned.
> >>
> >> My code was/is now:
> >> --==>
> >> request_irq(MPC52xx_IRQ2, intmod_isr, IRQF_DISABLED , "intmod",
> >>             INTMOD_IRQ_BOARD);
> >> <==--
> >>
> >> I have looked up "kernel/irq/manage.c". "-ENOSYS" is returned on function
> >> "setup_irq" because the used irq(MPC52xx_IRQ2) is the same as no_irq_chip.
> >>
> >> THE MPC52xx_IRQ2 is a excerpt from "include/ppc/mpc52xx.h" (per copy
> >> paste), but mpc52xx is (now) a powerpc-arch. What is the desired value for
> >> IRQ-2 on a mpc5200b?
> >
> > The irq number you pass into request_irq is a system-wide irq number;
> > it doesn't necessarily map directly onto the MPC52xx irq number.
> > Typically, you'd have a node for your device in the device tree which
> > has a phandle back to the interrupt node and you would use
> > irq_of_parse_and_map() to map it back to a system-wide irq number.
> >
> > Otherwise, you need to call of_irq_map_raw with the pointer to the
> > 52xx interrupt controller node and the interrupt number in the form
> > expected by the device tree.  (But adding a device tree node for your
> > device is far easier).
> >
> > Cheers,
> > g.
> >
>


-- 
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.
grant.likely@secretlab.ca
(403) 399-0195

Re: [NEWBIE] Interrupt-problem mpc5200

[Matt Sealey]

Grant Likely wrote:
> On 9/14/07, Matt Sealey <matt@genesi-usa.com> wrote:
>> sparse, irq_of_find_and_map isn't much help). Maybe I am just not
>> looking in the right place but not being an MPC52xx PIC Expert I
>> wouldn't even know where to start...
> 
> The l2 irq numbers map directly to the interrupt numbers listed in the
> 5200b user guide.  For example, on p7-11, the masks are listed for
> main interrupts 0 through 16.  and on p7-17,18, the peripherial
> interrupts are listed as numbered from 0 to 23 (but notice that it
> does *not* line up with bit positions).

Wow I even had to search.. it's on p7-13 here..

Right but it does start from a certain bit and progress linearly
across the rest of the register.

However, what is interrupt 0 and what is interrupt 16? Do you start
from the left or the right (i.e. Motorola big endian or Rest Of
World big endian)??

> However, it is interesting to note that other than in the register
> definitions, I don't think there is anywhere in the 5200b user manual
> that simple lists the interrupt numbers for each interrupt type.

I think the interesting note is that picking out "what does IRQ 4
in the main interrupt group handle" or picking out a device and
saying "this is IRQ 10" is still, even with your explanation, a
matter of luck and handedness.

Personally I would count from the right (Motorola bit 31) and
work my way from LSB to MSB, but Motorola likes it's backwards
representation and so do some other people. So, does bit 31
equal interrupt 0 or interrupt 16? :)

Then there are the status encoded registers, which report which
IRQ is firing. They are just values. But which value corresponds
to which interrupt (left or right reading) here or do they even
have completely different ones?

-- 
Matt Sealey <matt@genesi-usa.com>
Genesi, Manager, Developer Relations

Re: [NEWBIE] Interrupt-problem mpc5200

[Grant Likely]

On 9/14/07, Matt Sealey <matt@genesi-usa.com> wrote:
> Grant Likely wrote:
> > On 9/14/07, Matt Sealey <matt@genesi-usa.com> wrote:
> >> sparse, irq_of_find_and_map isn't much help). Maybe I am just not
> >> looking in the right place but not being an MPC52xx PIC Expert I
> >> wouldn't even know where to start...
> >
> > The l2 irq numbers map directly to the interrupt numbers listed in the
> > 5200b user guide.  For example, on p7-11, the masks are listed for
> > main interrupts 0 through 16.  and on p7-17,18, the peripherial
> > interrupts are listed as numbered from 0 to 23 (but notice that it
> > does *not* line up with bit positions).
>
> Wow I even had to search.. it's on p7-13 here..
>
> Right but it does start from a certain bit and progress linearly
> across the rest of the register.
>
> However, what is interrupt 0 and what is interrupt 16? Do you start
> from the left or the right (i.e. Motorola big endian or Rest Of
> World big endian)??
>
> > However, it is interesting to note that other than in the register
> > definitions, I don't think there is anywhere in the 5200b user manual
> > that simple lists the interrupt numbers for each interrupt type.
>
> I think the interesting note is that picking out "what does IRQ 4
> in the main interrupt group handle" or picking out a device and
> saying "this is IRQ 10" is still, even with your explanation, a
> matter of luck and handedness.
>
> Personally I would count from the right (Motorola bit 31) and
> work my way from LSB to MSB, but Motorola likes it's backwards
> representation and so do some other people. So, does bit 31
> equal interrupt 0 or interrupt 16? :)

No, they are explicitly numbered.  Are you looking at the 5200 or the
5200B user manual?  In my copy, on page 7-17, I see this:  PSa0 in
peripheral interrupt 0 (l2=3D0), PSa23 is peripheral interrupt #23
(l2=3D23)

       Bits        Name
         8       PSa23  BestCom
         9       PSa22  BDLC
        10        PSa0  BestCom
        11        PSa1  PSC1
        12         PSa2    PSC2
        13         PSa3    PSC3
        14         PSa4    PSC6
        15         PSa5    Ethernet
        16         PSa6    USB
        17         PSa7    ATA
        18         PSa8    PCI Contr
        19         PSa9    PCI SC In
        20         PSa10   PCI SC In
        21         PSa11   PSC4
        22         PSa12   PSC5
        23         PSa13   SPI modf
        24         PSa14   SPI spif
        25         PSa15   I2C1
        26         PSa16   I2C2
        27         PSa17   CAN1
        28         PSa18   CAN2
       29:30         =97     Reserved
        31         PSa21   XLB Arbit

>
> Then there are the status encoded registers, which report which
> IRQ is firing. They are just values. But which value corresponds
> to which interrupt (left or right reading) here or do they even
> have completely different ones?
>
> --
> Matt Sealey <matt@genesi-usa.com>
> Genesi, Manager, Developer Relations
>


--=20
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.
grant.likely@secretlab.ca
(403) 399-0195

Re: [NEWBIE] Interrupt-problem mpc5200

[Matt Sealey]

Grant Likely wrote:
> 
> No, they are explicitly numbered.  Are you looking at the 5200 or the
> 5200B user manual?

MPC5200B User's Manual, Rev. 1.3 (MPC5200BUM.pdf)

>  In my copy, on page 7-17, I see this:

Ah! 7-20 here. Do we have different revisions of the manual, perhaps? :)

   PSa0 in
> peripheral interrupt 0 (l2=0), PSa23 is peripheral interrupt #23
> (l2=23)
> 
>        Bits        Name
>          8       PSa23  BestCom

So, the numbering of the interrupts is not derived from anything but
the "Name" field in those tables? 0 1 3 would be Slice Timer 0, 1 0 3
would be Slice Timer 1 (main, interrupt 0, we always use 3 on Efika
for some reason) and 1 9 3 would be TMR0? PCI control and initiator
interrupts would be 2 (8,9,10) 3?

Well, this certainly makes a lot more sense, at least in terms of
deriving the numbers, however it looks like it's a fairly nonsensical
numbering system to be fair.

-- 
Matt Sealey <matt@genesi-usa.com>
Genesi, Manager, Developer Relations