Xilinx ML310 Linux 2.6 PCI bridge

Xilinx ML310 Linux 2.6 PCI bridge

[Jean-Samuel Chenard]

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Hi,

Thanks to the valuable information provided by this discussion group and
particularly by Grant Likely from Secret Lab Technologies, I was able to
setup and run Linux 2.6 on my ML-310 development platform.

On the ML-310, if I want to use the Ethernet port and some other
peripherals, I need to go through the PCI bus via the opb_pci core on the
FPGA.

However, when I enable PCI support in the kernel, I get the following error
messages:

arch/ppc/syslib/ppc4xx_setup.c: In function `ppc4xx_map_io':
arch/ppc/syslib/ppc4xx_setup.c:118: error: `PPC4xx_PCI_IO_VADDR' undeclared
(first use in this function)
arch/ppc/syslib/ppc4xx_setup.c:118: error: (Each undeclared identifier is
reported only once
arch/ppc/syslib/ppc4xx_setup.c:118: error: for each function it appears in.)
arch/ppc/syslib/ppc4xx_setup.c:119: error: `PPC4xx_PCI_IO_PADDR' undeclared
(first use in this function)
arch/ppc/syslib/ppc4xx_setup.c:119: error: `PPC4xx_PCI_IO_SIZE' undeclared
(first use in this function)
arch/ppc/syslib/ppc4xx_setup.c:120: error: `PPC4xx_PCI_CFG_VADDR' undeclared
(first use in this function)
arch/ppc/syslib/ppc4xx_setup.c:121: error: `PPC4xx_PCI_CFG_PADDR' undeclared
(first use in this function)
arch/ppc/syslib/ppc4xx_setup.c:121: error: `PPC4xx_PCI_CFG_SIZE' undeclared
(first use in this function)
arch/ppc/syslib/ppc4xx_setup.c:122: error: `PPC4xx_PCI_LCFG_VADDR'
undeclared (first use in this function)
arch/ppc/syslib/ppc4xx_setup.c:123: error: `PPC4xx_PCI_LCFG_PADDR'
undeclared (first use in this function)
arch/ppc/syslib/ppc4xx_setup.c:123: error: `PPC4xx_PCI_LCFG_SIZE' undeclared
(first use in this function)
make[1]: *** [arch/ppc/syslib/ppc4xx_setup.o] Error 1

My Xilinx Platform Studio has the proper PCI bridge component, but the
exported constants in xparameters_ml300.h are not helping me figure out the
mapping that I should give to those PPC4xx values (the parameters contain a
lot of XPAR_PCI32_BRIDGE_* constants).  I'm guessing that the address
mappings must be set from some of those for the PCI range to appear in the
PowerPC address space.  Please correct me if I'm misunderstanding something
here...

I only saw one mention of this error related to the ML-310 in a discussion
dating in 2005 and the answer was that the 2.6 kernel was not supporting the
Virtex-II Pro too well at the time.  Has this changed and does anyone have
had success using the PCI bridge in Linux 2.6 on an ML-310 development
platform ?

Thanks,

Jean-Samuel
-- 
Integrated Microsystems Laboratory
McGill University, Montréal, QC, CANADA
Web Page: http://chaos.ece.mcgill.ca

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Re: Xilinx ML310 Linux 2.6 PCI bridge

[Grant Likely]

On 12/8/07, Jean-Samuel Chenard <jsamch@macs.ece.mcgill.ca> wrote:
> Hi,
>
> Thanks to the valuable information provided by this discussion group and
> particularly by Grant Likely from Secret Lab Technologies, I was able to
> setup and run Linux 2.6 on my ML-310 development platform.

Congratulations.  If you had to make any changes to get it to work
then please send me your patches.

>
>  On the ML-310, if I want to use the Ethernet port and some other
> peripherals, I need to go through the PCI bus via the opb_pci core on the
> FPGA.
>
> However, when I enable PCI support in the kernel, I get the following error
> messages:

You'll have to go back into the mailing list archives to find a patch
for adding PCI support for a Virtex platform.  I don't have any of
that in my tree.  It probably only exists for the 2.4 kernel.  You'll
need to port forward to use it on 2.6 (I'm more than willing to help
you with this)

However, word of warning.  The Xilinx PCI bridge is badly broken.
Xilinx is not supporting the PCI core and it is missing the ability to
do certain types of transfers.  Last I heard, Xilinx has no plans to
fix their PCI core either.

Best of luck,
g.

-- 
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.
grant.likely@secretlab.ca
(403) 399-0195

Re: Xilinx ML310 Linux 2.6 PCI bridge

[Jean-Samuel Chenard]

On Dec 9, 2007 1:18 AM, Grant Likely <grant.likely@secretlab.ca> wrote:
> On 12/8/07, Jean-Samuel Chenard <jsamch@macs.ece.mcgill.ca> wrote:
> > Thanks to the valuable information provided by this discussion group an=
d
> > particularly by Grant Likely from Secret Lab Technologies, I was able t=
o
> > setup and run Linux 2.6 on my ML-310 development platform.
>
> Congratulations.  If you had to make any changes to get it to work
> then please send me your patches.

Thank you for the quick reply.

I will directly update Secret Lab's Wiki pages.  Those pages are the
ones that got me going really quickly, so I will add a few of my
observations directly on your pages so everyone can benefit.

I ended up using Secret Lab's GIT tree as my source archive, so I'll
let you know if I need to fix some code.

> You'll have to go back into the mailing list archives to find a patch
> for adding PCI support for a Virtex platform.  I don't have any of
> that in my tree.  It probably only exists for the 2.4 kernel.  You'll
> need to port forward to use it on 2.6 (I'm more than willing to help
> you with this)

Hmmm... I'm not really ready to invest that much time into the PCI for ML-3=
10.

My real target is the control FPGA on a BEE2 box
(http://bee2.eecs.berkeley.edu) and on that particular setup, the
control FPGA is directly connected to an LXT971A Ethernet PHY, so I'll
use the ethernet MAC from Xilinx.

I use the ML-310 as a stepping stone for quickly prototyping some of
my FPGA changes since the VirtexII-Pro in the ML-310 is much smaller
and doesn't eat up all my workstation resources when re-compiling the
FPGA.

> However, word of warning.  The Xilinx PCI bridge is badly broken.
> Xilinx is not supporting the PCI core and it is missing the ability to
> do certain types of transfers.  Last I heard, Xilinx has no plans to
> fix their PCI core either.

Ok, its nice to know the status of that module.  Too bad Xilinx is
dropping the support for it.

In that case, it would probably be more beneficial for all to adapt an
"open core" project such as this PCI bridge:
http://www.opencores.org/projects.cgi/web/pci/home

Along with the help of an OPB to Wishbone wrapper like that one:
http://www.opencores.org/projects.cgi/web/opb_wb_wrapper/overview

With some work (and ideally some PCI expertise) one could get an open
implementation of a PCI bridge that can integrate in the Xilinx EDK
flow and could be repaired or adapted as time goes...  I am a complete
newbie to PCI, so I'll leave that to some willing "hacker".

I'll continue on my quest to run Linux 2.6 on the BEE2 control FPGA.
There is no PCI bus involved in that architecture.  Just raw buses and
a sea of FPGA logic.

Regards,

Jean-Samuel
--=20
Integrated Microsystems Laboratory
McGill University, Montr=E9al, QC, CANADA
Web Page: http://chaos.ece.mcgill.ca

Re: Xilinx ML310 Linux 2.6 PCI bridge

[Grant Likely]

On 12/9/07, Jean-Samuel Chenard <jsamch@macs.ece.mcgill.ca> wrote:
> On Dec 9, 2007 1:18 AM, Grant Likely <grant.likely@secretlab.ca> wrote:
> > On 12/8/07, Jean-Samuel Chenard <jsamch@macs.ece.mcgill.ca> wrote:
> > > Thanks to the valuable information provided by this discussion group and
> > > particularly by Grant Likely from Secret Lab Technologies, I was able to
> > > setup and run Linux 2.6 on my ML-310 development platform.
> >
> > Congratulations.  If you had to make any changes to get it to work
> > then please send me your patches.
>
> Thank you for the quick reply.

No problem.

>
> I will directly update Secret Lab's Wiki pages.  Those pages are the
> ones that got me going really quickly, so I will add a few of my
> observations directly on your pages so everyone can benefit.

Much appreciated; thank you!

> My real target is the control FPGA on a BEE2 box
> (http://bee2.eecs.berkeley.edu) and on that particular setup, the
> control FPGA is directly connected to an LXT971A Ethernet PHY, so I'll
> use the ethernet MAC from Xilinx.

Cool platform.  Yes, you should have much better luck with the EMAC
core.  The driver needs some work to be acceptable for mainline, but
it should be functional.

Cheers,
g.

-- 
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.
grant.likely@secretlab.ca
(403) 399-0195

RE: Xilinx ML310 Linux 2.6 PCI bridge

[Stephen Neuendorffer]

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I would strongly recommend not spending a huge amount of time on the ml310.  The University program board is dirt cheap for universities, very well supported under Linux, using either secretlab.ca or git.xilinx.com and you won't spend your time getting PCI to place and route correctly, followed by figuring out how to get Linux to talk to it nicely.

If your lab can afford a bee2, then you should be able to afford one (or better yet, several) xupv2p's to go with it.

http://www.xilinx.com/univ/xupv2p.html

Steve

-----Original Message-----
From: linuxppc-embedded-bounces+stephen=neuendorffer.name@ozlabs.org on behalf of Grant Likely
Sent: Sun 12/9/2007 12:23 PM
To: Jean-Samuel Chenard
Cc: linuxppc-embedded@ozlabs.org
Subject: Re: Xilinx ML310 Linux 2.6 PCI bridge
 
On 12/9/07, Jean-Samuel Chenard <jsamch@macs.ece.mcgill.ca> wrote:
> On Dec 9, 2007 1:18 AM, Grant Likely <grant.likely@secretlab.ca> wrote:
> > On 12/8/07, Jean-Samuel Chenard <jsamch@macs.ece.mcgill.ca> wrote:
> > > Thanks to the valuable information provided by this discussion group and
> > > particularly by Grant Likely from Secret Lab Technologies, I was able to
> > > setup and run Linux 2.6 on my ML-310 development platform.
> >
> > Congratulations.  If you had to make any changes to get it to work
> > then please send me your patches.
>
> Thank you for the quick reply.

No problem.

>
> I will directly update Secret Lab's Wiki pages.  Those pages are the
> ones that got me going really quickly, so I will add a few of my
> observations directly on your pages so everyone can benefit.

Much appreciated; thank you!

> My real target is the control FPGA on a BEE2 box
> (http://bee2.eecs.berkeley.edu) and on that particular setup, the
> control FPGA is directly connected to an LXT971A Ethernet PHY, so I'll
> use the ethernet MAC from Xilinx.

Cool platform.  Yes, you should have much better luck with the EMAC
core.  The driver needs some work to be acceptable for mainline, but
it should be functional.

Cheers,
g.

-- 
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.
grant.likely@secretlab.ca
(403) 399-0195
_______________________________________________
Linuxppc-embedded mailing list
Linuxppc-embedded@ozlabs.org
https://ozlabs.org/mailman/listinfo/linuxppc-embedded



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Re: Xilinx ML310 Linux 2.6 PCI bridge

[Jean-Samuel Chenard]

On Dec 10, 2007 12:46 AM, Stephen Neuendorffer
<stephen.neuendorffer@xilinx.com> wrote:
> I would strongly recommend not spending a huge amount of time on the ml31=
0.
> The University program board is dirt cheap for universities, very well
> supported under Linux, using either secretlab.ca or git.xilinx.com and yo=
u
> won't spend your time getting PCI to place and route correctly, followed =
by
> figuring out how to get Linux to talk to it nicely.

Hi Stephen,

Thanks for the insight.  I was aware of the XUP V2P board and I think
this is a nice initiative to let students use some great technology.

>  If your lab can afford a bee2, then you should be able to afford one (or
> better yet, several) xupv2p's to go with it.

That's where things get complicated...  In our lab, we get expensive
hardware such as the BEE2 via CMC Microsystems (a Canadian granting
agency).  However, getting funds locally to buy other equipment is a
relatively long and administratively complex process...

One of my colleague did not use his ML-310 board so I got a hold of it
(in a day, with little overhead).  So far, the ML-310 has helped me
bring up Linux 2.6 and experiment most of what I need to use on the
BEE2.  I am only missing the networking.  This would make things much
nicer to work via a NFS-exported root file system.  However, I'm OK
swapping the CompactFlash card...

I find it strange that Xilinx would not invest in supporting Linux 2.6
for an important feature such as a PCI bridge (not specifically for
the ML-310, but in general) when this can bring many interesting
benefits to an embedded platform.  Is this something that is "in
progress" at Xilinx?  You seem to imply that most of the difficulty in
getting the PCI core working is in meeting the timing requirements
(not with the SW drivers), so I might be missing driver files when I
generate the BSP code for Linux 2.6.

Regards,

Jean-Samuel
--=20
Integrated Microsystems Laboratory
McGill University, Montr=E9al, QC, CANADA
Web Page: http://chaos.ece.mcgill.ca

RE: Xilinx ML310 Linux 2.6 PCI bridge

[Stephen Neuendorffer]

=20
> That's where things get complicated...  In our lab, we get expensive
> hardware such as the BEE2 via CMC Microsystems (a Canadian granting
> agency).  However, getting funds locally to buy other equipment is a
> relatively long and administratively complex process...

Yeah, I understand how such things go... :)

> I find it strange that Xilinx would not invest in supporting Linux 2.6
> for an important feature such as a PCI bridge (not specifically for
> the ML-310, but in general) when this can bring many interesting
> benefits to an embedded platform.  Is this something that is "in
> progress" at Xilinx?  You seem to imply that most of the difficulty in
> getting the PCI core working is in meeting the timing requirements
> (not with the SW drivers), so I might be missing driver files when I
> generate the BSP code for Linux 2.6.

The PCI core needs a separate driver for generating the right
constraints.  In EDK 9.2 there is some linux 2.6 support for this, but
the code won't work with any of the new kernels.  I've pulled the
changes into my internal git tree, but for reasons that I haven't been
able to ascertain, there are hardcoded xparameter-based interrupt
defines in the super I/O bridge controller.

In any event, I'll send you the patches directly and you can try getting
it to work, although you'll likely need to carefully write the
xparameters by hand.  If you can get away without networking, I'd do
that, though.  :)

Steve=20

RE: Xilinx ML310 Linux 2.6 PCI bridge

[Rick Moleres]

Grant,

Can you give me more details on why you say the opb_pci bridge is badly
broken?  I know there have been issues with it in the past, but I'm not
aware of major outages (perhaps I'm just not in the loop).

> However, word of warning.  The Xilinx PCI bridge is badly broken.
> Xilinx is not supporting the PCI core and it is missing the ability to
> do certain types of transfers.  Last I heard, Xilinx has no plans to
> fix their PCI core either.

The opb_pci and plb_pci (plbv34) bridges have transitioned to the
plbv36_pci bridge in EDK 9.2 and later.  This bridge is fully supported
and has been tested under MontaVista's 2.6.10 kernel.  I believe only
critical issues will be fixed in the opb/plbv34.

Thanks,
Rick

Re: Xilinx ML310 Linux 2.6 PCI bridge

[Grant Likely]

On 12/10/07, Rick Moleres <Rick.Moleres@xilinx.com> wrote:
>
> Grant,
>
> Can you give me more details on why you say the opb_pci bridge is badly
> broken?  I know there have been issues with it in the past, but I'm not
> aware of major outages (perhaps I'm just not in the loop).

Actually, it's more likely that I'm not in the loop (see below)

I know of 2 projects that had difficulty with the opb_pci core; The
major issue was that it didn't support all of the PCI transfer modes
(IIRC it was the multiple read transfer command).  Last I heard from
the FAE was that Xilinx was not offering support for the core.

> The opb_pci and plb_pci (plbv34) bridges have transitioned to the
> plbv36_pci bridge in EDK 9.2 and later.  This bridge is fully supported
> and has been tested under MontaVista's 2.6.10 kernel.  I believe only
> critical issues will be fixed in the opb/plbv34.

This I was not aware of.  I stand corrected.

Thanks,
g.

-- 
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.
grant.likely@secretlab.ca
(403) 399-0195

Re: Xilinx ML310 Linux 2.6 PCI bridge

[Grant Likely]

On 12/9/07, Jean-Samuel Chenard <jsamch@macs.ece.mcgill.ca> wrote:
> Thank you for the quick reply.
>
> I will directly update Secret Lab's Wiki pages.  Those pages are the
> ones that got me going really quickly, so I will add a few of my
> observations directly on your pages so everyone can benefit.

I saw your updates to the wiki; thank you very much.

Cheers,
g.

-- 
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.
grant.likely@secretlab.ca
(403) 399-0195