From: "Grant Likely" <grant.likely@secretlab.ca>
To: "Rick Moleres" <Rick.Moleres@xilinx.com>
Cc: Jean-Samuel Chenard <jsamch@macs.ece.mcgill.ca>,
linuxppc-embedded@ozlabs.org
Subject: Re: Xilinx ML310 Linux 2.6 PCI bridge
Date: Mon, 10 Dec 2007 17:20:43 -0700 [thread overview]
Message-ID: <fa686aa40712101620u14924d73gff6291dfb9e0a17e@mail.gmail.com> (raw)
In-Reply-To: <20071210235609.91265F18074@mail188-sin.bigfish.com>
On 12/10/07, Rick Moleres <Rick.Moleres@xilinx.com> wrote:
>
> Grant,
>
> Can you give me more details on why you say the opb_pci bridge is badly
> broken? I know there have been issues with it in the past, but I'm not
> aware of major outages (perhaps I'm just not in the loop).
Actually, it's more likely that I'm not in the loop (see below)
I know of 2 projects that had difficulty with the opb_pci core; The
major issue was that it didn't support all of the PCI transfer modes
(IIRC it was the multiple read transfer command). Last I heard from
the FAE was that Xilinx was not offering support for the core.
> The opb_pci and plb_pci (plbv34) bridges have transitioned to the
> plbv36_pci bridge in EDK 9.2 and later. This bridge is fully supported
> and has been tested under MontaVista's 2.6.10 kernel. I believe only
> critical issues will be fixed in the opb/plbv34.
This I was not aware of. I stand corrected.
Thanks,
g.
--
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.
grant.likely@secretlab.ca
(403) 399-0195
prev parent reply other threads:[~2007-12-11 0:20 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2007-12-09 5:51 Xilinx ML310 Linux 2.6 PCI bridge Jean-Samuel Chenard
2007-12-09 6:18 ` Grant Likely
2007-12-09 17:32 ` Jean-Samuel Chenard
2007-12-09 20:23 ` Grant Likely
2007-12-10 5:46 ` Stephen Neuendorffer
2007-12-10 16:33 ` Jean-Samuel Chenard
2007-12-10 18:47 ` Stephen Neuendorffer
2007-12-13 16:46 ` Grant Likely
2007-12-10 23:57 ` Rick Moleres
2007-12-11 0:20 ` Grant Likely [this message]
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