Re: [PATCH 2/3] [POWERPC] Xilinx: of_serial support for Xilinx uart 16550.

["Grant Likely" <grant.likely@secretlab.ca>]

On Mon, Mar 24, 2008 at 10:15 AM, Sergei Shtylyov
<sshtylyov@ru.mvista.com> wrote:
> Grant Likely wrote:
>  >>    Probably I misunderstood you: does it give the same result as offset 11?
>
>  > er; typo; oops.  A 32 bit read add offset 0 is the same as a byte read
>  > at offset *3*.
>
>     Oh, well... unfortunately, we can't use UPIO_MEM32 "register model" in
>  8250.c anyway since that makes use of readl()/writel() -- which treat the bus
>  as bigendian on PPC... anyway, we would need at least a "reg-size" property,
>  if not new "compatible"...

:-) ... and the *driver* itself isn't any sort of issue; it's just
figuring out the best way to describe the hardware
accurately/appropriately so the binding can decide how to configure
the driver.

>  >>    Have you considered using the existing "big-endian" property?
>
>  > No I haven't, but that would work too.  I'm happy with that if it
>  > works for you.  If the property was defined, then the byte offset to
>  > the first reg would be adjusted by 1^(reg-shift) - 1
>
>     You don't mean "xor" by ^, do you? :-O
>     In fact, it should be <<...

heh; pseudocoding in the wrong language.  You, of course, are right.

Cheers,
g.

-- 
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.