[PATCHv2] powerpc: Describe memory-mapped RAM&ROM chips OF bindings

[PATCHv2] powerpc: Describe memory-mapped RAM&ROM chips OF bindings

[Laurent Pinchart]

Signed-off-by: Laurent Pinchart <laurentp@cse-semaphore.com>
=2D--
 Documentation/powerpc/booting-without-of.txt |   13 ++++++++++++-
 1 files changed, 12 insertions(+), 1 deletions(-)

diff --git a/Documentation/powerpc/booting-without-of.txt b/Documentation/p=
owerpc/booting-without-of.txt
index 7b4e8a7..3e1963b 100644
=2D-- a/Documentation/powerpc/booting-without-of.txt
+++ b/Documentation/powerpc/booting-without-of.txt
@@ -57,7 +57,8 @@ Table of Contents
       n) 4xx/Axon EMAC ethernet nodes
       o) Xilinx IP cores
       p) Freescale Synchronous Serial Interface
=2D	  q) USB EHCI controllers
+      q) USB EHCI controllers
+      r) Memory-mapped RAM & ROM
=20
   VII - Specifying interrupt information for devices
     1) interrupts property
@@ -2816,6 +2817,16 @@ platforms are moved over to use the flattened-device=
=2Dtree model.
 		   big-endian;
 	   };
=20
+   r) Memory-mapped RAM & ROM
+
+    Dedicated RAM and ROM chips are often used as storage for temporary or
+    permanent data in embedded devices. Possible usage include non-volatile
+    storage in battery-backed SRAM, semi-permanent storage in dedicated SR=
AM
+    to preserve data accross reboots and firmware storage in dedicated ROM.
+
+     - name : should be either "ram" or "rom"
+     - reg : Address range of the RAM/ROM chip
+
=20
    More devices will be defined as this spec matures.
=20
=2D-=20
1.5.0


=2D-=20
Laurent Pinchart
CSE Semaphore Belgium

Chauss=E9e de Bruxelles, 732A
B-1410 Waterloo
Belgium

T +32 (2) 387 42 59
=46 +32 (2) 387 42 75

Re: [PATCHv2] powerpc: Describe memory-mapped RAM&ROM chips OF bindings

[Sergei Shtylyov]

Hello.

Laurent Pinchart wrote:

> Signed-off-by: Laurent Pinchart <laurentp@cse-semaphore.com>
> ---
>  Documentation/powerpc/booting-without-of.txt |   13 ++++++++++++-
>  1 files changed, 12 insertions(+), 1 deletions(-)
> 
> diff --git a/Documentation/powerpc/booting-without-of.txt b/Documentation/powerpc/booting-without-of.txt
> index 7b4e8a7..3e1963b 100644
> --- a/Documentation/powerpc/booting-without-of.txt
> +++ b/Documentation/powerpc/booting-without-of.txt
> @@ -57,7 +57,8 @@ Table of Contents
>        n) 4xx/Axon EMAC ethernet nodes
>        o) Xilinx IP cores
>        p) Freescale Synchronous Serial Interface
> -	  q) USB EHCI controllers
> +      q) USB EHCI controllers
> +      r) Memory-mapped RAM & ROM

    Memory-mapped RA/RO Memory again? Should better drop this. :-)

WBR, Sergei

Re: [PATCHv2] powerpc: Describe memory-mapped RAM&ROM chips OF bindings

[Laurent Pinchart]

On Monday 31 March 2008 19:06, Sergei Shtylyov wrote:
> Hello.
>=20
> Laurent Pinchart wrote:
>=20
> > Signed-off-by: Laurent Pinchart <laurentp@cse-semaphore.com>
> > ---
> >  Documentation/powerpc/booting-without-of.txt |   13 ++++++++++++-
> >  1 files changed, 12 insertions(+), 1 deletions(-)
> >=20
> > diff --git a/Documentation/powerpc/booting-without-of.txt=20
b/Documentation/powerpc/booting-without-of.txt
> > index 7b4e8a7..3e1963b 100644
> > --- a/Documentation/powerpc/booting-without-of.txt
> > +++ b/Documentation/powerpc/booting-without-of.txt
> > @@ -57,7 +57,8 @@ Table of Contents
> >        n) 4xx/Axon EMAC ethernet nodes
> >        o) Xilinx IP cores
> >        p) Freescale Synchronous Serial Interface
> > -	  q) USB EHCI controllers
> > +      q) USB EHCI controllers
> > +      r) Memory-mapped RAM & ROM
>=20
>     Memory-mapped RA/RO Memory again? Should better drop this. :-)

You're quite picky, aren't you ? :-)

I suppose "Memory-mapped RA & RO" won't be accepted, so what about "Auxilia=
ry=20
RAM & ROM" ?

=2D-=20
Laurent Pinchart
CSE Semaphore Belgium

Chauss=E9e de Bruxelles, 732A
B-1410 Waterloo
Belgium

T +32 (2) 387 42 59
=46 +32 (2) 387 42 75

Re: [PATCHv2] powerpc: Describe memory-mapped RAM&ROM chips OF bindings

[Trent Piepho]

On Tue, 1 Apr 2008, Laurent Pinchart wrote:
> On Monday 31 March 2008 19:06, Sergei Shtylyov wrote:
>>>        p) Freescale Synchronous Serial Interface
>>> -	  q) USB EHCI controllers
>>> +      q) USB EHCI controllers
>>> +      r) Memory-mapped RAM & ROM
>>
>>     Memory-mapped RA/RO Memory again? Should better drop this. :-)
>
> You're quite picky, aren't you ? :-)
>
> I suppose "Memory-mapped RA & RO" won't be accepted, so what about "Auxiliary
> RAM & ROM" ?

Direct-mapped?

Re: [PATCHv2] powerpc: Describe memory-mapped RAM&ROM chips OF bindings

[Laurent Pinchart]

On Tuesday 01 April 2008 11:18, Trent Piepho wrote:
> On Tue, 1 Apr 2008, Laurent Pinchart wrote:
> > On Monday 31 March 2008 19:06, Sergei Shtylyov wrote:
> >>>        p) Freescale Synchronous Serial Interface
> >>> -	  q) USB EHCI controllers
> >>> +      q) USB EHCI controllers
> >>> +      r) Memory-mapped RAM & ROM
> >>
> >>     Memory-mapped RA/RO Memory again? Should better drop this. :-)
> >
> > You're quite picky, aren't you ? :-)
> >
> > I suppose "Memory-mapped RA & RO" won't be accepted, so what about "Aux=
iliary
> > RAM & ROM" ?
>=20
> Direct-mapped?

=46ine with me. Sergei ?

=2D-=20
Laurent Pinchart
CSE Semaphore Belgium

Chauss=E9e de Bruxelles, 732A
B-1410 Waterloo
Belgium

T +32 (2) 387 42 59
=46 +32 (2) 387 42 75

Re: [PATCHv2] powerpc: Describe memory-mapped RAM&ROM chips OF bindings

[Sergei Shtylyov]

Laurent Pinchart wrote:

>>>On Monday 31 March 2008 19:06, Sergei Shtylyov wrote:

>>>>>       p) Freescale Synchronous Serial Interface
>>>>>-	  q) USB EHCI controllers
>>>>>+      q) USB EHCI controllers
>>>>>+      r) Memory-mapped RAM & ROM

>>>>    Memory-mapped RA/RO Memory again? Should better drop this. :-)

>>>You're quite picky, aren't you ? :-)

>>>I suppose "Memory-mapped RA & RO" won't be accepted, so what about "Auxiliary
>>>RAM & ROM" ?

>>Direct-mapped?

> Fine with me. Sergei ?

    I agree. The only thing that somewhat worries me it that it will have no 
"compatible" prop...

WBR, Sergei

Re: [PATCHv2] powerpc: Describe memory-mapped RAM&ROM chips OF bindings

[Grant Likely]

On Mon, Mar 31, 2008 at 10:39 AM, Laurent Pinchart
<laurentp@cse-semaphore.com> wrote:
>
>  Signed-off-by: Laurent Pinchart <laurentp@cse-semaphore.com>
>  ---
>   Documentation/powerpc/booting-without-of.txt |   13 ++++++++++++-
>   1 files changed, 12 insertions(+), 1 deletions(-)
>
>  diff --git a/Documentation/powerpc/booting-without-of.txt b/Documentation/powerpc/booting-without-of.txt
>  index 7b4e8a7..3e1963b 100644
>  --- a/Documentation/powerpc/booting-without-of.txt
>  +++ b/Documentation/powerpc/booting-without-of.txt
>  @@ -57,7 +57,8 @@ Table of Contents
>        n) 4xx/Axon EMAC ethernet nodes
>        o) Xilinx IP cores
>        p) Freescale Synchronous Serial Interface
>  -         q) USB EHCI controllers
>  +      q) USB EHCI controllers
>  +      r) Memory-mapped RAM & ROM
>
>    VII - Specifying interrupt information for devices
>      1) interrupts property
>  @@ -2816,6 +2817,16 @@ platforms are moved over to use the flattened-device-tree model.
>                    big-endian;
>            };
>
>  +   r) Memory-mapped RAM & ROM
>  +
>  +    Dedicated RAM and ROM chips are often used as storage for temporary or
>  +    permanent data in embedded devices. Possible usage include non-volatile
>  +    storage in battery-backed SRAM, semi-permanent storage in dedicated SRAM
>  +    to preserve data accross reboots and firmware storage in dedicated ROM.
>  +
>  +     - name : should be either "ram" or "rom"
>  +     - reg : Address range of the RAM/ROM chip
>  +

No compatible prop?  How does the OS know what the node is to be used for?

Cheers,
g.

-- 
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.

Re: [PATCHv2] powerpc: Describe memory-mapped RAM&ROM chips OF bindings

[Laurent Pinchart]

On Tuesday 01 April 2008 15:16, Grant Likely wrote:
> On Mon, Mar 31, 2008 at 10:39 AM, Laurent Pinchart
> <laurentp@cse-semaphore.com> wrote:
> >
> >  Signed-off-by: Laurent Pinchart <laurentp@cse-semaphore.com>
> >  ---
> >   Documentation/powerpc/booting-without-of.txt |   13 ++++++++++++-
> >   1 files changed, 12 insertions(+), 1 deletions(-)
> >
> >  diff --git a/Documentation/powerpc/booting-without-of.txt=20
> >  b/Documentation/powerpc/booting-without-of.txt=20
> >  index 7b4e8a7..3e1963b 100644
> >  --- a/Documentation/powerpc/booting-without-of.txt
> >  +++ b/Documentation/powerpc/booting-without-of.txt
> >  @@ -57,7 +57,8 @@ Table of Contents
> >        n) 4xx/Axon EMAC ethernet nodes
> >        o) Xilinx IP cores
> >        p) Freescale Synchronous Serial Interface
> >  -         q) USB EHCI controllers
> >  +      q) USB EHCI controllers
> >  +      r) Memory-mapped RAM & ROM
> >
> >    VII - Specifying interrupt information for devices
> >      1) interrupts property
> >  @@ -2816,6 +2817,16 @@ platforms are moved over to use the
> >  flattened-device-tree model.=20
> >                    big-endian;
> >            };
> >
> >  +   r) Memory-mapped RAM & ROM
> >  +
> >  +    Dedicated RAM and ROM chips are often used as storage for tempora=
ry
> >  or=20
> >  +    permanent data in embedded devices. Possible usage include
> >  non-volatile=20
> >  +    storage in battery-backed SRAM, semi-permanent storage in dedicat=
ed
> >  SRAM=20
> >  +    to preserve data accross reboots and firmware storage in dedicated
> >  ROM.=20
> >  +
> >  +     - name : should be either "ram" or "rom"
> >  +     - reg : Address range of the RAM/ROM chip
> >  +
>=20
> No compatible prop?  How does the OS know what the node is to be used for?

If I understood Sergei's arguments properly, the device tree should describ=
e=20
device properties and not their intended usage. With generic devices such a=
s=20
RAM chips, platform code is responsible for binding the device to the=20
appropriate driver (mtd-ram for instance).

Cheers,

=2D-=20
Laurent Pinchart
CSE Semaphore Belgium

Chauss=E9e de Bruxelles, 732A
B-1410 Waterloo
Belgium

T +32 (2) 387 42 59
=46 +32 (2) 387 42 75