Re: [PATCH 2/2] [POWERPC] Xilinx: Virtex: Enable dcr for MMIO and NATIVE

From: "Grant Likely" <grant.likely@secretlab.ca>
To: "Stephen Neuendorffer" <stephen.neuendorffer@xilinx.com>
Cc: linuxppc-dev@ozlabs.org
Subject: Re: [PATCH 2/2] [POWERPC] Xilinx: Virtex: Enable dcr for MMIO and NATIVE
Date: Fri, 18 Apr 2008 20:31:57 -0600	[thread overview]
Message-ID: <fa686aa40804181931p2b18d728q794a0c5c19d1e3b7@mail.gmail.com> (raw)
In-Reply-To: <20080418215513.C8D1A44007F@mail114-dub.bigfish.com>

On Fri, Apr 18, 2008 at 3:55 PM, Stephen Neuendorffer
<stephen.neuendorffer@xilinx.com> wrote:
> FPGA designs may have need of both MMIO-based and NATIVE-based dcr
>  interfaces.
>
>  Signed-off-by: Stephen Neuendorffer <stephen.neuendorffer@xilinx.com>
>  ---
>   arch/powerpc/platforms/40x/Kconfig |    2 ++
>   1 files changed, 2 insertions(+), 0 deletions(-)
>
>  diff --git a/arch/powerpc/platforms/40x/Kconfig b/arch/powerpc/platforms/40x/Kconfig
>  index a9260e2..b8e06df 100644
>  --- a/arch/powerpc/platforms/40x/Kconfig
>  +++ b/arch/powerpc/platforms/40x/Kconfig
>  @@ -123,6 +123,8 @@ config 405GPR
>
>   config XILINX_VIRTEX
>         bool
>  +       select PPC_DCR_MMIO
>  +       select PPC_DCR_NATIVE

Yeah; we'll probably want to be more sophisticated about this in the
future; but for now...

Acked-by: Grant Likely <grant.likely@secretlab.ca>

(Paulus; but this does depend on patch 1 of this series)

>
>   config XILINX_VIRTEX_II_PRO
>         bool
>  --
>  1.5.3.4-dirty
>
>
>
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-- 
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.