OF PCI howto?

OF PCI howto?

[Joakim Tjernlund]

I have just started to add PCI support to our custom MPC832x board
and I have a hard time figuring out how to describe this in the
dts. Looking at mpc832x_mds.dts I see:

        pci0: pci@e0008500 {
                cell-index = <1>;
                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                interrupt-map = <
                                /* IDSEL 0x11 AD17 */
                                 0x8800 0x0 0x0 0x1 &ipic 20 0x8
                                 0x8800 0x0 0x0 0x2 &ipic 21 0x8
                                 0x8800 0x0 0x0 0x3 &ipic 22 0x8
                                 0x8800 0x0 0x0 0x4 &ipic 23 0x8

                                /* IDSEL 0x12 AD18 */
                                 0x9000 0x0 0x0 0x1 &ipic 22 0x8
                                 0x9000 0x0 0x0 0x2 &ipic 23 0x8
                                 0x9000 0x0 0x0 0x3 &ipic 20 0x8
                                 0x9000 0x0 0x0 0x4 &ipic 21 0x8

                                /* IDSEL 0x13 AD19 */
                                 0x9800 0x0 0x0 0x1 &ipic 23 0x8
                                 0x9800 0x0 0x0 0x2 &ipic 20 0x8
                                 0x9800 0x0 0x0 0x3 &ipic 21 0x8
                                 0x9800 0x0 0x0 0x4 &ipic 22 0x8

                                /* IDSEL 0x15 AD21*/
                                 0xa800 0x0 0x0 0x1 &ipic 20 0x8
                                 0xa800 0x0 0x0 0x2 &ipic 21 0x8
                                 0xa800 0x0 0x0 0x3 &ipic 22 0x8
                                 0xa800 0x0 0x0 0x4 &ipic 23 0x8

                                /* IDSEL 0x16 AD22*/
                                 0xb000 0x0 0x0 0x1 &ipic 23 0x8
                                 0xb000 0x0 0x0 0x2 &ipic 20 0x8
                                 0xb000 0x0 0x0 0x3 &ipic 21 0x8
                                 0xb000 0x0 0x0 0x4 &ipic 22 0x8

                                /* IDSEL 0x17 AD23*/
                                 0xb800 0x0 0x0 0x1 &ipic 22 0x8
                                 0xb800 0x0 0x0 0x2 &ipic 23 0x8
                                 0xb800 0x0 0x0 0x3 &ipic 20 0x8
                                 0xb800 0x0 0x0 0x4 &ipic 21 0x8

                                /* IDSEL 0x18 AD24*/
                                 0xc000 0x0 0x0 0x1 &ipic 21 0x8
                                 0xc000 0x0 0x0 0x2 &ipic 22 0x8
                                 0xc000 0x0 0x0 0x3 &ipic 23 0x8
                                 0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
                interrupt-parent = <&ipic>;
                interrupts = <66 0x8>;
                bus-range = <0x0 0x0>;
                ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 
0x10000000
                          0x42000000 0x0 0x80000000 0x80000000 0x0 
0x10000000
                          0x01000000 0x0 0x00000000 0xd0000000 0x0 
0x00100000>;
                clock-frequency = <0>;
                #interrupt-cells = <1>;
                #size-cells = <2>;
                #address-cells = <3>;
                reg = <0xe0008500 0x100         /* internal registers */
                       0xe0008300 0x8>;         /* config space access 
registers */
                compatible = "fsl,mpc8349-pci";
                device_type = "pci";
        };

But I can't figure out what all this mean.
The board will have one PCI device connected directly to the CPU. Is the 
above
dts fragment correct for my setup? If not, is there a better example I can 
look at?

   Jocke

Re: OF PCI howto?

[Wolfram Sang]

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On Wed, Apr 15, 2009 at 02:54:57PM +0200, Joakim Tjernlund wrote:

> dts fragment correct for my setup? If not, is there a better example I can 
> look at?

Maybe this message/thread can help you:

http://ozlabs.org/pipermail/devicetree-discuss/2009-March/000597.html

-- 
Pengutronix e.K.                           | Wolfram Sang                |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |

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Re: OF PCI howto?

[Kumar Gala]

On Apr 15, 2009, at 8:08 AM, Wolfram Sang wrote:

> On Wed, Apr 15, 2009 at 02:54:57PM +0200, Joakim Tjernlund wrote:
>
>> dts fragment correct for my setup? If not, is there a better  
>> example I can
>> look at?
>
> Maybe this message/thread can help you:
>
> http://ozlabs.org/pipermail/devicetree-discuss/2009-March/000597.html

You may also want to take a look at ePAPR on the power.org site

- k

Re: OF PCI howto?

[Joakim Tjernlund]

Kumar Gala <galak@kernel.crashing.org> wrote on 15/04/2009 17:20:21:
> On Apr 15, 2009, at 8:08 AM, Wolfram Sang wrote:
> 
> > On Wed, Apr 15, 2009 at 02:54:57PM +0200, Joakim Tjernlund wrote:
> >
> >> dts fragment correct for my setup? If not, is there a better 
> >> example I can
> >> look at?
> >
> > Maybe this message/thread can help you:
> >
> > http://ozlabs.org/pipermail/devicetree-discuss/2009-March/000597.html
> 
> You may also want to take a look at ePAPR on the power.org site

Thanks guys

Looking in ePAPR I see I should read the IDSEL like this:
                /* IDSEL 0x11 AD17 */
                0x8800 0x0 0x0 0x1 &ipic 20 0x8 /* INTA */
                0x8800 0x0 0x0 0x2 &ipic 21 0x8 /* INTB */
                0x8800 0x0 0x0 0x3 &ipic 22 0x8 /* INTC */
                0x8800 0x0 0x0 0x4 &ipic 23 0x8 /* INTD */

grouping the first line into:
"0x8800 0x0 0x0" "0x1" "&ipic" "20 0x8" /* INTA */

"0x8800 0x0 0x0" = child unit address
"0x1" = child interrupt specifier = INTA
"&ipic" = interrupt parent
"20 0x8" = parent interrupt specifier

Questions:
 MPC832x appears to only have INTA so why are the INTB,INTC 
 and INTD lines there?

 I don't understand how IDSEL values are decided. Are IDSEL 0x11-0x18 
randomly
 selected or are they fixed for MPC832x?

What I really trying to understand is what fields I might need to change
and what to change them to.
So far the "interrupt-map" and the "ranges" items looks like they might 
need
some tweaking, but I really don't know at this point.
Any pointers in this area is much appreciated.

 Jocke

Re: OF PCI howto?

[Roderick Colenbrander]

On Thu, Apr 16, 2009 at 10:05 AM, Joakim Tjernlund
<Joakim.Tjernlund@transmode.se> wrote:
> Kumar Gala <galak@kernel.crashing.org> wrote on 15/04/2009 17:20:21:
>> On Apr 15, 2009, at 8:08 AM, Wolfram Sang wrote:
>>
>> > On Wed, Apr 15, 2009 at 02:54:57PM +0200, Joakim Tjernlund wrote:
>> >
>> >> dts fragment correct for my setup? If not, is there a better
>> >> example I can
>> >> look at?
>> >
>> > Maybe this message/thread can help you:
>> >
>> > http://ozlabs.org/pipermail/devicetree-discuss/2009-March/000597.html
>>
>> You may also want to take a look at ePAPR on the power.org site
>
> Thanks guys
>
> Looking in ePAPR I see I should read the IDSEL like this:
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0/* IDSEL 0x11 AD17 */
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A00x8800 0x0 0x0 0x1 &ipic 20 0x8 /* INTA */
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A00x8800 0x0 0x0 0x2 &ipic 21 0x8 /* INTB */
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A00x8800 0x0 0x0 0x3 &ipic 22 0x8 /* INTC */
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A00x8800 0x0 0x0 0x4 &ipic 23 0x8 /* INTD */
>
> grouping the first line into:
> "0x8800 0x0 0x0" "0x1" "&ipic" "20 0x8" /* INTA */
>
> "0x8800 0x0 0x0" =3D child unit address
> "0x1" =3D child interrupt specifier =3D INTA
> "&ipic" =3D interrupt parent
> "20 0x8" =3D parent interrupt specifier
>
> Questions:
> =A0MPC832x appears to only have INTA so why are the INTB,INTC
> =A0and INTD lines there?
>
> =A0I don't understand how IDSEL values are decided. Are IDSEL 0x11-0x18
> randomly
> =A0selected or are they fixed for MPC832x?

The idsel values depend on how the pci slots are wired on your board.
The 0x8800 value is
in general a function of bus, device and function number. ( bus << 16
| devfn << 8)

Further I would also watch out with the parent interrupt specifier
e.g. '20 0x8'. The openfirmware spec
normally suggests to use a value of '2' for interrupts which are
active low. During parsing of the interrupt-map
this value is normally translated using 'xlate' to linux kernel values
(active low is defined as IRQ_TYPE_LEVEL_LOW      0x00000008 in the
kernel).
The ipic driver code and various dts files are evil and store the
linux kernel value inside the DTS file, so they don't do any
conversion whis is EVIL
in my opinion. Watch out for that. (The corresponding DTS files and
drivers should be updated).

Regards,
Roderick Colenbrander

Re: OF PCI howto?

[Scott Wood]

On Thu, Apr 16, 2009 at 11:03:56AM +0200, Roderick Colenbrander wrote:
> The ipic driver code and various dts files are evil and store the
> linux kernel value inside the DTS file, so they don't do any
> conversion whis is EVIL
> in my opinion. Watch out for that. (The corresponding DTS files and
> drivers should be updated).

We should have made up some *other* arbitrary encoding instead?

Or perhaps reused the MPIC's screwy encoding that doesn't separate bits
for level and sense?

-Scott

Re: OF PCI howto?

[Grant Likely]

On Thu, Apr 16, 2009 at 3:03 AM, Roderick Colenbrander
<thunderbird2k@gmail.com> wrote:
> On Thu, Apr 16, 2009 at 10:05 AM, Joakim Tjernlund
> <Joakim.Tjernlund@transmode.se> wrote:
>> Kumar Gala <galak@kernel.crashing.org> wrote on 15/04/2009 17:20:21:
>>> On Apr 15, 2009, at 8:08 AM, Wolfram Sang wrote:
>>>
>>> > On Wed, Apr 15, 2009 at 02:54:57PM +0200, Joakim Tjernlund wrote:
>>> >
>>> >> dts fragment correct for my setup? If not, is there a better
>>> >> example I can
>>> >> look at?
>>> >
>>> > Maybe this message/thread can help you:
>>> >
>>> > http://ozlabs.org/pipermail/devicetree-discuss/2009-March/000597.html
>>>
>>> You may also want to take a look at ePAPR on the power.org site
>>
>> Thanks guys
>>
>> Looking in ePAPR I see I should read the IDSEL like this:
>> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0/* IDSEL 0x11 AD17 */
>> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A00x8800 0x0 0x0 0x1 &ipic 20 0x8 /* INTA *=
/
>> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A00x8800 0x0 0x0 0x2 &ipic 21 0x8 /* INTB *=
/
>> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A00x8800 0x0 0x0 0x3 &ipic 22 0x8 /* INTC *=
/
>> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A00x8800 0x0 0x0 0x4 &ipic 23 0x8 /* INTD *=
/
>>
>> grouping the first line into:
>> "0x8800 0x0 0x0" "0x1" "&ipic" "20 0x8" /* INTA */
>>
>> "0x8800 0x0 0x0" =3D child unit address
>> "0x1" =3D child interrupt specifier =3D INTA
>> "&ipic" =3D interrupt parent
>> "20 0x8" =3D parent interrupt specifier
>>
>> Questions:
>> =A0MPC832x appears to only have INTA so why are the INTB,INTC
>> =A0and INTD lines there?
>>
>> =A0I don't understand how IDSEL values are decided. Are IDSEL 0x11-0x18
>> randomly
>> =A0selected or are they fixed for MPC832x?
>
> The idsel values depend on how the pci slots are wired on your board.
> The 0x8800 value is
> in general a function of bus, device and function number. ( bus << 16
> | devfn << 8)
>
> Further I would also watch out with the parent interrupt specifier
> e.g. '20 0x8'. The openfirmware spec
> normally suggests to use a value of '2' for interrupts which are
> active low. During parsing of the interrupt-map
> this value is normally translated using 'xlate' to linux kernel values
> (active low is defined as IRQ_TYPE_LEVEL_LOW =A0 =A0 =A00x00000008 in the
> kernel).
> The ipic driver code and various dts files are evil and store the
> linux kernel value inside the DTS file, so they don't do any
> conversion whis is EVIL
> in my opinion. Watch out for that.

They're just numbers and they are intended to by interrupt controller
specific values.  Some IRQ controllers don't even have a 'flags' field
for instance.  The binding author is free to choose values he or she
deems suitable for the purpose as long as it is documented and
reviewed.

> (The corresponding DTS files and
> drivers should be updated).

No.  The binding is set.  We've made a commitment to not change
bindings after they are defined and deployed.  In some cases it is not
easy to update the device tree blob in deployed systems.


>
> Regards,
> Roderick Colenbrander
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-dev
>



--=20
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.