From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: MIME-Version: 1.0 Sender: slightlyunconventional@gmail.com In-Reply-To: <20100301191351.20987.49730.sendpatchset@norville.austin.ibm.com> References: <20100301191255.20987.84668.sendpatchset@norville.austin.ibm.com> <20100301191351.20987.49730.sendpatchset@norville.austin.ibm.com> Date: Thu, 4 Mar 2010 09:06:40 -0800 Message-ID: Subject: Re: [RFC: PATCH 08/13] powerpc/476: define specific cpu table entry for DD1 and DD1.1 cores From: Hollis Blanchard To: Dave Kleikamp Content-Type: multipart/alternative; boundary=00504502cbfb5adf720480fc9f6b Cc: linuxppc-dev list , Torez Smith List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , --00504502cbfb5adf720480fc9f6b Content-Type: text/plain; charset=ISO-8859-1 On Mon, Mar 1, 2010 at 11:13 AM, Dave Kleikamp wrote: > powerpc/476: define specific cpu table entry for DD1 and DD1.1 cores > > From: Benjamin Herrenschmidt > > There are still some unstable bits on the DD1 and DD1.1 cores. Don't use > the FPU or the tlbivax operation. Define CPU_FTR_476_DD1 and > CPU_FTR_476_DD1_1 for additional workarounds in later patches. > > The DD1 core requires workarounds triggered by both CPU_FTR_476_DD1 > and CPU_FTR_476_DD1_1. the DD1.1 core only needs CPU_FTR_476_DD1_1 > defined. > > Isn't the policy generally not to commit workarounds for early/errataful hardware which will not be seen in the real world? Otherwise, every new half-broken core could burn a bunch of feature bits... -Hollis --00504502cbfb5adf720480fc9f6b Content-Type: text/html; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable On Mon, Mar 1, 2010 at 11:13 AM, Dave Kleikamp <shaggy@linux.vnet.ibm.com> wrote:
powerpc/476: define specific cpu table entry for DD1 and DD1.1 cores

From: Benjamin Herrenschmidt <benh@kernel.crashing.org>

There are still some unstable bits on the DD1 and DD1.1 cores. =A0Don't= use
the FPU or the tlbivax operation. =A0Define CPU_FTR_476_DD1 and
CPU_FTR_476_DD1_1 for additional workarounds in later patches.

The DD1 core requires workarounds triggered by both CPU_FTR_476_DD1
and CPU_FTR_476_DD1_1. =A0the DD1.1 core only needs CPU_FTR_476_DD1_1
defined.

Isn't the policy generally not to com= mit workarounds for early/errataful hardware which will not be seen in the = real world? Otherwise, every new half-broken core could burn a bunch of feature bits...

-Hollis
=A0
--00504502cbfb5adf720480fc9f6b--