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Mon, 19 Sep 2022 06:49:23 GMT Received: from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 08297A404D; Mon, 19 Sep 2022 06:49:23 +0000 (GMT) Received: from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 5B3B6A4053; Mon, 19 Sep 2022 06:49:22 +0000 (GMT) Received: from ozlabs.au.ibm.com (unknown [9.192.253.14]) by d06av23.portsmouth.uk.ibm.com (Postfix) with ESMTP; Mon, 19 Sep 2022 06:49:22 +0000 (GMT) Received: from [10.61.2.107] (haven.au.ibm.com [9.192.254.114]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.au.ibm.com (Postfix) with ESMTPSA id 73B65602EA; Mon, 19 Sep 2022 16:49:13 +1000 (AEST) Message-ID: Subject: Re: [PATCH 1/6] powerpc/code-patching: Implement generic text patching function From: Benjamin Gray To: Christophe Leroy , "linuxppc-dev@lists.ozlabs.org" Date: Mon, 19 Sep 2022 16:49:13 +1000 In-Reply-To: <4c19a0fa-6af0-e71a-deaf-b150eeec6381@csgroup.eu> References: <20220916062330.430468-1-bgray@linux.ibm.com> <20220916062330.430468-2-bgray@linux.ibm.com> <4c19a0fa-6af0-e71a-deaf-b150eeec6381@csgroup.eu> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.44.4 (3.44.4-1.fc36) MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: 73RXf5HwWRlllT8LoakyjEHD06miVfQ6 X-Proofpoint-GUID: gSlMiGPcXkL4gkf-8qm8alCLMzK0xoUh X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.528,FMLib:17.11.122.1 definitions=2022-09-19_03,2022-09-16_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 priorityscore=1501 spamscore=0 lowpriorityscore=0 clxscore=1015 impostorscore=0 bulkscore=0 suspectscore=0 malwarescore=0 mlxlogscore=999 phishscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2209130000 definitions=main-2209190042 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "ajd@linux.ibm.com" , "peterz@infradead.org" , "npiggin@gmail.com" , "ardb@kernel.org" , "jbaron@akamai.com" , "rostedt@goodmis.org" , "jpoimboe@kernel.org" Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" On Mon, 2022-09-19 at 06:04 +0000, Christophe Leroy wrote: > With CONFIG_STRICT_KERNEL_RWX, this patches causes a 15% time > increase=20 > for activation/deactivation of ftrace. It's possible that new alignment check is the cause. I'll see > Without CONFIG_STRICT_KERNEL_RWX, it doesn't build. Yup, fixed for v2 > > +static int __patch_text(void *dest, const void *src, size_t size, > > bool is_exec, void *exec_addr) >=20 > Is 'text' a good name ? For me text mean executable code. Should it > be=20 > __patch_memory() ? Well patching regular memory is just a normal store. Text to me implies its non-writeable. Though __patch_memory would be fine. > Why pass src as a void * ? This forces data to go via the stack. > Can't=20 > you pass it as a 'long' ? Probably, I wasn't aware that it would make a difference. I prefer pointers in general for their semantic meaning, but will change if it affects param passing. > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0if (virt_to_pfn(dest) !=3D v= irt_to_pfn(dest + size - 1)) > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0return -EFAULT; >=20 > Why do you need that new check ? If the patch crosses a page boundary then letting it happen is unpredictable. Though perhaps this requirement can just be put as a comment, or require that patches be aligned to the patch size. > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0case 8: > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0__put_= kernel_nofault(dest, src, u64, > > failed); > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0break; >=20 > Is case 8 needed for PPC32 ? I don't have a particular need for it, but the underlying __put_kernel_nofault is capable of it so I included it. > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0} >=20 > Do you catch it when size if none of 1,2,4,8 ? >=20 Not yet. Perhaps I should wrap patch_text_data in a macro that checks the size with BUILD_BUG_ON? I'd rather not check at runtime. > > + > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0asm ("dcbst 0, %0; sync" :: = "r" (dest)); >=20 > Maybe write it in C: >=20 > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0dcbst(dest); > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0mb(); /* sync */ >=20 > > + > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0if (is_exec) > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0asm ("icbi 0,%0; sync; isync" :: "r" (exec_addr)); >=20 > Same, can be: >=20 > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0if (is_exec) { > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0icbi(exec_addr); > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0mb(); /* sync */ > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0isync(); > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0} >=20 > Or keep it flat: >=20 > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0if (!is_exec) > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0return 0; >=20 > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0icbi(exec_addr); > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0mb(); /* sync */ > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0isync(); >=20 > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0return 0; Will try this. > > +static int do_patch_text(void *dest, const void *src, size_t size, > > bool is_exec) > > +{ > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0int err; > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0pte_t *pte; > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0u32 *patch_addr; > > + > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0pte =3D start_text_patch(des= t, &patch_addr); > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0err =3D __patch_text(patch_a= ddr, src, size, is_exec, dest); > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0finish_text_patch(pte); >=20 > Why do you need to split this function in three parts ? I can't see > the=20 > added value, all it does is reduce readability. It made it more readable to me, so the __patch_text didn't get buried. It also made it easier to do the refactoring, and potentially add code patching variants that use the poke area but not __patch_text. I'll remove it for v2 though given this is the only use right now. > Did you check the impact of calling __this_cpu_read() twice ? I wasn't concerned about performance, but given I'll merge it back again it will only be read once in v2 again. > > +void *patch_memory(void *dest, const void *src, size_t size) >=20 > What is this function used for ? >=20 Build failure apparently :) It's removed in v2. >=20