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From: ebiederm@xmission.com (Eric W. Biederman)
To: David Miller <davem@davemloft.net>
Subject: Re: [RFC/PATCH 0/16] Ops based MSI Implementation
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Date: Wed, 31 Jan 2007 00:40:34 -0700
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David Miller <davem@davemloft.net> writes:

> From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> Date: Mon, 29 Jan 2007 11:58:21 +1100
>
>> Do you have some pointers to documentation on those sparc64
>> interfaces ?
>
> So I got things working on sparc64 with a one-liner to the current
> upstream vanilla 2.6.20-rc7 :-)  It's not the best, but it works.
>
> You can see it all at:
>
> 	kernel.org:/pub/scm/linux/kernel/git/davem/sparc-2.6.git
>
> Basically, I changed arch_teardown_msi_irq() to pass in the
> PCI device pointer, that's it.

Neat. 

I think you could have omitted your one liner if you had done:
struct msi_desc *entry = get_irq_data(irq);
struct pci_dev *dev = entry->dev;

> The rest is sparc64 specific stuff.
>
> One thing that's disappointing is that this "MSI Queue" framework
> sparc64 has really suggests a two-tiered interrupt handling scheme.
> As I previously explained, on sparc64 you assosciated each MSI with a
> queue, and you can attach multiple MSIs to a single queue.

Interesting.

> I've tested tg3 with MSI on my Niagara, it seems to work well.
> Unfortunately I don't have any MSI-X capable devices here, but
> eventually I am sure I will.  I glanced over the MSI-X code and I see
> no reason why it wouldn't work.

Congratulations!

Eric