From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from ebiederm.dsl.xmission.com (ebiederm.dsl.xmission.com [166.70.28.69]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTP id 1C114DDEEA for ; Sat, 27 Jan 2007 15:29:28 +1100 (EST) From: ebiederm@xmission.com (Eric W. Biederman) To: David Miller Subject: Re: [RFC/PATCH 14/16] MPIC MSI backend References: <17850.33971.762011.194195@cargo.ozlabs.ibm.com> <20070126.190216.95060896.davem@davemloft.net> Date: Fri, 26 Jan 2007 21:28:52 -0700 In-Reply-To: <20070126.190216.95060896.davem@davemloft.net> (David Miller's message of "Fri, 26 Jan 2007 19:02:16 -0800 (PST)") Message-ID: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Cc: grundler@parisc-linux.org, greg@kroah.com, kyle@parisc-linux.org, linuxppc-dev@ozlabs.org, paulus@samba.org, brice@myri.com, shaohua.li@intel.com, linux-pci@atrey.karlin.mff.cuni.cz List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , David Miller writes: > > Interesting. > > This is exactly how all sparc64 chips have always worked too. On > sparc64 the cpu can actually read in the packets and process them. > Can the x86 interrupt handler get at the full packet data? I wish. All it can get is a single byte of the packet, for selecting what to do. The rest of the information encodes irq type and which cpu to send interrupt to. Eric