* problem on netdevice
From: zhonglei @ 2004-11-25 2:42 UTC (permalink / raw)
To: linuxppc-dev
hi
Sorry for bothering you! But would you please give me a hand.When I insert a Intel Pro/100s server Adapter into the PCI slot on Lite5200(motorola MPC5200 development kit) and start the embedded kernel,the kernel run into a dead lock. (Before that I used 'make xconfig' to enable the e100 driver in kernel)
The reports are as follows:
.
.
.
IP-Config: Retrying forever (NFS root)...
eth1: config: auto-negotiation on, 100FDX, 100HDX, 10FDX, 10HDX.
eth1: Waiting for the link to be up...
eth1: status: link up, 100 Mbps Full Duplex, auto-negotiation complete.
e100: eth0 NIC Link is Up 100 Mbps Full duplex
Sending DHCP requests ...... timed out!
Please tell me how can I handle it! Thanks in advance!
Best Regards
zhonglei
^ permalink raw reply
* question on netdevice
From: zhonglei @ 2004-11-25 2:37 UTC (permalink / raw)
To: linuxppc-embedded
hi
Sorry for bothering you! But would you please give me a hand.When I insert a Intel Pro/100s server Adapter into the PCI slot on Lite5200(motorola MPC5200 development kit) and start the embedded kernel,the kernel run into a dead lock. (Before that I used 'make xconfig' to enable the e100 driver in kernel)
The reports are as follows:
.
.
.
IP-Config: Retrying forever (NFS root)...
eth1: config: auto-negotiation on, 100FDX, 100HDX, 10FDX, 10HDX.
eth1: Waiting for the link to be up...
eth1: status: link up, 100 Mbps Full Duplex, auto-negotiation complete.
e100: eth0 NIC Link is Up 100 Mbps Full duplex
Sending DHCP requests ...... timed out!
Because there is another netdevice in MPC5200(I use it to mount NFS root) as eth0 , is there a ip setting problem?
Please tell me how can I handle it! Thanks in advance!
Best Regards
zhonglei
^ permalink raw reply
* Re: TEST: Sleep patch #5
From: Benjamin Herrenschmidt @ 2004-11-25 0:51 UTC (permalink / raw)
To: Colin Leroy; +Cc: linuxppc-dev list
In-Reply-To: <20041124085054.14a89f5f@pirandello>
On Wed, 2004-11-24 at 08:50 +0100, Colin Leroy wrote:
> On 24 Nov 2004 at 18h11, Benjamin Herrenschmidt wrote:
>
> Hi Ben,
>
> > Ok, here's the 5th version of the sleep patch for ATI based albooks &
> > iBook G4. Other machine users, please test too as it may cause
> > regressions (or improvements) as well.
>
> Care to apply the attached patch to your tree ? It would avoid me
> a failing hunk when applying your patches, and also that's what
> AppleGmacEthernet does.
Ok. Does WOL works btw ?
Ben.
^ permalink raw reply
* Pthread dynamic linking problem
From: Iñigo Lopez Barranco @ 2004-11-24 17:23 UTC (permalink / raw)
To: linuxppc-embedded
Hi.
We're using use ELDK 3.0 with kernel linuxppc_2_4_devel from DENX CVS on =
a Lite5200 board.
The problem arises linking a program with a library using fopen and the =
pthread lib dynamically. My program gets stucked when doing a fopen =
call. This doesn't happen if the linking is static (against .a).
Here are an example library and program that show this problem:
* The main program is:
//
// cositas.cpp
//
#include <stdio.h>
#include <pthread.h>
void Polopos(char *fname);
int main(int argc, char **argv)
{
pthread_t th;
=09
// Do things
Polopos("/etc/AVMRecorder.conf");
return 0;
}
* The library it uses along with pthread lib is:
//=20
// acasitos.cpp
//
#include <stdio.h>
void Polopos(char *foo)
{
fprintf(stderr, "Opening file %s...\n", foo);
FILE* cositas =3D fopen(foo, "rt");
fprintf(stderr, "...file %s open\n", foo);
fprintf(stderr, "Closing file %s...\n", foo);
fclose(cositas);
fprintf(stderr, "...file %s closed\n", foo);
}
* To build the shared lib I issue the following commands:
@ /usr/local/ppc_82xx/bin/ppc_82xx-g++ -c -o acasitos.o =
-I/usr/local/ppc_82xx/local/include acasitos.cpp
@ /usr/local/ppc_82xx/bin/ppc_82xx-ld -o libacasitos.so acasitos.o
* And for the final binary:
@ /usr/local/ppc_82xx/bin/ppc_82xx-g++ -o cositas -L. =
-I/usr/local/ppc_82xx/local/include -lpthread -lacasitos cositas.cpp
* The output for the program is:
Opening file /etc/AVMRecorder.conf...
* The output of strace is:
execve("./cositas", ["./cositas"], [/* 20 vars */]) =3D 0
uname({sys=3D"Linux", node=3D"localhost", ...}) =3D 0
brk(0) =3D 0x10011c68
open("/etc/ld.so.preload", O_RDONLY) =3D -1 ENOENT (No such file or =
directory)
open("/etc/ld.so.cache", O_RDONLY) =3D 3
fstat64(3, {st_mode=3DS_IFREG|0644, st_size=3D11995, ...}) =3D 0
mmap(NULL, 11995, PROT_READ, MAP_PRIVATE, 3, 0) =3D 0x30015000
close(3) =3D 0
open("/lib/libpthread.so.0", O_RDONLY) =3D 3
read(3, "\177ELF\1\2\1\0\0\0\0\0\0\0\0\0\0\3\0\24\0\0\0\1\0\0@\374"..., =
1024) =3D 1024
fstat64(3, {st_mode=3DS_IFREG|0755, st_size=3D1416528, ...}) =3D 0
mmap(0xff8f000, 395776, PROT_READ|PROT_EXEC, MAP_PRIVATE, 3, 0) =3D =
0xff8f000
mprotect(0xff9d000, 338432, PROT_NONE) =3D 0
mmap(0xff9f000, 69632, PROT_READ|PROT_WRITE|PROT_EXEC, =
MAP_PRIVATE|MAP_FIXED, 3, 0) =3D 0xff9f000
mmap(0xffb0000, 260608, PROT_READ|PROT_WRITE|PROT_EXEC, =
MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) =3D 0xffb0000
close(3) =3D 0
open("/usr/local/lib/libacasitos.so", O_RDONLY) =3D 3
read(3, "\177ELF\1\2\1\0\0\0\0\0\0\0\0\0\0\3\0\24\0\0\0\1\0\0\4"..., =
1024) =3D 1024
fstat64(3, {st_mode=3DS_IFREG|0755, st_size=3D3141, ...}) =3D 0
mmap(NULL, 4096, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) =
=3D 0x30018000
mmap(0xff6e000, 67136, PROT_READ|PROT_EXEC, MAP_PRIVATE, 3, 0) =3D =
0xff6e000
mprotect(0xff6f000, 63040, PROT_NONE) =3D 0
mmap(0xff7e000, 4096, PROT_READ|PROT_WRITE|PROT_EXEC, =
MAP_PRIVATE|MAP_FIXED, 3, 0) =3D 0xff7e000
close(3) =3D 0
open("/usr/lib/libstdc++.so.5", O_RDONLY) =3D 3
read(3, "\177ELF\1\2\1\0\0\0\0\0\0\0\0\0\0\3\0\24\0\0\0\1\0\4C\250"..., =
1024) =3D 1024
fstat64(3, {st_mode=3DS_IFREG|0755, st_size=3D809956, ...}) =3D 0
mmap(0xfe82000, 898616, PROT_READ|PROT_EXEC, MAP_PRIVATE, 3, 0) =3D =
0xfe82000
mprotect(0xff35000, 165432, PROT_NONE) =3D 0
mmap(0xff42000, 86016, PROT_READ|PROT_WRITE|PROT_EXEC, =
MAP_PRIVATE|MAP_FIXED, 3, 0xb0000) =3D 0xff42000
mmap(0xff57000, 26168, PROT_READ|PROT_WRITE|PROT_EXEC, =
MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) =3D 0xff57000
close(3) =3D 0
open("/lib/libm.so.6", O_RDONLY) =3D 3
read(3, "\177ELF\1\2\1\0\0\0\0\0\0\0\0\0\0\3\0\24\0\0\0\1\0\0\242"..., =
1024) =3D 1024
fstat64(3, {st_mode=3DS_IFREG|0755, st_size=3D497740, ...}) =3D 0
mmap(0xfdec000, 545232, PROT_READ|PROT_EXEC, MAP_PRIVATE, 3, 0) =3D =
0xfdec000
mprotect(0xfe5f000, 74192, PROT_NONE) =3D 0
mmap(0xfe6c000, 20480, PROT_READ|PROT_WRITE|PROT_EXEC, =
MAP_PRIVATE|MAP_FIXED, 3, 0x70000) =3D 0xfe6c000
mmap(0xfe71000, 464, PROT_READ|PROT_WRITE|PROT_EXEC, =
MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) =3D 0xfe71000
close(3) =3D 0
open("/lib/libc.so.6", O_RDONLY) =3D 3
read(3, "\177ELF\1\2\1\0\0\0\0\0\0\0\0\0\0\3\0\24\0\0\0\1\0\1\300"..., =
1024) =3D 1024
fstat64(3, {st_mode=3DS_IFREG|0755, st_size=3D1363888, ...}) =3D 0
mmap(0xfc8d000, 1370128, PROT_READ|PROT_EXEC, MAP_PRIVATE, 3, 0) =3D =
0xfc8d000
mprotect(0xfdc4000, 96272, PROT_NONE) =3D 0
mmap(0xfdcd000, 49152, PROT_READ|PROT_WRITE|PROT_EXEC, =
MAP_PRIVATE|MAP_FIXED, 3, 0x130000) =3D 0xfdcd000
mmap(0xfdd9000, 10256, PROT_READ|PROT_WRITE|PROT_EXEC, =
MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) =3D 0xfdd9000
close(3) =3D 0
mprotect(0xfc8d000, 1273856, PROT_READ|PROT_WRITE) =3D 0
mprotect(0xfc8d000, 1273856, PROT_READ|PROT_EXEC) =3D 0
mprotect(0xff6e000, 4096, PROT_READ|PROT_WRITE) =3D 0
mprotect(0xff6e000, 4096, PROT_READ|PROT_EXEC) =3D 0
munmap(0x30015000, 11995) =3D 0
getpid() =3D 1212
rt_sigaction(SIGRTMIN, {0xff97690, [], 0}, NULL, 8) =3D 0
rt_sigaction(SIGRT_1, {0xff97548, [], 0}, NULL, 8) =3D 0
rt_sigaction(SIGRT_2, {0xff976c8, [], 0}, NULL, 8) =3D 0
rt_sigprocmask(SIG_BLOCK, [RTMIN], NULL, 8) =3D 0
_sysctl({{CTL_KERN, KERN_VERSION}, 2, 0x7ffff898, 33, (nil), 0}) =3D 0
brk(0) =3D 0x10011c68
brk(0x10012c68) =3D 0x10012c68
brk(0x10013000) =3D 0x10013000
write(2, "Opening file /etc/AVMRecorde"..., 42Opening file =
/etc/AVMRecorder.conf...
) =3D 42
rt_sigprocmask(SIG_SETMASK, NULL, [RTMIN], 8) =3D 0
rt_sigsuspend([] <unfinished ...>
It remains in the last line until I Ctrl-C the program.
Thanks in advance
^ permalink raw reply
* CRAMFS decompression
From: Sauro Salomoni @ 2004-11-24 11:16 UTC (permalink / raw)
To: linuxppc-embedded
Does anybory know where I can find some good documentation about
CRAMFS file systems?
I am having a problem in my embedded linux system, in wich I use 2
file systems: CRAMFS for the OS and JFFS2 for the applications. When
it tries to decompress the CRAMFS partition, it crashes and reboots...
I need to know how the kernel deals with the data, and where the
decompressed data goes (RAMDISK? TMPFS?).
I am currently using a Lite5200 board with 2.4.25 Denx linux kernel.
Thanks in advance
--
Sauro Salomoni
Ztec - Engineering
Phone: +55 61 322-2544 FAX:+55 61 224-7171
www.ztec.com.br
^ permalink raw reply
* Re: MPC5200 Cache coherency with BestComm issue (was: Lite5200 FEC Driver on linux 2.6 (updated))
From: Sylvain Munaut @ 2004-11-24 8:22 UTC (permalink / raw)
To: roger blofeld; +Cc: linuxppc-embedded
In-Reply-To: <20041123224241.1791.qmail@web53506.mail.yahoo.com>
Hi roger
> Using your latest tree still shows the packet checksum errors, despite
>XLB snooping being enabled.
>
>I think that the cache flush is required
>
It really shouldn't be.
Take a look at
http://www.freescale.com/files/microcontrollers/doc/app_note/AN2604.pdf,
page 3, 4th paragraph
quote : <<< In case the memory location interested by BestComm accesses
are cached in
copy-back mode by the core, a "Snooping" activity can be forced to the
core, so that an
'address retry' will be issued and the core will first flush it's cache
line before allowing
BestComm to retry it's transaction. >>>
Note that performance wise, adding it is probably a good idea. It will
have to be flushed
eventually and forcing BestComm to retry a transaction is just waste of
XLB cycles ...
>or
>that the skb pages must be marked coherent somehow.
>
Yes they must. I haven't checked if they were but since this requirement
is common
for multiple ppc, I'd guess they are.
>I note that the 8xx
>fec.c file also has a cache flush, so it isn't that strange.
>
>
I don't know 8xx in details, but in arch/ppc/Kconfig, 8xx defines
NOT_COHERENT_CACHE symbol. So they probably excpect it not to be.
Sylvain
^ permalink raw reply
* Re: TEST: Sleep patch #5
From: Colin Leroy @ 2004-11-24 7:50 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <1101280145.4511.4.camel@gaston>
[-- Attachment #1: Type: text/plain, Size: 420 bytes --]
On 24 Nov 2004 at 18h11, Benjamin Herrenschmidt wrote:
Hi Ben,
> Ok, here's the 5th version of the sleep patch for ATI based albooks &
> iBook G4. Other machine users, please test too as it may cause
> regressions (or improvements) as well.
Care to apply the attached patch to your tree ? It would avoid me
a failing hunk when applying your patches, and also that's what
AppleGmacEthernet does.
Thanks,
--
Colin
[-- Attachment #2: sungem_wol_opts.patch --]
[-- Type: text/plain, Size: 833 bytes --]
--- drivers/net/sungem_phy.c.orig 2004-11-24 08:43:44.499855352 +0100
+++ drivers/net/sungem_phy.c 2004-11-24 08:42:58.990773784 +0100
@@ -147,13 +147,15 @@
static int bcm5221_suspend(struct mii_phy* phy, int wol_options)
{
u16 data;
- data = phy_read(phy, MII_BCM5221_TEST);
- phy_write(phy, MII_BCM5221_TEST,
- data | MII_BCM5221_TEST_ENABLE_SHADOWS);
-
- data = phy_read(phy, MII_BCM5221_SHDOW_AUX_MODE4);
- phy_write(phy, MII_BCM5221_SHDOW_AUX_MODE4,
- data | MII_BCM5221_SHDOW_AUX_MODE4_IDDQMODE);
+ if (!wol_options) {
+ data = phy_read(phy, MII_BCM5221_TEST);
+ phy_write(phy, MII_BCM5221_TEST,
+ data | MII_BCM5221_TEST_ENABLE_SHADOWS);
+
+ data = phy_read(phy, MII_BCM5221_SHDOW_AUX_MODE4);
+ phy_write(phy, MII_BCM5221_SHDOW_AUX_MODE4,
+ data | MII_BCM5221_SHDOW_AUX_MODE4_IDDQMODE);
+ }
return 0;
}
^ permalink raw reply
* TEST: Sleep patch #5
From: Benjamin Herrenschmidt @ 2004-11-24 7:09 UTC (permalink / raw)
To: debian-powerpc@lists.debian.org, linuxppc-dev list; +Cc: gentoo-ppc-user
Ok, here's the 5th version of the sleep patch for ATI based albooks &
iBook G4. Other machine users, please test too as it may cause
regressions (or improvements) as well.
Not many changes since last version, I don't know why sometimes, the
panel doesn't come back properly (though a new sleep cycle tends to fix
it) and I have no fix for the USB issues. However, I added some hacks to
the cache flush code based on what Apple does in Darwin that may help
make the thing more robust, and I added a hook mecanism that allow the
video to be restored _very_ early on wakeup, pretty much before
everything else, thus making it easier to spot & debug crashes on
wakeup.
There are still pending issues, like cpufreq on some machines will
"think" it's running at full speed on wakeup while it's in fact running
at slow speed (thankfully not the opposite), I will try to fix those in
the next iteration.
http://gate.crashing.org/~benh/albook-ibookg4-sleep-5.diff
Ben.
^ permalink raw reply
* Re: TEST: Sleep patch #4
From: Benjamin Herrenschmidt @ 2004-11-23 23:27 UTC (permalink / raw)
To: Michael Schmitz; +Cc: linuxppc-dev list, debian-powerpc@lists.debian.org
In-Reply-To: <Pine.LNX.4.44.0411231224150.7434-100000@zirkon.biophys.uni-duesseldorf.de>
> Looking at radeon_base.c:radeon_screen_blank() (line 1045) we have:
>
> val &= ~(LVDS_BL_MOD_EN);
> udelay(100);
> val &= ~(LVDS_ON | LVDS_EN);
> OUTREG(LVDS_GEN_CNTL, val);
>
>
> Is there an OUTREG(LVDS_GEN_CNTL, val); missing before the udelay(100) ??
>
> That's in the panel blank code, not the unblank code though. Doesn't seem
> to hurt to put the OUTREG in.
won't hurt, dunno if it will help tho... could also be a different
issue, like the spread spectrum PLL not locking properly or something
like that ... I don't really know.
Ben.
^ permalink raw reply
* Re: TEST: Sleep patch #4
From: Benjamin Herrenschmidt @ 2004-11-23 23:25 UTC (permalink / raw)
To: Sean Neakums
Cc: linuxppc-dev list, Keith Conger, debian-powerpc@lists.debian.org,
gentoo-ppc-user
In-Reply-To: <6upt25ezr4.fsf@zork.zork.net>
On Tue, 2004-11-23 at 08:27 +0000, Sean Neakums wrote:
> On resume this morning, though, the display was behaving oddly, both
> in X and on the console: it was sort of shimmering, split and repeated
> about 1/5 of the screen's width to the right in what looked like
> 8-pixel horizontal stripes. Rebooting seemed to sort it.
Next time, please try to take a picture of the screen. Also, try
sleeping & waking up again and tell me if that helps.
Ben.
^ permalink raw reply
* Re: Lite5200 FEC Driver on linux 2.6 (updated)
From: roger blofeld @ 2004-11-23 22:42 UTC (permalink / raw)
To: tnt; +Cc: linuxppc-embedded
In-Reply-To: <20041116201654.GA3088@xyzzy>
Sylvain,
Using your latest tree still shows the packet checksum errors, despite
XLB snooping being enabled. I think that the cache flush is required or
that the skb pages must be marked coherent somehow. I note that the 8xx
fec.c file also has a cache flush, so it isn't that strange.
-rb
__________________________________
Do you Yahoo!?
Meet the all-new My Yahoo! - Try it today!
http://my.yahoo.com
^ permalink raw reply
* Re: mpc7447a
From: Matt Porter @ 2004-11-23 21:24 UTC (permalink / raw)
To: r.k; +Cc: linuxppc-embedded
In-Reply-To: <004601c4d19b$77367450$a1b210ac@nvidia.com>
On Tue, Nov 23, 2004 at 12:31:47PM -0800, r.k wrote:
> any ideas how to generate tool chain for mpc7447a ???
Again and again in the archives: http://kegel.com/crosstool/
-Matt
^ permalink raw reply
* mpc7447a
From: r.k @ 2004-11-23 20:31 UTC (permalink / raw)
To: linuxppc-embedded
[-- Attachment #1: Type: text/plain, Size: 53 bytes --]
any ideas how to generate tool chain for mpc7447a ???
[-- Attachment #2: Type: text/html, Size: 368 bytes --]
^ permalink raw reply
* Re: Kernel 2.6 hangs at m82xx_board_init
From: Dan Malek @ 2004-11-23 20:13 UTC (permalink / raw)
To: alebas; +Cc: linuxppc-embedded
In-Reply-To: <1101236780.41a38a2c7f44f@webmail.televes.com:443>
On Nov 23, 2004, at 2:06 PM, alebas@televes.com wrote:
> When this code is executed, the kernel jumps directly to another
> address, 0xc000984c,
I suspect the MMU isn't yet set up to map the address of the BCSR.
Access the address causes a fault, and the "jump" you see is the
result of executing a bunch of exception handler instructions that
you won't single step due to the exception priorities.
-- Dan
^ permalink raw reply
* Re: U-Boot with DDR ECC Compilation Error
From: Wolfgang Denk @ 2004-11-23 19:04 UTC (permalink / raw)
To: Jeff Stevens; +Cc: linuxppc-embedded
In-Reply-To: <20041123161139.2563.qmail@web41415.mail.yahoo.com>
In message <20041123161139.2563.qmail@web41415.mail.yahoo.com> you wrote:
> I am porting U-Boot for a custom board that is very
You should post U-Boot related questions to the u-boot-users mailing
list instead. Here on this list you re off topic.
> similar to the MPC8540ADS. Everything compiles fine,
> until I try to compile in DDR SDRAM ECC support. I
> tried compiling U-Boot for the MPC8540ADS and I get
> the same error once I define 'CONFIG_DDR_ECC'. Here
> is the output:
CONFIG_DDR_ECC is set by default for the MPC8540ADS board; this configuration builds fine here. I guess you must be doing something wrong.
Is there any chance that your files got corrupted by storing in a
Windoze filesystem?
...
> ppc_8xx-gcc -Wa,-gstabs -D__ASSEMBLY__ -g -Os -fPIC
Why do you chose the ppc_8xx compiler here? This is not the optimal
choice for a 85xx processor (allthough this does not really matter
here).
...
> /orss/gtvme/uboot/u-boot-1.1.1/cpu/mpc85xx/start.S
Seems you are using U-Boot 1.1.1; why are you using an old version
for a new port? Please use current code (top of CVS) instead.
> I am using the ppc_8xx- tools from ELDK 3.1. I would
Try using current code, and make sure that your files are not
corrupted.
Best regards,
Wolfgang Denk
--
Software Engineering: Embedded and Realtime Systems, Embedded Linux
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de
Every living thing wants to survive.
-- Spock, "The Ultimate Computer", stardate 4731.3
^ permalink raw reply
* Kernel 2.6 hangs at m82xx_board_init
From: alebas @ 2004-11-23 19:06 UTC (permalink / raw)
To: linuxppc-embedded
Hi all,
I was trying to get kernel 2.6.10-rc1 running in mpc8272ads board,
but i have some problems.
Debugging with BDI2000 + gdb i have arrived to m82xx_board_init call,
which is coded in arch/ppc/platforms/pq2ads.c as:
void __init
m82xx_board_init(void)
{
/* Enable the 2nd UART port */
*(volatile uint *)(BCSR_ADDR + 4) &= ~BCSR1_RS232_EN2;
}
When this code is executed, the kernel jumps directly to another
address, 0xc000984c, which is inside the __delay function, and
execution stays here in an infinite loop.
I get the following disassemble from objdump:
c01bf908 <m82xx_board_init>:
c01bf908: 3d 20 f4 50 lis r9,-2992
c01bf90c: 61 29 00 04 ori r9,r9,4
c01bf910: 80 09 00 00 lwz r0,0(r9) <=======
c01bf914: 54 00 02 0c rlwinm r0,r0,0,8,6
c01bf918: 90 09 00 00 stw r0,0(r9)
c01bf91c: 4e 80 00 20 blr
and the marked instruction is the last one executed before the jump.
Any idea? Why this instruction is braching without control?
As bootloader i am using uboot-1.1.2.
Thanks.
Alex
^ permalink raw reply
* [PATCH][PPC32] Fix uninitialized PPC40x vars
From: Matt Porter @ 2004-11-23 16:19 UTC (permalink / raw)
To: akpm; +Cc: linux-kernel, linuxppc-embedded
Fix more uninitialized variables in the PPC40x code.
Signed-off-by: Matt Porter <mporter@kernel.crashing.org>
===== arch/ppc/boot/simple/misc-embedded.c 1.14 vs edited =====
--- 1.14/arch/ppc/boot/simple/misc-embedded.c 2004-09-07 23:33:06 -07:00
+++ edited/arch/ppc/boot/simple/misc-embedded.c 2004-11-23 09:15:34 -07:00
@@ -218,7 +218,7 @@
puts("done.\n");
{
struct bi_record *rec;
- unsigned long initrd_loc;
+ unsigned long initrd_loc = 0;
unsigned long rec_loc = _ALIGN((unsigned long)(zimage_size) +
(1 << 20) - 1, (1 << 20));
rec = (struct bi_record *)rec_loc;
===== arch/ppc/syslib/ppc405_pci.c 1.9 vs edited =====
--- 1.9/arch/ppc/syslib/ppc405_pci.c 2004-05-14 19:00:24 -07:00
+++ edited/arch/ppc/syslib/ppc405_pci.c 2004-11-23 09:15:03 -07:00
@@ -82,8 +82,8 @@
unsigned int tmp_addr;
unsigned int tmp_size;
unsigned int reg_index;
- unsigned int new_pmm_max;
- unsigned int new_pmm_min;
+ unsigned int new_pmm_max = 0;
+ unsigned int new_pmm_min = 0;
isa_io_base = 0;
isa_mem_base = 0;
^ permalink raw reply
* U-Boot with DDR ECC Compilation Error
From: Jeff Stevens @ 2004-11-23 16:11 UTC (permalink / raw)
To: linuxppc-embedded
I am porting U-Boot for a custom board that is very
similar to the MPC8540ADS. Everything compiles fine,
until I try to compile in DDR SDRAM ECC support. I
tried compiling U-Boot for the MPC8540ADS and I get
the same error once I define 'CONFIG_DDR_ECC'. Here
is the output:
ppc_8xx-gcc -Wa,-gstabs -D__ASSEMBLY__ -g -Os -fPIC
-ffixed-r14 -meabi -D__KERNEL__ -DTEXT_BASE=0xfff80000
-I/orss/gtvme/uboot/u-boot-1.1.1/include -fno-builtin
-ffreestanding -nostdinc -isystem
/usr/lib/gcc/i386-redhat-linux/3.4.2/include -pipe
-DCONFIG_PPC -D__powerpc__ -DCONFIG_MPC85xx
-DCONFIG_E500 -ffixed-r2 -ffixed-r29 -Wa,-me500
-msoft-float -DCONFIG_MPC85xx=1 -DCONFIG_MPC8540=1
-DCONFIG_E500=1 -c -o cpu/mpc85xx/start.o
/orss/gtvme/uboot/u-boot-1.1.1/cpu/mpc85xx/start.S
/orss/gtvme/uboot/u-boot-1.1.1/include/mpc85xx.h:
Assembler messages:
/orss/gtvme/uboot/u-boot-1.1.1/include/mpc85xx.h:16:
Error: Unrecognized opcode: `void'
/orss/gtvme/uboot/u-boot-1.1.1/include/mpc85xx.h:17:
Error: Unrecognized opcode: `uint'
/orss/gtvme/uboot/u-boot-1.1.1/include/mpc85xx.h:18:
Error: Unrecognized opcode: `int'
make: *** [cpu/mpc85xx/start.o] Error 1
I am using the ppc_8xx- tools from ELDK 3.1. I would
appreciate any help!
Thanks,
Jeff Stevens
__________________________________
Do you Yahoo!?
The all-new My Yahoo! - Get yours free!
http://my.yahoo.com
^ permalink raw reply
* [PATCH][PPC32] PPC4xx PIC rewrite/cleanup
From: Matt Porter @ 2004-11-23 16:13 UTC (permalink / raw)
To: akpm; +Cc: linux-kernel, linuxppc-embedded
Patch from Eugene to do some cleanup of the PPC4xx PIC code.
Separates the interrupts that can have polarity/triggering
modified for platform modification if necessary. Between
the two of us, it's tested on most of the affected platforms.
Signed-off-by: Eugene Surovegin <ebs@ebshome.net>
Signed-off-by: Matt Porter <mporter@kernel.crashing.org>
diff -Nru a/arch/ppc/platforms/4xx/ebony.c b/arch/ppc/platforms/4xx/ebony.c
--- a/arch/ppc/platforms/4xx/ebony.c 2004-11-10 23:39:19 -08:00
+++ b/arch/ppc/platforms/4xx/ebony.c 2004-11-10 23:39:19 -08:00
@@ -55,73 +55,22 @@
static struct ibm44x_clocks clocks __initdata;
/*
- * Ebony IRQ triggering/polarity settings
+ * Ebony external IRQ triggering/polarity settings
*/
-static u_char ebony_IRQ_initsenses[] __initdata = {
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 0: UART 0 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 1: UART 1 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 2: IIC 0 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 3: IIC 1 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 4: PCI Inb Mess */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 5: PCI Cmd Wrt */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 6: PCI PM */
- (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* 7: PCI MSI 0 */
- (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* 8: PCI MSI 1 */
- (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* 9: PCI MSI 2 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 10: MAL TX EOB */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 11: MAL RX EOB */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 12: DMA Chan 0 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 13: DMA Chan 1 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 14: DMA Chan 2 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 15: DMA Chan 3 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 16: Reserved */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 17: Reserved */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 18: GPT Timer 0 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 19: GPT Timer 1 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 20: GPT Timer 2 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 21: GPT Timer 3 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 22: GPT Timer 4 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 23: Ext Int 0 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 24: Ext Int 1 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 25: Ext Int 2 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 26: Ext Int 3 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 27: Ext Int 4 */
- (IRQ_SENSE_EDGE | IRQ_POLARITY_NEGATIVE), /* 28: Ext Int 5 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 29: Ext Int 6 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 30: UIC1 NC Int */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 31: UIC1 Crit Int */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 32: MAL SERR */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 33: MAL TXDE */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 34: MAL RXDE */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 35: ECC Unc Err */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 36: ECC Corr Err */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 37: Ext Bus Ctrl */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 38: Ext Bus Mstr */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 39: OPB->PLB */
- (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* 40: PCI MSI 3 */
- (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* 41: PCI MSI 4 */
- (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* 42: PCI MSI 5 */
- (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* 43: PCI MSI 6 */
- (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* 44: PCI MSI 7 */
- (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* 45: PCI MSI 8 */
- (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* 46: PCI MSI 9 */
- (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* 47: PCI MSI 10 */
- (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* 48: PCI MSI 11 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 49: PLB Perf Mon */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 50: Ext Int 7 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 51: Ext Int 8 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 52: Ext Int 9 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 53: Ext Int 10 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 54: Ext Int 11 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 55: Ext Int 12 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 56: Ser ROM Err */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 57: Reserved */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 58: Reserved */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 59: PCI Async Err */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 60: EMAC 0 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 61: EMAC 0 WOL */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 62: EMAC 1 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 63: EMAC 1 WOL */
+unsigned char ppc4xx_uic_ext_irq_cfg[] __initdata = {
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ0: PCI slot 0 */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ1: PCI slot 1 */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ2: PCI slot 2 */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ3: PCI slot 3 */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* IRQ4: IRDA */
+ (IRQ_SENSE_EDGE | IRQ_POLARITY_NEGATIVE), /* IRQ5: SMI pushbutton */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ6: PHYs */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* IRQ7: AUX */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ8: EXT */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ9: EXT */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ10: EXT */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ11: EXT */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* IRQ12: EXT */
};
static void __init
@@ -357,9 +306,6 @@
#endif
ebony_early_serial_map();
-
- ibm4xxPIC_InitSenses = ebony_IRQ_initsenses;
- ibm4xxPIC_NumInitSenses = sizeof(ebony_IRQ_initsenses);
/* Identify the system */
printk("IBM Ebony port (MontaVista Software, Inc. (source@mvista.com))\n");
diff -Nru a/arch/ppc/platforms/4xx/ibm405ep.c b/arch/ppc/platforms/4xx/ibm405ep.c
--- a/arch/ppc/platforms/4xx/ibm405ep.c 2004-11-10 23:39:19 -08:00
+++ b/arch/ppc/platforms/4xx/ibm405ep.c 2004-11-10 23:39:19 -08:00
@@ -21,6 +21,7 @@
#include <asm/ibm4xx.h>
#include <asm/ocp.h>
+#include <asm/ppc4xx_pic.h>
#include <platforms/4xx/ibm405ep.h>
@@ -130,5 +131,13 @@
.show = &ocp_show_emac_data
},
{ .vendor = OCP_VENDOR_INVALID
+ }
+};
+
+/* Polarity and triggering settings for internal interrupt sources */
+struct ppc4xx_uic_settings ppc4xx_core_uic_cfg[] __initdata = {
+ { .polarity = 0xffff7f80,
+ .triggering = 0x00000000,
+ .ext_irq_mask = 0x0000007f, /* IRQ0 - IRQ6 */
}
};
diff -Nru a/arch/ppc/platforms/4xx/ibm405gp.c b/arch/ppc/platforms/4xx/ibm405gp.c
--- a/arch/ppc/platforms/4xx/ibm405gp.c 2004-11-10 23:39:19 -08:00
+++ b/arch/ppc/platforms/4xx/ibm405gp.c 2004-11-10 23:39:19 -08:00
@@ -22,6 +22,7 @@
#include <platforms/4xx/ibm405gp.h>
#include <asm/ibm4xx.h>
#include <asm/ocp.h>
+#include <asm/ppc4xx_pic.h>
static struct ocp_func_emac_data ibm405gp_emac0_def = {
.rgmii_idx = -1, /* No RGMII */
@@ -107,5 +108,13 @@
.show = &ocp_show_emac_data,
},
{ .vendor = OCP_VENDOR_INVALID
+ }
+};
+
+/* Polarity and triggering settings for internal interrupt sources */
+struct ppc4xx_uic_settings ppc4xx_core_uic_cfg[] __initdata = {
+ { .polarity = 0xffffff80,
+ .triggering = 0x10000000,
+ .ext_irq_mask = 0x0000007f, /* IRQ0 - IRQ6 */
}
};
diff -Nru a/arch/ppc/platforms/4xx/ibm405gpr.c b/arch/ppc/platforms/4xx/ibm405gpr.c
--- a/arch/ppc/platforms/4xx/ibm405gpr.c 2004-11-10 23:39:19 -08:00
+++ b/arch/ppc/platforms/4xx/ibm405gpr.c 2004-11-10 23:39:19 -08:00
@@ -18,6 +18,7 @@
#include <platforms/4xx/ibm405gpr.h>
#include <asm/ibm4xx.h>
#include <asm/ocp.h>
+#include <asm/ppc4xx_pic.h>
static struct ocp_func_emac_data ibm405gpr_emac0_def = {
.rgmii_idx = -1, /* No RGMII */
@@ -104,5 +105,13 @@
.show = &ocp_show_emac_data,
},
{ .vendor = OCP_VENDOR_INVALID
+ }
+};
+
+/* Polarity and triggering settings for internal interrupt sources */
+struct ppc4xx_uic_settings ppc4xx_core_uic_cfg[] __initdata = {
+ { .polarity = 0xffffe000,
+ .triggering = 0x10000000,
+ .ext_irq_mask = 0x00001fff, /* IRQ7 - IRQ12, IRQ0 - IRQ6 */
}
};
diff -Nru a/arch/ppc/platforms/4xx/ibm440gp.c b/arch/ppc/platforms/4xx/ibm440gp.c
--- a/arch/ppc/platforms/4xx/ibm440gp.c 2004-11-10 23:39:19 -08:00
+++ b/arch/ppc/platforms/4xx/ibm440gp.c 2004-11-10 23:39:19 -08:00
@@ -19,6 +19,7 @@
#include <linux/module.h>
#include <platforms/4xx/ibm440gp.h>
#include <asm/ocp.h>
+#include <asm/ppc4xx_pic.h>
static struct ocp_func_emac_data ibm440gp_emac0_def = {
.rgmii_idx = -1, /* No RGMII */
@@ -148,4 +149,16 @@
},
{ .vendor = OCP_VENDOR_INVALID
}
+};
+
+/* Polarity and triggering settings for internal interrupt sources */
+struct ppc4xx_uic_settings ppc4xx_core_uic_cfg[] __initdata = {
+ { .polarity = 0xfffffe03,
+ .triggering = 0x01c00000,
+ .ext_irq_mask = 0x000001fc, /* IRQ0 - IRQ6 */
+ },
+ { .polarity = 0xffffc0ff,
+ .triggering = 0x00ff8000,
+ .ext_irq_mask = 0x00003f00, /* IRQ7 - IRQ12 */
+ },
};
diff -Nru a/arch/ppc/platforms/4xx/ibm440gx.c b/arch/ppc/platforms/4xx/ibm440gx.c
--- a/arch/ppc/platforms/4xx/ibm440gx.c 2004-11-10 23:39:19 -08:00
+++ b/arch/ppc/platforms/4xx/ibm440gx.c 2004-11-10 23:39:19 -08:00
@@ -19,6 +19,7 @@
#include <linux/module.h>
#include <platforms/4xx/ibm440gx.h>
#include <asm/ocp.h>
+#include <asm/ppc4xx_pic.h>
static struct ocp_func_emac_data ibm440gx_emac0_def = {
.rgmii_idx = -1, /* No RGMII */
@@ -214,4 +215,20 @@
},
{ .vendor = OCP_VENDOR_INVALID
}
+};
+
+/* Polarity and triggering settings for internal interrupt sources */
+struct ppc4xx_uic_settings ppc4xx_core_uic_cfg[] __initdata = {
+ { .polarity = 0xfffffe03,
+ .triggering = 0x01c00000,
+ .ext_irq_mask = 0x000001fc, /* IRQ0 - IRQ6 */
+ },
+ { .polarity = 0xffffc0ff,
+ .triggering = 0x00ff8000,
+ .ext_irq_mask = 0x00003f00, /* IRQ7 - IRQ12 */
+ },
+ { .polarity = 0xffff83ff,
+ .triggering = 0x000f83c0,
+ .ext_irq_mask = 0x00007c00, /* IRQ13 - IRQ17 */
+ },
};
diff -Nru a/arch/ppc/platforms/4xx/ibmnp405h.h b/arch/ppc/platforms/4xx/ibmnp405h.h
--- a/arch/ppc/platforms/4xx/ibmnp405h.h 2004-11-10 23:39:19 -08:00
+++ b/arch/ppc/platforms/4xx/ibmnp405h.h 2004-11-10 23:39:19 -08:00
@@ -132,8 +132,7 @@
#define DCRN_UIC1_BASE 0x0D0
#define DCRN_CPC0_EPRCSR 0x0F3
-#define UIC0_UIC1NC 30 /* UIC1 non-critical interrupt */
-#define UIC0_UIC1CR 31 /* UIC1 critical interrupt */
+#define UIC0_UIC1NC 0x00000002
#define CHR1_CETE 0x00000004 /* CPU external timer enable */
#define UIC0 DCRN_UIC0_BASE
@@ -141,7 +140,6 @@
#undef NR_UICS
#define NR_UICS 2
-#define UIC_CASCADE_MASK 0x0003 /* bits 30 & 31 */
/* EMAC DCRN's FIXME: armin */
#define DCRN_MALRXCTP2R(base) ((base) + 0x42) /* Channel Rx 2 Channel Table Pointer */
diff -Nru a/arch/ppc/platforms/4xx/ibmstbx25.c b/arch/ppc/platforms/4xx/ibmstbx25.c
--- a/arch/ppc/platforms/4xx/ibmstbx25.c 2004-11-10 23:39:19 -08:00
+++ b/arch/ppc/platforms/4xx/ibmstbx25.c 2004-11-10 23:39:19 -08:00
@@ -12,6 +12,7 @@
#include <linux/init.h>
#include <asm/ocp.h>
#include <platforms/4xx/ibmstbx25.h>
+#include <asm/ppc4xx_pic.h>
static struct ocp_func_iic_data ibmstbx25_iic0_def = {
.fast_mode = 0, /* Use standad mode (100Khz) */
@@ -55,5 +56,13 @@
.pm = IBM_CPM_GPIO0,
},
{ .vendor = OCP_VENDOR_INVALID
+ }
+};
+
+/* Polarity and triggering settings for internal interrupt sources */
+struct ppc4xx_uic_settings ppc4xx_core_uic_cfg[] __initdata = {
+ { .polarity = 0xffff8f80,
+ .triggering = 0x00000000,
+ .ext_irq_mask = 0x0000707f, /* IRQ7 - IRQ9, IRQ0 - IRQ6 */
}
};
diff -Nru a/arch/ppc/platforms/4xx/oak.c b/arch/ppc/platforms/4xx/oak.c
--- a/arch/ppc/platforms/4xx/oak.c 2004-11-10 23:39:19 -08:00
+++ b/arch/ppc/platforms/4xx/oak.c 2004-11-10 23:39:19 -08:00
@@ -101,8 +101,8 @@
ppc_md.setup_arch = oak_setup_arch;
ppc_md.show_percpuinfo = oak_show_percpuinfo;
ppc_md.irq_canonicalize = NULL;
- ppc_md.init_IRQ = oak_init_IRQ;
- ppc_md.get_irq = oak_get_irq;
+ ppc_md.init_IRQ = ppc4xx_pic_init;
+ ppc_md.get_irq = NULL; /* Set in ppc4xx_pic_init() */
ppc_md.init = NULL;
ppc_md.restart = oak_restart;
@@ -153,32 +153,6 @@
bp->bi_busfreq / 1000000);
return 0;
-}
-
-/*
- * Document me.
- */
-void __init
-oak_init_IRQ(void)
-{
- int i;
-
- ppc4xx_pic_init();
-
- for (i = 0; i < NR_IRQS; i++) {
- irq_desc[i].handler = ppc4xx_pic;
- }
-
- return;
-}
-
-/*
- * Document me.
- */
-int
-oak_get_irq(struct pt_regs *regs)
-{
- return (ppc4xx_pic_get_irq(regs));
}
/*
diff -Nru a/arch/ppc/platforms/4xx/ocotea.c b/arch/ppc/platforms/4xx/ocotea.c
--- a/arch/ppc/platforms/4xx/ocotea.c 2004-11-10 23:39:19 -08:00
+++ b/arch/ppc/platforms/4xx/ocotea.c 2004-11-10 23:39:19 -08:00
@@ -347,12 +347,6 @@
ibm440gx_get_clocks(&clocks, 33333333, 6 * 1843200);
ocp_sys_info.opb_bus_freq = clocks.opb;
- /* XXX Fix L2C IRQ triggerring setting (edge-sensitive).
- * Firmware (at least PIBS v1.72 OCT/28/2003) sets it incorrectly
- * --ebs
- */
- mtdcr(DCRN_UIC_TR(UIC2), mfdcr(DCRN_UIC_TR(UIC2)) | 0x00000100);
-
ibm44x_platform_init();
ppc_md.setup_arch = ocotea_setup_arch;
diff -Nru a/arch/ppc/platforms/4xx/redwood6.c b/arch/ppc/platforms/4xx/redwood6.c
--- a/arch/ppc/platforms/4xx/redwood6.c 2004-11-10 23:39:19 -08:00
+++ b/arch/ppc/platforms/4xx/redwood6.c 2004-11-10 23:39:19 -08:00
@@ -19,44 +19,20 @@
#include <linux/delay.h>
#include <asm/machdep.h>
-
/*
- * Define all of the IRQ senses and polarities.
+ * Define external IRQ senses and polarities.
*/
-
-static u_char redwood6_IRQ_initsenses[] __initdata = {
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 0: RTC/FPC */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 1: Transport */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 2: Audio Dec */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 3: Video Dec */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 4: DMA Chan 0 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 5: DMA Chan 1 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 6: DMA Chan 2 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 7: DMA Chan 3 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 8: SmartCard 0 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 9: IIC0 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 10: IRR */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 11: Cap Timers */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 12: Cmp Timers */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 13: Serial Port */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 14: Soft Modem */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 15: Down Ctrs */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 16: SmartCard 1 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 17: Ext Int 7 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 18: Ext Int 8 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 19: Ext Int 9 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 20: Serial 0 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 21: Serial 1 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 22: Serial 2 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 23: XPT_DMA */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 24: DCR timeout */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 25: Ext Int 0 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 26: Ext Int 1 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 27: Ext Int 2 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 28: Ext Int 3 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 29: Ext Int 4 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 30: Ext Int 5 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 31: Ext Int 6 */
+unsigned char ppc4xx_uic_ext_irq_cfg[] __initdata = {
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 7 */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 8 */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 9 */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 0 */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 1 */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 2 */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 3 */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 4 */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 5 */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 6 */
};
static struct resource smc91x_resources[] = {
@@ -144,8 +120,6 @@
printk("\n");
#endif
- ibm4xxPIC_InitSenses = redwood6_IRQ_initsenses;
- ibm4xxPIC_NumInitSenses = sizeof(redwood6_IRQ_initsenses);
/* Identify the system */
printk(KERN_INFO "IBM Redwood6 (STBx25XX) Platform\n");
diff -Nru a/arch/ppc/platforms/4xx/sycamore.c b/arch/ppc/platforms/4xx/sycamore.c
--- a/arch/ppc/platforms/4xx/sycamore.c 2004-11-10 23:39:19 -08:00
+++ b/arch/ppc/platforms/4xx/sycamore.c 2004-11-10 23:39:19 -08:00
@@ -44,42 +44,22 @@
void *sycamore_rtc_base;
/*
- * Define all of the IRQ senses and polarities.
+ * Define external IRQ senses and polarities.
*/
-
-static u_char Sycamore_IRQ_initsenses[] __initdata = {
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 0: Uart 0*/
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 1: Uart 1*/
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 2: IIC */
- (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* 3: External Master */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 4: PCI ext cmd write*/
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 5: DMA Chan 0 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 6: DMA Chan 1 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 7: DMA Chan 2 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 8: DMA Chan 3 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 9: Ethernet wakeup (WOL)*/
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 10: Mal (SEER) */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 11: Mal TXEOB */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 12: Mal RXEOB */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 13: Mal TXDE*/
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 14: Mal RXDE*/
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 15: Ethernet */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 16: Ext PCI SERR */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 17: ECC */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* 18: PCI PM*/
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 19: Ext Int 7 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 20: Ext Int 8 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 21: Ext Int 9 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 22: Ext Int 10 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 23: Ext Int 11 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 24: Ext Int 12 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 25: Ext Int 0 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 26: Ext Int 1 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 27: Ext Int 2 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 28: Ext Int 3 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 29: Ext Int 4 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 30: Ext Int 5 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 31: Ext Int 6 */
+unsigned char ppc4xx_uic_ext_irq_cfg[] __initdata = {
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 7 */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 8 */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 9 */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 10 */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 11 */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 12 */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 0 */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 1 */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 2 */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 3 */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 4 */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 5 */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 6 */
};
@@ -158,8 +138,6 @@
sycamore_rtc_base = (void *) SYCAMORE_RTC_VADDR;
TODC_INIT(TODC_TYPE_DS1743, sycamore_rtc_base, sycamore_rtc_base,
sycamore_rtc_base, 8);
- ibm4xxPIC_InitSenses = Sycamore_IRQ_initsenses;
- ibm4xxPIC_NumInitSenses = sizeof(Sycamore_IRQ_initsenses);
/* Identify the system */
printk(KERN_INFO "IBM Sycamore (IBM405GPr) Platform\n");
diff -Nru a/arch/ppc/syslib/Makefile b/arch/ppc/syslib/Makefile
--- a/arch/ppc/syslib/Makefile 2004-11-10 23:39:19 -08:00
+++ b/arch/ppc/syslib/Makefile 2004-11-10 23:39:19 -08:00
@@ -17,7 +17,11 @@
ifeq ($(CONFIG_VIRTEX_II_PRO),y)
obj-$(CONFIG_40x) += xilinx_pic.o
else
+ifeq ($(CONFIG_403),y)
+obj-$(CONFIG_40x) += ppc403_pic.o
+else
obj-$(CONFIG_40x) += ppc4xx_pic.o
+endif
endif
obj-$(CONFIG_44x) += ppc4xx_pic.o
obj-$(CONFIG_40x) += ppc4xx_setup.o
diff -Nru a/arch/ppc/syslib/ibm44x_common.c b/arch/ppc/syslib/ibm44x_common.c
--- a/arch/ppc/syslib/ibm44x_common.c 2004-11-10 23:39:19 -08:00
+++ b/arch/ppc/syslib/ibm44x_common.c 2004-11-10 23:39:19 -08:00
@@ -142,19 +142,9 @@
return mem_size;
}
-static void __init ibm44x_init_irq(void)
-{
- int i;
-
- ppc4xx_pic_init();
-
- for (i = 0; i < NR_IRQS; i++)
- irq_desc[i].handler = ppc4xx_pic;
-}
-
void __init ibm44x_platform_init(void)
{
- ppc_md.init_IRQ = ibm44x_init_irq;
+ ppc_md.init_IRQ = ppc4xx_pic_init;
ppc_md.find_end_of_memory = ibm44x_find_end_of_memory;
ppc_md.restart = ibm44x_restart;
ppc_md.power_off = ibm44x_power_off;
diff -Nru a/arch/ppc/syslib/ppc403_pic.c b/arch/ppc/syslib/ppc403_pic.c
--- /dev/null Wed Dec 31 16:00:00 196900
+++ b/arch/ppc/syslib/ppc403_pic.c 2004-11-10 23:39:19 -08:00
@@ -0,0 +1,127 @@
+/*
+ *
+ * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
+ *
+ * Module name: ppc403_pic.c
+ *
+ * Description:
+ * Interrupt controller driver for PowerPC 403-based processors.
+ */
+
+/*
+ * The PowerPC 403 cores' Asynchronous Interrupt Controller (AIC) has
+ * 32 possible interrupts, a majority of which are not implemented on
+ * all cores. There are six configurable, external interrupt pins and
+ * there are eight internal interrupts for the on-chip serial port
+ * (SPU), DMA controller, and JTAG controller.
+ *
+ */
+
+#include <linux/init.h>
+#include <linux/sched.h>
+#include <linux/signal.h>
+#include <linux/stddef.h>
+
+#include <asm/processor.h>
+#include <asm/system.h>
+#include <asm/irq.h>
+#include <asm/ppc4xx_pic.h>
+
+/* Function Prototypes */
+
+static void ppc403_aic_enable(unsigned int irq);
+static void ppc403_aic_disable(unsigned int irq);
+static void ppc403_aic_disable_and_ack(unsigned int irq);
+
+static struct hw_interrupt_type ppc403_aic = {
+ "403GC AIC",
+ NULL,
+ NULL,
+ ppc403_aic_enable,
+ ppc403_aic_disable,
+ ppc403_aic_disable_and_ack,
+ 0
+};
+
+int
+ppc403_pic_get_irq(struct pt_regs *regs)
+{
+ int irq;
+ unsigned long bits;
+
+ /*
+ * Only report the status of those interrupts that are actually
+ * enabled.
+ */
+
+ bits = mfdcr(DCRN_EXISR) & mfdcr(DCRN_EXIER);
+
+ /*
+ * Walk through the interrupts from highest priority to lowest, and
+ * report the first pending interrupt found.
+ * We want PPC, not C bit numbering, so just subtract the ffs()
+ * result from 32.
+ */
+ irq = 32 - ffs(bits);
+
+ if (irq == NR_AIC_IRQS)
+ irq = -1;
+
+ return (irq);
+}
+
+static void
+ppc403_aic_enable(unsigned int irq)
+{
+ int bit, word;
+
+ bit = irq & 0x1f;
+ word = irq >> 5;
+
+ ppc_cached_irq_mask[word] |= (1 << (31 - bit));
+ mtdcr(DCRN_EXIER, ppc_cached_irq_mask[word]);
+}
+
+static void
+ppc403_aic_disable(unsigned int irq)
+{
+ int bit, word;
+
+ bit = irq & 0x1f;
+ word = irq >> 5;
+
+ ppc_cached_irq_mask[word] &= ~(1 << (31 - bit));
+ mtdcr(DCRN_EXIER, ppc_cached_irq_mask[word]);
+}
+
+static void
+ppc403_aic_disable_and_ack(unsigned int irq)
+{
+ int bit, word;
+
+ bit = irq & 0x1f;
+ word = irq >> 5;
+
+ ppc_cached_irq_mask[word] &= ~(1 << (31 - bit));
+ mtdcr(DCRN_EXIER, ppc_cached_irq_mask[word]);
+ mtdcr(DCRN_EXISR, (1 << (31 - bit)));
+}
+
+void __init
+ppc4xx_pic_init(void)
+{
+ int i;
+
+ /*
+ * Disable all external interrupts until they are
+ * explicity requested.
+ */
+ ppc_cached_irq_mask[0] = 0;
+
+ mtdcr(DCRN_EXIER, ppc_cached_irq_mask[0]);
+
+ ppc_md.get_irq = ppc403_pic_get_irq;
+
+ for (i = 0; i < NR_IRQS; i++)
+ irq_desc[i].handler = &ppc403_aic;
+}
diff -Nru a/arch/ppc/syslib/ppc4xx_pic.c b/arch/ppc/syslib/ppc4xx_pic.c
--- a/arch/ppc/syslib/ppc4xx_pic.c 2004-11-10 23:39:19 -08:00
+++ b/arch/ppc/syslib/ppc4xx_pic.c 2004-11-10 23:39:19 -08:00
@@ -1,31 +1,21 @@
/*
+ * arch/ppc/syslib/ppc4xx_pic.c
*
- * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
- *
- * Module name: ppc4xx_pic.c
- *
- * Description:
- * Interrupt controller driver for PowerPC 4xx-based processors.
- */
-
-/*
- * The PowerPC 403 cores' Asynchronous Interrupt Controller (AIC) has
- * 32 possible interrupts, a majority of which are not implemented on
- * all cores. There are six configurable, external interrupt pins and
- * there are eight internal interrupts for the on-chip serial port
- * (SPU), DMA controller, and JTAG controller.
+ * Interrupt controller driver for PowerPC 4xx-based processors.
*
- * The PowerPC 405/440 cores' Universal Interrupt Controller (UIC) has
- * 32 possible interrupts as well. Depending on the core and SoC
- * implementation, a portion of the interrrupts are used for on-chip
- * peripherals and a portion of the interrupts are available to be
- * configured for external devices generating interrupts.
+ * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
+ * Copyright (c) 2004 Zultys Technologies
*
- * The PowerNP and 440GP (and most likely future implementations) have
- * cascaded UICs.
+ * Based on original code by
+ * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
+ * Armin Custer <akuster@mvista.com>
*
- */
-
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+*/
+#include <linux/config.h>
#include <linux/init.h>
#include <linux/sched.h>
#include <linux/signal.h>
@@ -36,493 +26,212 @@
#include <asm/irq.h>
#include <asm/ppc4xx_pic.h>
-/* Global Variables */
-struct hw_interrupt_type *ppc4xx_pic;
-/*
- * We define 4xxIRQ_InitSenses table thusly:
- * bit 0x1: sense, 1 for edge and 0 for level.
- * bit 0x2: polarity, 0 for negative, 1 for positive.
+/* See comment in include/arch-ppc/ppc4xx_pic.h
+ * for more info about these two variables
*/
-unsigned int ibm4xxPIC_NumInitSenses __initdata = 0;
-unsigned char *ibm4xxPIC_InitSenses __initdata = NULL;
-
-/* Six of one, half dozen of the other....#ifdefs, separate files,
- * other tricks.....
- *
- * There are basically two types of interrupt controllers, the 403 AIC
- * and the "others" with UIC. I just kept them both here separated
- * with #ifdefs, but it seems to change depending upon how supporting
- * files (like ppc4xx.h) change. -- Dan.
- */
-
-#ifdef CONFIG_403
-
-/* Function Prototypes */
-
-static void ppc403_aic_enable(unsigned int irq);
-static void ppc403_aic_disable(unsigned int irq);
-static void ppc403_aic_disable_and_ack(unsigned int irq);
-
-static struct hw_interrupt_type ppc403_aic = {
- "403GC AIC",
- NULL,
- NULL,
- ppc403_aic_enable,
- ppc403_aic_disable,
- ppc403_aic_disable_and_ack,
- 0
-};
+extern struct ppc4xx_uic_settings ppc4xx_core_uic_cfg[NR_UICS] __attribute__((weak));
+extern unsigned char ppc4xx_uic_ext_irq_cfg[] __attribute__((weak));
-int
-ppc403_pic_get_irq(struct pt_regs *regs)
-{
- int irq;
- unsigned long bits;
-
- /*
- * Only report the status of those interrupts that are actually
- * enabled.
- */
-
- bits = mfdcr(DCRN_EXISR) & mfdcr(DCRN_EXIER);
-
- /*
- * Walk through the interrupts from highest priority to lowest, and
- * report the first pending interrupt found.
- * We want PPC, not C bit numbering, so just subtract the ffs()
- * result from 32.
- */
- irq = 32 - ffs(bits);
-
- if (irq == NR_AIC_IRQS)
- irq = -1;
-
- return (irq);
+#define IRQ_MASK_UIC0(irq) (1 << (31 - (irq)))
+#define IRQ_MASK_UICx(irq) (1 << (31 - ((irq) & 0x1f)))
+#define IRQ_MASK_UIC1(irq) IRQ_MASK_UICx(irq)
+#define IRQ_MASK_UIC2(irq) IRQ_MASK_UICx(irq)
+
+#define UIC_HANDLERS(n) \
+static void ppc4xx_uic##n##_enable(unsigned int irq) \
+{ \
+ ppc_cached_irq_mask[n] |= IRQ_MASK_UIC##n(irq); \
+ mtdcr(DCRN_UIC_ER(UIC##n), ppc_cached_irq_mask[n]); \
+} \
+ \
+static void ppc4xx_uic##n##_disable(unsigned int irq) \
+{ \
+ ppc_cached_irq_mask[n] &= ~IRQ_MASK_UIC##n(irq); \
+ mtdcr(DCRN_UIC_ER(UIC##n), ppc_cached_irq_mask[n]); \
+} \
+ \
+static void ppc4xx_uic##n##_ack(unsigned int irq) \
+{ \
+ u32 mask = IRQ_MASK_UIC##n(irq); \
+ ppc_cached_irq_mask[n] &= ~mask; \
+ mtdcr(DCRN_UIC_ER(UIC##n), ppc_cached_irq_mask[n]); \
+ mtdcr(DCRN_UIC_SR(UIC##n), mask); \
+ ACK_UIC##n##_PARENT \
+} \
+ \
+static void ppc4xx_uic##n##_end(unsigned int irq) \
+{ \
+ unsigned int status = irq_desc[irq].status; \
+ u32 mask = IRQ_MASK_UIC##n(irq); \
+ if (status & IRQ_LEVEL){ \
+ mtdcr(DCRN_UIC_SR(UIC##n), mask); \
+ ACK_UIC##n##_PARENT \
+ } \
+ if (!(status & (IRQ_DISABLED | IRQ_INPROGRESS))){ \
+ ppc_cached_irq_mask[n] |= mask; \
+ mtdcr(DCRN_UIC_ER(UIC##n), ppc_cached_irq_mask[n]); \
+ } \
+}
+
+#define DECLARE_UIC(n) \
+{ \
+ .typename = "UIC"#n, \
+ .enable = ppc4xx_uic##n##_enable, \
+ .disable = ppc4xx_uic##n##_disable, \
+ .ack = ppc4xx_uic##n##_ack, \
+ .end = ppc4xx_uic##n##_end, \
+} \
+
+#if NR_UICS == 3
+#define ACK_UIC0_PARENT mtdcr(DCRN_UIC_SR(UICB), UICB_UIC0NC);
+#define ACK_UIC1_PARENT mtdcr(DCRN_UIC_SR(UICB), UICB_UIC1NC);
+#define ACK_UIC2_PARENT mtdcr(DCRN_UIC_SR(UICB), UICB_UIC2NC);
+UIC_HANDLERS(0); UIC_HANDLERS(1); UIC_HANDLERS(2);
+
+static int ppc4xx_pic_get_irq(struct pt_regs *regs)
+{
+ u32 uicb = mfdcr(DCRN_UIC_MSR(UICB));
+ if (uicb & UICB_UIC0NC)
+ return 32 - ffs(mfdcr(DCRN_UIC_MSR(UIC0)));
+ else if (uicb & UICB_UIC1NC)
+ return 64 - ffs(mfdcr(DCRN_UIC_MSR(UIC1)));
+ else if (uicb & UICB_UIC2NC)
+ return 96 - ffs(mfdcr(DCRN_UIC_MSR(UIC2)));
+ else
+ return -1;
}
-static void
-ppc403_aic_enable(unsigned int irq)
+static void __init ppc4xx_pic_impl_init(void)
{
- int bit, word;
-
- bit = irq & 0x1f;
- word = irq >> 5;
-
- ppc_cached_irq_mask[word] |= (1 << (31 - bit));
- mtdcr(DCRN_EXIER, ppc_cached_irq_mask[word]);
+ /* Configure Base UIC */
+ mtdcr(DCRN_UIC_CR(UICB), 0);
+ mtdcr(DCRN_UIC_TR(UICB), 0);
+ mtdcr(DCRN_UIC_PR(UICB), 0xffffffff);
+ mtdcr(DCRN_UIC_SR(UICB), 0xffffffff);
+ mtdcr(DCRN_UIC_ER(UICB), UICB_UIC0NC | UICB_UIC1NC | UICB_UIC2NC);
}
-static void
-ppc403_aic_disable(unsigned int irq)
-{
- int bit, word;
-
- bit = irq & 0x1f;
- word = irq >> 5;
-
- ppc_cached_irq_mask[word] &= ~(1 << (31 - bit));
- mtdcr(DCRN_EXIER, ppc_cached_irq_mask[word]);
-}
+#elif NR_UICS == 2
+#define ACK_UIC0_PARENT
+#define ACK_UIC1_PARENT mtdcr(DCRN_UIC_SR(UIC0), UIC0_UIC1NC);
+UIC_HANDLERS(0); UIC_HANDLERS(1);
-static void
-ppc403_aic_disable_and_ack(unsigned int irq)
+static int ppc4xx_pic_get_irq(struct pt_regs *regs)
{
- int bit, word;
-
- bit = irq & 0x1f;
- word = irq >> 5;
-
- ppc_cached_irq_mask[word] &= ~(1 << (31 - bit));
- mtdcr(DCRN_EXIER, ppc_cached_irq_mask[word]);
- mtdcr(DCRN_EXISR, (1 << (31 - bit)));
+ u32 uic0 = mfdcr(DCRN_UIC_MSR(UIC0));
+ if (uic0 & UIC0_UIC1NC)
+ return 64 - ffs(mfdcr(DCRN_UIC_MSR(UIC1)));
+ else
+ return uic0 ? 32 - ffs(uic0) : -1;
}
-#else
-
-#ifndef UIC1
-#define UIC1 UIC0
-#endif
-#ifndef UIC2
-#define UIC2 UIC1
-#endif
-
-static void
-ppc4xx_uic_enable(unsigned int irq)
+static void __init ppc4xx_pic_impl_init(void)
{
- int bit, word;
- irq_desc_t *desc = irq_desc + irq;
-
- bit = irq & 0x1f;
- word = irq >> 5;
-
-#ifdef UIC_DEBUG
- printk("ppc4xx_uic_enable - irq %d word %d bit 0x%x\n", irq, word, bit);
-#endif
- ppc_cached_irq_mask[word] |= 1 << (31 - bit);
- switch (word) {
- case 0:
- mtdcr(DCRN_UIC_ER(UIC0), ppc_cached_irq_mask[word]);
- if ((mfdcr(DCRN_UIC_TR(UIC0)) & (1 << (31 - bit))) == 0)
- desc->status |= IRQ_LEVEL;
- else
- desc->status = desc->status & ~IRQ_LEVEL;
- break;
- case 1:
- mtdcr(DCRN_UIC_ER(UIC1), ppc_cached_irq_mask[word]);
- if ((mfdcr(DCRN_UIC_TR(UIC1)) & (1 << (31 - bit))) == 0)
- desc->status |= IRQ_LEVEL;
- else
- desc->status = desc->status & ~IRQ_LEVEL;
- break;
- case 2:
- mtdcr(DCRN_UIC_ER(UIC2), ppc_cached_irq_mask[word]);
- if ((mfdcr(DCRN_UIC_TR(UIC2)) & (1 << (31 - bit))) == 0)
- desc->status |= IRQ_LEVEL;
- else
- desc->status = desc->status & ~IRQ_LEVEL;
- break;
- }
-
+ /* Enable cascade interrupt in UIC0 */
+ ppc_cached_irq_mask[0] |= UIC0_UIC1NC;
+ mtdcr(DCRN_UIC_SR(UIC0), UIC0_UIC1NC);
+ mtdcr(DCRN_UIC_ER(UIC0), ppc_cached_irq_mask[0]);
}
-static void
-ppc4xx_uic_disable(unsigned int irq)
-{
- int bit, word;
+#elif NR_UICS == 1
+#define ACK_UIC0_PARENT
+UIC_HANDLERS(0);
- bit = irq & 0x1f;
- word = irq >> 5;
-#ifdef UIC_DEBUG
- printk("ppc4xx_uic_disable - irq %d word %d bit 0x%x\n", irq, word,
- bit);
-#endif
- ppc_cached_irq_mask[word] &= ~(1 << (31 - bit));
- switch (word) {
- case 0:
- mtdcr(DCRN_UIC_ER(UIC0), ppc_cached_irq_mask[word]);
- break;
- case 1:
- mtdcr(DCRN_UIC_ER(UIC1), ppc_cached_irq_mask[word]);
- break;
- case 2:
- mtdcr(DCRN_UIC_ER(UIC2), ppc_cached_irq_mask[word]);
- break;
- }
-}
-
-static void
-ppc4xx_uic_disable_and_ack(unsigned int irq)
+static int ppc4xx_pic_get_irq(struct pt_regs *regs)
{
- int bit, word;
-
- bit = irq & 0x1f;
- word = irq >> 5;
-
-#ifdef UIC_DEBUG
- printk("ppc4xx_uic_disable_and_ack - irq %d word %d bit 0x%x\n", irq,
- word, bit);
-#endif
- ppc_cached_irq_mask[word] &= ~(1 << (31 - bit));
- switch (word) {
- case 0:
- mtdcr(DCRN_UIC_ER(UIC0), ppc_cached_irq_mask[word]);
- mtdcr(DCRN_UIC_SR(UIC0), (1 << (31 - bit)));
-#if (NR_UICS > 2)
- mtdcr(DCRN_UIC_SR(UICB), UICB_UIC0NC);
-#endif
- break;
- case 1:
- mtdcr(DCRN_UIC_ER(UIC1), ppc_cached_irq_mask[word]);
- mtdcr(DCRN_UIC_SR(UIC1), (1 << (31 - bit)));
-#if (NR_UICS == 2)
- mtdcr(DCRN_UIC_SR(UIC0), (1 << (31 - UIC0_UIC1NC)));
-#endif
-#if (NR_UICS > 2)
- mtdcr(DCRN_UIC_SR(UICB), UICB_UIC1NC);
-#endif
- break;
- case 2:
- mtdcr(DCRN_UIC_ER(UIC2), ppc_cached_irq_mask[word]);
- mtdcr(DCRN_UIC_SR(UIC2), (1 << (31 - bit)));
-#if (NR_UICS > 2)
- mtdcr(DCRN_UIC_SR(UICB), UICB_UIC2NC);
-#endif
- break;
- }
-
+ u32 uic0 = mfdcr(DCRN_UIC_MSR(UIC0));
+ return uic0 ? 32 - ffs(uic0) : -1;
}
-static void
-ppc4xx_uic_end(unsigned int irq)
-{
- int bit, word;
- unsigned int tr_bits = 0;
-
- bit = irq & 0x1f;
- word = irq >> 5;
-
-#ifdef UIC_DEBUG
- printk("ppc4xx_uic_end - irq %d word %d bit 0x%x\n", irq, word, bit);
+static inline void ppc4xx_pic_impl_init(void){}
#endif
- switch (word) {
- case 0:
- tr_bits = mfdcr(DCRN_UIC_TR(UIC0));
- break;
- case 1:
- tr_bits = mfdcr(DCRN_UIC_TR(UIC1));
- break;
- case 2:
- tr_bits = mfdcr(DCRN_UIC_TR(UIC2));
- break;
- }
-
- if ((tr_bits & (1 << (31 - bit))) == 0) {
- /* level trigger */
- switch (word) {
- case 0:
- mtdcr(DCRN_UIC_SR(UIC0), 1 << (31 - bit));
-#if (NR_UICS > 2)
- mtdcr(DCRN_UIC_SR(UICB), UICB_UIC0NC);
-#endif
- break;
- case 1:
- mtdcr(DCRN_UIC_SR(UIC1), 1 << (31 - bit));
-#if (NR_UICS == 2)
- mtdcr(DCRN_UIC_SR(UIC0), (1 << (31 - UIC0_UIC1NC)));
-#endif
-#if (NR_UICS > 2)
- mtdcr(DCRN_UIC_SR(UICB), UICB_UIC1NC);
-#endif
- break;
- case 2:
- mtdcr(DCRN_UIC_SR(UIC2), 1 << (31 - bit));
-#if (NR_UICS > 2)
- mtdcr(DCRN_UIC_SR(UICB), UICB_UIC2NC);
+static struct ppc4xx_uic_impl {
+ struct hw_interrupt_type decl;
+ int base; /* Base DCR number */
+} __uic[] = {
+ { .decl = DECLARE_UIC(0), .base = UIC0 },
+#if NR_UICS > 1
+ { .decl = DECLARE_UIC(1), .base = UIC1 },
+#if NR_UICS > 2
+ { .decl = DECLARE_UIC(2), .base = UIC2 },
#endif
- break;
- }
- }
-
- if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
- ppc_cached_irq_mask[word] |= 1 << (31 - bit);
- switch (word) {
- case 0:
- mtdcr(DCRN_UIC_ER(UIC0), ppc_cached_irq_mask[word]);
- break;
- case 1:
- mtdcr(DCRN_UIC_ER(UIC1), ppc_cached_irq_mask[word]);
- break;
- case 2:
- mtdcr(DCRN_UIC_ER(UIC2), ppc_cached_irq_mask[word]);
- break;
- }
- }
-}
-
-static struct hw_interrupt_type ppc4xx_uic = {
-#if (NR_UICS == 1)
- "IBM UIC",
-#else
- "IBM UIC Cascade",
#endif
- NULL,
- NULL,
- ppc4xx_uic_enable,
- ppc4xx_uic_disable,
- ppc4xx_uic_disable_and_ack,
- ppc4xx_uic_end,
- 0
};
-int
-ppc4xx_pic_get_irq(struct pt_regs *regs)
+static inline int is_level_sensitive(int irq)
{
- int irq, cas_irq;
- unsigned long bits;
- cas_irq = 0;
- /*
- * Only report the status of those interrupts that are actually
- * enabled.
- */
-
-#if (NR_UICS > 2)
- bits = mfdcr(DCRN_UIC_MSR(UICB));
-#else
- bits = mfdcr(DCRN_UIC_MSR(UIC0));
-#endif
-#if (NR_UICS > 2)
- if (bits & UICB_UIC0NC) {
- bits = mfdcr(DCRN_UIC_MSR(UIC0));
- irq = 32 - ffs(bits);
- } else if (bits & UICB_UIC1NC) {
- bits = mfdcr(DCRN_UIC_MSR(UIC1));
- irq = 64 - ffs(bits);
- } else if (bits & UICB_UIC2NC) {
- bits = mfdcr(DCRN_UIC_MSR(UIC2));
- irq = 96 - ffs(bits);
- } else {
- irq = -1;
- }
-#elif (NR_UICS > 1)
- if (bits & UIC_CASCADE_MASK) {
- bits = mfdcr(DCRN_UIC_MSR(UIC1));
- cas_irq = 32 - ffs(bits);
- irq = 32 + cas_irq;
- } else {
- irq = 32 - ffs(bits);
- if (irq == 32)
- irq = -1;
- }
-#else
- /*
- * Walk through the interrupts from highest priority to lowest, and
- * report the first pending interrupt found.
- * We want PPC, not C bit numbering, so just subtract the ffs()
- * result from 32.
- */
- irq = 32 - ffs(bits);
-#endif
- if (irq == (NR_UIC_IRQS * NR_UICS))
- irq = -1;
-
-#ifdef UIC_DEBUG
- printk("ppc4xx_pic_get_irq - irq %d bit 0x%x\n", irq, bits);
-#endif
-
- return (irq);
+ u32 tr = mfdcr(DCRN_UIC_TR(__uic[irq >> 5].base));
+ return (tr & IRQ_MASK_UICx(irq)) == 0;
}
-#endif
-void __init
-ppc4xx_extpic_init(void)
+void __init ppc4xx_pic_init(void)
{
- /* set polarity
- * 1 = default/pos/rising , 0= neg/falling internal
- * 1 = neg/falling , 0= pos/rising external
- * Sense
- * 0 = default level internal
- * 0 = level, 1 = edge external
- */
-
- unsigned int sense, irq;
- int bit, word;
- unsigned long ppc_cached_sense_mask[NR_MASK_WORDS];
- unsigned long ppc_cached_pol_mask[NR_MASK_WORDS];
- ppc_cached_sense_mask[0] = 0;
- ppc_cached_sense_mask[1] = 0;
- ppc_cached_sense_mask[2] = 0;
- ppc_cached_pol_mask[0] = 0;
- ppc_cached_pol_mask[1] = 0;
- ppc_cached_pol_mask[2] = 0;
-
- for (irq = 0; irq < NR_IRQS; irq++) {
-
- bit = irq & 0x1f;
- word = irq >> 5;
-
- sense =
- (irq <
- ibm4xxPIC_NumInitSenses) ? ibm4xxPIC_InitSenses[irq] : 3;
-#ifdef PPC4xx_PIC_DEBUG
- printk("PPC4xx_picext %d word:%x bit:%x sense:%x", irq, word,
- bit, sense);
-#endif
- ppc_cached_sense_mask[word] |=
- (~sense & IRQ_SENSE_MASK) << (31 - bit);
- ppc_cached_pol_mask[word] |=
- ((sense & IRQ_POLARITY_MASK) >> 1) << (31 - bit);
- switch (word) {
- case 0:
-#ifdef PPC4xx_PIC_DEBUG
- printk("Pol %x ", mfdcr(DCRN_UIC_PR(UIC0)));
- printk("Level %x\n", mfdcr(DCRN_UIC_TR(UIC0)));
-#endif
- /* polarity setting */
- mtdcr(DCRN_UIC_PR(UIC0), ppc_cached_pol_mask[word]);
-
- /* Level setting */
- mtdcr(DCRN_UIC_TR(UIC0), ppc_cached_sense_mask[word]);
-
- break;
- case 1:
-#ifdef PPC4xx_PIC_DEBUG
- printk("Pol %x ", mfdcr(DCRN_UIC_PR(UIC1)));
- printk("Level %x\n", mfdcr(DCRN_UIC_TR(UIC1)));
-#endif
- /* polarity setting */
- mtdcr(DCRN_UIC_PR(UIC1), ppc_cached_pol_mask[word]);
-
- /* Level setting */
- mtdcr(DCRN_UIC_TR(UIC1), ppc_cached_sense_mask[word]);
-
- break;
- case 2:
-#ifdef PPC4xx_PIC_DEBUG
- printk("Pol %x ", mfdcr(DCRN_UIC_PR(UIC2)));
- printk("Level %x\n", mfdcr(DCRN_UIC_TR(UIC2)));
-#endif
- /* polarity setting */
- mtdcr(DCRN_UIC_PR(UIC2), ppc_cached_pol_mask[word]);
-
- /* Level setting */
- mtdcr(DCRN_UIC_TR(UIC2), ppc_cached_sense_mask[word]);
-
- break;
+ int i;
+ unsigned char* eirqs = ppc4xx_uic_ext_irq_cfg;
+
+ for (i = 0; i < NR_UICS; ++i){
+ int base = __uic[i].base;
+
+ /* Disable everything by default */
+ ppc_cached_irq_mask[i] = 0;
+ mtdcr(DCRN_UIC_ER(base), 0);
+
+ /* We don't use critical interrupts */
+ mtdcr(DCRN_UIC_CR(base), 0);
+
+ /* Configure polarity and triggering */
+ if (ppc4xx_core_uic_cfg){
+ struct ppc4xx_uic_settings* p = ppc4xx_core_uic_cfg + i;
+ u32 mask = p->ext_irq_mask;
+ u32 pr = mfdcr(DCRN_UIC_PR(base)) & mask;
+ u32 tr = mfdcr(DCRN_UIC_TR(base)) & mask;
+
+ /* "Fixed" interrupts (on-chip devices) */
+ pr |= p->polarity & ~mask;
+ tr |= p->triggering & ~mask;
+
+ /* Merge external IRQs settings if board port
+ * provided them
+ */
+ if (eirqs && mask){
+ pr &= ~mask;
+ tr &= ~mask;
+ while (mask){
+ /* Extract current external IRQ mask */
+ u32 eirq_mask = 1 << __ilog2(mask);
+
+ if (!(*eirqs & IRQ_SENSE_LEVEL))
+ tr |= eirq_mask;
+
+ if (*eirqs & IRQ_POLARITY_POSITIVE)
+ pr |= eirq_mask;
+
+ mask &= ~eirq_mask;
+ ++eirqs;
+ }
+ }
+ mtdcr(DCRN_UIC_PR(base), pr);
+ mtdcr(DCRN_UIC_TR(base), tr);
}
- }
-
-}
-void __init
-ppc4xx_pic_init(void)
-{
- /*
- * Disable all external interrupts until they are
- * explicity requested.
- */
- ppc_cached_irq_mask[0] = 0;
- ppc_cached_irq_mask[1] = 0;
- ppc_cached_irq_mask[2] = 0;
-
-#if defined CONFIG_403
- mtdcr(DCRN_EXIER, ppc_cached_irq_mask[0]);
-
- ppc4xx_pic = &ppc403_aic;
- ppc_md.get_irq = ppc403_pic_get_irq;
-#else
-#if (NR_UICS > 2)
- mtdcr(DCRN_UIC_ER(UICB), UICB_UIC0NC | UICB_UIC1NC | UICB_UIC2NC);
- mtdcr(DCRN_UIC_CR(UICB), 0);
-
- mtdcr(DCRN_UIC_ER(UIC2), ppc_cached_irq_mask[2]);
- mtdcr(DCRN_UIC_CR(UIC2), 0);
-
-#endif
-#if (NR_UICS > 1)
-#if (NR_UICS == 2)
- /* enable cascading interrupt */
- ppc_cached_irq_mask[0] |= 1 << (31 - UIC0_UIC1NC);
-#endif
- mtdcr(DCRN_UIC_ER(UIC1), ppc_cached_irq_mask[1]);
- mtdcr(DCRN_UIC_CR(UIC1), 0);
-#endif
- mtdcr(DCRN_UIC_ER(UIC0), ppc_cached_irq_mask[0]);
- mtdcr(DCRN_UIC_CR(UIC0), 0);
-
- if (ibm4xxPIC_InitSenses != NULL)
- ppc4xx_extpic_init();
+
+ /* ACK any pending interrupts to prevent false
+ * triggering after first enable
+ */
+ mtdcr(DCRN_UIC_SR(base), 0xffffffff);
+ }
+
+ /* Perform optional implementation specific setup
+ * (e.g. enable cascade interrupts for multi-UIC configurations)
+ */
+ ppc4xx_pic_impl_init();
+
+ /* Attach low-level handlers */
+ for (i = 0; i < (NR_UICS << 5); ++i){
+ irq_desc[i].handler = &__uic[i >> 5].decl;
+ if (is_level_sensitive(i))
+ irq_desc[i].status |= IRQ_LEVEL;
+ }
- /* Clear any pending interrupts */
-#if (NR_UICS > 2)
- mtdcr(DCRN_UIC_SR(UICB), 0xffffffff);
- mtdcr(DCRN_UIC_SR(UIC2), 0xffffffff);
-#endif
-#if (NR_UICS > 1)
- mtdcr(DCRN_UIC_SR(UIC1), 0xffffffff);
-#endif
- mtdcr(DCRN_UIC_SR(UIC0), 0xffffffff);
-
- ppc4xx_pic = &ppc4xx_uic;
ppc_md.get_irq = ppc4xx_pic_get_irq;
-#endif
}
diff -Nru a/arch/ppc/syslib/ppc4xx_setup.c b/arch/ppc/syslib/ppc4xx_setup.c
--- a/arch/ppc/syslib/ppc4xx_setup.c 2004-11-10 23:39:19 -08:00
+++ b/arch/ppc/syslib/ppc4xx_setup.c 2004-11-10 23:39:19 -08:00
@@ -133,12 +133,7 @@
void __init
ppc4xx_init_IRQ(void)
{
- int i;
-
ppc4xx_pic_init();
-
- for (i = 0; i < NR_IRQS; i++)
- irq_desc[i].handler = ppc4xx_pic;
}
static void
diff -Nru a/arch/ppc/syslib/xilinx_pic.c b/arch/ppc/syslib/xilinx_pic.c
--- a/arch/ppc/syslib/xilinx_pic.c 2004-11-10 23:39:19 -08:00
+++ b/arch/ppc/syslib/xilinx_pic.c 2004-11-10 23:39:19 -08:00
@@ -38,9 +38,6 @@
#define intc_in_be32(addr) mfdcr((addr))
#endif
-/* Global Variables */
-struct hw_interrupt_type *ppc4xx_pic;
-
static void
xilinx_intc_enable(unsigned int irq)
{
@@ -115,6 +112,8 @@
void __init
ppc4xx_pic_init(void)
{
+ int i;
+
#if XPAR_XINTC_USE_DCR == 0
intc = ioremap(XPAR_INTC_0_BASEADDR, 32);
@@ -137,6 +136,8 @@
/* Turn on the Master Enable. */
intc_out_be32(intc + MER, 0x3UL);
- ppc4xx_pic = &xilinx_intc;
ppc_md.get_irq = xilinx_pic_get_irq;
+
+ for (i = 0; i < NR_IRQS; ++i)
+ irq_desc[i].handler = &xilinx_intc;
}
diff -Nru a/include/asm-ppc/ibm44x.h b/include/asm-ppc/ibm44x.h
--- a/include/asm-ppc/ibm44x.h 2004-11-10 23:39:19 -08:00
+++ b/include/asm-ppc/ibm44x.h 2004-11-10 23:39:19 -08:00
@@ -162,8 +162,7 @@
#define DCRN_UIC_VR(base) (base + 0x7)
#define DCRN_UIC_VCR(base) (base + 0x8)
-#define UIC0_UIC1NC 30 /* UIC1 non-critical interrupt */
-#define UIC0_UIC1CR 31 /* UIC1 critical interrupt */
+#define UIC0_UIC1NC 0x00000002
#define UICB_UIC0NC 0x40000000
#define UICB_UIC1NC 0x10000000
@@ -518,7 +517,6 @@
#else
#define NR_UICS 2
#endif
-#define UIC_CASCADE_MASK 0x0003 /* bits 30 & 31 */
#define BD_EMAC_ADDR(e,i) bi_enetaddr[e][i]
diff -Nru a/include/asm-ppc/ppc4xx_pic.h b/include/asm-ppc/ppc4xx_pic.h
--- a/include/asm-ppc/ppc4xx_pic.h 2004-11-10 23:39:19 -08:00
+++ b/include/asm-ppc/ppc4xx_pic.h 2004-11-10 23:39:19 -08:00
@@ -1,28 +1,53 @@
/*
+ * include/asm-ppc/ppc4xx_pic.h
*
- * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
+ * Interrupt controller driver for PowerPC 4xx-based processors.
*
- * Module name: ppc4xx_pic.h
+ * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
*
- * Description:
- * Interrupt controller driver for PowerPC 4xx-based processors.
+ * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
+ * Copyright (c) 2004 Zultys Technologies
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
*/
#ifndef __PPC4XX_PIC_H__
#define __PPC4XX_PIC_H__
#include <linux/config.h>
+#include <linux/types.h>
#include <linux/irq.h>
-/* External Global Variables */
-
-extern struct hw_interrupt_type *ppc4xx_pic;
-extern unsigned int ibm4xxPIC_NumInitSenses;
-extern unsigned char *ibm4xxPIC_InitSenses;
-
-/* Function Prototypes */
+/* "Fixed" UIC settings (they are chip, not board specific),
+ * e.g. polarity/triggerring for internal interrupt sources.
+ *
+ * Platform port should provide NR_UICS-sized array named ppc4xx_core_uic_cfg
+ * with these "fixed" settings: .polarity contains exact value which will
+ * be written (masked with "ext_irq_mask") into UICx_PR register,
+ * .triggering - to UICx_TR.
+ *
+ * Settings for external IRQs can be specified separately by the
+ * board support code. In this case properly sized array of unsigned
+ * char named ppc4xx_uic_ext_irq_cfg should be filled with correct
+ * values using IRQ_SENSE_XXXXX and IRQ_POLARITY_XXXXXXX defines.
+ *
+ * If these arrays aren't provided, UIC initialization code keeps firmware
+ * configuration. Also, ppc4xx_uic_ext_irq_cfg implies ppc4xx_core_uic_cfg
+ * is defined.
+ *
+ * Both ppc4xx_core_uic_cfg and ppc4xx_uic_ext_irq_cfg are declared as
+ * "weak" symbols in ppc4xx_pic.c
+ *
+ */
+struct ppc4xx_uic_settings {
+ u32 polarity;
+ u32 triggering;
+ u32 ext_irq_mask;
+};
extern void ppc4xx_pic_init(void);
-extern int ppc4xx_pic_get_irq(struct pt_regs *regs);
-#endif /* __PPC4XX_PIC_H__ */
+#endif /* __PPC4XX_PIC_H__ */
^ permalink raw reply
* Re: TEST: Sleep patch #4
From: Michael Schmitz @ 2004-11-23 12:28 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev list, debian-powerpc@lists.debian.org
In-Reply-To: <1101160237.13598.121.camel@gaston>
> It reads them from OF at boot. What do you mean by "freak out" ? the
> usual problem with those models where the display gets all fuzzy ? I'm
> not completely sure what's up, I tend to blame the panel power sequence
> nowadays ...
Just got a garbled display when waking up from sleep. That seems to
support your panel powerup idea. A second sleep/wake cycle fixed it.
Looking at radeon_base.c:radeon_screen_blank() (line 1045) we have:
val &= ~(LVDS_BL_MOD_EN);
udelay(100);
val &= ~(LVDS_ON | LVDS_EN);
OUTREG(LVDS_GEN_CNTL, val);
Is there an OUTREG(LVDS_GEN_CNTL, val); missing before the udelay(100) ??
That's in the panel blank code, not the unblank code though. Doesn't seem
to hurt to put the OUTREG in.
Michael
^ permalink raw reply
* Re: TEST: Sleep patch #4
From: Sean Neakums @ 2004-11-23 8:40 UTC (permalink / raw)
To: Guido Guenther
Cc: Keith Conger, debian-powerpc@lists.debian.org, gentoo-ppc-user,
linuxppc-dev list
In-Reply-To: <20041123075833.GB15009@bogon.ms20.nix>
Guido Guenther <agx@debian.org> writes:
> On Mon, Nov 22, 2004 at 06:36:02PM +0000, Sean Neakums wrote:
>> Keith Conger <keith.conger@gmail.com> writes:
>>
>> > Works great here also (15" 1GHz PB). One issue which may be unrelated
>> > I have some sound issues. For instance one a sound is played it sounds
>> > fine but if a sound is played right after its volume is extremely low.
>> > But with headphones this doesn't occur.
>>
>> I have a similar problem post-resume -- sound from the speakers is
>> very quiet (although it seems to be louder at the very beginning) and
>> I had to plug and re-plug the headphones to get sound from them. I
>> tried unloading and reloading snd_powermac, to no avail.
> Could you check if:
> http://honk.physik.uni-konstanz.de/~agx/linux-ppc/kernel/alsa-2.6.9-rc2-revert.diff
> helps?
Increasing DRC Range as suggested by Ben seems to fix my problem.
I note that this patch seems to have a few hunks relating to 48KHz --
does this do anything to help applications that do not resample audio
to 44.1KHz? The asoundrcs using dmix to adjust the rate that I have
seen posted produce rather poor sound.
^ permalink raw reply
* Re: TEST: Sleep patch #4
From: Guido Guenther @ 2004-11-23 7:58 UTC (permalink / raw)
To: Keith Conger, Benjamin Herrenschmidt,
debian-powerpc@lists.debian.org, linuxppc-dev list,
gentoo-ppc-user
In-Reply-To: <6uzn19g299.fsf@zork.zork.net>
On Mon, Nov 22, 2004 at 06:36:02PM +0000, Sean Neakums wrote:
> Keith Conger <keith.conger@gmail.com> writes:
>
> > Works great here also (15" 1GHz PB). One issue which may be unrelated
> > I have some sound issues. For instance one a sound is played it sounds
> > fine but if a sound is played right after its volume is extremely low.
> > But with headphones this doesn't occur.
>
> I have a similar problem post-resume -- sound from the speakers is
> very quiet (although it seems to be louder at the very beginning) and
> I had to plug and re-plug the headphones to get sound from them. I
> tried unloading and reloading snd_powermac, to no avail.
Could you check if:
http://honk.physik.uni-konstanz.de/~agx/linux-ppc/kernel/alsa-2.6.9-rc2-revert.diff
helps?
-- Guido
^ permalink raw reply
* Re: TEST: Sleep patch #4
From: Sean Neakums @ 2004-11-23 8:27 UTC (permalink / raw)
To: Benjamin Herrenschmidt
Cc: linuxppc-dev list, Keith Conger, debian-powerpc@lists.debian.org,
gentoo-ppc-user
In-Reply-To: <1101160349.22529.123.camel@gaston>
Benjamin Herrenschmidt <benh@kernel.crashing.org> writes:
> On Mon, 2004-11-22 at 18:36 +0000, Sean Neakums wrote:
>> Keith Conger <keith.conger@gmail.com> writes:
>>
>> > Works great here also (15" 1GHz PB). One issue which may be unrelated
>> > I have some sound issues. For instance one a sound is played it sounds
>> > fine but if a sound is played right after its volume is extremely low.
>> > But with headphones this doesn't occur.
>>
>> I have a similar problem post-resume -- sound from the speakers is
>> very quiet (although it seems to be louder at the very beginning) and
>> I had to plug and re-plug the headphones to get sound from them. I
>> tried unloading and reloading snd_powermac, to no avail.
>
> Tried playing with the DRC setting in Alsa mixer ?
I hadn't noticed that this was happening pre-suspend, too, and
cranking DRC up fixed it. Thanks!
On resume this morning, though, the display was behaving oddly, both
in X and on the console: it was sort of shimmering, split and repeated
about 1/5 of the screen's width to the right in what looked like
8-pixel horizontal stripes. Rebooting seemed to sort it.
^ permalink raw reply
* Re: TEST: Sleep patch #4
From: Michael Schmitz @ 2004-11-23 8:05 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev list, debian-powerpc@lists.debian.org
In-Reply-To: <1101160237.13598.121.camel@gaston>
> > > http://gate.crashing.org/~benh/albook-ibookg4-sleep-4.diff
> >
> > Sorry for coming late to the party ... the current code works nicely on
> > the 17" PB. On the first boot with that code, I had the PLL freak out (or
> > so it looked like) but I couldn't reproduce that. Needless to say, the
> > new PLL fixup code produces the same dividers as the hardcoded fixup
> > before, so it should work :-)
>
> It reads them from OF at boot. What do you mean by "freak out" ? the
> usual problem with those models where the display gets all fuzzy ? I'm
Yep - the display get totally unreadable, worse than before when the PLL
wouldn't lock properly. When I turned down the backlight (using the
f-keys), it would switch off and not come back up until X had fully
started. Though that might be a bug in pbbuttonsd as well, to be honest (I
turned the backlight off before pbbuttonsd started, perhaps).
> not completely sure what's up, I tend to blame the panel power sequence
> nowadays ...
Anything I can do to test that?
Michael
^ permalink raw reply
* Re: [PATCH][PPC32] Marvell host bridge support (mv64x60)
From: Andrew Morton @ 2004-11-23 4:24 UTC (permalink / raw)
To: Mark A. Greer; +Cc: linuxppc-dev, linux-kernel, linuxppc-embedded
In-Reply-To: <41A27F77.9080401@mvista.com>
"Mark A. Greer" <mgreer@mvista.com> wrote:
>
> Andrew Morton wrote:
>
> >Anyway, I'll stick this as-is in -mm. Feel free to send an incremental
> >patch, or a replacement.
> >
>
> Here is an incremental patch [hopefully] with your concerns addressed.
OK, thanks. I added this to the queue for post-2.6.10. I'll assume that
silence means assent from the rest of the ppc team ;)
(Patches are at
ftp://ftp.kernel.org/pub/linux/kernel/people/akpm/patches/2.6/2.6.10-rc2/2.6.10-rc2-mm3/broken-out/ppc32-marvell-host-bridge-support-mv64x60.patch
ftp://ftp.kernel.org/pub/linux/kernel/people/akpm/patches/2.6/2.6.10-rc2/2.6.10-rc2-mm3/broken-out/ppc32-support-for-marvell-ev-64260-bp-eval-platform.patch
ftp://ftp.kernel.org/pub/linux/kernel/people/akpm/patches/2.6/2.6.10-rc2/2.6.10-rc2-mm3/broken-out/ppc32-support-for-artesyn-katana-cpci-boards.patch
^ permalink raw reply
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