* G5 noisier under linux than firmware or OSX
From: Chris Friesen @ 2005-01-07 15:25 UTC (permalink / raw)
To: linuxppc-dev
I've noticed that when booting, right around the time the kernel first
accesses my disks the fan speed jumps a bit. It's not full-on vacuum
cleaner howling, just a bit noisier.
I've only got the one machine so I can't do A/B comparisons, but it
seems to be quieter when running OSX.
Is linux using the same fan speed parameters, or are we maybe a bit
conservative?
Chris
^ permalink raw reply
* MPC8272 PCI bridge problem
From: Vitaly Bordug @ 2005-01-07 15:03 UTC (permalink / raw)
To: linuxppc-embedded
Hi to all.
I am working on 8272ADS PCI bridge support in 2.4 kernel.
Does anybody have this working more or less? The point is that it's
nearly works for me, but I can't
get interrupt from CPLD interrupt controller and thus PCI cascade
handler won't triggered even once.
I ioremap IC register (0xf4730000 according to RM) in m8260_setup_arch.
After find_bridges call (where PCI staff is configured in immr) the
values of IC status and mask registers change, though they haven't been
touched in the function.
Any advice or clue will be greatly appreciated.
--
Thanks, Vitaly
^ permalink raw reply
* [PATCH] Handle I-TLB Error and Miss separately on 8xx
From: Tom Rini @ 2005-01-07 16:22 UTC (permalink / raw)
To: linuxppc-embedded
As the code stands currently, there is a bug in the 2.4 and 2.6 handling
of I-TLB Miss and Error exceptions on 8xx. The problem is that since we
treat both of them as the same exception when we hit do_page_fault,
there is a case where we can incorrectly find that a protection fault
has occured, when it hasn't. This is because we check bit 4 of SRR1 in
both cases, but in the case of an I-TLB Miss, this bit is always set,
and it only indicates a protection fault on an I-TLB Error.
Originally from Grigori Tolstolytkin <gtolstolytkin@ru.mvista.com>.
Signed-off-by: Tom Rini <trini@kernel.crashing.org>
Patch vs 2.4-current:
--- 1.19/arch/ppc/kernel/head_8xx.S 2003-10-27 12:31:25 -07:00
+++ edited/arch/ppc/kernel/head_8xx.S 2005-01-07 08:57:31 -07:00
@@ -501,10 +501,18 @@
/* This is an instruction TLB error on the MPC8xx. This could be due
* to many reasons, such as executing guarded memory or illegal instruction
* addresses. There is nothing to do but handle a big time error fault.
+ * But we can't just jump from the InstructionAccess fault (0x400) as
+ * do_page_fault() needs to know.
*/
. = 0x1300
InstructionTLBError:
- b InstructionAccess
+ EXCEPTION_PROLOG
+ addi r3,r1,STACK_FRAME_OVERHEAD
+ mr r4,r22
+ mr r5,r23
+ li r20,MSR_KERNEL
+ rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
+ FINISH_EXCEPTION(do_page_fault)
/* This is the data TLB error on the MPC8xx. This could be due to
* many reasons, including a dirty update to a pte. We can catch that
--- 1.15/arch/ppc/mm/fault.c 2003-08-29 03:37:49 -07:00
+++ edited/arch/ppc/mm/fault.c 2005-01-07 08:59:25 -07:00
@@ -91,7 +91,8 @@
* For 600- and 800-family processors, the error_code parameter is DSISR
* for a data fault, SRR1 for an instruction fault. For 400-family processors
* the error_code parameter is ESR for a data fault, 0 for an instruction
- * fault.
+ * fault. On 800-family processors, we fudge an I-TLB Miss (0x1100) as
+ * being at 0x400 for space reasons.
*/
void do_page_fault(struct pt_regs *regs, unsigned long address,
unsigned long error_code)
@@ -111,7 +112,11 @@
* bits we are interested in. But there are some bits which
* indicate errors in DSISR but can validly be set in SRR1.
*/
+#ifdef CONFIG_8xx
+ if (regs->trap == 0x400 || regs->trap == 0x1300)
+#else
if (regs->trap == 0x400)
+#endif
error_code &= 0x48200000;
else
is_write = error_code & 0x02000000;
@@ -204,8 +209,17 @@
goto bad_area;
/* a read */
} else {
- /* protection fault */
+ /*
+ * On non-8xx, a protection fault. On 8xx, this bit is
+ * always set on I-TLB Miss, but indicates a protection
+ * fault on an I-TLB Error. So we only check this bit
+ * if we aren't an I-TLB Miss.
+ */
+#ifdef CONFIG_8xx
+ if ((error_code & 0x08000000) && regs->trap != 0x400)
+#else
if (error_code & 0x08000000)
+#endif
goto bad_area;
if (!(vma->vm_flags & (VM_READ | VM_EXEC)))
goto bad_area;
Patch vs 2.6-current:
--- 1.18/arch/ppc/kernel/head_8xx.S 2004-11-11 01:25:53 -07:00
+++ edited/arch/ppc/kernel/head_8xx.S 2005-01-07 09:13:05 -07:00
@@ -445,10 +445,15 @@
/* This is an instruction TLB error on the MPC8xx. This could be due
* to many reasons, such as executing guarded memory or illegal instruction
* addresses. There is nothing to do but handle a big time error fault.
+ * But we can't just jump from the InstructionAccess fault (0x400) as
+ * do_page_fault() needs to know.
*/
. = 0x1300
InstructionTLBError:
- b InstructionAccess
+ EXCEPTION_PROLOG
+ mr r4,r12
+ mr r5,r9
+ EXC_XFER_EE_LITE(0x1300, handle_page_fault)
/* This is the data TLB error on the MPC8xx. This could be due to
* many reasons, including a dirty update to a pte. We can catch that
--- 1.21/arch/ppc/mm/fault.c 2004-07-26 14:43:22 -07:00
+++ edited/arch/ppc/mm/fault.c 2005-01-07 09:11:44 -07:00
@@ -90,7 +90,8 @@
* For 600- and 800-family processors, the error_code parameter is DSISR
* for a data fault, SRR1 for an instruction fault. For 400-family processors
* the error_code parameter is ESR for a data fault, 0 for an instruction
- * fault.
+ * fault. On 800-family processors, we fudge an I-TLB Miss (0x1100) as
+ * being at 0x400 for space reasons.
*/
int do_page_fault(struct pt_regs *regs, unsigned long address,
unsigned long error_code)
@@ -110,7 +111,11 @@
* bits we are interested in. But there are some bits which
* indicate errors in DSISR but can validly be set in SRR1.
*/
- if (TRAP(regs) == 0x400)
+#ifdef CONFIG_8xx
+ if (TRAP(regs) == 0x400 || TRAP(regs) == 0x1300)
+#else
+ if (TRAP(regs) == 0x400)
+#endif
error_code &= 0x48200000;
else
is_write = error_code & 0x02000000;
@@ -235,8 +240,17 @@
#endif
/* a read */
} else {
- /* protection fault */
+ /*
+ * On non-8xx, a protection fault. On 8xx, this bit is
+ * always set on I-TLB Miss, but indicates a protection
+ * fault on an I-TLB Error. So we only check this bit
+ * if we aren't an I-TLB Miss.
+ */
+#ifdef CONFIG_8xx
+ if ((error_code & 0x08000000) && regs->trap != 0x400)
+#else
if (error_code & 0x08000000)
+#endif
goto bad_area;
if (!(vma->vm_flags & (VM_READ | VM_EXEC)))
goto bad_area;
--
Tom Rini
http://gate.crashing.org/~trini/
^ permalink raw reply
* Looking for PowerPC Linux experts in Austin, TX
From: Charlie Ashton @ 2005-01-07 16:33 UTC (permalink / raw)
To: linuxppc-embedded
I'm responsible for PowerPC Software at AMCC, who acquired the embedded 405
and 440 product lines from IBM.
I'm interested in talking with PowerPC Linux experts in the Austin TX area.
We have a number of development projects in mind and are looking for advice,
opinions and contributions.
Regards,
Charlie Ashton
^ permalink raw reply
* RE: Looking for PowerPC Linux experts in Austin, TX
From: Charlie Ashton @ 2005-01-07 16:42 UTC (permalink / raw)
To: 'Kumar Gala'; +Cc: linuxppc-embedded
In-Reply-To: <87E60733-60CA-11D9-B453-000393DBC2E8@freescale.com>
Kumar,
The primary interest is in community involvement but we're always interested
in talking to great engineers about opportunities to join our team.
Regards,
Charlie
-----Original Message-----
From: Kumar Gala [mailto:kumar.gala@freescale.com]
Sent: Friday, January 07, 2005 10:38 AM
To: cashton@amcc.com
Cc: linuxppc-embedded@ozlabs.org
Subject: Re: Looking for PowerPC Linux experts in Austin, TX
Charlie,
Are you looking to hire people or are you looking for some community
involvement?
- kumar
On Jan 7, 2005, at 10:33 AM, Charlie Ashton wrote:
> I'm responsible for PowerPC Software at AMCC, who acquired the
> embedded 405 and 440 product lines from IBM.
>
> I'm interested in talking with PowerPC Linux experts in the Austin TX
> area.
> We have a number of development projects in mind and are looking for
> advice, opinions and contributions.
>
> Regards,
> Charlie Ashton
>
>
>
> _______________________________________________
> Linuxppc-embedded mailing list
> Linuxppc-embedded@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-embedded
^ permalink raw reply
* Re: Looking for PowerPC Linux experts in Austin, TX
From: Kumar Gala @ 2005-01-07 16:38 UTC (permalink / raw)
To: cashton; +Cc: linuxppc-embedded
In-Reply-To: <I9YGNJ02.V3Y@hadar.amcc.com>
Charlie,
Are you looking to hire people or are you looking for some community
involvement?
- kumar
On Jan 7, 2005, at 10:33 AM, Charlie Ashton wrote:
> I'm responsible for PowerPC Software at AMCC, who acquired the
> embedded 405
> and 440 product lines from IBM.
>
> I'm interested in talking with PowerPC Linux experts in the Austin TX
> area.
> We have a number of development projects in mind and are looking for
> advice,
> opinions and contributions.
>
> Regards,
> Charlie Ashton
>
>
>
> _______________________________________________
> Linuxppc-embedded mailing list
> Linuxppc-embedded@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-embedded
^ permalink raw reply
* Frame Buffer and Y Cb Cr
From: Federico Lucifredi @ 2005-01-07 21:13 UTC (permalink / raw)
To: Linux-ppc [mailing list]
Hello All,
I am working on a fb driver for linux in an embedded PPC setup. I
have it working as far as linux is concerned, and I also understand the
video card side of the problem.
My trouble is: Linux sends me R G B and the hardware expects Y Cb
Cr. As things work through a memory-mapped file, I am at a loss for an
"intelligent" way to intercept and convert these values.
Any suggestions ?
Best - Federico
--
_________________________________________
-- "'Problem' is a bleak word for challenge" - Richard Fish
Muad'Dib of Caladan (Federico L. Lucifredi)- Harvard University & BU
http://metcs.bu.edu/~lucifred
^ permalink raw reply
* Re: Looking for PowerPC Linux experts in Austin, TX
From: annamaya @ 2005-01-07 22:24 UTC (permalink / raw)
To: cashton, linuxppc-embedded
In-Reply-To: <I9YGNJ02.V3Y@hadar.amcc.com>
Hello Charlie,
I live in Austin, TX and work on embedded Linux for a
local company here. What can I do for you?
--- Charlie Ashton <cashton@amcc.com> wrote:
> I'm responsible for PowerPC Software at AMCC, who
> acquired the embedded 405
> and 440 product lines from IBM.
>
> I'm interested in talking with PowerPC Linux experts
> in the Austin TX area.
> We have a number of development projects in mind and
> are looking for advice,
> opinions and contributions.
>
> Regards,
> Charlie Ashton
>
>
> _______________________________________________
> Linuxppc-embedded mailing list
> Linuxppc-embedded@ozlabs.org
>
https://ozlabs.org/mailman/listinfo/linuxppc-embedded
>
__________________________________
Do you Yahoo!?
Yahoo! Mail - Easier than ever with enhanced search. Learn more.
http://info.mail.yahoo.com/mail_250
^ permalink raw reply
* Re: Frame Buffer and Y Cb Cr
From: Wolfgang Denk @ 2005-01-07 22:30 UTC (permalink / raw)
To: Federico Lucifredi; +Cc: Linux-ppc [mailing list]
In-Reply-To: <41DEFB89.5060404@acm.org>
In message <41DEFB89.5060404@acm.org> you wrote:
>
> My trouble is: Linux sends me R G B and the hardware expects Y Cb
> Cr. As things work through a memory-mapped file, I am at a loss for an
> "intelligent" way to intercept and convert these values.
Have a look at the arch/ppc/8xx_io/viedo* files in our old linux-2.4
tree on the CVS server - this driver is for the video contoller on a
MPC823 wich needs YCbCr.
Best regards,
Wolfgang Denk
--
Software Engineering: Embedded and Realtime Systems, Embedded Linux
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de
Sometimes a feeling is all we humans have to go on.
-- Kirk, "A Taste of Armageddon", stardate 3193.9
^ permalink raw reply
* RE: Looking for PowerPC Linux experts in Austin, TX
From: Josh Boyer @ 2005-01-07 22:30 UTC (permalink / raw)
To: cashton; +Cc: linuxppc-embedded
In-Reply-To: <I9YH3802.341@hadar.amcc.com>
On Fri, 2005-01-07 at 10:42 -0600, Charlie Ashton wrote:
> Kumar,
>
> The primary interest is in community involvement but we're always interested
> in talking to great engineers about opportunities to join our team.
I think the Austin, TX part of your request has some people confused.
The community is much much larger than Austin, so why are you only
interested in talking with people from there?
josh
^ permalink raw reply
* Re: G5 noisier under linux than firmware or OSX
From: Jerome Glisse @ 2005-01-08 11:22 UTC (permalink / raw)
To: Chris Friesen; +Cc: linuxppc-dev
In-Reply-To: <41DEA9D8.3000506@nortelnetworks.com>
Chris Friesen wrote:
> I've noticed that when booting, right around the time the kernel first
> accesses my disks the fan speed jumps a bit. It's not full-on vacuum
> cleaner howling, just a bit noisier.
>
> I've only got the one machine so I can't do A/B comparisons, but it
> seems to be quieter when running OSX.
>
> Is linux using the same fan speed parameters, or are we maybe a bit
> conservative?
From my memory, there have been some guess on values for
therm regulation as Apple seems to not give informations or
source code on that. Thus the values for regulating the fan are not
the same as OS X.
By the way, i also hear little more noise. The question is : Should
we lower the speed or stay with this conservative values ? :)
best,
Jerome Glisse
^ permalink raw reply
* [PATCH] ppc32: ide, mpc8xx - volatile fix
From: Magnus Damm @ 2005-01-08 18:02 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Magnus Damm
This patch makes sure that a PCMCIA register is accessed with a volatile
pointer. Wierd things happen without the patch if compiled with gcc-3.
Signed-off-by: Magnus Damm <damm@opensource.se>
--- linux-2.6.10/drivers/ide/ppc/mpc8xx.c 2004-12-24 22:35:39.000000000 +0100
+++ linux-2.6.10-ppc32_ide_mpc8xx_volatile/drivers/ide/ppc/mpc8xx.c 2005-01-08 18:42:06.000000000 +0100
@@ -172,7 +172,7 @@
volatile pcmcia_win_t *win;
volatile pcmconf8xx_t *pcmp;
- uint *pgcrx;
+ volatile uint *pgcrx;
u32 pcmcia_phy_base;
u32 pcmcia_phy_end;
static unsigned long pcmcia_base = 0;
^ permalink raw reply
* Re: TZ variable setting for denx 2.4.20
From: Tony Lee @ 2005-01-09 3:30 UTC (permalink / raw)
To: Robin; +Cc: Linuxppc-embedded
In-Reply-To: <41DE3A2A.3050105@india.tejasnetworks.com>
What's denx?
Anyway, in my embeded ppc-linux, I set it with
/etc/TZ
echo "PST8PDT" > /etc/TZ to set it to pacific time.
Have fun.
-Tony
On Fri, 07 Jan 2005 12:58:42 +0530, Robin <robin@india.tejasnetworks.com> wrote:
> Hi
> Thanx for your response. I am setting TZ variable as
> given in the documentation.
> export TZ="xxx5:30yyy4:30,M10.1.1,M2.1.1"
> Its working fine till Dec 31 23:59:59GMT. On Jan 01 00:00:00,
> its not taking DST into account at all.
>
> Please tell me some way of setting it across an year boundary.
> Thanks,
> Robin
>
> Marius Groeger wrote:
>
> > Robin,
> >
> > On Thu, 6 Jan 2005, Robin wrote:
> >
> >> I have tried with the standard linux date too. That too doesnt seem
> >> to consider timezone variable that has been set. Can you give me a
> >> way for setting timezone for southern hemisphere countries?? The
> >> busybox code uses strftime function. But that does not seem to
> >> consider TZ variable...
> >
> >
> > You should read up on how glibc handles all that timezone stuff:
> >
> > sh# info libc "TZ Variable"
> >
> > Most notably, make sure you /etc/localtime is set up correctly. There
> > is also a tool (script) called tzselect which may be helpful for you.
> >
> > Note I'm not exactly an expert on this, I'm just giving pointers...
> >
> > Regards,
> > Marius
> >
>
> _______________________________________________
> Linuxppc-embedded mailing list
> Linuxppc-embedded@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-embedded
>
--
-Tony
Having fun with FPGA HW + ppc + Linux
^ permalink raw reply
* status of pegasos2 support
From: Christoph Hellwig @ 2005-01-09 11:59 UTC (permalink / raw)
To: linuxppc-dev
Guys, could we please get some definit comments on the Pegasos2 support?
We've been carring it around forever in the Debian tree and it's been
making no progress at all.
#! /bin/sh -e
##
## All lines beginning with `## DP:' are a description of the patch.
## DP: Description: Add Pegasos 1 and 2 support.
## DP: Patch author: Sven Luther <luther@debian.org>
## DP: Upstream status: submitted and approved.
. $(dirname $0)/DPATCH
@DPATCH@
diff -urN kernel-source-2.6.8.orig/arch/ppc/kernel/ppc_ksyms.c kernel-source-2.6.8/arch/ppc/kernel/ppc_ksyms.c
--- kernel-source-2.6.8.orig/arch/ppc/kernel/ppc_ksyms.c 2004-08-14 07:37:41.000000000 +0200
+++ kernel-source-2.6.8/arch/ppc/kernel/ppc_ksyms.c 2004-12-26 11:50:48.234758552 +0100
@@ -96,6 +96,9 @@
EXPORT_SYMBOL(_prep_type);
EXPORT_SYMBOL(ucSystemType);
#endif
+#if defined(CONFIG_PPC_MULTIPLATFORM)
+EXPORT_SYMBOL(_chrp_type);
+#endif
#if !defined(__INLINE_BITOPS)
EXPORT_SYMBOL(set_bit);
diff -urN kernel-source-2.6.8.orig/arch/ppc/platforms/chrp_pci.c kernel-source-2.6.8/arch/ppc/platforms/chrp_pci.c
--- kernel-source-2.6.8.orig/arch/ppc/platforms/chrp_pci.c 2004-12-26 12:03:07.438382520 +0100
+++ kernel-source-2.6.8/arch/ppc/platforms/chrp_pci.c 2004-12-26 12:02:26.819557520 +0100
@@ -97,8 +97,9 @@
rtas_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
int len, u32 *val)
{
+ struct pci_controller *hose = bus->sysdata;
unsigned long addr = (offset & 0xff) | ((devfn & 0xff) << 8)
- | ((bus->number & 0xff) << 16);
+ | (((bus->number - hose->first_busno) & 0xff) << 16) | (pci_domain_nr(bus) << 24);
unsigned long ret = ~0UL;
int rval;
@@ -111,8 +112,9 @@
rtas_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
int len, u32 val)
{
+ struct pci_controller *hose = bus->sysdata;
unsigned long addr = (offset & 0xff) | ((devfn & 0xff) << 8)
- | ((bus->number & 0xff) << 16);
+ | (((bus->number - hose->first_busno) & 0xff) << 16) | (pci_domain_nr(bus) << 24);
int rval;
rval = call_rtas("write-pci-config", 3, 1, NULL, addr, len, val);
@@ -186,6 +188,26 @@
iounmap(reg);
}
+/* Marvell Discovery II based Pegasos 2 */
+//#define PEGASOS_USE_PCI_DOMAINS
+
+static void __init
+setup_peg2(struct pci_controller *hose, struct device_node *dev)
+{
+ struct device_node *root = find_path_device("/");
+ struct device_node *rtas;
+
+ rtas = of_find_node_by_name (root, "rtas");
+ if (rtas) {
+ hose->ops = &rtas_pci_ops;
+ } else {
+ printk ("RTAS supporting Pegasos OF not found, please upgrade your firmware\n");
+ }
+#ifndef PEGASOS_USE_PCI_DOMAINS
+ pci_assign_all_busses = 1;
+#endif
+}
+
void __init
chrp_find_bridges(void)
{
@@ -195,7 +217,7 @@
struct pci_controller *hose;
unsigned int *dma;
char *model, *machine;
- int is_longtrail = 0, is_mot = 0;
+ int is_longtrail = 0, is_mot = 0, is_pegasos = 0;
struct device_node *root = find_path_device("/");
/*
@@ -207,6 +229,8 @@
if (machine != NULL) {
is_longtrail = strncmp(machine, "IBM,LongTrail", 13) == 0;
is_mot = strncmp(machine, "MOT", 3) == 0;
+ if (strncmp(machine, "Pegasos2", 8) == 0) is_pegasos = 2;
+ else if (strncmp(machine, "Pegasos", 7) == 0) is_pegasos = 1;
}
for (dev = root->child; dev != NULL; dev = dev->sibling) {
if (dev->type == NULL || strcmp(dev->type, "pci") != 0)
@@ -257,6 +281,10 @@
hose->cfg_data = (unsigned char *)
ioremap(GG2_PCI_CONFIG_BASE, 0x80000);
gg2_pci_config_base = (unsigned long) hose->cfg_data;
+ } else if (is_pegasos == 1) {
+ setup_indirect_pci(hose, 0xfec00cf8, 0xfee00cfc);
+ } else if (is_pegasos == 2) {
+ setup_peg2(hose, dev);
} else {
printk("No methods for %s (model %s), using RTAS\n",
dev->full_name, model);
@@ -274,6 +302,9 @@
printk("pci_dram_offset = %lx\n", pci_dram_offset);
}
}
-
- ppc_md.pcibios_fixup = chrp_pcibios_fixup;
+
+ if (is_pegasos)
+ ppc_md.pcibios_fixup = NULL;
+ else
+ ppc_md.pcibios_fixup = chrp_pcibios_fixup;
}
diff -urN kernel-source-2.6.8.orig/arch/ppc/platforms/chrp_setup.c kernel-source-2.6.8/arch/ppc/platforms/chrp_setup.c
--- kernel-source-2.6.8.orig/arch/ppc/platforms/chrp_setup.c 2004-12-26 12:03:07.440382216 +0100
+++ kernel-source-2.6.8/arch/ppc/platforms/chrp_setup.c 2004-12-26 12:01:39.050819472 +0100
@@ -68,6 +68,8 @@
extern unsigned long pmac_find_end_of_memory(void);
extern int of_show_percpuinfo(struct seq_file *, int);
+int _chrp_type;
+
/*
* XXX this should be in xmon.h, but putting it there means xmon.h
* has to include <linux/interrupt.h> (to get irqreturn_t), which
@@ -214,6 +216,36 @@
}
}
+void pegasos_set_l2cr(void)
+{
+ struct device_node *root = find_path_device("/");
+ char *machine;
+ struct device_node *np;
+
+ /* On Pegasos, enable the l2 cache if needed, as the OF forgets it */
+ if (root == NULL)
+ return;
+ machine = get_property(root, "model", NULL);
+ if (machine == NULL)
+ return;
+ if (_chrp_type == _CHRP_Pegasos) {
+ /* Enable L2 cache if needed */
+ np = find_type_devices("cpu");
+ if (np != NULL) {
+ unsigned int *l2cr = (unsigned int *)
+ get_property (np, "l2cr", NULL);
+ if (l2cr == NULL) {
+ printk ("Pegasos l2cr : no cpu l2cr property found\n");
+ return;
+ }
+ if (!((*l2cr) & 0x80000000)) {
+ printk ("Pegasos l2cr : L2 cache was not active, activating\n");
+ _set_L2CR(0);
+ _set_L2CR((*l2cr) | 0x80000000);
+ }
+ }
+ }
+}
void __init
chrp_setup_arch(void)
@@ -236,6 +268,9 @@
/* Lookup PCI host bridges */
chrp_find_bridges();
+ /* On pegasos, enable the L2 cache if not already done by OF */
+ pegasos_set_l2cr();
+
#ifndef CONFIG_PPC64BRIDGE
/*
* Temporary fixes for PCI devices.
@@ -400,16 +435,19 @@
if (np == NULL)
printk(KERN_ERR "Cannot find PCI interrupt acknowledge address\n");
- chrp_find_openpic();
-
- prom_get_irq_senses(init_senses, NUM_8259_INTERRUPTS, NR_IRQS);
- OpenPIC_InitSenses = init_senses;
- OpenPIC_NumInitSenses = NR_IRQS - NUM_8259_INTERRUPTS;
-
- openpic_init(NUM_8259_INTERRUPTS);
- /* We have a cascade on OpenPIC IRQ 0, Linux IRQ 16 */
- openpic_hookup_cascade(NUM_8259_INTERRUPTS, "82c59 cascade",
+ /* Pegasos doesn't have openpic */
+ if (_chrp_type != _CHRP_Pegasos) {
+ chrp_find_openpic();
+
+ prom_get_irq_senses(init_senses, NUM_8259_INTERRUPTS, NR_IRQS);
+ OpenPIC_InitSenses = init_senses;
+ OpenPIC_NumInitSenses = NR_IRQS - NUM_8259_INTERRUPTS;
+
+ openpic_init(NUM_8259_INTERRUPTS);
+ /* We have a cascade on OpenPIC IRQ 0, Linux IRQ 16 */
+ openpic_hookup_cascade(NUM_8259_INTERRUPTS, "82c59 cascade",
i8259_irq);
+ }
for (i = 0; i < NUM_8259_INTERRUPTS; i++)
irq_desc[i].handler = &i8259_pic;
@@ -450,6 +488,8 @@
chrp_init(unsigned long r3, unsigned long r4, unsigned long r5,
unsigned long r6, unsigned long r7)
{
+ struct device_node *root = find_path_device ("/");
+ char *machine;
#ifdef CONFIG_BLK_DEV_INITRD
/* take care of initrd if we have one */
if ( r6 )
@@ -464,12 +504,27 @@
DMA_MODE_WRITE = 0x48;
isa_io_base = CHRP_ISA_IO_BASE; /* default value */
+ machine = get_property(root, "model", NULL);
+ if (strncmp(machine, "Pegasos", 7) == 0) {
+ _chrp_type = _CHRP_Pegasos;
+ } else if (strncmp(machine, "IBM", 3) == 0) {
+ _chrp_type = _CHRP_IBM;
+ } else if (strncmp(machine, "MOT", 3) == 0) {
+ _chrp_type = _CHRP_Motorola;
+ } else {
+ /* Let's assume it is an IBM chrp if all else fails */
+ _chrp_type = _CHRP_IBM;
+ }
+
ppc_md.setup_arch = chrp_setup_arch;
ppc_md.show_percpuinfo = of_show_percpuinfo;
ppc_md.show_cpuinfo = chrp_show_cpuinfo;
ppc_md.irq_canonicalize = chrp_irq_canonicalize;
ppc_md.init_IRQ = chrp_init_IRQ;
- ppc_md.get_irq = openpic_get_irq;
+ if (_chrp_type == _CHRP_Pegasos)
+ ppc_md.get_irq = i8259_irq;
+ else
+ ppc_md.get_irq = openpic_get_irq;
ppc_md.init = chrp_init2;
diff -urN kernel-source-2.6.8.orig/arch/ppc/platforms/chrp_time.c kernel-source-2.6.8/arch/ppc/platforms/chrp_time.c
--- kernel-source-2.6.8.orig/arch/ppc/platforms/chrp_time.c 2004-12-26 12:03:07.552365192 +0100
+++ kernel-source-2.6.8/arch/ppc/platforms/chrp_time.c 2004-11-24 22:47:24.000000000 +0100
@@ -41,6 +41,8 @@
int base;
rtcs = find_compatible_devices("rtc", "pnpPNP,b00");
+ if (rtcs == NULL)
+ rtcs = find_compatible_devices("rtc", "ds1385-rtc");
if (rtcs == NULL || rtcs->addrs == NULL)
return 0;
base = rtcs->addrs[0].address;
diff -urN kernel-source-2.6.8.orig/arch/ppc/syslib/prom_init.c kernel-source-2.6.8/arch/ppc/syslib/prom_init.c
--- kernel-source-2.6.8.orig/arch/ppc/syslib/prom_init.c 2004-12-26 12:03:07.672346952 +0100
+++ kernel-source-2.6.8/arch/ppc/syslib/prom_init.c 2004-12-26 11:58:49.597580280 +0100
@@ -794,6 +794,9 @@
char *p, *d;
unsigned long phys;
void *result[3];
+ char model[32];
+ phandle node;
+ int rc;
/* Default */
phys = (unsigned long) &_stext;
@@ -850,11 +853,20 @@
klimit = (char *) (mem - offset);
- /* If we are already running at 0xc0000000, we assume we were
- * loaded by an OF bootloader which did set a BAT for us.
- * This breaks OF translate so we force phys to be 0.
- */
- if (offset == 0) {
+ node = call_prom("finddevice", 1, 1, "/");
+ rc = call_prom("getprop", 4, 1, node, "model", model, sizeof(model));
+ if (rc > 0 && !strncmp (model, "Pegasos", 7)
+ && strncmp (model, "Pegasos2", 8)) {
+ /* Pegasos 1 has a broken translate method in the OF,
+ * and furthermore the BATs are mapped 1:1 so the phys
+ * address calculated above is correct, so let's use
+ * it directly.
+ */
+ } else if (offset == 0) {
+ /* If we are already running at 0xc0000000, we assume we were
+ * loaded by an OF bootloader which did set a BAT for us.
+ * This breaks OF translate so we force phys to be 0.
+ */
prom_print("(already at 0xc0000000) phys=0\n");
phys = 0;
} else if ((int) call_prom("getprop", 4, 1, prom_chosen, "mmu",
diff -urN kernel-source-2.6.8.orig/include/asm-ppc/processor.h kernel-source-2.6.8/include/asm-ppc/processor.h
--- kernel-source-2.6.8.orig/include/asm-ppc/processor.h 2004-08-14 07:36:11.000000000 +0200
+++ kernel-source-2.6.8/include/asm-ppc/processor.h 2004-12-26 13:50:25.909586120 +0100
@@ -34,6 +34,7 @@
/* these are arbitrary */
#define _CHRP_Motorola 0x04 /* motorola chrp, the cobra */
#define _CHRP_IBM 0x05 /* IBM chrp, the longtrail and longtrail 2 */
+#define _CHRP_Pegasos 0x06 /* Genesi/bplan's Pegasos and Pegasos2 */
#define _GLOBAL(n)\
.stabs __stringify(n:F-1),N_FUN,0,0,n;\
@@ -54,6 +55,7 @@
/* what kind of prep workstation we are */
extern int _prep_type;
+extern int _chrp_type;
/*
* This is used to identify the board type from a given PReP board
^ permalink raw reply
* status of the G4 l2 cache flush and MSR errate patch
From: Christoph Hellwig @ 2005-01-09 11:57 UTC (permalink / raw)
To: Sven Luther, benh; +Cc: linuxppc-dev
Sven & Ben,
what's the status of the patch below (forward-port to 2.6.10 by me)?
#! /bin/sh -e
##
## All lines beginning with `## DP:' are a description of the patch.
## DP: Description: Fixes g4 l2 cache flush and MSR erratas.
## DP: Patch author: Sven Luther <luther@debian.org>
## DP: Upstream status: under review by benh.
. $(dirname $0)/DPATCH
@DPATCH@
--- 1.31/arch/ppc/kernel/cputable.c 2004-11-11 09:25:53 +01:00
+++ edited/arch/ppc/kernel/cputable.c 2005-01-02 12:53:10 +01:00
@@ -380,7 +380,7 @@ struct cpu_spec cpu_specs[] = {
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
- CPU_FTR_NEED_COHERENT,
+ CPU_FTR_NEED_COHERENT | CPU_FTR_HWFLUSH_L2_CACHE,
.cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
.icache_bsize = 32,
.dcache_bsize = 32,
@@ -397,7 +397,7 @@ struct cpu_spec cpu_specs[] = {
CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP |
- CPU_FTR_NEED_COHERENT,
+ CPU_FTR_NEED_COHERENT | CPU_FTR_HWFLUSH_L2_CACHE,
.cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
.icache_bsize = 32,
.dcache_bsize = 32,
@@ -413,7 +413,8 @@ struct cpu_spec cpu_specs[] = {
CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
- CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT,
+ CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT |
+ CPU_FTR_HWFLUSH_L2_CACHE,
.cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
.icache_bsize = 32,
.dcache_bsize = 32,
@@ -428,7 +429,8 @@ struct cpu_spec cpu_specs[] = {
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
- CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT,
+ CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT |
+ CPU_FTR_HWFLUSH_L2_CACHE,
.cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
.icache_bsize = 32,
.dcache_bsize = 32,
@@ -445,7 +447,8 @@ struct cpu_spec cpu_specs[] = {
CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP |
- CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS,
+ CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS |
+ CPU_FTR_HWFLUSH_L2_CACHE,
.cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
.icache_bsize = 32,
.dcache_bsize = 32,
@@ -462,7 +465,7 @@ struct cpu_spec cpu_specs[] = {
CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
- CPU_FTR_NEED_COHERENT,
+ CPU_FTR_NEED_COHERENT | CPU_FTR_HWFLUSH_L2_CACHE,
.cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
.icache_bsize = 32,
.dcache_bsize = 32,
@@ -479,7 +482,8 @@ struct cpu_spec cpu_specs[] = {
CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
- CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC,
+ CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC |
+ CPU_FTR_HWFLUSH_L2_CACHE,
.cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
.icache_bsize = 32,
.dcache_bsize = 32,
@@ -496,7 +500,8 @@ struct cpu_spec cpu_specs[] = {
CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
- CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC,
+ CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC |
+ CPU_FTR_HWFLUSH_L2_CACHE,
.cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
.icache_bsize = 32,
.dcache_bsize = 32,
@@ -513,7 +518,7 @@ struct cpu_spec cpu_specs[] = {
CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
- CPU_FTR_NEED_COHERENT,
+ CPU_FTR_NEED_COHERENT | CPU_FTR_HWFLUSH_L2_CACHE,
.cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
.icache_bsize = 32,
.dcache_bsize = 32,
@@ -529,7 +534,8 @@ struct cpu_spec cpu_specs[] = {
CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
- CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT,
+ CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT |
+ CPU_FTR_HWFLUSH_L2_CACHE,
.cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
.icache_bsize = 32,
.dcache_bsize = 32,
--- 1.11/arch/ppc/kernel/l2cr.S 2004-02-21 02:30:29 +01:00
+++ edited/arch/ppc/kernel/l2cr.S 2005-01-02 12:55:28 +01:00
@@ -19,7 +19,7 @@
/*
Thur, Dec. 12, 1998.
- First public release, contributed by PowerLogix.
- ***********
+
Sat, Aug. 7, 1999.
- Terry: Made sure code disabled interrupts before running. (Previously
it was assumed interrupts were already disabled).
@@ -27,16 +27,19 @@
instead of 2MB. (Prob. only 3 is necessary).
- Terry: Updated for workaround to HID0[DPM] processor bug
during global invalidates.
- ***********
+
Thu, July 13, 2000.
- Terry: Added isync to correct for an errata.
- 22 August 2001.
+ We, August 22, 2001.
- DanM: Finally added the 7450 patch I've had for the past
several months. The L2CR is similar, but I'm going
to assume the user of this functions knows what they
are doing.
+ Thu, June 17, 2004.
+ - JPAN: Fixed 745X L3 cache enablement routine, also use HW flush assist.
+
Author: Terry Greeniaus (tgree@phys.ualberta.ca)
Please e-mail updates to this file to me, thanks!
*/
@@ -154,9 +157,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
Don't do this unless you accomodate all processor variations.
The bit moved on the 7450.....
****/
-
- /* TODO: use HW flush assist when available */
-
+BEGIN_FTR_SECTION
lis r4,0x0002
mtctr r4
li r4,0
@@ -175,7 +176,23 @@ END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
dcbf 0,r4
addi r4,r4,32 /* Go to start of next cache line */
bdnz 1b
+END_FTR_SECTION_IFCLR(CPU_FTR_HWFLUSH_L2_CACHE)
+BEGIN_FTR_SECTION
+ /* Use HW flush assist, MPC7447A errata #3 */
+ oris r4,r4,0x0010 /* Set L2CR[IONLY/11] = 1 */
+ oris r4,r4,0x0001 /* Set L2CR[DONLY/15] = 1 */
+ mtspr L2CR,r4 /* Lock the L2 */
+ sync
+ ori r4,r4,0x0800 /* Set L2CR[L2HWF/20] = 1 */
+ mtspr L2CR,r4 /* Flush the L2 */
+1:
+ mfspr r4,L2CR
+ andi. r4,r4,0x0800 /* L2HWF still set? */
+ bne 1b
+ sync /* sync to clear the store queues before L3 flush (UM step 5)*/
+END_FTR_SECTION_IFSET(CPU_FTR_HWFLUSH_L2_CACHE)
+
2:
/* Set up the L2CR configuration bits (and switch L2 off) */
/* CPU errata: Make sure the mtspr below is already in the
@@ -292,17 +309,18 @@ END_FTR_SECTION_IFCLR(CPU_FTR_L3CR)
/* Flush the cache.
*/
-
- /* TODO: use HW flush assist */
-
- lis r4,0x0008
- mtctr r4
- li r4,0
-1:
- lwzx r0,r0,r4
- dcbf 0,r4
- addi r4,r4,32 /* Go to start of next cache line */
- bdnz 1b
+ /* use HW flush assist. (UM 3.6.3.1.5) */
+ mfspr r4, SPRN_L3CR
+ oris r4,r4,0x0040 /* Set L3CR[L3IO/9] = 1. */
+ ori r4,r4,0x0040 /* Set L3CR[L3DO/29] = 1.*/
+ mtspr 1018,r4 /* Lock the L3 by making IONLY and DONLY */
+ ori r4,r4,0x0800 /* Set L3CR[L3HWF/20] for hardware flush */
+ mtspr SPRN_L3CR,r4
+flush_745x_L3_poll:
+ mfspr r4,SPRN_L3CR
+ rlwinm. r4,r4,0,20,20
+ bne flush_745x_L3_poll
+ sync /* Clear the store queues per procedure (UM step 8) */
2:
/* Set up the L3CR configuration bits (and switch L3 off) */
@@ -348,8 +366,8 @@ END_FTR_SECTION_IFCLR(CPU_FTR_L3CR)
cmplwi r5,0
beq 4f
- /* Enable the cache */
- oris r3,r3,(L3CR_L3E | L3CR_L3CLKEN)@h
+ /* enable L3 clock */
+ oris r3,r3,(L3CR_L3CLKEN)@h
mtspr SPRN_L3CR,r3
sync
@@ -357,6 +375,15 @@ END_FTR_SECTION_IFCLR(CPU_FTR_L3CR)
li r0,256
mtctr r0
1: bdnz 1b
+
+ /* Clear MSSSR0 which may cause parity error */
+ xor r5,r5,r5
+ mtspr 1015, r5
+
+ /* Enable L3 cache */
+ oris r3,r3,(L3CR_L3E)@h
+ mtspr SPRN_L3CR,r3
+ sync
/* Restore MSR (restores EE and DR bits to original state) */
4: SYNC
--- 1.36/arch/ppc/kernel/traps.c 2004-11-02 15:40:33 +01:00
+++ edited/arch/ppc/kernel/traps.c 2005-01-02 12:53:46 +01:00
@@ -298,7 +298,9 @@ void MachineCheckException(struct pt_reg
case 0x80000:
printk("Machine check signal\n");
break;
- case 0: /* for 601 */
+ case 0: /* for 601 and 744x */
+ printk("Transfer error ack signal if 601, or MCP if 744x \n");
+ break;
case 0x40000:
case 0x140000: /* 7450 MSS error and TEA */
printk("Transfer error ack signal\n");
--- 1.10/include/asm-ppc/cputable.h 2004-11-11 09:25:52 +01:00
+++ edited/include/asm-ppc/cputable.h 2005-01-02 12:53:46 +01:00
@@ -83,6 +83,7 @@ extern struct cpu_spec *cur_cpu_spec[];
#define CPU_FTR_HAS_HIGH_BATS 0x00010000
#define CPU_FTR_NEED_COHERENT 0x00020000
#define CPU_FTR_NO_BTIC 0x00040000
+#define CPU_FTR_HWFLUSH_L2_CACHE 0x00080000
#ifdef __ASSEMBLY__
^ permalink raw reply
* Re: status of pegasos2 support
From: Sven Luther @ 2005-01-09 12:31 UTC (permalink / raw)
To: Christoph Hellwig; +Cc: linuxppc-dev
In-Reply-To: <20050109115935.GA19249@lst.de>
On Sun, Jan 09, 2005 at 12:59:36PM +0100, Christoph Hellwig wrote:
> Guys, could we please get some definit comments on the Pegasos2 support?
>
> We've been carring it around forever in the Debian tree and it's been
> making no progress at all.
As for me, it is ready to be submitted upstream, i sent it already, and it was
mostly ok when i wrote to linuxppc-dev and i think benh also said they are ok.
I believe benh is waiting to go back home (should be in the plane right now if
i am not wrong) to do the submission part of it.
Friendly,
Sven Luther
^ permalink raw reply
* Re: status of the G4 l2 cache flush and MSR errate patch
From: Sven Luther @ 2005-01-09 12:35 UTC (permalink / raw)
To: Christoph Hellwig; +Cc: linuxppc-dev
In-Reply-To: <20050109115720.GA19213@lst.de>
On Sun, Jan 09, 2005 at 12:57:20PM +0100, Christoph Hellwig wrote:
> Sven & Ben,
>
> what's the status of the patch below (forward-port to 2.6.10 by me)?
>
>
>
> #! /bin/sh -e
> ##
> ## All lines beginning with `## DP:' are a description of the patch.
> ## DP: Description: Fixes g4 l2 cache flush and MSR erratas.
> ## DP: Patch author: Sven Luther <luther@debian.org>
Mmm, well, i am not really the author of this one. Jacob Pan from freescale is
the author, so we should change this, will do. So this should show :
## DP: Patch author: Pan Jacob-r7aahq <Jacob.Pan@freescale.com>
> ## DP: Upstream status: under review by benh.
The patch does two things. Use hardware assist for cache flush, which seems to
be ok on 744x processors, but broken on earlier G4s and G3s. And add a printk
in case of some exception, so the user knows about it instead of it being
silently discarded.
I was under the impression that benh said that the patch was ok, but not
really relevant, since it applies to code travel cases which either are not
really used in the common case, or result in a dying of the kernel anyway.
Don't remember all the details though. They do respond to some G4 processor
errata's though.
Friendly,
Sven Luther
^ permalink raw reply
* [PATCH 2.6.10-mm2] Remove duplicate define (PPC)
From: tglx @ 2005-01-09 12:25 UTC (permalink / raw)
To: trini; +Cc: akpm, linuxppc-embedded
The MMCR0_PMXE is already defined in reg.h, so no need to redefine it here.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
---
perfmon.c | 1 -
1 files changed, 1 deletion(-)
---
Index: 2.6.10-mm2/arch/ppc/kernel/perfmon.c
===================================================================
--- 2.6.10-mm2/arch/ppc/kernel/perfmon.c (revision 141)
+++ 2.6.10-mm2/arch/ppc/kernel/perfmon.c (working copy)
@@ -47,7 +47,6 @@
#else
/* Ensure exceptions are disabled */
-#define MMCR0_PMXE (1UL << (31 - 5))
static void dummy_perf(struct pt_regs *regs)
{
^ permalink raw reply
* [PATCH 2.6.10-mm2] Include missing header (PPC)
From: tglx @ 2005-01-09 12:27 UTC (permalink / raw)
To: trini; +Cc: akpm, linuxppc-embedded
Include missing header to avoid implicit function declaration warnings
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
---
init.c | 1 +
1 files changed, 1 insertion(+)
---
Index: 2.6.10-mm2/arch/ppc/mm/init.c
===================================================================
--- 2.6.10-mm2/arch/ppc/mm/init.c (revision 141)
+++ 2.6.10-mm2/arch/ppc/mm/init.c (working copy)
@@ -31,6 +31,7 @@
#include <linux/bootmem.h>
#include <linux/highmem.h>
#include <linux/initrd.h>
+#include <linux/pagemap.h>
#include <asm/pgalloc.h>
#include <asm/prom.h>
^ permalink raw reply
* [PATCH 2.6.10-mm2] Fix idle with interrupts disabled (PPC)
From: tglx @ 2005-01-09 12:22 UTC (permalink / raw)
To: trini; +Cc: akpm, mingo, linuxppc-embedded
The idle-thread-preemption-fix.patch in mm1/2 leads to a stalled box
on PPC machines which do not provide a powersave function and therefor
poll the idle loop with interrupts disabled. The patch reenables interrupts.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
---
idle.c | 7 +++++--
1 files changed, 5 insertions(+), 2 deletions(-)
---
Index: 2.6.10-mm2/arch/ppc/kernel/idle.c
===================================================================
--- 2.6.10-mm2/arch/ppc/kernel/idle.c (revision 141)
+++ 2.6.10-mm2/arch/ppc/kernel/idle.c (working copy)
@@ -41,14 +41,17 @@
if (!need_resched()) {
if (powersave != NULL)
powersave();
+ else {
#ifdef CONFIG_SMP
- else {
set_thread_flag(TIF_POLLING_NRFLAG);
+ local_irq_enable();
while (!need_resched())
barrier();
clear_thread_flag(TIF_POLLING_NRFLAG);
+#else
+ local_irq_enable();
+#endif
}
-#endif
}
if (need_resched())
schedule();
^ permalink raw reply
* U3 G5 AGP support patch (v4)
From: Jerome Glisse @ 2005-01-09 15:26 UTC (permalink / raw)
To: benh, linuxppc-dev, linuxppc64-dev
[-- Attachment #1: Type: text/plain, Size: 204 bytes --]
Hi,
Attached is a patch for the U3 agp bridge. This one just fix some typo
from the previous patch. (DEVICE instead of DEVIEC...).
Signed-off-by: Jerome Glisse <j.glisse@gmail.com>
best,
Jerome Glisse
[-- Attachment #2: uninorth-patch4 --]
[-- Type: application/octet-stream, Size: 10216 bytes --]
diff -Naur linux/drivers/char/agp/Kconfig linux-new/drivers/char/agp/Kconfig
--- linux/drivers/char/agp/Kconfig 2004-12-26 14:39:28.000000000 +0100
+++ linux-new/drivers/char/agp/Kconfig 2005-01-09 14:53:07.000000000 +0100
@@ -155,11 +155,11 @@
default AGP
config AGP_UNINORTH
- tristate "Apple UniNorth AGP support"
+ tristate "Apple UniNorth & U3 AGP support"
depends on AGP && PPC_PMAC
help
This option gives you AGP support for Apple machines with a
- UniNorth bridge.
+ UniNorth or U3 (Apple G5) bridge.
config AGP_EFFICEON
tristate "Transmeta Efficeon support"
diff -Naur linux/drivers/char/agp/uninorth-agp.c linux-new/drivers/char/agp/uninorth-agp.c
--- linux/drivers/char/agp/uninorth-agp.c 2004-12-26 14:39:28.000000000 +0100
+++ linux-new/drivers/char/agp/uninorth-agp.c 2005-01-09 14:43:03.000000000 +0100
@@ -8,8 +8,37 @@
#include <linux/agp_backend.h>
#include <asm/uninorth.h>
#include <asm/pci-bridge.h>
+#include <asm/sections.h>
+#include <asm/prom.h>
#include "agp.h"
+/*
+ * NOTES for uninorth3 (G5 AGP) supports :
+ *
+ * This are redundant with arch/ppc(64)/platforms/pmac_features.c,
+ * we need to know uninorth_rev any other way ?
+ *
+ * There maybe also possibility to have bigger cache line size for
+ * agp (see pmac_pci.c and look for cache line). Need to be investigated
+ * by someone.
+ *
+ * Darwin seems to add UNI_N_CFG_GART_PERFRD for all agp3 controller but
+ * this seems to work without this, so in order to minimize code differences
+ * between AGP2 & AGP3 uninorth, i do not set this.
+ *
+ * PAGE size are hardcoded but this may change, see asm/page.h.
+ *
+ * Jerome Glisse <j.glisse@gmail.com>
+ */
+static struct device_node* uninorth_node __pmacdata;
+static u32 __iomem * uninorth_base __pmacdata;
+static u32 uninorth_rev __pmacdata;
+
+/*
+ * Uninorth reg. access. Note that Uni-N regs are big endian
+ */
+#define UN_REG(r) (uninorth_base + ((r) >> 2))
+
static int uninorth_fetch_size(void)
{
int i;
@@ -17,7 +46,7 @@
struct aper_size_info_32 *values;
pci_read_config_dword(agp_bridge->dev, UNI_N_CFG_GART_BASE, &temp);
- temp &= ~(0xfffff000);
+ temp &= ~PAGE_MASK;
values = A_SIZE_32(agp_bridge->driver->aperture_sizes);
for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
@@ -73,7 +102,7 @@
/* aperture size and gatt addr */
pci_write_config_dword(agp_bridge->dev,
UNI_N_CFG_GART_BASE,
- (agp_bridge->gatt_bus_addr & 0xfffff000)
+ (agp_bridge->gatt_bus_addr & PAGE_MASK)
| current_size->size_value);
/* HACK ALERT
@@ -111,14 +140,56 @@
}
for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
- agp_bridge->gatt_table[j] = cpu_to_le32((mem->memory[i] & 0xfffff000) | 0x00000001UL);
+ agp_bridge->gatt_table[j] = cpu_to_le32((mem->memory[i] &
+ PAGE_MASK) |
+ 0x00000001UL);
flush_dcache_range((unsigned long)__va(mem->memory[i]),
(unsigned long)__va(mem->memory[i])+0x1000);
}
(void)in_le32((volatile u32*)&agp_bridge->gatt_table[pg_start]);
mb();
flush_dcache_range((unsigned long)&agp_bridge->gatt_table[pg_start],
- (unsigned long)&agp_bridge->gatt_table[pg_start + mem->page_count]);
+ (unsigned long)&agp_bridge->gatt_table[pg_start +
+ mem->page_count]);
+
+ uninorth_tlbflush(mem);
+ return 0;
+}
+
+static int uninorth3_insert_memory(struct agp_memory *mem, off_t pg_start,
+ int type)
+{
+ int i, j, num_entries;
+ void *temp;
+
+ temp = agp_bridge->current_size;
+ num_entries = A_SIZE_32(temp)->num_entries;
+
+ if (type != 0 || mem->type != 0)
+ /* We know nothing of memory types */
+ return -EINVAL;
+ if ((pg_start + mem->page_count) > num_entries)
+ return -EINVAL;
+
+ j = pg_start;
+
+ while (j < (pg_start + mem->page_count)) {
+ if (!PGE_EMPTY(agp_bridge, agp_bridge->gatt_table[j]))
+ return -EBUSY;
+ j++;
+ }
+
+ for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
+ agp_bridge->gatt_table[j] = ((mem->memory[i] >> PAGE_SHIFT) |
+ 0x80000000UL);
+ flush_dcache_range((unsigned long)__va(mem->memory[i]),
+ (unsigned long)__va(mem->memory[i])+0x1000);
+ }
+ (void)in_le32((volatile u32*)&agp_bridge->gatt_table[pg_start]);
+ mb();
+ flush_dcache_range((unsigned long)&agp_bridge->gatt_table[pg_start],
+ (unsigned long)&agp_bridge->gatt_table[pg_start +
+ mem->page_count]);
uninorth_tlbflush(mem);
return 0;
@@ -134,7 +205,23 @@
&command);
command = agp_collect_device_status(mode, command);
- command |= 0x100;
+ command |= UNI_N_CFG_GART_ENABLE;
+
+ if(uninorth_rev == 0x21) {
+ /*
+ * Darwin disable AGP 4x on this revision, thus we
+ * may assume it's broken. This is an AGP2 controller.
+ */
+ command &= ~AGPSTAT2_4X;
+ }
+
+ if((uninorth_rev >= 0x30) && (uninorth_rev <= 0x33)) {
+ /*
+ * We need to to set REQ_DEPTH to 7 for U3 versions 1.0, 2.1,
+ * 2.2 and 2.3, Darwin do so.
+ */
+ command |= (7 << AGPSTAT_RQ_DEPTH_SHIFT);
+ }
uninorth_tlbflush(NULL);
@@ -146,11 +233,17 @@
pci_read_config_dword(agp_bridge->dev,
agp_bridge->capndx + PCI_AGP_COMMAND,
&scratch);
- } while ((scratch & 0x100) == 0 && ++timeout < 1000);
- if ((scratch & 0x100) == 0)
+ } while ((scratch & UNI_N_CFG_GART_ENABLE) == 0 && ++timeout < 1000);
+ if ((scratch & UNI_N_CFG_GART_ENABLE) == 0)
printk(KERN_ERR PFX "failed to write UniNorth AGP command reg\n");
- agp_device_command(command, 0);
+ if (agp_bridge->dev->device == PCI_DEVICE_ID_APPLE_U3_AGP) {
+ /* This is an AGP V3 */
+ agp_device_command(command, TRUE);
+ } else {
+ /* AGP V2 */
+ agp_device_command(command, FALSE);
+ }
uninorth_tlbflush(NULL);
}
@@ -258,6 +351,22 @@
{4, 1024, 0, 1}
};
+static struct aper_size_info_32 u3_sizes[8] =
+{
+/*
+ * Not sure that uninorth3 supports that high aperture sizes but it
+ * would strange if it did not :)
+ */
+ {512, 131072, 7, 128},
+ {256, 65536, 6, 64},
+ {128, 32768, 5, 32},
+ {64, 16384, 4, 16},
+ {32, 8192, 3, 8},
+ {16, 4096, 2, 4},
+ {8, 2048, 1, 2},
+ {4, 1024, 0, 1}
+};
+
struct agp_bridge_driver uninorth_agp_driver = {
.owner = THIS_MODULE,
.aperture_sizes = (void *)uninorth_sizes,
@@ -299,6 +408,10 @@
.device_id = PCI_DEVICE_ID_APPLE_UNI_N_AGP2,
.chipset_name = "UniNorth 2",
},
+ {
+ .device_id = PCI_DEVICE_ID_APPLE_U3_AGP,
+ .chipset_name = "U3",
+ },
};
static int __devinit agp_uninorth_probe(struct pci_dev *pdev,
@@ -327,6 +440,33 @@
return -ENODEV;
found:
+ /* Locate core99 Uni-N */
+ uninorth_node = of_find_node_by_name(NULL, "uni-n");
+ /* Locate G5 u3 */
+ if (uninorth_node == NULL) {
+ uninorth_node = of_find_node_by_name(NULL, "u3");
+ }
+ if (uninorth_node && uninorth_node->n_addrs > 0) {
+ unsigned long address = uninorth_node->addrs[0].address;
+ uninorth_base = ioremap(address, 0x40000);
+ uninorth_rev = in_be32(UN_REG(UNI_N_VERSION));
+ }
+
+ /*
+ * Set specific functions & values for agp3 controller.
+ */
+ if (pdev->device == PCI_DEVICE_ID_APPLE_U3_AGP) {
+ uninorth_agp_driver.insert_memory = uninorth3_insert_memory;
+ uninorth_agp_driver.aperture_sizes = (void *)u3_sizes;
+ uninorth_agp_driver.num_aperture_sizes = 8;
+ /*
+ * Some revs have some high bits sets in the version register,
+ * mask it thus they won't mess up with the version number
+ */
+ uninorth_rev &= 0x3f;
+ }
+
+
bridge = agp_alloc_bridge();
if (!bridge)
return -ENOMEM;
diff -Naur linux/drivers/ide/ppc/pmac.c linux-new/drivers/ide/ppc/pmac.c
--- linux/drivers/ide/ppc/pmac.c 2004-12-26 14:39:43.000000000 +0100
+++ linux-new/drivers/ide/ppc/pmac.c 2005-01-09 15:11:58.310123504 +0100
@@ -1527,7 +1527,7 @@
};
static struct pci_device_id pmac_ide_pci_match[] = {
- { PCI_VENDOR_ID_APPLE, PCI_DEVIEC_ID_APPLE_UNI_N_ATA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
+ { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_ATA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
{ PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_IPID_ATA100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
{ PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_K2_ATA100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
};
diff -Naur linux/include/asm/uninorth.h linux-new/include/asm/uninorth.h
--- linux/include/asm/uninorth.h 2004-12-26 14:40:03.000000000 +0100
+++ linux-new/include/asm/uninorth.h 2005-01-09 14:45:27.000000000 +0100
@@ -34,6 +34,11 @@
#define UNI_N_CFG_GART_ENABLE 0x00000100
#define UNI_N_CFG_GART_2xRESET 0x00010000
#define UNI_N_CFG_GART_DISSBADET 0x00020000
+/* The following seems to only be used only on U3 <j.glisse@gmail.com> */
+#define U3_N_CFG_GART_SYNCMODE 0x00040000
+#define U3_N_CFG_GART_PERFRD 0x00080000
+#define U3_N_CFG_GART_B2BGNT 0x00200000
+#define U3_N_CFG_GART_FASTDDR 0x00400000
/* My understanding of UniNorth AGP as of UniNorth rev 1.0x,
* revision 1.5 (x4 AGP) may need further changes.
diff -Naur linux/include/asm-ppc/uninorth.h linux-new/include/asm-ppc/uninorth.h
--- linux/include/asm-ppc/uninorth.h 2004-12-26 14:40:03.000000000 +0100
+++ linux-new/include/asm-ppc/uninorth.h 2005-01-09 14:45:27.000000000 +0100
@@ -34,6 +34,11 @@
#define UNI_N_CFG_GART_ENABLE 0x00000100
#define UNI_N_CFG_GART_2xRESET 0x00010000
#define UNI_N_CFG_GART_DISSBADET 0x00020000
+/* The following seems to only be used only on U3 <j.glisse@gmail.com> */
+#define U3_N_CFG_GART_SYNCMODE 0x00040000
+#define U3_N_CFG_GART_PERFRD 0x00080000
+#define U3_N_CFG_GART_B2BGNT 0x00200000
+#define U3_N_CFG_GART_FASTDDR 0x00400000
/* My understanding of UniNorth AGP as of UniNorth rev 1.0x,
* revision 1.5 (x4 AGP) may need further changes.
diff -Naur linux/include/linux/pci_ids.h linux-new/include/linux/pci_ids.h
--- linux/include/linux/pci_ids.h 2004-12-26 14:40:05.000000000 +0100
+++ linux-new/include/linux/pci_ids.h 2005-01-09 14:46:17.000000000 +0100
@@ -840,8 +840,9 @@
#define PCI_DEVICE_ID_APPLE_UNI_N_AGP15 0x002d
#define PCI_DEVICE_ID_APPLE_UNI_N_FW2 0x0030
#define PCI_DEVICE_ID_APPLE_UNI_N_GMAC2 0x0032
-#define PCI_DEVIEC_ID_APPLE_UNI_N_ATA 0x0033
+#define PCI_DEVICE_ID_APPLE_UNI_N_ATA 0x0033
#define PCI_DEVICE_ID_APPLE_UNI_N_AGP2 0x0034
+#define PCI_DEVICE_ID_APPLE_U3_AGP 0x0059
#define PCI_DEVICE_ID_APPLE_IPID_ATA100 0x003b
#define PCI_DEVICE_ID_APPLE_KEYLARGO_I 0x003e
#define PCI_DEVICE_ID_APPLE_K2_ATA100 0x0043
^ permalink raw reply
* Classic PPC specific ASM (CONFIG_6XX)
From: Jerome Glisse @ 2005-01-09 15:40 UTC (permalink / raw)
To: trini, linuxppc-dev, linuxppc64-dev
[-- Attachment #1: Type: text/plain, Size: 627 bytes --]
Hi,
With 2.6.10 i get a compilation error with disable_6xx_mmu
i guess this is linked with the patch you supplied in december
in arch/ppc/boot/common/util.S
Patch which comment disable_6xx_mmu if flags CONFIG_6XX
not defined. The problem arise in arch/ppc/boot/simple/misc-prep.c
where there is no conditional compilation for this function.
Attached is a patch that use the flags CONFIG_6XX to comment
out call to this function if flags not set.
By the way there is many compilation warning related to PPC with 2.6.10
anyone looking to correct them ?
Signed-off-by: Jerome Glisse <j.glisse@gmail.com>
best,
Jerome Glisse
[-- Attachment #2: disable_6xx-patch --]
[-- Type: application/octet-stream, Size: 855 bytes --]
diff -Nru linux/arch/ppc/boot/simple/misc-prep.c linux-2.6.10/arch/ppc/boot/simple/misc-prep.c
--- linux/arch/ppc/boot/simple/misc-prep.c 2004-12-24 22:33:51.000000000 +0100
+++ linux-2.6.10/arch/ppc/boot/simple/misc-prep.c 2005-01-09 16:30:59.938766448 +0100
@@ -34,7 +34,9 @@
extern void serial_fixups(void);
extern struct bi_record *decompress_kernel(unsigned long load_addr,
int num_words, unsigned long cksum);
+#ifdef CONFIG_6XX
extern void disable_6xx_mmu(void);
+#endif
extern unsigned long mpc10x_get_mem_size(void);
static void
@@ -152,9 +154,11 @@
hold_residual->VitalProductData.Reserved5 = 0xdeadbeef;
}
+ #ifdef CONFIG_6XX
/* Now go and clear out the BATs and ensure that our MSR is
* correct .*/
disable_6xx_mmu();
+ #endif
/* Make r3 be a pointer to the residual data. */
return (unsigned long)hold_residual;
^ permalink raw reply
* Re: [PATCH] raid6: altivec support
From: Olaf Hering @ 2005-01-09 15:13 UTC (permalink / raw)
To: linux-kernel; +Cc: linuxppc-dev
In-Reply-To: <200501082324.j08NOIva030415@hera.kernel.org>
On Sat, Jan 08, Linux Kernel Mailing List wrote:
> ChangeSet 1.2347, 2005/01/08 14:02:27-08:00, hpa@zytor.com
>
> [PATCH] raid6: altivec support
>
> This patch adds Altivec support for RAID-6, if appropriately configured on
> the ppc or ppc64 architectures. Note that it changes the compile flags for
> ppc64 in order to handle -maltivec correctly; this change was vetted on the
> ppc64 mailing list and OK'd by paulus.
This fails to compile on ppc, enable_kernel_altivec() is an exported but
undeclared function. cpu_features is also missing.
drivers/md/raid6altivec1.c: In function `raid6_altivec1_gen_syndrome':
drivers/md/raid6altivec1.c:99: warning: implicit declaration of function `enable_kernel_altivec'
drivers/md/raid6altivec1.c: In function `raid6_have_altivec':
drivers/md/raid6altivec1.c:111: error: request for member `cpu_features' in something not a structure or union
drivers/md/raid6altivec2.c: In function `raid6_altivec2_gen_syndrome':
drivers/md/raid6altivec2.c:110: warning: implicit declaration of function `enable_kernel_altivec'
There are a few more exported symbols without declaration:
__ashldi3
__ashrdi3
__lshrdi3
enable_kernel_spe
fec_register_ph
fec_unregister_ph
idma_pci9_read
idma_pci9_read_le
local_irq_disable_end
local_irq_enable_end
local_irq_restore_end
local_save_flags_ptr_end
ocp_bus_type
ppc4xx_set_dma_addr
I'm not sure if the EXPORT_SYMBOL should be dropped for them, they have
no users in the current kernel.
--- ../linux-2.6.10-bk12/include/asm-ppc/system.h 2004-12-24 22:34:32.000000000 +0100
+++ ./include/asm-ppc/system.h 2005-01-09 15:53:32.338569809 +0100
@@ -76,6 +76,7 @@ extern void giveup_fpu(struct task_struc
extern void enable_kernel_fp(void);
extern void giveup_altivec(struct task_struct *);
extern void load_up_altivec(struct task_struct *);
+extern void enable_kernel_altivec(void);
extern void giveup_spe(struct task_struct *);
extern void load_up_spe(struct task_struct *);
extern int fix_alignment(struct pt_regs *);
^ permalink raw reply
* Re: U3 G5 AGP support patch (v4)
From: Christoph Hellwig @ 2005-01-09 16:06 UTC (permalink / raw)
To: Jerome Glisse; +Cc: linuxppc64-dev, linuxppc-dev
In-Reply-To: <4240b916050109072621440269@mail.gmail.com>
+static struct device_node* uninorth_node __pmacdata;
+static u32 __iomem * uninorth_base __pmacdata;
static struct device_node *uninorth_node __pmacdata;
static u32 __iomem *uninorth_base __pmacdata;
+ if(uninorth_rev == 0x21) {
if (uninorth_rev == 0x21) {
+ if((uninorth_rev >= 0x30) && (uninorth_rev <= 0x33)) {
if ((uninorth_rev >= 0x30) && (uninorth_rev <= 0x33)) {
+ if (agp_bridge->dev->device == PCI_DEVICE_ID_APPLE_U3_AGP) {
+ /* This is an AGP V3 */
+ agp_device_command(command, TRUE);
+ } else {
+ /* AGP V2 */
+ agp_device_command(command, FALSE);
+ }
double-indentation, also please use 1/0 instead of TRUE/FALSE.
+static struct aper_size_info_32 u3_sizes[8] =
+{
+/*
+ * Not sure that uninorth3 supports that high aperture sizes but it
+ * would strange if it did not :)
+ */
comment before the struct declearation, please, aka
/*
* Not sure that uninorth3 supports that high aperture sizes but it
* would strange if it did not :)
*/
static struct aper_size_info_32 u3_sizes[8] = {
+ uninorth_node = of_find_node_by_name(NULL, "uni-n");
+ /* Locate G5 u3 */
+ if (uninorth_node == NULL) {
+ uninorth_node = of_find_node_by_name(NULL, "u3");
+ }
/* Locate G5 u3 */
uninorth_node = of_find_node_by_name(NULL, "uni-n");
if (!uninorth_node)
uninorth_node = of_find_node_by_name(NULL, "u3");
+ /*
+ * Set specific functions & values for agp3 controller.
+ */
+ if (pdev->device == PCI_DEVICE_ID_APPLE_U3_AGP) {
+ uninorth_agp_driver.insert_memory = uninorth3_insert_memory;
+ uninorth_agp_driver.aperture_sizes = (void *)u3_sizes;
+ uninorth_agp_driver.num_aperture_sizes = 8;
Please delcare separate driver instance instead of overriding.
And asm-ppc64 is still missing an agp.h, no?
^ permalink raw reply
* Re: U3 G5 AGP support patch (v4)
From: Jerome Glisse @ 2005-01-09 17:46 UTC (permalink / raw)
To: Christoph Hellwig; +Cc: linuxppc64-dev, linuxppc-dev
In-Reply-To: <20050109160614.GA22839@lst.de>
[-- Attachment #1: Type: text/plain, Size: 335 bytes --]
> Please delcare separate driver instance instead of overriding.
I hope new patch follow codestyle ? :)
> And asm-ppc64 is still missing an agp.h, no?
Maybe, some one with better knowledge may tell us more on that :)
Anyway BenH tell me that there is still pending issue with agp & a
potential cache aliasing.
best,
Jerome Glisse
[-- Attachment #2: uninorth-patch5 --]
[-- Type: application/octet-stream, Size: 11216 bytes --]
diff -Nru linux/drivers/char/agp/Kconfig linux-new/drivers/char/agp/Kconfig
--- linux/drivers/char/agp/Kconfig 2004-12-26 14:39:28.000000000 +0100
+++ linux-new/drivers/char/agp/Kconfig 2005-01-09 14:53:07.000000000 +0100
@@ -155,11 +155,11 @@
default AGP
config AGP_UNINORTH
- tristate "Apple UniNorth AGP support"
+ tristate "Apple UniNorth & U3 AGP support"
depends on AGP && PPC_PMAC
help
This option gives you AGP support for Apple machines with a
- UniNorth bridge.
+ UniNorth or U3 (Apple G5) bridge.
config AGP_EFFICEON
tristate "Transmeta Efficeon support"
diff -Nru linux/drivers/char/agp/uninorth-agp.c linux-new/drivers/char/agp/uninorth-agp.c
--- linux/drivers/char/agp/uninorth-agp.c 2004-12-26 14:39:28.000000000 +0100
+++ linux-new/drivers/char/agp/uninorth-agp.c 2005-01-09 18:31:51.000000000 +0100
@@ -8,8 +8,37 @@
#include <linux/agp_backend.h>
#include <asm/uninorth.h>
#include <asm/pci-bridge.h>
+#include <asm/sections.h>
+#include <asm/prom.h>
#include "agp.h"
+/*
+ * NOTES for uninorth3 (G5 AGP) supports :
+ *
+ * This are redundant with arch/ppc(64)/platforms/pmac_features.c,
+ * we need to know uninorth_rev any other way ?
+ *
+ * There maybe also possibility to have bigger cache line size for
+ * agp (see pmac_pci.c and look for cache line). Need to be investigated
+ * by someone.
+ *
+ * Darwin seems to add UNI_N_CFG_GART_PERFRD for all agp3 controller but
+ * this seems to work without this, so in order to minimize code differences
+ * between AGP2 & AGP3 uninorth, i do not set this.
+ *
+ * PAGE size are hardcoded but this may change, see asm/page.h.
+ *
+ * Jerome Glisse <j.glisse@gmail.com>
+ */
+static struct device_node *uninorth_node __pmacdata;
+static u32 __iomem *uninorth_base __pmacdata;
+static u32 uninorth_rev __pmacdata;
+
+/*
+ * Uninorth reg. access. Note that Uni-N regs are big endian
+ */
+#define UN_REG(r) (uninorth_base + ((r) >> 2))
+
static int uninorth_fetch_size(void)
{
int i;
@@ -17,7 +46,7 @@
struct aper_size_info_32 *values;
pci_read_config_dword(agp_bridge->dev, UNI_N_CFG_GART_BASE, &temp);
- temp &= ~(0xfffff000);
+ temp &= ~PAGE_MASK;
values = A_SIZE_32(agp_bridge->driver->aperture_sizes);
for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
@@ -73,7 +102,7 @@
/* aperture size and gatt addr */
pci_write_config_dword(agp_bridge->dev,
UNI_N_CFG_GART_BASE,
- (agp_bridge->gatt_bus_addr & 0xfffff000)
+ (agp_bridge->gatt_bus_addr & PAGE_MASK)
| current_size->size_value);
/* HACK ALERT
@@ -111,14 +140,55 @@
}
for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
- agp_bridge->gatt_table[j] = cpu_to_le32((mem->memory[i] & 0xfffff000) | 0x00000001UL);
+ agp_bridge->gatt_table[j] = cpu_to_le32((mem->memory[i] &
+ PAGE_MASK) |
+ 0x00000001UL);
+ flush_dcache_range((unsigned long)__va(mem->memory[i]),
+ (unsigned long)__va(mem->memory[i])+0x1000);
+ }
+ (void)in_le32((volatile u32*)&agp_bridge->gatt_table[pg_start]);
+ mb();
+ flush_dcache_range((unsigned long)&agp_bridge->gatt_table[pg_start],
+ (unsigned long)&agp_bridge->gatt_table[pg_start +
+ mem->page_count]);
+
+ uninorth_tlbflush(mem);
+ return 0;
+}
+
+static int u3_insert_memory(struct agp_memory *mem, off_t pg_start, int type)
+{
+ int i, j, num_entries;
+ void *temp;
+
+ temp = agp_bridge->current_size;
+ num_entries = A_SIZE_32(temp)->num_entries;
+
+ if (type != 0 || mem->type != 0)
+ /* We know nothing of memory types */
+ return -EINVAL;
+ if ((pg_start + mem->page_count) > num_entries)
+ return -EINVAL;
+
+ j = pg_start;
+
+ while (j < (pg_start + mem->page_count)) {
+ if (!PGE_EMPTY(agp_bridge, agp_bridge->gatt_table[j]))
+ return -EBUSY;
+ j++;
+ }
+
+ for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
+ agp_bridge->gatt_table[j] = ((mem->memory[i] >> PAGE_SHIFT) |
+ 0x80000000UL);
flush_dcache_range((unsigned long)__va(mem->memory[i]),
(unsigned long)__va(mem->memory[i])+0x1000);
}
(void)in_le32((volatile u32*)&agp_bridge->gatt_table[pg_start]);
mb();
flush_dcache_range((unsigned long)&agp_bridge->gatt_table[pg_start],
- (unsigned long)&agp_bridge->gatt_table[pg_start + mem->page_count]);
+ (unsigned long)&agp_bridge->gatt_table[pg_start +
+ mem->page_count]);
uninorth_tlbflush(mem);
return 0;
@@ -134,7 +204,23 @@
&command);
command = agp_collect_device_status(mode, command);
- command |= 0x100;
+ command |= UNI_N_CFG_GART_ENABLE;
+
+ if (uninorth_rev == 0x21) {
+ /*
+ * Darwin disable AGP 4x on this revision, thus we
+ * may assume it's broken. This is an AGP2 controller.
+ */
+ command &= ~AGPSTAT2_4X;
+ }
+
+ if ((uninorth_rev >= 0x30) && (uninorth_rev <= 0x33)) {
+ /*
+ * We need to to set REQ_DEPTH to 7 for U3 versions 1.0, 2.1,
+ * 2.2 and 2.3, Darwin do so.
+ */
+ command |= (7 << AGPSTAT_RQ_DEPTH_SHIFT);
+ }
uninorth_tlbflush(NULL);
@@ -146,11 +232,17 @@
pci_read_config_dword(agp_bridge->dev,
agp_bridge->capndx + PCI_AGP_COMMAND,
&scratch);
- } while ((scratch & 0x100) == 0 && ++timeout < 1000);
- if ((scratch & 0x100) == 0)
+ } while ((scratch & UNI_N_CFG_GART_ENABLE) == 0 && ++timeout < 1000);
+ if ((scratch & UNI_N_CFG_GART_ENABLE) == 0)
printk(KERN_ERR PFX "failed to write UniNorth AGP command reg\n");
- agp_device_command(command, 0);
+ if (agp_bridge->dev->device == PCI_DEVICE_ID_APPLE_U3_AGP) {
+ /* This is an AGP V3 */
+ agp_device_command(command, 1);
+ } else {
+ /* AGP V2 */
+ agp_device_command(command, 0);
+ }
uninorth_tlbflush(NULL);
}
@@ -258,6 +350,22 @@
{4, 1024, 0, 1}
};
+/*
+ * Not sure that u3 supports that high aperture sizes but it
+ * would strange if it did not :)
+ */
+static struct aper_size_info_32 u3_sizes[8] =
+{
+ {512, 131072, 7, 128},
+ {256, 65536, 6, 64},
+ {128, 32768, 5, 32},
+ {64, 16384, 4, 16},
+ {32, 8192, 3, 8},
+ {16, 4096, 2, 4},
+ {8, 2048, 1, 2},
+ {4, 1024, 0, 1}
+};
+
struct agp_bridge_driver uninorth_agp_driver = {
.owner = THIS_MODULE,
.aperture_sizes = (void *)uninorth_sizes,
@@ -282,6 +390,30 @@
.cant_use_aperture = 1,
};
+struct agp_bridge_driver u3_agp_driver = {
+ .owner = THIS_MODULE,
+ .aperture_sizes = (void *)u3_sizes,
+ .size_type = U32_APER_SIZE,
+ .num_aperture_sizes = 8,
+ .configure = uninorth_configure,
+ .fetch_size = uninorth_fetch_size,
+ .cleanup = uninorth_cleanup,
+ .tlb_flush = uninorth_tlbflush,
+ .mask_memory = agp_generic_mask_memory,
+ .masks = NULL,
+ .cache_flush = null_cache_flush,
+ .agp_enable = uninorth_agp_enable,
+ .create_gatt_table = uninorth_create_gatt_table,
+ .free_gatt_table = uninorth_free_gatt_table,
+ .insert_memory = u3_insert_memory,
+ .remove_memory = agp_generic_remove_memory,
+ .alloc_by_type = agp_generic_alloc_by_type,
+ .free_by_type = agp_generic_free_by_type,
+ .agp_alloc_page = agp_generic_alloc_page,
+ .agp_destroy_page = agp_generic_destroy_page,
+ .cant_use_aperture = 1,
+};
+
static struct agp_device_ids uninorth_agp_device_ids[] __devinitdata = {
{
.device_id = PCI_DEVICE_ID_APPLE_UNI_N_AGP,
@@ -299,6 +431,10 @@
.device_id = PCI_DEVICE_ID_APPLE_UNI_N_AGP2,
.chipset_name = "UniNorth 2",
},
+ {
+ .device_id = PCI_DEVICE_ID_APPLE_U3_AGP,
+ .chipset_name = "U3",
+ },
};
static int __devinit agp_uninorth_probe(struct pci_dev *pdev,
@@ -327,11 +463,35 @@
return -ENODEV;
found:
+ /* Set revision to 0 if we could not read it. */
+ uninorth_rev = 0;
+ /* Locate core99 Uni-N */
+ uninorth_node = of_find_node_by_name(NULL, "uni-n");
+ /* Locate G5 u3 */
+ if (uninorth_node == NULL) {
+ uninorth_node = of_find_node_by_name(NULL, "u3");
+ }
+ if (uninorth_node && uninorth_node->n_addrs > 0) {
+ unsigned long address = uninorth_node->addrs[0].address;
+ uninorth_base = ioremap(address, 0x40000);
+ uninorth_rev = in_be32(UN_REG(UNI_N_VERSION));
+ /*
+ * Some revs have some high bits sets in the version register,
+ * mask it thus they won't mess up with the version number
+ */
+ uninorth_rev &= 0x3f;
+ }
+
bridge = agp_alloc_bridge();
if (!bridge)
return -ENOMEM;
- bridge->driver = &uninorth_agp_driver;
+ if (pdev->device == PCI_DEVICE_ID_APPLE_U3_AGP) {
+ bridge->driver = &u3_agp_driver;
+ } else {
+ bridge->driver = &uninorth_agp_driver;
+ }
+
bridge->dev = pdev;
bridge->capndx = cap_ptr;
diff -Nru linux/drivers/ide/ppc/pmac.c linux-new/drivers/ide/ppc/pmac.c
--- linux/drivers/ide/ppc/pmac.c 2004-12-26 14:39:43.000000000 +0100
+++ linux-new/drivers/ide/ppc/pmac.c 2005-01-09 15:11:58.000000000 +0100
@@ -1527,7 +1527,7 @@
};
static struct pci_device_id pmac_ide_pci_match[] = {
- { PCI_VENDOR_ID_APPLE, PCI_DEVIEC_ID_APPLE_UNI_N_ATA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
+ { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_ATA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
{ PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_IPID_ATA100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
{ PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_K2_ATA100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
};
diff -Nru linux/include/asm/uninorth.h linux-new/include/asm/uninorth.h
--- linux/include/asm/uninorth.h 2004-12-26 14:40:03.000000000 +0100
+++ linux-new/include/asm/uninorth.h 2005-01-09 14:45:27.000000000 +0100
@@ -34,6 +34,11 @@
#define UNI_N_CFG_GART_ENABLE 0x00000100
#define UNI_N_CFG_GART_2xRESET 0x00010000
#define UNI_N_CFG_GART_DISSBADET 0x00020000
+/* The following seems to only be used only on U3 <j.glisse@gmail.com> */
+#define U3_N_CFG_GART_SYNCMODE 0x00040000
+#define U3_N_CFG_GART_PERFRD 0x00080000
+#define U3_N_CFG_GART_B2BGNT 0x00200000
+#define U3_N_CFG_GART_FASTDDR 0x00400000
/* My understanding of UniNorth AGP as of UniNorth rev 1.0x,
* revision 1.5 (x4 AGP) may need further changes.
diff -Nru linux/include/asm-ppc/uninorth.h linux-new/include/asm-ppc/uninorth.h
--- linux/include/asm-ppc/uninorth.h 2004-12-26 14:40:03.000000000 +0100
+++ linux-new/include/asm-ppc/uninorth.h 2005-01-09 14:45:27.000000000 +0100
@@ -34,6 +34,11 @@
#define UNI_N_CFG_GART_ENABLE 0x00000100
#define UNI_N_CFG_GART_2xRESET 0x00010000
#define UNI_N_CFG_GART_DISSBADET 0x00020000
+/* The following seems to only be used only on U3 <j.glisse@gmail.com> */
+#define U3_N_CFG_GART_SYNCMODE 0x00040000
+#define U3_N_CFG_GART_PERFRD 0x00080000
+#define U3_N_CFG_GART_B2BGNT 0x00200000
+#define U3_N_CFG_GART_FASTDDR 0x00400000
/* My understanding of UniNorth AGP as of UniNorth rev 1.0x,
* revision 1.5 (x4 AGP) may need further changes.
diff -Nru linux/include/linux/pci_ids.h linux-new/include/linux/pci_ids.h
--- linux/include/linux/pci_ids.h 2004-12-26 14:40:05.000000000 +0100
+++ linux-new/include/linux/pci_ids.h 2005-01-09 14:46:17.000000000 +0100
@@ -840,8 +840,9 @@
#define PCI_DEVICE_ID_APPLE_UNI_N_AGP15 0x002d
#define PCI_DEVICE_ID_APPLE_UNI_N_FW2 0x0030
#define PCI_DEVICE_ID_APPLE_UNI_N_GMAC2 0x0032
-#define PCI_DEVIEC_ID_APPLE_UNI_N_ATA 0x0033
+#define PCI_DEVICE_ID_APPLE_UNI_N_ATA 0x0033
#define PCI_DEVICE_ID_APPLE_UNI_N_AGP2 0x0034
+#define PCI_DEVICE_ID_APPLE_U3_AGP 0x0059
#define PCI_DEVICE_ID_APPLE_IPID_ATA100 0x003b
#define PCI_DEVICE_ID_APPLE_KEYLARGO_I 0x003e
#define PCI_DEVICE_ID_APPLE_K2_ATA100 0x0043
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