* Re: Linux processes, tempfs and programs
From: Eugene Surovegin @ 2005-02-18 0:59 UTC (permalink / raw)
To: Stephen Williams, linuxppc-embedded
In-Reply-To: <20050218004327.GB10915@gate.ebshome.net>
On Thu, Feb 17, 2005 at 04:43:27PM -0800, Eugene Surovegin wrote:
> On Thu, Feb 17, 2005 at 03:38:05PM -0800, Stephen Williams wrote:
> > My embedded system is structured such that the main user-mode
> > processes that are being run are downloaded and executed on demand.
> > I'm currently downloading the executable to an ext3 system on the
> > CompactFlash, but there is really no reason to use non-volatile
> > memory so I'm thinking to download to a tempfs directory and
> > execute from there.
> >
> > But if I do that, I want to remove the program from the directory
> > after I start it, so that the file does not take up ram space. Will
> > that actually work? I'm using exec(2) to execute the program file
> > wherever it is downloaded. Will a subsequent unlink of the file
> > have a result, or will the file continue to take up space as
> > backing store for the executable?
>
> I think unlink will remove the file from directory (so you won't be
> able to see it with ls), but it will still continue to to take space -
> you're right it will be used as backing store, at least for read-only
> segments, which can be discarded if memory is tight. Even if you mlock
> all executable in memory, I think there will be still at least one
> reference to this file, which will prevent freeing tmpfs memory.
A little correction, according to tmpfs doc, it lives completely in
page cache, so I think memory is not wasted for unmodified sections of
the loaded file (e.g. a second copy, when file is executed and loaded
into user-space, isn't being made).
But as usual, make some measurements first :)
--
Eugene.
^ permalink raw reply
* Freeing unused kernel memory: 56k init - hang problem
From: srinivas.surabhi @ 2005-02-18 4:16 UTC (permalink / raw)
To: wd, linuxppc-embedded
[-- Attachment #1: Type: text/plain, Size: 1022 bytes --]
Is there any patch for ppc-8260 for the hang problem after the following output on the serial console.
"Freeing unused kernel memory: 56k init"
Thanks & Rgds
SS
________________________________
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^ permalink raw reply
* Re: Freeing unused kernel memory: 56k init - hang problem
From: David Jander @ 2005-02-18 8:23 UTC (permalink / raw)
To: linuxppc-embedded
In-Reply-To: <EF9B29C78F41FA488927FCBC7750AF0E08DA18@hyd-mdp-msg.wipro.com>
On Friday 18 February 2005 05:16, srinivas.surabhi@wipro.com wrote:
> Is there any patch for ppc-8260 for the hang problem after the following
> output on the serial console.
>
> "Freeing unused kernel memory: 56k init"
I don't know about any known "hang problem" or such, but at that point,
normally your root filesystem is mounted and /sbin/init is executed. So if it
hangs there, probably something is wrong with your root filesystem.
Could you tell more about what board/kernel/sdk/etc... you are using? Where is
"/" supposed to be mounted from? NFS? flash? initrd?
Greetings,
--
David Jander
Protonic Holland.
^ permalink raw reply
* telnet and ioremap probs seem to be solved
From: Vijay Padiyar @ 2005-02-18 8:40 UTC (permalink / raw)
To: LinuxPPC Support, BusyBox Support; +Cc: David Bruce, Achim Machura
Hi all
Just thought I'd let everyone know regarding the status of the problems I
was facing.
The first problem I was facing was telnetd getting stuck whenever a
significant amount of data transfer was happening between the target and a
remote host. It turned out that the problem was related to MTU size.
I now set the MTU size to 192 bytes and all seems to be fine now.
ifconfig eth0 192.168.144.222 netmask 255.255.255.0 mtu 192
This seems to be ok so far.
The second problem was about not being able to access ioremapped memory. As
some of you suggested on this forum, it turned out to be a problem with the
MMU not having been configured to access that memory region. In other words,
we set the appropriate ORx and BRx registers to map that memory range, and
then the ioremapped memory was accessible perfectly fine. So that's that.
Thanks to all of you guys for your invaluable assistance!
Regards
Vijay Padiyar
http://www.vijaypadiyar.eu.tf
^ permalink raw reply
* Freeing unused kernel memory: 56k init
From: srinivas.surabhi @ 2005-02-18 9:11 UTC (permalink / raw)
To: linuxppc-embedded
[-- Attachment #1: Type: text/plain, Size: 3511 bytes --]
The latest update is that the init was also found in one of the packages. So now I am not facing init not found problem . But there was a hung problem, once the init is invoked .. Please find the output below...
RAMDISK: Compressed image found at block 0
Freeing initrd memory: 1235k freed
kjournald starting. Commit interval 5 seconds
EXT3-fs: mounted filesystem with ordered data mode.
VFS: Mounted root (ext3 filesystem) readonly.
Mounted devfs on /dev
Freeing unused kernel memory: 56k init
< there is no output after the above statement.....>
Thanks & Regards
Surabhi Srinivas
________________________________
From: Wolfgang Denk [mailto:wd@denx.de]
Sent: Thu 2/17/2005 5:12 PM
To: Srinivas Surabhi (WT01 - EMBEDDED & PRODUCT ENGINEERING SOLUTIONS)
Cc: linuxppc-embedded@ozlabs.org
Subject: Re: Mounta Vista Linux prompt on serial console
In message <EF9B29C78F41FA488927FCBC7750AF0E08DA14@hyd-mdp-msg.wipro.com> you wrote:
>
> But the problem is that it was stopping at
>
> "No init found. Try passing init= option to kernel". Before that there
> were no errors. Everthing looks fine Mounted VFS root file system was also
Fine. So you can mount the root filesystem, but it obviously does not
contain all the required files.
> seen. >From the net I understood is that the fstab file was the cause. So
> edited the filesytem parameter for / as /dev/ram earlier it used to be
> /dev/root.
No. /etc/fstab has absolutley nothing to do with your problem. The
kernel cannot start the init porocess - make sure init is in the
filesystem, plus all required libraries.
> So please tell me whether the given fstab file will suffice? The filesystem
This is completley unrelated.
> 2. I have one more doubt /sbin/init utility comes with what package?
> Because in /sbin directory although the init binary is present, not shown
> in the file system heirarchy view. For eg. if I select DHCPD package then
> able to see dhcpd related binary in the /sbin similarly my question was
> which package has to be selected to have init included.
Please contact MV support. I have no idea how they package their
distribution, or how their config tools might work. You paid for
their stuff, so ask _them_.
Best regards,
Wolfgang Denk
--
See us @ Embedded World, Nuremberg, Feb 22 - 24, Hall 10.0 Booth 310
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de
The most exciting phrase to hear in science, the one that heralds new
discoveries, is not "Eureka!" (I found it!) but "That's funny ..."
-- Isaac Asimov
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^ permalink raw reply
* Re: [PATCH] Heartbeat LED for iBook
From: Nico Schottelius @ 2005-02-18 11:13 UTC (permalink / raw)
To: Segher Boessenkool; +Cc: linuxppc-dev list
In-Reply-To: <8f293b6dbedd2ae1a825608a48a0604b@kernel.crashing.org>
[-- Attachment #1: Type: text/plain, Size: 717 bytes --]
Segher Boessenkool [Mon, Feb 14, 2005 at 02:14:40PM +0100]:
> >Btw, howto control it via /dev/adb? Can you point me to a document
> >which explains that?
>
> Write a byte 0x06 followed by the PMU packet (all in one write());
> read back the PMU reply (all in one read()).
What exactly does 0x06 mean? Flash led? Isn't there some kind of
"bright-led" "5V,12V,24V" settings available? I mean I want to be able
to change the brightness.
And what is the PMU packet? One Byte, two byte, value 0x2342?
Please point me to a FM about adb.
Nico
--
Keep it simple & stupid, use what's available.
Please use pgp encryption: 8D0E 27A4 is my id.
http://nico.schotteli.us | http://linux.schottelius.org
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^ permalink raw reply
* Re: [PATCH] Heartbeat LED for iBook
From: Segher Boessenkool @ 2005-02-18 12:11 UTC (permalink / raw)
To: Nico Schottelius; +Cc: linuxppc-dev list
In-Reply-To: <20050218111304.GH5801@schottelius.org>
>>> Btw, howto control it via /dev/adb? Can you point me to a document
>>> which explains that?
>>
>> Write a byte 0x06 followed by the PMU packet (all in one write());
>> read back the PMU reply (all in one read()).
>
> What exactly does 0x06 mean?
6 just means "send to PMU". It is a Linux thing, nothing to do
with the PMU itself.
> Flash led? Isn't there some kind of
> "bright-led" "5V,12V,24V" settings available? I mean I want to be able
> to change the brightness.
You can't change brightness on a LED. You can however make it blink,
say, a few hundred times per second, and change the duty-cycle.
> And what is the PMU packet? One Byte, two byte, value 0x2342?
Dunno what the exact command for this is.
> Please point me to a FM about adb.
What is a FM? And it has nothing to do with ADB.
Segher
^ permalink raw reply
* Re: [PATCH] Heartbeat LED for iBook
From: Nico Schottelius @ 2005-02-18 12:20 UTC (permalink / raw)
To: Segher Boessenkool; +Cc: linuxppc-dev list
In-Reply-To: <f585c9c6e4bdfbba6dcaafc96b7c0607@kernel.crashing.org>
[-- Attachment #1: Type: text/plain, Size: 1053 bytes --]
Segher Boessenkool [Fri, Feb 18, 2005 at 01:11:00PM +0100]:
> >>>Btw, howto control it via /dev/adb? Can you point me to a document
> >>>which explains that?
> >>
> >>Write a byte 0x06 followed by the PMU packet (all in one write());
> >>read back the PMU reply (all in one read()).
> >
> >What exactly does 0x06 mean?
>
> 6 just means "send to PMU". It is a Linux thing, nothing to do
> with the PMU itself.
thought something like that.
> >Flash led? Isn't there some kind of
> >"bright-led" "5V,12V,24V" settings available? I mean I want to be able
> >to change the brightness.
>
> You can't change brightness on a LED. You can however make it blink,
> say, a few hundred times per second, and change the duty-cycle.
Ok, that's what I meant.
> >Please point me to a FM about adb.
>
> What is a FM? And it has nothing to do with ADB.
Well, it's the last part of RTFM, so I was asking
for the "fine manual", the documentation to ADB/PMU. So I can
lookup the commands I need for setting the led on/off.
Nico
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^ permalink raw reply
* Re: [PATCH] Heartbeat LED for iBook
From: Segher Boessenkool @ 2005-02-18 13:00 UTC (permalink / raw)
To: Nico Schottelius; +Cc: linuxppc-dev list
In-Reply-To: <20050218122009.GK5801@schottelius.org>
> Well, it's the last part of RTFM, so I was asking
> for the "fine manual", the documentation to ADB/PMU. So I can
> lookup the commands I need for setting the led on/off.
There is no manual. You can look at some Darwin source code,
I guess, or there is some code in Linux to do this as well, IIRC.
Segher
^ permalink raw reply
* ibook-led (finished) (was: [PATCH] Heartbeat LED for iBook)
From: Nico Schottelius @ 2005-02-18 14:57 UTC (permalink / raw)
To: Joerg Dorchain; +Cc: linuxppc-dev list
In-Reply-To: <20050127163606.GN14866@Redstar.dorchain.net>
[-- Attachment #1: Type: text/plain, Size: 442 bytes --]
Hello everybody!
Thank you everybody for the help.
I found the correct bytes in the beginning of this thread and wrote
ibook-led (should work with powerbooks, too).
The program works as following:
ei nico # ./ibook-led
ibook-led <0,1,2> <delay>
0: switch led off
1: switch led on
2: switch led on for <delay> useconds
The source code can be found on http://linux.schottelius.org/hacks/.
Sincerly,
Nico
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^ permalink raw reply
* AW: bdi2000 debugging
From: Martin Krause @ 2005-02-18 15:44 UTC (permalink / raw)
To: Matej Kupljen, Sylvain Munaut; +Cc: linuxppc-embedded
Hi,
matej.kupljen@ultra.si wrote:
> > L25R marking on the top means rev 1.2 IIRC. That's the one I have.
> > Also, if you have a rev 2, you're lucky, I'd like one ;)
>=20
> Nope, mine has: 2L25R
Mine also has a 2L25R marking, and it is rev 1.2
U-Boot reads the System-On-Chip Version Register (SVR) and prints
the version information while booting:
U-Boot 1.1.3 (Feb 16 2005 - 10:38:30)
CPU: MPC5200 v1.2 at 396 MHz
Bus 132 MHz, IPB 132 MHz, PCI 66 MHz
...
I don't think rev 2 is released officially, yet.
Regards,
Martin
^ permalink raw reply
* Re: 440GX interrupt
From: Matt Porter @ 2005-02-18 15:56 UTC (permalink / raw)
To: Barbier, Renaud (GE Infrastructure), linuxppc-embedded,
Matt Porter
In-Reply-To: <20050217233605.GA10915@gate.ebshome.net>
On Thu, Feb 17, 2005 at 03:36:05PM -0800, Eugene Surovegin wrote:
> On Thu, Feb 17, 2005 at 02:54:14PM -0800, Eugene Surovegin wrote:
> > Probably it's a race which cannot be avoided anyway because external
> > IRQs are completely async, and your version of ppc4xx_pic.c just has a
> > bug. I'll think about it a little more.
>
> Uhh, yes, I think it's a bug in 4xx version of disable_irq.
>
> We have to ACK parent UIC after disabling IRQ to prevent false
> triggering in case this IRQ was already pending during disable_irq
> call.
>
> Here is a patch against current 2.6, so you can get an idea what I'm
> talking about :):
Gah, yes. Please add the sign off line and it can go in the mainline.
-Matt
^ permalink raw reply
* oops in process_backlog : kernel 2.6.9
From: Philip Van-Houtte @ 2005-02-18 17:03 UTC (permalink / raw)
To: linuxppc-dev, linuxppc-embedded
I have an embedded application, running a stock kernel 2.6.9, on an 8240
receiving UDP. Occasionaly after a (re)boot the system will oops after
opening (socket/bind) its first connection just as the traffic comes in.
It always occurs after the call to netif_receive_skb has competed.
Oops: kernel access of bad area, sig: 11 [#1]
PREEMPT
NIP: C021FD14 LR: C021FCB4 SP: C3049C70 REGS: c3049bc0 TRAP: 0300 Tainted: P
MSR: 00001032 EE: 0 PR: 0 FP: 0 ME: 1 IR/DR: 11
DAR: 00003CAE, DSISR: 20000000
TASK = c309d050[162] 'rtp_daemon' THREAD: c3048000Last syscall: 102
GPR00: 00001032 C3049C70 C309D050 00000000 C3049B50 00000000 00000000 C5023E04
GPR08: 00000002 0000000D 00000000 C036496C 2010C002 00000000 037FB000 038D0000
GPR16: 00002020 00000000 10000000 7FFFF960 00000001 00000000 C0300000 C3049CB8
GPR24: FFFBDE37 C0364960 C0364988 00000040 00000000 C0429800 00000001 C036496C
NIP [c021fd14] process_backlog+0x108/0x188
LR [c021fcb4] process_backlog+0xa8/0x188
Call trace:
[c021fe2c] net_rx_action+0x98/0x178
[c011fdd0] __do_softirq+0xdc/0xec
[c011fe38] do_softirq+0x58/0x5c
[c0106188] do_IRQ+0xdc/0xe0
[c01048ec] ret_from_except+0x0/0x14
[c0217f68] lock_sock+0x6c/0x84
[c02152ac] sys_bind+0x70/0x94
[c0215f58] sys_socketcall+0xc8/0x1d8
[c0104240] ret_from_syscall+0x0/0x44
Kernel panic - not syncing: Aiee, killing interrupt handler!
<0>Rebooting in 180 seconds..
Any insights/work-arounds/ would be appreciated.
^ permalink raw reply
* [PATCH] emac: filter illegal frame sizes
From: Matt Porter @ 2005-02-18 17:12 UTC (permalink / raw)
To: jgarzik; +Cc: netdev, linuxppc-embedded
Fix to drop frames that are too large for the current MTU.
Signed-off-by: Matt Porter <mporter@kernel.crashing.org>
===== drivers/net/ibm_emac/ibm_emac_core.c 1.9 vs edited =====
--- 1.9/drivers/net/ibm_emac/ibm_emac_core.c 2005-01-20 13:25:10 -07:00
+++ edited/drivers/net/ibm_emac/ibm_emac_core.c 2005-02-18 09:23:08 -07:00
@@ -665,14 +665,21 @@
fep->rx_skb[i]->dev = dev;
fep->rx_skb[i]->protocol =
eth_type_trans(fep->rx_skb[i], dev);
- error = netif_rx(fep->rx_skb[i]);
- if ((error == NET_RX_DROP) ||
- (error == NET_RX_BAD)) {
- fep->stats.rx_dropped++;
+ /* Filter frame sizes > our MTU */
+ if (fep->rx_skb[i]->len <= (dev->mtu + ENET_HEADER_SIZE + ENET_FCS_SIZE)) {
+ error = netif_rx(fep->rx_skb[i]);
+ if ((error == NET_RX_DROP) ||
+ (error == NET_RX_BAD)) {
+ fep->stats.rx_dropped++;
+ } else {
+ fep->stats.rx_packets++;
+ fep->stats.rx_bytes += frame_length;
+ }
} else {
- fep->stats.rx_packets++;
- fep->stats.rx_bytes += frame_length;
+ dev_kfree_skb(fep->rx_skb[i]);
+ fep->stats.rx_length_errors++;
+ fep->stats.rx_errors++;
}
fep->rx_skb[i] = NULL;
} else {
@@ -752,15 +759,23 @@
fep->rx_skb[buf[0]]->protocol =
eth_type_trans(fep->rx_skb[buf[0]],
dev);
- error = netif_rx(fep->rx_skb[buf[0]]);
- if ((error == NET_RX_DROP)
- || (error == NET_RX_BAD)) {
- fep->stats.rx_dropped++;
+ /* Filter frame sizes > our MTU */
+ if (fep->rx_skb[buf[0]]->len <= (dev->mtu + ENET_HEADER_SIZE + ENET_FCS_SIZE)) {
+ error = netif_rx(fep->rx_skb[buf[0]]);
+
+ if ((error == NET_RX_DROP)
+ || (error == NET_RX_BAD)) {
+ fep->stats.rx_dropped++;
+ } else {
+ fep->stats.rx_packets++;
+ fep->stats.rx_bytes +=
+ fep->rx_skb[buf[0]]->len;
+ }
} else {
- fep->stats.rx_packets++;
- fep->stats.rx_bytes +=
- fep->rx_skb[buf[0]]->len;
+ fep->stats.rx_length_errors++;
+ fep->stats.rx_errors++;
+ dev_kfree_skb(fep->rx_skb[buf[0]]);
}
for (b = 0; b < bnum; b++)
fep->rx_skb[buf[b]] = NULL;
@@ -1041,7 +1056,7 @@
/* set speed (default is 10Mb) */
switch (speed) {
case SPEED_1000:
- mode_reg |= EMAC_M1_JUMBO_ENABLE | EMAC_M1_RFS_16K;
+ mode_reg |= EMAC_M1_RFS_16K;
if (fep->rgmii_dev) {
struct ibm_ocp_rgmii *rgmii = RGMII_PRIV(fep->rgmii_dev);
@@ -1118,6 +1133,7 @@
{
struct ocp_enet_private *fep = dev->priv;
int old_mtu = dev->mtu;
+ unsigned long mode_reg;
emac_t *emacp = fep->emacp;
u32 em0mr0;
int i, full;
@@ -1160,10 +1176,17 @@
fep->rx_skb[i] = NULL;
}
- /* Set new rx_buffer_size and advertise new mtu */
- fep->rx_buffer_size =
- new_mtu + ENET_HEADER_SIZE + ENET_FCS_SIZE;
+ /* Set new rx_buffer_size, jumbo cap, and advertise new mtu */
+ mode_reg = in_be32(&emacp->em0mr1);
+ if (new_mtu > ENET_DEF_MTU_SIZE) {
+ mode_reg |= EMAC_M1_JUMBO_ENABLE;
+ fep->rx_buffer_size = EMAC_MAX_FRAME;
+ } else {
+ mode_reg &= ~EMAC_M1_JUMBO_ENABLE;
+ fep->rx_buffer_size = ENET_DEF_BUF_SIZE;
+ }
dev->mtu = new_mtu;
+ out_be32(&emacp->em0mr1, mode_reg);
/* Re-init rx skbs */
fep->rx_slot = 0;
===== drivers/net/ibm_emac/ibm_emac_core.h 1.3 vs edited =====
--- 1.3/drivers/net/ibm_emac/ibm_emac_core.h 2005-02-08 22:24:52 -07:00
+++ edited/drivers/net/ibm_emac/ibm_emac_core.h 2005-02-18 09:30:07 -07:00
@@ -77,6 +77,8 @@
#define ENET_HEADER_SIZE 14
#define ENET_FCS_SIZE 4
+#define ENET_DEF_MTU_SIZE 1500
+#define ENET_DEF_BUF_SIZE (ENET_DEF_MTU_SIZE + ENET_HEADER_SIZE + ENET_FCS_SIZE)
#define EMAC_MIN_FRAME 64
#define EMAC_MAX_FRAME 9018
#define EMAC_MIN_MTU (EMAC_MIN_FRAME - ENET_HEADER_SIZE - ENET_FCS_SIZE)
^ permalink raw reply
* [PATCH][PPC32] SCC4 UART for MPC8272
From: Vitaly Bordug @ 2005-02-18 17:14 UTC (permalink / raw)
To: linuxppc-embedded
[-- Attachment #1: Type: text/plain, Size: 179 bytes --]
This patch adds support for SCC4 UART on MPC8272ADS, it is created
against current linuxppc-2.4 tree.
Signed-off-by: Vitaly Bordug <vbordug@ru.mvista.com>
--
Sincerely, Vitaly
[-- Attachment #2: cpm2.diff --]
[-- Type: text/x-patch, Size: 3852 bytes --]
===== uart.c 1.19 vs 1.21 =====
--- 1.19/arch/ppc/cpm2_io/uart.c 2005-01-04 20:12:19 +03:00
+++ 1.21/arch/ppc/cpm2_io/uart.c 2005-02-18 13:57:22 +03:00
@@ -179,7 +179,11 @@
static struct serial_state rs_table[] = {
/* UART CLK PORT IRQ FLAGS NUM */
{ 0, 0, PROFF_SCC1, SIU_INT_SCC1, 0, SCC_NUM_BASE}, /* SCC1 ttyS2 */
+#ifdef CONFIG_ADS8272
+ { 0, 0, PROFF_SCC4, SIU_INT_SCC4, 0, SCC_NUM_BASE + 3 }, /* SCC4 ttyS1 */
+#else
{ 0, 0, PROFF_SCC2, SIU_INT_SCC2, 0, SCC_NUM_BASE + 1}, /* SCC2 ttyS3 */
+#endif
};
#endif /* SCC_CONSOLE */
@@ -2575,6 +2579,12 @@
volatile cpm2_map_t *immap;
volatile iop_cpm2_t *io;
+#ifdef CONFIG_ADS8272
+ /* Enable the RS-232 transceivers.
+ */
+ *(volatile uint *)(BCSR_ADDR + 4) &= ~(BCSR1_RS232_EN1 | BCSR1_RS232_EN2);
+#endif
+
init_bh(SERIAL_BH, do_serial_bh);
show_serial_version();
@@ -2693,7 +2703,14 @@
*/
immap->im_cpmux.cmx_scr &= ~0x00ffff00;
immap->im_cpmux.cmx_scr |= 0x00121b00;
-#else
+#else /* SCC_CONSOLE */
+#if !defined(CONFIG_ADS8272) /* SCC_CONSOLE && !ADS8272 */
+ /* Connect SCC1, SCC2, SCC3 to NMSI. Connect BRG1 to SCC1,
+ * BRG2 to SCC2, BRG3 to SCC3.
+ */
+ immap->im_cpmux.cmx_scr &= ~0xffffff00;
+ immap->im_cpmux.cmx_scr |= 0x00091200;
+
/* This configures SCC2 and SCC3 as the IO pins.
*/
#if !defined(CONFIG_MPC85xx_GP3)
@@ -2711,13 +2728,31 @@
io->iop_psord |= 0x00000002; /* Tx */
io->iop_pdird &= ~0x00000001; /* Rx */
io->iop_pdird |= 0x00000002; /* Tx */
-
- /* Connect SCC1, SCC2, SCC3 to NMSI. Connect BRG1 to SCC1,
- * BRG2 to SCC2, BRG3 to SCC3.
+#else /* SCC_CONSOLE && CONFIG_ADS8272 */
+ /* wire BRG1 to SCC1 and BRG4 to SCC4 */
+ immap->im_cpmux.cmx_scr &= ~0xff0000ff;
+ immap->im_cpmux.cmx_scr |= 0x0000001b;
+
+ /* The ADS8272 has serial ports on SCC1 and SCC2 configured as follows:
+ * TXD1 PD30 SCC1 Output
+ * RTS1 PD29 General Purpose Output
+ * RXD1 PD31 SCC1 Input
+ * DCD1 PC14 General Purpose Input
+ *
+ * TXD2 PD21 SCC4 Output
+ * RTS2 PD20 General Purpose Output
+ * RXD2 PD22 SCC4 Input
+ * DCD2 PC8 General Purpose Input
*/
- immap->im_cpmux.cmx_scr &= ~0xffffff00;
- immap->im_cpmux.cmx_scr |= 0x00091200;
+ io->iop_ppard |= 0x00000e07;
+ io->iop_psord &= ~0x00000e05; /* Rx */
+ io->iop_psord |= 0x00000002; /* Tx */
+ io->iop_pdird &= ~0x00000201; /* Rx */
+ io->iop_pdird |= 0x00000c06; /* Tx */
+ io->iop_pparc &= ~0x00820000;
+ io->iop_pdirc &= ~0x00820000;
#endif
+#endif /*SCC_CONSOLE*/
for (i = 0, state = rs_table; i < NR_PORTS; i++,state++) {
state->magic = SSTATE_MAGIC;
@@ -2916,6 +2951,11 @@
page = CPM_CR_SCC3_PAGE;
sblock = CPM_CR_SCC3_SBLOCK;
break;
+ case 3:
+ page = CPM_CR_SCC4_PAGE;
+ sblock = CPM_CR_SCC4_SBLOCK;
+ break;
+
}
#else
if (state->smc_scc_num == 2) {
@@ -3014,6 +3054,16 @@
scp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
#ifdef CONFIG_SCC1_CONSOLE
+#ifdef CONFIG_ADS8272
+ /* Use Port D for SCC1 and SCC4 */
+ io->iop_ppard |= 0x00000e07;
+ io->iop_psord &= ~0x00000e05; /* Rx */
+ io->iop_psord |= 0x00000002; /* Tx */
+ io->iop_pdird &= ~0x00000201; /* Rx */
+ io->iop_pdird |= 0x00000c06; /* Tx */
+ io->iop_pparc &= ~0x00820000;
+ io->iop_pdirc &= ~0x00820000;
+#else
/* Use Port D for SCC1 instead of other functions.
*/
io->iop_ppard |= 0x00000003;
@@ -3021,6 +3071,7 @@
io->iop_psord |= 0x00000002; /* Tx */
io->iop_pdird &= ~0x00000001; /* Rx */
io->iop_pdird |= 0x00000002; /* Tx */
+#endif /* CONFIG_ADS8272 */
#endif
#if defined(CONFIG_SCC2_CONSOLE) && !defined(CONFIG_MPC85xx_GP3)
/* Use Port B for SCC2.
@@ -3133,6 +3184,11 @@
page = CPM_CR_SCC3_PAGE;
sblock = CPM_CR_SCC3_SBLOCK;
break;
+ case 4:
+ page = CPM_CR_SCC4_PAGE;
+ sblock = CPM_CR_SCC4_SBLOCK;
+ break;
+
}
cp->cp_cpcr = mk_cr_cmd(page, sblock, 0,
^ permalink raw reply
* [PATCH] PCI bridge support for MPC8272 and PQ2FADS
From: Vitaly Bordug @ 2005-02-18 17:27 UTC (permalink / raw)
To: linuxppc-embedded
[-- Attachment #1: Type: text/plain, Size: 298 bytes --]
This patch adds PCI bridge support for MPC8272 and PQ2FADS to the
current linuxppc-2.4 tree. Actually it has been tested with 8272, but
PQ2 _should_ also work, though it will complain that host bridge ID is
unrecognized.
Signed-off-by: Vitaly Bordug <vbordug@ru.mvista.com>
--
Sincerely, Vitaly
[-- Attachment #2: pq2-pci.patch --]
[-- Type: text/x-patch, Size: 20111 bytes --]
# This is a BitKeeper generated diff -Nru style patch.
#
# ChangeSet
# 2005/02/18 17:11:57+03:00 vbordug@ru.mvista.com
# Fixed compilation warnings for 8260-like boards when CONFIG_PCI=y
#
# include/asm-ppc/mpc8260.h
# 2005/02/18 17:11:54+03:00 vbordug@ru.mvista.com +2 -0
# Fixed compilation warnings when CONFIG_PCI=y
#
# ChangeSet
# 2005/02/18 16:17:49+03:00 vbordug@ru.mvista.com
# Added support for PCI bridge on MPC8272 and PQ2FADS boards
#
# arch/ppc/platforms/pq2ads.h
# 2005/02/18 16:17:47+03:00 vbordug@ru.mvista.com +88 -5
# Added support for PCI bridge on MPC8272 and PQ2FADS
#
# arch/ppc/platforms/Makefile
# 2005/02/18 16:17:47+03:00 vbordug@ru.mvista.com +5 -0
# Added support for PCI bridge on MPC8272 and PQ2FADS
#
# arch/ppc/kernel/m8260_setup.c
# 2005/02/18 16:17:47+03:00 vbordug@ru.mvista.com +17 -0
# Added support for PCI bridge on MPC8272 and PQ2FADS
#
# arch/ppc/kernel/Makefile
# 2005/02/18 16:17:47+03:00 vbordug@ru.mvista.com +8 -0
# Modules needed for PCI Bridge support on MPC8272 and PQ2FADS
#
# arch/ppc/platforms/pq2ads_pci.c
# 2005/02/18 16:15:29+03:00 vbordug@ru.mvista.com +361 -0
# PCI Bridge setup routines for MPC8272ADS and PQ2FADS (initial revision)
#
# arch/ppc/platforms/pq2ads_pci.c
# 2005/02/18 16:15:29+03:00 vbordug@ru.mvista.com +0 -0
# BitKeeper file /home/common/work/community/kernel/linuxppc-2.4/arch/ppc/platforms/pq2ads_pci.c
#
diff -Nru a/arch/ppc/kernel/Makefile b/arch/ppc/kernel/Makefile
--- a/arch/ppc/kernel/Makefile 2005-02-18 17:14:12 +03:00
+++ b/arch/ppc/kernel/Makefile 2005-02-18 17:14:12 +03:00
@@ -108,6 +108,14 @@
obj-$(CONFIG_PCI) += indirect_pci.o pci_auto.o
endif
+ifeq ($(CONFIG_ADS8272),y)
+obj-$(CONFIG_PCI) += indirect_pci.o pci_auto.o
+endif
+
+ifeq ($(CONFIG_PQ2FADS),y)
+obj-$(CONFIG_PCI) += indirect_pci.o pci_auto.o
+endif
+
include $(TOPDIR)/Rules.make
entry.o: entry.S ppc_defs.h
diff -Nru a/arch/ppc/kernel/m8260_setup.c b/arch/ppc/kernel/m8260_setup.c
--- a/arch/ppc/kernel/m8260_setup.c 2005-02-18 17:14:12 +03:00
+++ b/arch/ppc/kernel/m8260_setup.c 2005-02-18 17:14:12 +03:00
@@ -54,6 +54,7 @@
unsigned char __res[sizeof(bd_t)];
extern void cpm2_reset(void);
+extern void pq2ads_init_irq(void);
static void __init
m8260_setup_arch(void)
@@ -61,6 +62,12 @@
/* Reset the Communication Processor Module.
*/
cpm2_reset();
+
+#ifdef CONFIG_PCI
+ /* Lookup PCI host bridges */
+ m8260_find_bridges();
+#endif
+
}
static void
@@ -184,6 +191,13 @@
cpm2_immr->im_intctl.ic_siprr = 0x05309770;
cpm2_immr->im_intctl.ic_scprrh = 0x05309770;
cpm2_immr->im_intctl.ic_scprrl = 0x05309770;
+#if defined (CONFIG_PCI) && ( defined (CONFIG_ADS8272) || defined (CONFIG_PQ2FADS) )
+ /* Install the handlers for the external interrupt controller on the
+ * MPC8272ADS and PQ2FADS boards.
+ */
+ pq2ads_init_irq();
+#endif
+
}
@@ -209,6 +223,9 @@
static void __init
m8260_map_io(void)
{
+#if defined (CONFIG_PCI) && ( defined (CONFIG_ADS8272) || defined (CONFIG_PQ2FADS) )
+ io_block_mapping(0x80000000, 0x80000000, 0x10000000, _PAGE_IO);
+#endif
io_block_mapping(0xf0000000, 0xf0000000, 0x10000000, _PAGE_IO);
io_block_mapping(0xe0000000, 0xe0000000, 0x10000000, _PAGE_IO);
}
diff -Nru a/arch/ppc/platforms/Makefile b/arch/ppc/platforms/Makefile
--- a/arch/ppc/platforms/Makefile 2005-02-18 17:14:12 +03:00
+++ b/arch/ppc/platforms/Makefile 2005-02-18 17:14:12 +03:00
@@ -98,6 +98,11 @@
obj-$(CONFIG_MPC85xx_CDS) += mpc85xx_cds_common.o
endif
+ifeq ($(CONFIG_PCI),y)
+obj-$(CONFIG_ADS8272) += pq2ads_pci.o
+obj-$(CONFIG_PQ2FADS) += pq2ads_pci.o
+endif
+
ifeq ($(CONFIG_SMP),y)
obj-$(CONFIG_ALL_PPC) += pmac_smp.o chrp_smp.o
endif
diff -Nru a/arch/ppc/platforms/pq2ads.h b/arch/ppc/platforms/pq2ads.h
--- a/arch/ppc/platforms/pq2ads.h 2005-02-18 17:14:12 +03:00
+++ b/arch/ppc/platforms/pq2ads.h 2005-02-18 17:14:12 +03:00
@@ -14,6 +14,10 @@
#include <asm/ppcboot.h>
+#ifdef CONFIG_PCI
+#include <linux/pci_ids.h>
+#endif
+
/* Memory map is configured by the PROM startup.
* We just map a few things we need. The CSR is actually 4 byte-wide
* registers that can be accessed as 8-, 16-, or 32-bit values.
@@ -40,7 +44,79 @@
#define PHY_INTERRUPT SIU_INT_IRQ7
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration Register 4-31
+ */
+#define SIUMCR_BBD 0x80000000 /* Bus Busy Disable */
+#define SIUMCR_ESE 0x40000000 /* External Snoop Enable */
+#define SIUMCR_PBSE 0x20000000 /* Parity Byte Select Enable */
+#define SIUMCR_CDIS 0x10000000 /* Core Disable */
+#define SIUMCR_DPPC00 0x00000000 /* Data Parity Pins Configuration*/
+#define SIUMCR_DPPC01 0x04000000 /* - " - */
+#define SIUMCR_DPPC10 0x08000000 /* - " - */
+#define SIUMCR_DPPC11 0x0c000000 /* - " - */
+#define SIUMCR_L2CPC00 0x00000000 /* L2 Cache Pins Configuration */
+#define SIUMCR_L2CPC01 0x01000000 /* - " - */
+#define SIUMCR_L2CPC10 0x02000000 /* - " - */
+#define SIUMCR_L2CPC11 0x03000000 /* - " - */
+#define SIUMCR_LBPC00 0x00000000 /* Local Bus Pins Configuration */
+#define SIUMCR_LBPC01 0x00400000 /* - " - */
+#define SIUMCR_LBPC10 0x00800000 /* - " - */
+#define SIUMCR_LBPC11 0x00c00000 /* - " - */
+#define SIUMCR_APPC00 0x00000000 /* Address Parity Pins Configuration*/
+#define SIUMCR_APPC01 0x00100000 /* - " - */
+#define SIUMCR_APPC10 0x00200000 /* - " - */
+#define SIUMCR_APPC11 0x00300000 /* - " - */
+#define SIUMCR_CS10PC00 0x00000000 /* CS10 Pin Configuration */
+#define SIUMCR_CS10PC01 0x00040000 /* - " - */
+#define SIUMCR_CS10PC10 0x00080000 /* - " - */
+#define SIUMCR_CS10PC11 0x000c0000 /* - " - */
+#define SIUMCR_BCTLC00 0x00000000 /* Buffer Control Configuration */
+#define SIUMCR_BCTLC01 0x00010000 /* - " - */
+#define SIUMCR_BCTLC10 0x00020000 /* - " - */
+#define SIUMCR_BCTLC11 0x00030000 /* - " - */
+#define SIUMCR_MMR00 0x00000000 /* Mask Masters Requests */
+#define SIUMCR_MMR01 0x00004000 /* - " - */
+#define SIUMCR_MMR10 0x00008000 /* - " - */
+#define SIUMCR_MMR11 0x0000c000 /* - " - */
+#define SIUMCR_LPBSE 0x00002000 /* LocalBus Parity Byte Select Enable*/
+
+
#ifdef CONFIG_PCI
+/*
+ * Define the vendor/device ID for the MPC82XX.
+ */
+#define PCI_DEVICE_ID_MPC8265 ((0x18C0 << 16) | PCI_VENDOR_ID_MOTOROLA)
+#define PCI_DEVICE_ID_MPC8272 ((0x18C1 << 16) | PCI_VENDOR_ID_MOTOROLA)
+
+
+/* Bit definitions for PCIBR registers */
+
+#define PCIBR_ENABLE 0x00000001
+
+/* Bit definitions for POMCR registers */
+#define POCMR_ENABLE 0x80000000
+#define POCMR_PCI_IO 0x40000000
+#define POCMR_PREFETCH_EN 0x20000000
+#define POTA_ADDR_SHIFT 12
+
+/* Bit definitions for PCI Inbound Comparison Mask registers */
+#define PICMR_ENABLE 0x80000000
+#define PICMR_NO_SNOOP_EN 0x40000000
+#define PICMR_PREFETCH_EN 0x20000000
+#define PITA_ADDR_SHIFT 12
+
+/* Bit definitions for PCI_GCR register */
+
+#define PCIGCR_PCI_BUS_EN 0x1
+
+/* Bus parking decides where the bus control sits when idle */
+/* If modifying memory controllers for PCI park on the core */
+
+#define PPC_ACR_BUS_PARK_CORE 0x6
+#define PPC_ACR_BUS_PARK_PCI 0x3
+
+
/* PCI interrupt controller */
#define PCI_INT_STAT_REG 0xF8200000
#define PCI_INT_MASK_REG 0xF8200004
@@ -50,22 +126,23 @@
#define PIRQD (NR_SIU_INTS + 3)
/*
- * PCI memory map definitions for MPC8266ADS-PCI.
+ * PCI memory map definitions for MPC82XXADS.
*
* processor view
* local address PCI address target
* 0x80000000-0x9FFFFFFF 0x80000000-0x9FFFFFFF PCI mem with prefetch
* 0xA0000000-0xBFFFFFFF 0xA0000000-0xBFFFFFFF PCI mem w/o prefetch
- * 0xF4000000-0xF7FFFFFF 0x00000000-0x03FFFFFF PCI IO
+ * 0xF6000000-0xF7FFFFFF 0x00000000-0x01FFFFFF PCI IO
*
* PCI master view
* local address PCI address target
- * 0x00000000-0x1FFFFFFF 0x00000000-0x1FFFFFFF MPC8266 local memory
+ * 0x00000000-0x1FFFFFFF 0x00000000-0x1FFFFFFF MPC82XXADS local memory
*/
/* window for a PCI master to access MPC8266 memory */
#define PCI_SLV_MEM_LOCAL 0x00000000 /* Local base */
#define PCI_SLV_MEM_BUS 0x00000000 /* PCI base */
+#define PCI_SLV_MEM_SIZE 0x10000000 /* 256Mb */
/* window for the processor to access PCI memory with prefetching */
#define PCI_MSTR_MEM_LOCAL 0x80000000 /* Local base */
@@ -78,9 +155,15 @@
#define PCI_MSTR_MEMIO_SIZE 0x20000000 /* 512MB */
/* window for the processor to access PCI I/O */
-#define PCI_MSTR_IO_LOCAL 0xF4000000 /* Local base */
+#define PCI_MSTR_IO_LOCAL 0xF6000000 /* Local base */
#define PCI_MSTR_IO_BUS 0x00000000 /* PCI base */
-#define PCI_MSTR_IO_SIZE 0x04000000 /* 64MB */
+#define PCI_MSTR_IO_SIZE 0x02000000 /* 32MB */
+
+#if defined CONFIG_ADS8272
+#define PCI_INT_TO_SIU SIU_INT_IRQ2
+#elif defined CONFIG_PQ2FADS
+#define PCI_INT_TO_SIU SIU_INT_IRQ6
+#endif
#define _IO_BASE PCI_MSTR_IO_LOCAL
#define _ISA_MEM_BASE PCI_MSTR_MEMIO_LOCAL
diff -Nru a/arch/ppc/platforms/pq2ads_pci.c b/arch/ppc/platforms/pq2ads_pci.c
--- /dev/null Wed Dec 31 16:00:00 196900
+++ b/arch/ppc/platforms/pq2ads_pci.c 2005-02-18 17:14:12 +03:00
@@ -0,0 +1,361 @@
+/*
+ * arch/ppc/platforms/pq2fads_pci.c
+ *
+ * PCI Bridge setup routines for MPC8272 and PQ2FADS boards
+ *
+ * Based on: PCI setup routines for the Motorola SPS MPC8266ADS-PCI
+ * reference board by andy_lowe@mvista.com
+ *
+ * Author: Vitaly Bordug <vbordug@ru.mvista.com>
+ *
+ * 2003 (c) MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/pci.h>
+#include <linux/slab.h>
+#include <linux/irq.h>
+
+#include <asm/byteorder.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/uaccess.h>
+#include <asm/machdep.h>
+#include <asm/pci-bridge.h>
+#include <asm/immap_cpm2.h>
+//#include <asm/m8260_pci.h>
+#include <asm/delay.h>
+
+#include "pq2ads.h"
+
+extern void setup_m8260_indirect_pci(struct pci_controller* hose,
+ u32 cfg_addr,
+ u32 cfg_data);
+
+/*
+ * interrupt routing
+ */
+
+static inline int
+pq2ads_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
+{
+ static char pci_irq_table[][4] =
+ /*
+ * PCI IDSEL/INTPIN->INTLINE
+ * A B C D
+ */
+ {
+ { PIRQA, PIRQB, PIRQC, PIRQD }, /* IDSEL 22 - PCI slot 0 */
+ { PIRQD, PIRQA, PIRQB, PIRQC }, /* IDSEL 23 - PCI slot 1 */
+ { PIRQC, PIRQD, PIRQA, PIRQB }, /* IDSEL 24 - PCI slot 2 */
+ };
+
+ const long min_idsel = 22, max_idsel = 24, irqs_per_slot = 4;
+ return PCI_IRQ_TABLE_LOOKUP;
+}
+
+static void
+pq2ads_mask_irq(unsigned int irq)
+{
+ int bit = irq - NR_SIU_INTS;
+
+ *(volatile unsigned long *) PCI_INT_MASK_REG |= (1 << (31 - bit));
+ return;
+}
+
+static void
+pq2ads_unmask_irq(unsigned int irq)
+{
+ int bit = irq - NR_SIU_INTS;
+
+ *(volatile unsigned long *) PCI_INT_MASK_REG &= ~(1 << (31 - bit));
+ return;
+}
+
+static void
+pq2ads_mask_and_ack(unsigned int irq)
+{
+ int bit = irq - NR_SIU_INTS;
+
+ *(volatile unsigned long *) PCI_INT_MASK_REG |= (1 << (31 - bit));
+ return;
+}
+
+static void
+pq2ads_end_irq(unsigned int irq)
+{
+ int bit = irq - NR_SIU_INTS;
+
+ *(volatile unsigned long *) PCI_INT_MASK_REG &= ~(1 << (31 - bit));
+ return;
+}
+
+struct hw_interrupt_type pq2ads_ic = {
+ "PQ2ADS PCI IC",
+ NULL,
+ NULL,
+ pq2ads_unmask_irq,
+ pq2ads_mask_irq,
+ pq2ads_mask_and_ack,
+ pq2ads_end_irq,
+ 0
+};
+
+static void
+pci_irq_demux(int irq, void *dev_id, struct pt_regs *regs)
+{
+ unsigned long stat, mask, pend;
+ int bit;
+
+ for(;;) {
+ stat = *(volatile unsigned long *) PCI_INT_STAT_REG;
+ mask = *(volatile unsigned long *) PCI_INT_MASK_REG;
+ pend = stat & ~mask & 0xf0000000;
+ if (!pend)
+ break;
+ for (bit = 0; pend != 0; ++bit, pend <<= 1) {
+ if (pend & 0x80000000)
+ ppc_irq_dispatch_handler(regs, NR_SIU_INTS + bit);
+ }
+ }
+
+ return;
+}
+
+void
+pq2ads_init_irq(void)
+{
+ int irq;
+ volatile cpm2_map_t* immap = cpm2_immr;
+#ifdef CONFIG_ADS8272
+ /* configure chip select for PCI interrupt controller */
+ immap->im_memctl.memc_br3 = PCI_INT_STAT_REG | 0x00001801;
+ immap->im_memctl.memc_or3 = 0xffff8010;
+#elif defined CONFIG_PQ2FADS
+ /* configure chip select for PCI interrupt controller */
+ immap->im_memctl.memc_br8 = PCI_INT_STAT_REG | 0x00001801;
+ immap->im_memctl.memc_or8 = 0xffff8010;
+#else
+#error This software is not intended to support this chip!
+#endif
+
+ for (irq = NR_SIU_INTS; irq < NR_SIU_INTS + 4; irq++)
+ irq_desc[irq].handler = &pq2ads_ic;
+
+ /* make PCI IRQ level sensitive */
+ immap->im_intctl.ic_siexr &=
+ ~(1 << (14 - (PCI_INT_TO_SIU - SIU_INT_IRQ1)));
+
+ /* mask all PCI interrupts */
+ *(volatile unsigned long *) PCI_INT_MASK_REG |= 0xfff00000;
+
+ /* install the demultiplexer for the PCI cascade interrupt */
+ if (request_irq(PCI_INT_TO_SIU, pci_irq_demux, SA_INTERRUPT,
+ "PCI IRQ demux", 0))
+ {
+ printk("Installation of PCI IRQ demux handler failed.\n");
+ }
+ return;
+}
+
+static int
+pq2ads_exclude_device(u_char bus, u_char devfn)
+{
+ return PCIBIOS_SUCCESSFUL;
+}
+
+static void
+pq2ads_hw_init(struct pci_controller *hose)
+{
+ __u32 val;
+ volatile cpm2_map_t *immap = cpm2_immr;
+ /* PCI int lowest prio */
+ /* Each 4 bits is a device bus request and the MS 4bits
+ is highest priority */
+ /* Bus 4bit value
+ --- ----------
+ CPM high 0b0000
+ CPM middle 0b0001
+ CPM low 0b0010
+ PCI reguest 0b0011
+ Reserved 0b0100
+ Reserved 0b0101
+ Internal Core 0b0110
+ External Master 1 0b0111
+ External Master 2 0b1000
+ External Master 3 0b1001
+ The rest are reserved
+ */
+ immap->im_siu_conf.siu_82xx.sc_ppc_alrh = 0x61207893;
+ /* park bus on core */
+ immap->im_siu_conf.siu_82xx.sc_ppc_acr = PPC_ACR_BUS_PARK_CORE;
+ /*
+ * Set up master windows that allow the CPU to access PCI space. These
+ * windows are set up using the two SIU PCIBR registers.
+ */
+
+ immap->im_memctl.memc_pcimsk0 = ~(PCI_MSTR_IO_SIZE - 1U);
+ immap->im_memctl.memc_pcibr0 = PCI_MSTR_IO_LOCAL | PCIBR_ENABLE;
+
+ immap->im_memctl.memc_pcimsk1 = ~(PCI_MSTR_MEM_SIZE + PCI_MSTR_MEMIO_SIZE - 1U);
+ immap->im_memctl.memc_pcibr1 = PCI_MSTR_MEM_LOCAL | PCIBR_ENABLE;
+#ifdef CONFIG_ADS8272
+ immap->im_siu_conf.siu_82xx.sc_siumcr = (immap->im_siu_conf.siu_82xx.sc_siumcr &
+ ~SIUMCR_BBD &
+ ~SIUMCR_ESE &
+ ~SIUMCR_PBSE &
+ ~SIUMCR_CDIS &
+ ~SIUMCR_DPPC11 &
+ ~SIUMCR_L2CPC11 &
+ ~SIUMCR_LBPC11 &
+ ~SIUMCR_APPC11 &
+ ~SIUMCR_CS10PC11 &
+ ~SIUMCR_BCTLC11 &
+ ~SIUMCR_MMR11)
+ | SIUMCR_DPPC11 | SIUMCR_L2CPC01 | SIUMCR_LBPC00
+ | SIUMCR_APPC10 | SIUMCR_CS10PC00 | SIUMCR_BCTLC00 | SIUMCR_MMR11;
+#elif defined CONFIG_PQ2FADS
+ /*
+ * Setting required to enable IRQ1-IRQ7 (SIUMCR [DPPC]),
+ * and local bus for PCI (SIUMCR [LBPC]).
+ */
+ immap->im_siu_conf.siu_82xx.sc_siumcr = (immap->im_siu_conf.sc_siumcr &
+ ~SIUMCR_LBPC11 &
+ ~SIUMCR_CS10PC11 &
+ ~SIUMCR_LBPC11) |
+ SIUMCR_LBPC01 | SIUMCR_CS10PC01 | SIUMCR_APPC10;
+#endif
+ /* Enable PCI */
+ immap->im_pci.pci_gcr = cpu_to_le32(PCIGCR_PCI_BUS_EN);
+ {
+ /* give it some time */
+ int i;
+ for(i=0;i<100;i++)
+ udelay(100);
+ }
+
+ /* setup ATU registers */
+ immap->im_pci.pci_pocmr0 = cpu_to_le32(POCMR_ENABLE | POCMR_PCI_IO |
+ ((~(PCI_MSTR_IO_SIZE - 1U)) >> POTA_ADDR_SHIFT));
+ immap->im_pci.pci_potar0 = cpu_to_le32(PCI_MSTR_IO_BUS >> POTA_ADDR_SHIFT);
+ immap->im_pci.pci_pobar0 = cpu_to_le32(PCI_MSTR_IO_LOCAL >> POTA_ADDR_SHIFT);
+
+ /* Set-up non-prefetchable window */
+ immap->im_pci.pci_pocmr1 = cpu_to_le32(POCMR_ENABLE | ((~(PCI_MSTR_MEMIO_SIZE-1U)) >> POTA_ADDR_SHIFT));
+ immap->im_pci.pci_potar1 = cpu_to_le32(PCI_MSTR_MEMIO_BUS >> POTA_ADDR_SHIFT);
+ immap->im_pci.pci_pobar1 = cpu_to_le32(PCI_MSTR_MEMIO_LOCAL >> POTA_ADDR_SHIFT);
+
+ /* Set-up prefetchable window */
+ immap->im_pci.pci_pocmr2 = cpu_to_le32(POCMR_ENABLE |POCMR_PREFETCH_EN |
+ (~(PCI_MSTR_MEM_SIZE-1U) >> POTA_ADDR_SHIFT));
+ immap->im_pci.pci_potar2 = cpu_to_le32((PCI_MSTR_MEM_BUS+PCI_MSTR_MEM_SIZE) >> POTA_ADDR_SHIFT);
+ immap->im_pci.pci_pobar2 = cpu_to_le32((PCI_MSTR_MEM_LOCAL+PCI_MSTR_MEM_SIZE) >> POTA_ADDR_SHIFT);
+
+ /* Inbound transactions from PCI memory space */
+ immap->im_pci.pci_picmr0 = cpu_to_le32(PICMR_ENABLE | PICMR_PREFETCH_EN |
+ ((~(PCI_SLV_MEM_SIZE-1U)) >> PITA_ADDR_SHIFT));
+ immap->im_pci.pci_pibar0 = cpu_to_le32(PCI_SLV_MEM_BUS >> PITA_ADDR_SHIFT);
+ immap->im_pci.pci_pitar0 = cpu_to_le32(PCI_SLV_MEM_LOCAL>> PITA_ADDR_SHIFT);
+
+#if defined CONFIG_ADS8272
+ /* PCI int highest prio */
+ immap->im_siu_conf.siu_82xx.sc_ppc_alrh = 0x01236745;
+#elif defined CONFIG_PQ2FADS
+ immap->im_siu_conf.siu_82xx.sc_ppc_alrh = 0x03124567;
+#endif
+ /* park bus on PCI */
+ immap->im_siu_conf.siu_82xx.sc_ppc_acr = PPC_ACR_BUS_PARK_PCI;
+
+ /* Enable bus mastering and inbound memory transactions */
+ early_read_config_dword(hose, hose->first_busno, 0, PCI_COMMAND, &val);
+ val &= 0xffff0000;
+ val |= PCI_COMMAND_MEMORY|PCI_COMMAND_MASTER;
+ early_write_config_dword(hose, hose->first_busno, 0, PCI_COMMAND, val);
+
+}
+
+
+void __init
+m8260_find_bridges(void)
+{
+ struct pci_controller *hose;
+ int host_bridge;
+ volatile cpm2_map_t *immap = cpm2_immr;
+
+ hose = pcibios_alloc_controller();
+
+ if (!hose)
+ return;
+
+ hose->first_busno = 0;
+ hose->last_busno = 0xff;
+ hose->bus_offset = 0;
+ hose->set_cfg_type = 1;
+
+ setup_indirect_pci(hose,
+ (ulong)&immap->im_pci.pci_cfg_addr,
+ (ulong)&immap->im_pci.pci_cfg_data);
+
+
+ /* Make sure it is a supported bridge */
+ early_read_config_dword(hose,
+ 0,
+ PCI_DEVFN(0,0),
+ PCI_VENDOR_ID,
+ &host_bridge);
+
+ switch (host_bridge) {
+ case PCI_DEVICE_ID_MPC8265:
+ break;
+ case PCI_DEVICE_ID_MPC8272:
+ break;
+
+ default:
+ printk("Attempting to use unrecognized host bridge ID"
+ " 0x%08x.\n", host_bridge);
+ break;
+ }
+
+ pq2ads_hw_init(hose);
+
+ hose->pci_mem_offset = PCI_MSTR_MEM_LOCAL - PCI_MSTR_MEM_BUS;
+ hose->io_space.start = PCI_MSTR_IO_BUS;
+ hose->io_space.end = PCI_MSTR_IO_BUS + PCI_MSTR_IO_SIZE - 1U;
+ hose->mem_space.start = PCI_MSTR_MEM_BUS;
+ hose->mem_space.end = PCI_MSTR_MEMIO_BUS + PCI_MSTR_MEMIO_SIZE - 1U;
+ hose->io_base_virt = (void *)PCI_MSTR_IO_LOCAL;
+ isa_io_base = PCI_MSTR_IO_LOCAL;
+
+ pci_init_resource(&hose->io_resource,
+ PCI_MSTR_IO_BUS,
+ PCI_MSTR_IO_BUS + PCI_MSTR_IO_SIZE - 1U,
+ IORESOURCE_IO,
+ "PCI host bridge");
+
+ pci_init_resource(&hose->mem_resources[0],
+ PCI_MSTR_MEMIO_BUS,
+ PCI_MSTR_MEMIO_BUS + PCI_MSTR_MEMIO_SIZE - 1U,
+ IORESOURCE_MEM,
+ "PCI host bridge");
+
+ pci_init_resource(&hose->mem_resources[1],
+ PCI_MSTR_MEM_BUS,
+ PCI_MSTR_MEM_BUS + PCI_MSTR_MEM_SIZE - 1U,
+ IORESOURCE_MEM | IORESOURCE_PREFETCH,
+ "PCI host bridge");
+
+ pci_dram_offset = PCI_SLV_MEM_LOCAL;
+
+ ppc_md.pci_exclude_device = pq2ads_exclude_device;
+ hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
+
+ ppc_md.pcibios_fixup = NULL;
+ ppc_md.pcibios_fixup_bus = NULL;
+ ppc_md.pci_swizzle = common_swizzle;
+ ppc_md.pci_map_irq = pq2ads_map_irq;
+
+ return;
+}
diff -Nru a/include/asm-ppc/mpc8260.h b/include/asm-ppc/mpc8260.h
--- a/include/asm-ppc/mpc8260.h 2005-02-18 17:14:12 +03:00
+++ b/include/asm-ppc/mpc8260.h 2005-02-18 17:14:12 +03:00
@@ -24,12 +24,14 @@
#include <platforms/pq2ads.h>
#endif
+#ifndef CONFIG_PCI
/* I don't yet have the ISA or PCI stuff done....no 8260 with
* such thing.....
*/
#define _IO_BASE 0
#define _ISA_MEM_BASE 0
#define PCI_DRAM_OFFSET 0
+#endif
#ifndef __ASSEMBLY__
/* The "residual" data board information structure the boot loader
^ permalink raw reply
* Re: Lite5200 full duplex support
From: Dale Farnsworth @ 2005-02-18 17:20 UTC (permalink / raw)
To: Grant Likely, linuxppc-embedded
In-Reply-To: <528646bc05021714356238ff35@mail.gmail.com>
On Thu, Feb 17, 2005 at 10:35:14PM +0000, Grant Likely wrote:
> On Thu, 17 Feb 2005 15:13:33 -0700, Grant Likely <glikely@gmail.com> wrote:
> > On Wed, 16 Feb 2005 21:46:09 +0100, Sylvain Munaut <tnt@246tnt.com> wrote:
> > > Grant Likely wrote:
> > >
> > > >BTW, here's what I changed:
> > > >drivers/net/fec_mpc52xx/fec_phy.c line 294 (phy_info_lxt971)
> > > >from:
> > > > { mk_mii_write(MII_REG_ANAR, 0x0A1), NULL }, /* 10/100, HD */
> > > >to:
> > > > { mk_mii_write(MII_REG_ANAR, 0x1E1), NULL }, /* 10/100, HD */
> > > >
> > > >
> > > >
> > > I'm not sure actually. I also wondered and forgot to ask the author. I guess
> > > I always tought there was a problem with it without checking.
> > >
> > I've played around with it a bit more and I have discovered one
> > problem. When in full duplex the carrier detect seems to bounce up
> > and down for every frame received off the wire. I've beaten the tar
> > out of it with netperf and it doesn't seem to be causeing any
> > instability (yet)... Still investigating.
> >
> Update: The error seems to be carrier sense loss during transmit. The
> FEC documentation states that carrier loss errors are counted, but the
> frame is not retransmitted and no interrupt is generated. The driver
> copies the value directly out of the counter register when reporting
> status.
>
> I do not know yet if it affects received frames...
I've used the Lite5200 ethernet in either full-duplex mode or
half-duplex mode. However, the change quoted above is insufficient.
You also need to change the call to fec_restart in fec.c to be something like:
fec_restart(dev, 1); /* always use full duplex mode only */
There is currently no mechanism for the driver to detect if the PHY
negotiated full or half duplex. There is no PHY interrupt and no
routine has been coded to poll for PHY status. Therefore, the lite5200
can't automatically work with either full or half duplex. You have
to select one or the other. I selected half duplex as the least common
denominator.
-Dale Farnsworth
^ permalink raw reply
* Re: [PATCH] Heartbeat LED for iBook
From: Segher Boessenkool @ 2005-02-18 18:10 UTC (permalink / raw)
To: Brad Boyer; +Cc: Nico Schottelius, linuxppc-dev list
In-Reply-To: <20050218175822.GA30616@pants.nu>
> There is some minimal documentation available. Some Apple docs:
>
> ADB-The Untold Story: Space Aliens Ate My Mouse
> http://developer.apple.com/technotes/hw/hw_01.html
>
> Inside Macintosh: Devices / Chapter 5 - ADB Manager
> http://developer.apple.com/documentation/mac/Devices/Devices-203.html
>
> These will tell you the basic design of ADB as well as the packet
> formats and information about keyboards and mice.
>
> Note that these document ADB in a generic sense, so nothing PMU
> specific is in them. Apple has been very reluctant to document
> the PMU and it's functions.
ADB has nothing to do with the PMU (well, the PMU emulates an ADB
device, sort of).
The Linux kernel multiplexes the /dev/adb device to also serve as
a channel to the PMU, though. This ugliness should be fixed, some
day...
Segher
^ permalink raw reply
* Re: [PATCH] Heartbeat LED for iBook
From: Brad Boyer @ 2005-02-18 17:58 UTC (permalink / raw)
To: Segher Boessenkool; +Cc: Nico Schottelius, linuxppc-dev list
In-Reply-To: <629f63c4608b762de8bf6f962b6180ef@kernel.crashing.org>
On Fri, Feb 18, 2005 at 02:00:32PM +0100, Segher Boessenkool wrote:
> There is no manual. You can look at some Darwin source code,
> I guess, or there is some code in Linux to do this as well, IIRC.
There is some minimal documentation available. Some Apple docs:
ADB-The Untold Story: Space Aliens Ate My Mouse
http://developer.apple.com/technotes/hw/hw_01.html
Inside Macintosh: Devices / Chapter 5 - ADB Manager
http://developer.apple.com/documentation/mac/Devices/Devices-203.html
These will tell you the basic design of ADB as well as the packet
formats and information about keyboards and mice.
Note that these document ADB in a generic sense, so nothing PMU
specific is in them. Apple has been very reluctant to document
the PMU and it's functions.
Brad Boyer
flar@allandria.com
^ permalink raw reply
* Re: Linux processes, tempfs and programs
From: Stephen Williams @ 2005-02-18 18:58 UTC (permalink / raw)
To: linuxppc-embedded
In-Reply-To: <20050218005905.GC10915@gate.ebshome.net>
-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1
Eugene Surovegin wrote:
| On Thu, Feb 17, 2005 at 04:43:27PM -0800, Eugene Surovegin wrote:
|
|>On Thu, Feb 17, 2005 at 03:38:05PM -0800, Stephen Williams wrote:
|>>But if I do that, I want to remove the program from the directory
|>>after I start it, so that the file does not take up ram space. Will
|>>that actually work? I'm using exec(2) to execute the program file
|>>wherever it is downloaded. Will a subsequent unlink of the file
|>>have a result, or will the file continue to take up space as
|>>backing store for the executable?
|>I think unlink will remove the file from directory (so you won't be
|>able to see it with ls), but it will still continue to to take space -
|>you're right it will be used as backing store, at least for read-only
|>segments, which can be discarded if memory is tight. Even if you mlock
|>all executable in memory, I think there will be still at least one
|>reference to this file, which will prevent freeing tmpfs memory.
|
|
| A little correction, according to tmpfs doc, it lives completely in
| page cache, so I think memory is not wasted for unmodified sections of
| the loaded file (e.g. a second copy, when file is executed and loaded
| into user-space, isn't being made).
|
| But as usual, make some measurements first :)
So far as I can see in my simplistic tests, this still takes twice
as much memory as leaving the executable on a disk somewhere. This
seems to be an inevitable consequence of execve on Linux 2.4.x. That's
a bummer. Any other suggestions?
- --
Steve Williams "The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,
http://www.icarus.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep."
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.2.5 (GNU/Linux)
Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org
iD8DBQFCFjrjrPt1Sc2b3ikRAjwvAKCogiZ5i+OHdsGskhsfC97+jxl/ygCgqAql
P77LUWxMW87T7ReXVg27fj8=
=j9KI
-----END PGP SIGNATURE-----
^ permalink raw reply
* [PATCH][PPC32] Lindentify PPC4xx PIC driver
From: Eugene Surovegin @ 2005-02-18 20:34 UTC (permalink / raw)
To: Andrew Morton; +Cc: linuxppc-embedded
[-- Attachment #1: Type: text/plain, Size: 110 bytes --]
Andrew,
this patch fixes whitespace in PPC4xx PIC driver.
Signed-off-by: Eugene Surovegin <ebs@ebshome.net>
[-- Attachment #2: ppc4xx_pic_lindent.diff --]
[-- Type: text/plain, Size: 4479 bytes --]
diff -Nru a/arch/ppc/syslib/ppc4xx_pic.c b/arch/ppc/syslib/ppc4xx_pic.c
--- a/arch/ppc/syslib/ppc4xx_pic.c 2005-02-18 12:12:29 -08:00
+++ b/arch/ppc/syslib/ppc4xx_pic.c 2005-02-18 12:12:29 -08:00
@@ -29,8 +29,9 @@
/* See comment in include/arch-ppc/ppc4xx_pic.h
* for more info about these two variables
*/
-extern struct ppc4xx_uic_settings ppc4xx_core_uic_cfg[NR_UICS] __attribute__((weak));
-extern unsigned char ppc4xx_uic_ext_irq_cfg[] __attribute__((weak));
+extern struct ppc4xx_uic_settings ppc4xx_core_uic_cfg[NR_UICS]
+ __attribute__ ((weak));
+extern unsigned char ppc4xx_uic_ext_irq_cfg[] __attribute__ ((weak));
#define IRQ_MASK_UIC0(irq) (1 << (31 - (irq)))
#define IRQ_MASK_UICx(irq) (1 << (31 - ((irq) & 0x1f)))
@@ -63,11 +64,11 @@
{ \
unsigned int status = irq_desc[irq].status; \
u32 mask = IRQ_MASK_UIC##n(irq); \
- if (status & IRQ_LEVEL){ \
+ if (status & IRQ_LEVEL) { \
mtdcr(DCRN_UIC_SR(UIC##n), mask); \
ACK_UIC##n##_PARENT \
} \
- if (!(status & (IRQ_DISABLED | IRQ_INPROGRESS))){ \
+ if (!(status & (IRQ_DISABLED | IRQ_INPROGRESS))) { \
ppc_cached_irq_mask[n] |= mask; \
mtdcr(DCRN_UIC_ER(UIC##n), ppc_cached_irq_mask[n]); \
} \
@@ -86,7 +87,9 @@
#define ACK_UIC0_PARENT mtdcr(DCRN_UIC_SR(UICB), UICB_UIC0NC);
#define ACK_UIC1_PARENT mtdcr(DCRN_UIC_SR(UICB), UICB_UIC1NC);
#define ACK_UIC2_PARENT mtdcr(DCRN_UIC_SR(UICB), UICB_UIC2NC);
-UIC_HANDLERS(0); UIC_HANDLERS(1); UIC_HANDLERS(2);
+UIC_HANDLERS(0);
+UIC_HANDLERS(1);
+UIC_HANDLERS(2);
static int ppc4xx_pic_get_irq(struct pt_regs *regs)
{
@@ -114,7 +117,8 @@
#elif NR_UICS == 2
#define ACK_UIC0_PARENT
#define ACK_UIC1_PARENT mtdcr(DCRN_UIC_SR(UIC0), UIC0_UIC1NC);
-UIC_HANDLERS(0); UIC_HANDLERS(1);
+UIC_HANDLERS(0);
+UIC_HANDLERS(1);
static int ppc4xx_pic_get_irq(struct pt_regs *regs)
{
@@ -143,18 +147,20 @@
return uic0 ? 32 - ffs(uic0) : -1;
}
-static inline void ppc4xx_pic_impl_init(void){}
+static inline void ppc4xx_pic_impl_init(void)
+{
+}
#endif
static struct ppc4xx_uic_impl {
struct hw_interrupt_type decl;
- int base; /* Base DCR number */
+ int base; /* Base DCR number */
} __uic[] = {
- { .decl = DECLARE_UIC(0), .base = UIC0 },
+ { .decl = DECLARE_UIC(0), .base = UIC0 },
#if NR_UICS > 1
- { .decl = DECLARE_UIC(1), .base = UIC1 },
+ { .decl = DECLARE_UIC(1), .base = UIC1 },
#if NR_UICS > 2
- { .decl = DECLARE_UIC(2), .base = UIC2 },
+ { .decl = DECLARE_UIC(2), .base = UIC2 },
#endif
#endif
};
@@ -168,9 +174,9 @@
void __init ppc4xx_pic_init(void)
{
int i;
- unsigned char* eirqs = ppc4xx_uic_ext_irq_cfg;
+ unsigned char *eirqs = ppc4xx_uic_ext_irq_cfg;
- for (i = 0; i < NR_UICS; ++i){
+ for (i = 0; i < NR_UICS; ++i) {
int base = __uic[i].base;
/* Disable everything by default */
@@ -181,23 +187,23 @@
mtdcr(DCRN_UIC_CR(base), 0);
/* Configure polarity and triggering */
- if (ppc4xx_core_uic_cfg){
- struct ppc4xx_uic_settings* p = ppc4xx_core_uic_cfg + i;
+ if (ppc4xx_core_uic_cfg) {
+ struct ppc4xx_uic_settings *p = ppc4xx_core_uic_cfg + i;
u32 mask = p->ext_irq_mask;
u32 pr = mfdcr(DCRN_UIC_PR(base)) & mask;
u32 tr = mfdcr(DCRN_UIC_TR(base)) & mask;
/* "Fixed" interrupts (on-chip devices) */
- pr |= p->polarity & ~mask;
+ pr |= p->polarity & ~mask;
tr |= p->triggering & ~mask;
/* Merge external IRQs settings if board port
* provided them
*/
- if (eirqs && mask){
+ if (eirqs && mask) {
pr &= ~mask;
tr &= ~mask;
- while (mask){
+ while (mask) {
/* Extract current external IRQ mask */
u32 eirq_mask = 1 << __ilog2(mask);
@@ -227,8 +233,8 @@
ppc4xx_pic_impl_init();
/* Attach low-level handlers */
- for (i = 0; i < (NR_UICS << 5); ++i){
- irq_desc[i].handler = &__uic[i >> 5].decl;
+ for (i = 0; i < (NR_UICS << 5); ++i) {
+ irq_desc[i].handler = &__uic[i >> 5].decl;
if (is_level_sensitive(i))
irq_desc[i].status |= IRQ_LEVEL;
}
diff -Nru a/include/asm-ppc/ppc4xx_pic.h b/include/asm-ppc/ppc4xx_pic.h
--- a/include/asm-ppc/ppc4xx_pic.h 2005-02-18 12:12:29 -08:00
+++ b/include/asm-ppc/ppc4xx_pic.h 2005-02-18 12:12:29 -08:00
@@ -43,11 +43,11 @@
*
*/
struct ppc4xx_uic_settings {
- u32 polarity;
- u32 triggering;
- u32 ext_irq_mask;
+ u32 polarity;
+ u32 triggering;
+ u32 ext_irq_mask;
};
extern void ppc4xx_pic_init(void);
-#endif /* __PPC4XX_PIC_H__ */
+#endif /* __PPC4XX_PIC_H__ */
^ permalink raw reply
* [PATCH][PPC32] PPC4xx PIC: ack parent UIC in disable_irq
From: Eugene Surovegin @ 2005-02-18 20:38 UTC (permalink / raw)
To: Andrew Morton; +Cc: linuxppc-embedded
In-Reply-To: <20050218203455.GA18041@gate.ebshome.net>
[-- Attachment #1: Type: text/plain, Size: 226 bytes --]
Andrew,
this patch fixes bug in PPC4xx disable_irq implementation. We need to
ACK parent UIC to prevent false triggering in case IRQ we just
disabled was already pending.
Signed-off-by: Eugene Surovegin <ebs@ebshome.net>
[-- Attachment #2: ppc4xx_pic_disable_irq_ack_parent.diff --]
[-- Type: text/plain, Size: 793 bytes --]
diff -Nru a/arch/ppc/syslib/ppc4xx_pic.c b/arch/ppc/syslib/ppc4xx_pic.c
--- a/arch/ppc/syslib/ppc4xx_pic.c 2005-02-18 12:12:54 -08:00
+++ b/arch/ppc/syslib/ppc4xx_pic.c 2005-02-18 12:12:54 -08:00
@@ -4,7 +4,7 @@
* Interrupt controller driver for PowerPC 4xx-based processors.
*
* Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
- * Copyright (c) 2004 Zultys Technologies
+ * Copyright (c) 2004, 2005 Zultys Technologies
*
* Based on original code by
* Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
@@ -49,6 +49,7 @@
{ \
ppc_cached_irq_mask[n] &= ~IRQ_MASK_UIC##n(irq); \
mtdcr(DCRN_UIC_ER(UIC##n), ppc_cached_irq_mask[n]); \
+ ACK_UIC##n##_PARENT \
} \
\
static void ppc4xx_uic##n##_ack(unsigned int irq) \
^ permalink raw reply
* Re: Lite5200 full duplex support
From: cpclark @ 2005-02-18 19:28 UTC (permalink / raw)
To: Grant Likely; +Cc: linuxppc-embedded
In-Reply-To: <20050218172039.GA14098@xyzzy>
On Fri, 18 Feb 2005, Dale Farnsworth wrote:
> There is currently no mechanism for the driver to detect if the PHY
> negotiated full or half duplex.
You may want to take a look at arch/ppc/5xxx_io/fec.[ch] in the denx.de
linuxppc_2_4_devel CVS tree (particularly cvs revisions 1.4 and 1.10 of
fec.c and revisions 1.5 and 1.6 of fec.h).
Chris
^ permalink raw reply
* RE: oops in process_backlog : kernel 2.6.9
From: Rune Torgersen @ 2005-02-18 23:26 UTC (permalink / raw)
To: Philip Van-Houtte, linuxppc-embedded
[-- Attachment #1: Type: text/plain, Size: 85 bytes --]
Try this patch.
It makes sure the IP stack is intialized before accepting packets.
[-- Attachment #2: ip_stack_init_26.patch --]
[-- Type: application/octet-stream, Size: 493 bytes --]
--- linux-2.5/net/ipv4/ip_output.c 2005-01-12 08:59:11.000000000 -0600
+++ linux-innsys/net/ipv4/ip_output.c 2005-02-18 17:22:50.250776473 -0600
@@ -1339,11 +1335,11 @@ static struct packet_type ip_packet_type
void __init ip_init(void)
{
- dev_add_pack(&ip_packet_type);
-
ip_rt_init();
inet_initpeers();
+ dev_add_pack(&ip_packet_type);
+
#if defined(CONFIG_IP_MULTICAST) && defined(CONFIG_PROC_FS)
igmp_mc_proc_init();
#endif
^ permalink raw reply
* linux-2.5-marvell tree deletion
From: Mark A. Greer @ 2005-02-18 23:27 UTC (permalink / raw)
To: David Woodhouse, Steven J. Hill, Brian Waite; +Cc: Embedded PPC Linux list
Dale Farnsworth has moved the mv64[34]60 enet driver to
bk://dfarnsworth.bkbits.net/linux-2.5-mv643xx-enet and all of the code
that I've worked on is either in linux-2.5 or on a queue to go in so
this tree should evaporate.
If you have an issue with this please let me know before the morning of
Wednesday, Feb 23, 2005; otherwise, I will delete it on Wednesday.
Thanks,
Mark
^ permalink raw reply
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