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* Re: RFC: PHY Abstraction Layer II
From: James Chapman @ 2005-03-15 19:18 UTC (permalink / raw)
  To: Andy Fleming; +Cc: netdev, David S. Miller, linuxppc-embedded
In-Reply-To: <ba5d844255b5ba76b2685f9397faf689@freescale.com>

Hi Andy,

I finally found some time to review your phy abstraction code.

I haven't reviewed the low level MII functions; I focused mostly on
its API to the net driver and whether it has the necessary hooks to
handle the various hardware that I know.

General comment: nice, clean code. No serious style or Linux kernel
core API issues that I can see.

Specific comments follow.

- It isn't obvious what has to be done in net drivers to hook up this
   code. Consider writing a Documentation/networking/phy.txt to
   describe typical net driver code changes needed.

- If a net driver is modified to use your new code, should it use any
   functions from mii.c at all? I guess I'm unclear about the
   relationship with mii.c.

- netif_carrier_on()/off() calls are done by mii.c on link state
   changes. Consider doing the same inside your phy code.

- Some hardware does not use a separate irq for phy but instead
   indicates phy events via the ethernet chip's irq.

   There are registered phy_driver callbacks to handle things like
   read/clear/ack interrupt status. But if my ethernet device's phy
   interrupt is effectively one or more bits in the ethernet chip's
   status register (where there is no separate phy interrupt), how
   would this hook into your phy code? For example, in the interrupt
   handler of mv643xx_eth, we check status bits that indicate link
   state change from the same register that indicates rx/tx packet
   events.

   Also, NAPI drivers will disable irqs and poll for tx/rx while there
   is work to do. If they have a combined tx/rx/phy interrupt then does
   this pose other issues for hooking up the new phy code?

- What determines whether the phy driver uses interrupts or polling?

- The callback registered in phy_connect() is called when phy link
   changes are detected. It is passed a struct device*. How about
   letting the net driver register its struct net_device* which would
   be passed back in the callback? It is likely that the callback will
   need access to net driver data anyway. Some net drivers will need to
   reconfigure their ethernet chip for duplex/speed setting changes,
   for example. Passing in the struct net_device* also lets the phy
   code call netif_xxx() functions such as netif_carrier_on()/off()
   mentioned earlier as well as the netif_msg_xxx message control
   macros.

- The callback function is only called by the phy timer poll as
   far as I can tell. Shouldn't it also be called in the phy interrupt
   handler when link state changes?

- Have all phy printk messages controlled by the netif_msg_ macros.

- Many drivers use mii.c to implement ethtool functions. I don't see
   equivalents in your new code.

- Does include/linux/phy.h represent a public API for use by net
   drivers or is it also the internal API used by various C files in
   your phy code?  It seems to contain some data/defs that are
   private to the implementation. Separate some members of struct
   phy_device into public and private parts and move the private bits
   into separate files away from include/linux?

- phy_sanitize_settings() / phy_force_reduction()

   I don't understand why this is done. Are you trying to handle
   link negotiation in software for phy chips that can't autoneg?

Other minor notes:-

- Rename register_mdiobus() --> mdiobus_register()?

- I personally try to avoid listing parameter names in function header
   comment blocks; they seldom contain useful info and they're a
   maintenance overhead. If it would be useful for docbook-generated
   documentation then ok, but your comment blocks don't follow that
   format anyway.

I hope this was useful.

/james

Andy Fleming wrote:

> 
> On Mar 10, 2005, at 17:01, James Chapman wrote:
> 
>> Hi Andy,
>>
>> Can you elaborate on why this phy abstraction is needed?
>>
>> In your original post, you mentioned that you were going to post a
>> patch to show how your code would be hooked up in an existing net
>> driver. Did I miss it? It would help in understanding the pros and cons
>> of using genphy over using plain old mii.c.
> 
> 
> Hi James,
> 
> I haven't posted it yet, since it's a large patch (it deletes a lot of 
> code from my driver), but I can give a basic overview of how my driver 
> hooks into this code:
> 
> 1) The driver connects to the PHY when opened, calling phy_connect, and 
> then clears some bits to declare functionality it doesn't support (my 
> driver, for instance, does not support gigabit in half-duplex mode).
> 
> 2) The driver implements a function which reads the speed/duplex 
> settings, and modifies the controller registers as appropriate (also 
> bringing the carrier up and down depending on link state).  My driver 
> needs to note whether it's gigabit or not (for GMII vs MII mode), and 
> the duplex (to set the MAC full or half).
> 
> Both of those steps are very straightforward.  The PHY layer will invoke 
> the callback whenever the link state changes, so the controller will 
> always be up-to-date.
> 
> 3) The third step is the part that can make things a little messier.  My 
> driver implements a second driver for the MDIO bus, which is connected 
> through its registers.  This bus needs to be registered, and the driver 
> also needs to register.  Then some code needs to be written to deal with 
> initialization, and takedown.  I can send out that patch anytime, if 
> there's demand.
> 
>>
>> btw, I recently posted a patch to add GigE support to mii.c which is
>> in Jeff's netdev-2.6 queue. Some register definitions were added in
>> mii.h that will collide with yours.
> 
> 
> Yeah, I ran in to some of those.  I can't remember whether they're in 
> the patch or not, I suspect not.  I will have to submit a new patch to 
> cover those (I just changed my code to use your definitions).
> 
> Andy

^ permalink raw reply

* Re: [PATCH 3/3] PPC440EP IBM EMAC support
From: Eugene Surovegin @ 2005-03-15 19:22 UTC (permalink / raw)
  To: Wade Farnsworth; +Cc: linuxppc-embedded
In-Reply-To: <1110913134.24673.32.camel@rhino.az.mvista.com>

On Tue, Mar 15, 2005 at 11:58:54AM -0700, Wade Farnsworth wrote:
> This patch adds support to the IBM EMAC ethernet driver for the 440EP.
> 
> Regards,
> Wade Farnsworth
> 
> Signed-off-by: Wade Farnsworth <wfarnsworth@mvista.com>
> 

> --- linux-2.6.11-bk7/drivers/net/ibm_emac/ibm_emac_phy.c	2005-03-02 00:38:13.000000000 -0700
> +++ linux-2.6.11-bk7-440ep/drivers/net/ibm_emac/ibm_emac_phy.c	2005-03-11 16:32:01.000000000 -0700
> @@ -27,6 +27,12 @@
>  
>  #include "ibm_emac_phy.h"
>  
> +#ifdef CONFIG_BAMBOO
> +#define BAMBOO_REV0 (mfspr(PVR) == PVR_440EP_RA)
> +#else
> +#define BAMBOO_REV0 0
> +#endif
> +

I really don't like it. Chip revision doesn't imply which board 
this code is running on. Please, think of some other way to do this or 
drop this completely.

--
Eugene

^ permalink raw reply

* Re: [patch] mpc8560ads mtd map
From: Greg Weeks @ 2005-03-15 19:23 UTC (permalink / raw)
  To: linuxppc-embedded
In-Reply-To: <423732E1.2090906@mvista.com>

Mark A. Greer wrote:

> Greg Weeks wrote:
>
>>
>> Add an MTD map for the flash on the mpc8560ads board.
>>
>> Signed-off-by: Greg Weeks <greg.weeks@timesys.com> 
>
>
>
> <snip>
>
> Most of the code in this patch can be eliminated if you set up the 
> table in your platform file and use the proper CONFIG_MTD_xxx options.
>
> Mark
>
Yep, I pulled this off our 2.6.4 kernel tree. I think it should be in 
the platform code, but I've not tried moving it yet. That should get rid 
of the map file and the Kconfig changes to support it.

Greg Weeks

^ permalink raw reply

* Re: [PATCH 3/3] PPC440EP IBM EMAC support
From: Eugene Surovegin @ 2005-03-15 19:24 UTC (permalink / raw)
  To: Wade Farnsworth, linuxppc-embedded
In-Reply-To: <20050315192216.GB18588@gate.ebshome.net>

On Tue, Mar 15, 2005 at 11:22:16AM -0800, Eugene Surovegin wrote:
> On Tue, Mar 15, 2005 at 11:58:54AM -0700, Wade Farnsworth wrote:
> > This patch adds support to the IBM EMAC ethernet driver for the 440EP.
> > 
> > Regards,
> > Wade Farnsworth
> > 
> > Signed-off-by: Wade Farnsworth <wfarnsworth@mvista.com>
> > 
> 
> > --- linux-2.6.11-bk7/drivers/net/ibm_emac/ibm_emac_phy.c	2005-03-02 00:38:13.000000000 -0700
> > +++ linux-2.6.11-bk7-440ep/drivers/net/ibm_emac/ibm_emac_phy.c	2005-03-11 16:32:01.000000000 -0700
> > @@ -27,6 +27,12 @@
> >  
> >  #include "ibm_emac_phy.h"
> >  
> > +#ifdef CONFIG_BAMBOO
> > +#define BAMBOO_REV0 (mfspr(PVR) == PVR_440EP_RA)
> > +#else
> > +#define BAMBOO_REV0 0
> > +#endif
> > +
> 
> I really don't like it. Chip revision doesn't imply which board 
> this code is running on. Please, think of some other way to do this or 
> drop this completely.
> 

Or to phrase this differently, it's better to avoid any board specific 
code/defines in network driver.

--
Eugene

^ permalink raw reply

* 440EP FPU patch
From: McMullan, Jason @ 2005-03-15 19:31 UTC (permalink / raw)
  To: Wade Farnsworth; +Cc: linuxppc-embedded
In-Reply-To: <1110907039.24673.12.camel@rhino.az.mvista.com>


[-- Attachment #1.1: Type: text/plain, Size: 292 bytes --]

This patch (against vanilla 2.4.11.3) breaks out the FPU code for
PowerPC into a common .S code for all the head*.S files.

Less cargo-culted code.

Wade, you may want to integrate this into your 440EP patch.


-- 
Jason McMullan <jason.mcmullan@timesys.com>
TimeSys Corporation


[-- Attachment #1.2: cpu-ppc-fpu.patch --]
[-- Type: text/x-patch, Size: 19624 bytes --]

#### Auto-generated patch ####
Date:        Tue, 15 Mar 2005 14:27:50 -0500
Maintainer:  Jason McMullan <jason.mcmullan@timesys.com>
Summary:     FPU support on PPC chips that don't use the normal head.S
Signed-Off-By: Jason McMullan <jason.mcmullan@timesys.com>
###############################

Index of changes:

 arch/ppc/Kconfig            |    6 
 arch/ppc/Makefile           |    1 
 arch/ppc/kernel/Makefile    |    1 
 arch/ppc/kernel/head.S      |  276 ----------------------------------------
 arch/ppc/kernel/head_44x.S  |   13 +
 arch/ppc/kernel/traps.c     |    2 
 include/asm-ppc/reg_booke.h |    1 
 linux/arch/ppc/kernel/fpu.S |  297 ++++++++++++++++++++++++++++++++++++++++++++
 8 files changed, 317 insertions(+), 280 deletions(-)


--- linux-orig/arch/ppc/Kconfig
+++ linux/arch/ppc/Kconfig
@@ -53,6 +53,7 @@
 
 config 6xx
 	bool "6xx/7xx/74xx/52xx/8260"
+	select FPU
 	help
 	  There are four types of PowerPC chips supported.  The more common
 	  types (601, 603, 604, 740, 750, 7400), the Motorola embedded
@@ -83,8 +84,11 @@
 
 config E500
 	bool "e500"
+	
+endchoice
 
-endchoice
+config FPU
+	bool
 
 config BOOKE
 	bool
--- linux-orig/arch/ppc/Makefile
+++ linux/arch/ppc/Makefile
@@ -53,6 +53,7 @@
 
 head-$(CONFIG_6xx)		+= arch/ppc/kernel/idle_6xx.o
 head-$(CONFIG_POWER4)		+= arch/ppc/kernel/idle_power4.o
+head-$(CONFIG_FPU)              += arch/ppc/kernel/fpu.o
 
 core-y				+= arch/ppc/kernel/ arch/ppc/platforms/ \
 				   arch/ppc/mm/ arch/ppc/lib/ arch/ppc/syslib/
--- linux-orig/arch/ppc/kernel/Makefile
+++ linux/arch/ppc/kernel/Makefile
@@ -9,6 +9,7 @@
 extra-$(CONFIG_8xx)		:= head_8xx.o
 extra-$(CONFIG_6xx)		+= idle_6xx.o
 extra-$(CONFIG_POWER4)		+= idle_power4.o
+extra-$(CONFIG_FPU)             += fpu.o
 extra-y				+= vmlinux.lds
 
 obj-y				:= entry.o traps.o irq.o idle.o time.o misc.o \
--- /dev/null
+++ linux/arch/ppc/kernel/fpu.S
@@ -0,0 +1,297 @@
+// FPU support code, moved here from head.S so that it can be used
+// by chips which use other head-whatever.S files.
+
+#include <linux/config.h>
+#include <asm/processor.h>
+#include <asm/page.h>
+#include <asm/mmu.h>
+#include <asm/pgtable.h>
+#include <asm/cputable.h>
+#include <asm/cache.h>
+#include <asm/thread_info.h>
+#include <asm/ppc_asm.h>
+#include <asm/offsets.h>
+
+/*
+ * This task wants to use the FPU now.
+ * On UP, disable FP for the task which had the FPU previously,
+ * and save its floating-point registers in its thread_struct.
+ * Load up this task's FP registers from its thread_struct,
+ * enable the FPU for the current task and return to the task.
+ */
+	.global load_up_fpu
+load_up_fpu:
+	mfmsr	r5
+	ori	r5,r5,MSR_FP
+#ifdef CONFIG_PPC64BRIDGE
+	clrldi	r5,r5,1			/* turn off 64-bit mode */
+#endif /* CONFIG_PPC64BRIDGE */
+	SYNC
+	MTMSRD(r5)			/* enable use of fpu now */
+	isync
+/*
+ * For SMP, we don't do lazy FPU switching because it just gets too
+ * horrendously complex, especially when a task switches from one CPU
+ * to another.  Instead we call giveup_fpu in switch_to.
+ */
+#ifndef CONFIG_SMP
+	tophys(r6,0)			/* get __pa constant */
+	addis	r3,r6,last_task_used_math@ha
+	lwz	r4,last_task_used_math@l(r3)
+	cmpwi	0,r4,0
+	beq	1f
+	add	r4,r4,r6
+	addi	r4,r4,THREAD		/* want last_task_used_math->thread */
+	SAVE_32FPRS(0, r4)
+	mffs	fr0
+	stfd	fr0,THREAD_FPSCR-4(r4)
+	lwz	r5,PT_REGS(r4)
+	add	r5,r5,r6
+	lwz	r4,_MSR-STACK_FRAME_OVERHEAD(r5)
+	li	r10,MSR_FP|MSR_FE0|MSR_FE1
+	andc	r4,r4,r10		/* disable FP for previous task */
+	stw	r4,_MSR-STACK_FRAME_OVERHEAD(r5)
+1:
+#endif /* CONFIG_SMP */
+	/* enable use of FP after return */
+	mfspr	r5,SPRG3		/* current task's THREAD (phys) */
+	lwz	r4,THREAD_FPEXC_MODE(r5)
+	ori	r9,r9,MSR_FP		/* enable FP for current */
+	or	r9,r9,r4
+	lfd	fr0,THREAD_FPSCR-4(r5)
+	mtfsf	0xff,fr0
+	REST_32FPRS(0, r5)
+#ifndef CONFIG_SMP
+	subi	r4,r5,THREAD
+	sub	r4,r4,r6
+	stw	r4,last_task_used_math@l(r3)
+#endif /* CONFIG_SMP */
+	/* restore registers and return */
+	/* we haven't used ctr or xer or lr */
+	/* fall through to fast_exception_return */
+
+	.global fast_exception_return
+fast_exception_return:
+#if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE))
+	andi.	r10,r9,MSR_RI		/* check for recoverable interrupt */
+	beq	1f			/* if not, we've got problems */
+#endif
+
+2:	REST_4GPRS(3, r11)
+	lwz	r10,_CCR(r11)
+	REST_GPR(1, r11)
+	mtcr	r10
+	lwz	r10,_LINK(r11)
+	mtlr	r10
+	REST_GPR(10, r11)
+	mtspr	SRR1,r9
+	mtspr	SRR0,r12
+	REST_GPR(9, r11)
+	REST_GPR(12, r11)
+	lwz	r11,GPR11(r11)
+	SYNC
+	RFI
+
+/* check if the exception happened in a restartable section */
+1:	lis	r3,exc_exit_restart_end@ha
+	addi	r3,r3,exc_exit_restart_end@l
+	cmplw	r12,r3
+	bge	3f
+	lis	r4,exc_exit_restart@ha
+	addi	r4,r4,exc_exit_restart@l
+	cmplw	r12,r4
+	blt	3f
+	lis	r3,fee_restarts@ha
+	tophys(r3,r3)
+	lwz	r5,fee_restarts@l(r3)
+	addi	r5,r5,1
+	stw	r5,fee_restarts@l(r3)
+	mr	r12,r4		/* restart at exc_exit_restart */
+	b	2b
+
+	.comm	fee_restarts,4
+
+/* aargh, a nonrecoverable interrupt, panic */
+/* aargh, we don't know which trap this is */
+/* but the 601 doesn't implement the RI bit, so assume it's OK */
+3:
+BEGIN_FTR_SECTION
+	b	2b
+END_FTR_SECTION_IFSET(CPU_FTR_601)
+	li	r10,-1
+	stw	r10,TRAP(r11)
+	addi	r3,r1,STACK_FRAME_OVERHEAD
+	lis	r10, MSR_KERNEL@h
+	ori	r10, r10, MSR_KERNEL@l
+	bl	transfer_to_handler_full
+	.long	nonrecoverable_exception
+	.long	ret_from_except
+
+/*
+ * FP unavailable trap from kernel - print a message, but let
+ * the task use FP in the kernel until it returns to user mode.
+ */
+ 	.global KernelFP
+KernelFP:
+	lwz	r3,_MSR(r1)
+	ori	r3,r3,MSR_FP
+	stw	r3,_MSR(r1)		/* enable use of FP after return */
+	lis	r3,86f@h
+	ori	r3,r3,86f@l
+	mr	r4,r2			/* current */
+	lwz	r5,_NIP(r1)
+	bl	printk
+	b	ret_from_except
+86:	.string	"floating point used in kernel (task=%p, pc=%x)\n"
+	.align	4,0
+
+#ifdef CONFIG_ALTIVEC
+/* Note that the AltiVec support is closely modeled after the FP
+ * support.  Changes to one are likely to be applicable to the
+ * other!  */
+ 	.global load_up_altivec
+load_up_altivec:
+/*
+ * Disable AltiVec for the task which had AltiVec previously,
+ * and save its AltiVec registers in its thread_struct.
+ * Enables AltiVec for use in the kernel on return.
+ * On SMP we know the AltiVec units are free, since we give it up every
+ * switch.  -- Kumar
+ */
+	mfmsr	r5
+	oris	r5,r5,MSR_VEC@h
+	MTMSRD(r5)			/* enable use of AltiVec now */
+	isync
+/*
+ * For SMP, we don't do lazy AltiVec switching because it just gets too
+ * horrendously complex, especially when a task switches from one CPU
+ * to another.  Instead we call giveup_altivec in switch_to.
+ */
+#ifndef CONFIG_SMP
+	tophys(r6,0)
+	addis	r3,r6,last_task_used_altivec@ha
+	lwz	r4,last_task_used_altivec@l(r3)
+	cmpwi	0,r4,0
+	beq	1f
+	add	r4,r4,r6
+	addi	r4,r4,THREAD	/* want THREAD of last_task_used_altivec */
+	SAVE_32VR(0,r10,r4)
+	mfvscr	vr0
+	li	r10,THREAD_VSCR
+	stvx	vr0,r10,r4
+	lwz	r5,PT_REGS(r4)
+	add	r5,r5,r6
+	lwz	r4,_MSR-STACK_FRAME_OVERHEAD(r5)
+	lis	r10,MSR_VEC@h
+	andc	r4,r4,r10	/* disable altivec for previous task */
+	stw	r4,_MSR-STACK_FRAME_OVERHEAD(r5)
+1:
+#endif /* CONFIG_SMP */
+	/* enable use of AltiVec after return */
+	oris	r9,r9,MSR_VEC@h
+	mfspr	r5,SPRG3		/* current task's THREAD (phys) */
+	li	r4,1
+	li	r10,THREAD_VSCR
+	stw	r4,THREAD_USED_VR(r5)
+	lvx	vr0,r10,r5
+	mtvscr	vr0
+	REST_32VR(0,r10,r5)
+#ifndef CONFIG_SMP
+	subi	r4,r5,THREAD
+	sub	r4,r4,r6
+	stw	r4,last_task_used_altivec@l(r3)
+#endif /* CONFIG_SMP */
+	/* restore registers and return */
+	/* we haven't used ctr or xer or lr */
+	b	fast_exception_return
+
+/*
+ * AltiVec unavailable trap from kernel - print a message, but let
+ * the task use AltiVec in the kernel until it returns to user mode.
+ */
+ 	.global KernelAltiVec
+KernelAltiVec:
+	lwz	r3,_MSR(r1)
+	oris	r3,r3,MSR_VEC@h
+	stw	r3,_MSR(r1)	/* enable use of AltiVec after return */
+	lis	r3,87f@h
+	ori	r3,r3,87f@l
+	mr	r4,r2		/* current */
+	lwz	r5,_NIP(r1)
+	bl	printk
+	b	ret_from_except
+87:	.string	"AltiVec used in kernel  (task=%p, pc=%x)  \n"
+	.align	4,0
+
+/*
+ * giveup_altivec(tsk)
+ * Disable AltiVec for the task given as the argument,
+ * and save the AltiVec registers in its thread_struct.
+ * Enables AltiVec for use in the kernel on return.
+ */
+
+	.global giveup_altivec
+giveup_altivec:
+	mfmsr	r5
+	oris	r5,r5,MSR_VEC@h
+	SYNC
+	MTMSRD(r5)			/* enable use of AltiVec now */
+	isync
+	cmpwi	0,r3,0
+	beqlr-				/* if no previous owner, done */
+	addi	r3,r3,THREAD		/* want THREAD of task */
+	lwz	r5,PT_REGS(r3)
+	cmpwi	0,r5,0
+	SAVE_32VR(0, r4, r3)
+	mfvscr	vr0
+	li	r4,THREAD_VSCR
+	stvx	vr0,r4,r3
+	beq	1f
+	lwz	r4,_MSR-STACK_FRAME_OVERHEAD(r5)
+	lis	r3,MSR_VEC@h
+	andc	r4,r4,r3		/* disable AltiVec for previous task */
+	stw	r4,_MSR-STACK_FRAME_OVERHEAD(r5)
+1:
+#ifndef CONFIG_SMP
+	li	r5,0
+	lis	r4,last_task_used_altivec@ha
+	stw	r5,last_task_used_altivec@l(r4)
+#endif /* CONFIG_SMP */
+	blr
+#endif /* CONFIG_ALTIVEC */
+
+/*
+ * giveup_fpu(tsk)
+ * Disable FP for the task given as the argument,
+ * and save the floating-point registers in its thread_struct.
+ * Enables the FPU for use in the kernel on return.
+ */
+	.global giveup_fpu
+giveup_fpu:
+	mfmsr	r5
+	ori	r5,r5,MSR_FP
+	SYNC_601
+	ISYNC_601
+	MTMSRD(r5)			/* enable use of fpu now */
+	SYNC_601
+	isync
+	cmpwi	0,r3,0
+	beqlr-				/* if no previous owner, done */
+	addi	r3,r3,THREAD	        /* want THREAD of task */
+	lwz	r5,PT_REGS(r3)
+	cmpwi	0,r5,0
+	SAVE_32FPRS(0, r3)
+	mffs	fr0
+	stfd	fr0,THREAD_FPSCR-4(r3)
+	beq	1f
+	lwz	r4,_MSR-STACK_FRAME_OVERHEAD(r5)
+	li	r3,MSR_FP|MSR_FE0|MSR_FE1
+	andc	r4,r4,r3		/* disable FP for previous task */
+	stw	r4,_MSR-STACK_FRAME_OVERHEAD(r5)
+1:
+#ifndef CONFIG_SMP
+	li	r5,0
+	lis	r4,last_task_used_math@ha
+	stw	r5,last_task_used_math@l(r4)
+#endif /* CONFIG_SMP */
+	blr

--- linux-orig/arch/ppc/kernel/head.S
+++ linux/arch/ppc/kernel/head.S
@@ -776,282 +776,6 @@
 #endif /* CONFIG_PPC64BRIDGE */
 
 /*
- * This task wants to use the FPU now.
- * On UP, disable FP for the task which had the FPU previously,
- * and save its floating-point registers in its thread_struct.
- * Load up this task's FP registers from its thread_struct,
- * enable the FPU for the current task and return to the task.
- */
-load_up_fpu:
-	mfmsr	r5
-	ori	r5,r5,MSR_FP
-#ifdef CONFIG_PPC64BRIDGE
-	clrldi	r5,r5,1			/* turn off 64-bit mode */
-#endif /* CONFIG_PPC64BRIDGE */
-	SYNC
-	MTMSRD(r5)			/* enable use of fpu now */
-	isync
-/*
- * For SMP, we don't do lazy FPU switching because it just gets too
- * horrendously complex, especially when a task switches from one CPU
- * to another.  Instead we call giveup_fpu in switch_to.
- */
-#ifndef CONFIG_SMP
-	tophys(r6,0)			/* get __pa constant */
-	addis	r3,r6,last_task_used_math@ha
-	lwz	r4,last_task_used_math@l(r3)
-	cmpwi	0,r4,0
-	beq	1f
-	add	r4,r4,r6
-	addi	r4,r4,THREAD		/* want last_task_used_math->thread */
-	SAVE_32FPRS(0, r4)
-	mffs	fr0
-	stfd	fr0,THREAD_FPSCR-4(r4)
-	lwz	r5,PT_REGS(r4)
-	add	r5,r5,r6
-	lwz	r4,_MSR-STACK_FRAME_OVERHEAD(r5)
-	li	r10,MSR_FP|MSR_FE0|MSR_FE1
-	andc	r4,r4,r10		/* disable FP for previous task */
-	stw	r4,_MSR-STACK_FRAME_OVERHEAD(r5)
-1:
-#endif /* CONFIG_SMP */
-	/* enable use of FP after return */
-	mfspr	r5,SPRG3		/* current task's THREAD (phys) */
-	lwz	r4,THREAD_FPEXC_MODE(r5)
-	ori	r9,r9,MSR_FP		/* enable FP for current */
-	or	r9,r9,r4
-	lfd	fr0,THREAD_FPSCR-4(r5)
-	mtfsf	0xff,fr0
-	REST_32FPRS(0, r5)
-#ifndef CONFIG_SMP
-	subi	r4,r5,THREAD
-	sub	r4,r4,r6
-	stw	r4,last_task_used_math@l(r3)
-#endif /* CONFIG_SMP */
-	/* restore registers and return */
-	/* we haven't used ctr or xer or lr */
-	/* fall through to fast_exception_return */
-
-	.globl	fast_exception_return
-fast_exception_return:
-	andi.	r10,r9,MSR_RI		/* check for recoverable interrupt */
-	beq	1f			/* if not, we've got problems */
-2:	REST_4GPRS(3, r11)
-	lwz	r10,_CCR(r11)
-	REST_GPR(1, r11)
-	mtcr	r10
-	lwz	r10,_LINK(r11)
-	mtlr	r10
-	REST_GPR(10, r11)
-	mtspr	SRR1,r9
-	mtspr	SRR0,r12
-	REST_GPR(9, r11)
-	REST_GPR(12, r11)
-	lwz	r11,GPR11(r11)
-	SYNC
-	RFI
-
-/* check if the exception happened in a restartable section */
-1:	lis	r3,exc_exit_restart_end@ha
-	addi	r3,r3,exc_exit_restart_end@l
-	cmplw	r12,r3
-	bge	3f
-	lis	r4,exc_exit_restart@ha
-	addi	r4,r4,exc_exit_restart@l
-	cmplw	r12,r4
-	blt	3f
-	lis	r3,fee_restarts@ha
-	tophys(r3,r3)
-	lwz	r5,fee_restarts@l(r3)
-	addi	r5,r5,1
-	stw	r5,fee_restarts@l(r3)
-	mr	r12,r4		/* restart at exc_exit_restart */
-	b	2b
-
-	.comm	fee_restarts,4
-
-/* aargh, a nonrecoverable interrupt, panic */
-/* aargh, we don't know which trap this is */
-/* but the 601 doesn't implement the RI bit, so assume it's OK */
-3:
-BEGIN_FTR_SECTION
-	b	2b
-END_FTR_SECTION_IFSET(CPU_FTR_601)
-	li	r10,-1
-	stw	r10,TRAP(r11)
-	addi	r3,r1,STACK_FRAME_OVERHEAD
-	li	r10,MSR_KERNEL
-	bl	transfer_to_handler_full
-	.long	nonrecoverable_exception
-	.long	ret_from_except
-
-/*
- * FP unavailable trap from kernel - print a message, but let
- * the task use FP in the kernel until it returns to user mode.
- */
-KernelFP:
-	lwz	r3,_MSR(r1)
-	ori	r3,r3,MSR_FP
-	stw	r3,_MSR(r1)		/* enable use of FP after return */
-	lis	r3,86f@h
-	ori	r3,r3,86f@l
-	mr	r4,r2			/* current */
-	lwz	r5,_NIP(r1)
-	bl	printk
-	b	ret_from_except
-86:	.string	"floating point used in kernel (task=%p, pc=%x)\n"
-	.align	4,0
-
-#ifdef CONFIG_ALTIVEC
-/* Note that the AltiVec support is closely modeled after the FP
- * support.  Changes to one are likely to be applicable to the
- * other!  */
-load_up_altivec:
-/*
- * Disable AltiVec for the task which had AltiVec previously,
- * and save its AltiVec registers in its thread_struct.
- * Enables AltiVec for use in the kernel on return.
- * On SMP we know the AltiVec units are free, since we give it up every
- * switch.  -- Kumar
- */
-	mfmsr	r5
-	oris	r5,r5,MSR_VEC@h
-	MTMSRD(r5)			/* enable use of AltiVec now */
-	isync
-/*
- * For SMP, we don't do lazy AltiVec switching because it just gets too
- * horrendously complex, especially when a task switches from one CPU
- * to another.  Instead we call giveup_altivec in switch_to.
- */
-#ifndef CONFIG_SMP
-	tophys(r6,0)
-	addis	r3,r6,last_task_used_altivec@ha
-	lwz	r4,last_task_used_altivec@l(r3)
-	cmpwi	0,r4,0
-	beq	1f
-	add	r4,r4,r6
-	addi	r4,r4,THREAD	/* want THREAD of last_task_used_altivec */
-	SAVE_32VR(0,r10,r4)
-	mfvscr	vr0
-	li	r10,THREAD_VSCR
-	stvx	vr0,r10,r4
-	lwz	r5,PT_REGS(r4)
-	add	r5,r5,r6
-	lwz	r4,_MSR-STACK_FRAME_OVERHEAD(r5)
-	lis	r10,MSR_VEC@h
-	andc	r4,r4,r10	/* disable altivec for previous task */
-	stw	r4,_MSR-STACK_FRAME_OVERHEAD(r5)
-1:
-#endif /* CONFIG_SMP */
-	/* enable use of AltiVec after return */
-	oris	r9,r9,MSR_VEC@h
-	mfspr	r5,SPRG3		/* current task's THREAD (phys) */
-	li	r4,1
-	li	r10,THREAD_VSCR
-	stw	r4,THREAD_USED_VR(r5)
-	lvx	vr0,r10,r5
-	mtvscr	vr0
-	REST_32VR(0,r10,r5)
-#ifndef CONFIG_SMP
-	subi	r4,r5,THREAD
-	sub	r4,r4,r6
-	stw	r4,last_task_used_altivec@l(r3)
-#endif /* CONFIG_SMP */
-	/* restore registers and return */
-	/* we haven't used ctr or xer or lr */
-	b	fast_exception_return
-
-/*
- * AltiVec unavailable trap from kernel - print a message, but let
- * the task use AltiVec in the kernel until it returns to user mode.
- */
-KernelAltiVec:
-	lwz	r3,_MSR(r1)
-	oris	r3,r3,MSR_VEC@h
-	stw	r3,_MSR(r1)	/* enable use of AltiVec after return */
-	lis	r3,87f@h
-	ori	r3,r3,87f@l
-	mr	r4,r2		/* current */
-	lwz	r5,_NIP(r1)
-	bl	printk
-	b	ret_from_except
-87:	.string	"AltiVec used in kernel  (task=%p, pc=%x)  \n"
-	.align	4,0
-
-/*
- * giveup_altivec(tsk)
- * Disable AltiVec for the task given as the argument,
- * and save the AltiVec registers in its thread_struct.
- * Enables AltiVec for use in the kernel on return.
- */
-
-	.globl	giveup_altivec
-giveup_altivec:
-	mfmsr	r5
-	oris	r5,r5,MSR_VEC@h
-	SYNC
-	MTMSRD(r5)			/* enable use of AltiVec now */
-	isync
-	cmpwi	0,r3,0
-	beqlr-				/* if no previous owner, done */
-	addi	r3,r3,THREAD		/* want THREAD of task */
-	lwz	r5,PT_REGS(r3)
-	cmpwi	0,r5,0
-	SAVE_32VR(0, r4, r3)
-	mfvscr	vr0
-	li	r4,THREAD_VSCR
-	stvx	vr0,r4,r3
-	beq	1f
-	lwz	r4,_MSR-STACK_FRAME_OVERHEAD(r5)
-	lis	r3,MSR_VEC@h
-	andc	r4,r4,r3		/* disable AltiVec for previous task */
-	stw	r4,_MSR-STACK_FRAME_OVERHEAD(r5)
-1:
-#ifndef CONFIG_SMP
-	li	r5,0
-	lis	r4,last_task_used_altivec@ha
-	stw	r5,last_task_used_altivec@l(r4)
-#endif /* CONFIG_SMP */
-	blr
-#endif /* CONFIG_ALTIVEC */
-
-/*
- * giveup_fpu(tsk)
- * Disable FP for the task given as the argument,
- * and save the floating-point registers in its thread_struct.
- * Enables the FPU for use in the kernel on return.
- */
-	.globl	giveup_fpu
-giveup_fpu:
-	mfmsr	r5
-	ori	r5,r5,MSR_FP
-	SYNC_601
-	ISYNC_601
-	MTMSRD(r5)			/* enable use of fpu now */
-	SYNC_601
-	isync
-	cmpwi	0,r3,0
-	beqlr-				/* if no previous owner, done */
-	addi	r3,r3,THREAD	        /* want THREAD of task */
-	lwz	r5,PT_REGS(r3)
-	cmpwi	0,r5,0
-	SAVE_32FPRS(0, r3)
-	mffs	fr0
-	stfd	fr0,THREAD_FPSCR-4(r3)
-	beq	1f
-	lwz	r4,_MSR-STACK_FRAME_OVERHEAD(r5)
-	li	r3,MSR_FP|MSR_FE0|MSR_FE1
-	andc	r4,r4,r3		/* disable FP for previous task */
-	stw	r4,_MSR-STACK_FRAME_OVERHEAD(r5)
-1:
-#ifndef CONFIG_SMP
-	li	r5,0
-	lis	r4,last_task_used_math@ha
-	stw	r5,last_task_used_math@l(r4)
-#endif /* CONFIG_SMP */
-	blr
-
-/*
  * This code is jumped to from the startup code to copy
  * the kernel image to physical address 0.
  */
--- linux-orig/arch/ppc/kernel/head_44x.S
+++ linux/arch/ppc/kernel/head_44x.S
@@ -425,8 +425,15 @@
 	/* Program Interrupt */
 	PROGRAM_EXCEPTION
 
-	/* Floating Point Unavailable Interrupt */
+#ifdef CONFIG_FPU
+	START_EXCEPTION(FloatingPointUnavailable)
+	NORMAL_EXCEPTION_PROLOG
+	bne	load_up_fpu		/* if from user, just load it up */
+	addi	r3,r1,STACK_FRAME_OVERHEAD
+	EXC_XFER_EE_LITE(0x800, KernelFP)
+#else
 	EXCEPTION(0x2010, FloatingPointUnavailable, UnknownException, EXC_XFER_EE)
+#endif
 
 	/* System Call Interrupt */
 	START_EXCEPTION(SystemCall)
@@ -686,9 +693,11 @@
  *
  * The 44x core does not have an FPU.
  */
+#ifndef CONFIG_FPU
 _GLOBAL(giveup_fpu)
 	blr
-
+#endif
+ 
 /*
  * extern void abort(void)
  *
--- linux-orig/arch/ppc/kernel/traps.c
+++ linux/arch/ppc/kernel/traps.c
@@ -176,7 +176,7 @@
 #else
 #define get_mc_reason(regs)	(mfspr(SPRN_MCSR))
 #endif
-#define REASON_FP		0
+#define REASON_FP		ESR_FP
 #define REASON_ILLEGAL		ESR_PIL
 #define REASON_PRIVILEGED	ESR_PPR
 #define REASON_TRAP		ESR_PTR
--- linux-orig/include/asm-ppc/reg_booke.h
+++ linux/include/asm-ppc/reg_booke.h
@@ -305,6 +305,7 @@
 #define ESR_PIL		0x08000000	/* Program Exception - Illegal */
 #define ESR_PPR		0x04000000	/* Program Exception - Priveleged */
 #define ESR_PTR		0x02000000	/* Program Exception - Trap */
+#define ESR_FP          0x01000000      /* Floating Point Operation */
 #define ESR_DST		0x00800000	/* Storage Exception - Data miss */
 #define ESR_DIZ		0x00400000	/* Storage Exception - Zone fault */
 #define ESR_ST		0x00800000	/* Store Operation */

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^ permalink raw reply

* [PATCH 2.6.11] ppc32: update Radstone ppc7d platform for enet/i2c
From: James Chapman @ 2005-03-15 19:52 UTC (permalink / raw)
  To: Mark A. Greer; +Cc: Linuxppc-Embedded

[-- Attachment #1: Type: text/plain, Size: 1 bytes --]



[-- Attachment #2: ppc7d-platdata.patch --]
[-- Type: text/plain, Size: 6142 bytes --]

ppc32: add ethernet and I2C support to Radstone PPC7D platform

Signed-off-by: James Chapman <jchapman@katalix.com>

Change default platform config to add mv643xx_eth and mv64xxx-i2c
config options. Add i2c platform data and update to cope with the
recent platform device name change.

Index: linux-2.6/arch/ppc/platforms/radstone_ppc7d.c
===================================================================
--- linux-2.6.orig/arch/ppc/platforms/radstone_ppc7d.c	2005-03-15 19:29:22.000000000 +0000
+++ linux-2.6/arch/ppc/platforms/radstone_ppc7d.c	2005-03-15 19:35:02.000000000 +0000
@@ -669,6 +669,42 @@
 }
 #endif
 
+#if defined(CONFIG_I2C_MV64XXX)
+static void __init
+ppc7d_fixup_i2c_pdata(struct platform_device *pdev)
+{
+	struct mv64xxx_i2c_pdata *pdata;
+	int i;
+
+	pdata = pdev->dev.platform_data;
+	if (pdata == NULL) {
+		pdata = kmalloc(GFP_KERNEL, sizeof(*pdata));
+		if (pdata == NULL)
+			return;
+
+		memset(pdata, 0, sizeof(*pdata));
+		pdev->dev.platform_data = pdata;
+	}
+
+	/* divisors M=8, N=3 for 100kHz I2C from 133MHz system clock */
+	pdata->freq_m = 8;
+	pdata->freq_n = 3;
+	pdata->timeout = 500;
+	pdata->retries = 3;
+
+	/* Adjust IRQ by mv64360_irq_base */
+	for (i = 0; i < pdev->num_resources; i++) {
+		struct resource *r = &pdev->resource[i];
+
+		if (r->flags & IORESOURCE_IRQ) {
+			r->start += mv64360_irq_base;
+			r->end += mv64360_irq_base;
+			pr_debug("%s, uses IRQ %d\n", pdev->name, (int) r->start);
+		}
+	}
+}
+#endif
+
 static int __init ppc7d_platform_notify(struct device *dev)
 {
 	static struct {
@@ -676,13 +712,16 @@
 		void ((*rtn) (struct platform_device * pdev));
 	} dev_map[] = {
 #if defined(CONFIG_SERIAL_MPSC)
-		{ MPSC_CTLR_NAME "0", ppc7d_fixup_mpsc_pdata },
-		{ MPSC_CTLR_NAME "1", ppc7d_fixup_mpsc_pdata },
+		{ MPSC_CTLR_NAME ".0", ppc7d_fixup_mpsc_pdata },
+		{ MPSC_CTLR_NAME ".1", ppc7d_fixup_mpsc_pdata },
 #endif
 #if defined(CONFIG_MV643XX_ETH)
-		{ MV643XX_ETH_NAME "0", ppc7d_fixup_eth_pdata },
-		{ MV643XX_ETH_NAME "1", ppc7d_fixup_eth_pdata },
-		{ MV643XX_ETH_NAME "2", ppc7d_fixup_eth_pdata },
+		{ MV643XX_ETH_NAME ".0", ppc7d_fixup_eth_pdata },
+		{ MV643XX_ETH_NAME ".1", ppc7d_fixup_eth_pdata },
+		{ MV643XX_ETH_NAME ".2", ppc7d_fixup_eth_pdata },
+#endif
+#if defined(CONFIG_I2C_MV64XXX)
+		{ MV64XXX_I2C_CTLR_NAME ".0", ppc7d_fixup_i2c_pdata },
 #endif
 	};
 	struct platform_device *pdev;
@@ -1363,7 +1402,8 @@
 
 	ppc_md.pcibios_fixup_bus = ppc7d_pci_fixup_bus;
 
-#if defined(CONFIG_SERIAL_MPSC) || defined(CONFIG_MV643XX_ETH)
+#if defined(CONFIG_SERIAL_MPSC) || defined(CONFIG_MV643XX_ETH) || \
+    defined(CONFIG_I2C_MV64XXX)
 	platform_notify = ppc7d_platform_notify;
 #endif
 
@@ -1405,4 +1445,8 @@
 	rev_num = (val8 & PPC7D_CPLD_BOARD_REVISION_NUMBER_MASK) >> 5;
 	if (rev_num <= 1)
 		ppc7d_has_alma = 1;
+
+#ifdef DEBUG
+	console_printk[0] = 8;
+#endif
 }
Index: linux-2.6/arch/ppc/configs/radstone_ppc7d_defconfig
===================================================================
--- linux-2.6.orig/arch/ppc/configs/radstone_ppc7d_defconfig	2005-03-15 19:29:22.000000000 +0000
+++ linux-2.6/arch/ppc/configs/radstone_ppc7d_defconfig	2005-03-15 19:30:50.000000000 +0000
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
 # Linux kernel version: 2.6.11
-# Tue Mar 15 11:11:47 2005
+# Tue Mar 15 14:31:19 2005
 #
 CONFIG_MMU=y
 CONFIG_GENERIC_HARDIRQS=y
@@ -514,7 +514,10 @@
 CONFIG_SK98LIN=y
 # CONFIG_VIA_VELOCITY is not set
 CONFIG_TIGON3=y
-# CONFIG_MV643XX_ETH is not set
+CONFIG_MV643XX_ETH=y
+CONFIG_MV643XX_ETH_0=y
+CONFIG_MV643XX_ETH_1=y
+# CONFIG_MV643XX_ETH_2 is not set
 
 #
 # Ethernet (10000 Mbit)
@@ -667,7 +670,90 @@
 #
 # I2C support
 #
-# CONFIG_I2C is not set
+CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
+
+#
+# I2C Algorithms
+#
+# CONFIG_I2C_ALGOBIT is not set
+# CONFIG_I2C_ALGOPCF is not set
+# CONFIG_I2C_ALGOPCA is not set
+
+#
+# I2C Hardware Bus support
+#
+# CONFIG_I2C_ALI1535 is not set
+# CONFIG_I2C_ALI1563 is not set
+# CONFIG_I2C_ALI15X3 is not set
+# CONFIG_I2C_AMD756 is not set
+# CONFIG_I2C_AMD8111 is not set
+# CONFIG_I2C_I801 is not set
+# CONFIG_I2C_I810 is not set
+# CONFIG_I2C_ISA is not set
+# CONFIG_I2C_MPC is not set
+# CONFIG_I2C_NFORCE2 is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_PIIX4 is not set
+# CONFIG_I2C_PROSAVAGE is not set
+# CONFIG_I2C_SAVAGE4 is not set
+# CONFIG_SCx200_ACB is not set
+# CONFIG_I2C_SIS5595 is not set
+# CONFIG_I2C_SIS630 is not set
+# CONFIG_I2C_SIS96X is not set
+# CONFIG_I2C_STUB is not set
+# CONFIG_I2C_VIA is not set
+# CONFIG_I2C_VIAPRO is not set
+# CONFIG_I2C_VOODOO3 is not set
+# CONFIG_I2C_PCA_ISA is not set
+CONFIG_I2C_MV64XXX=y
+
+#
+# Hardware Sensors Chip support
+#
+CONFIG_I2C_SENSOR=y
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ASB100 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_FSCHER is not set
+# CONFIG_SENSORS_FSCPOS is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_LM63 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM87 is not set
+CONFIG_SENSORS_LM90=y
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_SIS5595 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_VIA686A is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83627HF is not set
+
+#
+# Other I2C Chip support
+#
+# CONFIG_SENSORS_EEPROM is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_RTC8564 is not set
+# CONFIG_SENSORS_M41T00 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
 
 #
 # Dallas's 1-wire bus

^ permalink raw reply

* [patch] mpc8560ads mtd platform
From: Greg Weeks @ 2005-03-15 20:19 UTC (permalink / raw)
  To: linuxppc-embedded

[-- Attachment #1: Type: text/plain, Size: 123 bytes --]

Add an MTD partitions in the platform code for the mpc8560ads board.

Signed-off-by: Greg Weeks <greg.weeks@timesys.com>



[-- Attachment #2: mpc8560ads.mtd.paltform.patch --]
[-- Type: text/x-patch, Size: 4168 bytes --]

--- ppc-mpc8560ads/arch/ppc/configs/mpc8560_ads_defconfig-orig
+++ ppc-mpc8560ads/arch/ppc/configs/mpc8560_ads_defconfig

@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.11-rc1
-# Thu Jan 20 01:24:56 2005
+# Linux kernel version: 2.6.11.3
+# Tue Mar 15 15:06:17 2005
 #
 CONFIG_MMU=y
 CONFIG_GENERIC_HARDIRQS=y
@@ -75,6 +75,7 @@
 # CONFIG_MPC8555_CDS is not set
 CONFIG_MPC8560_ADS=y
 # CONFIG_SBC8560 is not set
+# CONFIG_STX_GP3 is not set
 CONFIG_MPC8560=y
 
 #
@@ -134,7 +135,78 @@
 #
 # Memory Technology Devices (MTD)
 #
-# CONFIG_MTD is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_CONCAT is not set
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+CONFIG_MTD_CFI_INTELEXT=y
+# CONFIG_MTD_CFI_AMDSTD is not set
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+# CONFIG_MTD_XIP is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_PHYSMAP_START=0xff000000
+CONFIG_MTD_PHYSMAP_LEN=0x01000000
+CONFIG_MTD_PHYSMAP_BANKWIDTH=4
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLKMTD is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+
+#
+# NAND Flash Device Drivers
+#
+# CONFIG_MTD_NAND is not set
 
 #
 # Parallel port support
@@ -540,7 +612,6 @@
 # Graphics support
 #
 # CONFIG_FB is not set
-# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
 
 #
 # Sound
@@ -587,6 +658,10 @@
 CONFIG_FS_MBCACHE=y
 # CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
+
+#
+# XFS support
+#
 # CONFIG_XFS_FS is not set
 # CONFIG_MINIX_FS is not set
 # CONFIG_ROMFS_FS is not set
@@ -631,6 +706,8 @@
 # CONFIG_BEFS_FS is not set
 # CONFIG_BFS_FS is not set
 # CONFIG_EFS_FS is not set
+# CONFIG_JFFS_FS is not set
+# CONFIG_JFFS2_FS is not set
 # CONFIG_CRAMFS is not set
 # CONFIG_VXFS_FS is not set
 # CONFIG_HPFS_FS is not set
@@ -648,7 +725,6 @@
 # CONFIG_NFSD is not set
 CONFIG_ROOT_NFS=y
 CONFIG_LOCKD=y
-# CONFIG_EXPORTFS is not set
 CONFIG_SUNRPC=y
 # CONFIG_RPCSEC_GSS_KRB5 is not set
 # CONFIG_RPCSEC_GSS_SPKM3 is not set

--- ppc-mpc8560ads/arch/ppc/platforms/85xx/mpc8560_ads.c-orig
+++ ppc-mpc8560ads/arch/ppc/platforms/85xx/mpc8560_ads.c

@@ -30,6 +30,7 @@
 #include <linux/serial.h>
 #include <linux/tty.h>	/* for linux/serial_core.h */
 #include <linux/serial_core.h>
+#include <linux/mtd/physmap.h>
 #include <linux/initrd.h>
 #include <linux/module.h>
 #include <linux/fsl_devices.h>
@@ -220,3 +221,39 @@
 
 	return;
 }
+
+#ifdef CONFIG_MTD_PHYSMAP
+static struct mtd_partition mpc85xxads_partitions[] = {
+	{
+		.name =   "Linux JFFS2 Filesystem",
+		.offset = 0x0,
+		.size =   0x00800000,
+	},
+	{
+		.name =   "Linux Kernel",
+		.offset = 0x00800000,
+		.size =   0x00200000,
+	},
+	{
+		.name =   "Linux INITRD",
+		.offset = 0x00a00000,
+		.size =   0x00580000,
+	},
+	{
+		.name	= "Bootloader",
+		.offset	= 0x00f80000,
+		.size	= 0x00080000,
+	}
+};
+
+static int __init
+mpc8560ads_setup_mtd(void)
+{
+
+	physmap_set_partitions(&mpc85xxads_partitions[0], 4);
+	return 0;
+}
+
+arch_initcall(mpc8560ads_setup_mtd);
+
+#endif

^ permalink raw reply

* Re: mtd maps
From: Matt Porter @ 2005-03-15 20:32 UTC (permalink / raw)
  To: Mark A. Greer; +Cc: linuxppc-embedded
In-Reply-To: <42372CF0.6040901@mvista.com>

On Tue, Mar 15, 2005 at 11:44:00AM -0700, Mark A. Greer wrote:
> Greg Weeks wrote:
> 
> > Are mtd maps still in drivers/mtd/maps or has that all moved to the 
> > platform code? I have an mtd map for the mpc8560ads but it's in mtd/maps.
> 
> 
> The mtd code has changed so that platform code can get at the routines 
> to set up the maps from there.  arch/ppc/platforms/katana.c has its mtd 
> maps there and I recently posted a patch that moves it for the chestnut 
> as well.
> 
> I think its a good idea to move them to the platform code since the mtd 
> maps are platform specific anyway.  Plus its one less place to add/edit 
> a file.  But that's just my $0.02...

But keep in mind that this currently only applies in the case where
you need to map chips of the same type. Some boards have multiple
chip types and physmap doesn't yet support that.

-Matt

^ permalink raw reply

* Re: [PATCH 3/3] PPC440EP IBM EMAC support
From: Matt Porter @ 2005-03-15 20:37 UTC (permalink / raw)
  To: Wade Farnsworth, linuxppc-embedded
In-Reply-To: <20050315192216.GB18588@gate.ebshome.net>

On Tue, Mar 15, 2005 at 11:22:16AM -0800, Eugene Surovegin wrote:
> On Tue, Mar 15, 2005 at 11:58:54AM -0700, Wade Farnsworth wrote:
> > This patch adds support to the IBM EMAC ethernet driver for the 440EP.
> > 
> > Regards,
> > Wade Farnsworth
> > 
> > Signed-off-by: Wade Farnsworth <wfarnsworth@mvista.com>
> > 
> 
> > --- linux-2.6.11-bk7/drivers/net/ibm_emac/ibm_emac_phy.c	2005-03-02 00:38:13.000000000 -0700
> > +++ linux-2.6.11-bk7-440ep/drivers/net/ibm_emac/ibm_emac_phy.c	2005-03-11 16:32:01.000000000 -0700
> > @@ -27,6 +27,12 @@
> >  
> >  #include "ibm_emac_phy.h"
> >  
> > +#ifdef CONFIG_BAMBOO
> > +#define BAMBOO_REV0 (mfspr(PVR) == PVR_440EP_RA)
> > +#else
> > +#define BAMBOO_REV0 0
> > +#endif
> > +
> 
> I really don't like it. Chip revision doesn't imply which board 
> this code is running on. Please, think of some other way to do this or 
> drop this completely.

Wade and I talked about this one before and there is no direct way
to detect the board revision on this platform. Given that, I
think that if the PVR of the 440EP in a Bamboo board does imply
the board revision, then this is appropriate.

-Matt

^ permalink raw reply

* Re: [PATCH 3/3] PPC440EP IBM EMAC support
From: Matt Porter @ 2005-03-15 20:43 UTC (permalink / raw)
  To: Wade Farnsworth, linuxppc-embedded
In-Reply-To: <20050315192424.GC18588@gate.ebshome.net>

On Tue, Mar 15, 2005 at 11:24:24AM -0800, Eugene Surovegin wrote:
> On Tue, Mar 15, 2005 at 11:22:16AM -0800, Eugene Surovegin wrote:
> > On Tue, Mar 15, 2005 at 11:58:54AM -0700, Wade Farnsworth wrote:
> > > This patch adds support to the IBM EMAC ethernet driver for the 440EP.
> > > 
> > > Regards,
> > > Wade Farnsworth
> > > 
> > > Signed-off-by: Wade Farnsworth <wfarnsworth@mvista.com>
> > > 
> > 
> > > --- linux-2.6.11-bk7/drivers/net/ibm_emac/ibm_emac_phy.c	2005-03-02 00:38:13.000000000 -0700
> > > +++ linux-2.6.11-bk7-440ep/drivers/net/ibm_emac/ibm_emac_phy.c	2005-03-11 16:32:01.000000000 -0700
> > > @@ -27,6 +27,12 @@
> > >  
> > >  #include "ibm_emac_phy.h"
> > >  
> > > +#ifdef CONFIG_BAMBOO
> > > +#define BAMBOO_REV0 (mfspr(PVR) == PVR_440EP_RA)
> > > +#else
> > > +#define BAMBOO_REV0 0
> > > +#endif
> > > +
> > 
> > I really don't like it. Chip revision doesn't imply which board 
> > this code is running on. Please, think of some other way to do this or 
> > drop this completely.
> > 
> 
> Or to phrase this differently, it's better to avoid any board specific 
> code/defines in network driver.

Indeed it's better. However, I made the suggestion that it's not
worth the effort to add in another hook to provide board specific
phy help to ibm_emac/ at this time.  I think the hack can exist
until a proper hook can be added to the phy lib stuff that should
be used in the future.

If you think that's too far off, we can go ahead and add another hook
so the hack can be moved into bamboo.c where it ideally belongs.

-Matt

^ permalink raw reply

* Re: 440EP FPU patch
From: Matt Porter @ 2005-03-15 20:50 UTC (permalink / raw)
  To: McMullan, Jason; +Cc: linuxppc-embedded
In-Reply-To: <1110915063.5937.93.camel@ad.doubleclick.net>

On Tue, Mar 15, 2005 at 02:27:57PM -0500, McMullan, Jason wrote:
> This patch (against vanilla 2.4.11.3) breaks out the FPU code for
> PowerPC into a common .S code for all the head*.S files.
> 
> Less cargo-culted code.
> 
> Wade, you may want to integrate this into your 440EP patch.

Hi Jason,

Can you change CONFIG_FPU->CONFIG_PPC_FPU? Otherwise, this looks
like exactly what we need to me.

-Matt

^ permalink raw reply

* Re: [PATCH 1/3] PPC440EP SoC and Bamboo board support
From: Jason McMullan @ 2005-03-15 20:58 UTC (permalink / raw)
  To: Wade Farnsworth; +Cc: linuxppc-embedded
In-Reply-To: <1110913681.24673.42.camel@rhino.az.mvista.com>

[-- Attachment #1: Type: text/plain, Size: 405 bytes --]

I think your setup for BAMBOO_PCIL0_PTM1MS is actually incorrect.
According to the AMCC 440EP docs, BAMBOO_PCIL0_PTM1MS is a mask,
so the correct code should look more like:

        memory_size = 0xffffffff - (memory_size - 1);
	PCI_WRITEL(memory_size | 1, BAMBOO_PCIL0_PTM1MS);

(assuming 'memory_size' is a power of 2)

-- 
Jason McMullan <jason.mcmullan@timesys.com>
TimeSys Corporation


[-- Attachment #2: This is a digitally signed message part --]
[-- Type: application/pgp-signature, Size: 189 bytes --]

^ permalink raw reply

* Re: 440EP FPU patch
From: Kumar Gala @ 2005-03-15 21:09 UTC (permalink / raw)
  To: McMullan, Jason; +Cc: linuxppc-embedded
In-Reply-To: <1110915063.5937.93.camel@ad.doubleclick.net>

Jason,

A few comments:

1. Change config option to CONFIG_PPC_FPU
2. split out altivec support into a separate file, most likely just 
move it into vector.S
3. Get ride of the C++ comments

- kumar

On Mar 15, 2005, at 1:27 PM, McMullan, Jason wrote:

> _______________________________________________
> Linuxppc-embedded mailing list
>  Linuxppc-embedded@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-embedded
>
> Date: March 15, 2005 1:43:37 PM CST
> Subject:
>
>
>
> Date: March 15, 2005 1:43:37 PM CST
> Subject:
>
>
> <ATT110571.txt><cpu-ppc-fpu.patch>
>
> <signature.asc>
>

^ permalink raw reply

* Re: [PATCH 1/3] PPC440EP SoC and Bamboo board support
From: Wade Farnsworth @ 2005-03-15 21:38 UTC (permalink / raw)
  To: Jason McMullan; +Cc: linuxppc-embedded
In-Reply-To: <1110920303.5937.103.camel@ad.doubleclick.net>

On Tue, 2005-03-15 at 13:58, Jason McMullan wrote:
> I think your setup for BAMBOO_PCIL0_PTM1MS is actually incorrect.
> According to the AMCC 440EP docs, BAMBOO_PCIL0_PTM1MS is a mask,
> so the correct code should look more like:
> 
>         memory_size = 0xffffffff - (memory_size - 1);
> 	PCI_WRITEL(memory_size | 1, BAMBOO_PCIL0_PTM1MS);
> 
> (assuming 'memory_size' is a power of 2)

Jason,

I think you're right.  Your way is much more concise too.

Thanks,
Wade Farnsworth

^ permalink raw reply

* Re: 440EP FPU patch
From: Jason McMullan @ 2005-03-15 22:18 UTC (permalink / raw)
  To: Kumar Gala; +Cc: linuxppc-embedded
In-Reply-To: <583185c11becaca3ce73e4010c18154d@freescale.com>


[-- Attachment #1.1: Type: text/plain, Size: 372 bytes --]

On Tue, 2005-03-15 at 15:09 -0600, Kumar Gala wrote:
> 1. Change config option to CONFIG_PPC_FPU
> 2. split out altivec support into a separate file, most likely just 
> move it into vector.S
> 3. Get ride of the C++ comments

Changes made, as per your suggestions, and new patch attached.

-- 
Jason McMullan <jason.mcmullan@timesys.com>
TimeSys Corporation


[-- Attachment #1.2: cpu-ppc-fpu.patch --]
[-- Type: text/x-patch, Size: 19842 bytes --]

#### Auto-generated patch ####
Date:        Tue, 15 Mar 2005 17:16:47 -0500
Maintainer:  Jason McMullan <jason.mcmullan@timesys.com>
Summary:     FPU support on PPC chips that don't use the normal head.S
Signed-Off-By: Jason McMullan <jason.mcmullan@timesys.com>
###############################

Index of changes:

 arch/ppc/Kconfig            |    6 
 arch/ppc/Makefile           |    1 
 arch/ppc/kernel/Makefile    |    1 
 arch/ppc/kernel/head.S      |  276 --------------------------------------------
 arch/ppc/kernel/head_44x.S  |   12 +
 arch/ppc/kernel/traps.c     |    2 
 arch/ppc/kernel/vector.S    |  116 ++++++++++++++++++
 include/asm-ppc/reg_booke.h |    1 
 linux/arch/ppc/kernel/fpu.S |  183 +++++++++++++++++++++++++++++
 9 files changed, 319 insertions(+), 279 deletions(-)


--- linux-orig/arch/ppc/Kconfig
+++ linux/arch/ppc/Kconfig
@@ -53,6 +53,7 @@
 
 config 6xx
 	bool "6xx/7xx/74xx/52xx/8260"
+	select PPC_FPU
 	help
 	  There are four types of PowerPC chips supported.  The more common
 	  types (601, 603, 604, 740, 750, 7400), the Motorola embedded
@@ -83,8 +84,11 @@
 
 config E500
 	bool "e500"
+	
+endchoice
 
-endchoice
+config PPC_FPU
+	bool
 
 config BOOKE
 	bool
--- linux-orig/arch/ppc/Makefile
+++ linux/arch/ppc/Makefile
@@ -53,6 +53,7 @@
 
 head-$(CONFIG_6xx)		+= arch/ppc/kernel/idle_6xx.o
 head-$(CONFIG_POWER4)		+= arch/ppc/kernel/idle_power4.o
+head-$(CONFIG_PPC_FPU)		+= arch/ppc/kernel/fpu.o
 
 core-y				+= arch/ppc/kernel/ arch/ppc/platforms/ \
 				   arch/ppc/mm/ arch/ppc/lib/ arch/ppc/syslib/
--- linux-orig/arch/ppc/kernel/Makefile
+++ linux/arch/ppc/kernel/Makefile
@@ -9,6 +9,7 @@
 extra-$(CONFIG_8xx)		:= head_8xx.o
 extra-$(CONFIG_6xx)		+= idle_6xx.o
 extra-$(CONFIG_POWER4)		+= idle_power4.o
+extra-$(CONFIG_PPC_FPU)		+= fpu.o
 extra-y				+= vmlinux.lds
 
 obj-y				:= entry.o traps.o irq.o idle.o time.o misc.o \
--- /dev/null
+++ linux/arch/ppc/kernel/fpu.S
@@ -0,0 +1,183 @@
+/* FPU support code, moved here from head.S so that it can be used
+ * by chips which use other head-whatever.S files.
+ */
+
+#include <linux/config.h>
+#include <asm/processor.h>
+#include <asm/page.h>
+#include <asm/mmu.h>
+#include <asm/pgtable.h>
+#include <asm/cputable.h>
+#include <asm/cache.h>
+#include <asm/thread_info.h>
+#include <asm/ppc_asm.h>
+#include <asm/offsets.h>
+
+/*
+ * This task wants to use the FPU now.
+ * On UP, disable FP for the task which had the FPU previously,
+ * and save its floating-point registers in its thread_struct.
+ * Load up this task's FP registers from its thread_struct,
+ * enable the FPU for the current task and return to the task.
+ */
+	.global load_up_fpu
+load_up_fpu:
+	mfmsr	r5
+	ori	r5,r5,MSR_FP
+#ifdef CONFIG_PPC64BRIDGE
+	clrldi	r5,r5,1			/* turn off 64-bit mode */
+#endif /* CONFIG_PPC64BRIDGE */
+	SYNC
+	MTMSRD(r5)			/* enable use of fpu now */
+	isync
+/*
+ * For SMP, we don't do lazy FPU switching because it just gets too
+ * horrendously complex, especially when a task switches from one CPU
+ * to another.  Instead we call giveup_fpu in switch_to.
+ */
+#ifndef CONFIG_SMP
+	tophys(r6,0)			/* get __pa constant */
+	addis	r3,r6,last_task_used_math@ha
+	lwz	r4,last_task_used_math@l(r3)
+	cmpwi	0,r4,0
+	beq	1f
+	add	r4,r4,r6
+	addi	r4,r4,THREAD		/* want last_task_used_math->thread */
+	SAVE_32FPRS(0, r4)
+	mffs	fr0
+	stfd	fr0,THREAD_FPSCR-4(r4)
+	lwz	r5,PT_REGS(r4)
+	add	r5,r5,r6
+	lwz	r4,_MSR-STACK_FRAME_OVERHEAD(r5)
+	li	r10,MSR_FP|MSR_FE0|MSR_FE1
+	andc	r4,r4,r10		/* disable FP for previous task */
+	stw	r4,_MSR-STACK_FRAME_OVERHEAD(r5)
+1:
+#endif /* CONFIG_SMP */
+	/* enable use of FP after return */
+	mfspr	r5,SPRG3		/* current task's THREAD (phys) */
+	lwz	r4,THREAD_FPEXC_MODE(r5)
+	ori	r9,r9,MSR_FP		/* enable FP for current */
+	or	r9,r9,r4
+	lfd	fr0,THREAD_FPSCR-4(r5)
+	mtfsf	0xff,fr0
+	REST_32FPRS(0, r5)
+#ifndef CONFIG_SMP
+	subi	r4,r5,THREAD
+	sub	r4,r4,r6
+	stw	r4,last_task_used_math@l(r3)
+#endif /* CONFIG_SMP */
+	/* restore registers and return */
+	/* we haven't used ctr or xer or lr */
+	/* fall through to fast_exception_return */
+
+	.global fast_exception_return
+fast_exception_return:
+#if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE))
+	andi.	r10,r9,MSR_RI		/* check for recoverable interrupt */
+	beq	1f			/* if not, we've got problems */
+#endif
+
+2:	REST_4GPRS(3, r11)
+	lwz	r10,_CCR(r11)
+	REST_GPR(1, r11)
+	mtcr	r10
+	lwz	r10,_LINK(r11)
+	mtlr	r10
+	REST_GPR(10, r11)
+	mtspr	SRR1,r9
+	mtspr	SRR0,r12
+	REST_GPR(9, r11)
+	REST_GPR(12, r11)
+	lwz	r11,GPR11(r11)
+	SYNC
+	RFI
+
+/* check if the exception happened in a restartable section */
+1:	lis	r3,exc_exit_restart_end@ha
+	addi	r3,r3,exc_exit_restart_end@l
+	cmplw	r12,r3
+	bge	3f
+	lis	r4,exc_exit_restart@ha
+	addi	r4,r4,exc_exit_restart@l
+	cmplw	r12,r4
+	blt	3f
+	lis	r3,fee_restarts@ha
+	tophys(r3,r3)
+	lwz	r5,fee_restarts@l(r3)
+	addi	r5,r5,1
+	stw	r5,fee_restarts@l(r3)
+	mr	r12,r4		/* restart at exc_exit_restart */
+	b	2b
+
+	.comm	fee_restarts,4
+
+/* aargh, a nonrecoverable interrupt, panic */
+/* aargh, we don't know which trap this is */
+/* but the 601 doesn't implement the RI bit, so assume it's OK */
+3:
+BEGIN_FTR_SECTION
+	b	2b
+END_FTR_SECTION_IFSET(CPU_FTR_601)
+	li	r10,-1
+	stw	r10,TRAP(r11)
+	addi	r3,r1,STACK_FRAME_OVERHEAD
+	lis	r10, MSR_KERNEL@h
+	ori	r10, r10, MSR_KERNEL@l
+	bl	transfer_to_handler_full
+	.long	nonrecoverable_exception
+	.long	ret_from_except
+
+/*
+ * FP unavailable trap from kernel - print a message, but let
+ * the task use FP in the kernel until it returns to user mode.
+ */
+ 	.global KernelFP
+KernelFP:
+	lwz	r3,_MSR(r1)
+	ori	r3,r3,MSR_FP
+	stw	r3,_MSR(r1)		/* enable use of FP after return */
+	lis	r3,86f@h
+	ori	r3,r3,86f@l
+	mr	r4,r2			/* current */
+	lwz	r5,_NIP(r1)
+	bl	printk
+	b	ret_from_except
+86:	.string	"floating point used in kernel (task=%p, pc=%x)\n"
+	.align	4,0
+
+/*
+ * giveup_fpu(tsk)
+ * Disable FP for the task given as the argument,
+ * and save the floating-point registers in its thread_struct.
+ * Enables the FPU for use in the kernel on return.
+ */
+	.global giveup_fpu
+giveup_fpu:
+	mfmsr	r5
+	ori	r5,r5,MSR_FP
+	SYNC_601
+	ISYNC_601
+	MTMSRD(r5)			/* enable use of fpu now */
+	SYNC_601
+	isync
+	cmpwi	0,r3,0
+	beqlr-				/* if no previous owner, done */
+	addi	r3,r3,THREAD	        /* want THREAD of task */
+	lwz	r5,PT_REGS(r3)
+	cmpwi	0,r5,0
+	SAVE_32FPRS(0, r3)
+	mffs	fr0
+	stfd	fr0,THREAD_FPSCR-4(r3)
+	beq	1f
+	lwz	r4,_MSR-STACK_FRAME_OVERHEAD(r5)
+	li	r3,MSR_FP|MSR_FE0|MSR_FE1
+	andc	r4,r4,r3		/* disable FP for previous task */
+	stw	r4,_MSR-STACK_FRAME_OVERHEAD(r5)
+1:
+#ifndef CONFIG_SMP
+	li	r5,0
+	lis	r4,last_task_used_math@ha
+	stw	r5,last_task_used_math@l(r4)
+#endif /* CONFIG_SMP */
+	blr

--- linux-orig/arch/ppc/kernel/head.S
+++ linux/arch/ppc/kernel/head.S
@@ -776,282 +776,6 @@
 #endif /* CONFIG_PPC64BRIDGE */
 
 /*
- * This task wants to use the FPU now.
- * On UP, disable FP for the task which had the FPU previously,
- * and save its floating-point registers in its thread_struct.
- * Load up this task's FP registers from its thread_struct,
- * enable the FPU for the current task and return to the task.
- */
-load_up_fpu:
-	mfmsr	r5
-	ori	r5,r5,MSR_FP
-#ifdef CONFIG_PPC64BRIDGE
-	clrldi	r5,r5,1			/* turn off 64-bit mode */
-#endif /* CONFIG_PPC64BRIDGE */
-	SYNC
-	MTMSRD(r5)			/* enable use of fpu now */
-	isync
-/*
- * For SMP, we don't do lazy FPU switching because it just gets too
- * horrendously complex, especially when a task switches from one CPU
- * to another.  Instead we call giveup_fpu in switch_to.
- */
-#ifndef CONFIG_SMP
-	tophys(r6,0)			/* get __pa constant */
-	addis	r3,r6,last_task_used_math@ha
-	lwz	r4,last_task_used_math@l(r3)
-	cmpwi	0,r4,0
-	beq	1f
-	add	r4,r4,r6
-	addi	r4,r4,THREAD		/* want last_task_used_math->thread */
-	SAVE_32FPRS(0, r4)
-	mffs	fr0
-	stfd	fr0,THREAD_FPSCR-4(r4)
-	lwz	r5,PT_REGS(r4)
-	add	r5,r5,r6
-	lwz	r4,_MSR-STACK_FRAME_OVERHEAD(r5)
-	li	r10,MSR_FP|MSR_FE0|MSR_FE1
-	andc	r4,r4,r10		/* disable FP for previous task */
-	stw	r4,_MSR-STACK_FRAME_OVERHEAD(r5)
-1:
-#endif /* CONFIG_SMP */
-	/* enable use of FP after return */
-	mfspr	r5,SPRG3		/* current task's THREAD (phys) */
-	lwz	r4,THREAD_FPEXC_MODE(r5)
-	ori	r9,r9,MSR_FP		/* enable FP for current */
-	or	r9,r9,r4
-	lfd	fr0,THREAD_FPSCR-4(r5)
-	mtfsf	0xff,fr0
-	REST_32FPRS(0, r5)
-#ifndef CONFIG_SMP
-	subi	r4,r5,THREAD
-	sub	r4,r4,r6
-	stw	r4,last_task_used_math@l(r3)
-#endif /* CONFIG_SMP */
-	/* restore registers and return */
-	/* we haven't used ctr or xer or lr */
-	/* fall through to fast_exception_return */
-
-	.globl	fast_exception_return
-fast_exception_return:
-	andi.	r10,r9,MSR_RI		/* check for recoverable interrupt */
-	beq	1f			/* if not, we've got problems */
-2:	REST_4GPRS(3, r11)
-	lwz	r10,_CCR(r11)
-	REST_GPR(1, r11)
-	mtcr	r10
-	lwz	r10,_LINK(r11)
-	mtlr	r10
-	REST_GPR(10, r11)
-	mtspr	SRR1,r9
-	mtspr	SRR0,r12
-	REST_GPR(9, r11)
-	REST_GPR(12, r11)
-	lwz	r11,GPR11(r11)
-	SYNC
-	RFI
-
-/* check if the exception happened in a restartable section */
-1:	lis	r3,exc_exit_restart_end@ha
-	addi	r3,r3,exc_exit_restart_end@l
-	cmplw	r12,r3
-	bge	3f
-	lis	r4,exc_exit_restart@ha
-	addi	r4,r4,exc_exit_restart@l
-	cmplw	r12,r4
-	blt	3f
-	lis	r3,fee_restarts@ha
-	tophys(r3,r3)
-	lwz	r5,fee_restarts@l(r3)
-	addi	r5,r5,1
-	stw	r5,fee_restarts@l(r3)
-	mr	r12,r4		/* restart at exc_exit_restart */
-	b	2b
-
-	.comm	fee_restarts,4
-
-/* aargh, a nonrecoverable interrupt, panic */
-/* aargh, we don't know which trap this is */
-/* but the 601 doesn't implement the RI bit, so assume it's OK */
-3:
-BEGIN_FTR_SECTION
-	b	2b
-END_FTR_SECTION_IFSET(CPU_FTR_601)
-	li	r10,-1
-	stw	r10,TRAP(r11)
-	addi	r3,r1,STACK_FRAME_OVERHEAD
-	li	r10,MSR_KERNEL
-	bl	transfer_to_handler_full
-	.long	nonrecoverable_exception
-	.long	ret_from_except
-
-/*
- * FP unavailable trap from kernel - print a message, but let
- * the task use FP in the kernel until it returns to user mode.
- */
-KernelFP:
-	lwz	r3,_MSR(r1)
-	ori	r3,r3,MSR_FP
-	stw	r3,_MSR(r1)		/* enable use of FP after return */
-	lis	r3,86f@h
-	ori	r3,r3,86f@l
-	mr	r4,r2			/* current */
-	lwz	r5,_NIP(r1)
-	bl	printk
-	b	ret_from_except
-86:	.string	"floating point used in kernel (task=%p, pc=%x)\n"
-	.align	4,0
-
-#ifdef CONFIG_ALTIVEC
-/* Note that the AltiVec support is closely modeled after the FP
- * support.  Changes to one are likely to be applicable to the
- * other!  */
-load_up_altivec:
-/*
- * Disable AltiVec for the task which had AltiVec previously,
- * and save its AltiVec registers in its thread_struct.
- * Enables AltiVec for use in the kernel on return.
- * On SMP we know the AltiVec units are free, since we give it up every
- * switch.  -- Kumar
- */
-	mfmsr	r5
-	oris	r5,r5,MSR_VEC@h
-	MTMSRD(r5)			/* enable use of AltiVec now */
-	isync
-/*
- * For SMP, we don't do lazy AltiVec switching because it just gets too
- * horrendously complex, especially when a task switches from one CPU
- * to another.  Instead we call giveup_altivec in switch_to.
- */
-#ifndef CONFIG_SMP
-	tophys(r6,0)
-	addis	r3,r6,last_task_used_altivec@ha
-	lwz	r4,last_task_used_altivec@l(r3)
-	cmpwi	0,r4,0
-	beq	1f
-	add	r4,r4,r6
-	addi	r4,r4,THREAD	/* want THREAD of last_task_used_altivec */
-	SAVE_32VR(0,r10,r4)
-	mfvscr	vr0
-	li	r10,THREAD_VSCR
-	stvx	vr0,r10,r4
-	lwz	r5,PT_REGS(r4)
-	add	r5,r5,r6
-	lwz	r4,_MSR-STACK_FRAME_OVERHEAD(r5)
-	lis	r10,MSR_VEC@h
-	andc	r4,r4,r10	/* disable altivec for previous task */
-	stw	r4,_MSR-STACK_FRAME_OVERHEAD(r5)
-1:
-#endif /* CONFIG_SMP */
-	/* enable use of AltiVec after return */
-	oris	r9,r9,MSR_VEC@h
-	mfspr	r5,SPRG3		/* current task's THREAD (phys) */
-	li	r4,1
-	li	r10,THREAD_VSCR
-	stw	r4,THREAD_USED_VR(r5)
-	lvx	vr0,r10,r5
-	mtvscr	vr0
-	REST_32VR(0,r10,r5)
-#ifndef CONFIG_SMP
-	subi	r4,r5,THREAD
-	sub	r4,r4,r6
-	stw	r4,last_task_used_altivec@l(r3)
-#endif /* CONFIG_SMP */
-	/* restore registers and return */
-	/* we haven't used ctr or xer or lr */
-	b	fast_exception_return
-
-/*
- * AltiVec unavailable trap from kernel - print a message, but let
- * the task use AltiVec in the kernel until it returns to user mode.
- */
-KernelAltiVec:
-	lwz	r3,_MSR(r1)
-	oris	r3,r3,MSR_VEC@h
-	stw	r3,_MSR(r1)	/* enable use of AltiVec after return */
-	lis	r3,87f@h
-	ori	r3,r3,87f@l
-	mr	r4,r2		/* current */
-	lwz	r5,_NIP(r1)
-	bl	printk
-	b	ret_from_except
-87:	.string	"AltiVec used in kernel  (task=%p, pc=%x)  \n"
-	.align	4,0
-
-/*
- * giveup_altivec(tsk)
- * Disable AltiVec for the task given as the argument,
- * and save the AltiVec registers in its thread_struct.
- * Enables AltiVec for use in the kernel on return.
- */
-
-	.globl	giveup_altivec
-giveup_altivec:
-	mfmsr	r5
-	oris	r5,r5,MSR_VEC@h
-	SYNC
-	MTMSRD(r5)			/* enable use of AltiVec now */
-	isync
-	cmpwi	0,r3,0
-	beqlr-				/* if no previous owner, done */
-	addi	r3,r3,THREAD		/* want THREAD of task */
-	lwz	r5,PT_REGS(r3)
-	cmpwi	0,r5,0
-	SAVE_32VR(0, r4, r3)
-	mfvscr	vr0
-	li	r4,THREAD_VSCR
-	stvx	vr0,r4,r3
-	beq	1f
-	lwz	r4,_MSR-STACK_FRAME_OVERHEAD(r5)
-	lis	r3,MSR_VEC@h
-	andc	r4,r4,r3		/* disable AltiVec for previous task */
-	stw	r4,_MSR-STACK_FRAME_OVERHEAD(r5)
-1:
-#ifndef CONFIG_SMP
-	li	r5,0
-	lis	r4,last_task_used_altivec@ha
-	stw	r5,last_task_used_altivec@l(r4)
-#endif /* CONFIG_SMP */
-	blr
-#endif /* CONFIG_ALTIVEC */
-
-/*
- * giveup_fpu(tsk)
- * Disable FP for the task given as the argument,
- * and save the floating-point registers in its thread_struct.
- * Enables the FPU for use in the kernel on return.
- */
-	.globl	giveup_fpu
-giveup_fpu:
-	mfmsr	r5
-	ori	r5,r5,MSR_FP
-	SYNC_601
-	ISYNC_601
-	MTMSRD(r5)			/* enable use of fpu now */
-	SYNC_601
-	isync
-	cmpwi	0,r3,0
-	beqlr-				/* if no previous owner, done */
-	addi	r3,r3,THREAD	        /* want THREAD of task */
-	lwz	r5,PT_REGS(r3)
-	cmpwi	0,r5,0
-	SAVE_32FPRS(0, r3)
-	mffs	fr0
-	stfd	fr0,THREAD_FPSCR-4(r3)
-	beq	1f
-	lwz	r4,_MSR-STACK_FRAME_OVERHEAD(r5)
-	li	r3,MSR_FP|MSR_FE0|MSR_FE1
-	andc	r4,r4,r3		/* disable FP for previous task */
-	stw	r4,_MSR-STACK_FRAME_OVERHEAD(r5)
-1:
-#ifndef CONFIG_SMP
-	li	r5,0
-	lis	r4,last_task_used_math@ha
-	stw	r5,last_task_used_math@l(r4)
-#endif /* CONFIG_SMP */
-	blr
-
-/*
  * This code is jumped to from the startup code to copy
  * the kernel image to physical address 0.
  */
--- linux-orig/arch/ppc/kernel/head_44x.S
+++ linux/arch/ppc/kernel/head_44x.S
@@ -426,7 +426,15 @@
 	PROGRAM_EXCEPTION
 
 	/* Floating Point Unavailable Interrupt */
+#ifdef CONFIG_PPC_FPU
+	START_EXCEPTION(FloatingPointUnavailable)
+	NORMAL_EXCEPTION_PROLOG
+	bne	load_up_fpu		/* if from user, just load it up */
+	addi	r3,r1,STACK_FRAME_OVERHEAD
+	EXC_XFER_EE_LITE(0x800, KernelFP)
+#else
 	EXCEPTION(0x2010, FloatingPointUnavailable, UnknownException, EXC_XFER_EE)
+#endif
 
 	/* System Call Interrupt */
 	START_EXCEPTION(SystemCall)
@@ -686,9 +694,11 @@
  *
  * The 44x core does not have an FPU.
  */
+#ifndef CONFIG_PPC_FPU
 _GLOBAL(giveup_fpu)
 	blr
-
+#endif
+ 
 /*
  * extern void abort(void)
  *
--- linux-orig/arch/ppc/kernel/traps.c
+++ linux/arch/ppc/kernel/traps.c
@@ -176,7 +176,7 @@
 #else
 #define get_mc_reason(regs)	(mfspr(SPRN_MCSR))
 #endif
-#define REASON_FP		0
+#define REASON_FP		ESR_FP
 #define REASON_ILLEGAL		ESR_PIL
 #define REASON_PRIVILEGED	ESR_PPR
 #define REASON_TRAP		ESR_PTR
--- linux-orig/arch/ppc/kernel/vector.S
+++ linux/arch/ppc/kernel/vector.S
@@ -1,3 +1,6 @@
+/* Altivec support code.
+ */
+
 #include <asm/ppc_asm.h>
 #include <asm/processor.h>
 
@@ -215,3 +218,116 @@
 	mtlr	r0
 	addi	r1,r1,32
 	blr
+
+/* Note that the AltiVec support is closely modeled after the FP
+ * support.  Changes to one are likely to be applicable to the
+ * other!  */
+ 	.global load_up_altivec
+load_up_altivec:
+/*
+ * Disable AltiVec for the task which had AltiVec previously,
+ * and save its AltiVec registers in its thread_struct.
+ * Enables AltiVec for use in the kernel on return.
+ * On SMP we know the AltiVec units are free, since we give it up every
+ * switch.  -- Kumar
+ */
+	mfmsr	r5
+	oris	r5,r5,MSR_VEC@h
+	MTMSRD(r5)			/* enable use of AltiVec now */
+	isync
+/*
+ * For SMP, we don't do lazy AltiVec switching because it just gets too
+ * horrendously complex, especially when a task switches from one CPU
+ * to another.  Instead we call giveup_altivec in switch_to.
+ */
+#ifndef CONFIG_SMP
+	tophys(r6,0)
+	addis	r3,r6,last_task_used_altivec@ha
+	lwz	r4,last_task_used_altivec@l(r3)
+	cmpwi	0,r4,0
+	beq	1f
+	add	r4,r4,r6
+	addi	r4,r4,THREAD	/* want THREAD of last_task_used_altivec */
+	SAVE_32VR(0,r10,r4)
+	mfvscr	vr0
+	li	r10,THREAD_VSCR
+	stvx	vr0,r10,r4
+	lwz	r5,PT_REGS(r4)
+	add	r5,r5,r6
+	lwz	r4,_MSR-STACK_FRAME_OVERHEAD(r5)
+	lis	r10,MSR_VEC@h
+	andc	r4,r4,r10	/* disable altivec for previous task */
+	stw	r4,_MSR-STACK_FRAME_OVERHEAD(r5)
+1:
+#endif /* CONFIG_SMP */
+	/* enable use of AltiVec after return */
+	oris	r9,r9,MSR_VEC@h
+	mfspr	r5,SPRG3		/* current task's THREAD (phys) */
+	li	r4,1
+	li	r10,THREAD_VSCR
+	stw	r4,THREAD_USED_VR(r5)
+	lvx	vr0,r10,r5
+	mtvscr	vr0
+	REST_32VR(0,r10,r5)
+#ifndef CONFIG_SMP
+	subi	r4,r5,THREAD
+	sub	r4,r4,r6
+	stw	r4,last_task_used_altivec@l(r3)
+#endif /* CONFIG_SMP */
+	/* restore registers and return */
+	/* we haven't used ctr or xer or lr */
+	b	fast_exception_return
+
+/*
+ * AltiVec unavailable trap from kernel - print a message, but let
+ * the task use AltiVec in the kernel until it returns to user mode.
+ */
+ 	.global KernelAltiVec
+KernelAltiVec:
+	lwz	r3,_MSR(r1)
+	oris	r3,r3,MSR_VEC@h
+	stw	r3,_MSR(r1)	/* enable use of AltiVec after return */
+	lis	r3,87f@h
+	ori	r3,r3,87f@l
+	mr	r4,r2		/* current */
+	lwz	r5,_NIP(r1)
+	bl	printk
+	b	ret_from_except
+87:	.string	"AltiVec used in kernel  (task=%p, pc=%x)  \n"
+	.align	4,0
+
+/*
+ * giveup_altivec(tsk)
+ * Disable AltiVec for the task given as the argument,
+ * and save the AltiVec registers in its thread_struct.
+ * Enables AltiVec for use in the kernel on return.
+ */
+
+	.global giveup_altivec
+giveup_altivec:
+	mfmsr	r5
+	oris	r5,r5,MSR_VEC@h
+	SYNC
+	MTMSRD(r5)			/* enable use of AltiVec now */
+	isync
+	cmpwi	0,r3,0
+	beqlr-				/* if no previous owner, done */
+	addi	r3,r3,THREAD		/* want THREAD of task */
+	lwz	r5,PT_REGS(r3)
+	cmpwi	0,r5,0
+	SAVE_32VR(0, r4, r3)
+	mfvscr	vr0
+	li	r4,THREAD_VSCR
+	stvx	vr0,r4,r3
+	beq	1f
+	lwz	r4,_MSR-STACK_FRAME_OVERHEAD(r5)
+	lis	r3,MSR_VEC@h
+	andc	r4,r4,r3		/* disable AltiVec for previous task */
+	stw	r4,_MSR-STACK_FRAME_OVERHEAD(r5)
+1:
+#ifndef CONFIG_SMP
+	li	r5,0
+	lis	r4,last_task_used_altivec@ha
+	stw	r5,last_task_used_altivec@l(r4)
+#endif /* CONFIG_SMP */
+	blr
--- linux-orig/include/asm-ppc/reg_booke.h
+++ linux/include/asm-ppc/reg_booke.h
@@ -305,6 +305,7 @@
 #define ESR_PIL		0x08000000	/* Program Exception - Illegal */
 #define ESR_PPR		0x04000000	/* Program Exception - Priveleged */
 #define ESR_PTR		0x02000000	/* Program Exception - Trap */
+#define ESR_FP          0x01000000      /* Floating Point Operation */
 #define ESR_DST		0x00800000	/* Storage Exception - Data miss */
 #define ESR_DIZ		0x00400000	/* Storage Exception - Zone fault */
 #define ESR_ST		0x00800000	/* Store Operation */

[-- Attachment #2: This is a digitally signed message part --]
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^ permalink raw reply

* [PATCH 2.6.12] ppc32: Patch for changed dev->bus_id format
From: Mark A. Greer @ 2005-03-15 22:26 UTC (permalink / raw)
  To: akpm; +Cc: Embedded PPC Linux list

[-- Attachment #1: Type: text/plain, Size: 556 bytes --]

ppc32: Patch for changed dev->bus_id format + some misc fixups

- Recent changes to drivers/base/platform.c:platform_device_register() 
changed the format
of dev->bus_id (there is now a '.' between the name & instance (e.g., 
the old mpsc0 is now mpsc.0)).  This field is used by some platform's 
platform_notify() routine to identify  the dev entry.  This patch 
updates the bus_id value compared to include the dot.
- Fix an bad macro name change by a previous patch.
- Some coding style fixups, etc.

Signed-off-by: Mark A. Greer <mgreer@mvista.com>
--

[-- Attachment #2: bus_id_fixups.patch --]
[-- Type: text/plain, Size: 5213 bytes --]

diff -Nru a/arch/ppc/platforms/cpci690.c b/arch/ppc/platforms/cpci690.c
--- a/arch/ppc/platforms/cpci690.c	2005-03-15 15:15:30 -07:00
+++ b/arch/ppc/platforms/cpci690.c	2005-03-15 15:15:30 -07:00
@@ -60,8 +60,7 @@
 
 		const long min_idsel = 20, max_idsel = 20, irqs_per_slot = 4;
 		return PCI_IRQ_TABLE_LOOKUP;
-	}
-	else {
+	} else {
 		static char pci_irq_table[][4] =
 		/*
 		 *	PCI IDSEL/INTPIN->INTLINE
@@ -79,18 +78,12 @@
 }
 
 static int
-cpci690_get_bus_speed(void)
-{
-	return 133333333;
-}
-
-static int
 cpci690_get_cpu_speed(void)
 {
 	unsigned long	hid1;
 
 	hid1 = mfspr(SPRN_HID1) >> 28;
-	return cpci690_get_bus_speed() * cpu_7xx[hid1]/2;
+	return CPCI690_BUS_FREQ * cpu_7xx[hid1]/2;
 }
 
 #define	KB	(1024UL)
@@ -226,8 +219,6 @@
 	bh.hose_b->last_busno = 0xff;
 	bh.hose_b->last_busno = pciauto_bus_scan(bh.hose_b,
 		bh.hose_b->first_busno);
-
-	return;
 }
 
 static void __init
@@ -285,8 +276,6 @@
 	/* Route MPP interrupt inputs to GPP */
 	mv64x60_write(&bh, MV64x60_MPP_CNTL_2, 0x00000000);
 	mv64x60_write(&bh, MV64x60_MPP_CNTL_3, 0x00000000);
-
-	return;
 }
 
 static void __init
@@ -326,8 +315,6 @@
 
 	if (ppc_md.progress)
 		ppc_md.progress("cpci690_setup_arch: exit", 0);
-
-	return;
 }
 
 /* Platform device data fixup routines. */
@@ -340,11 +327,9 @@
 	pdata = (struct mpsc_pdata *)pdev->dev.platform_data;
 
 	pdata->max_idle = 40;
-	pdata->default_baud = 9600;
-	pdata->brg_clk_src = 8;
-	pdata->brg_clk_freq = 133000000;
-
-	return;
+	pdata->default_baud = CPCI690_MPSC_BAUD;
+	pdata->brg_clk_src = CPCI690_MPSC_CLK_SRC;
+	pdata->brg_clk_freq = CPCI690_BUS_FREQ;
 }
 
 static int __init
@@ -354,8 +339,8 @@
 		char	*bus_id;
 		void	((*rtn)(struct platform_device *pdev));
 	} dev_map[] = {
-		{ MPSC_CTLR_NAME "0", cpci690_fixup_mpsc_pdata },
-		{ MPSC_CTLR_NAME "1", cpci690_fixup_mpsc_pdata },
+		{ MPSC_CTLR_NAME ".0", cpci690_fixup_mpsc_pdata },
+		{ MPSC_CTLR_NAME ".1", cpci690_fixup_mpsc_pdata },
 	};
 	struct platform_device	*pdev;
 	int	i;
@@ -412,7 +397,7 @@
 	seq_printf(m, "vendor\t\t: " BOARD_VENDOR "\n");
 	seq_printf(m, "machine\t\t: " BOARD_MACHINE "\n");
 	seq_printf(m, "cpu MHz\t\t: %d\n", cpci690_get_cpu_speed()/1000/1000);
-	seq_printf(m, "bus MHz\t\t: %d\n", cpci690_get_bus_speed()/1000/1000);
+	seq_printf(m, "bus MHz\t\t: %d\n", CPCI690_BUS_FREQ/1000/1000);
 
 	return 0;
 }
@@ -422,15 +407,13 @@
 {
 	ulong freq;
 
-	freq = cpci690_get_bus_speed()/4;
+	freq = CPCI690_BUS_FREQ / 4;
 
 	printk(KERN_INFO "time_init: decrementer frequency = %lu.%.6lu MHz\n",
 	       freq/1000000, freq%1000000);
 
 	tb_ticks_per_jiffy = freq / HZ;
 	tb_to_us = mulhwu_scale_factor(freq, 1000000);
-
-	return;
 }
 
 static __inline__ void
@@ -444,8 +427,6 @@
 	mtspr(SPRN_DBAT1U, addr | size | 0x2); /* Vs == 1; Vp == 0 */
 	mtspr(SPRN_DBAT1L, addr | 0x2a); /* WIMG bits == 0101; PP == r/w access */
 	mb();
-
-	return;
 }
 
 #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
@@ -507,6 +488,4 @@
 #if defined(CONFIG_SERIAL_MPSC)
 	platform_notify = cpci690_platform_notify;
 #endif
-
-	return;
 }
diff -Nru a/arch/ppc/platforms/cpci690.h b/arch/ppc/platforms/cpci690.h
--- a/arch/ppc/platforms/cpci690.h	2005-03-15 15:15:30 -07:00
+++ b/arch/ppc/platforms/cpci690.h	2005-03-15 15:15:30 -07:00
@@ -70,4 +70,9 @@
 #define	CPCI690_IPMI_SIZE		max(GT64260_WINDOW_SIZE_MIN,	\
 						CPCI690_IPMI_SIZE_ACTUAL)
 
+#define	CPCI690_MPSC_BAUD			9600
+#define	CPCI690_MPSC_CLK_SRC			8 /* TCLK */
+
+#define	CPCI690_BUS_FREQ			133333333
+
 #endif /* __PPC_PLATFORMS_CPCI690_H */
diff -Nru a/arch/ppc/platforms/ev64260.c b/arch/ppc/platforms/ev64260.c
--- a/arch/ppc/platforms/ev64260.c	2005-03-15 15:15:30 -07:00
+++ b/arch/ppc/platforms/ev64260.c	2005-03-15 15:15:30 -07:00
@@ -80,7 +80,7 @@
 {
 	unsigned long	pvr, hid1, pll_ext;
 
-	pvr = SPRN_VER(mfspr(SPRN_PVR));
+	pvr = PVR_VER(mfspr(SPRN_PVR));
 
 	if (pvr != PVR_VER(PVR_7450)) {
 		hid1 = mfspr(SPRN_HID1) >> 28;
@@ -422,8 +422,8 @@
 		char	*bus_id;
 		void	((*rtn)(struct platform_device *pdev));
 	} dev_map[] = {
-		{ MPSC_CTLR_NAME "0", ev64260_fixup_mpsc_pdata },
-		{ MPSC_CTLR_NAME "1", ev64260_fixup_mpsc_pdata },
+		{ MPSC_CTLR_NAME ".0", ev64260_fixup_mpsc_pdata },
+		{ MPSC_CTLR_NAME ".1", ev64260_fixup_mpsc_pdata },
 	};
 	struct platform_device	*pdev;
 	int	i;
diff -Nru a/arch/ppc/platforms/katana.c b/arch/ppc/platforms/katana.c
--- a/arch/ppc/platforms/katana.c	2005-03-15 15:15:30 -07:00
+++ b/arch/ppc/platforms/katana.c	2005-03-15 15:15:30 -07:00
@@ -521,13 +521,13 @@
 		void	((*rtn)(struct platform_device *pdev));
 	} dev_map[] = {
 #if defined(CONFIG_SERIAL_MPSC)
-		{ MPSC_CTLR_NAME "0", katana_fixup_mpsc_pdata },
-		{ MPSC_CTLR_NAME "1", katana_fixup_mpsc_pdata },
+		{ MPSC_CTLR_NAME ".0", katana_fixup_mpsc_pdata },
+		{ MPSC_CTLR_NAME ".1", katana_fixup_mpsc_pdata },
 #endif
 #if defined(CONFIG_MV643XX_ETH)
-		{ MV643XX_ETH_NAME "0", katana_fixup_eth_pdata },
-		{ MV643XX_ETH_NAME "1", katana_fixup_eth_pdata },
-		{ MV643XX_ETH_NAME "2", katana_fixup_eth_pdata },
+		{ MV643XX_ETH_NAME ".0", katana_fixup_eth_pdata },
+		{ MV643XX_ETH_NAME ".1", katana_fixup_eth_pdata },
+		{ MV643XX_ETH_NAME ".2", katana_fixup_eth_pdata },
 #endif
 	};
 	struct platform_device	*pdev;

^ permalink raw reply

* [PATCH 2.6.11] ppc32: update Radstone ppc7d platform
From: Mark A. Greer @ 2005-03-15 23:05 UTC (permalink / raw)
  To: akpm; +Cc: Embedded PPC Linux list

[-- Attachment #1: Type: text/plain, Size: 407 bytes --]

ppc32: Radstone PPC7D platform update

- Recent mv643xx #define name changes broke the PPC7D platform
compile. Fixed by this patch.

- Change default platform config to add mv643xx_eth and mv64xxx-i2c
config options.

- Add i2c platform data and update to cope with recent platform device
name change.

Signed-off-by: James Chapman <jchapman@katalix.com>
Signed-off-by: Mark A. Greer <mgreer@mvista.com>
--

[-- Attachment #2: ppc7d-2.patch --]
[-- Type: text/plain, Size: 10252 bytes --]

Index: linux-2.6/arch/ppc/platforms/radstone_ppc7d.c
===================================================================
--- linux-2.6.orig/arch/ppc/platforms/radstone_ppc7d.c	2005-03-15 14:44:43.000000000 +0000
+++ linux-2.6/arch/ppc/platforms/radstone_ppc7d.c	2005-03-15 22:17:56.000000000 +0000
@@ -669,6 +669,42 @@
 }
 #endif
 
+#if defined(CONFIG_I2C_MV64XXX)
+static void __init
+ppc7d_fixup_i2c_pdata(struct platform_device *pdev)
+{
+	struct mv64xxx_i2c_pdata *pdata;
+	int i;
+
+	pdata = pdev->dev.platform_data;
+	if (pdata == NULL) {
+		pdata = kmalloc(GFP_KERNEL, sizeof(*pdata));
+		if (pdata == NULL)
+			return;
+
+		memset(pdata, 0, sizeof(*pdata));
+		pdev->dev.platform_data = pdata;
+	}
+
+	/* divisors M=8, N=3 for 100kHz I2C from 133MHz system clock */
+	pdata->freq_m = 8;
+	pdata->freq_n = 3;
+	pdata->timeout = 500;
+	pdata->retries = 3;
+
+	/* Adjust IRQ by mv64360_irq_base */
+	for (i = 0; i < pdev->num_resources; i++) {
+		struct resource *r = &pdev->resource[i];
+
+		if (r->flags & IORESOURCE_IRQ) {
+			r->start += mv64360_irq_base;
+			r->end += mv64360_irq_base;
+			pr_debug("%s, uses IRQ %d\n", pdev->name, (int) r->start);
+		}
+	}
+}
+#endif
+
 static int __init ppc7d_platform_notify(struct device *dev)
 {
 	static struct {
@@ -676,13 +712,16 @@
 		void ((*rtn) (struct platform_device * pdev));
 	} dev_map[] = {
 #if defined(CONFIG_SERIAL_MPSC)
-		{ MPSC_CTLR_NAME "0", ppc7d_fixup_mpsc_pdata },
-		{ MPSC_CTLR_NAME "1", ppc7d_fixup_mpsc_pdata },
+		{ MPSC_CTLR_NAME ".0", ppc7d_fixup_mpsc_pdata },
+		{ MPSC_CTLR_NAME ".1", ppc7d_fixup_mpsc_pdata },
 #endif
 #if defined(CONFIG_MV643XX_ETH)
-		{ MV643XX_ETH_NAME "0", ppc7d_fixup_eth_pdata },
-		{ MV643XX_ETH_NAME "1", ppc7d_fixup_eth_pdata },
-		{ MV643XX_ETH_NAME "2", ppc7d_fixup_eth_pdata },
+		{ MV643XX_ETH_NAME ".0", ppc7d_fixup_eth_pdata },
+		{ MV643XX_ETH_NAME ".1", ppc7d_fixup_eth_pdata },
+		{ MV643XX_ETH_NAME ".2", ppc7d_fixup_eth_pdata },
+#endif
+#if defined(CONFIG_I2C_MV64XXX)
+		{ MV64XXX_I2C_CTLR_NAME ".0", ppc7d_fixup_i2c_pdata },
 #endif
 	};
 	struct platform_device *pdev;
@@ -1162,7 +1201,7 @@
 
 	/* Disable ethernet. It might have been setup by the bootrom */
 	for (port = 0; port < 3; port++)
-		mv64x60_write(&bh, MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(port),
+		mv64x60_write(&bh, MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port),
 			      0x0000ff00);
 
 	/* Clear queue pointers to ensure they are all initialized,
@@ -1172,25 +1211,25 @@
 	 */
 	for (port = 0; port < 3; port++) {
 		mv64x60_write(&bh,
-			      MV64340_ETH_RX_CURRENT_QUEUE_DESC_PTR_1(port),
+			      MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_1(port),
 			      0x00000000);
 		mv64x60_write(&bh,
-			      MV64340_ETH_RX_CURRENT_QUEUE_DESC_PTR_2(port),
+			      MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_2(port),
 			      0x00000000);
 		mv64x60_write(&bh,
-			      MV64340_ETH_RX_CURRENT_QUEUE_DESC_PTR_3(port),
+			      MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_3(port),
 			      0x00000000);
 		mv64x60_write(&bh,
-			      MV64340_ETH_RX_CURRENT_QUEUE_DESC_PTR_4(port),
+			      MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_4(port),
 			      0x00000000);
 		mv64x60_write(&bh,
-			      MV64340_ETH_RX_CURRENT_QUEUE_DESC_PTR_5(port),
+			      MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_5(port),
 			      0x00000000);
 		mv64x60_write(&bh,
-			      MV64340_ETH_RX_CURRENT_QUEUE_DESC_PTR_6(port),
+			      MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_6(port),
 			      0x00000000);
 		mv64x60_write(&bh,
-			      MV64340_ETH_RX_CURRENT_QUEUE_DESC_PTR_7(port),
+			      MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_7(port),
 			      0x00000000);
 	}
 
@@ -1363,7 +1402,8 @@
 
 	ppc_md.pcibios_fixup_bus = ppc7d_pci_fixup_bus;
 
-#if defined(CONFIG_SERIAL_MPSC) || defined(CONFIG_MV643XX_ETH)
+#if defined(CONFIG_SERIAL_MPSC) || defined(CONFIG_MV643XX_ETH) || \
+    defined(CONFIG_I2C_MV64XXX)
 	platform_notify = ppc7d_platform_notify;
 #endif
 
@@ -1405,4 +1445,8 @@
 	rev_num = (val8 & PPC7D_CPLD_BOARD_REVISION_NUMBER_MASK) >> 5;
 	if (rev_num <= 1)
 		ppc7d_has_alma = 1;
+
+#ifdef DEBUG
+	console_printk[0] = 8;
+#endif
 }
Index: linux-2.6/arch/ppc/configs/radstone_ppc7d_defconfig
===================================================================
--- linux-2.6.orig/arch/ppc/configs/radstone_ppc7d_defconfig	2005-03-15 14:44:43.000000000 +0000
+++ linux-2.6/arch/ppc/configs/radstone_ppc7d_defconfig	2005-03-15 22:17:56.000000000 +0000
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.11-rc4
-# Thu Feb 24 21:26:04 2005
+# Linux kernel version: 2.6.11
+# Tue Mar 15 14:31:19 2005
 #
 CONFIG_MMU=y
 CONFIG_GENERIC_HARDIRQS=y
@@ -29,13 +29,13 @@
 # CONFIG_BSD_PROCESS_ACCT is not set
 CONFIG_SYSCTL=y
 # CONFIG_AUDIT is not set
-CONFIG_LOG_BUF_SHIFT=14
 # CONFIG_HOTPLUG is not set
 CONFIG_KOBJECT_UEVENT=y
 # CONFIG_IKCONFIG is not set
 CONFIG_EMBEDDED=y
 CONFIG_KALLSYMS=y
 CONFIG_KALLSYMS_EXTRA_PASS=y
+CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
 CONFIG_EPOLL=y
 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
@@ -45,6 +45,7 @@
 CONFIG_CC_ALIGN_LOOPS=0
 CONFIG_CC_ALIGN_JUMPS=0
 # CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
 
 #
 # Loadable module support
@@ -71,6 +72,7 @@
 # CONFIG_TAU is not set
 # CONFIG_CPU_FREQ is not set
 CONFIG_PPC_GEN550=y
+# CONFIG_PM is not set
 CONFIG_PPC_STD_MMU=y
 # CONFIG_NOT_COHERENT_CACHE is not set
 
@@ -107,6 +109,7 @@
 # CONFIG_ADS8272 is not set
 # CONFIG_PQ2FADS is not set
 # CONFIG_LITE5200 is not set
+# CONFIG_MPC834x_SYS is not set
 CONFIG_MV64360=y
 CONFIG_MV64X60=y
 
@@ -138,10 +141,6 @@
 # CONFIG_PCCARD is not set
 
 #
-# PC-card bridges
-#
-
-#
 # Advanced setup
 #
 CONFIG_ADVANCED_OPTIONS=y
@@ -171,8 +170,8 @@
 #
 CONFIG_MTD=y
 # CONFIG_MTD_DEBUG is not set
-# CONFIG_MTD_PARTITIONS is not set
 # CONFIG_MTD_CONCAT is not set
+# CONFIG_MTD_PARTITIONS is not set
 
 #
 # User Modules And Translation Layers
@@ -490,7 +489,6 @@
 # CONFIG_DGRS is not set
 # CONFIG_EEPRO100 is not set
 CONFIG_E100=y
-# CONFIG_E100_NAPI is not set
 # CONFIG_FEALNX is not set
 # CONFIG_NATSEMI is not set
 # CONFIG_NE2K_PCI is not set
@@ -516,6 +514,10 @@
 CONFIG_SK98LIN=y
 # CONFIG_VIA_VELOCITY is not set
 CONFIG_TIGON3=y
+CONFIG_MV643XX_ETH=y
+CONFIG_MV643XX_ETH_0=y
+CONFIG_MV643XX_ETH_1=y
+# CONFIG_MV643XX_ETH_2 is not set
 
 #
 # Ethernet (10000 Mbit)
@@ -573,19 +575,6 @@
 # CONFIG_INPUT_EVBUG is not set
 
 #
-# Input I/O drivers
-#
-# CONFIG_GAMEPORT is not set
-CONFIG_SOUND_GAMEPORT=y
-CONFIG_SERIO=y
-CONFIG_SERIO_I8042=y
-CONFIG_SERIO_SERPORT=y
-# CONFIG_SERIO_CT82C710 is not set
-# CONFIG_SERIO_PCIPS2 is not set
-CONFIG_SERIO_LIBPS2=y
-# CONFIG_SERIO_RAW is not set
-
-#
 # Input Device Drivers
 #
 CONFIG_INPUT_KEYBOARD=y
@@ -600,6 +589,18 @@
 # CONFIG_INPUT_MISC is not set
 
 #
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+CONFIG_SERIO_I8042=y
+CONFIG_SERIO_SERPORT=y
+# CONFIG_SERIO_PCIPS2 is not set
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_SERIO_RAW is not set
+# CONFIG_GAMEPORT is not set
+CONFIG_SOUND_GAMEPORT=y
+
+#
 # Character devices
 #
 CONFIG_VT=y
@@ -641,7 +642,6 @@
 # Watchdog Device Drivers
 #
 # CONFIG_SOFT_WATCHDOG is not set
-CONFIG_MV64X60_WDT=y
 
 #
 # PCI-based Watchdog Cards
@@ -663,9 +663,97 @@
 # CONFIG_RAW_DRIVER is not set
 
 #
+# TPM devices
+#
+# CONFIG_TCG_TPM is not set
+
+#
 # I2C support
 #
-# CONFIG_I2C is not set
+CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
+
+#
+# I2C Algorithms
+#
+# CONFIG_I2C_ALGOBIT is not set
+# CONFIG_I2C_ALGOPCF is not set
+# CONFIG_I2C_ALGOPCA is not set
+
+#
+# I2C Hardware Bus support
+#
+# CONFIG_I2C_ALI1535 is not set
+# CONFIG_I2C_ALI1563 is not set
+# CONFIG_I2C_ALI15X3 is not set
+# CONFIG_I2C_AMD756 is not set
+# CONFIG_I2C_AMD8111 is not set
+# CONFIG_I2C_I801 is not set
+# CONFIG_I2C_I810 is not set
+# CONFIG_I2C_ISA is not set
+# CONFIG_I2C_MPC is not set
+# CONFIG_I2C_NFORCE2 is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_PIIX4 is not set
+# CONFIG_I2C_PROSAVAGE is not set
+# CONFIG_I2C_SAVAGE4 is not set
+# CONFIG_SCx200_ACB is not set
+# CONFIG_I2C_SIS5595 is not set
+# CONFIG_I2C_SIS630 is not set
+# CONFIG_I2C_SIS96X is not set
+# CONFIG_I2C_STUB is not set
+# CONFIG_I2C_VIA is not set
+# CONFIG_I2C_VIAPRO is not set
+# CONFIG_I2C_VOODOO3 is not set
+# CONFIG_I2C_PCA_ISA is not set
+CONFIG_I2C_MV64XXX=y
+
+#
+# Hardware Sensors Chip support
+#
+CONFIG_I2C_SENSOR=y
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ASB100 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_FSCHER is not set
+# CONFIG_SENSORS_FSCPOS is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_LM63 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM87 is not set
+CONFIG_SENSORS_LM90=y
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_SIS5595 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_VIA686A is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83627HF is not set
+
+#
+# Other I2C Chip support
+#
+# CONFIG_SENSORS_EEPROM is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_RTC8564 is not set
+# CONFIG_SENSORS_M41T00 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
 
 #
 # Dallas's 1-wire bus
@@ -705,13 +793,9 @@
 #
 # USB support
 #
-# CONFIG_USB is not set
 CONFIG_USB_ARCH_HAS_HCD=y
 CONFIG_USB_ARCH_HAS_OHCI=y
-
-#
-# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
-#
+# CONFIG_USB is not set
 
 #
 # USB Gadget Support
@@ -851,7 +935,9 @@
 #
 # Kernel hacking
 #
+# CONFIG_PRINTK_TIME is not set
 # CONFIG_DEBUG_KERNEL is not set
+CONFIG_LOG_BUF_SHIFT=14
 # CONFIG_SERIAL_TEXT_DEBUG is not set
 
 #

^ permalink raw reply

* Re: Newer laptops & CPU speed
From: Benjamin Herrenschmidt @ 2005-03-15 23:35 UTC (permalink / raw)
  To: Joerg Dorchain; +Cc: linuxppc-dev list, debian-powerpc@lists.debian.org
In-Reply-To: <20050315140329.GA15214@Redstar.dorchain.net>


> My ibook G4 boots at low speed. /proc/cpuinfo shows 666MHz and a smiliar
> bogomips value. Nevertheless, the cpu frequency scaler works, i.e. set
> it to performance to be at high speed after boot up, or, as I currently
> do, use the userspace governor and powernowd. All this is without your
> patch (Did not try it yet, my ibook lacks internet) on linus' 2.6.11.

Sure, I already had support for some models :) The patch extends it to
all present and future models that are MacRISC3 and have a 7447A CPU.

Ben.

^ permalink raw reply

* Re: boot time scheduling hile atomic
From: Benjamin Herrenschmidt @ 2005-03-16  0:18 UTC (permalink / raw)
  To: Takeharu KATO; +Cc: linuxppc-dev list
In-Reply-To: <4231387D.6030204@jp.fujitsu.com>

On Fri, 2005-03-11 at 15:19 +0900, Takeharu KATO wrote:
> Hi Joerg:
> 
> First of all, I am sorry to making mistake on my stack analysis.
> After all, I found what is wrong.
> 
> The syscall_exit_work is called(jumped) by fork, strictly speaking,
> this is caused by kernel_thead for init process.
> At this point, kernel set a need_resched flag in thread_info struct
> (flags member).
> So, the system executes syscall_exit_work when
> the swapper thread exited from syscall.
> 
> However, the syscall_exit_work routine does not check
> preempt counts when it calls schedule function.
> 
> FYI, I post the patch which fix this problem.
> I've confirmed the problem has been removed by this patch,
> but I can not figure out whether it is truely
> correct or not.

I think the problem is more why are we calling a syscall while the
preempt count is up ?

Ben.

^ permalink raw reply

* [PATCH 2.6.12] ppc32: Clean up mv64x60 bootwrapper support
From: Mark A. Greer @ 2005-03-16  1:33 UTC (permalink / raw)
  To: akpm; +Cc: Embedded PPC Linux list

[-- Attachment #1: Type: text/plain, Size: 534 bytes --]

ppc32: Clean up mv64x60 bootwrapper support

This patch removes the call to mv64x60_init() in 
arch/ppc/boot/simple/head.S and now uses the 'load_kernel()' hook to 
call to have mv64x60-specific code called.  This means that the mv64x60 
code will be called after the bootwrapper has relocated itself.  The 
platforms affected by this change are updated by this patch as well.

Depends on patch: 
http://ozlabs.org/pipermail/linuxppc-embedded/2005-March/017269.html

Please apply.

Signed-off-by: Mark A. Greer <mgreer@mvista.com>
--

[-- Attachment #2: ppc32_bootwrapper.patch --]
[-- Type: text/plain, Size: 23908 bytes --]

diff -Nru a/arch/ppc/boot/simple/Makefile b/arch/ppc/boot/simple/Makefile
--- a/arch/ppc/boot/simple/Makefile	2005-03-15 18:24:50 -07:00
+++ b/arch/ppc/boot/simple/Makefile	2005-03-15 18:24:50 -07:00
@@ -49,7 +49,7 @@
 #----------------------------------------------------------------------------
       zimage-$(CONFIG_CPCI690)		:= zImage-STRIPELF
 zimageinitrd-$(CONFIG_CPCI690)		:= zImage.initrd-STRIPELF
-     extra.o-$(CONFIG_CPCI690)		:= misc-cpci690.o mv64x60_stub.o
+     extra.o-$(CONFIG_CPCI690)		:= misc-cpci690.o
          end-$(CONFIG_CPCI690)		:= cpci690
    cacheflag-$(CONFIG_CPCI690)		:= -include $(clear_L2_L3)
 
@@ -94,11 +94,11 @@
          end-$(CONFIG_K2)		:= k2
    cacheflag-$(CONFIG_K2)		:= -include $(clear_L2_L3)
 
-     extra.o-$(CONFIG_KATANA)		:= misc-katana.o mv64x60_stub.o
+     extra.o-$(CONFIG_KATANA)		:= misc-katana.o
          end-$(CONFIG_KATANA)		:= katana
    cacheflag-$(CONFIG_KATANA)		:= -include $(clear_L2_L3)
 
-     extra.o-$(CONFIG_RADSTONE_PPC7D)	:= misc-radstone_ppc7d.o mv64x60_stub.o
+     extra.o-$(CONFIG_RADSTONE_PPC7D)	:= misc-radstone_ppc7d.o
          end-$(CONFIG_RADSTONE_PPC7D)	:= radstone_ppc7d
    cacheflag-$(CONFIG_RADSTONE_PPC7D)	:= -include $(clear_L2_L3)
 
diff -Nru a/arch/ppc/boot/simple/head.S b/arch/ppc/boot/simple/head.S
--- a/arch/ppc/boot/simple/head.S	2005-03-15 18:24:50 -07:00
+++ b/arch/ppc/boot/simple/head.S	2005-03-15 18:24:50 -07:00
@@ -135,11 +135,6 @@
 			 */
 #endif
 
-#ifdef	CONFIG_MV64X60
-	/* mv64x60 specific hook to do things like moving register base, etc. */
-	bl	mv64x60_init
-#endif
-
 	/* Get the load address.
 	*/
 	subi	r3, r3, 4	/* Get the actual IP, not NIP */
diff -Nru a/arch/ppc/boot/simple/misc-chestnut.S b/arch/ppc/boot/simple/misc-chestnut.S
--- a/arch/ppc/boot/simple/misc-chestnut.S	2005-03-15 18:24:50 -07:00
+++ /dev/null	Wed Dec 31 16:00:00 196900
@@ -1,41 +0,0 @@
-/*
- * arch/ppc/boot/simple/misc-chestnut.S
- *
- * Setup for the IBM Chestnut (ibm-750fxgx_eval)
- *
- * Author: <source@mvista.com>
- *
- * <2004> (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-
-#include <asm/ppc_asm.h>
-#include <asm/mv64x60_defs.h>
-#include <platforms/chestnut.h>
-
-	.globl	mv64x60_board_init
-mv64x60_board_init:
-	/*
-	 * move UART to 0xffc00000
-	 */
-
-	li      r23,16
-
-	addis	r25,0,CONFIG_MV64X60_BASE@h
-	ori     r25,r25,MV64x60_CPU2DEV_2_BASE
-	addis   r26,0,CHESTNUT_UART_BASE@h
-	srw     r26,r26,r23
-	stwbrx  r26,0,(r25)
-	sync
-
-	addis	r25,0,CONFIG_MV64X60_BASE@h
-	ori     r25,r25,MV64x60_CPU2DEV_2_SIZE
-	addis   r26,0,0x00100000@h
-	srw     r26,r26,r23
-	stwbrx  r26,0,(r25)
-	sync
-
-	blr
diff -Nru a/arch/ppc/boot/simple/misc-chestnut.c b/arch/ppc/boot/simple/misc-chestnut.c
--- /dev/null	Wed Dec 31 16:00:00 196900
+++ b/arch/ppc/boot/simple/misc-chestnut.c	2005-03-15 18:24:50 -07:00
@@ -0,0 +1,35 @@
+/*
+ * arch/ppc/boot/simple/misc-chestnut.c
+ *
+ * Setup for the IBM Chestnut (ibm-750fxgx_eval)
+ *
+ * Author: Mark A. Greer <mgreer@mvista.com>
+ *
+ * 2005 (c) MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+
+#include <linux/config.h>
+#include <linux/types.h>
+#include <asm/io.h>
+#include <asm/mv64x60_defs.h>
+#include <platforms/chestnut.h>
+
+/* Not in the kernel so won't include kernel.h to get its 'max' definition */
+#define max(a,b)	(((a) > (b)) ? (a) : (b))
+
+void
+mv64x60_board_init(void __iomem *old_base, void __iomem *new_base)
+{
+#ifdef CONFIG_SERIAL_8250_CONSOLE
+	/*
+	 * Change device bus 2 window so that bootoader can do I/O thru
+	 * 8250/16550 UART that's mapped in that window.
+	 */
+	out_le32(new_base + MV64x60_CPU2DEV_2_BASE, CHESTNUT_UART_BASE >> 16);
+	out_le32(new_base + MV64x60_CPU2DEV_2_SIZE, CHESTNUT_UART_SIZE >> 16);
+	__asm__ __volatile__("sync");
+#endif
+}
diff -Nru a/arch/ppc/boot/simple/misc-cpci690.c b/arch/ppc/boot/simple/misc-cpci690.c
--- a/arch/ppc/boot/simple/misc-cpci690.c	2005-03-15 18:24:50 -07:00
+++ b/arch/ppc/boot/simple/misc-cpci690.c	2005-03-15 18:24:50 -07:00
@@ -12,4 +12,16 @@
  */
 
 #include <linux/types.h>
-long	mv64x60_mpsc_clk_freq = 133000000;
+#include <platforms/cpci690.h>
+
+extern u32 mv64x60_console_baud;
+extern u32 mv64x60_mpsc_clk_src;
+extern u32 mv64x60_mpsc_clk_freq;
+
+void
+mv64x60_board_init(void __iomem *old_base, void __iomem *new_base)
+{
+	mv64x60_console_baud = CPCI690_MPSC_BAUD;
+	mv64x60_mpsc_clk_src = CPCI690_MPSC_CLK_SRC;
+	mv64x60_mpsc_clk_freq = CPCI690_BUS_FREQ;
+}
diff -Nru a/arch/ppc/boot/simple/misc-ev64260.S b/arch/ppc/boot/simple/misc-ev64260.S
--- a/arch/ppc/boot/simple/misc-ev64260.S	2005-03-15 18:24:50 -07:00
+++ /dev/null	Wed Dec 31 16:00:00 196900
@@ -1,68 +0,0 @@
-/*
- * arch/ppc/boot/simple/misc-ev64260.S
- *
- * Host bridge init code for the Marvell/Galileo EV-64260-BP evaluation board
- * with a GT64260 onboard.
- *
- * Author: Mark Greer <mgreer@mvista.com>
- *
- * 2001 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#include <asm/ppc_asm.h>
-#include <asm/processor.h>
-#include <asm/cache.h>
-#include <asm/mv64x60_defs.h>
-#include <platforms/ev64260.h>
-
-	.globl	mv64x60_board_init
-mv64x60_board_init:
-	/* DINK doesn't enable 745x timebase, so enable here (Adrian Cox) */
-	mfspr	r25,SPRN_PVR
-	srwi	r25,r25,16
-	cmplwi	r25,(PVR_7450 >> 16)
-	bne	1f
-	mfspr	r25,SPRN_HID0
-	oris	r25,r25,(HID0_TBEN >> 16)
-	mtspr	SPRN_HID0,r25
-1:
-#if (CONFIG_MV64X60_NEW_BASE != CONFIG_MV64X60_BASE)
-	li	r23,20
-
-	/*
-	 * Change the CS2 window for the UART so that the bootloader
-	 * can do I/O thru the UARTs.
-	 */
-	addis	r25,0,CONFIG_MV64X60_NEW_BASE@h
-	ori	r25,r25,MV64x60_CPU2DEV_2_BASE
-	addis	r26,0,EV64260_UART_BASE@h
-	srw	r26,r26,r23
-	stwbrx	r26,0,(r25)
-	sync
-
-	addis	r25,0,CONFIG_MV64X60_NEW_BASE@h
-	ori	r25,r25,MV64x60_CPU2DEV_2_SIZE
-	addis	r26,0,EV64260_UART_END@h
-	srw	r26,r26,r23
-	stwbrx	r26,0,(r25)
-	sync
-#endif
-	blr
-
-#if defined(CONFIG_SERIAL_MPSC_CONSOLE)
-.data
-	.globl	mv64x60_console_baud
-mv64x60_console_baud:
-.long	EV64260_DEFAULT_BAUD
-
-	.globl	mv64x60_mpsc_clk_src
-mv64x60_mpsc_clk_src:
-.long	EV64260_MPSC_CLK_SRC
-
-	.globl	mv64x60_mpsc_clk_freq
-mv64x60_mpsc_clk_freq:
-.long	EV64260_MPSC_CLK_FREQ
-#endif
diff -Nru a/arch/ppc/boot/simple/misc-ev64260.c b/arch/ppc/boot/simple/misc-ev64260.c
--- /dev/null	Wed Dec 31 16:00:00 196900
+++ b/arch/ppc/boot/simple/misc-ev64260.c	2005-03-15 18:24:50 -07:00
@@ -0,0 +1,57 @@
+/*
+ * arch/ppc/boot/simple/misc-ev64260.c
+ *
+ * Host bridge init code for the Marvell/Galileo EV-64260-BP evaluation board
+ * with a GT64260 onboard.
+ *
+ * Author: Mark A. Greer <mgreer@mvista.com>
+ *
+ * 2001 (c) MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+
+#include <linux/config.h>
+#include <linux/types.h>
+#include <asm/reg.h>
+#include <asm/io.h>
+#include <asm/mv64x60_defs.h>
+#include <platforms/ev64260.h>
+
+#ifdef CONFIG_SERIAL_MPSC_CONSOLE
+extern u32 mv64x60_console_baud;
+extern u32 mv64x60_mpsc_clk_src;
+extern u32 mv64x60_mpsc_clk_freq;
+#endif
+
+void
+mv64x60_board_init(void __iomem *old_base, void __iomem *new_base)
+{
+	u32	p, v;
+
+	/* DINK doesn't enable 745x timebase, so enable here (Adrian Cox) */
+	p = mfspr(SPRN_PVR);
+	p >>= 16;
+
+	/* Reasonable SWAG at a 745x PVR value */
+	if (((p & 0xfff0) == 0x8000) && (p != 0x800c)) {
+		v = mfspr(SPRN_HID0);
+		v |= HID0_TBEN;
+		mtspr(SPRN_HID0, v);
+	}
+
+#ifdef CONFIG_SERIAL_8250_CONSOLE
+	/*
+	 * Change device bus 2 window so that bootoader can do I/O thru
+	 * 8250/16550 UART that's mapped in that window.
+	 */
+	out_le32(new_base + MV64x60_CPU2DEV_2_BASE, EV64260_UART_BASE >> 20);
+	out_le32(new_base + MV64x60_CPU2DEV_2_SIZE, EV64260_UART_END >> 20);
+	__asm__ __volatile__("sync");
+#elif defined(CONFIG_SERIAL_MPSC_CONSOLE)
+	mv64x60_console_baud = EV64260_DEFAULT_BAUD;
+	mv64x60_mpsc_clk_src = EV64260_MPSC_CLK_SRC;
+	mv64x60_mpsc_clk_freq = EV64260_MPSC_CLK_FREQ;
+#endif
+}
diff -Nru a/arch/ppc/boot/simple/misc-katana.c b/arch/ppc/boot/simple/misc-katana.c
--- a/arch/ppc/boot/simple/misc-katana.c	2005-03-15 18:24:50 -07:00
+++ b/arch/ppc/boot/simple/misc-katana.c	2005-03-15 18:24:50 -07:00
@@ -1,7 +1,7 @@
 /*
  * arch/ppc/boot/simple/misc-katana.c
  *
- * Add birec data for Artesyn KATANA board.
+ * Set up MPSC values to bootwrapper can prompt user.
  *
  * Author: Mark A. Greer <source@mvista.com>
  *
@@ -11,5 +11,27 @@
  * or implied.
  */
 
+#include <linux/config.h>
 #include <linux/types.h>
-long	mv64x60_mpsc_clk_freq = 133333333;
+#include <asm/io.h>
+#include <asm/mv64x60_defs.h>
+#include <platforms/katana.h>
+
+extern u32 mv64x60_console_baud;
+extern u32 mv64x60_mpsc_clk_src;
+extern u32 mv64x60_mpsc_clk_freq;
+
+/* Not in the kernel so won't include kernel.h to get its 'min' definition */
+#ifndef min
+#define	min(a,b)	(((a) < (b)) ? (a) : (b))
+#endif
+
+void
+mv64x60_board_init(void __iomem *old_base, void __iomem *new_base)
+{
+	mv64x60_console_baud = KATANA_DEFAULT_BAUD;
+	mv64x60_mpsc_clk_src = KATANA_MPSC_CLK_SRC;
+	mv64x60_mpsc_clk_freq =
+		min(katana_bus_freq((void __iomem *)KATANA_CPLD_BASE),
+			MV64x60_TCLK_FREQ_MAX);
+}
diff -Nru a/arch/ppc/boot/simple/misc-mv64x60.S b/arch/ppc/boot/simple/misc-mv64x60.S
--- a/arch/ppc/boot/simple/misc-mv64x60.S	2005-03-15 18:24:50 -07:00
+++ /dev/null	Wed Dec 31 16:00:00 196900
@@ -1,61 +0,0 @@
-/*
- * arch/ppc/boot/simple/misc-mv64x60.S
- *
- * Code to change the base address of the host bridges and call board specific
- * init routine.
- *
- * Author: Mark Greer <mgreer@mvista.com>
- *
- * 2002 (c) MontaVista, Software, Inc.  This file is licensed under the terms
- * of the GNU General Public License version 2.  This program is licensed
- * "as is" without any warranty of any kind, whether express or implied.
- */
-
-#include <linux/config.h>
-#include <asm/ppc_asm.h>
-#include <asm/processor.h>
-#include <asm/cache.h>
-#include <asm/mv64x60_defs.h>
-
-	.globl	mv64x60_init
-mv64x60_init:
-	mflr	r27
-
-#if (CONFIG_MV64X60_NEW_BASE != CONFIG_MV64X60_BASE)
-	bl	move_base
-#endif
-	bl	mv64x60_board_init
-
-	mtlr	r27
-	blr
-
-#if (CONFIG_MV64X60_NEW_BASE != CONFIG_MV64X60_BASE)
-move_base:
-	li	r20,0
-#ifdef CONFIG_GT64260
-	li	r23,20
-#else /* Must be mv64[34]60 which uses top 16 bits */
-	li	r23,16
-#endif
-
-	/* Relocate bridge's regs */
-	addis	r25,0,CONFIG_MV64X60_BASE@h
-	ori	r25,r25,MV64x60_INTERNAL_SPACE_DECODE
-	lwbrx	r26,0,(r25)
-	lis	r24,0xffff
-	and	r26,r26,r24
-	addis	r24,0,CONFIG_MV64X60_NEW_BASE@h
-	srw	r24,r24,r23
-	or	r26,r26,r24
-	stwbrx	r26,0,(r25)
-	sync
-
-	/* Wait for write to take effect */
-	addis	r25,0,CONFIG_MV64X60_NEW_BASE@h
-	ori	r25,r25,MV64x60_INTERNAL_SPACE_DECODE
-1:	lwbrx	r24,0,(r25)
-	cmpw	r24,r26
-	bne	1b
-
-	blr
-#endif
diff -Nru a/arch/ppc/boot/simple/misc-mv64x60.c b/arch/ppc/boot/simple/misc-mv64x60.c
--- /dev/null	Wed Dec 31 16:00:00 196900
+++ b/arch/ppc/boot/simple/misc-mv64x60.c	2005-03-15 18:24:50 -07:00
@@ -0,0 +1,61 @@
+/*
+ * arch/ppc/boot/simple/misc-mv64x60.c
+ *
+ * Relocate bridge's register base and call board specific routine.
+ *
+ * Author: Mark A. Greer <source@mvista.com>
+ *
+ * 2005 (c) MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+
+#include <linux/config.h>
+#include <linux/types.h>
+#include <asm/io.h>
+#include <asm/mv64x60_defs.h>
+
+extern struct bi_record *decompress_kernel(unsigned long load_addr,
+	int num_words, unsigned long cksum);
+
+void
+mv64x60_move_base(void __iomem *old_base, void __iomem *new_base)
+{
+	u32	bits, mask, b;
+
+	if (old_base != new_base) {
+#ifdef CONFIG_GT64260
+		bits = 12; 
+		mask = 0x07000000;
+#else /* Must be mv64[34]60 */
+		bits = 16; 
+		mask = 0x03000000;
+#endif
+		b = in_le32(old_base + MV64x60_INTERNAL_SPACE_DECODE);
+		b &= mask;
+		b |= ((u32)new_base >> (32 - bits));
+		out_le32(old_base + MV64x60_INTERNAL_SPACE_DECODE, b);
+
+		__asm__ __volatile__("sync");
+
+		/* Wait for change to happen (in accordance with the manual) */
+		while (in_le32(new_base + MV64x60_INTERNAL_SPACE_DECODE) != b);
+	}
+}
+
+void __attribute__ ((weak))
+mv64x60_board_init(void __iomem *old_base, void __iomem *new_base)
+{
+}
+
+void *
+load_kernel(unsigned long load_addr, int num_words, unsigned long cksum,
+		void *ign1, void *ign2)
+{
+	mv64x60_move_base((void __iomem *)CONFIG_MV64X60_BASE,
+		(void __iomem *)CONFIG_MV64X60_NEW_BASE);
+	mv64x60_board_init((void __iomem *)CONFIG_MV64X60_BASE,
+		(void __iomem *)CONFIG_MV64X60_NEW_BASE);
+	return decompress_kernel(load_addr, num_words, cksum);
+}
diff -Nru a/arch/ppc/boot/simple/misc-radstone_ppc7d.c b/arch/ppc/boot/simple/misc-radstone_ppc7d.c
--- a/arch/ppc/boot/simple/misc-radstone_ppc7d.c	2005-03-15 18:24:50 -07:00
+++ b/arch/ppc/boot/simple/misc-radstone_ppc7d.c	2005-03-15 18:24:50 -07:00
@@ -7,13 +7,20 @@
  */
 
 #include <linux/types.h>
-#include <asm/reg.h>
-
-#include "../../platforms/radstone_ppc7d.h"
+#include <platforms/radstone_ppc7d.h>
 
 #if defined(CONFIG_SERIAL_MPSC_CONSOLE)
-long	mv64x60_mpsc_clk_freq = PPC7D_MPSC_CLK_FREQ;;
-long	mv64x60_mpsc_clk_src = PPC7D_MPSC_CLK_SRC;
-long	mv64x60_mpsc_console_baud = PPC7D_DEFAULT_BAUD;
+extern u32 mv64x60_console_baud;
+extern u32 mv64x60_mpsc_clk_src;
+extern u32 mv64x60_mpsc_clk_freq;
 #endif
 
+void
+mv64x60_board_init(void __iomem *old_base, void __iomem *new_base)
+{
+#if defined(CONFIG_SERIAL_MPSC_CONSOLE)
+	mv64x60_console_baud = PPC7D_DEFAULT_BAUD;
+	mv64x60_mpsc_clk_src = PPC7D_MPSC_CLK_SRC;
+	mv64x60_mpsc_clk_freq = PPC7D_MPSC_CLK_FREQ;
+#endif
+}
diff -Nru a/arch/ppc/boot/simple/mv64x60_stub.c b/arch/ppc/boot/simple/mv64x60_stub.c
--- a/arch/ppc/boot/simple/mv64x60_stub.c	2005-03-15 18:24:50 -07:00
+++ /dev/null	Wed Dec 31 16:00:00 196900
@@ -1,24 +0,0 @@
-/*
- * arch/ppc/boot/simple/mv64x60_stub.c
- *
- * Stub for board_init() routine called from mv64x60_init().
- *
- * Author: Mark A. Greer <mgreer@mvista.com>
- *
- * 2002 (c) MontaVista, Software, Inc.  This file is licensed under the terms
- * of the GNU General Public License version 2.  This program is licensed
- * "as is" without any warranty of any kind, whether express or implied.
- */
-
-#include <linux/config.h>
-
-#if defined(CONFIG_SERIAL_MPSC_CONSOLE)
-long __attribute__ ((weak))	mv64x60_console_baud = 9600;
-long __attribute__ ((weak))	mv64x60_mpsc_clk_src = 8; /* TCLK */
-long __attribute__ ((weak))	mv64x60_mpsc_clk_freq = 100000000;
-#endif
-
-void __attribute__ ((weak))
-mv64x60_board_init(void)
-{
-}
diff -Nru a/arch/ppc/boot/simple/mv64x60_tty.c b/arch/ppc/boot/simple/mv64x60_tty.c
--- a/arch/ppc/boot/simple/mv64x60_tty.c	2005-03-15 18:24:50 -07:00
+++ b/arch/ppc/boot/simple/mv64x60_tty.c	2005-03-15 18:24:50 -07:00
@@ -18,36 +18,18 @@
 #include <linux/types.h>
 #include <linux/serial_reg.h>
 #include <asm/serial.h>
+#include <asm/io.h>
 #include <asm/mv64x60_defs.h>
 #include <mpsc_defs.h>
 
+u32	mv64x60_console_baud = 9600;
+u32	mv64x60_mpsc_clk_src = 8; /* TCLK */
+u32	mv64x60_mpsc_clk_freq = 100000000;
+
 extern void udelay(long);
 static void stop_dma(int chan);
 
-static u32	mv64x60_base = CONFIG_MV64X60_NEW_BASE;
-
-inline unsigned
-mv64x60_in_le32(volatile unsigned *addr)
-{
-	unsigned ret;
-
-	__asm__ __volatile__("lwbrx %0,0,%1; eieio" : "=r" (ret) :
-				"r" (addr), "m" (*addr));
-	return ret;
-}
-
-inline void
-mv64x60_out_le32(volatile unsigned *addr, int val)
-{
-	__asm__ __volatile__("stwbrx %1,0,%2; eieio" : "=m" (*addr) :
-				"r" (val), "r" (addr));
-}
-
-#define MV64x60_REG_READ(offs)						\
-	(mv64x60_in_le32((volatile uint *)(mv64x60_base + (offs))))
-#define MV64x60_REG_WRITE(offs, d)					\
-	(mv64x60_out_le32((volatile uint *)(mv64x60_base + (offs)), (int)(d)))
-
+static void __iomem *mv64x60_base = (void __iomem *)CONFIG_MV64X60_NEW_BASE;
 
 struct sdma_regs {
 	u32	sdc;
@@ -142,9 +124,6 @@
 {
 	u32		mpsc_routing_base, sdma_base, brg_bcr, cdv;
 	int		i;
-	extern long	mv64x60_console_baud;
-	extern long	mv64x60_mpsc_clk_src;
-	extern long	mv64x60_mpsc_clk_freq;
 
 	chan = (chan == 1); /* default to chan 0 if anything but 1 */
 
@@ -157,8 +136,7 @@
 		sdma_base = MV64x60_SDMA_0_OFFSET;
 		brg_bcr = MV64x60_BRG_0_OFFSET + BRG_BCR;
 		SDMA_REGS_INIT(&sdma_regs[0], MV64x60_SDMA_0_OFFSET);
-	}
-	else {
+	} else {
 		sdma_base = MV64x60_SDMA_1_OFFSET;
 		brg_bcr = MV64x60_BRG_1_OFFSET + BRG_BCR;
 		SDMA_REGS_INIT(&sdma_regs[0], MV64x60_SDMA_1_OFFSET);
@@ -186,10 +164,10 @@
 	td[chan][TX_NUM_DESC - 1].next_desc_ptr = (u32)&td[chan][0];
 
 	/* Set MPSC Routing */
-	MV64x60_REG_WRITE(mpsc_routing_base + MPSC_MRR, 0x3ffffe38);
+	out_le32(mv64x60_base + mpsc_routing_base + MPSC_MRR, 0x3ffffe38);
 
 #ifdef CONFIG_GT64260
-	MV64x60_REG_WRITE(GT64260_MPP_SERIAL_PORTS_MULTIPLEX, 0x00001102);
+	out_le32(mv64x60_base + GT64260_MPP_SERIAL_PORTS_MULTIPLEX, 0x00001102);
 #else /* Must be MV64360 or MV64460 */
 	{
 	u32	enables, prot_bits, v;
@@ -197,68 +175,70 @@
 	/* Set up comm unit to memory mapping windows */
 	/* Note: Assumes MV64x60_CPU2MEM_WINDOWS == 4 */
 
-	enables = MV64x60_REG_READ(MV64360_CPU_BAR_ENABLE) & 0xf;
+	enables = in_le32(mv64x60_base + MV64360_CPU_BAR_ENABLE) & 0xf;
 	prot_bits = 0;
 
 	for (i=0; i<MV64x60_CPU2MEM_WINDOWS; i++) {
 		if (!(enables & (1 << i))) {
-			v = MV64x60_REG_READ(cpu2mem_tab[i][0]);
+			v = in_le32(mv64x60_base + cpu2mem_tab[i][0]);
 			v = ((v & 0xffff) << 16) | (dram_selects[i] << 8);
-			MV64x60_REG_WRITE(com2mem_tab[i][0], v);
+			out_le32(mv64x60_base + com2mem_tab[i][0], v);
 
-			v = MV64x60_REG_READ(cpu2mem_tab[i][1]);
+			v = in_le32(mv64x60_base + cpu2mem_tab[i][1]);
 			v = (v & 0xffff) << 16;
-			MV64x60_REG_WRITE(com2mem_tab[i][1], v);
+			out_le32(mv64x60_base + com2mem_tab[i][1], v);
 
 			prot_bits |= (0x3 << (i << 1)); /* r/w access */
 		}
 	}
 
-	MV64x60_REG_WRITE(MV64360_MPSC_0_REMAP, 0);
-	MV64x60_REG_WRITE(MV64360_MPSC_1_REMAP, 0);
-	MV64x60_REG_WRITE(MV64360_MPSC2MEM_ACC_PROT_0, prot_bits);
-	MV64x60_REG_WRITE(MV64360_MPSC2MEM_ACC_PROT_1, prot_bits);
-	MV64x60_REG_WRITE(MV64360_MPSC2MEM_BAR_ENABLE, enables);
+	out_le32(mv64x60_base + MV64360_MPSC_0_REMAP, 0);
+	out_le32(mv64x60_base + MV64360_MPSC_1_REMAP, 0);
+	out_le32(mv64x60_base + MV64360_MPSC2MEM_ACC_PROT_0, prot_bits);
+	out_le32(mv64x60_base + MV64360_MPSC2MEM_ACC_PROT_1, prot_bits);
+	out_le32(mv64x60_base + MV64360_MPSC2MEM_BAR_ENABLE, enables);
 	}
 #endif
 
 	/* MPSC 0/1 Rx & Tx get clocks BRG0/1 */
-	MV64x60_REG_WRITE(mpsc_routing_base + MPSC_RCRR, 0x00000100);
-	MV64x60_REG_WRITE(mpsc_routing_base + MPSC_TCRR, 0x00000100);
+	out_le32(mv64x60_base + mpsc_routing_base + MPSC_RCRR, 0x00000100);
+	out_le32(mv64x60_base + mpsc_routing_base + MPSC_TCRR, 0x00000100);
 
 	/* clear pending interrupts */
-	MV64x60_REG_WRITE(MV64x60_SDMA_INTR_OFFSET + SDMA_INTR_MASK, 0);
+	out_le32(mv64x60_base + MV64x60_SDMA_INTR_OFFSET + SDMA_INTR_MASK, 0);
 
-	MV64x60_REG_WRITE(SDMA_SCRDP + sdma_base, &rd[chan][0]);
-	MV64x60_REG_WRITE(SDMA_SCTDP + sdma_base, &td[chan][TX_NUM_DESC - 1]);
-	MV64x60_REG_WRITE(SDMA_SFTDP + sdma_base, &td[chan][TX_NUM_DESC - 1]);
+	out_le32(mv64x60_base + SDMA_SCRDP + sdma_base, (int)&rd[chan][0]);
+	out_le32(mv64x60_base + SDMA_SCTDP + sdma_base,
+		(int)&td[chan][TX_NUM_DESC - 1]);
+	out_le32(mv64x60_base + SDMA_SFTDP + sdma_base,
+		(int)&td[chan][TX_NUM_DESC - 1]);
 
-	MV64x60_REG_WRITE(SDMA_SDC + sdma_base,
+	out_le32(mv64x60_base + SDMA_SDC + sdma_base,
 		SDMA_SDC_RFT | SDMA_SDC_SFM | SDMA_SDC_BLMR | SDMA_SDC_BLMT |
 		(3 << 12));
 
 	cdv = ((mv64x60_mpsc_clk_freq/(32*mv64x60_console_baud))-1);
-	MV64x60_REG_WRITE(brg_bcr,
+	out_le32(mv64x60_base + brg_bcr,
 		((mv64x60_mpsc_clk_src << 18) | (1 << 16) | cdv));
 
 	/* Put MPSC into UART mode, no null modem, 16x clock mode */
-	MV64x60_REG_WRITE(MPSC_MMCRL + mpsc_base[chan], 0x000004c4);
-	MV64x60_REG_WRITE(MPSC_MMCRH + mpsc_base[chan], 0x04400400);
+	out_le32(mv64x60_base + MPSC_MMCRL + mpsc_base[chan], 0x000004c4);
+	out_le32(mv64x60_base + MPSC_MMCRH + mpsc_base[chan], 0x04400400);
 
-	MV64x60_REG_WRITE(MPSC_CHR_1 + mpsc_base[chan], 0);
-	MV64x60_REG_WRITE(MPSC_CHR_9 + mpsc_base[chan], 0);
-	MV64x60_REG_WRITE(MPSC_CHR_10 + mpsc_base[chan], 0);
-	MV64x60_REG_WRITE(MPSC_CHR_3 + mpsc_base[chan], 4);
-	MV64x60_REG_WRITE(MPSC_CHR_4 + mpsc_base[chan], 0);
-	MV64x60_REG_WRITE(MPSC_CHR_5 + mpsc_base[chan], 0);
-	MV64x60_REG_WRITE(MPSC_CHR_6 + mpsc_base[chan], 0);
-	MV64x60_REG_WRITE(MPSC_CHR_7 + mpsc_base[chan], 0);
-	MV64x60_REG_WRITE(MPSC_CHR_8 + mpsc_base[chan], 0);
+	out_le32(mv64x60_base + MPSC_CHR_1 + mpsc_base[chan], 0);
+	out_le32(mv64x60_base + MPSC_CHR_9 + mpsc_base[chan], 0);
+	out_le32(mv64x60_base + MPSC_CHR_10 + mpsc_base[chan], 0);
+	out_le32(mv64x60_base + MPSC_CHR_3 + mpsc_base[chan], 4);
+	out_le32(mv64x60_base + MPSC_CHR_4 + mpsc_base[chan], 0);
+	out_le32(mv64x60_base + MPSC_CHR_5 + mpsc_base[chan], 0);
+	out_le32(mv64x60_base + MPSC_CHR_6 + mpsc_base[chan], 0);
+	out_le32(mv64x60_base + MPSC_CHR_7 + mpsc_base[chan], 0);
+	out_le32(mv64x60_base + MPSC_CHR_8 + mpsc_base[chan], 0);
 
 	/* 8 data bits, 1 stop bit */
-	MV64x60_REG_WRITE(MPSC_MPCR + mpsc_base[chan], (3 << 12));
-	MV64x60_REG_WRITE(SDMA_SDCM + sdma_base, SDMA_SDCM_ERD);
-	MV64x60_REG_WRITE(MPSC_CHR_2 + mpsc_base[chan], MPSC_CHR_2_EH);
+	out_le32(mv64x60_base + MPSC_MPCR + mpsc_base[chan], (3 << 12));
+	out_le32(mv64x60_base + SDMA_SDCM + sdma_base, SDMA_SDCM_ERD);
+	out_le32(mv64x60_base + MPSC_CHR_2 + mpsc_base[chan], MPSC_CHR_2_EH);
 
 	udelay(100);
 
@@ -271,20 +251,19 @@
 	int	i;
 
 	/* Abort MPSC Rx (aborting Tx messes things up) */
-	MV64x60_REG_WRITE(MPSC_CHR_2 + mpsc_base[chan], MPSC_CHR_2_RA);
+	out_le32(mv64x60_base + MPSC_CHR_2 + mpsc_base[chan], MPSC_CHR_2_RA);
 
 	/* Abort SDMA Rx, Tx */
-	MV64x60_REG_WRITE(sdma_regs[chan].sdcm, SDMA_SDCM_AR | SDMA_SDCM_STD);
+	out_le32(mv64x60_base + sdma_regs[chan].sdcm,
+		SDMA_SDCM_AR | SDMA_SDCM_STD);
 
 	for (i=0; i<MAX_RESET_WAIT; i++) {
-		if ((MV64x60_REG_READ(sdma_regs[chan].sdcm) &
+		if ((in_le32(mv64x60_base + sdma_regs[chan].sdcm) &
 				(SDMA_SDCM_AR | SDMA_SDCM_AT)) == 0)
 			break;
 
 		udelay(100);
 	}
-
-	return;
 }
 
 static int
@@ -293,7 +272,7 @@
 	int	i;
 
 	for (i=0; i<MAX_TX_WAIT; i++) {
-		if ((MV64x60_REG_READ(sdma_regs[chan].sdcm) &
+		if ((in_le32(mv64x60_base + sdma_regs[chan].sdcm) &
 				SDMA_SDCM_TXD) == 0)
 			break;
 
@@ -321,12 +300,11 @@
 	tdp->cmd_stat = SDMA_DESC_CMDSTAT_L | SDMA_DESC_CMDSTAT_F |
 		SDMA_DESC_CMDSTAT_O;
 
-	MV64x60_REG_WRITE(sdma_regs[com_port].sctdp, tdp);
-	MV64x60_REG_WRITE(sdma_regs[com_port].sftdp, tdp);
-	MV64x60_REG_WRITE(sdma_regs[com_port].sdcm,
-		MV64x60_REG_READ(sdma_regs[com_port].sdcm) | SDMA_SDCM_TXD);
-
-	return;
+	out_le32(mv64x60_base + sdma_regs[com_port].sctdp, (int)tdp);
+	out_le32(mv64x60_base + sdma_regs[com_port].sftdp, (int)tdp);
+	out_le32(mv64x60_base + sdma_regs[com_port].sdcm,
+		in_le32(mv64x60_base + sdma_regs[com_port].sdcm) |
+			SDMA_SDCM_TXD);
 }
 
 unsigned char
@@ -366,8 +344,7 @@
 			if (++cur_rd[com_port] >= RX_NUM_DESC)
 				cur_rd[com_port] = 0;
 			rdp = (struct mv64x60_rx_desc *)rdp->next_desc_ptr;
-		}
-		else {
+		} else {
 			rc = 1;
 			break;
 		}
@@ -380,5 +357,4 @@
 serial_close(unsigned long com_port)
 {
 	stop_dma(com_port);
-	return;
 }

^ permalink raw reply

* Re: mtd maps
From: Josh Boyer @ 2005-03-16  1:33 UTC (permalink / raw)
  To: Matt Porter; +Cc: linuxppc-embedded
In-Reply-To: <20050315133231.A5861@cox.net>

On Tue, 2005-03-15 at 13:32 -0700, Matt Porter wrote:
> On Tue, Mar 15, 2005 at 11:44:00AM -0700, Mark A. Greer wrote:
> > Greg Weeks wrote:
> > 
> > > Are mtd maps still in drivers/mtd/maps or has that all moved to the 
> > > platform code? I have an mtd map for the mpc8560ads but it's in mtd/maps.
> > 
> > 
> > The mtd code has changed so that platform code can get at the routines 
> > to set up the maps from there.  arch/ppc/platforms/katana.c has its mtd 
> > maps there and I recently posted a patch that moves it for the chestnut 
> > as well.
> > 
> > I think its a good idea to move them to the platform code since the mtd 
> > maps are platform specific anyway.  Plus its one less place to add/edit 
> > a file.  But that's just my $0.02...
> 
> But keep in mind that this currently only applies in the case where
> you need to map chips of the same type. Some boards have multiple
> chip types and physmap doesn't yet support that.

There is a driver in MTD CVS now called mphysmap (untested I believe),
that might be able to deal with that.  Eventually.

josh

^ permalink raw reply

* Re: [PATCH 1/3] PPC440EP SoC and Bamboo board support
From: Josh Boyer @ 2005-03-16  1:43 UTC (permalink / raw)
  To: Wade Farnsworth; +Cc: linuxppc-embedded
In-Reply-To: <1110907039.24673.12.camel@rhino.az.mvista.com>

On Tue, 2005-03-15 at 10:17 -0700, Wade Farnsworth wrote:
> Hello all,
> 
> This adds support for the IBM/AMCC PPC440EP SoC and the Bamboo reference
> board.  Any comments would be appreciated.

Isn't the NAND chip on that board a 64MiB chip?  If so, the
BAMBOO_NAND_FLASH_SIZE define is wrong.  It should be 0x4000000.

Also, are there any plans to add MTD support for the NAND controller
found on those boards?

thx,
josh

^ permalink raw reply

* Re: boot time scheduling hile atomic
From: Takeharu KATO @ 2005-03-16  5:24 UTC (permalink / raw)
  To: Benjamin Herrenschmidt; +Cc: linuxppc-dev list
In-Reply-To: <1110932285.25201.66.camel@gaston>

Hi Benjamin:

Thank you for your response.

> I think the problem is more why are we calling a syscall while the
> preempt count is up ?
> 
Because, start_kernel(line:455) in init/main.c count up this.
-- start_kernel (init/main.c)
451         /*
452          * Disable preemption - early bootup scheduling is extremely
453          * fragile until we cpu_idle() for the first time.
454          */
455         preempt_disable();
456         build_all_zonelists();
-- start_kernel(init/main.c)

Preemption is disabled until it enters the body of idle task from rest_init.
Please see below:
-- rest_init (init/main.c)
379 static void noinline rest_init(void)
380         __releases(kernel_lock)
381 {
382         kernel_thread(init, NULL, CLONE_FS | CLONE_SIGHAND);
383         numa_default_policy();
384         unlock_kernel();
385         preempt_enable_no_resched();
386         cpu_idle();
387 }
--
I think that the kernel assumes that init thread(the kernel thread which become to
init process later) is kicked by idle process(cpu_idle).

But, the kernel invoke a system call trap when it execute kernel_thread call
(at rest_init line:382) on PowerPC.
The preemption count has positive value here.
So, PowerPC linux kernel invoke system call when the preempt count is up.

Regards,

-- 
Takeharu KATO
Fujitsu Limited
Email:kato.takeharu at jp.fujitsu.com

^ permalink raw reply

* Re: boot time scheduling hile atomic
From: Takeharu KATO @ 2005-03-16  5:49 UTC (permalink / raw)
  To: benh; +Cc: linuxppc-dev
In-Reply-To: <4237C319.4050109@jp.fujitsu.com>

Hi Benjamin:

I forgot writing that I've sent the revised edition of
the patch to the PPC-Dev ML.
Please see the patch as ``boot time scheduling w hile atomic fix''
which I posted in 2005-03-15 from Patch tracking
system for PowerPC Linux as follows.

http://ozlabs.org/ppc32-patches/

It changes the implementation of kernel_thread function
to be performed with function call.

Regards,

Takeharu KATO wrote:

> But, the kernel invoke a system call trap when it execute kernel_thread call
> (at rest_init line:382) on PowerPC.
> The preemption count has positive value here.
> So, PowerPC linux kernel invoke system call when the preempt count is up.
> 

-- 
Takeharu KATO
Fujitsu Limited
Email:kato.takeharu at jp.fujitsu.com

^ permalink raw reply

* Re: boot time scheduling hile atomic
From: Benjamin Herrenschmidt @ 2005-03-16  6:28 UTC (permalink / raw)
  To: Takeharu KATO; +Cc: linuxppc-dev list
In-Reply-To: <4237C8F0.1010605@jp.fujitsu.com>

On Wed, 2005-03-16 at 14:49 +0900, Takeharu KATO wrote:
> Hi Benjamin:
> 
> I forgot writing that I've sent the revised edition of
> the patch to the PPC-Dev ML.
> Please see the patch as ``boot time scheduling w hile atomic fix''
> which I posted in 2005-03-15 from Patch tracking
> system for PowerPC Linux as follows.
> 
> http://ozlabs.org/ppc32-patches/
> 
> It changes the implementation of kernel_thread function
> to be performed with function call.

I prefer your previous patch. Paul hacked it a bit and will commit his
modified version.

Ben.

^ permalink raw reply


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