* Réf. : RE: mmap : please help !
From: scarayol @ 2005-04-14 9:38 UTC (permalink / raw)
To: Fillod Stephane; +Cc: linuxppc-embedded
St=E9phane,
thanks for your help.
But I think that, except instruction eieio, I do similar things. You u=
se
the virtual address returned by mmap but have you the same values if yo=
u
use write/read(axs_mem_fd,...) instead of in_8/out_8.
That is my problem : I want to be sure that when I use the virtual add=
ress
returned by mmap, I access really to the physical memory mapped area.
Do you know a shell command in order to dump the memory and verify what=
I
do ?
----------------------------------------------------------
Sophie CARAYOL
TECHNOLOGIES & SYSTEMES
50 rue du Pr=E9sident Sadate
F - 29337 QUIMPER CEDEX
T=E9l: +33 2 98 10 30 06
mailto:scarayol@assystembrime.com
----------------------------------------------------------
=
^ permalink raw reply
* Boot problems (NFS)
From: André Bitzer @ 2005-04-14 9:08 UTC (permalink / raw)
To: linuxppc-embedded
Hi,
I work with the 860FADS-Board and have the following problem:
I load the kernel to the flash with the u-boot (1.1.2). at startup of
the system, i copy the kernel to RAM and start it.
(set bootargs nfsroot=/tftpboot/busybox,nolock rw
ip=192.168.40.144:192.168.40.120::::eth0:on;
setenv bootcmd "cp.b 0xfe080000 0x100000 0xf7fff; bootm")
But, when i don't establish a network connection to my server (nfs-root)
with u-boot, the kernel will hang with this messages:
PQRM: Init
PQFEC: Init
NET4: Linux TCP/IP 1.0 for NET4.0
IP: routing cache hash table of 512 buckets, 4Kbytes
TCP: Hash tables configured (established 512 bind 1024)
PQFEC: Open eth0 device
IP-Config: Guessing netmask 255.255.255.0
IP-Config: Complete:
device=eth0, addr=192.168.40.144, mask=255.255.255.0,
gw=255.255.255.255,
host=192.168.40.144, domain=, nis-domain=(none),
bootserver=192.168.40.120, rootserver=192.168.40.120, rootpath=
NET4: Unix domain sockets 1.0/SMP for Linux NET4.0.
Looking up port of RPC 100003/2 on 192.168.40.120
portmap: server 192.168.40.120 not responding, timed out
Root-NFS: Unable to get nfsd port number from server, using default
Looking up port of RPC 100005/1 on 192.168.40.120
portmap: server 192.168.40.120 not responding, timed out
Root-NFS: Unable to get mountd port number from server, using default
mount: server 192.168.40.120 not responding, timed out
Root-NFS: Server returned error -5 while mounting /tftpboot/busybox
VFS: Unable to mount root fs via NFS, trying floppy.
VFS: Cannot open root device "" or 02:00
Please append a correct "root=" boot option
Kernel panic: VFS: Unable to mount root fs on 02:00
if i first open a tftp connection to my server with u-boot, then the
kernel starts properly.
With tcpdump i do the following dumps:
kernel start:
09:49:54.506470 arp who-has linux.site tell 192.168.40.144
09:49:54.506492 arp reply linux.site is-at 00:01:02:af:02:f0
09:49:54.506737 IP 192.168.40.144.mdbs_daemon > linux.site.sunrpc: UDP,
length: 56
09:49:54.508045 IP linux.site.sunrpc > 192.168.40.144.mdbs_daemon: UDP,
length: 28
09:49:54.522869 IP 192.168.40.144.mdbs_daemon > linux.site.sunrpc: UDP,
length: 56
09:49:54.523310 IP linux.site.sunrpc > 192.168.40.144.mdbs_daemon: UDP,
length: 28
09:49:54.524804 IP 192.168.40.144.mdbs_daemon > linux.site.783: UDP,
length: 64
09:49:54.547407 IP linux.site.783 > 192.168.40.144.mdbs_daemon: UDP,
length: 60
09:49:54.550351 IP 192.168.40.144.4024160259 > linux.site.nfs: 108
getattr [|nfs]
09:49:54.552402 IP linux.site.nfs > 192.168.40.144.4024160259: reply ok
96 getattr DIR 40755 ids 0/0 sz 480
09:49:54.553425 IP 192.168.40.144.4024160260 > linux.site.nfs: 108
fsstat [|nfs]
09:49:54.553473 IP linux.site.nfs > 192.168.40.144.4024160260: reply ok
48 fsstat tsize 32768 bsize 4096 blocks 1311254 bfree 198425 bavail
198425
09:49:54.564656 IP 192.168.40.144.4024160261 > linux.site.nfs: 108
getattr [|nfs]
09:49:54.564711 IP linux.site.nfs > 192.168.40.144.4024160261: reply ok
96 getattr DIR 40755 ids 0/0 sz 480
09:49:54.565727 IP 192.168.40.144.4024160262 > linux.site.nfs: 108
getattr [|nfs]
09:49:54.565759 IP linux.site.nfs > 192.168.40.144.4024160262: reply ok
96 getattr DIR 40755 ids 0/0 sz 480
09:49:54.566751 IP 192.168.40.144.4024160263 > linux.site.nfs: 116
lookup [|nfs]
09:49:54.597890 IP linux.site.nfs > 192.168.40.144.4024160263: reply ok
128 lookup [|nfs]
09:49:54.617168 IP 192.168.40.144.4024160264 > linux.site.nfs: 116
lookup [|nfs]
09:49:54.621860 IP linux.site.nfs > 192.168.40.144.4024160264: reply ok
128 lookup [|nfs]
09:49:54.623180 IP 192.168.40.144.4024160265 > linux.site.nfs: 116
lookup [|nfs]
09:49:54.637662 IP linux.site.nfs > 192.168.40.144.4024160265: reply ok
128 lookup [|nfs]
09:49:54.638776 IP 192.168.40.144.4024160266 > linux.site.nfs: 108
readlink [|nfs]
09:49:54.638900 IP linux.site.nfs > 192.168.40.144.4024160266: reply ok
48 readlink "../bin/busybox"
09:49:54.639991 IP 192.168.40.144.4024160267 > linux.site.nfs: 116
lookup [|nfs]
09:49:54.649638 IP linux.site.nfs > 192.168.40.144.4024160267: reply ok
128 lookup [|nfs]
09:49:54.650727 IP 192.168.40.144.4024160268 > linux.site.nfs: 120
lookup [|nfs]
09:49:54.663338 IP linux.site.nfs > 192.168.40.144.4024160268: reply ok
128 lookup [|nfs]
09:49:54.664753 IP 192.168.40.144.4024160269 > linux.site.nfs: 120 read
[|nfs]
09:49:54.684925 IP linux.site.nfs > 192.168.40.144.4024160269: reply ok
1472 read
09:49:54.684933 IP linux.site > 192.168.40.144: udp
......
kernel don't start:
nothing happens on the network interface!!
rpcinfo -p on server:
program vers proto port
100000 2 tcp 111 portmapper
100000 2 udp 111 portmapper
100003 2 udp 2049 nfs
100003 3 udp 2049 nfs
100227 3 udp 2049 nfs_acl
100003 2 tcp 2049 nfs
100003 3 tcp 2049 nfs
100227 3 tcp 2049 nfs_acl
100021 1 udp 32768 nlockmgr
100021 3 udp 32768 nlockmgr
100021 4 udp 32768 nlockmgr
100024 1 udp 32768 status
100021 1 tcp 32768 nlockmgr
100021 3 tcp 32768 nlockmgr
100021 4 tcp 32768 nlockmgr
100024 1 tcp 32768 status
100005 1 udp 783 mountd
100005 1 tcp 786 mountd
100005 2 udp 783 mountd
100005 2 tcp 786 mountd
100005 3 udp 783 mountd
100005 3 tcp 786 mountd
can anybody help me??
thanks!
^ permalink raw reply
* CPM uart
From: Marco Schramel @ 2005-04-14 7:26 UTC (permalink / raw)
To: PPC_LINUX
Hi,
on my target (MPC8270, 2.4.25) SCC1, SCC2 and SCC3 will work fine as ttyS0 .. ttyS2 with console at ttyS0.
It works with this code in arch/ppc/8260_io/uart.c
#define CONFIG_SERIAL_CONSOLE_PORT 0
#define SCC_NUM_BASE 0 /* SCC base tty "number" */
#define SCC_IDX_BASE 0 /* table index */
static struct serial_state rs_table[] = {
/* UART CLK PORT IRQ FLAGS NUM */
{ 0, 0, PROFF_SCC1, SIU_INT_SCC1, 0, SCC_NUM_BASE}, /* SCC1 ttyS0 */
{ 0, 0, PROFF_SCC2, SIU_INT_SCC2, 0, SCC_NUM_BASE + 1}, /* SCC2 ttyS1 */
{ 0, 0, PROFF_SCC3, SIU_INT_SCC3, 0, SCC_NUM_BASE +2}, /* SCC3 ttyS2 */
Now i need the two SMC's.
I changed the source to:
#define CONFIG_SERIAL_CONSOLE_PORT 2
#define SCC_NUM_BASE 2 /* SCC base tty "number" */
#define SCC_IDX_BASE 2 /* table index */
static struct serial_state rs_table[] = {
/* UART CLK PORT IRQ FLAGS NUM */
{ 0, 0, PROFF_SMC1, SIU_INT_SMC1, 0, 0}, /* SMC1 ttyS0 */
{ 0, 0, PROFF_SMC2, SIU_INT_SMC2, 0, 1}, /* SMC2 ttyS1 */
{ 0, 0, PROFF_SCC1, SIU_INT_SCC1, 0, SCC_NUM_BASE}, /* SCC1 ttyS2 */
{ 0, 0, PROFF_SCC2, SIU_INT_SCC2, 0, SCC_NUM_BASE + 1}, /* SCC2 ttyS3 */
{ 0, 0, PROFF_SCC3, SIU_INT_SCC3, 0, SCC_NUM_BASE + 2}, /* SCC3 ttyS4 */
and passed the bootloader the correct console=ttyS2.
During booting kernel hangs on initializing ttyS2 forever.
What could be wrong ? I only changed the io port configuration in the init function.
Thanks in advance
Marco
---------
Marco Schramel
^ permalink raw reply
* From the Desk of Mr. Paul Kadiri
From: Paul Kadiri @ 2005-04-14 2:21 UTC (permalink / raw)
To: linuxppc-embedded
>From the Desk of Mr. Paul Kadiri
Dear Sir/Madam,
My name is Paul Kadiri, I am a banker with one of the banks
in Lagos in Nigeria. I have urgent and very confidential
business proposition for you. On June 6 2002, a Zimbabwean
farmer/businessman made a numbered time(Fixed) deposited
for twelve calendar months, valued at $15,320,000.00
(Fifteen million,three hundred and twenty thousand united
states dollars-five) in my branch. Upon maturity, I sent a
routine notification to his forwarding address but got no
reply. After a month,i sent a reminder and finally we
discovered from his co-farmer who previously had a joint
account with him in my bank that he died in the land
crisis in Zimbabwe.
On further investigation, I found out that he did not
leave a WILL and all attempts to trace his next of kin
were fruitless. I therefore made further investigation and
discovered that he did not declare any next of kin in all
his official documents, including his Bank Deposit
paperwork.
This sum of US$15,320,000.00 is still sitting in the Bank
and the interest is being rolled over with the principal
sum at the end of each year. No one will come forward to
claim it. According to the Nigerian Law, at the expiration
of 5 (five) years, the money will revert to the ownership
of the Nigerian Government{STATE} if nobody applies to
claim the funds. Consequently, my proposal is that I will
like you as a foreigner to stand in as his next of kin so
that the fruits of this old man's labor will not get into
the hands of some corrupt officials. I will intimate you
with the requirements that the attorney will need to
prepare the necessary documents and affidavits, which will
put you in place as the next of kin upon your positive
response.
We shall employ the services of two attorneys for drafting
and notarization of the WILL and obtain the necessary
documents and letter of probate/administration in your
favor for the transfer. A bank Account in any part of the
world, which you provide, will then facilitate the
transfer of this money to you as the beneficiary/next of
kin. The money will be paid into your account for us to
share in the ratio of 70% for me and 30% for you, There is
no risk at all as all the paperwork for this transaction
will be done by the attorney and my position as the
Regional manager guarantees the successful execution of
this transaction. Upon your positive response,i shall let
you know who i am,the name of my bank and the name of the
deceased.I will also provide you with more details and
relevant documents that will put you in a clearer picture
of this pending transaction.
Please observe utmost confidentiality, and be rest assured
that this transaction would be most profitable for both of
us because I shall require your assistance to invest my
share in your country.
You can email me via this email
address:pakadi13@yahoo.com
Awaiting your urgent reply
Yours faithfully.
Mr. Paul Kadiri
^ permalink raw reply
* From the Desk of Mr. Paul Kadiri
From: Paul Kadiri @ 2005-04-14 2:21 UTC (permalink / raw)
To: linuxppc-dev
>From the Desk of Mr. Paul Kadiri
Dear Sir/Madam,
My name is Paul Kadiri, I am a banker with one of the banks
in Lagos in Nigeria. I have urgent and very confidential
business proposition for you. On June 6 2002, a Zimbabwean
farmer/businessman made a numbered time(Fixed) deposited
for twelve calendar months, valued at $15,320,000.00
(Fifteen million,three hundred and twenty thousand united
states dollars-five) in my branch. Upon maturity, I sent a
routine notification to his forwarding address but got no
reply. After a month,i sent a reminder and finally we
discovered from his co-farmer who previously had a joint
account with him in my bank that he died in the land
crisis in Zimbabwe.
On further investigation, I found out that he did not
leave a WILL and all attempts to trace his next of kin
were fruitless. I therefore made further investigation and
discovered that he did not declare any next of kin in all
his official documents, including his Bank Deposit
paperwork.
This sum of US$15,320,000.00 is still sitting in the Bank
and the interest is being rolled over with the principal
sum at the end of each year. No one will come forward to
claim it. According to the Nigerian Law, at the expiration
of 5 (five) years, the money will revert to the ownership
of the Nigerian Government{STATE} if nobody applies to
claim the funds. Consequently, my proposal is that I will
like you as a foreigner to stand in as his next of kin so
that the fruits of this old man's labor will not get into
the hands of some corrupt officials. I will intimate you
with the requirements that the attorney will need to
prepare the necessary documents and affidavits, which will
put you in place as the next of kin upon your positive
response.
We shall employ the services of two attorneys for drafting
and notarization of the WILL and obtain the necessary
documents and letter of probate/administration in your
favor for the transfer. A bank Account in any part of the
world, which you provide, will then facilitate the
transfer of this money to you as the beneficiary/next of
kin. The money will be paid into your account for us to
share in the ratio of 70% for me and 30% for you, There is
no risk at all as all the paperwork for this transaction
will be done by the attorney and my position as the
Regional manager guarantees the successful execution of
this transaction. Upon your positive response,i shall let
you know who i am,the name of my bank and the name of the
deceased.I will also provide you with more details and
relevant documents that will put you in a clearer picture
of this pending transaction.
Please observe utmost confidentiality, and be rest assured
that this transaction would be most profitable for both of
us because I shall require your assistance to invest my
share in your country.
You can email me via this email
address:pakadi13@yahoo.com
Awaiting your urgent reply
Yours faithfully.
Mr. Paul Kadiri
^ permalink raw reply
* Re: ELDK 3.1.1 support for x86_64 host architecture
From: Wolfgang Denk @ 2005-04-14 5:48 UTC (permalink / raw)
To: larry_chen; +Cc: linuxppc-embedded
In-Reply-To: <26F517960E0A454BAC0748B5C33D5DEA18A722@wcosmb05.cos.agilent.com>
In message <26F517960E0A454BAC0748B5C33D5DEA18A722@wcosmb05.cos.agilent.com> you wrote:
>
> I've noticed that the ELDK build and install scripts do NOT
> support x86_64 host architecture.
Which sort of host system is this (Processor(s), RAM, Linux distribution) ?
> What support for x86_64 host architecture ever attempted
> by anyone?
It works fine here on several Athlon / Opteron systems running Fedora
Core 2 and Fedora Core 3; for example:
-> cat /etc/issue
Fedora Core release 2 (Tettnang)
Kernel \r on an \m
-> uname -a
Linux pollux 2.6.10-1.770_FC2smp #1 SMP Sat Feb 26 19:46:59 EST 2005 x86_64 x86_64 x86_64 GNU/Linux
-> cat /proc/cpuinfo
processor : 0
vendor_id : AuthenticAMD
cpu family : 15
model : 5
model name : AMD Opteron(tm) Processor 246
stepping : 10
cpu MHz : 2004.596
cache size : 1024 KB
fpu : yes
fpu_exception : yes
cpuid level : 1
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 pni syscall nx mmxext lm 3dnowext 3dnow
bogomips : 3940.35
TLB size : 1088 4K pages
clflush size : 64
cache_alignment : 64
address sizes : 40 bits physical, 48 bits virtual
power management: ts fid vid ttp
processor : 1
vendor_id : AuthenticAMD
cpu family : 15
model : 5
model name : AMD Opteron(tm) Processor 246
stepping : 10
cpu MHz : 2004.596
cache size : 1024 KB
fpu : yes
fpu_exception : yes
cpuid level : 1
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 pni syscall nx mmxext lm 3dnowext 3dnow
bogomips : 4005.88
TLB size : 1088 4K pages
clflush size : 64
cache_alignment : 64
address sizes : 40 bits physical, 48 bits virtual
power management: ts fid vid ttp
-> type ppc_8xx-gcc
ppc_8xx-gcc is /opt/eldk/usr/bin/ppc_8xx-gcc
-> ppc_8xx-gcc -v
Reading specs from /opt/eldk-3.1.1/usr/bin/../lib/gcc-lib/ppc-linux/3.3.3/specs
Configured with: ../configure --prefix=/usr --mandir=/usr/share/man --infodir=/usr/share/info --enable-shared --enable-threads=posix --disable-checking --with-system-zlib --enable-__cxa_atexit --with-newlib --enable-languages=c,c++ --disable-libgcj --host=i386-redhat-linux --target=ppc-linux
Thread model: posix
gcc version 3.3.3 (DENX ELDK 3.1.1 3.3.3-9)
Best regards,
Wolfgang Denk
--
Software Engineering: Embedded and Realtime Systems, Embedded Linux
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de
Neckties strangle clear thinking. -- Lin Yutang
^ permalink raw reply
* Re: 824x Sandpoint with 2.6.x
From: Sam Song @ 2005-04-14 5:01 UTC (permalink / raw)
To: Mark A. Greer; +Cc: linuxppc-embedded
--- "Mark A. Greer" <mgreer@mvista.com> wrote:
[snip]
> No problem, Sam. Let me know if you encounter any
> problems with it.
Well, encounter one puzzle on bd_info:-)
I use 2.6.11 release package on my custom Sandpoint
board with u-boot. In 2.6.11 ppcboot.h, I noticed
that there were no CONFIG_8260 but CONFIG_CPM2,
which had a conflict with bd_info of u-boot. Does
CONFIG_CPM2 means CONFIG_8260 in 2.6.x? If so, it
seems that I should use CPM2 UART driver rather
than the one CONFIG_SERIAL_8250 which is defined by
sandpoint_defconfig. Well, CPM2 UART driver support
is off line from menuconfig:-(
I created one image only with 8250 serial and RAMDISK
support kernel. The console setting is "ttyS0,115200".
But hanged after loading the kernel... What could the
problem be?
Thanks for your kind help,
Sam
_________________________________________________________
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http://music.yisou.com/
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^ permalink raw reply
* Re: Can you suggest a small FTP utility for Linux suitable for embedded systems?
From: Donald White @ 2005-04-14 3:32 UTC (permalink / raw)
To: linuxppc-embedded
In-Reply-To: <s25d2c02.087@EMAIL>
I also used betaftpd which I got from sourceforge. I think it was only
about 30KB in size.
Don
Rupesh S wrote:
> I know 'betaftpd' is small & suitable for small systems.
>
> --
> Rupesh S
>
>
>>>>"Vijay Padiyar" <vijay_padiyar@hotmail.com> 04/13/05 02:00PM >>>
>
> Hi there
>
> I am running BusyBox 1.0 on the Linux 2.6.10 kernel on an MPC8260 target.
> Since BusyBox currently doesn't appear to provide an FTP server utility, I
> wanted to know where I can get a small FTP utility for Linux that doesn't
> take up much space and is suitable for embedded applications.
>
> Regards
>
> Vijay Padiyar
>
> http://www.vijaypadiyar.eu.tf
> _______________________________________________
> Linuxppc-embedded mailing list
> Linuxppc-embedded@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-embedded
>
> _______________________________________________
> Linuxppc-embedded mailing list
> Linuxppc-embedded@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-embedded
^ permalink raw reply
* [PATCH] ppc32: add sound support for Mac Mini
From: Benjamin Herrenschmidt @ 2005-04-14 2:14 UTC (permalink / raw)
To: Andrew Morton
Cc: linuxppc-dev list, debian-powerpc@lists.debian.org, alsa-devel
Hi !
This patch applies on top of my previous g5 related sound patches and
adds support for the Mac Mini to the PowerMac Alsa driver.
However, I haven't found any kind of HW support for volume control on
this machine. If it exist, it's well hidden. That means that you
probably want to make sure you use software with the ability to do soft
volume control, or use Alsa 0.9 pre-release with the softvol plugin.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Index: linux-work/sound/ppc/toonie.c
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ linux-work/sound/ppc/toonie.c 2005-04-14 12:13:17.000000000 +1000
@@ -0,0 +1,380 @@
+/*
+ * Mac Mini "toonie" mixer control
+ *
+ * Copyright (c) 2005 by Benjamin Herrenschmidt <benh@kernel.crashing.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include <sound/driver.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/i2c.h>
+#include <linux/i2c-dev.h>
+#include <linux/kmod.h>
+#include <linux/slab.h>
+#include <linux/interrupt.h>
+#include <sound/core.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/machdep.h>
+#include <asm/pmac_feature.h>
+#include "pmac.h"
+
+#undef DEBUG
+
+#ifdef DEBUG
+#define DBG(fmt...) printk(fmt)
+#else
+#define DBG(fmt...)
+#endif
+
+struct pmac_gpio {
+ unsigned int addr;
+ u8 active_val;
+ u8 inactive_val;
+ u8 active_state;
+};
+
+struct pmac_toonie
+{
+ struct pmac_gpio hp_detect_gpio;
+ struct pmac_gpio hp_mute_gpio;
+ struct pmac_gpio amp_mute_gpio;
+ int hp_detect_irq;
+ int auto_mute_notify;
+ struct work_struct detect_work;
+};
+
+
+/*
+ * gpio access
+ */
+#define do_gpio_write(gp, val) \
+ pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, (gp)->addr, val)
+#define do_gpio_read(gp) \
+ pmac_call_feature(PMAC_FTR_READ_GPIO, NULL, (gp)->addr, 0)
+#define tumbler_gpio_free(gp) /* NOP */
+
+static void write_audio_gpio(struct pmac_gpio *gp, int active)
+{
+ if (! gp->addr)
+ return;
+ active = active ? gp->active_val : gp->inactive_val;
+ do_gpio_write(gp, active);
+ DBG("(I) gpio %x write %d\n", gp->addr, active);
+}
+
+static int check_audio_gpio(struct pmac_gpio *gp)
+{
+ int ret;
+
+ if (! gp->addr)
+ return 0;
+
+ ret = do_gpio_read(gp);
+
+ return (ret & 0xd) == (gp->active_val & 0xd);
+}
+
+static int read_audio_gpio(struct pmac_gpio *gp)
+{
+ int ret;
+ if (! gp->addr)
+ return 0;
+ ret = ((do_gpio_read(gp) & 0x02) !=0);
+ return ret == gp->active_state;
+}
+
+
+enum { TOONIE_MUTE_HP, TOONIE_MUTE_AMP };
+
+static int toonie_get_mute_switch(snd_kcontrol_t *kcontrol,
+ snd_ctl_elem_value_t *ucontrol)
+{
+ pmac_t *chip = snd_kcontrol_chip(kcontrol);
+ struct pmac_toonie *mix = chip->mixer_data;
+ struct pmac_gpio *gp;
+
+ if (mix == NULL)
+ return -ENODEV;
+ switch(kcontrol->private_value) {
+ case TOONIE_MUTE_HP:
+ gp = &mix->hp_mute_gpio;
+ break;
+ case TOONIE_MUTE_AMP:
+ gp = &mix->amp_mute_gpio;
+ break;
+ default:
+ return -EINVAL;;
+ }
+ ucontrol->value.integer.value[0] = !check_audio_gpio(gp);
+ return 0;
+}
+
+static int toonie_put_mute_switch(snd_kcontrol_t *kcontrol,
+ snd_ctl_elem_value_t *ucontrol)
+{
+ pmac_t *chip = snd_kcontrol_chip(kcontrol);
+ struct pmac_toonie *mix = chip->mixer_data;
+ struct pmac_gpio *gp;
+ int val;
+
+ if (chip->update_automute && chip->auto_mute)
+ return 0; /* don't touch in the auto-mute mode */
+
+ if (mix == NULL)
+ return -ENODEV;
+
+ switch(kcontrol->private_value) {
+ case TOONIE_MUTE_HP:
+ gp = &mix->hp_mute_gpio;
+ break;
+ case TOONIE_MUTE_AMP:
+ gp = &mix->amp_mute_gpio;
+ break;
+ default:
+ return -EINVAL;;
+ }
+ val = ! check_audio_gpio(gp);
+ if (val != ucontrol->value.integer.value[0]) {
+ write_audio_gpio(gp, ! ucontrol->value.integer.value[0]);
+ return 1;
+ }
+ return 0;
+}
+
+static snd_kcontrol_new_t toonie_hp_sw __initdata = {
+ .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
+ .name = "Headphone Playback Switch",
+ .info = snd_pmac_boolean_mono_info,
+ .get = toonie_get_mute_switch,
+ .put = toonie_put_mute_switch,
+ .private_value = TOONIE_MUTE_HP,
+};
+static snd_kcontrol_new_t toonie_speaker_sw __initdata = {
+ .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
+ .name = "PC Speaker Playback Switch",
+ .info = snd_pmac_boolean_mono_info,
+ .get = toonie_get_mute_switch,
+ .put = toonie_put_mute_switch,
+ .private_value = TOONIE_MUTE_AMP,
+};
+
+/*
+ * auto-mute stuffs
+ */
+static int toonie_detect_headphone(pmac_t *chip)
+{
+ struct pmac_toonie *mix = chip->mixer_data;
+ int detect = 0;
+
+ if (mix->hp_detect_gpio.addr)
+ detect |= read_audio_gpio(&mix->hp_detect_gpio);
+ return detect;
+}
+
+static void toonie_check_mute(pmac_t *chip, struct pmac_gpio *gp, int val,
+ int do_notify, snd_kcontrol_t *sw)
+{
+ if (check_audio_gpio(gp) != val) {
+ write_audio_gpio(gp, val);
+ if (do_notify)
+ snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
+ &sw->id);
+ }
+}
+
+static void toonie_detect_handler(void *self)
+{
+ pmac_t *chip = (pmac_t*) self;
+ struct pmac_toonie *mix;
+ int headphone;
+
+ if (!chip)
+ return;
+
+ mix = chip->mixer_data;
+ snd_assert(mix, return);
+
+ headphone = toonie_detect_headphone(chip);
+
+ DBG("headphone: %d, lineout: %d\n", headphone, lineout);
+
+ if (headphone) {
+ /* unmute headphone/lineout & mute speaker */
+ toonie_check_mute(chip, &mix->hp_mute_gpio, 0,
+ mix->auto_mute_notify, chip->master_sw_ctl);
+ toonie_check_mute(chip, &mix->amp_mute_gpio, 1,
+ mix->auto_mute_notify, chip->speaker_sw_ctl);
+ } else {
+ /* unmute speaker, mute others */
+ toonie_check_mute(chip, &mix->amp_mute_gpio, 0,
+ mix->auto_mute_notify, chip->speaker_sw_ctl);
+ toonie_check_mute(chip, &mix->hp_mute_gpio, 1,
+ mix->auto_mute_notify, chip->master_sw_ctl);
+ }
+ if (mix->auto_mute_notify) {
+ snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
+ &chip->hp_detect_ctl->id);
+ }
+}
+
+static void toonie_update_automute(pmac_t *chip, int do_notify)
+{
+ if (chip->auto_mute) {
+ struct pmac_toonie *mix;
+ mix = chip->mixer_data;
+ snd_assert(mix, return);
+ mix->auto_mute_notify = do_notify;
+ schedule_work(&mix->detect_work);
+ }
+}
+
+/* interrupt - headphone plug changed */
+static irqreturn_t toonie_hp_intr(int irq, void *devid, struct pt_regs *regs)
+{
+ pmac_t *chip = devid;
+
+ if (chip->update_automute && chip->initialized) {
+ chip->update_automute(chip, 1);
+ return IRQ_HANDLED;
+ }
+ return IRQ_NONE;
+}
+
+/* look for audio gpio device */
+static int find_audio_gpio(const char *name, const char *platform,
+ struct pmac_gpio *gp)
+{
+ struct device_node *np;
+ u32 *base, addr;
+
+ if (! (np = find_devices("gpio")))
+ return -ENODEV;
+
+ for (np = np->child; np; np = np->sibling) {
+ char *property = get_property(np, "audio-gpio", NULL);
+ if (property && strcmp(property, name) == 0)
+ break;
+ if (device_is_compatible(np, name))
+ break;
+ }
+ if (np == NULL)
+ return -ENODEV;
+
+ base = (u32 *)get_property(np, "AAPL,address", NULL);
+ if (! base) {
+ base = (u32 *)get_property(np, "reg", NULL);
+ if (!base) {
+ DBG("(E) cannot find address for device %s !\n", device);
+ snd_printd("cannot find address for device %s\n", device);
+ return -ENODEV;
+ }
+ addr = *base;
+ if (addr < 0x50)
+ addr += 0x50;
+ } else
+ addr = *base;
+
+ gp->addr = addr & 0x0000ffff;
+
+ /* Try to find the active state, default to 0 ! */
+ base = (u32 *)get_property(np, "audio-gpio-active-state", NULL);
+ if (base) {
+ gp->active_state = *base;
+ gp->active_val = (*base) ? 0x5 : 0x4;
+ gp->inactive_val = (*base) ? 0x4 : 0x5;
+ } else {
+ u32 *prop = NULL;
+ gp->active_state = 0;
+ gp->active_val = 0x4;
+ gp->inactive_val = 0x5;
+ /* Here are some crude hacks to extract the GPIO polarity and
+ * open collector informations out of the do-platform script
+ * as we don't yet have an interpreter for these things
+ */
+ if (platform)
+ prop = (u32 *)get_property(np, platform, NULL);
+ if (prop) {
+ if (prop[3] == 0x9 && prop[4] == 0x9) {
+ gp->active_val = 0xd;
+ gp->inactive_val = 0xc;
+ }
+ if (prop[3] == 0x1 && prop[4] == 0x1) {
+ gp->active_val = 0x5;
+ gp->inactive_val = 0x4;
+ }
+ }
+ }
+
+ DBG("(I) GPIO device %s found, offset: %x, active state: %d !\n",
+ device, gp->addr, gp->active_state);
+
+ return (np->n_intrs > 0) ? np->intrs[0].line : 0;
+}
+
+static void toonie_cleanup(pmac_t *chip)
+{
+ struct pmac_toonie *mix = chip->mixer_data;
+ if (! mix)
+ return;
+ if (mix->hp_detect_irq >= 0)
+ free_irq(mix->hp_detect_irq, chip);
+ kfree(mix);
+ chip->mixer_data = NULL;
+}
+
+int snd_pmac_toonie_init(pmac_t *chip)
+{
+ struct pmac_toonie *mix;
+
+ mix = kmalloc(sizeof(*mix), GFP_KERNEL);
+ if (! mix)
+ return -ENOMEM;
+
+ chip->mixer_data = mix;
+ chip->mixer_free = toonie_cleanup;
+
+ find_audio_gpio("headphone-mute", NULL, &mix->hp_mute_gpio);
+ find_audio_gpio("amp-mute", NULL, &mix->amp_mute_gpio);
+ mix->hp_detect_irq = find_audio_gpio("headphone-detect",
+ NULL, &mix->hp_detect_gpio);
+
+ strcpy(chip->card->mixername, "PowerMac Toonie");
+
+ chip->master_sw_ctl = snd_ctl_new1(&toonie_hp_sw, chip);
+ snd_ctl_add(chip->card, chip->master_sw_ctl);
+
+ chip->speaker_sw_ctl = snd_ctl_new1(&toonie_speaker_sw, chip);
+ snd_ctl_add(chip->card, chip->speaker_sw_ctl);
+
+ INIT_WORK(&mix->detect_work, toonie_detect_handler, (void *)chip);
+
+ if (mix->hp_detect_irq >= 0) {
+ snd_pmac_add_automute(chip);
+
+ chip->detect_headphone = toonie_detect_headphone;
+ chip->update_automute = toonie_update_automute;
+ toonie_update_automute(chip, 0);
+
+ if (request_irq(mix->hp_detect_irq, toonie_hp_intr, 0,
+ "Sound Headphone Detection", chip) < 0)
+ mix->hp_detect_irq = -1;
+ }
+
+ return 0;
+}
+
Index: linux-work/sound/ppc/Makefile
===================================================================
--- linux-work.orig/sound/ppc/Makefile 2005-03-15 12:00:38.000000000 +1100
+++ linux-work/sound/ppc/Makefile 2005-04-14 11:15:38.000000000 +1000
@@ -3,7 +3,7 @@
# Copyright (c) 2001 by Jaroslav Kysela <perex@suse.cz>
#
-snd-powermac-objs := powermac.o pmac.o awacs.o burgundy.o daca.o tumbler.o keywest.o beep.o
+snd-powermac-objs := powermac.o pmac.o awacs.o burgundy.o daca.o tumbler.o toonie.o keywest.o beep.o
# Toplevel Module Dependency
obj-$(CONFIG_SND_POWERMAC) += snd-powermac.o
Index: linux-work/sound/ppc/pmac.c
===================================================================
--- linux-work.orig/sound/ppc/pmac.c 2005-04-12 18:07:50.000000000 +1000
+++ linux-work/sound/ppc/pmac.c 2005-04-14 11:16:33.000000000 +1000
@@ -986,7 +986,13 @@
chip->num_freqs = ARRAY_SIZE(tumbler_freqs);
chip->model = PMAC_SNAPPER;
chip->can_byte_swap = 0; /* FIXME: check this */
- chip->control_mask = MASK_IEPC | 0x11; /* disable IEE */
+ chip->control_mask = MASK_IEPC | 0x11;/* disable IEE */
+ break;
+ case 0x3a:
+ chip->num_freqs = ARRAY_SIZE(tumbler_freqs);
+ chip->model = PMAC_TOONIE;
+ chip->can_byte_swap = 0; /* FIXME: check this */
+ chip->control_mask = MASK_IEPC | 0x11;/* disable IEE */
break;
}
}
Index: linux-work/sound/ppc/pmac.h
===================================================================
--- linux-work.orig/sound/ppc/pmac.h 2005-04-12 18:07:50.000000000 +1000
+++ linux-work/sound/ppc/pmac.h 2005-04-14 11:19:06.000000000 +1000
@@ -94,7 +94,8 @@
*/
enum snd_pmac_model {
- PMAC_AWACS, PMAC_SCREAMER, PMAC_BURGUNDY, PMAC_DACA, PMAC_TUMBLER, PMAC_SNAPPER
+ PMAC_AWACS, PMAC_SCREAMER, PMAC_BURGUNDY, PMAC_DACA, PMAC_TUMBLER,
+ PMAC_SNAPPER, PMAC_TOONIE
};
struct snd_pmac {
@@ -191,6 +192,7 @@
int snd_pmac_daca_init(pmac_t *chip);
int snd_pmac_tumbler_init(pmac_t *chip);
int snd_pmac_tumbler_post_init(void);
+int snd_pmac_toonie_init(pmac_t *chip);
/* i2c functions */
typedef struct snd_pmac_keywest {
Index: linux-work/sound/ppc/powermac.c
===================================================================
--- linux-work.orig/sound/ppc/powermac.c 2005-03-15 12:00:38.000000000 +1100
+++ linux-work/sound/ppc/powermac.c 2005-04-14 11:18:49.000000000 +1000
@@ -95,6 +95,13 @@
if ( snd_pmac_tumbler_init(chip) < 0 || snd_pmac_tumbler_post_init() < 0)
goto __error;
break;
+ case PMAC_TOONIE:
+ strcpy(card->driver, "PMac Toonie");
+ strcpy(card->shortname, "PowerMac Toonie");
+ strcpy(card->longname, card->shortname);
+ if ((err = snd_pmac_toonie_init(chip)) < 0)
+ goto __error;
+ break;
case PMAC_AWACS:
case PMAC_SCREAMER:
name_ext = chip->model == PMAC_SCREAMER ? "Screamer" : "AWACS";
^ permalink raw reply
* [RFC] attempt to remove misc-embedded.c
From: Marcelo Tosatti @ 2005-04-13 19:57 UTC (permalink / raw)
To: Tom Rini, linux-ppc-embedded
Hi Tom,
This is an attempt to move remove misc-embedded.c by moving its quirks to
misc.c.
It needs further fixing and cleaning, for sure.
Are there any major disagreements about the change?
Might need to define a bd_t structure for all ppc's?
PS: it crashes right after
loaded at: 00002120 00C8744C
relocated to: 00400020 0108534C
board data at: 01083130 0108334C
relocated to: 0040522C 00405448
zimage at: 00405D49 0050E525
initrd at: 0050F000 01082C6E
avail ram: 01086000 08000000
Linux/PPC load: root=/dev/ram rw
Uncompressing Linux...
done.
Now booting the kernel
BDI>i
Target state : debug mode
Debug entry cause : machine check interrupt
Current PC : 0x00001280
Data address : 0x24702000
DSISR value : 0x0000014a
BDI>
but shouldnt be a major thing (I haven't figured what it is).
--- /mnt/test1/tslinux_mv21-CVS/linux-2.6/arch/ppc/boot/simple/misc.c 2005-03-17 15:56:59.000000000 -0300
+++ misc.c 2005-04-13 17:57:36.000000000 -0300
@@ -25,7 +25,10 @@
#include <asm/bootinfo.h>
#ifdef CONFIG_44x
#include <asm/ibm4xx.h>
+#elif CONFIG_8xx
+#include <asm/mpc8xx.h>
#endif
+
#include <asm/reg.h>
#include "nonstdio.h"
@@ -54,6 +57,16 @@
|| defined(CONFIG_SERIAL_MPSC_CONSOLE)) \
&& !defined(CONFIG_GEMINI)
#define INTERACTIVE_CONSOLE 1
+
+
+
+#ifdef CONFIG_EMBEDDEDBOOT
+/* We need to make sure that this is before the images to ensure
+ * that it's in a mapped location. - Tom */
+bd_t hold_resid_buf __attribute__ ((__section__ (".data.boot")));
+bd_t *hold_residual = &hold_resid_buf;
+char ramroot_string[] = "root=/dev/ram rw";
+char netroot_string[] = "root=/dev/nfs rw ip=on";
#endif
char *avail_ram;
@@ -88,8 +101,16 @@
return 0;
}
+/* Weak function for boards which don't need to build the
+ * board info struct because they are using PPCBoot/U-Boot.
+ */
+void __attribute__ ((weak))
+embed_config(bd_t **bdp)
+{
+}
+
struct bi_record *
-decompress_kernel(unsigned long load_addr, int num_words, unsigned long cksum)
+decompress_kernel(unsigned long load_addr, int num_words, unsigned long cksum, bd_t *bp)
{
#ifdef INTERACTIVE_CONSOLE
int timer = 0;
@@ -99,8 +120,9 @@
struct bi_record *rec;
unsigned long initrd_loc = 0, TotalMemory = 0;
-#if defined(CONFIG_SERIAL_8250_CONSOLE) || defined(CONFIG_SERIAL_MPSC_CONSOLE)
- com_port = serial_init(0, NULL);
+ embed_config(&bp);
+#if defined(CONFIG_SERIAL_CONSOLE) || defined(CONFIG_SERIAL_MPSC_CONSOLE)
+ com_port = serial_init(0, bp);
#endif
#if defined(CONFIG_44x) && defined(PPC44x_EMAC0_MR0)
@@ -112,6 +134,18 @@
*(volatile unsigned long *)PPC44x_EMAC0_MR0 = 0x20000000;
__asm__ __volatile__("eieio");
#endif
+#ifdef CONFIG_MBX
+ /* Because of the way the MBX loads the ELF image, we can't
+ * tell where we started. We read a magic variable from the NVRAM
+ * that gives us the intermediate buffer load address.
+ */
+ load_addr = *(uint *)0xfa000020;
+ load_addr += 0x10000; /* Skip ELF header */
+#endif
+#ifdef CONFIG_EMBEDDEDBOOT
+ if (bp)
+ memcpy(hold_residual,bp,sizeof(bd_t));
+#endif
/*
* Call get_mem_size(), which is memory controller dependent,
@@ -119,8 +153,15 @@
*/
TotalMemory = get_mem_size();
+#ifdef CONFIG_EMBEDDEDBOOT
+ /* Set end of memory available to us. It is always the highest
+ * memory address provided by the board information.
+ */
+ end_avail = (char *)(bp->bi_memsize);
+#else
/* assume the chunk below 8M is free */
end_avail = (char *)0x00800000;
+#endif
/*
* Reveal where we were loaded at and where we
@@ -136,6 +177,16 @@
puthex((unsigned long)((unsigned long)&start + (4*num_words)));
puts("\n");
}
+ if (bp) {
+ puts("board data at: "); puthex((unsigned long)bp);
+ puts(" ");
+ puthex((unsigned long)((unsigned long)bp + sizeof(bd_t)));
+ puts("\nrelocated to: ");
+ puthex((unsigned long)hold_residual);
+ puts(" ");
+ puthex((unsigned long)((unsigned long)hold_residual + sizeof(bd_t)));
+ puts("\n");
+ }
/*
* We link ourself to 0x00800000. When we run, we relocate
@@ -163,9 +214,10 @@
puthex((unsigned long)(&__ramdisk_begin));
puts(" "); puthex((unsigned long)(&__ramdisk_end));puts("\n");
}
-
+#ifndef CONFIG_EMBEDDEDBOOT
avail_ram = (char *)0x00400000;
end_avail = (char *)0x00800000;
+#endif
puts("avail ram: "); puthex((unsigned long)avail_ram); puts(" ");
puthex((unsigned long)end_avail); puts("\n");
@@ -181,11 +233,17 @@
if ( (cmd_line[0] == '\0') && (cmd_preset[0] != '\0'))
memcpy (cmd_line, cmd_preset, sizeof(cmd_preset));
#endif
+#ifdef CONFIG_EMBEDDEDBOOT
+ if ( initrd_size )
+ memcpy (cmd_line, ramroot_string, sizeof(ramroot_string));
+ else
+ memcpy (cmd_line, netroot_string, sizeof(netroot_string));
+#endif
/* Display standard Linux/PPC boot prompt for kernel args */
puts("\nLinux/PPC load: ");
cp = cmd_line;
- memcpy (cmd_line, cmd_preset, sizeof(cmd_preset));
+// memcpy (cmd_line, cmd_preset, sizeof(cmd_preset));
while ( *cp ) putc(*cp++);
#ifdef INTERACTIVE_CONSOLE
@@ -224,6 +282,7 @@
puts("Uncompressing Linux...");
gunzip(0x0, 0x400000, zimage_start, &zimage_size);
puts("done.\n");
+ flush_instruction_cache();
/* get the bi_rec address */
rec = bootinfo_addr(zimage_size);
@@ -280,5 +339,5 @@
void *ign1, void *ign2)
{
board_isa_init();
- return decompress_kernel(load_addr, num_words, cksum);
+ return decompress_kernel(load_addr, num_words, cksum, ign1);
}
^ permalink raw reply
* ELDK 3.1.1 support for x86_64 host architecture
From: larry_chen @ 2005-04-13 22:35 UTC (permalink / raw)
To: linuxppc-embedded
I've noticed that the ELDK build and install scripts do NOT
support x86_64 host architecture.
What support for x86_64 host architecture ever attempted
by anyone?
Thanks in advance.
Regards,
Larry
^ permalink raw reply
* Re: Sound drivers for newer machines: need help
From: Eddy Petrisor @ 2005-04-13 22:09 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev list, debian-powerpc@lists.debian.org
In-Reply-To: <1113006674.9568.414.camel@gaston>
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset=x-user-defined; format=flowed, Size: 896 bytes --]
Benjamin Herrenschmidt wrote:
> Hi !
>
> If you have a newer machine, that is a machine released on or after
> 2002, can you please send me the output of:
>
> echo `cat /proc/device-tree/model`
PowerBook5,2
>
> and
>
> for i in `find /proc/device-tree -name layout-id -print`; do echo $i && hexdump -n4 $i; done
>
Nothing
> If the later returns nothing, it's fine, just tell me.
>
> I'm especially interested in the various models of G5 based machines. It
> seems apple is having all sorts of very different sound HW setups on
> those machines, and I'm trying to figure out exactly what is where based
> on those infos and the darwin sources.
>
> Ben.
>
>
>
I am not sure if my Powerbook was released after 2002, but the date(the
copyright stuff) on the back is 2003.
--
Regards,
EddyP
===========================
I had a favourite quote, but I forgot it. And it was insightful.
^ permalink raw reply
* Re: Help needed Linux-2.6 - MPC8541
From: Andy Fleming @ 2005-04-13 22:01 UTC (permalink / raw)
To: Junita Ajith; +Cc: ari, linuxppc-embedded
In-Reply-To: <20050413205839.71410.qmail@web53702.mail.yahoo.com>
Hi Junita,
We encountered a similar error when bringing up 83xx support, and it =20
was due to the platform code not properly passing in the register space =20=
of the TSEC driver. The graceful stop check is the first point in the =20=
driver that the registers actually have to contain sane data (the =20
driver stops the controller before doing anything with the registers), =20=
so it would make sense that, if the address for the registers were =20
wrong, this spot would get stuck. Investigate the platform init code, =20=
is my suggestion.
Andy
On Apr 13, 2005, at 15:58, Junita Ajith wrote:
> Hello Clement Koller,
> =A0=A0=A0 =A0 Thanks for your response.
> =A0
> We have both Marvel & Intel's phy in our 8541 board.
> =A0
> As of now in the kernel we have just enabled support for Marvel's PHY.
> =A0
> It doesnt even=A0 come to the point of detecting=A0 the PHY ID =20
> (88E1011S). It just reads the PHy Address(Board specific)=A0correclty.
> =A0
> Even before it gets into gianfar_phy.c it hangs at gianfar.c.
> =A0
> This is the screen dump.
> ---------------------------------------
> =A0
> =A0
> Board: PCI-G8500 [PowerQUICC III]
> =A0=A0=A0=A0=A0=A0=A0 CPU: 825 MHz
> =A0=A0=A0=A0=A0=A0=A0 CCB: 330 MHz
> =A0=A0=A0=A0=A0=A0=A0 DDR: 165 MHz
> =A0=A0=A0=A0=A0=A0=A0 LBC: 82 MHz
> L1 D-cache 32KB, L1 I-cache 32KB enabled.
> I2C:=A0=A0 ready
> DRAM:=A0 256 MB
> RMCG8400 in PCI Host Mode.
> RMCG8400 is the PCI Arbiter.
> FLASH:=A0 8 MB
> L2 cache enabled: 256KB
> In:=A0=A0=A0 serial
> Out:=A0=A0 serial
> Err:=A0=A0 serial
> Net:=A0=A0 MOTO ENET0: PHY is Marvell 88E1011S (1410c67)
> MOTO ENET2: PHY is Intel LXT971A (1378e2)
> MOTO ENET0, MOTO ENET2
> Hit any key to stop autoboot:=A0 0
> RMCG8500#>tftp 2000000 8541/vmlinux.img
> Speed: 1000, full duplex
> Using MOTO ENET0 device
> TFTP from server 192.168.201.11; our IP address is 192.168.201.191
> Filename '8541/vmlinux.img'.
> Load address: 0x2000000
> Loading: =20
> #################################################################
> =A0=A0=A0=A0=A0=A0=A0=A0 =20
> #################################################################
> =A0=A0=A0=A0=A0=A0=A0=A0 ###########################################
> done
> Bytes transferred =3D 883219 (d7a13 hex)
> RMCG8500#>tftp 3000000 8541/ramdisk.image-8541.hdr
> Speed: 1000, full duplex
> Using MOTO ENET0 device
> TFTP from server 192.168.201.11; our IP address is 192.168.201.191
> Filename '8541/ramdisk.image-8541.hdr'.
> Load address: 0x3000000
> Loading: =20
> #################################################################
> =A0=A0=A0=A0=A0=A0=A0=A0 =20
> #################################################################
> =A0=A0=A0=A0=A0=A0=A0=A0 =20
> #################################################################
> =A0=A0=A0=A0=A0=A0=A0=A0 =20
> #################################################################
> =A0=A0=A0=A0=A0=A0=A0=A0 =20
> #################################################################
> =A0=A0=A0=A0=A0=A0=A0=A0 =20
> #################################################################
> =A0=A0=A0=A0=A0=A0=A0=A0 =20
> #################################################################
> =A0=A0=A0=A0=A0=A0=A0=A0 =20
> #################################################################
> =A0=A0=A0=A0=A0=A0=A0=A0 ##################
> done
> Bytes transferred =3D 2751871 (29fd7f hex)
> RMCG8500#>bootm 2000000 3000000
> ## Booting image at 02000000 ...
> =A0=A0 Image Name:=A0=A0 PCIG8400-Rel-1.1
> =A0=A0 Image Type:=A0=A0 PowerPC Linux Kernel Image (gzip compressed)
> =A0=A0 Data Size:=A0=A0=A0 883155 Bytes =3D 862.5 kB
> =A0=A0 Load Address: 00000000
> =A0=A0 Entry Point:=A0 00000000
> =A0=A0 Verifying Checksum ... OK
> =A0=A0 Uncompressing Kernel Image ... OK
> ## Loading RAMDisk Image at 03000000 ...
> =A0=A0 Image Name:=A0=A0 PCIG8400
> =A0=A0 Image Type:=A0=A0 PowerPC Linux RAMDisk Image (gzip compressed)
> =A0=A0 Data Size:=A0=A0=A0 2751807 Bytes =3D=A0 2.6 MB
> =A0=A0 Load Address: 00000000
> =A0=A0 Entry Point:=A0 00000000
> =A0=A0 Verifying Checksum ... OK
> =A0=A0 Loading Ramdisk to 0fd12000, end 0ffb1d3f ... OK
> Memory CAM mapping: CAM0=3D256Mb, CAM1=3D0Mb, CAM2=3D0Mb residual: 0Mb
> Linux version 2.6.11 (pari@sjswsvr11) (gcc version 3.3.2) #16 Tue Apr =20=
> 5 11:19:57
> =A0PDT 2005
> Built 1 zonelists
> Kernel command line: console=3DttyS0,115200 root=3D/dev/ram rw doPci=3D1=
> OpenPIC Version 1.2 (1 CPUs and 44 IRQ sources) at fcfbb000
> PID hash table entries: 2048 (order: ! 11, 32768 bytes)
> Console: colour dummy device 80x25
> Dentry cache hash table entries: 65536 (order: 6, 262144 bytes)
> Inode-cache hash table entries: 32768 (order: 5, 131072 bytes)
> Memory: 254720k available (1252k kernel code, 444k data, 292k init, 0k =
=20
> highmem)
> Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
> checking if image is initramfs...it isn't (no cpio magic); looks like =20=
> an initrd
> Freeing initrd memory: 2687k freed
> NET: Registered protocol family 16
> PCI: Probing PCI hardware
> devfs: 2004-01-31 Richard Gooch (rgooch@atnf.csiro.au)
> devfs: boot_options: 0x0
> Serial: 8250/16550 driver $Revision: 1.90 $ 1 ports, IRQ sharing =20
> enabled
> ttyS0 at MMIO 0xfdf04500 (irq =3D 90) is a 16550A
> io scheduler noop registered inside elv_register()
> RAMDISK driver initialized: 16 RAM disks of 32768K size 1024 blocksize
> Inside gfar_probe() of gianfar.c
> *************************************
> Inside alloc_etherdev() for eth-1072721460
> PHY base Addr is 0xd1002000
> Before DMA engine stop for IEVENT
> value of DMACTRL reg before writing to it : 0x0
> value to be written to DMACTRL reg : 0x18
> value of DMACTRL reg after writing to it=A0 : 0x80000000
> value of IEVENT reg : 0x80000000
> =
***********************************************************************=20=
> ****
> =A0
> And after this it just gets into the loop where it looks if the =20
> 'Gracious receive and Gracious stop' bits of the IEVENT register are =20=
> set.
> In our case it doesnt get set and so the kernel hangs at that point.
> =A0
> Thanks
> Junita
>
> Clemens Koller <clemens.koller@anagramm.de> wrote:
> Hi, Junita!
>
> What PHYs do you use on the 8541?
> Check if they are supported in gianfar_phy or if they
> can be used with Generic MII
> Check if you get the the phy_id is correct.
> Some more debug-output would be nice.
>
> I had to add Intel LXT971 support to the gianfar_phy
> for my platform which is a 100MBit MII PHY only.
>
> Clemens Koller
> _______________________________
> R&D Imaging Devices
> Anagramm GmbH
> Rupert-Mayer-Str. 45/1
> 81379 Muenchen
> Germany
>
> http://www.anagramm.de
> Phone: +49-89-741518-50
> Fax: +49-89-741518-19
>
> Junita Ajith wrote:
> > Andy
> >
> > 1. The code hangs exaclty at the point where it looks for the =20
> 'graceful transmit/receive' bits set in the IEVENT register. =20
> (IEVENT_GRSC , IEVENT_GTSC) .
> > File - (linux-2.6/drivers/net/gianfar.c)
> > Function - static int gfar_probe(struct d! evice *device) ;
> >
> > In that ,we write Graceful Receive Stop and Graceful Transmit Stop, =20=
> and then wait until the corresponding bits in IEVENT indicate the =20
> stops have completed.
> >
> > This never happens and hence hangs at the 'while' loop inside that =20=
> function.
> >
> > 2. We are using Linux-2.6.11
> >
> > Here's the serial output dump with a few debug messages.
> >
> > ## Booting image at 02000000 ...
> > Image Name: PCIG8400-Rel-1.1
> > Image Type: PowerPC Linux Kernel Image (gzip compressed)
> > Data Size: 883221 Bytes =3D 862.5 kB
> > Load Address: 00000000
> > Entry Point: 00000000
> > Verifying Checksum ... OK
> > Uncompressing Kernel Image ... OK
> > ## Loading RAMDisk Image at 03000000 ...
> > Image Name: PCIG8400
> > Image Type: PowerPC Linux RAMDisk Image (gzip compressed)
> > Data Size: 2751807 Bytes =3D 2.6 MB
> > Load Address: 00000000
> > Entry Point: 00000000
> > Ve! rifying Checksum ... OK
> > Loading Ramdisk to 0fd12000, end 0ffb1d3f ... OK
> > Memory CAM mapping: CAM0=3D256Mb, CAM1=3D0Mb, CAM2=3D0Mb residual: =
0Mb
> > Linux version 2.6.11 (pari@sjswsvr11) (gcc version 3.3.2) #16 Tue =20=
> Apr 5 11:19:57
> > PDT 2005
> > Built 1 zonelists
> > Kernel command line: console=3DttyS0,115200 root=3D/dev/ram rw =
doPci=3D1
> > OpenPIC Version 1.2 (1 CPUs and 44 IRQ sources) at fcfbb000
> > PID hash table entries: 2048 (order: 11, 32768 bytes)
> > Console: colour dummy device 80x25
> > Dentry cache hash table entries: 65536 (order: 6, 262144 bytes)
> > Inode-cache hash table entries: 32768 (order: 5, 131072 bytes)
> > Memory: 254720k available (1252k kernel code, 444k data, 292k init, =20=
> 0k highmem)
> > Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
> > checking if image is initramfs...it isn't (no cpio magic); looks =20
> like an initrd
> > Freeing initrd memory: 2687k freed
> > NET: Registered protocol ! family 16
> > PCI: Probing PCI hardware
> > devfs: 2004-01-31 Richard Gooch (rgooch@atnf.csiro.au)
> > devfs: boot_options: 0x0
> > Serial: 8250/16550 driver $Revision: 1.90 $ 1 ports, IRQ sharing =20
> enabled
> > ttyS0 at MMIO 0xfdf04500 (irq =3D 90) is a 16550A
> > io scheduler noop registered inside elv_register()
> > RAMDISK driver initialized: 16 RAM disks of 32768K size 1024 =20
> blocksize
> > Inside gfar_probe()
> > einfo Phy ID 7
> > gfar 1: additional data!
> > Inside alloc_etherdev() for eth-1072721560
> > start e0024000
> > Resetting MAC........
> > --2--MACCFG1 is 0x80000000
> > MACCFG2 is 0x 0
> > -2- tempval 000000db
> > -3- tempval 00000000
> > -4-1- tempval 00000000
> > -4-2- tempval 00000000
> > -4-2-a tempval 00000000
> > -4-3 tempval 00000000
> > -4-4 tempval 00000000
> > Before loop -5- after writing to IEVENT tempval
> > -5- after writing to IEVENT tempval 80000000
> > -5- ! after writing to IEVENT tempval 80000000
> > -5- after writing to IEVENT tempval 80000000
> > -5- after writing to IEVENT tempval 80000000
> > -5- after writing to IEVENT tempval 80000000
> > -5- after writing to IEVENT tempval 80000000
> > -5- after writing to IEVENT tempval 80000000
> >
> >
> >
> > thanks,
> > Junita
> > Andy Fleming wrote:
> >
> > Could you send me what the kernel prints up to the point of the =
hang?
> >
> > Also, what version of 2.6 are you using? The board interface for the
> > driver changed recently to support the new driver model.
> >
> > Andy
> >
> > On Apr 12, 2005, at 12:38, Junita Ajith wrote:
> >
> >
> >>Hi
> >>We are trying to port Linux-2.6 for our custom
> >>MPC8541 board.
> >>
> >>We have a TSEC and an FEC in the board.
> >>
> >>With the "Networking Support" disabled in the Kernel,
> >>the board boots up fine and gets to the prompt.
> >>
> >>But with the "Networking Support" enabled in the
> >>kernel the board hangs where it identifies the PHY,
> >>inspite of giving the corrct PHY ID.
> >>
> >>
> >>Any help is greatly appreciated.
> >>
> >>PS:
> >>We have linux-2.4 ported for the same board and so
> >>taking that as reference trying to port Linux-2.6 ,
> >>but havent succeeded yet.
> >>
> >>Thanks
> >>Junita
> >>
> >>
> >>
> >>__________________________________
> >>Do you Yahoo!?
> >>Make Yahoo! your home page
> >>http://www.yahoo.com/r/hs
> >>_______________________________________________
> >>Linuxppc-embedded mailing list
> >>Linuxppc-embedded@ozlabs.org
> >>https://ozlabs.org/mailman/listinfo/linuxppc-embedded
> >>
> >
> >
> >
> &g! t;
> >
> > ---------------------------------
> > Do you Yahoo!?
> > Yahoo! Small Business - Try our new resources site!
> >
> >
> > =20
> =
-----------------------------------------------------------------------=20=
> -
> >
> > _______________________________________________
> > Linuxppc-embedded mailing list
> > Linuxppc-embedded@ozlabs.org
> > https://ozlabs.org/mailman/listinfo/linuxppc-embedded
>
> __________________________________________________
> Do You Yahoo!?
> Tired of spam? Yahoo! Mail has the best spam protection around
> http://mail.yahoo.com
> _______________________________________________
> Linuxppc-embedded mailing list
> Linuxppc-embedded@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-embedded
^ permalink raw reply
* Re: Error enabling CONFIG_PPC4XX_DMA in lk2.4.27-pre3?
From: Roger Larsson @ 2005-04-13 20:50 UTC (permalink / raw)
To: linuxppc-embedded
In-Reply-To: <0007F077BB3476449151699150E8FEA21A7B92@exchange.tsi-telsys.com>
On Friday 08 April 2005 22.19, Sanjay Bajaj wrote:
> Hi! Gurus,
>
> I tried to enable DMA in lk2.4.27-pre3 and it fails with the error attached
> to the end of the mail. On further debugging, I found that though
> CONFIG_PPC4XX_DMA is included in the .config but the asm/ppc4xx_dma.h
> includes CONFIG_PPC4XX_EDMA, which includes all the constants reported
> undeclared in the error message. Out of curiosity, changed .._EDMA to
> .._DMA in asm/ppc4xx_dma.h and still had errors. Any help is appreciated.
>
Hmm...
What processor are you using?
If I remember correctly 405GPr did not enable CONFIG_PPC4XX_EDMA
but 405GP did... yepp, this check in 'arch/ppc/config.in' checks for 405GP
but not 405GPr
bool 'PPC4xx DMA controller support' CONFIG_PPC4xx_DMA
if [ "$CONFIG_PPC4xx_DMA" = "y" ]; then
if [ "$CONFIG_405GP" = "y" -o "$CONFIG_NP405L" = "y" \
-o "$CONFIG_NP405H" = "y" -o "$CONFIG_NP405GS" = "y" \
-o "$CONFIG_440" = "y" -o "$CONFIG_405LP" = "y" \
-o "$CONFIG_405EP" = "y" ]; then
define_bool CONFIG_PPC4xx_EDMA y
fi
if [ "$CONFIG_STB03xxx" = "y" ]; then
define_bool CONFIG_STBXXX_DMA y
fi
fi
^ permalink raw reply
* Re: Help needed Linux-2.6 - MPC8541
From: Junita Ajith @ 2005-04-13 20:58 UTC (permalink / raw)
To: Clemens Koller, linuxppc-embedded, ari
In-Reply-To: <425CDCD1.3040302@anagramm.de>
[-- Attachment #1: Type: text/plain, Size: 10154 bytes --]
Hello Clement Koller,
Thanks for your response.
We have both Marvel & Intel's phy in our 8541 board.
As of now in the kernel we have just enabled support for Marvel's PHY.
It doesnt even come to the point of detecting the PHY ID (88E1011S). It just reads the PHy Address(Board specific) correclty.
Even before it gets into gianfar_phy.c it hangs at gianfar.c.
This is the screen dump.
---------------------------------------
Board: PCI-G8500 [PowerQUICC III]
CPU: 825 MHz
CCB: 330 MHz
DDR: 165 MHz
LBC: 82 MHz
L1 D-cache 32KB, L1 I-cache 32KB enabled.
I2C: ready
DRAM: 256 MB
RMCG8400 in PCI Host Mode.
RMCG8400 is the PCI Arbiter.
FLASH: 8 MB
L2 cache enabled: 256KB
In: serial
Out: serial
Err: serial
Net: MOTO ENET0: PHY is Marvell 88E1011S (1410c67)
MOTO ENET2: PHY is Intel LXT971A (1378e2)
MOTO ENET0, MOTO ENET2
Hit any key to stop autoboot: 0
RMCG8500#>tftp 2000000 8541/vmlinux.img
Speed: 1000, full duplex
Using MOTO ENET0 device
TFTP from server 192.168.201.11; our IP address is 192.168.201.191
Filename '8541/vmlinux.img'.
Load address: 0x2000000
Loading: #################################################################
#################################################################
###########################################
done
Bytes transferred = 883219 (d7a13 hex)
RMCG8500#>tftp 3000000 8541/ramdisk.image-8541.hdr
Speed: 1000, full duplex
Using MOTO ENET0 device
TFTP from server 192.168.201.11; our IP address is 192.168.201.191
Filename '8541/ramdisk.image-8541.hdr'.
Load address: 0x3000000
Loading: #################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
##################
done
Bytes transferred = 2751871 (29fd7f hex)
RMCG8500#>bootm 2000000 3000000
## Booting image at 02000000 ...
Image Name: PCIG8400-Rel-1.1
Image Type: PowerPC Linux Kernel Image (gzip compressed)
Data Size: 883155 Bytes = 862.5 kB
Load Address: 00000000
Entry Point: 00000000
Verifying Checksum ... OK
Uncompressing Kernel Image ... OK
## Loading RAMDisk Image at 03000000 ...
Image Name: PCIG8400
Image Type: PowerPC Linux RAMDisk Image (gzip compressed)
Data Size: 2751807 Bytes = 2.6 MB
Load Address: 00000000
Entry Point: 00000000
Verifying Checksum ... OK
Loading Ramdisk to 0fd12000, end 0ffb1d3f ... OK
Memory CAM mapping: CAM0=256Mb, CAM1=0Mb, CAM2=0Mb residual: 0Mb
Linux version 2.6.11 (pari@sjswsvr11) (gcc version 3.3.2) #16 Tue Apr 5 11:19:57
PDT 2005
Built 1 zonelists
Kernel command line: console=ttyS0,115200 root=/dev/ram rw doPci=1
OpenPIC Version 1.2 (1 CPUs and 44 IRQ sources) at fcfbb000
PID hash table entries: 2048 (order: 11, 32768 bytes)
Console: colour dummy device 80x25
Dentry cache hash table entries: 65536 (order: 6, 262144 bytes)
Inode-cache hash table entries: 32768 (order: 5, 131072 bytes)
Memory: 254720k available (1252k kernel code, 444k data, 292k init, 0k highmem)
Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
checking if image is initramfs...it isn't (no cpio magic); looks like an initrd
Freeing initrd memory: 2687k freed
NET: Registered protocol family 16
PCI: Probing PCI hardware
devfs: 2004-01-31 Richard Gooch (rgooch@atnf.csiro.au)
devfs: boot_options: 0x0
Serial: 8250/16550 driver $Revision: 1.90 $ 1 ports, IRQ sharing enabled
ttyS0 at MMIO 0xfdf04500 (irq = 90) is a 16550A
io scheduler noop registered inside elv_register()
RAMDISK driver initialized: 16 RAM disks of 32768K size 1024 blocksize
Inside gfar_probe() of gianfar.c
*************************************
Inside alloc_etherdev() for eth-1072721460
PHY base Addr is 0xd1002000
Before DMA engine stop for IEVENT
value of DMACTRL reg before writing to it : 0x0
value to be written to DMACTRL reg : 0x18
value of DMACTRL reg after writing to it : 0x80000000
value of IEVENT reg : 0x80000000
***************************************************************************
And after this it just gets into the loop where it looks if the 'Gracious receive and Gracious stop' bits of the IEVENT register are set.
In our case it doesnt get set and so the kernel hangs at that point.
Thanks
Junita
Clemens Koller <clemens.koller@anagramm.de> wrote:
Hi, Junita!
What PHYs do you use on the 8541?
Check if they are supported in gianfar_phy or if they
can be used with Generic MII
Check if you get the the phy_id is correct.
Some more debug-output would be nice.
I had to add Intel LXT971 support to the gianfar_phy
for my platform which is a 100MBit MII PHY only.
Clemens Koller
_______________________________
R&D Imaging Devices
Anagramm GmbH
Rupert-Mayer-Str. 45/1
81379 Muenchen
Germany
http://www.anagramm.de
Phone: +49-89-741518-50
Fax: +49-89-741518-19
Junita Ajith wrote:
> Andy
>
> 1. The code hangs exaclty at the point where it looks for the 'graceful transmit/receive' bits set in the IEVENT register. (IEVENT_GRSC , IEVENT_GTSC) .
> File - (linux-2.6/drivers/net/gianfar.c)
> Function - static int gfar_probe(struct device *device) ;
>
> In that ,we write Graceful Receive Stop and Graceful Transmit Stop, and then wait until the corresponding bits in IEVENT indicate the stops have completed.
>
> This never happens and hence hangs at the 'while' loop inside that function.
>
> 2. We are using Linux-2.6.11
>
> Here's the serial output dump with a few debug messages.
>
> ## Booting image at 02000000 ...
> Image Name: PCIG8400-Rel-1.1
> Image Type: PowerPC Linux Kernel Image (gzip compressed)
> Data Size: 883221 Bytes = 862.5 kB
> Load Address: 00000000
> Entry Point: 00000000
> Verifying Checksum ... OK
> Uncompressing Kernel Image ... OK
> ## Loading RAMDisk Image at 03000000 ...
> Image Name: PCIG8400
> Image Type: PowerPC Linux RAMDisk Image (gzip compressed)
> Data Size: 2751807 Bytes = 2.6 MB
> Load Address: 00000000
> Entry Point: 00000000
> Verifying Checksum ... OK
> Loading Ramdisk to 0fd12000, end 0ffb1d3f ... OK
> Memory CAM mapping: CAM0=256Mb, CAM1=0Mb, CAM2=0Mb residual: 0Mb
> Linux version 2.6.11 (pari@sjswsvr11) (gcc version 3.3.2) #16 Tue Apr 5 11:19:57
> PDT 2005
> Built 1 zonelists
> Kernel command line: console=ttyS0,115200 root=/dev/ram rw doPci=1
> OpenPIC Version 1.2 (1 CPUs and 44 IRQ sources) at fcfbb000
> PID hash table entries: 2048 (order: 11, 32768 bytes)
> Console: colour dummy device 80x25
> Dentry cache hash table entries: 65536 (order: 6, 262144 bytes)
> Inode-cache hash table entries: 32768 (order: 5, 131072 bytes)
> Memory: 254720k available (1252k kernel code, 444k data, 292k init, 0k highmem)
> Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
> checking if image is initramfs...it isn't (no cpio magic); looks like an initrd
> Freeing initrd memory: 2687k freed
> NET: Registered protocol family 16
> PCI: Probing PCI hardware
> devfs: 2004-01-31 Richard Gooch (rgooch@atnf.csiro.au)
> devfs: boot_options: 0x0
> Serial: 8250/16550 driver $Revision: 1.90 $ 1 ports, IRQ sharing enabled
> ttyS0 at MMIO 0xfdf04500 (irq = 90) is a 16550A
> io scheduler noop registered inside elv_register()
> RAMDISK driver initialized: 16 RAM disks of 32768K size 1024 blocksize
> Inside gfar_probe()
> einfo Phy ID 7
> gfar 1: additional data!
> Inside alloc_etherdev() for eth-1072721560
> start e0024000
> Resetting MAC........
> --2--MACCFG1 is 0x80000000
> MACCFG2 is 0x 0
> -2- tempval 000000db
> -3- tempval 00000000
> -4-1- tempval 00000000
> -4-2- tempval 00000000
> -4-2-a tempval 00000000
> -4-3 tempval 00000000
> -4-4 tempval 00000000
> Before loop -5- after writing to IEVENT tempval
> -5- after writing to IEVENT tempval 80000000
> -5- after writing to IEVENT tempval 80000000
> -5- after writing to IEVENT tempval 80000000
> -5- after writing to IEVENT tempval 80000000
> -5- after writing to IEVENT tempval 80000000
> -5- after writing to IEVENT tempval 80000000
> -5- after writing to IEVENT tempval 80000000
>
>
>
> thanks,
> Junita
> Andy Fleming wrote:
>
> Could you send me what the kernel prints up to the point of the hang?
>
> Also, what version of 2.6 are you using? The board interface for the
> driver changed recently to support the new driver model.
>
> Andy
>
> On Apr 12, 2005, at 12:38, Junita Ajith wrote:
>
>
>>Hi
>>We are trying to port Linux-2.6 for our custom
>>MPC8541 board.
>>
>>We have a TSEC and an FEC in the board.
>>
>>With the "Networking Support" disabled in the Kernel,
>>the board boots up fine and gets to the prompt.
>>
>>But with the "Networking Support" enabled in the
>>kernel the board hangs where it identifies the PHY,
>>inspite of giving the corrct PHY ID.
>>
>>
>>Any help is greatly appreciated.
>>
>>PS:
>>We have linux-2.4 ported for the same board and so
>>taking that as reference trying to port Linux-2.6 ,
>>but havent succeeded yet.
>>
>>Thanks
>>Junita
>>
>>
>>
>>__________________________________
>>Do you Yahoo!?
>>Make Yahoo! your home page
>>http://www.yahoo.com/r/hs
>>_______________________________________________
>>Linuxppc-embedded mailing list
>>Linuxppc-embedded@ozlabs.org
>>https://ozlabs.org/mailman/listinfo/linuxppc-embedded
>>
>
>
>
>
>
> ---------------------------------
> Do you Yahoo!?
> Yahoo! Small Business - Try our new resources site!
>
>
> ------------------------------------------------------------------------
>
> _______________________________________________
> Linuxppc-embedded mailing list
> Linuxppc-embedded@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-embedded
__________________________________________________
Do You Yahoo!?
Tired of spam? Yahoo! Mail has the best spam protection around
http://mail.yahoo.com
[-- Attachment #2: Type: text/html, Size: 12956 bytes --]
^ permalink raw reply
* Re: MPC5200 I2S driver
From: Hans Thielemans @ 2005-04-13 20:23 UTC (permalink / raw)
To: linuxppc-embedded, Eric N. Johnson (ACD)
In-Reply-To: <6.2.1.2.1.20050412173010.02adaaa0@mail.int.acdstar.com>
Hi Eric,
I have been working on a driver for a similar case:
mpc5200 talking to adi blackfin sport channel.
It is rather stable at the moment. Only now and then (~1/hour)
transmission stops due to bestcomm missing a taskstart.
When I check with the bdi2000 it is always the task active bit which
is cleared in the bestcomm registers.
When I kick the dma descriptor by setting the task active bit again with the
bdi2000 it continues normally. I suspect a problem with the bestcomm
api. The dma task active bit is cleared when dma is done. When this
interferes with the
ppc setting the bit. the task is not started (so far my analysis).
I did not find yet a 100% secure way of getting the bit set.
My main problem was also that I wanted the blackfin to be master of the
link. But the mpc5200 has an anomaly on the frame sync. I managed to
get it work by using the mpc5200 psc spi slave mode and proper
settings at the blackfin side. I got reliable transmission for several hours
at 16 Mbit/s
The driver supports simultaneous use of several psc channels. I tried psc2
and psc3 together.
You can use the driver as master or slave by changing the control register
with ioctl.
I'll forward the present version and a test program when i'm back at work
tomorrow.
Regards,
Hans Thielemans
HAZO bvba
----- Original Message -----
From: "Eric N. Johnson (ACD)" <ejohnson@acdstar.com>
To: <linuxppc-embedded@ozlabs.org>
Sent: Wednesday, April 13, 2005 12:46 AM
Subject: Re: MPC5200 I2S driver
> At 04:13 PM 4/12/2005, Wolfgang Denk wrote:
>>i2s.c is not really a driver, but a (very OLD) test version of one
>>used to demonstrate certain BestComm related problems. Don't try
>>using it as a real driver ;-)
>
> Humm, any pointers on writing our own driver then then? Digging through
> the source for other drivers, bestcomm seems to be a real house of cards.
> We just want simple audio output capability. No need to make it work with
> the standard Linux/OSS sound API.
>
> Where can we keep track of the eratta/bugs in bestcomm? Browsing through
> the mailing list, I've found references that:
> IDE and Ethernet DMA can't work at the same time
> I2S TX and RX DMA can't work at the same time
> AC-97 is terminally broken (no way to handle the slot tags properly
> for variable sampling rates)
> Are these all still true?
>
> We've tried asking our local Freescale rep, but they seem to think that
> Linux==Metrowerks, and they are looking into the bestcomm question, but
> official responses from Freescale tend to take >1 week.
>
> This is for a custom MPC5200 board, heavily based on IceCube with a single
> I2S DAC on PSC2 running in "CODEC with MCLK" mode.
>
> Sorry about the null subject line previously: fingers were working faster
> than brain...
>
> Thanks
> Eric
>
>
> ------------------------------------
> Eric Johnson, Electrical Engineer
> Advanced Communication Design
> 7901 12th Avenue South
> Bloomington, MN 55425
> Ph: 952-854-4000 Fax: 952-854-5774
>
> _______________________________________________
> Linuxppc-embedded mailing list
> Linuxppc-embedded@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-embedded
>
^ permalink raw reply
* Re: bdi2000 + mpc8560ads, very early breakpoints
From: Wolfgang Denk @ 2005-04-13 19:37 UTC (permalink / raw)
To: Kylo Ginsberg; +Cc: linuxppc-embedded
In-Reply-To: <425D6C03.1070805@kylo.net>
In message <425D6C03.1070805@kylo.net> you wrote:
>
> off the road. As a workaround, I modified u-boot to re-point IVPR when
> it relocates itself into ddr.
Will you submit a patch to the U-Boot mailing list, please?
Best regards,
Wolfgang Denk
--
Software Engineering: Embedded and Realtime Systems, Embedded Linux
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de
I think there's a world market for about five computers.
-- attr. Thomas J. Watson (Chairman of the Board, IBM), 1943
^ permalink raw reply
* Re: bdi2000 + mpc8560ads, very early breakpoints
From: Kylo Ginsberg @ 2005-04-13 18:59 UTC (permalink / raw)
To: Fahd Abidi; +Cc: linuxppc-embedded
In-Reply-To: <81C69D96BDD30640952C7A404004AA25018DB9@ultsol01.tewks.ultsol.local>
Thanks; that was instructive. I hadn't read up on the 85xx debug
exceptions yet.
For posterity, my issue was that even though the code is running out of
ddr at this stage, u-boot has left the IVPR pointed at flash. So once
head_e500.S invalidated the tlb entry for the flash region, the debug
exception vector was inaccessible and a breakpoint sent the processor
off the road. As a workaround, I modified u-boot to re-point IVPR when
it relocates itself into ddr.
Cheers,
Kylo
Fahd Abidi wrote:
>Try the suggestions pointed out in here:
>
>http://www.ultsol.com/faq-P308.htm
>
>This is based off suggestions from another customer. Let me know if this
>works for you or not.
>
>Fahd
>
>-----Original Message-----
>From: Kylo Ginsberg [mailto:kylo@veriwave.com]
>Sent: Tuesday, April 12, 2005 3:21 PM
>To: linuxppc-embedded@ozlabs.org
>Subject: bdi2000 + mpc8560ads, very early breakpoints
>
>I'm running a bdi2000 (with mpc85xx-gdb f/w 1.03) with a mpc8560ads
>target, and I'm trying to set breakpoints early on in linux startup (in
>the head_e500.S code that sets up tlb's). I'm setting the breakpoints
>from within the bdi telnet interface.
>
>I can:
>--succesfully hit a breakpoint set up to any instruction <= the address
>of the first 'tlbwe'.
>--single step (with the bdi "TI" command) past that 'tlbwe' as far as
>I've cared to try
>
>I cannot:
>--hit a breakpoint once the first 'tlbwe' has executed. If I attempt to
>
>do so, linux startup doesn't proceed, I lose further communication with
>the target and the BDI claims "COP Freeze" and I have to reset the
>target.
>
>Btw, the 'tlbwe' in question marks invalid the first tlb1 entry setup by
>
>u-boot, which pointed at flash address space. Code is running out of
>ram at this point.
>
>I'm probably missing something very basic here. Any ideas?
>
>Thanks,
>Kylo
>
>_______________________________________________
>Linuxppc-embedded mailing list
>Linuxppc-embedded@ozlabs.org
>https://ozlabs.org/mailman/listinfo/linuxppc-embedded
>
>_______________________________________________
>Linuxppc-embedded mailing list
>Linuxppc-embedded@ozlabs.org
>https://ozlabs.org/mailman/listinfo/linuxppc-embedded
>
>
>
^ permalink raw reply
* [PATCH 2.6.12-rc2] Freescale 8272ADS PCI bridge support to the stock linux-2.5 (updated)
From: Vitaly Bordug @ 2005-04-13 17:36 UTC (permalink / raw)
Cc: "Kumar Gala", linuxppc-embedded
In-Reply-To: <425D35E0.4040305@nm.ru>
[-- Attachment #1: Type: text/plain, Size: 198 bytes --]
Kumar,
This patch adds support for the MPC8272ADS PCI bridge.
The previous one is cleaned up after the final review.
Signed-off-by: Vitaly Bordug <vbordug@ru.mvista.com>
--
Sincerely,
Vitaly
[-- Attachment #2: 8272PCI.patch --]
[-- Type: text/x-patch, Size: 17766 bytes --]
===== arch/ppc/Kconfig 1.109 vs edited =====
--- 1.109/arch/ppc/Kconfig 2005-04-04 07:03:47 +04:00
+++ edited/arch/ppc/Kconfig 2005-04-12 16:47:48 +04:00
@@ -1123,7 +1123,7 @@
config PCI_8260
bool
- depends on PCI && 8260 && !8272
+ depends on PCI && 8260
default y
config 8260_PCI9
===== arch/ppc/platforms/pq2ads.h 1.3 vs edited =====
--- 1.3/arch/ppc/platforms/pq2ads.h 2005-01-16 01:01:51 +03:00
+++ edited/arch/ppc/platforms/pq2ads.h 2005-04-13 20:38:43 +04:00
@@ -49,10 +49,10 @@
/* PCI interrupt controller */
#define PCI_INT_STAT_REG 0xF8200000
#define PCI_INT_MASK_REG 0xF8200004
-#define PIRQA (NR_SIU_INTS + 0)
-#define PIRQB (NR_SIU_INTS + 1)
-#define PIRQC (NR_SIU_INTS + 2)
-#define PIRQD (NR_SIU_INTS + 3)
+#define PIRQA (NR_CPM_INTS + 0)
+#define PIRQB (NR_CPM_INTS + 1)
+#define PIRQC (NR_CPM_INTS + 2)
+#define PIRQD (NR_CPM_INTS + 3)
/*
* PCI memory map definitions for MPC8266ADS-PCI.
@@ -71,6 +71,7 @@
/* window for a PCI master to access MPC8266 memory */
#define PCI_SLV_MEM_LOCAL 0x00000000 /* Local base */
#define PCI_SLV_MEM_BUS 0x00000000 /* PCI base */
+#define PCI_SLV_MEM_SIZE 0x10000000 /* 256 Mb */
/* window for the processor to access PCI memory with prefetching */
#define PCI_MSTR_MEM_LOCAL 0x80000000 /* Local base */
@@ -83,9 +84,75 @@
#define PCI_MSTR_MEMIO_SIZE 0x20000000 /* 512MB */
/* window for the processor to access PCI I/O */
+#if !defined(CONFIG_ADS8272) && !defined(CONFIG_PQ2FADS)
+
#define PCI_MSTR_IO_LOCAL 0xF4000000 /* Local base */
#define PCI_MSTR_IO_BUS 0x00000000 /* PCI base */
#define PCI_MSTR_IO_SIZE 0x04000000 /* 64MB */
+
+#else /* CONFIG_ADS8272 or CONFIG_PQ2FADS */
+
+#define PCI_MSTR_IO_LOCAL 0xF6000000 /* Local base */
+#define PCI_MSTR_IO_BUS 0x00000000 /* PCI base */
+#define PCI_MSTR_IO_SIZE 0x02000000 /* 64MB */
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration Register 4-31
+ */
+#define SIUMCR_BBD 0x80000000 /* Bus Busy Disable */
+#define SIUMCR_ESE 0x40000000 /* External Snoop Enable */
+#define SIUMCR_PBSE 0x20000000 /* Parity Byte Select Enable */
+#define SIUMCR_CDIS 0x10000000 /* Core Disable */
+#define SIUMCR_DPPC00 0x00000000 /* Data Parity Pins Configuration*/
+#define SIUMCR_DPPC01 0x04000000 /* - " - */
+#define SIUMCR_DPPC10 0x08000000 /* - " - */
+#define SIUMCR_DPPC11 0x0c000000 /* - " - */
+#define SIUMCR_L2CPC00 0x00000000 /* L2 Cache Pins Configuration */
+#define SIUMCR_L2CPC01 0x01000000 /* - " - */
+#define SIUMCR_L2CPC10 0x02000000 /* - " - */
+#define SIUMCR_L2CPC11 0x03000000 /* - " - */
+#define SIUMCR_LBPC00 0x00000000 /* Local Bus Pins Configuration */
+#define SIUMCR_LBPC01 0x00400000 /* - " - */
+#define SIUMCR_LBPC10 0x00800000 /* - " - */
+#define SIUMCR_LBPC11 0x00c00000 /* - " - */
+#define SIUMCR_APPC00 0x00000000 /* Address Parity Pins Configuration*/
+#define SIUMCR_APPC01 0x00100000 /* - " - */
+#define SIUMCR_APPC10 0x00200000 /* - " - */
+#define SIUMCR_APPC11 0x00300000 /* - " - */
+#define SIUMCR_CS10PC00 0x00000000 /* CS10 Pin Configuration */
+#define SIUMCR_CS10PC01 0x00040000 /* - " - */
+#define SIUMCR_CS10PC10 0x00080000 /* - " - */
+#define SIUMCR_CS10PC11 0x000c0000 /* - " - */
+#define SIUMCR_BCTLC00 0x00000000 /* Buffer Control Configuration */
+#define SIUMCR_BCTLC01 0x00010000 /* - " - */
+#define SIUMCR_BCTLC10 0x00020000 /* - " - */
+#define SIUMCR_BCTLC11 0x00030000 /* - " - */
+#define SIUMCR_MMR00 0x00000000 /* Mask Masters Requests */
+#define SIUMCR_MMR01 0x00004000 /* - " - */
+#define SIUMCR_MMR10 0x00008000 /* - " - */
+#define SIUMCR_MMR11 0x0000c000 /* - " - */
+#define SIUMCR_LPBSE 0x00002000 /* LocalBus Parity Byte Select Enable*/
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock Control Register 9-8
+ */
+#define SCCR_PCI_MODE 0x00000100 /* PCI Mode */
+#define SCCR_PCI_MODCK 0x00000080 /* Value of PCI_MODCK pin */
+#define SCCR_PCIDF_MSK 0x00000078 /* PCI division factor */
+#define SCCR_PCIDF_SHIFT 3
+
+#endif
+
+#if defined(CONFIG_ADS8272)
+#define PCI_INT_TO_SIU SIU_INT_IRQ2
+#elif defined(CONFIG_PQ2FADS)
+#define PCI_INT_TO_SIU SIU_INT_IRQ6
+#else
+#warning PCI Bridge will be without interrupts support
+#endif
+
+#define POTA_ADDR_SHIFT 12
+#define PITA_ADDR_SHIFT 12
#define _IO_BASE PCI_MSTR_IO_LOCAL
#define _ISA_MEM_BASE PCI_MSTR_MEMIO_LOCAL
===== arch/ppc/syslib/Makefile 1.51 vs edited =====
--- 1.51/arch/ppc/syslib/Makefile 2005-03-31 14:59:04 +04:00
+++ edited/arch/ppc/syslib/Makefile 2005-04-12 16:47:50 +04:00
@@ -82,6 +82,9 @@
todc_time.o
obj-$(CONFIG_8260) += m8260_setup.o
obj-$(CONFIG_PCI_8260) += m8260_pci.o indirect_pci.o
+ifeq ($(CONFIG_ADS8272),y)
+obj-$(CONFIG_PCI) += pci_auto.o
+endif
obj-$(CONFIG_8260_PCI9) += m8260_pci_erratum9.o
obj-$(CONFIG_CPM2) += cpm2_common.o cpm2_pic.o
ifeq ($(CONFIG_PPC_GEN550),y)
===== arch/ppc/syslib/m8260_pci.c 1.2 vs edited =====
--- 1.2/arch/ppc/syslib/m8260_pci.c 2004-06-17 16:57:15 +04:00
+++ edited/arch/ppc/syslib/m8260_pci.c 2005-04-13 20:38:02 +04:00
@@ -1,4 +1,7 @@
/*
+ * 2005 (c) MontaVista Software, Inc.
+ * Vitaly Bordug <vbordug@ru.mvista.com>
+ *
* (C) Copyright 2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
@@ -28,6 +31,8 @@
#include <linux/pci.h>
#include <linux/slab.h>
#include <linux/delay.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
#include <asm/byteorder.h>
#include <asm/io.h>
@@ -38,12 +43,144 @@
#include <asm/immap_cpm2.h>
#include <asm/mpc8260.h>
+#if !defined(CONFIG_ADS8272) && !defined(CONFIG_PQ2FADS)
#include "m8260_pci.h"
+#endif
+
+/*
+ * Interrupt routing
+ */
+
+static inline int
+pq2pci_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
+{
+ static char pci_irq_table[][4] =
+ /*
+ * PCI IDSEL/INTPIN->INTLINE
+ * A B C D
+ */
+ {
+ { PIRQA, PIRQB, PIRQC, PIRQD }, /* IDSEL 22 - PCI slot 0 */
+ { PIRQD, PIRQA, PIRQB, PIRQC }, /* IDSEL 23 - PCI slot 1 */
+ { PIRQC, PIRQD, PIRQA, PIRQB }, /* IDSEL 24 - PCI slot 2 */
+ };
+
+ const long min_idsel = 22, max_idsel = 24, irqs_per_slot = 4;
+ return PCI_IRQ_TABLE_LOOKUP;
+}
+
+static void
+pq2pci_mask_irq(unsigned int irq)
+{
+ int bit = irq - NR_CPM_INTS;
+
+ *(volatile unsigned long *) PCI_INT_MASK_REG |= (1 << (31 - bit));
+ return;
+}
+
+static void
+pq2pci_unmask_irq(unsigned int irq)
+{
+ int bit = irq - NR_CPM_INTS;
+
+ *(volatile unsigned long *) PCI_INT_MASK_REG &= ~(1 << (31 - bit));
+ return;
+}
+
+static void
+pq2pci_mask_and_ack(unsigned int irq)
+{
+ int bit = irq - NR_CPM_INTS;
+
+ *(volatile unsigned long *) PCI_INT_MASK_REG |= (1 << (31 - bit));
+ return;
+}
+
+static void
+pq2pci_end_irq(unsigned int irq)
+{
+ int bit = irq - NR_CPM_INTS;
+
+ *(volatile unsigned long *) PCI_INT_MASK_REG &= ~(1 << (31 - bit));
+ return;
+}
+
+struct hw_interrupt_type pq2pci_ic = {
+ "PQ2 PCI",
+ NULL,
+ NULL,
+ pq2pci_unmask_irq,
+ pq2pci_mask_irq,
+ pq2pci_mask_and_ack,
+ pq2pci_end_irq,
+ 0
+};
+
+static irqreturn_t
+pq2pci_irq_demux(int irq, void *dev_id, struct pt_regs *regs)
+{
+ unsigned long stat, mask, pend;
+ int bit;
+
+ for(;;) {
+ stat = *(volatile unsigned long *) PCI_INT_STAT_REG;
+ mask = *(volatile unsigned long *) PCI_INT_MASK_REG;
+ pend = stat & ~mask & 0xf0000000;
+ if (!pend)
+ break;
+ for (bit = 0; pend != 0; ++bit, pend <<= 1) {
+ if (pend & 0x80000000)
+ __do_IRQ(NR_CPM_INTS + bit, regs);
+ }
+ }
+
+ return IRQ_HANDLED;
+}
+
+static struct irqaction pq2pci_irqaction = {
+ .handler = pq2pci_irq_demux,
+ .flags = SA_INTERRUPT,
+ .mask = CPU_MASK_NONE,
+ .name = "PQ2 PCI cascade",
+};
+
+
+void
+pq2pci_init_irq(void)
+{
+ int irq;
+ volatile cpm2_map_t *immap = cpm2_immr;
+#ifdef CONFIG_ADS8272
+ /* configure chip select for PCI interrupt controller */
+ immap->im_memctl.memc_br3 = PCI_INT_STAT_REG | 0x00001801;
+ immap->im_memctl.memc_or3 = 0xffff8010;
+#endif
+ for (irq = NR_CPM_INTS; irq < NR_CPM_INTS + 4; irq++)
+ irq_desc[irq].handler = &pq2pci_ic;
+
+ /* make PCI IRQ level sensitive */
+ immap->im_intctl.ic_siexr &=
+ ~(1 << (14 - (PCI_INT_TO_SIU - SIU_INT_IRQ1)));
+
+ /* mask all PCI interrupts */
+ *(volatile unsigned long *) PCI_INT_MASK_REG |= 0xfff00000;
+
+ /* install the demultiplexer for the PCI cascade interrupt */
+ setup_irq(PCI_INT_TO_SIU, &pq2pci_irqaction);
+ return;
+}
+
+static int
+pq2pci_exclude_device(u_char bus, u_char devfn)
+{
+ return PCIBIOS_SUCCESSFUL;
+}
/* PCI bus configuration registers.
*/
+#if !defined(CONFIG_ADS8272) && !defined(CONFIG_PQ2FADS)
static void __init m8260_setup_pci(struct pci_controller *hose)
{
volatile cpm2_map_t *immap = cpm2_immr;
@@ -146,10 +283,148 @@
tempShort | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
}
-void __init m8260_find_bridges(void)
+#else /* setup hardware for 8272ADS and PQ2FADS */
+
+static void
+pq2ads_setup_pci(struct pci_controller *hose)
+{
+ __u32 val;
+ volatile cpm2_map_t *immap = cpm2_immr;
+ bd_t* binfo = (bd_t*) __res;
+ u32 sccr = immap->im_clkrst.car_sccr;
+ uint pci_div,freq,time;
+ /* PCI int lowest prio */
+ /* Each 4 bits is a device bus request and the MS 4bits
+ is highest priority */
+ /* Bus 4bit value
+ --- ----------
+ CPM high 0b0000
+ CPM middle 0b0001
+ CPM low 0b0010
+ PCI reguest 0b0011
+ Reserved 0b0100
+ Reserved 0b0101
+ Internal Core 0b0110
+ External Master 1 0b0111
+ External Master 2 0b1000
+ External Master 3 0b1001
+ The rest are reserved
+ */
+ immap->im_siu_conf.siu_82xx.sc_ppc_alrh = 0x61207893;
+ /* park bus on core */
+ immap->im_siu_conf.siu_82xx.sc_ppc_acr = PPC_ACR_BUS_PARK_CORE;
+ /*
+ * Set up master windows that allow the CPU to access PCI space. These
+ * windows are set up using the two SIU PCIBR registers.
+ */
+
+ immap->im_memctl.memc_pcimsk0 = ~(PCI_MSTR_IO_SIZE - 1U);
+ immap->im_memctl.memc_pcibr0 = PCI_MSTR_IO_LOCAL | PCIBR_ENABLE;
+
+ immap->im_memctl.memc_pcimsk1 = ~(PCI_MSTR_MEM_SIZE + PCI_MSTR_MEMIO_SIZE - 1U);
+ immap->im_memctl.memc_pcibr1 = PCI_MSTR_MEM_LOCAL | PCIBR_ENABLE;
+#ifdef CONFIG_ADS8272
+ immap->im_siu_conf.siu_82xx.sc_siumcr = (immap->im_siu_conf.siu_82xx.sc_siumcr &
+ ~SIUMCR_BBD &
+ ~SIUMCR_ESE &
+ ~SIUMCR_PBSE &
+ ~SIUMCR_CDIS &
+ ~SIUMCR_DPPC11 &
+ ~SIUMCR_L2CPC11 &
+ ~SIUMCR_LBPC11 &
+ ~SIUMCR_APPC11 &
+ ~SIUMCR_CS10PC11 &
+ ~SIUMCR_BCTLC11 &
+ ~SIUMCR_MMR11)
+ | SIUMCR_DPPC11 | SIUMCR_L2CPC01 | SIUMCR_LBPC00
+ | SIUMCR_APPC10 | SIUMCR_CS10PC00 | SIUMCR_BCTLC00 | SIUMCR_MMR11;
+#elif defined CONFIG_PQ2FADS
+ /*
+ * Setting required to enable IRQ1-IRQ7 (SIUMCR [DPPC]),
+ * and local bus for PCI (SIUMCR [LBPC]).
+ */
+ immap->im_siu_conf.siu_82xx.sc_siumcr = (immap->im_siu_conf.sc_siumcr &
+ ~SIUMCR_LBPC11 &
+ ~SIUMCR_CS10PC11 &
+ ~SIUMCR_LBPC11) |
+ SIUMCR_LBPC01 | SIUMCR_CS10PC01 | SIUMCR_APPC10;
+#endif
+ /* Enable PCI */
+ immap->im_pci.pci_gcr = cpu_to_le32(PCIGCR_PCI_BUS_EN);
+
+ pci_div = ( (sccr & SCCR_PCI_MODCK) ? 2 : 1) *
+ ( ( (sccr & SCCR_PCIDF_MSK) >> SCCR_PCIDF_SHIFT) + 1);
+ freq = (uint)((2*binfo->bi_cpmfreq)/(pci_div));
+ time = (int)666666/freq;
+ /* due to PCI Local Bus spec, some devices needs to wait such a long
+ time after RST deassertion. More specifically, 0.508s for 66MHz & twice more for 33 */
+ printk("%s: The PCI bus is %d Mhz.\nWaiting %s after deasserting RST...\n",__FILE__,freq,
+ (time==1) ? "0.5 seconds":"1 second" );
+
+ {
+ int i;
+ for(i=0;i<(500*time);i++)
+ udelay(1000);
+ }
+
+ /* setup ATU registers */
+ immap->im_pci.pci_pocmr0 = cpu_to_le32(POCMR_ENABLE | POCMR_PCI_IO |
+ ((~(PCI_MSTR_IO_SIZE - 1U)) >> POTA_ADDR_SHIFT));
+ immap->im_pci.pci_potar0 = cpu_to_le32(PCI_MSTR_IO_BUS >> POTA_ADDR_SHIFT);
+ immap->im_pci.pci_pobar0 = cpu_to_le32(PCI_MSTR_IO_LOCAL >> POTA_ADDR_SHIFT);
+
+ /* Set-up non-prefetchable window */
+ immap->im_pci.pci_pocmr1 = cpu_to_le32(POCMR_ENABLE | ((~(PCI_MSTR_MEMIO_SIZE-1U)) >> POTA_ADDR_SHIFT));
+ immap->im_pci.pci_potar1 = cpu_to_le32(PCI_MSTR_MEMIO_BUS >> POTA_ADDR_SHIFT);
+ immap->im_pci.pci_pobar1 = cpu_to_le32(PCI_MSTR_MEMIO_LOCAL >> POTA_ADDR_SHIFT);
+
+ /* Set-up prefetchable window */
+ immap->im_pci.pci_pocmr2 = cpu_to_le32(POCMR_ENABLE |POCMR_PREFETCH_EN |
+ (~(PCI_MSTR_MEM_SIZE-1U) >> POTA_ADDR_SHIFT));
+ immap->im_pci.pci_potar2 = cpu_to_le32((PCI_MSTR_MEM_BUS) >> POTA_ADDR_SHIFT);
+ immap->im_pci.pci_pobar2 = cpu_to_le32((PCI_MSTR_MEM_LOCAL) >> POTA_ADDR_SHIFT);
+
+ /* Inbound transactions from PCI memory space */
+ immap->im_pci.pci_picmr0 = cpu_to_le32(PICMR_ENABLE | PICMR_PREFETCH_EN |
+ ((~(PCI_SLV_MEM_SIZE-1U)) >> PITA_ADDR_SHIFT));
+ immap->im_pci.pci_pibar0 = cpu_to_le32(PCI_SLV_MEM_BUS >> PITA_ADDR_SHIFT);
+ immap->im_pci.pci_pitar0 = cpu_to_le32(PCI_SLV_MEM_LOCAL>> PITA_ADDR_SHIFT);
+
+#if defined CONFIG_ADS8272
+ /* PCI int highest prio */
+ immap->im_siu_conf.siu_82xx.sc_ppc_alrh = 0x01236745;
+#elif defined CONFIG_PQ2FADS
+ immap->im_siu_conf.siu_82xx.sc_ppc_alrh = 0x03124567;
+#endif
+ /* park bus on PCI */
+ immap->im_siu_conf.siu_82xx.sc_ppc_acr = PPC_ACR_BUS_PARK_PCI;
+
+ /* Enable bus mastering and inbound memory transactions */
+ early_read_config_dword(hose, hose->first_busno, 0, PCI_COMMAND, &val);
+ val &= 0xffff0000;
+ val |= PCI_COMMAND_MEMORY|PCI_COMMAND_MASTER;
+ early_write_config_dword(hose, hose->first_busno, 0, PCI_COMMAND, val);
+
+}
+
+static void pq2ads_setup_hose(struct pci_controller * hose)
+{
+ hose->io_space.start = MPC826x_PCI_LOWER_IO;
+ hose->io_space.end = MPC826x_PCI_UPPER_IO;
+ hose->mem_space.start = MPC826x_PCI_LOWER_MEM;
+ hose->mem_space.end = MPC826x_PCI_UPPER_MMIO;
+ hose->io_base_virt = (void*)MPC826x_PCI_IO_BASE;
+ isa_io_base = MPC826x_PCI_IO_BASE;
+}
+
+#endif
+
+
+void __init pq2_find_bridges(void)
{
extern int pci_assign_all_busses;
struct pci_controller * hose;
+ int host_bridge;
pci_assign_all_busses = 1;
@@ -164,18 +439,45 @@
hose->bus_offset = 0;
hose->last_busno = 0xff;
+#ifdef CONFIG_ADS8272
+ hose->set_cfg_type = 1;
+#endif
+
setup_m8260_indirect_pci(hose,
(unsigned long)&cpm2_immr->im_pci.pci_cfg_addr,
(unsigned long)&cpm2_immr->im_pci.pci_cfg_data);
+ /* Make sure it is a supported bridge */
+ early_read_config_dword(hose,
+ 0,
+ PCI_DEVFN(0,0),
+ PCI_VENDOR_ID,
+ &host_bridge);
+ switch (host_bridge) {
+ case PCI_DEVICE_ID_MPC8265:
+ break;
+ case PCI_DEVICE_ID_MPC8272:
+ break;
+ default:
+ printk("Attempting to use unrecognized host bridge ID"
+ " 0x%08x.\n", host_bridge);
+ break;
+ }
+
+#if defined(CONFIG_ADS8272) || defined(CONFIG_PQ2FADS)
+ pq2ads_setup_pci(hose);
+ pq2ads_setup_hose(hose);
+#else
m8260_setup_pci(hose);
+
hose->pci_mem_offset = MPC826x_PCI_MEM_OFFSET;
- isa_io_base =
+ isa_io_base =
(unsigned long) ioremap(MPC826x_PCI_IO_BASE,
MPC826x_PCI_IO_SIZE);
hose->io_base_virt = (void *) isa_io_base;
-
+#endif
+
/* setup resources */
pci_init_resource(&hose->mem_resources[0],
MPC826x_PCI_LOWER_MEM,
@@ -191,4 +493,15 @@
MPC826x_PCI_LOWER_IO,
MPC826x_PCI_UPPER_IO,
IORESOURCE_IO, "PCI I/O");
+
+#if defined(CONFIG_ADS8272) || defined(CONFIG_PQ2FADS)
+ ppc_md.pci_exclude_device = pq2pci_exclude_device;
+ hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
+
+ ppc_md.pci_map_irq = pq2pci_map_irq;
+ ppc_md.pcibios_fixup = NULL;
+ ppc_md.pcibios_fixup_bus = NULL;
+
+#endif
+
}
===== arch/ppc/syslib/m8260_setup.c 1.30 vs edited =====
--- 1.30/arch/ppc/syslib/m8260_setup.c 2005-03-31 14:59:04 +04:00
+++ edited/arch/ppc/syslib/m8260_setup.c 2005-04-13 20:33:52 +04:00
@@ -34,7 +34,11 @@
unsigned char __res[sizeof(bd_t)];
extern void cpm2_reset(void);
+#if !defined(CONFIG_ADS8272) && !defined(CONFIG_PQ2FADS)
extern void m8260_find_bridges(void);
+#endif
+extern void pq2_find_bridges(void);
+extern void pq2pci_init_irq(void);
extern void idma_pci9_init(void);
/* Place-holder for board-specific init */
@@ -56,7 +60,11 @@
idma_pci9_init();
#endif
#ifdef CONFIG_PCI_8260
+#if defined(CONFIG_ADS8272) || defined(CONFIG_PQ2FADS)
+ pq2_find_bridges();
+#else
m8260_find_bridges();
+#endif
#endif
#ifdef CONFIG_BLK_DEV_INITRD
if (initrd_start)
@@ -173,6 +181,12 @@
* in case the boot rom changed something on us.
*/
cpm2_immr->im_intctl.ic_siprr = 0x05309770;
+
+#if defined(CONFIG_PCI) && (defined(CONFIG_ADS8272) || defined(CONFIG_PQ2FADS))
+ /* Initialize stuff for the 82xx CPLD IC and install demux */
+ pq2pci_init_irq();
+#endif
+
}
/*
@@ -195,6 +209,9 @@
m8260_map_io(void)
{
uint addr;
+#if defined(CONFIG_PCI) && (defined(CONFIG_ADS8272) || defined(CONFIG_PQ2FADS))
+ io_block_mapping(0x80000000,0x80000000,0x10000000, _PAGE_IO);
+#endif
/* Map IMMR region to a 256MB BAT */
addr = (cpm2_immr != NULL) ? (uint)cpm2_immr : CPM_MAP_ADDR;
===== include/asm-ppc/m8260_pci.h 1.1 vs edited =====
--- 1.1/include/asm-ppc/m8260_pci.h 2004-06-17 02:56:05 +04:00
+++ edited/include/asm-ppc/m8260_pci.h 2005-04-12 17:17:29 +04:00
@@ -19,6 +19,7 @@
* Define the vendor/device ID for the MPC8265.
*/
#define PCI_DEVICE_ID_MPC8265 ((0x18C0 << 16) | PCI_VENDOR_ID_MOTOROLA)
+#define PCI_DEVICE_ID_MPC8272 ((0x18C1 << 16) | PCI_VENDOR_ID_MOTOROLA)
#define M8265_PCIBR0 0x101ac
#define M8265_PCIBR1 0x101b0
^ permalink raw reply
* Re: 824x Sandpoint with 2.6.x
From: Mark A. Greer @ 2005-04-13 16:48 UTC (permalink / raw)
To: Sam Song; +Cc: linuxppc-embedded
In-Reply-To: <20050412041021.64111.qmail@web15810.mail.cnb.yahoo.com>
Sam Song wrote:
>--- "Mark A. Greer" <mgreer@mvista.com> wrote:
>
>
>>Sam Song wrote:
>>
>>
>>
>>>Hi all,
>>>
>>>I'd like to know where I could get a good start on
>>>824x Sandpoint board with 2.6.x? Is linuxppc-2.5 BK
>>>tree nice for me to work?
>>>
>>>
>>No. Use linux-2.5/6.
>>
>>
>
>Thanks a lot, Mark.
>
No problem, Sam. Let me know if you encounter any problems with it.
Mark
^ permalink raw reply
* RE: mmap : please help !
From: Fillod Stephane @ 2005-04-13 16:33 UTC (permalink / raw)
To: scarayol; +Cc: linuxppc-embedded
Sophie CARAYOL wrote:
[...]
> What is the good manner to read or write in the physical memory?
Please have a look at Denx's FAQ for accessing memory bus:
=20
http://www.denx.de/twiki/bin/view/PPCEmbedded/DeviceDrivers#Section_Acce
ssingPeripheralsFromUserSpace
or shorter: http://tinyurl.com/6c7th
Depending on the O_SYNC flag passed to open, the mmap'ed memory will be
accessed through non guarded cache or not. See linux/drivers/char/mem.c.
The ppc instruction "eieio" deals with I/O ordering.
Kenavo
--=20
Stephane
PS: be careful not sending twice the same mail to the list=20
^ permalink raw reply
* mmap : please help !
From: scarayol @ 2005-04-13 16:19 UTC (permalink / raw)
To: akpm; +Cc: linuxppc-embedded
Hi all,
I need somme help : I wrote driver like /dev/mem to read and write into=
physical memory at specific addresses. For that, I use instruction mmap=
like that :
if((mem_mc_fd =3D open("/dev/map_mc",O_RDWR | O_SYNC)) < 0)
{
printf("\nProbleme pour ouvrir /dev/map_mc\n");
exit(-1);
}
// mapping de la zone correspondante
pmapMC =3D (DisqueMC *)mmap (0,MC_SIZE, PROT_READ | PROT_WRITE |
PROT_EXEC, MAP_SHARED, mem_mc_fd, MC_BASE_ADDRESS);
if (pmapMC =3D=3D MAP_FAILED)
{
printf("Erreur de mmap pour MC:%d,%s\n",errno, strerror(errno))=
;
close(mem_mc_fd);
}
I use function pread, pwrite to access datas within the driver function=
s
but, I should prefer to use pmapMC pointer (by the mean of this virtual=
address) that points to a structure. I thought that it was the same to
access to the physical memory to use the pointer or to use read, write =
on
the file (by mem_mc_fd), but it seems to have different results. What i=
s
wrong ? What is the good manner to read or write in the physical memory=
?
Thanks a lot.
----------------------------------------------------------
Sophie CARAYOL
TECHNOLOGIES & SYSTEMES
50 rue du Pr=E9sident Sadate
F - 29337 QUIMPER CEDEX
T=E9l: +33 2 98 10 30 06
mailto:scarayol@assystembrime.com
----------------------------------------------------------
=
^ permalink raw reply
* mmap : please help !
From: scarayol @ 2005-04-13 16:17 UTC (permalink / raw)
To: akpm; +Cc: linuxppc-embedded
Hi all,
I need somme help : I wrote driver like /dev/mem to read and write into=
physical memory at specific addresses. For that, I use instruction mmap=
like that :
if((mem_mc_fd =3D open("/dev/map_mc",O_RDWR | O_SYNC)) < 0)
{
printf("\nProbleme pour ouvrir /dev/map_mc\n");
exit(-1);
}
// mapping de la zone correspondante
pmapMC =3D (DisqueMC *)mmap (0,MC_SIZE, PROT_READ | PROT_WRITE |
PROT_EXEC, MAP_SHARED, mem_mc_fd, MC_BASE_ADDRESS);
if (pmapMC =3D=3D MAP_FAILED)
{
printf("Erreur de mmap pour MC:%d,%s\n",errno, strerror(errno))=
;
close(mem_mc_fd);
}
I use function pread, pwrite to access datas within the driver function=
s
but, I should prefer to use pmapMC pointer (by the mean of this virtual=
address) that points to a structure. I thought that it was the same to
access to the physical memory to use the pointer or to use read, write =
on
the file (by mem_mc_fd), but it seems to have different results. What i=
s
wrong ? What is the good manner to read or write in the physical memory=
?
Thanks a lot.
----------------------------------------------------------
Sophie CARAYOL
TECHNOLOGIES & SYSTEMES
50 rue du Pr=E9sident Sadate
F - 29337 QUIMPER CEDEX
T=E9l: +33 2 98 10 30 06
mailto:scarayol@assystembrime.com
----------------------------------------------------------
=
^ permalink raw reply
* Booting from cramfs with 2.6.11
From: Pawel Studencki @ 2005-04-13 15:48 UTC (permalink / raw)
To: linuxppc-embedded
hallo,
after solving some problems I got 2.6.11 kernel
booting on my board with
8xx.
Now I'm trying to mount cramfs root filesystem from
flash. I've debuged this
until inode->i_op->lookup in real_lookup function -
I hoped to see here
cramfs_lookup, but simple_lookup was called instead
of that...
From the beginning: mounting process starts in
do_mount, where with call
path_lookup it is looked for mount point. Actually
it is function
link_path_walk, where do_lookup is called - it
returns a dentry using
function real_lookup (and i_op->lookup is equal
simple_lookup). inode of the
returned dentry is NULL. So link_path_walk returns
-ENOENT (-2), the same
value returns than path_lookup and do_mount.
I thought, the problem is wrong i_op->lookup
function (simple_lookup instead
of cramfs_looup). But the right values will be set
first in do_new_mount
calling do_kern_mount.
here is a simple draft to help you understand...
sys_mount(name, "/root", fs, flags, data); - in my
case fs is cramfs.
|
|-->do_mount()
|
|-- some checks...
|
|-- path_lookup()
| |
| |-- link_path_walk() (fs/namei.c)
| |
| |-- do_lookup() (returns
next.dentry)
| | |
| | |-- __d_lookup
| | |
| | |-- real_lookup(nd->dentry,
name, nd);
| | |
| | |-- dentry =
d_alloc(parent, name);
(dentry->d_inode=NULL)
| | |
| | |- result =
dir->i_op->lookup(dir, dentry, nd);
!!! result is a
dentry with inode = NULL !!!
| |
| |
| |
| |
| |
| |-- follow_mount()
| |
| |
| | inode = next.dentry->d_inode;
(inode is NULL!!!!)
|
|
|
|-- do_new_mount()
|
|-- do_kern_mount() (fs/super.c)
|
|-- type->get_sb (type is cramfs, and first
get_sb
sets i_op....
see fs/cramfs/inode.c )
I don't understand all dependances, so perhaps
someone could give me a hint,
what is wrong here...is this normal that a dentry
hat inode NULL? should the
function cramfs_lookup be called here? If so, is
there another place, where
i_op is set?
best regards
Pawel
----------------------------------------------------------------------------
> ------
> Linux version 2.6.11 (nb221330@nb2g156c) (gcc
> version 3.3.4) #29 Wed Apr 13
> 14:38:33 WEST 2005
> Built 1 zonelists
> Kernel command line: console=ttyCPM0, 57600
> root=/dev/mtdblock1
> rootfstype=cramfs ro
> PID hash table entries: 128 (order: 7, 2048 bytes)
> Decrementer Frequency = 187500000/60
> m8xx_wdt: wdt disabled (SYPCR: 0xFFFFFF88)
> Console: colour dummy device 80x25
> Dentry cache hash table entries: 4096 (order: 2,
> 16384 bytes)
> Inode-cache hash table entries: 2048 (order: 1, 8192
> bytes)
> Memory: 14748k available (996k kernel code, 372k
> data, 60k init, 0k highmem)
> Mount-cache hash table entries: 512 (order: 0, 4096
> bytes)
> NET: Registered protocol family 16
> JFFS2 version 2.2. (NAND) (C) 2001-2003 Red Hat,
> Inc.
> Serial: CPM driver $Revision: 0.01 $
> ttyCPM0 at MMIO 0xff000a60 (irq = 43) is a CPM UART
> io scheduler noop registered
> loop: loaded (max 8 devices)
> physmap flash device: 400000 at ffc00000
> phys_mapped_flash: Found 1 x16 devices at 0x0 in
> 16-bit bank
> Amd/Fujitsu Extended Query Table at 0x0040
> number of CFI chips: 1
> cfi_cmdset_0002: Disabling erase-suspend-program due
> to code brokenness.
> Creating 5 MTD partitions on "phys_mapped_flash":
> 0x00000000-0x000d0000 : "Kernel"
> mtd: Giving out device 0 to Kernel
> 0x000d0000-0x001d0000 : "RootFS"
> mtd: Giving out device 1 to RootFS
> 0x001d0000-0x00300000 : "ApplFS1"
> mtd: Giving out device 2 to ApplFS1
> 0x00300000-0x00330000 : "U-Boot"
> mtd: Giving out device 3 to U-Boot
> 0x00330000-0x00400000 : "ApplFS2"
> mtd: Giving out device 4 to ApplFS2
> slram: not enough parameters.
>
> VFS: Cannot open root device "mtdblock1" or
> unknown-block(31,1)
> Please append a correct "root=" boot option
> Kernel panic - not syncing: VFS: Unable to mount
> root fs on
> unknown-block(31,1)
>
----------------------------------------------------------------------------
__________________________________________________
Do You Yahoo!?
Tired of spam? Yahoo! Mail has the best spam protection around
http://mail.yahoo.com
^ permalink raw reply
* [PATCH 2.6.12-rc2] Freescale 8272ADS PCI bridge support to the stock linux-2.5
From: Vitaly @ 2005-04-13 15:08 UTC (permalink / raw)
To: Kumar Gala; +Cc: linuxppc-embedded
[-- Attachment #1: Type: text/plain, Size: 297 bytes --]
Kumar,
This patch adds support for the MPC8272ADS PCI bridge.
The stuff that alters delay after RST deassertion relative to the
current PCI frequency included (thus it will wait for 1 second if PCI
bus is 33MHz).
Signed-off-by: Vitaly Bordug <vbordug@ru.mvista.com>
--
Sincerely,
Vitaly
[-- Attachment #2: 2005-04-12-8272ADS.patch --]
[-- Type: text/x-patch, Size: 17613 bytes --]
===== arch/ppc/Kconfig 1.109 vs edited =====
--- 1.109/arch/ppc/Kconfig 2005-04-04 07:03:47 +04:00
+++ edited/arch/ppc/Kconfig 2005-04-12 16:47:48 +04:00
@@ -1123,7 +1123,7 @@
config PCI_8260
bool
- depends on PCI && 8260 && !8272
+ depends on PCI && 8260
default y
config 8260_PCI9
===== arch/ppc/platforms/pq2ads.h 1.3 vs edited =====
--- 1.3/arch/ppc/platforms/pq2ads.h 2005-01-16 01:01:51 +03:00
+++ edited/arch/ppc/platforms/pq2ads.h 2005-04-12 19:57:14 +04:00
@@ -49,10 +49,10 @@
/* PCI interrupt controller */
#define PCI_INT_STAT_REG 0xF8200000
#define PCI_INT_MASK_REG 0xF8200004
-#define PIRQA (NR_SIU_INTS + 0)
-#define PIRQB (NR_SIU_INTS + 1)
-#define PIRQC (NR_SIU_INTS + 2)
-#define PIRQD (NR_SIU_INTS + 3)
+#define PIRQA (NR_CPM_INTS + 0)
+#define PIRQB (NR_CPM_INTS + 1)
+#define PIRQC (NR_CPM_INTS + 2)
+#define PIRQD (NR_CPM_INTS + 3)
/*
* PCI memory map definitions for MPC8266ADS-PCI.
@@ -71,6 +71,7 @@
/* window for a PCI master to access MPC8266 memory */
#define PCI_SLV_MEM_LOCAL 0x00000000 /* Local base */
#define PCI_SLV_MEM_BUS 0x00000000 /* PCI base */
+#define PCI_SLV_MEM_SIZE 0x10000000 /* 256 Mb */
/* window for the processor to access PCI memory with prefetching */
#define PCI_MSTR_MEM_LOCAL 0x80000000 /* Local base */
@@ -83,9 +84,75 @@
#define PCI_MSTR_MEMIO_SIZE 0x20000000 /* 512MB */
/* window for the processor to access PCI I/O */
+#ifndef CONFIG_ADS8272
+
#define PCI_MSTR_IO_LOCAL 0xF4000000 /* Local base */
#define PCI_MSTR_IO_BUS 0x00000000 /* PCI base */
#define PCI_MSTR_IO_SIZE 0x04000000 /* 64MB */
+
+#else /* CONFIG_ADS8272 */
+
+#define PCI_MSTR_IO_LOCAL 0xF6000000 /* Local base */
+#define PCI_MSTR_IO_BUS 0x00000000 /* PCI base */
+#define PCI_MSTR_IO_SIZE 0x02000000 /* 64MB */
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration Register 4-31
+ */
+#define SIUMCR_BBD 0x80000000 /* Bus Busy Disable */
+#define SIUMCR_ESE 0x40000000 /* External Snoop Enable */
+#define SIUMCR_PBSE 0x20000000 /* Parity Byte Select Enable */
+#define SIUMCR_CDIS 0x10000000 /* Core Disable */
+#define SIUMCR_DPPC00 0x00000000 /* Data Parity Pins Configuration*/
+#define SIUMCR_DPPC01 0x04000000 /* - " - */
+#define SIUMCR_DPPC10 0x08000000 /* - " - */
+#define SIUMCR_DPPC11 0x0c000000 /* - " - */
+#define SIUMCR_L2CPC00 0x00000000 /* L2 Cache Pins Configuration */
+#define SIUMCR_L2CPC01 0x01000000 /* - " - */
+#define SIUMCR_L2CPC10 0x02000000 /* - " - */
+#define SIUMCR_L2CPC11 0x03000000 /* - " - */
+#define SIUMCR_LBPC00 0x00000000 /* Local Bus Pins Configuration */
+#define SIUMCR_LBPC01 0x00400000 /* - " - */
+#define SIUMCR_LBPC10 0x00800000 /* - " - */
+#define SIUMCR_LBPC11 0x00c00000 /* - " - */
+#define SIUMCR_APPC00 0x00000000 /* Address Parity Pins Configuration*/
+#define SIUMCR_APPC01 0x00100000 /* - " - */
+#define SIUMCR_APPC10 0x00200000 /* - " - */
+#define SIUMCR_APPC11 0x00300000 /* - " - */
+#define SIUMCR_CS10PC00 0x00000000 /* CS10 Pin Configuration */
+#define SIUMCR_CS10PC01 0x00040000 /* - " - */
+#define SIUMCR_CS10PC10 0x00080000 /* - " - */
+#define SIUMCR_CS10PC11 0x000c0000 /* - " - */
+#define SIUMCR_BCTLC00 0x00000000 /* Buffer Control Configuration */
+#define SIUMCR_BCTLC01 0x00010000 /* - " - */
+#define SIUMCR_BCTLC10 0x00020000 /* - " - */
+#define SIUMCR_BCTLC11 0x00030000 /* - " - */
+#define SIUMCR_MMR00 0x00000000 /* Mask Masters Requests */
+#define SIUMCR_MMR01 0x00004000 /* - " - */
+#define SIUMCR_MMR10 0x00008000 /* - " - */
+#define SIUMCR_MMR11 0x0000c000 /* - " - */
+#define SIUMCR_LPBSE 0x00002000 /* LocalBus Parity Byte Select Enable*/
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock Control Register 9-8
+ */
+#define SCCR_PCI_MODE 0x00000100 /* PCI Mode */
+#define SCCR_PCI_MODCK 0x00000080 /* Value of PCI_MODCK pin */
+#define SCCR_PCIDF_MSK 0x00000078 /* PCI division factor */
+#define SCCR_PCIDF_SHIFT 3
+
+#endif
+
+#if defined(CONFIG_ADS8272)
+#define PCI_INT_TO_SIU SIU_INT_IRQ2
+#elif defined(CONFIG_PQ2FADS)
+#define PCI_INT_TO_SIU SIU_INT_IRQ6
+#else
+#warning PCI Bridge will be without interrupts support
+#endif
+
+#define POTA_ADDR_SHIFT 12
+#define PITA_ADDR_SHIFT 12
#define _IO_BASE PCI_MSTR_IO_LOCAL
#define _ISA_MEM_BASE PCI_MSTR_MEMIO_LOCAL
===== arch/ppc/syslib/Makefile 1.51 vs edited =====
--- 1.51/arch/ppc/syslib/Makefile 2005-03-31 14:59:04 +04:00
+++ edited/arch/ppc/syslib/Makefile 2005-04-12 16:47:50 +04:00
@@ -82,6 +82,9 @@
todc_time.o
obj-$(CONFIG_8260) += m8260_setup.o
obj-$(CONFIG_PCI_8260) += m8260_pci.o indirect_pci.o
+ifeq ($(CONFIG_ADS8272),y)
+obj-$(CONFIG_PCI) += pci_auto.o
+endif
obj-$(CONFIG_8260_PCI9) += m8260_pci_erratum9.o
obj-$(CONFIG_CPM2) += cpm2_common.o cpm2_pic.o
ifeq ($(CONFIG_PPC_GEN550),y)
===== arch/ppc/syslib/m8260_pci.c 1.2 vs edited =====
--- 1.2/arch/ppc/syslib/m8260_pci.c 2004-06-17 16:57:15 +04:00
+++ edited/arch/ppc/syslib/m8260_pci.c 2005-04-12 19:56:31 +04:00
@@ -1,4 +1,7 @@
/*
+ * 2005 (c) MontaVista Software, Inc.
+ * Vitaly Bordug <vbordug@ru.mvista.com>
+ *
* (C) Copyright 2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
@@ -28,6 +31,8 @@
#include <linux/pci.h>
#include <linux/slab.h>
#include <linux/delay.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
#include <asm/byteorder.h>
#include <asm/io.h>
@@ -38,12 +43,144 @@
#include <asm/immap_cpm2.h>
#include <asm/mpc8260.h>
+#if !defined(CONFIG_ADS8272) || !defined(CONFIG_PQ2FADS)
#include "m8260_pci.h"
+#endif
+
+/*
+ * Interrupt routing
+ */
+
+static inline int
+pq2pci_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
+{
+ static char pci_irq_table[][4] =
+ /*
+ * PCI IDSEL/INTPIN->INTLINE
+ * A B C D
+ */
+ {
+ { PIRQA, PIRQB, PIRQC, PIRQD }, /* IDSEL 22 - PCI slot 0 */
+ { PIRQD, PIRQA, PIRQB, PIRQC }, /* IDSEL 23 - PCI slot 1 */
+ { PIRQC, PIRQD, PIRQA, PIRQB }, /* IDSEL 24 - PCI slot 2 */
+ };
+
+ const long min_idsel = 22, max_idsel = 24, irqs_per_slot = 4;
+ return PCI_IRQ_TABLE_LOOKUP;
+}
+
+static void
+pq2pci_mask_irq(unsigned int irq)
+{
+ int bit = irq - NR_CPM_INTS;
+
+ *(volatile unsigned long *) PCI_INT_MASK_REG |= (1 << (31 - bit));
+ return;
+}
+
+static void
+pq2pci_unmask_irq(unsigned int irq)
+{
+ int bit = irq - NR_CPM_INTS;
+
+ *(volatile unsigned long *) PCI_INT_MASK_REG &= ~(1 << (31 - bit));
+ return;
+}
+
+static void
+pq2pci_mask_and_ack(unsigned int irq)
+{
+ int bit = irq - NR_CPM_INTS;
+
+ *(volatile unsigned long *) PCI_INT_MASK_REG |= (1 << (31 - bit));
+ return;
+}
+
+static void
+pq2pci_end_irq(unsigned int irq)
+{
+ int bit = irq - NR_CPM_INTS;
+
+ *(volatile unsigned long *) PCI_INT_MASK_REG &= ~(1 << (31 - bit));
+ return;
+}
+
+struct hw_interrupt_type pq2pci_ic = {
+ "PQ2 PCI",
+ NULL,
+ NULL,
+ pq2pci_unmask_irq,
+ pq2pci_mask_irq,
+ pq2pci_mask_and_ack,
+ pq2pci_end_irq,
+ 0
+};
+
+static irqreturn_t
+pq2pci_irq_demux(int irq, void *dev_id, struct pt_regs *regs)
+{
+ unsigned long stat, mask, pend;
+ int bit;
+
+ for(;;) {
+ stat = *(volatile unsigned long *) PCI_INT_STAT_REG;
+ mask = *(volatile unsigned long *) PCI_INT_MASK_REG;
+ pend = stat & ~mask & 0xf0000000;
+ if (!pend)
+ break;
+ for (bit = 0; pend != 0; ++bit, pend <<= 1) {
+ if (pend & 0x80000000)
+ __do_IRQ(NR_CPM_INTS + bit, regs);
+ }
+ }
+
+ return IRQ_HANDLED;
+}
+
+static struct irqaction pq2pci_irqaction = {
+ .handler = pq2pci_irq_demux,
+ .flags = SA_INTERRUPT,
+ .mask = CPU_MASK_NONE,
+ .name = "PQ2 PCI cascade",
+};
+
+
+void
+pq2pci_init_irq(void)
+{
+ int irq;
+ volatile cpm2_map_t *immap = cpm2_immr;
+#ifdef CONFIG_ADS8272
+ /* configure chip select for PCI interrupt controller */
+ immap->im_memctl.memc_br3 = PCI_INT_STAT_REG | 0x00001801;
+ immap->im_memctl.memc_or3 = 0xffff8010;
+#endif
+ for (irq = NR_CPM_INTS; irq < NR_CPM_INTS + 4; irq++)
+ irq_desc[irq].handler = &pq2pci_ic;
+
+ /* make PCI IRQ level sensitive */
+ immap->im_intctl.ic_siexr &=
+ ~(1 << (14 - (PCI_INT_TO_SIU - SIU_INT_IRQ1)));
+
+ /* mask all PCI interrupts */
+ *(volatile unsigned long *) PCI_INT_MASK_REG |= 0xfff00000;
+
+ /* install the demultiplexer for the PCI cascade interrupt */
+ setup_irq(PCI_INT_TO_SIU, &pq2pci_irqaction);
+ return;
+}
+
+static int
+pq2pci_exclude_device(u_char bus, u_char devfn)
+{
+ return PCIBIOS_SUCCESSFUL;
+}
/* PCI bus configuration registers.
*/
+#ifndef CONFIG_ADS8272
static void __init m8260_setup_pci(struct pci_controller *hose)
{
volatile cpm2_map_t *immap = cpm2_immr;
@@ -146,10 +283,148 @@
tempShort | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
}
-void __init m8260_find_bridges(void)
+#else /* setup hardware for 8272ADS and PQ2FADS */
+
+static void
+pq2ads_setup_pci(struct pci_controller *hose)
+{
+ __u32 val;
+ volatile cpm2_map_t *immap = cpm2_immr;
+ bd_t* binfo = (bd_t*) __res;
+ u32 sccr = immap->im_clkrst.car_sccr;
+ uint pci_div,freq,time;
+ /* PCI int lowest prio */
+ /* Each 4 bits is a device bus request and the MS 4bits
+ is highest priority */
+ /* Bus 4bit value
+ --- ----------
+ CPM high 0b0000
+ CPM middle 0b0001
+ CPM low 0b0010
+ PCI reguest 0b0011
+ Reserved 0b0100
+ Reserved 0b0101
+ Internal Core 0b0110
+ External Master 1 0b0111
+ External Master 2 0b1000
+ External Master 3 0b1001
+ The rest are reserved
+ */
+ immap->im_siu_conf.siu_82xx.sc_ppc_alrh = 0x61207893;
+ /* park bus on core */
+ immap->im_siu_conf.siu_82xx.sc_ppc_acr = PPC_ACR_BUS_PARK_CORE;
+ /*
+ * Set up master windows that allow the CPU to access PCI space. These
+ * windows are set up using the two SIU PCIBR registers.
+ */
+
+ immap->im_memctl.memc_pcimsk0 = ~(PCI_MSTR_IO_SIZE - 1U);
+ immap->im_memctl.memc_pcibr0 = PCI_MSTR_IO_LOCAL | PCIBR_ENABLE;
+
+ immap->im_memctl.memc_pcimsk1 = ~(PCI_MSTR_MEM_SIZE + PCI_MSTR_MEMIO_SIZE - 1U);
+ immap->im_memctl.memc_pcibr1 = PCI_MSTR_MEM_LOCAL | PCIBR_ENABLE;
+#ifdef CONFIG_ADS8272
+ immap->im_siu_conf.siu_82xx.sc_siumcr = (immap->im_siu_conf.siu_82xx.sc_siumcr &
+ ~SIUMCR_BBD &
+ ~SIUMCR_ESE &
+ ~SIUMCR_PBSE &
+ ~SIUMCR_CDIS &
+ ~SIUMCR_DPPC11 &
+ ~SIUMCR_L2CPC11 &
+ ~SIUMCR_LBPC11 &
+ ~SIUMCR_APPC11 &
+ ~SIUMCR_CS10PC11 &
+ ~SIUMCR_BCTLC11 &
+ ~SIUMCR_MMR11)
+ | SIUMCR_DPPC11 | SIUMCR_L2CPC01 | SIUMCR_LBPC00
+ | SIUMCR_APPC10 | SIUMCR_CS10PC00 | SIUMCR_BCTLC00 | SIUMCR_MMR11;
+#elif defined CONFIG_PQ2FADS
+ /*
+ * Setting required to enable IRQ1-IRQ7 (SIUMCR [DPPC]),
+ * and local bus for PCI (SIUMCR [LBPC]).
+ */
+ immap->im_siu_conf.siu_82xx.sc_siumcr = (immap->im_siu_conf.sc_siumcr &
+ ~SIUMCR_LBPC11 &
+ ~SIUMCR_CS10PC11 &
+ ~SIUMCR_LBPC11) |
+ SIUMCR_LBPC01 | SIUMCR_CS10PC01 | SIUMCR_APPC10;
+#endif
+ /* Enable PCI */
+ immap->im_pci.pci_gcr = cpu_to_le32(PCIGCR_PCI_BUS_EN);
+
+ pci_div = ( (sccr & SCCR_PCI_MODCK) ? 2 : 1) *
+ ( ( (sccr & SCCR_PCIDF_MSK) >> SCCR_PCIDF_SHIFT) + 1);
+ freq = (uint)((2*binfo->bi_cpmfreq)/(pci_div));
+ time = (int)666666/freq;
+ /* due to PCI Local Bus spec, some devices needs to wait such a long
+ time after RST deassertion. More specifically, 0.508s for 66MHz & twice more for 33 */
+ printk("%s: The PCI bus is %d Mhz.\nWaiting %s after deasserting RST...\n",__FILE__,freq,
+ (time==1) ? "0.5 seconds":"1 second" );
+
+ {
+ int i;
+ for(i=0;i<(500*time);i++)
+ udelay(1000);
+ }
+
+ /* setup ATU registers */
+ immap->im_pci.pci_pocmr0 = cpu_to_le32(POCMR_ENABLE | POCMR_PCI_IO |
+ ((~(PCI_MSTR_IO_SIZE - 1U)) >> POTA_ADDR_SHIFT));
+ immap->im_pci.pci_potar0 = cpu_to_le32(PCI_MSTR_IO_BUS >> POTA_ADDR_SHIFT);
+ immap->im_pci.pci_pobar0 = cpu_to_le32(PCI_MSTR_IO_LOCAL >> POTA_ADDR_SHIFT);
+
+ /* Set-up non-prefetchable window */
+ immap->im_pci.pci_pocmr1 = cpu_to_le32(POCMR_ENABLE | ((~(PCI_MSTR_MEMIO_SIZE-1U)) >> POTA_ADDR_SHIFT));
+ immap->im_pci.pci_potar1 = cpu_to_le32(PCI_MSTR_MEMIO_BUS >> POTA_ADDR_SHIFT);
+ immap->im_pci.pci_pobar1 = cpu_to_le32(PCI_MSTR_MEMIO_LOCAL >> POTA_ADDR_SHIFT);
+
+ /* Set-up prefetchable window */
+ immap->im_pci.pci_pocmr2 = cpu_to_le32(POCMR_ENABLE |POCMR_PREFETCH_EN |
+ (~(PCI_MSTR_MEM_SIZE-1U) >> POTA_ADDR_SHIFT));
+ immap->im_pci.pci_potar2 = cpu_to_le32((PCI_MSTR_MEM_BUS) >> POTA_ADDR_SHIFT);
+ immap->im_pci.pci_pobar2 = cpu_to_le32((PCI_MSTR_MEM_LOCAL) >> POTA_ADDR_SHIFT);
+
+ /* Inbound transactions from PCI memory space */
+ immap->im_pci.pci_picmr0 = cpu_to_le32(PICMR_ENABLE | PICMR_PREFETCH_EN |
+ ((~(PCI_SLV_MEM_SIZE-1U)) >> PITA_ADDR_SHIFT));
+ immap->im_pci.pci_pibar0 = cpu_to_le32(PCI_SLV_MEM_BUS >> PITA_ADDR_SHIFT);
+ immap->im_pci.pci_pitar0 = cpu_to_le32(PCI_SLV_MEM_LOCAL>> PITA_ADDR_SHIFT);
+
+#if defined CONFIG_ADS8272
+ /* PCI int highest prio */
+ immap->im_siu_conf.siu_82xx.sc_ppc_alrh = 0x01236745;
+#elif defined CONFIG_PQ2FADS
+ immap->im_siu_conf.siu_82xx.sc_ppc_alrh = 0x03124567;
+#endif
+ /* park bus on PCI */
+ immap->im_siu_conf.siu_82xx.sc_ppc_acr = PPC_ACR_BUS_PARK_PCI;
+
+ /* Enable bus mastering and inbound memory transactions */
+ early_read_config_dword(hose, hose->first_busno, 0, PCI_COMMAND, &val);
+ val &= 0xffff0000;
+ val |= PCI_COMMAND_MEMORY|PCI_COMMAND_MASTER;
+ early_write_config_dword(hose, hose->first_busno, 0, PCI_COMMAND, val);
+
+}
+
+static void pq2ads_setup_hose(struct pci_controller * hose)
+{
+ hose->io_space.start = MPC826x_PCI_LOWER_IO;
+ hose->io_space.end = MPC826x_PCI_UPPER_IO;
+ hose->mem_space.start = MPC826x_PCI_LOWER_MEM;
+ hose->mem_space.end = MPC826x_PCI_UPPER_MMIO;
+ hose->io_base_virt = (void*)MPC826x_PCI_IO_BASE;
+ isa_io_base = MPC826x_PCI_IO_BASE;
+}
+
+#endif
+
+
+void __init pq2_find_bridges(void)
{
extern int pci_assign_all_busses;
struct pci_controller * hose;
+ int host_bridge;
pci_assign_all_busses = 1;
@@ -164,18 +439,45 @@
hose->bus_offset = 0;
hose->last_busno = 0xff;
+#ifdef CONFIG_ADS8272
+ hose->set_cfg_type = 1;
+#endif
+
setup_m8260_indirect_pci(hose,
(unsigned long)&cpm2_immr->im_pci.pci_cfg_addr,
(unsigned long)&cpm2_immr->im_pci.pci_cfg_data);
+ /* Make sure it is a supported bridge */
+ early_read_config_dword(hose,
+ 0,
+ PCI_DEVFN(0,0),
+ PCI_VENDOR_ID,
+ &host_bridge);
+ switch (host_bridge) {
+ case PCI_DEVICE_ID_MPC8265:
+ break;
+ case PCI_DEVICE_ID_MPC8272:
+ break;
+ default:
+ printk("Attempting to use unrecognized host bridge ID"
+ " 0x%08x.\n", host_bridge);
+ break;
+ }
+
+#if defined(CONFIG_ADS8272) || defined(CONFIG_PQ2FADS)
+ pq2ads_setup_pci(hose);
+ pq2ads_setup_hose(hose);
+#else
m8260_setup_pci(hose);
+
hose->pci_mem_offset = MPC826x_PCI_MEM_OFFSET;
- isa_io_base =
+ isa_io_base =
(unsigned long) ioremap(MPC826x_PCI_IO_BASE,
MPC826x_PCI_IO_SIZE);
hose->io_base_virt = (void *) isa_io_base;
-
+#endif
+
/* setup resources */
pci_init_resource(&hose->mem_resources[0],
MPC826x_PCI_LOWER_MEM,
@@ -191,4 +493,15 @@
MPC826x_PCI_LOWER_IO,
MPC826x_PCI_UPPER_IO,
IORESOURCE_IO, "PCI I/O");
+
+#if defined(CONFIG_ADS8272) || defined(CONFIG_PQ2FADS)
+ ppc_md.pci_exclude_device = pq2pci_exclude_device;
+ hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
+
+ ppc_md.pci_map_irq = pq2pci_map_irq;
+ ppc_md.pcibios_fixup = NULL;
+ ppc_md.pcibios_fixup_bus = NULL;
+
+#endif
+
}
===== arch/ppc/syslib/m8260_setup.c 1.30 vs edited =====
--- 1.30/arch/ppc/syslib/m8260_setup.c 2005-03-31 14:59:04 +04:00
+++ edited/arch/ppc/syslib/m8260_setup.c 2005-04-12 16:47:51 +04:00
@@ -34,7 +34,8 @@
unsigned char __res[sizeof(bd_t)];
extern void cpm2_reset(void);
-extern void m8260_find_bridges(void);
+extern void pq2_find_bridges(void);
+extern void pq2pci_init_irq(void);
extern void idma_pci9_init(void);
/* Place-holder for board-specific init */
@@ -56,7 +57,11 @@
idma_pci9_init();
#endif
#ifdef CONFIG_PCI_8260
+#if defined(CONFIG_ADS8272) || defined(CONFIG_PQ2FADS)
+ pq2_find_bridges();
+#else
m8260_find_bridges();
+#endif
#endif
#ifdef CONFIG_BLK_DEV_INITRD
if (initrd_start)
@@ -173,6 +178,12 @@
* in case the boot rom changed something on us.
*/
cpm2_immr->im_intctl.ic_siprr = 0x05309770;
+
+#if defined(CONFIG_PCI) && (defined(CONFIG_ADS8272) || defined(CONFIG_ADS8272))
+ /* Initialize stuff for the 82xx CPLD IC and install demux */
+ pq2pci_init_irq();
+#endif
+
}
/*
@@ -195,6 +206,9 @@
m8260_map_io(void)
{
uint addr;
+#if defined(CONFIG_PCI) && (defined(CONFIG_ADS8272) || defined(CONFIG_ADS8272))
+ io_block_mapping(0x80000000,0x80000000,0x10000000, _PAGE_IO);
+#endif
/* Map IMMR region to a 256MB BAT */
addr = (cpm2_immr != NULL) ? (uint)cpm2_immr : CPM_MAP_ADDR;
===== include/asm-ppc/m8260_pci.h 1.1 vs edited =====
--- 1.1/include/asm-ppc/m8260_pci.h 2004-06-17 02:56:05 +04:00
+++ edited/include/asm-ppc/m8260_pci.h 2005-04-12 17:17:29 +04:00
@@ -19,6 +19,7 @@
* Define the vendor/device ID for the MPC8265.
*/
#define PCI_DEVICE_ID_MPC8265 ((0x18C0 << 16) | PCI_VENDOR_ID_MOTOROLA)
+#define PCI_DEVICE_ID_MPC8272 ((0x18C1 << 16) | PCI_VENDOR_ID_MOTOROLA)
#define M8265_PCIBR0 0x101ac
#define M8265_PCIBR1 0x101b0
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