* Re: [PATCH][5/5] RapidIO support: net driver over messaging
From: Matt Porter @ 2005-07-27 13:56 UTC (permalink / raw)
To: Avni Hillel-R58467; +Cc: 'linuxppc-embedded@ozlabs.org'
In-Reply-To: <D39C8B3D64A0D511A61E00D0B7828EEA0C0764FD@zil05exm01.ea.freescale.net>
On Wed, Jul 27, 2005 at 01:36:15PM +0300, Avni Hillel-R58467 wrote:
> Hi Matt,
>
> Two questions:
>
> A. How can a node (not the host) know who is in the rionet to broadcast to them?
All nodes in the rionet are flagged in the active peer list. There is an
active peer list kept for the rionet instance on _each node_. There is
no distinction as to whether a node was the winning enumerating host or
is just another processing element that found devices in the system via
passing discovery. The only inherently significant about a "host" in
RapidIO is that it participates in enumeration. After the system is
enumerated it's no longer special (unless your particular system
application designates the hosts have some special network-wide
ownership of resources or something).
Broadcast works the same way on all nodes by sending the same packet
to every node in the active peer list.
> B. How do you emulate broadcasting to all the mailboxes, in multi mbox systems? Is this done by the node getting the broadcast in MB 0 and forwarding it to the other MBs?
rionet doesn't handle multiple mailboxes yet.
However, it becomes tricky because we don't want to bridge separate
Ethernet networks by policy in the driver. If two mailboxes are
part of separate rio device trees, then it doesn't make sense to send
broadcasts out on both mailboxes. It needs some thought and also
docs on how new silicon might be implementing queues in new mailboxes.
With RIO, there's so much left to be implementation specific in the
silicon. It did not make sense to make assumptions and try to
handle multiple mailboxes. If you have a multi mbox system it would
help to have a description so we can work to support it.
-Matt
^ permalink raw reply
* custom ads8272 board PCI interrupt no response
From: Sam Song @ 2005-07-27 13:52 UTC (permalink / raw)
To: linuxppc-embedded
Hi all,
A PCI interrupt probelm confused me when porting
2.6.13-rc3 on a custom 8248 board. There was a
Gb ethernet RTL8110S on board with IDSEL AD25 and
IRQ3. So I made some changes as follows:
--- linux-2.6.13-rc3/arch/ppc/platforms/pq2ads.h
+++ linux-2.6.13-rc3-sam/arch/ppc/platforms/pq2ads.h
@@ -74,11 +78,11 @@
-#define PCI_INT_TO_SIU SIU_INT_IRQ2
+#define PCI_INT_TO_SIU SIU_INT_IRQ3
--- linux-2.6.13-rc3/arch/ppc/syslib/m82xx_pci.c
+++ linux-2.6.13-rc3-sam/arch/ppc/syslib/m82xx_pci.c
@@ -60,12 +60,20 @@
* A B C D
*/
{
+#if 0
{ PIRQA, PIRQB, PIRQC, PIRQD },/* IDSEL 22 - PCI
slot 0 */
{ PIRQD, PIRQA, PIRQB, PIRQC }, /* IDSEL 23 - PCI
slot 1 */
{ PIRQC, PIRQD, PIRQA, PIRQB }, /* IDSEL 24 - PCI
slot 2 */
+#else
+ {22, 22, 22, 22},/* IDSEL 22/IRQ4-PCI slot 0-USB */
+ {23, 23, 23, 23},/* IDSEL 23/IRQ5-PCI slot 1-IDE */
+ {24, 24, 0, 0},/* IDSEL 24 - PCI slot # - NULL */
+ {25, 25, 25, 25},/* IDSEL 25/IRQ3-PCI slot 2- Gb */
+
+#endif
};
- const long min_idsel = 22, max_idsel = 24,
irqs_per_slot = 4;
+ const long min_idsel = 22, max_idsel = 25,
irqs_per_slot = 4;
Then got a interrupt map:
# cat /proc/interrupts
CPU0
21: 0 CPM2 SIU Level PQ2 PCI cascade
25: 0 CPM2 SIU Level eth0
40: 14 CPM2 SIU Level cpm_uart
BAD: 2
Gb interrupt remained unchangable in the whole test
process. I could ping target itself but not for
outside machine. So I suspect this result was due to
PCI interrupt setting but don't know where the probelm
is. Any idea?
Thanks in advance,
Sam
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^ permalink raw reply
* Re: [PATCH] Support for AMCC Yosemite 440EP Eval Board
From: Stefan Roese @ 2005-07-27 13:47 UTC (permalink / raw)
To: linuxppc-embedded; +Cc: John Otken
In-Reply-To: <42E776DD.9080307@softadvances.com>
Hi John,
On Wednesday 27 July 2005 13:58, John Otken wrote:
> This patch adds support for the new AMCC Yosemite 440EP Eval
> Board. I tested it on the both Bamboo and Yosemite boards
> using the 2.6.12 kernel.
How about a patch against a more recent kernel?
> This patch has three dependencies:
> 2005-04-07 Wade Farnsworth's PPC440EP SoC and Bamboo board support
Please use the patches Wade sent yesterday to this list.
> 2005-07-20 My fix invalid function name usb_hcd_put in ohci-ppc-soc.c
> 2005-07-27 My Support 440EP On-Chip OHCI USB Host Controller
>
> http://patchwork.ozlabs.org/linuxppc/patch?id=1311
> http://patchwork.ozlabs.org/linuxppc/patch?id=1803
> http://patchwork.ozlabs.org/linuxppc/patch?id=1855
>
> Comments are welcome.
OK, here we go...
<snip>
> diff -uprN c/arch/ppc/platforms/4xx/bamboo.c
> d/arch/ppc/platforms/4xx/bamboo.c ---
> c/arch/ppc/platforms/4xx/bamboo.c 2005-07-25 06:34:52.000000000 -0500 +++
> d/arch/ppc/platforms/4xx/bamboo.c 2005-07-26 10:31:37.000000000 -0500 @@
> -59,6 +59,20 @@
> */
> #include "../../../../drivers/net/ibm_emac/ibm_emac_phy.h"
>
> +#if defined(CONFIG_BAMBOO)
> +static const int bamboo = 1;
> +static const char cpu_name[] = {"440EP"};
> +static const char brd_name[] = {"Bamboo"};
> +#elif defined(CONFIG_YELLOWSTONE)
> +static const int bamboo = 0;
> +static const char cpu_name[] = {"440GR"};
> +static const char brd_name[] = {"Yellowstone"};
> +#else
> +static const int bamboo = 0;
> +static const char cpu_name[] = {"440EP"};
> +static const char brd_name[] = {"Yosemite"};
> +#endif
> +
Hmmm. You seem to include not only the Yosemite but also the Yellowstone with
a different processor type (440GR) into the bamboo platform file. I would
prefer seperate platform files for the different boards, especially since the
differences are not marginal.
<snip>
> diff -uprN c/arch/ppc/platforms/4xx/Makefile
> d/arch/ppc/platforms/4xx/Makefile ---
> c/arch/ppc/platforms/4xx/Makefile 2005-07-24 16:14:36.000000000 -0500 +++
> d/arch/ppc/platforms/4xx/Makefile 2005-07-26 10:51:35.000000000 -0500 @@
> -15,6 +15,7 @@ obj-$(CONFIG_REDWOOD_6) += redwood6.o
> obj-$(CONFIG_SYCAMORE) += sycamore.o
> obj-$(CONFIG_WALNUT) += walnut.o
> obj-$(CONFIG_XILINX_ML300) += xilinx_ml300.o
> +obj-$(CONFIG_YOSEMITE) += bamboo.o
Please see above.
Best regards,
Stefan
^ permalink raw reply
* [PATCH] Support for AMCC Yosemite 440EP Eval Board
From: John Otken @ 2005-07-27 11:58 UTC (permalink / raw)
To: linuxppc-embedded
This patch adds support for the new AMCC Yosemite 440EP Eval
Board. I tested it on the both Bamboo and Yosemite boards
using the 2.6.12 kernel.
This patch has three dependencies:
2005-04-07 Wade Farnsworth's PPC440EP SoC and Bamboo board support
2005-07-20 My fix invalid function name usb_hcd_put in ohci-ppc-soc.c
2005-07-27 My Support 440EP On-Chip OHCI USB Host Controller
http://patchwork.ozlabs.org/linuxppc/patch?id=1311
http://patchwork.ozlabs.org/linuxppc/patch?id=1803
http://patchwork.ozlabs.org/linuxppc/patch?id=1855
Comments are welcome.
Signed-off-by: John Otken <jotken@softadvances.com>
diff -uprN c/arch/ppc/configs/yosemite_defconfig d/arch/ppc/configs/yosemite_defconfig
--- c/arch/ppc/configs/yosemite_defconfig 1969-12-31 17:00:00.000000000 -0700
+++ d/arch/ppc/configs/yosemite_defconfig 2005-07-26 09:49:51.000000000 -0500
@@ -0,0 +1,874 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.12
+# Wed Jul 13 20:59:13 2005
+#
+CONFIG_MMU=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_RWSEM_XCHGADD_ALGORITHM=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_HAVE_DEC_LOCK=y
+CONFIG_PPC=y
+CONFIG_PPC32=y
+CONFIG_GENERIC_NVRAM=y
+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_CLEAN_COMPILE=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+
+#
+# General setup
+#
+CONFIG_LOCALVERSION=""
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_SYSCTL=y
+# CONFIG_AUDIT is not set
+# CONFIG_HOTPLUG is not set
+CONFIG_KOBJECT_UEVENT=y
+# CONFIG_IKCONFIG is not set
+CONFIG_EMBEDDED=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SHMEM=y
+CONFIG_CC_ALIGN_FUNCTIONS=0
+CONFIG_CC_ALIGN_LABELS=0
+CONFIG_CC_ALIGN_LOOPS=0
+CONFIG_CC_ALIGN_JUMPS=0
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+
+#
+# Loadable module support
+#
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+CONFIG_OBSOLETE_MODPARM=y
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
+
+#
+# Processor
+#
+# CONFIG_6xx is not set
+# CONFIG_40x is not set
+CONFIG_44x=y
+# CONFIG_POWER3 is not set
+# CONFIG_POWER4 is not set
+# CONFIG_8xx is not set
+# CONFIG_E500 is not set
+CONFIG_PPC_FPU=y
+CONFIG_BOOKE=y
+CONFIG_PTE_64BIT=y
+CONFIG_PHYS_64BIT=y
+# CONFIG_MATH_EMULATION is not set
+# CONFIG_CPU_FREQ is not set
+CONFIG_4xx=y
+
+#
+# IBM 4xx options
+#
+# CONFIG_BAMBOO is not set
+# CONFIG_EBONY is not set
+# CONFIG_LUAN is not set
+# CONFIG_OCOTEA is not set
+# CONFIG_YELLOWSTONE is not set
+CONFIG_YOSEMITE=y
+CONFIG_440EP=y
+CONFIG_440_FPU=y
+CONFIG_IBM440EP_ERR42=y
+CONFIG_IBM_OCP=y
+# CONFIG_PPC4xx_DMA is not set
+CONFIG_PPC_GEN550=y
+# CONFIG_PM is not set
+CONFIG_NOT_COHERENT_CACHE=y
+
+#
+# Platform options
+#
+# CONFIG_PC_KEYBOARD is not set
+# CONFIG_SMP is not set
+# CONFIG_PREEMPT is not set
+# CONFIG_HIGHMEM is not set
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+CONFIG_CMDLINE_BOOL=y
+CONFIG_CMDLINE="ip=on root=/dev/ram rw ramdisk=49152"
+CONFIG_ISA_DMA_API=y
+
+#
+# Bus options
+#
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+# CONFIG_PCI_LEGACY_PROC is not set
+# CONFIG_PCI_NAMES is not set
+# CONFIG_PCI_DEBUG is not set
+
+#
+# PCCARD (PCMCIA/CardBus) support
+#
+# CONFIG_PCCARD is not set
+
+#
+# Advanced setup
+#
+# CONFIG_ADVANCED_OPTIONS is not set
+
+#
+# Default settings for advanced configuration options are used
+#
+CONFIG_HIGHMEM_START=0xfe000000
+CONFIG_LOWMEM_SIZE=0x30000000
+CONFIG_KERNEL_START=0xc0000000
+CONFIG_TASK_SIZE=0x80000000
+CONFIG_CONSISTENT_START=0xff100000
+CONFIG_CONSISTENT_SIZE=0x00200000
+CONFIG_BOOT_LOAD=0x01000000
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+# CONFIG_STANDALONE is not set
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_FW_LOADER is not set
+# CONFIG_DEBUG_DRIVER is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+# CONFIG_MTD is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Plug and Play support
+#
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_SX8 is not set
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=4096
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_LBD is not set
+# CONFIG_CDROM_PKTCDVD is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_ATA_OVER_ETH is not set
+
+#
+# ATA/ATAPI/MFM/RLL support
+#
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+CONFIG_SCSI=y
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+
+#
+# SCSI Transport Attributes
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+
+#
+# SCSI low-level drivers
+#
+# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
+# CONFIG_SCSI_3W_9XXX is not set
+# CONFIG_SCSI_ACARD is not set
+# CONFIG_SCSI_AACRAID is not set
+# CONFIG_SCSI_AIC7XXX is not set
+# CONFIG_SCSI_AIC7XXX_OLD is not set
+# CONFIG_SCSI_AIC79XX is not set
+# CONFIG_SCSI_DPT_I2O is not set
+# CONFIG_MEGARAID_NEWGEN is not set
+# CONFIG_MEGARAID_LEGACY is not set
+# CONFIG_SCSI_SATA is not set
+# CONFIG_SCSI_BUSLOGIC is not set
+# CONFIG_SCSI_DMX3191D is not set
+# CONFIG_SCSI_EATA is not set
+# CONFIG_SCSI_FUTURE_DOMAIN is not set
+# CONFIG_SCSI_GDTH is not set
+# CONFIG_SCSI_IPS is not set
+# CONFIG_SCSI_INITIO is not set
+# CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_SYM53C8XX_2 is not set
+# CONFIG_SCSI_IPR is not set
+# CONFIG_SCSI_QLOGIC_FC is not set
+# CONFIG_SCSI_QLOGIC_1280 is not set
+CONFIG_SCSI_QLA2XXX=y
+# CONFIG_SCSI_QLA21XX is not set
+# CONFIG_SCSI_QLA22XX is not set
+# CONFIG_SCSI_QLA2300 is not set
+# CONFIG_SCSI_QLA2322 is not set
+# CONFIG_SCSI_QLA6312 is not set
+# CONFIG_SCSI_LPFC is not set
+# CONFIG_SCSI_DC395x is not set
+# CONFIG_SCSI_DC390T is not set
+# CONFIG_SCSI_NSP32 is not set
+# CONFIG_SCSI_DEBUG is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+
+#
+# Fusion MPT device support
+#
+# CONFIG_FUSION is not set
+
+#
+# IEEE 1394 (FireWire) support
+#
+# CONFIG_IEEE1394 is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+
+#
+# Macintosh device drivers
+#
+
+#
+# Networking support
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_IP_TCPDIAG=y
+# CONFIG_IP_TCPDIAG_IPV6 is not set
+
+#
+# IP: Virtual Server Configuration
+#
+# CONFIG_IP_VS is not set
+# CONFIG_IPV6 is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+
+#
+# IP: Netfilter Configuration
+#
+# CONFIG_IP_NF_CONNTRACK is not set
+# CONFIG_IP_NF_CONNTRACK_MARK is not set
+# CONFIG_IP_NF_QUEUE is not set
+# CONFIG_IP_NF_IPTABLES is not set
+# CONFIG_IP_NF_ARPTABLES is not set
+
+#
+# SCTP Configuration (EXPERIMENTAL)
+#
+# CONFIG_IP_SCTP is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+# CONFIG_NET_CLS_ROUTE is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+
+#
+# ARCnet devices
+#
+# CONFIG_ARCNET is not set
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_NET_VENDOR_3COM is not set
+
+#
+# Tulip family network device support
+#
+# CONFIG_NET_TULIP is not set
+# CONFIG_HP100 is not set
+CONFIG_IBM_EMAC=y
+# CONFIG_IBM_EMAC_ERRMSG is not set
+CONFIG_IBM_EMAC_RXB=128
+CONFIG_IBM_EMAC_TXB=128
+CONFIG_IBM_EMAC_FGAP=8
+CONFIG_IBM_EMAC_SKBRES=0
+# CONFIG_NET_PCI is not set
+
+#
+# Ethernet (1000 Mbit)
+#
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_E1000 is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_R8169 is not set
+# CONFIG_SK98LIN is not set
+# CONFIG_TIGON3 is not set
+# CONFIG_BNX2 is not set
+
+#
+# Ethernet (10000 Mbit)
+#
+# CONFIG_IXGB is not set
+# CONFIG_S2IO is not set
+
+#
+# Token Ring devices
+#
+# CONFIG_TR is not set
+
+#
+# Wireless LAN (non-hamradio)
+#
+# CONFIG_NET_RADIO is not set
+
+#
+# Wan interfaces
+#
+# CONFIG_WAN is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NET_FC is not set
+# CONFIG_SHAPER is not set
+# CONFIG_NETCONSOLE is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# Telephony Support
+#
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+# CONFIG_INPUT is not set
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+# CONFIG_SERIO_I8042 is not set
+# CONFIG_SERIO_SERPORT is not set
+# CONFIG_SERIO_PCIPS2 is not set
+# CONFIG_SERIO_LIBPS2 is not set
+# CONFIG_SERIO_RAW is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_EXTENDED=y
+# CONFIG_SERIAL_8250_MANY_PORTS is not set
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+# CONFIG_SERIAL_8250_DETECT_IRQ is not set
+# CONFIG_SERIAL_8250_MULTIPORT is not set
+# CONFIG_SERIAL_8250_RSA is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_JSM is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+
+#
+# IPMI
+#
+# CONFIG_IPMI_HANDLER is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_NVRAM is not set
+# CONFIG_GEN_RTC is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_RAW_DRIVER is not set
+
+#
+# TPM devices
+#
+# CONFIG_TCG_TPM is not set
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# Dallas's 1-wire bus
+#
+# CONFIG_W1 is not set
+
+#
+# Misc devices
+#
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# Digital Video Broadcasting Devices
+#
+# CONFIG_DVB is not set
+
+#
+# Graphics support
+#
+# CONFIG_FB is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+CONFIG_USB=y
+CONFIG_USB_DEBUG=y
+
+#
+# Miscellaneous USB options
+#
+# CONFIG_USB_DEVICEFS is not set
+# CONFIG_USB_BANDWIDTH is not set
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_OTG is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_EHCI_HCD is not set
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_HCD_PPC_SOC=y
+CONFIG_USB_OHCI_BIG_ENDIAN=y
+# CONFIG_USB_OHCI_LITTLE_ENDIAN is not set
+# CONFIG_USB_UHCI_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_BLUETOOTH_TTY is not set
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+
+#
+# USB Input Devices
+#
+# CONFIG_USB_HID is not set
+
+#
+# USB HID Boot Protocol drivers
+#
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB Multimedia devices
+#
+# CONFIG_USB_DABUSB is not set
+
+#
+# Video4Linux support is needed for USB Multimedia device support
+#
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
+CONFIG_USB_MON=y
+
+#
+# USB port drivers
+#
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_AUERSWALD is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_PHIDGETKIT is not set
+# CONFIG_USB_PHIDGETSERVO is not set
+# CONFIG_USB_IDMOUSE is not set
+
+#
+# USB ATM/DSL drivers
+#
+
+#
+# USB Gadget Support
+#
+# CONFIG_USB_GADGET is not set
+
+#
+# MMC/SD Card support
+#
+# CONFIG_MMC is not set
+
+#
+# InfiniBand support
+#
+# CONFIG_INFINIBAND is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_JBD is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+
+#
+# XFS support
+#
+# CONFIG_XFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_QUOTA is not set
+CONFIG_DNOTIFY=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_SYSFS=y
+# CONFIG_DEVFS_FS is not set
+# CONFIG_DEVPTS_FS_XATTR is not set
+CONFIG_TMPFS=y
+CONFIG_TMPFS_XATTR=y
+# CONFIG_TMPFS_SECURITY is not set
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_RAMFS=y
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+
+#
+# Network File Systems
+#
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V4 is not set
+# CONFIG_NFS_DIRECTIO is not set
+# CONFIG_NFSD is not set
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_SUNRPC=y
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+
+#
+# Native Language Support
+#
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+
+#
+# Library routines
+#
+# CONFIG_CRC_CCITT is not set
+CONFIG_CRC32=y
+# CONFIG_LIBCRC32C is not set
+
+#
+# Profiling support
+#
+# CONFIG_PROFILING is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_MAGIC_SYSRQ is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_KOBJECT is not set
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_FS is not set
+# CONFIG_KGDB is not set
+# CONFIG_XMON is not set
+CONFIG_BDI_SWITCH=y
+# CONFIG_SERIAL_TEXT_DEBUG is not set
+CONFIG_PPC_OCP=y
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+
+#
+# Cryptographic options
+#
+# CONFIG_CRYPTO is not set
+
+#
+# Hardware crypto devices
+#
diff -uprN c/arch/ppc/platforms/4xx/bamboo.c d/arch/ppc/platforms/4xx/bamboo.c
--- c/arch/ppc/platforms/4xx/bamboo.c 2005-07-25 06:34:52.000000000 -0500
+++ d/arch/ppc/platforms/4xx/bamboo.c 2005-07-26 10:31:37.000000000 -0500
@@ -59,6 +59,20 @@
*/
#include "../../../../drivers/net/ibm_emac/ibm_emac_phy.h"
+#if defined(CONFIG_BAMBOO)
+static const int bamboo = 1;
+static const char cpu_name[] = {"440EP"};
+static const char brd_name[] = {"Bamboo"};
+#elif defined(CONFIG_YELLOWSTONE)
+static const int bamboo = 0;
+static const char cpu_name[] = {"440GR"};
+static const char brd_name[] = {"Yellowstone"};
+#else
+static const int bamboo = 0;
+static const char cpu_name[] = {"440EP"};
+static const char brd_name[] = {"Yosemite"};
+#endif
+
bd_t __res;
static struct ibm44x_clocks clocks __initdata;
@@ -85,19 +99,18 @@ bamboo_calibrate_decr(void)
unsigned int freq;
if (mfspr(SPRN_CCR1) & CCR1_TCS)
- freq = BAMBOO_TMRCLK;
+ freq = bamboo ? BAMBOO_TMRCLK : YOSEMITE_TMRCLK;
else
freq = clocks.cpu;
ibm44x_calibrate_decr(freq);
-
}
static int
bamboo_show_cpuinfo(struct seq_file *m)
{
- seq_printf(m, "vendor\t\t: IBM\n");
- seq_printf(m, "machine\t\t: PPC440EP EVB (Bamboo)\n");
+ seq_printf(m, "vendor\t\t: AMCC\n");
+ seq_printf(m, "machine\t\t: PPC %s EVB (%s)\n", cpu_name, brd_name);
return 0;
}
@@ -127,17 +140,20 @@ static void __init bamboo_set_emacdata(v
struct ocp_def *def;
struct ocp_func_emac_data *emacdata;
u8 selection1_val;
- int mode;
-
- selection1_base = ioremap64(BAMBOO_FPGA_SELECTION1_REG_ADDR, 16);
- selection1_val = readb(selection1_base);
- iounmap((void *) selection1_base);
- if (BAMBOO_SEL_MII(selection1_val))
- mode = PHY_MODE_MII;
- else if (BAMBOO_SEL_RMII(selection1_val))
- mode = PHY_MODE_RMII;
- else
- mode = PHY_MODE_SMII;
+ int mode = PHY_MODE_RMII; /* default to RMII for yosemite */
+
+ if (bamboo) /* if bamboo board */
+ {
+ selection1_base = ioremap64(BAMBOO_FPGA_SELECTION1_REG_ADDR, 16);
+ selection1_val = readb(selection1_base);
+ iounmap((void *) selection1_base);
+ if (BAMBOO_SEL_MII(selection1_val))
+ mode = PHY_MODE_MII;
+ else if (BAMBOO_SEL_RMII(selection1_val))
+ mode = PHY_MODE_RMII;
+ else
+ mode = PHY_MODE_SMII;
+ }
/* Set mac_addr and phy mode for each EMAC */
@@ -367,15 +383,19 @@ bamboo_setup_arch(void)
* from FPGA, because it can be changed by on-board switches
* --ebs
*/
- ibm440gx_get_clocks(&clocks, 33333333, 6 * 1843200);
+ ibm440gx_get_clocks(&clocks, bamboo ? BAMBOO_SYSCLK : YOSEMITE_SYSCLK,
+ 6 * 1843200);
ocp_sys_info.opb_bus_freq = clocks.opb;
- /* Setup TODC access */
- TODC_INIT(TODC_TYPE_DS1743,
+ if (bamboo) /* if bamboo board */
+ {
+ /* Setup TODC access */
+ TODC_INIT(TODC_TYPE_DS1743,
0,
0,
ioremap64(BAMBOO_RTC_ADDR, BAMBOO_RTC_SIZE),
8);
+ }
/* init to some ~sane value until calibrate_delay() runs */
loops_per_jiffy = 50000000/HZ;
@@ -397,7 +417,11 @@ bamboo_setup_arch(void)
bamboo_early_serial_map();
/* Identify the system */
- printk("IBM Bamboo port (MontaVista Software, Inc. (source@mvista.com))\n");
+ printk("AMCC PowerPC %s %s Platform"
+#ifdef CONFIG_BAMBOO
+ " (MontaVista Software, Inc. (source@mvista.com))"
+#endif
+ "\n", cpu_name, brd_name);
}
void __init platform_init(unsigned long r3, unsigned long r4,
@@ -412,7 +436,26 @@ void __init platform_init(unsigned long
if (r3)
__res = *(bd_t *)(r3 + KERNELBASE);
- ibm440gx_get_clocks(&clocks, 33333333, 6 * 1843200);
+#if defined(CONFIG_BLK_DEV_INITRD)
+ /*
+ * If the init RAM disk has been configured in, and there's a valid
+ * starting address for it, set it up.
+ */
+ if (r4) {
+ initrd_start = r4 + KERNELBASE;
+ initrd_end = r5 + KERNELBASE;
+ }
+#endif /* CONFIG_BLK_DEV_INITRD */
+
+ /* Copy the kernel command line arguments to a safe place. */
+
+ if (r6) {
+ *(char *) (r7 + KERNELBASE) = 0;
+ strcpy(cmd_line, (char *) (r6 + KERNELBASE));
+ }
+
+ ibm440gx_get_clocks(&clocks, bamboo ? BAMBOO_SYSCLK : YOSEMITE_SYSCLK,
+ 6 * 1843200);
ocp_sys_info.opb_bus_freq = clocks.opb;
ibm44x_platform_init();
@@ -422,12 +465,17 @@ void __init platform_init(unsigned long
ppc_md.get_irq = NULL; /* Set in ppc4xx_pic_init() */
ppc_md.calibrate_decr = bamboo_calibrate_decr;
- ppc_md.time_init = todc_time_init;
- ppc_md.set_rtc_time = todc_set_rtc_time;
- ppc_md.get_rtc_time = todc_get_rtc_time;
- ppc_md.nvram_read_val = todc_direct_read_val;
- ppc_md.nvram_write_val = todc_direct_write_val;
+ if (bamboo)
+ {
+ ppc_md.time_init = todc_time_init;
+ ppc_md.set_rtc_time = todc_set_rtc_time;
+ ppc_md.get_rtc_time = todc_get_rtc_time;
+
+ ppc_md.nvram_read_val = todc_direct_read_val;
+ ppc_md.nvram_write_val = todc_direct_write_val;
+ }
+
#ifdef CONFIG_KGDB
ppc_md.early_serial_map = bamboo_early_serial_map;
#endif
diff -uprN c/arch/ppc/platforms/4xx/bamboo.h d/arch/ppc/platforms/4xx/bamboo.h
--- c/arch/ppc/platforms/4xx/bamboo.h 2005-07-24 16:14:36.000000000 -0500
+++ d/arch/ppc/platforms/4xx/bamboo.h 2005-07-26 06:34:01.000000000 -0500
@@ -31,6 +31,10 @@
/* Default clock rate */
#define BAMBOO_TMRCLK 25000000
+#define BAMBOO_SYSCLK 33333333
+
+#define YOSEMITE_SYSCLK 66666666
+#define YOSEMITE_TMRCLK 50000000
/* RTC/NVRAM location */
#define BAMBOO_RTC_ADDR 0x080000000ULL
diff -uprN c/arch/ppc/platforms/4xx/Kconfig d/arch/ppc/platforms/4xx/Kconfig
--- c/arch/ppc/platforms/4xx/Kconfig 2005-07-24 16:14:36.000000000 -0500
+++ d/arch/ppc/platforms/4xx/Kconfig 2005-07-26 09:53:34.000000000 -0500
@@ -88,6 +88,11 @@ config BAMBOO
help
This option enables support for the IBM PPC440EP evaluation board.
+config YOSEMITE
+ bool "Yosemite"
+ help
+ This option enables support for the AMCC PPC440EP evaluation board.
+
endchoice
config EP405PC
@@ -120,7 +125,7 @@ config 440SP
config 440EP
bool
- depends on BAMBOO
+ depends on BAMBOO || YOSEMITE
select PPC_FPU
default y
@@ -163,7 +168,7 @@ config BOOKE
config IBM_OCP
bool
- depends on ASH || BUBINGA || CPCI405 || EBONY || EP405 || LUAN || OCOTEA || REDWOOD_5 || REDWOOD_6 || SYCAMORE || WALNUT || BAMBOO
+ depends on ASH || BUBINGA || CPCI405 || EBONY || EP405 || LUAN || OCOTEA || REDWOOD_5 || REDWOOD_6 || SYCAMORE || WALNUT || BAMBOO || YOSEMITE
default y
config XILINX_OCP
diff -uprN c/arch/ppc/platforms/4xx/Makefile d/arch/ppc/platforms/4xx/Makefile
--- c/arch/ppc/platforms/4xx/Makefile 2005-07-24 16:14:36.000000000 -0500
+++ d/arch/ppc/platforms/4xx/Makefile 2005-07-26 10:51:35.000000000 -0500
@@ -15,6 +15,7 @@ obj-$(CONFIG_REDWOOD_6) += redwood6.o
obj-$(CONFIG_SYCAMORE) += sycamore.o
obj-$(CONFIG_WALNUT) += walnut.o
obj-$(CONFIG_XILINX_ML300) += xilinx_ml300.o
+obj-$(CONFIG_YOSEMITE) += bamboo.o
obj-$(CONFIG_405GP) += ibm405gp.o
obj-$(CONFIG_REDWOOD_5) += ibmstb4.o
diff -uprN c/arch/ppc/syslib/Makefile d/arch/ppc/syslib/Makefile
--- c/arch/ppc/syslib/Makefile 2005-07-24 16:14:36.000000000 -0500
+++ d/arch/ppc/syslib/Makefile 2005-07-26 10:51:14.000000000 -0500
@@ -46,6 +46,7 @@ obj-$(CONFIG_PPC_PREP) += open_pic.o in
obj-$(CONFIG_ADIR) += i8259.o indirect_pci.o pci_auto.o \
todc_time.o
obj-$(CONFIG_BAMBOO) += indirect_pci.o pci_auto.o todc_time.o
+obj-$(CONFIG_YOSEMITE) += indirect_pci.o pci_auto.o
obj-$(CONFIG_CPCI690) += todc_time.o pci_auto.o
obj-$(CONFIG_EBONY) += indirect_pci.o pci_auto.o todc_time.o
obj-$(CONFIG_EV64260) += todc_time.o pci_auto.o
diff -uprN c/include/asm-ppc/ibm4xx.h d/include/asm-ppc/ibm4xx.h
--- c/include/asm-ppc/ibm4xx.h 2005-07-24 16:14:36.000000000 -0500
+++ d/include/asm-ppc/ibm4xx.h 2005-07-26 09:59:21.000000000 -0500
@@ -109,7 +109,7 @@ void ppc4xx_init(unsigned long r3, unsig
#include <platforms/4xx/ocotea.h>
#endif
-#if defined(CONFIG_BAMBOO)
+#if defined(CONFIG_BAMBOO) || defined(CONFIG_YOSEMITE)
#include <platforms/4xx/bamboo.h>
#endif
^ permalink raw reply
* [PATCH][5/5] RapidIO support: net driver over messaging
From: Avni Hillel-R58467 @ 2005-07-27 10:36 UTC (permalink / raw)
To: 'linuxppc-embedded@ozlabs.org'
Hi Matt,
Two questions:
A. How can a node (not the host) know who is in the rionet to broadcast to them?
B. How do you emulate broadcasting to all the mailboxes, in multi mbox systems? Is this done by the node getting the broadcast in MB 0 and forwarding it to the other MBs?
Regards,
Hillel
^ permalink raw reply
* FEC-trouble with MPC5200 CRV400 M08A
From: Kunkel, Ulrich @ 2005-07-27 9:42 UTC (permalink / raw)
To: 'linuxppc-embedded@ozlabs.org'
[-- Attachment #1: Type: text/plain, Size: 869 bytes --]
Hi everybody,
we had a very fine system with the old Rev CBV400 2LR25. We can boot over
ethernet and do the transfer without any problems.
No we have the CRV400 M08A on the board. We just adapted the registers tfifo
and rfifo to 0x0F040000 and we use now the BAPIV2.2.
We use the elinos-kernel 2.4.25 with the new bestcom-files. We copied them
into the directory bestcom.
But in the most cases the board does not boot over ethernet. We see sig4 or
sig11 when linux starts init.
When we boot from flash we can see that a ping to the board with heavy loads
causes error, especialy when the board sends a ping to the server
simultaneous. There is mostly one false nibble in the data sections, mostly
at the borders of an ethernet-packet.
The error might a little rarer when using BAPI V2.2 instead of BAPI 2.1.
Any ideas? Thanks for Your help
Ulrich Kunkel
[-- Attachment #2: Type: text/html, Size: 2307 bytes --]
^ permalink raw reply
* Re: Porting Linux On MPC8266 custom board
From: Alex Zeffertt @ 2005-07-27 8:52 UTC (permalink / raw)
To: apoorv sangal; +Cc: Linuxppc-embedded
In-Reply-To: <a7966936050726231628bb1c77@mail.gmail.com>
On Wed, 27 Jul 2005 11:46:05 +0530
apoorv sangal <apoorvsangal@gmail.com> wrote:
> Hi Alex,
> Thanks a lot for your reply.
> I have been able to procedd further and now I am facing problem in
> mounting root file system.
> As suggested by you in earlier mail about the following :-
> "
> 1. linux/init/main.c
>
> (which contains the following code
> #endif
> #ifdef CONFIG_MTD
> { "mtdblock", 0x1f00 },
> #endif
> { NULL, 0 }
> };
> )
> "
> I am not able to find the above mention code snippet in the linux/init/main.c.
> I am using Linux Kerne 2.4.24 which came with eldk.
> Does that mean that i have to deifne CONFIG_MTD myself as i am trying
> to JFFS2 file system ?
The code is definitely in there!
You need to define CONFIG_MTD using make menuconfig (make sure you define it as kernel resident not
as a module). If you are new to all this read the README in the kernel source directory first.
Alex
^ permalink raw reply
* Re: Porting Linux On MPC8266 custom board
From: apoorv sangal @ 2005-07-27 6:16 UTC (permalink / raw)
To: Alex Zeffertt, Linuxppc-embedded
Cc: vikrant_basotra, nishant_galange, apoorv sangal
In-Reply-To: <20050707101239.1389b917.ajz@cambridgebroadband.com>
Hi Alex,
Thanks a lot for your reply.
I have been able to procedd further and now I am facing problem in
mounting root file system.
As suggested by you in earlier mail about the following :-
"=20
1. linux/init/main.c
=20
(which contains the following code
#endif
#ifdef CONFIG_MTD
{ "mtdblock", 0x1f00 },
#endif
{ NULL, 0 }
};
)
"
I am not able to find the above mention code snippet in the linux/init/main=
.c.
I am using Linux Kerne 2.4.24 which came with eldk.
Does that mean that i have to deifne CONFIG_MTD myself as i am trying
to JFFS2 file system ?
The output captured on the hyperterminal is as following :-
bootm 02000000 ## Booting image at 02000000 ...
Image Name: 2.4.24 MPC8260ADS
Image Type: PowerPC Linux Kernel Image (gzip compressed)
Data Size: 714527 Bytes =3D 697.8 kB
Load Address: 00000000
Entry Point: 00000000
Verifying Checksum ... OK
Uncompressing Kernel Image ... OK
Memory BAT mapping: BAT2=3D128Mb, BAT3=3D0Mb, residual: 0Mb
Linux version 2.4.24-pre2 (satyam@pmcserver) (gcc version 3.2.2
20030217 (Yellow Dog Linux 3.0 3.2.2-2a_1)) #13 Tue Jul 19 12:55:18
IST 2005
On node 0 totalpages: 32768
zone(0): 32768 pages.
zone(1): 0 pages.
zone(2): 0 pages.
Kernel command line: console=3DttyS0,115200 root=3D/dev/ram
Warning: real time clock seems stuck!
Calibrating delay loop... 131.89 BogoMIPS
Memory: 127816k available (1232k kernel code, 408k data, 64k init, 0k highm=
em)
Dentry cache hash table entries: 16384 (order: 5, 131072 bytes)
Inode cache hash table entries: 8192 (order: 4, 65536 bytes)
Mount cache hash table entries: 512 (order: 0, 4096 bytes)
Buffer cache hash table entries: 8192 (order: 3, 32768 bytes)
Page-cache hash table entries: 32768 (order: 5, 131072 bytes)
POSIX conformance testing by UNIFIX
Linux NET4.0 for Linux 2.4
Based upon Swansea University Computer Society NET3.039
Initializing RT netlink socket
Starting kswapd
JFFS2 version 2.1. (C) 2001 Red Hat, Inc., designed by Axis Communications =
AB.
Inside Chr_dev_init
i2c-core.o: i2c core module version 2.6.1 (20010830)
i2c-dev.o: i2c /dev entries driver module version 2.6.1 (20010830)
CPM UART driver version 0.01
ttyS0 on SMC1 at 0x0000, BRG7
ttyS1 on SMC2 at 0x0040, BRG8
ttyS2 on SCC1 at 0x8000, BRG1
ttyS3 on SCC2 at 0x8100, BRG2
Before return statement
Pty initialisation is complete
End of tty_init
After tty_init
Before misc_init
Inside misc_init b4 create_proc_read_entry
Inside misc_init after create_proc_read_entry
End of misc_init before return 0=20
After misc_init
End of Chr_dev_init b4 return statement
Inside rd_init=20
RAMDISK driver initialized: 16 RAM disks of 4096K size 1024 blocksize
PPP generic driver version 2.4.2
PPP Deflate Compression module registered
PPP BSD Compression module registered
NET4: Linux TCP/IP 1.0 for NET4.0
IP Protocols: ICMP, UDP, TCP, IGMP
IP: routing cache hash table of 1024 buckets, 8Kbytes
TCP: Hash tables configured (established 8192 bind 16384)
ip_conntrack version 2.1 (1024 buckets, 8192 max) - 292 bytes per conntrack
ip_tables: (C) 2000-2002 Netfilter core team
NET4: Unix domain sockets 1.0/SMP for Linux NET4.0.
NET4: Ethernet Bridge 008 for NET4.0
*****
VFS:test name =3D /dev/root
VFS:fs_name =3D jffs2=20
VFS:root name =3D 01:00
****=20
VFS:tried fs_name =3D jffs2 err =3D -22
Kernel panic: VFS: Unable to mount root fs on 01:00
<0>Rebooting in 180 seconds..
Thanks and Regards,
Apoorv Sangal
***************************************************************************=
*************
On 7/7/05, Alex Zeffertt <ajz@cambridgebroadband.com> wrote:
> Apoorv,
>=20
> You need to look in two places:
>=20
> 1. linux/init/main.c
>=20
> (which contains the following code
> #endif
> #ifdef CONFIG_MTD
> { "mtdblock", 0x1f00 },
> #endif
> { NULL, 0 }
> };
> )
>=20
> and
>=20
> 2. http://www.denx.de/twiki/bin/view/DULG/LinuxKernelArgs
>=20
> It looks to me that you're trying to use an mtdblock device for your root
> filesystem. For this to work you need CONFIG_MTD defined and - obviously=
- a
> root file system image in the appropriate place in your flash.
>=20
> It also appears that you are losing output shortly after the ttyS0 driver=
s are
> created. Maybe the problem is that your serial console program (e.g. min=
icom)
> is not configured for 11520 .. or for some reason the driver is selecting
> another rate. Strangely, on my 82xx board I don't need the console argum=
ent on
> the kernel command line, it just automatically uses ttyS0@9600. Probably=
this
> is because it detects u-boot is also using this, but I don't know.
>=20
> Alex
>=20
>=20
> On Thu, 7 Jul 2005 09:48:53 +0530
> apoorv sangal <apoorvsangal@gmail.com> wrote:
>=20
> > Hi All,
> > I am porting Linux on MPC8266 custom board, after getting=
in to
> > Linux the system seems to be struck at a point.
> > Saved Environment variable:-
> > bootargs console=3DttyS0,11520 root=3D1f00 and downloaded the Ker=
nel
> > image at address 0x02000000 in the RAM.
> > From the u-boot prompt the bootm command is invoked as:-
> > bootm 0x02000000
> >
> > After that what I get on the terminal is pasted below for your referenc=
e.
> > I couldn't make out any thing from the output, can any body tell me
> > where I am doing wrong, and also I don't have any idea about the
> > bootargs argument "root". Can any body give the precise description of
> > this argument?
> >
> >
> > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++=
+++++
> > =3D> bootm 02000000 ## Booting image at 02000000...
> > Image Name: 2.4.24 MPC8260ADS
> > Image Type: PowerPC Linux Kernel Image (gzip compressed)
> > Data Size: 725838 Bytes =3D 708.8 kB
> > Load Address: 00000000
> > Entry Point: 00000000
> > Verifying Checksum ... OK
> > Uncompressing Kernel Image ... OK
> > Memory BAT mapping: BAT2=3D128Mb, BAT3=3D0Mb, residual: 0Mb
> >
> > Linux version 2.4.24-pre2 (root@pmcserver) (gcc version 3.3.4) #2 Tue
> > Jul 5 15:05:10 IST 2005
> >
> > On node 0 totalpages: 32768
> >
> > zone(0): 32768 pages.
> >
> > zone(1): 0 pages.
> >
> > zone(2): 0 pages.
> >
> > Kernel command line: console=3DttyS0,115200 root=3D1f00
> >
> > Warning: real time clock seems stuck!
> >
> > Calibrating delay loop... 131.89 BogoMIPS
> >
> > Memory: 127812k available (1232k kernel code, 412k data, 64k init, 0k h=
ighmem)
> >
> > Dentry cache hash table entries: 16384 (order: 5, 131072 bytes)
> >
> > Inode cache hash table entries: 8192 (order: 4, 65536 bytes)
> >
> > Mount cache hash table entries: 512 (order: 0, 4096 bytes)
> >
> > Buffer cache hash table entries: 8192 (order: 3, 32768 bytes)
> >
> > Page-cache hash table entries: 32768 (order: 5, 131072 bytes)
> >
> > POSIX conformance testing by UNIFIX
> >
> > Linux NET4.0 for Linux 2.4
> >
> > Based upon Swansea University Computer Society NET3.039
> >
> > Initializing RT netlink socket
> >
> > Starting kswapd
> >
> > JFFS2 version 2.1. (C) 2001 Red Hat, Inc., designed by Axis Communicati=
ons AB.
> >
> > i2c-core.o: i2c core module version 2.6.1 (20010830)
> >
> > i2c-dev.o: i2c /dev entries driver module version 2.6.1 (20010830)
> >
> > CPM UART driver version 0.01
> >
> > ttyS0 on SMC1 at 0x0000, BRG7
> >
> > ttyS1 on SMC2 at 0x0040, BRG8
> >
> > ttyS2 on SCC1 at 0x8000, BRG1
> >
> > ttyS3 on SCC2 at 0x8100, BRG2
> >
> > pty: 256 Unix98 ptys configured
> > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++=
+
> >
> > Waiting eagerly,
> > Regards,
> > VB
> > _______________________________________________
> > Linuxppc-embedded mailing list
> > Linuxppc-embedded@ozlabs.org
> > https://ozlabs.org/mailman/listinfo/linuxppc-embedded
>
^ permalink raw reply
* mpc8540 SK board FEC work now! (Thanks for Andy Fleming)
From: KylongMu @ 2005-07-27 4:10 UTC (permalink / raw)
To: 'Andy Fleming'; +Cc: Linuxppc-embedded
In-Reply-To: <8F2178E8-C29F-412E-9F07-F81F5E40153F@freescale.com>
Hi Andy:
Thanks for your help , my board's all eth ports works now ,
according the file you give out:
" arch/ppc/ platforms/85xx/mpc8540_ads.c " , I modified the TSEC ID from 0,1
to 4,5 , and modified
the TFEC interrupt source from 5 to 7 , after these modification , my board
can work.
Thanks a lot!
KylongMu
On Jul 26, 2005, at 01:02, KylongMu wrote:
>
> eth0 and eth1 not work, they are giga ethernet , but eth2 work well ,
> I know all of them are drived under same driver " drivers/net/gianfar*
> ", and I checked the 8540 datasheet , because the MAC is integrated ,
> the only deferent is the PHY , the 2.4.18 kernel come with my board is
> work well at all eth port , so I'm sure the hardware is OK
On Jul 27, 2005, at 02:26, Andy Fleming wrote:
The manual says the PHY addresses for TSEC 1 and TSEC 2 are:
TSEC1: 4
TSEC2: 5
The 8540 ADS has this configuration:
TSEC1: 0
TSEC2: 1
The correct solution would be to make a new board file for the SK board, and
properly configure everything. However, if you insist on using the 8540 ADS
config for this, you will need to change arch/ppc/
platforms/85xx/mpc8540_ads.c so that TSEC1 and TSEC2 have their phyid
platform data fields assigned to be:
TSEC1: 4
TSEC2: 5
^ permalink raw reply
* about ppc8260 mcc hdlc driver
From: wangdq @ 2005-07-27 1:27 UTC (permalink / raw)
To: linuxppc-embedded
aGVsbG8gZXZlcnkgb25lOiANCiAgIEkgYW0gcHJvZ3JhbW1pbmcgYSBIRExDIGRyaXZlciBmb3Ig
cHBjODI2MCB1c2luZyBNQ0MyICwgQnV0IGlmIEkgZW5hYmxlIHRoZSBURE0sIHRoZSBib2FyZCB3
aWxsIGRpZS4NCmNhbiBhbnlvbmUgaGVscCBtZSA/IG9yIGdpdmUgbWUgc29tZSBleGFtcGxlIHNv
dXJjZSA/IA0KICAgICAgICAgdGhhbmtzICEgICAgDQoNCgkNCg0KIAkJCQkNCg0KoaGhoaGhoaGh
oaGhoaGhoXdhbmdkcQ0KoaGhoaGhoaGhoaGhoaGhoXdhbmdkcUBnb25neWUuY29tLmNuDQqhoaGh
oaGhoaGhoaGhoaGhoaGhoTIwMDUtMDYtMjcNCg==
^ permalink raw reply
* [PATCH] ppc32: Fix building of TQM8260 board
From: Kumar Gala @ 2005-07-26 23:44 UTC (permalink / raw)
To: Andrew Morton; +Cc: linux-kernel, linuxppc-embedded
Added missing include of cpm2.h in correct order to allow TQM8260 to build
Signed-off-by: Kumar Gala <kumar.gala@freescale.com>
---
commit 2fd8dd75c93a89c465a08d1d0085772cad225927
tree b322bf8a4e146fe7c88e39eac88bc923ac1a567e
parent ca451627946729719d17b7e6c1376ec273a501b5
author Kumar K. Gala <kumar.gala@freescale.com> Tue, 26 Jul 2005 18:43:16 -0500
committer Kumar K. Gala <kumar.gala@freescale.com> Tue, 26 Jul 2005 18:43:16 -0500
arch/ppc/platforms/tqm8260_setup.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/ppc/platforms/tqm8260_setup.c b/arch/ppc/platforms/tqm8260_setup.c
--- a/arch/ppc/platforms/tqm8260_setup.c
+++ b/arch/ppc/platforms/tqm8260_setup.c
@@ -16,8 +16,8 @@
#include <linux/init.h>
-#include <asm/immap_cpm2.h>
#include <asm/mpc8260.h>
+#include <asm/cpm2.h>
#include <asm/machdep.h>
static int
^ permalink raw reply
* Re: platform/board removal update
From: Dan Malek @ 2005-07-26 22:14 UTC (permalink / raw)
To: Marcelo Tosatti; +Cc: linuxppc-dev list, Embedded PPC Linux list
In-Reply-To: <20050726100500.GB28003@dmt.cnet>
On Jul 26, 2005, at 6:05 AM, Marcelo Tosatti wrote:
> 8xx_io/fec.c is still using v2.4's workqueue infrastructure but other
> than
> that its working fine.
I talked to panto about this earlier today.
> The fix will be pushed upstream ASAP.
That's OK, I'm just glad I know what it is :-)
> BTW, we should schedule 8xx_io/fec.c for removal, but before that we
> ought to
> test all supported PHY's on the new driver.
It will be around in old kernels if we need it for reference.
Thanks, and good luck with the new job :-)
-- Dan
^ permalink raw reply
* cpufreq on powerbook lombard
From: Sergey Kolosov @ 2005-07-26 22:10 UTC (permalink / raw)
To: linuxppc-dev
How i can enabled cpufreq on my powerbook lombard? In kernel(2.6.11) source=
:
file /usr/src/kernel-source-2.6.11/arch/ppc/platforms/pmac_cpufreq.c
<...>
/* Currently, we support the following machines:
*
* - Titanium PowerBook 1Ghz (PMU based, 667Mhz & 1Ghz)
* - Titanium PowerBook 800 (PMU based, 667Mhz & 800Mhz)
* - Titanium PowerBook 400 (PMU based, 300Mhz & 400Mhz)
* - Titanium PowerBook 500 (PMU based, 300Mhz & 500Mhz)
* - iBook2 500/600 (PMU based, 400Mhz & 500/600Mhz)
* - iBook2 700 (CPU based, 400Mhz & 700Mhz, support low voltage)
* - Recent MacRISC3 laptops
* - iBook G4s and PowerBook G4s with 7447A CPUs
*/
static int __init pmac_cpufreq_setup(void)
<...>
But can be there is a way for addition of support cpufreq for
powerbook lombard ?
P.S.
sk@powerbook:~$ cat /proc/cpuinfo
processor : 0
cpu : 740/750
temperature : 74-76 C (uncalibrated)
clock : 333MHz
revision : 131.0 (pvr 0008 8300)
bogomips : 665.60
machine : PowerBook1,1
motherboard : PowerBook1,1 MacRISC Power Macintosh
detected as : 64 (PowerBook 101 (Lombard))
pmac flags : 00000009
L2 cache : 512K unified
memory : 256MB
pmac-generation : NewWorld
sk@powerbook:~$ uname -a
Linux powerbook 2.6.8-powerpc #1 Sun Mar 20 14:09:41 CET 2005 ppc GNU/Linux
sk@powerbook:~$ cat /etc/debian_version
3.1
^ permalink raw reply
* patch i2c-mpc-restore-code-removed.patch added to gregkh-2.6 tree
From: gregkh @ 2005-07-26 21:48 UTC (permalink / raw)
To: galak, greg, gregkh, kumar.gala, linuxppc-embedded
In-Reply-To: <Pine.LNX.4.61.0507142157350.14920@nylon.am.freescale.net>
This is a note to let you know that I've just added the patch titled
Subject: I2C-MPC: Restore code removed
to my gregkh-2.6 tree. Its filename is
i2c-mpc-restore-code-removed.patch
This tree can be found at
http://www.kernel.org/pub/linux/kernel/people/gregkh/gregkh-2.6/patches/
Patches currently in gregkh-2.6 which might be from galak@freescale.com are
i2c-mpc-restore-code-removed.patch
>From galak@freescale.com Thu Jul 14 20:02:54 2005
Date: Thu, 14 Jul 2005 21:58:46 -0500 (CDT)
From: Kumar Gala <galak@freescale.com>
To: Greg KH <greg@kroah.com>
cc: linux-kernel@vger.kernel.org,
linuxppc-embedded <linuxppc-embedded@ozlabs.org>
Subject: I2C-MPC: Restore code removed
Message-ID: <Pine.LNX.4.61.0507142157350.14920@nylon.am.freescale.net>
I2C-MPC: Restore code removed
A previous patch to remove support for the OCP device model was way
to generious and moved some of the platform device model code, oops.
Signed-off-by: Kumar Gala <kumar.gala@freescale.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
diff --git a/drivers/i2c/busses/i2c-mpc.c b/drivers/i2c/busses/i2c-mpc.c
--- a/drivers/i2c/busses/i2c-mpc.c
+++ b/drivers/i2c/busses/i2c-mpc.c
@@ -288,6 +288,100 @@ static struct i2c_adapter mpc_ops = {
.retries = 1
};
+static int fsl_i2c_probe(struct device *device)
+{
+ int result = 0;
+ struct mpc_i2c *i2c;
+ struct platform_device *pdev = to_platform_device(device);
+ struct fsl_i2c_platform_data *pdata;
+ struct resource *r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+
+ pdata = (struct fsl_i2c_platform_data *) pdev->dev.platform_data;
+
+ if (!(i2c = kmalloc(sizeof(*i2c), GFP_KERNEL))) {
+ return -ENOMEM;
+ }
+ memset(i2c, 0, sizeof(*i2c));
+
+ i2c->irq = platform_get_irq(pdev, 0);
+ i2c->flags = pdata->device_flags;
+ init_waitqueue_head(&i2c->queue);
+
+ i2c->base = ioremap((phys_addr_t)r->start, MPC_I2C_REGION);
+
+ if (!i2c->base) {
+ printk(KERN_ERR "i2c-mpc - failed to map controller\n");
+ result = -ENOMEM;
+ goto fail_map;
+ }
+
+ if (i2c->irq != 0)
+ if ((result = request_irq(i2c->irq, mpc_i2c_isr,
+ SA_SHIRQ, "i2c-mpc", i2c)) < 0) {
+ printk(KERN_ERR
+ "i2c-mpc - failed to attach interrupt\n");
+ goto fail_irq;
+ }
+
+ mpc_i2c_setclock(i2c);
+ dev_set_drvdata(device, i2c);
+
+ i2c->adap = mpc_ops;
+ i2c_set_adapdata(&i2c->adap, i2c);
+ i2c->adap.dev.parent = &pdev->dev;
+ if ((result = i2c_add_adapter(&i2c->adap)) < 0) {
+ printk(KERN_ERR "i2c-mpc - failed to add adapter\n");
+ goto fail_add;
+ }
+
+ return result;
+
+ fail_add:
+ if (i2c->irq != 0)
+ free_irq(i2c->irq, NULL);
+ fail_irq:
+ iounmap(i2c->base);
+ fail_map:
+ kfree(i2c);
+ return result;
+};
+
+static int fsl_i2c_remove(struct device *device)
+{
+ struct mpc_i2c *i2c = dev_get_drvdata(device);
+
+ i2c_del_adapter(&i2c->adap);
+ dev_set_drvdata(device, NULL);
+
+ if (i2c->irq != 0)
+ free_irq(i2c->irq, i2c);
+
+ iounmap(i2c->base);
+ kfree(i2c);
+ return 0;
+};
+
+/* Structure for a device driver */
+static struct device_driver fsl_i2c_driver = {
+ .name = "fsl-i2c",
+ .bus = &platform_bus_type,
+ .probe = fsl_i2c_probe,
+ .remove = fsl_i2c_remove,
+};
+
+static int __init fsl_i2c_init(void)
+{
+ return driver_register(&fsl_i2c_driver);
+}
+
+static void __exit fsl_i2c_exit(void)
+{
+ driver_unregister(&fsl_i2c_driver);
+}
+
+module_init(fsl_i2c_init);
+module_exit(fsl_i2c_exit);
+
MODULE_AUTHOR("Adrian Cox <adrian@humboldt.co.uk>");
MODULE_DESCRIPTION
("I2C-Bus adapter for MPC107 bridge and MPC824x/85xx/52xx processors");
^ permalink raw reply
* [PATCH] Support 440EP On-Chip OHCI USB Host Controller
From: John Otken @ 2005-07-26 21:41 UTC (permalink / raw)
To: linuxppc-embedded
This patch adds support for the AMCC 440EP on-chip OHCI USB host controller. I tested it on the Bamboo and Yosemite boards using the 2.6.12 kernel.
This patch depends on Wade Farnsworth's "PPC440EP SoC and Bamboo board support" patch from 2005-04-07 and my "fix invalid function name usb_hcd_put in ohci-ppc-soc.c" patch from 2005-07-20:
http://patchwork.ozlabs.org/linuxppc/patch?id=1311
http://patchwork.ozlabs.org/linuxppc/patch?id=1803
Comments are welcome.
(This is a repost. My email host has had problems.)
Signed-off-by: John Otken <jotken@softadvances.com>
diff -uprN b/arch/ppc/platforms/4xx/bamboo.c c/arch/ppc/platforms/4xx/bamboo.c
--- b/arch/ppc/platforms/4xx/bamboo.c 2005-07-24 16:14:36.000000000 -0500
+++ c/arch/ppc/platforms/4xx/bamboo.c 2005-07-25 06:34:52.498441038 -0500
@@ -431,5 +431,7 @@ void __init platform_init(unsigned long
#ifdef CONFIG_KGDB
ppc_md.early_serial_map = bamboo_early_serial_map;
#endif
+
+ SDR_WRITE( 0x320, 1 ); /* little endian usb (SDR0_USB0) */
}
diff -uprN b/arch/ppc/platforms/4xx/ibm440ep.c c/arch/ppc/platforms/4xx/ibm440ep.c
--- b/arch/ppc/platforms/4xx/ibm440ep.c 2005-07-24 16:14:36.000000000 -0500
+++ c/arch/ppc/platforms/4xx/ibm440ep.c 2005-07-24 18:00:38.000000000 -0500
@@ -187,3 +187,44 @@ struct ppc4xx_uic_settings ppc4xx_core_u
},
};
+static struct resource ohci_usb_resources[] = {
+ [0] = {
+ .start = 0x0EF601000,
+ .end = 0x0EF601000 + 0x80 - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = 40,
+ .end = 40,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static u64 dma_mask = 0xffffffffULL;
+
+#include <asm/usb.h>
+
+static struct usb_hcd_platform_data platform_data;
+
+static struct platform_device ohci_usb_device = {
+ .name = "ppc-soc-ohci",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(ohci_usb_resources),
+ .resource = ohci_usb_resources,
+ .dev = {
+ .dma_mask = &dma_mask,
+ .coherent_dma_mask = 0xffffffffULL,
+ .platform_data = &platform_data,
+ }
+};
+
+static struct platform_device *ibm440ep_devs[] __initdata = {
+ &ohci_usb_device,
+};
+
+static int __init
+ ibm440ep_platform_add_devices(void)
+{
+ return platform_add_devices(ibm440ep_devs, ARRAY_SIZE(ibm440ep_devs));
+}
+arch_initcall(ibm440ep_platform_add_devices);
diff -uprN b/drivers/usb/host/Kconfig c/drivers/usb/host/Kconfig
--- b/drivers/usb/host/Kconfig 2005-07-14 09:48:19.000000000 -0500
+++ c/drivers/usb/host/Kconfig 2005-07-24 18:00:38.000000000 -0500
@@ -68,7 +68,7 @@ config USB_OHCI_HCD
config USB_OHCI_HCD_PPC_SOC
bool "OHCI support for on-chip PPC USB controller"
- depends on USB_OHCI_HCD && (STB03xxx || PPC_MPC52xx)
+ depends on USB_OHCI_HCD && (STB03xxx || PPC_MPC52xx || 440EP)
default y
select USB_OHCI_BIG_ENDIAN
---help---
@@ -92,7 +92,7 @@ config USB_OHCI_BIG_ENDIAN
config USB_OHCI_LITTLE_ENDIAN
bool
depends on USB_OHCI_HCD
- default n if STB03xxx || PPC_MPC52xx
+ default n if STB03xxx || PPC_MPC52xx || 440EP
default y
config USB_UHCI_HCD
diff -uprN b/include/asm-ppc/usb.h c/include/asm-ppc/usb.h
--- b/include/asm-ppc/usb.h 1969-12-31 17:00:00.000000000 -0700
+++ c/include/asm-ppc/usb.h 2005-07-24 18:00:38.000000000 -0500
@@ -0,0 +1,13 @@
+/*
+ * ppc/usb.h:
+ *
+ */
+#ifndef _PPC_USB_H
+#define _PPC_USB_H
+
+struct usb_hcd_platform_data {
+ int (*start) (struct platform_device *pdev);
+ void (*stop) (struct platform_device *pdev);
+};
+
+#endif /* !(_PPC_USB_H) */
^ permalink raw reply
* [PATCH] ppc32: fix 440SP MAL channels count
From: Eugene Surovegin @ 2005-07-26 21:32 UTC (permalink / raw)
To: Andrew Morton; +Cc: linuxppc-embedded
Andrew,
the following patch fixes MAL channels count in PPC 440SP OCP
definition. PPC 440SP has only 1 EMAC attached to MAL.
Signed-off-by: Eugene Surovegin <ebs@ebshome.net>
diff --git a/arch/ppc/platforms/4xx/ibm440sp.c b/arch/ppc/platforms/4xx/ibm440sp.c
--- a/arch/ppc/platforms/4xx/ibm440sp.c
+++ b/arch/ppc/platforms/4xx/ibm440sp.c
@@ -36,8 +36,8 @@ static struct ocp_func_emac_data ibm440s
OCP_SYSFS_EMAC_DATA()
static struct ocp_func_mal_data ibm440sp_mal0_def = {
- .num_tx_chans = 4, /* Number of TX channels */
- .num_rx_chans = 4, /* Number of RX channels */
+ .num_tx_chans = 1, /* Number of TX channels */
+ .num_rx_chans = 1, /* Number of RX channels */
.txeob_irq = 38, /* TX End Of Buffer IRQ */
.rxeob_irq = 39, /* RX End Of Buffer IRQ */
.txde_irq = 34, /* TX Descriptor Error IRQ */
^ permalink raw reply
* RE: 8260 FCC Ethernet problem
From: Rune Torgersen @ 2005-07-26 19:44 UTC (permalink / raw)
To: Leitner, Kip, linuxppc-dev
=20
> -----Original Message-----
> From: linuxppc-dev-bounces@ozlabs.org=20
> [mailto:linuxppc-dev-bounces@ozlabs.org] On Behalf Of Leitner, Kip
> Sent: Tuesday, July 26, 2005 14:15
> We are wondering if we apply your patch to 2.4.18 fcc_enet.c,=20
> will this fix our late collision problem, as 2.4.18=20
> fcc_enet.c has the uncorrected part of the code in our Linux=20
> distribution that your patch fixes.
Try and see.
I have some doubts, as this only fixes a problem in full duplex mode,
and you are running in half duplex.
^ permalink raw reply
* 8260 FCC Ethernet problem
From: Leitner, Kip @ 2005-07-26 19:15 UTC (permalink / raw)
To: linuxppc-dev
[-- Attachment #1: Type: text/plain, Size: 3905 bytes --]
Rune,
I just found your post regarding the Local_Protect_Bit not being set in
8260 FCC, for "some versions of 2.4 source " fcc_enet.c, and this
causing problems. In my situation, we are getting late collision errors
in our application, details follow (after your patch notes).
We are wondering if we apply your patch to 2.4.18 fcc_enet.c, will this
fix our late collision problem, as 2.4.18 fcc_enet.c has the uncorrected
part of the code in our Linux distribution that your patch fixes.
Sincerely,
Kip Leitner
**************
<Rune Wrote >
I just found that there is a problem in the FCC driver.
This was fixed in some versions of the 2.4 source....
Th Local Protect Bit is not set when enterring Full Duplex mode. This
causes the FCC to turn off the transmitter when packets are received,
and also
causes NonOctet frame errors and CRC errors (late collission)
This diff is agains the 2.6.7 sources, but should apply cleanly against
top of source.
===== arch/ppc/8260_io/fcc_enet.c 1.20 vs edited =====
--- 1.20/arch/ppc/8260_io/fcc_enet.c 2004-07-06 16:44:29 -05:00
+++ edited/arch/ppc/8260_io/fcc_enet.c 2004-09-10 14:44:05 -05:00
@@ -2013,9 +2013,9 @@
fccp = fcp->fccp;
if (duplex)
- fccp->fcc_fpsmr |= FCC_PSMR_FDE;
+ fccp->fcc_fpsmr |= FCC_PSMR_FDE | FCC_PSMR_LPB;
else
- fccp->fcc_fpsmr &= ~FCC_PSMR_FDE;
+ fccp->fcc_fpsmr &= ~(FCC_PSMR_FDE | FCC_PSMR_LPB);
/* Enable transmit/receive */
fccp->fcc_gfmr |= FCC_GFMR_ENR | FCC_GFMR_ENT;
Rune Torgersen
System Developer
Innovative Systems LLC
1000 Innovative Drive
Mitchell, SD 57301
Ph: 605-995-6120
www.innovsys.com
**************
< Dump from Kip Leitner >
In kernel version 2.4.18, in the Ethernet driver fcc_enet.c, we hit the
ring data dump with text message "eth0: transmit timeout". Upon
inspection of the buffer descriptors, we noticed that buffer four (4,
0-based numbering) shows status for a late collision. Our lan
conditions at the time of the dump: PHY running at 10 Base T,
half-duplex, connected to half-duplex hub. We know (from our high-level
software) that while we were continuously transmitting, we also began to
receive packets, which is when this repeatable condition of the Ring
Dump occurred. Dump below (more text after):
NETDEV WATCHDOG: eth0: transmit timed out
eth0: transmit timed out.
Ring data dump: cur_tx c01aa380 (full) cur_rx c01aa220.
Tx @base c01aa308 :
9c00 0051 070f79a2
1c00 0056 070f7da2
1c00 0056 070f7ea2
1c00 0051 070f7ba2
1c80 003f 070f51c2 ** Late Collision **
9c00 0056 070f50c2
9c00 0051 070f52c2
9c00 0056 070f53c2
9c00 0056 070f55c2
9c00 0051 070f54c2
dc00 0038 070f56c2
9c00 0056 070f57c2
9c00 0051 070f58c2
9c00 0056 070f59c2
9c00 0056 070f5ac2
bc00 0056 070f7ca2
Rx @base c01aa208 :
9c00 0040 0046f000
9c00 0040 0046f800
9c00 0040 0046e000
9c00 0072 0046e800
9c00 0072 0046d000
9c00 0072 0046d800
9c00 0072 0046c000
9c00 0072 0046c800
9c00 0072 0046b000
9c00 0072 0046b800
9c00 0072 0046a000
9c00 0040 0046a800
9c00 0072 00469000
9c00 0072 00469800
9c00 0072 00468000
9c00 0072 00468800
9c00 0072 00467000
9c00 0040 00467800
9c00 0072 00466000
9c00 0040 00466800
9c00 0072 00465000
9c00 0040 00465800
9c00 0040 00464000
9c00 0040 00464800
9c00 0040 00463000
9c00 0040 00463800
9c00 0040 00462000
9c00 0040 00462800
9c00 0040 00461000
9c00 0040 00461800
9c00 0040 00460000
bc00 0040 00460800
We are wondering if our hardware (we build our own) has a problem, our
physical network has a problem, and/or if
--> the driver supports recovery from late collisions.
[-- Attachment #2: Type: text/html, Size: 19200 bytes --]
^ permalink raw reply
* Re: mpc8540 SK board FEC not work! (second message)
From: Andy Fleming @ 2005-07-26 18:26 UTC (permalink / raw)
To: KylongMu; +Cc: Linuxppc-embedded
In-Reply-To: <20050726060304.AF08EC372E@smtp.263.net>
On Jul 26, 2005, at 01:02, KylongMu wrote:
>
> eth0 and eth1 not work, they are giga ethernet , but eth2 work
> well , I know
> all of them are drived under same driver " drivers/net/gianfar* ",
> and I checked the 8540 datasheet , because the MAC is integrated ,
> the only
> deferent is the PHY , the 2.4.18 kernel come with my board
> is work well at all eth port , so I'm sure the hardware is OK
The manual says the PHY addresses for TSEC 1 and TSEC 2 are:
TSEC1: 4
TSEC2: 5
The 8540 ADS has this configuration:
TSEC1: 0
TSEC2: 1
The correct solution would be to make a new board file for the SK
board, and properly configure everything. However, if you insist on
using the 8540 ADS config for this, you will need to change arch/ppc/
platforms/85xx/mpc8540_ads.c so that TSEC1 and TSEC2 have their phyid
platform data fields assigned to be:
TSEC1: 4
TSEC2: 5
^ permalink raw reply
* preliminary 750GX PLL control patch
From: Kevin Diggs @ 2005-07-26 17:28 UTC (permalink / raw)
To: linuxppc-dev
[-- Attachment #1: Type: text/plain, Size: 987 bytes --]
Hi,
I've attached a patch that adds preliminary access to the HID1
register in the 750GX (aka the PLL config register). The patch is
against 2.4.30. It has been lightly tested on a PowerMac 8600 with a
PowerLogix PowerForce 750GX cpu card.
Depending on the values for the pllx_cfg field, this should
work on the 750FX as well ... except for the stuff in idle_6xx.S. Since
there are plenty of people on this list way more smarterer than me I was
hoping someone could answer a question about the powersave modes that
some of the PowerPC processors have:
Since, as I understand it, the clock is shut off to much of the
chip when a powersave mode is engaged does it really buy you that much
to switch to a lower clock speed? Wouldn't you be better off shutting
off the unused PLL?
Also, please note that I am not very experienced creating
patches so please use a backup of your source tree.
kevin
[-- Attachment #2: pllpatch.u --]
[-- Type: text/plain, Size: 31193 bytes --]
diff -Naur linux-2.4.30.orig/Documentation/Configure.help linux-2.4.30/Documentation/Configure.help
--- linux-2.4.30.orig/Documentation/Configure.help Fri Apr 8 15:47:19 2005
+++ linux-2.4.30/Documentation/Configure.help Wed Jun 22 18:00:35 2005
@@ -24304,6 +24304,11 @@
a lot, or the TAU hardware is broken (likely on some G4's). If the range
is small (around 4 degrees), the temperature is relatively stable.
+Dual PLL support
+CONFIG_DUAL_PLL
+ This option enables sysctl support for checking and modifying the PLLs in
+ the IBM 750FX and 750GX processors.
+
Power management support for PowerBooks
CONFIG_PMAC_PBOOK
This provides support for putting a PowerBook to sleep; it also
diff -Naur linux-2.4.30.orig/arch/ppc/config.in linux-2.4.30/arch/ppc/config.in
--- linux-2.4.30.orig/arch/ppc/config.in Thu Apr 7 22:25:11 2005
+++ linux-2.4.30/arch/ppc/config.in Tue Jun 21 18:02:56 2005
@@ -175,10 +175,12 @@
bool ' Average high and low temp' CONFIG_TAU_AVERAGE
fi
define_bool CONFIG_PPC_ISATIMER y
+
+ bool 'Dual PLL Support (750FX/GX)' CONFIG_DUAL_PLL
fi
-if [ "$CONFIG_POWER4" = "y" ]; then
- bool 'VMX (same as AltiVec) support' CONFIG_ALTIVEC
-fi
+#if [ "$CONFIG_POWER4" = "y" ]; then
+# bool 'VMX (same as AltiVec) support' CONFIG_ALTIVEC
+#fi
if [ "$CONFIG_4xx" = "y" -o "$CONFIG_8xx" = "y" ]; then
bool 'Math emulation' CONFIG_MATH_EMULATION
diff -Naur linux-2.4.30.orig/arch/ppc/kernel/Makefile linux-2.4.30/arch/ppc/kernel/Makefile
--- linux-2.4.30.orig/arch/ppc/kernel/Makefile Thu Apr 7 22:24:19 2005
+++ linux-2.4.30/arch/ppc/kernel/Makefile Tue Jun 21 18:10:03 2005
@@ -50,6 +50,7 @@
obj-$(CONFIG_PPCBUG_NVRAM) += prep_nvram.o
obj-$(CONFIG_SMP) += smp.o
obj-$(CONFIG_TAU) += temp.o
+obj-$(CONFIG_DUAL_PLL) += pll.o pll_init.o
ifeq ($(CONFIG_SERIAL)$(CONFIG_GEN550),yy)
obj-$(CONFIG_KGDB) += gen550_kgdb.o gen550_dbg.o
obj-$(CONFIG_SERIAL_TEXT_DEBUG) += gen550_dbg.o
@@ -97,6 +98,8 @@
entry.o: entry.S ppc_defs.h
misc.o: misc.S ppc_defs.h
l2cr.o: l2cr.S ppc_defs.h
+pll.o: pll.S ppc_defs.h
+pll_init.o: pll_init.c ppc_defs.h
head.o: head.S ppc_defs.h
head_4xx.o: head_4xx.S ppc_defs.h
head_44x.o: head_44x.S ppc_defs.h
diff -Naur linux-2.4.30.orig/arch/ppc/kernel/cpu_setup_6xx.S linux-2.4.30/arch/ppc/kernel/cpu_setup_6xx.S
--- linux-2.4.30.orig/arch/ppc/kernel/cpu_setup_6xx.S Thu Apr 7 22:22:52 2005
+++ linux-2.4.30/arch/ppc/kernel/cpu_setup_6xx.S Sun May 15 12:16:39 2005
@@ -48,6 +48,13 @@
bl setup_750fx
mtlr r4
blr
+_GLOBAL(__setup_cpu_750gx)
+ mflr r4
+ bl setup_common_caches
+ bl setup_750_7400_hid0
+ bl setup_750gx
+ mtlr r4
+ blr
_GLOBAL(__setup_cpu_7400)
mflr r4
bl setup_7400_workarounds
@@ -200,6 +207,11 @@
/* 750fx specific
*/
setup_750fx:
+ blr
+
+/* 750gx specific
+ */
+setup_750gx:
blr
/* MPC 745x
diff -Naur linux-2.4.30.orig/arch/ppc/kernel/cputable.c linux-2.4.30/arch/ppc/kernel/cputable.c
--- linux-2.4.30.orig/arch/ppc/kernel/cputable.c Fri Apr 8 15:47:21 2005
+++ linux-2.4.30/arch/ppc/kernel/cputable.c Thu Jun 23 12:22:14 2005
@@ -24,6 +24,7 @@
extern void __setup_cpu_750(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
extern void __setup_cpu_750cx(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
extern void __setup_cpu_750fx(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
+extern void __setup_cpu_750gx(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
extern void __setup_cpu_7400(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
extern void __setup_cpu_7410(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
extern void __setup_cpu_745x(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
@@ -60,6 +61,19 @@
#define CPU_FTR_COMMON 0
#endif
+#if 0
+const char *cpu_type_strings[] = {
+ "601","603","603e","603ev","604","604e","604r","604ev","740/750",
+ "745/755","750CX","750FX","750GX","7400","7400 (1.1)","7410","7450",
+ "7455","7457","7447A","82xx","8280","(generic PPC)","Power3 (630)",
+ "Power3 (630+)","I-star","S-star","Power4","PPC970","8xx","403GC",
+ "403GCX","403G ??","405GP","STB03xxx","440GP Rev. B","440GP Rev. C",
+ "440GX Rev. A","440GX Rev. B","440GX Rev. C"
+};
+
+#define CPU_TYPE_601 cpu_type_strings[0]
+#endif
+
struct cpu_spec cpu_specs[] = {
#if CLASSIC_PPC
{ /* 601 */
@@ -165,7 +179,7 @@
CPU_FTR_COMMON |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP |
- CPU_FTR_750FX | CPU_FTR_NO_DPM,
+ CPU_FTR_750FX | CPU_FTR_NO_DPM | CPU_FTR_DUALPLL,
COMMON_PPC,
32, 32,
__setup_cpu_750
@@ -175,7 +189,8 @@
CPU_FTR_COMMON |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP |
- CPU_FTR_750FX | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NO_DPM,
+ CPU_FTR_750FX | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NO_DPM |
+ CPU_FTR_DUALPLL,
COMMON_PPC,
32, 32,
__setup_cpu_750
@@ -185,10 +200,40 @@
CPU_FTR_COMMON |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP |
- CPU_FTR_750FX | CPU_FTR_HAS_HIGH_BATS,
+ CPU_FTR_750FX | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_DUALPLL,
COMMON_PPC,
32, 32,
__setup_cpu_750fx
+ },
+ { /* 750GX (rev 1.x) */
+ 0xffffff00, 0x70020100, "750GX",
+ CPU_FTR_COMMON |
+ CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
+ CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP |
+ CPU_FTR_750GX | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_DUALPLL,
+ COMMON_PPC,
+ 32, 32,
+ __setup_cpu_750gx
+ },
+ { /* 750GX (rev 2.3, as used on PowerLogix 750GX) */
+ 0xffffffff, 0x00080203, "750GX",
+ CPU_FTR_COMMON |
+ CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
+ CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP |
+ CPU_FTR_750GX | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_DUALPLL,
+ COMMON_PPC,
+ 32, 32,
+ __setup_cpu_750gx
+ },
+ { /* 750GX (All revs >= 2.0) */
+ 0xffffff00, 0x70020200, "750GX",
+ CPU_FTR_COMMON |
+ CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
+ CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP |
+ CPU_FTR_750GX | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_DUALPLL,
+ COMMON_PPC,
+ 32, 32,
+ __setup_cpu_750gx
},
{ /* 740/750 (L2CR bit need fixup for 740) */
0xffff0000, 0x00080000, "740/750",
diff -Naur linux-2.4.30.orig/arch/ppc/kernel/pll.S linux-2.4.30/arch/ppc/kernel/pll.S
--- linux-2.4.30.orig/arch/ppc/kernel/pll.S Wed Dec 31 16:00:00 1969
+++ linux-2.4.30/arch/ppc/kernel/pll.S Wed Jun 22 18:15:51 2005
@@ -0,0 +1,182 @@
+/*
+ Dual PLL functions, for 750FX & 750GX
+ Copyright © 2005 by Kevin Diggs
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+*/
+/*
+ Tue, June 14, 2005.
+ - First public release, contributed by Kevin Diggs.
+ ***********
+ ***********
+
+ Author: Kevin Diggs ()
+ Please e-mail updates to this file to me, thanks!
+*/
+#include <linux/config.h>
+#include <asm/processor.h>
+#include <asm/cputable.h>
+#include <asm/ppc_asm.h>
+#include <asm/cache.h>
+
+/* Usage:
+
+ Examples:
+
+ _setPLL(0) - disables the cache
+ _setPLL(0xB3A04000) - enables my G3 upgrade card:
+ - L2E set to turn on the cache
+ - L2SIZ set to 1MB
+ - L2CLK set to 1:1
+ - L2RAM set to pipelined synchronous late-write
+ - L2I set to perform a global invalidation
+ - L2OH set to 0.5 nS
+ - L2DF set because this upgrade card
+ requires it
+
+ The layout of the PLL register (HID1) is:
+
+ 0 4|5 6|7|8| 9 11|12 13|14| 15 |16 20|21 22|24 28|29 30| 31
+ PCE |PRE|v|v| Res | Res |v | PS | PC0 | PR0 | PC1 | PR1 |Res
+ | | |
+ PSTAT1 -| | |
+ ECLK -----| |
+ PI0 --------------------|
+
+ PCE PLL0 read-only external config
+ PRE PLL0 read-only external range
+ PSTAT1 PLL status (0 -> PLL0, 1 -> PLL1)
+ ECLK 1 -> enable clkout pin
+ PI0 PLL0 control: 0 -> external
+ PS PLL select: 0 -> PLL0, 1 -> PLL1
+ PC0 PLL0 configuration
+ PR0 PLL0 range
+ PC1 PLL1 configuration
+ PR1 PLL1 range
+
+ PLL_CFG bus ratio PLL_CFG bus ratio
+ 00000 off 10000 8
+ 00001 off 10001 8.5
+ 00010 bypass 10010 9
+ 00011 bypass 10011 9.5
+ 00100 2 10100 10
+ 00101 2.5 10101 11
+ 00110 3 10110 12
+ 00111 3.5 10111 13
+ 01000 4 11000 14
+ 01001 4.5 11001 15
+ 01010 5 11010 16
+ 01011 5.5 11011 17
+ 01100 6 11100 18
+ 01101 6.5 11101 19
+ 01110 7 11110 20
+ 01111 7.5 11111 off
+
+ PLL_RNG range
+ 00 600 - 900
+ 01 900 - 1000
+ 10 500 - 600
+*/
+
+/*
+ * Return current PLL configuration
+ */
+_GLOBAL(_get_PLL)
+ /* Make sure this is a 750FX or 750GX chip */
+BEGIN_FTR_SECTION
+ li r3,-1
+ blr
+END_FTR_SECTION_IFCLR(CPU_FTR_DUALPLL)
+ mfspr r3,HID1 /* Get current PLL config */
+ blr
+
+/*
+ * Return active (selected) PLL from configuration (0 or 1)
+ * r3 contains configuration to dig selection out of
+ */
+_GLOBAL(_get_active_PLL)
+ /* Make sure this is a 750FX or 750GX chip */
+BEGIN_FTR_SECTION
+ li r3,-1
+ blr
+END_FTR_SECTION_IFCLR(CPU_FTR_DUALPLL)
+ rlwinm r3,r3,8,31,31 /* PSTAT1 to LSBit and mask */
+ blr
+
+/*
+ * Return next PLL from configuration (0 or 1)
+ * r3 contains configuration to dig next PLL out of (PS bit)
+ */
+_GLOBAL(_get_next_PLL)
+ /* Make sure this is a 750FX or 750GX chip */
+BEGIN_FTR_SECTION
+ li r3,-1
+ blr
+END_FTR_SECTION_IFCLR(CPU_FTR_DUALPLL)
+ rlwinm r3,r3,16,31,31 /* PS to LSBit and mask */
+ blr
+
+/*
+ * Return selected ratio
+ * r3 contains ratio to return (0 or 1)
+ * r4 contains the configuration to pick it out of
+ */
+_GLOBAL(_get_PLL_ratio)
+BEGIN_FTR_SECTION
+ li r3,-1
+ blr
+END_FTR_SECTION_IFCLR(CPU_FTR_DUALPLL)
+ /*
+ * Turn r3 into a rotate count for the selected configuration.
+ * 0 needs to become 21, 1 needs to become 29.
+ */
+ slwi r3,r3,3
+ addi r3,r3,21
+
+ rlwnm r3,r4,r3,27,31
+ blr
+
+/*
+ * Return selected range
+ * r3 contains range to return (0 or 1)
+ * r4 contains the configuration to pick it out of
+ */
+_GLOBAL(_get_PLL_range)
+BEGIN_FTR_SECTION
+ li r3,-1
+ blr
+END_FTR_SECTION_IFCLR(CPU_FTR_DUALPLL)
+ /*
+ * Turn r3 into a rotate count for the selected range.
+ * 0 needs to become 23, 1 needs to become 31.
+ */
+ slwi r3,r3,3
+ addi r3,r3,23
+
+ rlwnm r3,r4,r3,30,31
+ blr
+
+/*
+ * Update the value of the PLL configuration register
+ */
+_GLOBAL(_set_PLL)
+ /* Make sure this is a 750FX or 750GX chip */
+BEGIN_FTR_SECTION
+ li r3,-1
+ blr
+END_FTR_SECTION_IFCLR(CPU_FTR_DUALPLL)
+
+ mtspr HID1,r3 /* Get current PLL config */
+ blr
diff -Naur linux-2.4.30.orig/arch/ppc/kernel/pll_init.c linux-2.4.30/arch/ppc/kernel/pll_init.c
--- linux-2.4.30.orig/arch/ppc/kernel/pll_init.c Wed Dec 31 16:00:00 1969
+++ linux-2.4.30/arch/ppc/kernel/pll_init.c Sat Jun 25 21:15:14 2005
@@ -0,0 +1,506 @@
+#include <linux/config.h>
+#include <linux/errno.h>
+#include <linux/sched.h>
+#include <linux/proc_fs.h>
+#include <linux/stat.h>
+#include <linux/sysctl.h>
+#include <linux/ctype.h>
+#include <linux/threads.h>
+#include <linux/init.h>
+
+#include <asm/uaccess.h>
+#include <asm/bitops.h>
+#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <asm/residual.h>
+#include <asm/io.h>
+#include <asm/pgtable.h>
+#include <asm/cputable.h>
+#include <asm/system.h>
+#include <asm/pll.h>
+
+extern unsigned long loops_per_jiffy;
+
+static struct timer_list pll_timer;
+
+unsigned long boot_loops;
+unsigned int boot_ratio;
+
+#define TMPBUFLEN 128
+
+/*
+ * This initializes the code for the PLL control:
+ * boot_ratio is used to scale the loops_per_jiffy value from its boot value
+ * boot_loops is the boot value of loops_per_jiffy and is used to compute new
+ * values
+ */
+void __init init_PLL()
+{
+int temp;
+
+ temp=_get_PLL();
+ temp=_get_PLL_ratio(_get_active_PLL(temp),temp);
+
+ /*
+ * Units for boot ratio is halves, i.e. 20 is a ratio of 10.
+ * From 21 on the returned value needs to be converted to halves.
+ */
+ if(temp>20) temp=(temp-10)<<1;
+
+ boot_ratio=temp;
+ boot_loops=loops_per_jiffy;
+}
+
+__initcall(init_PLL);
+
+static unsigned long pllNewLPJ(unsigned int oldRatio, unsigned int newRatio,
+ unsigned long LPJ)
+{
+ if(LPJ>200000000) return LPJ/oldRatio*newRatio;
+ else return LPJ*newRatio/oldRatio;
+}
+
+static void pllSwitchPLLs(unsigned int newPLL)
+{
+#if 0
+unsigned long flags;
+#endif
+unsigned int new_ratio,old_ratio,current_pll,masked_boot_ratio;
+
+#if DEBUG
+printk(__FILE__"-%d: newPLL=0x%08x\n",__LINE__,newPLL);
+#endif
+ /*
+ * Compute new loops_per_jiffy
+ */
+ current_pll=_get_PLL();
+ new_ratio=_get_PLL_ratio(_get_next_PLL(newPLL),current_pll);
+ old_ratio=_get_PLL_ratio(_get_active_PLL(current_pll),current_pll);
+ masked_boot_ratio=boot_ratio&0xff;
+#if DEBUG
+ printk(__FILE__"-%d: current_pll=0x%08x, new=%d, old=%d\n",__LINE__,
+ current_pll,new_ratio,old_ratio);
+#endif
+ current_pll=(current_pll&~PLL_SEL_MASK)|newPLL;
+
+#if DEBUG
+ printk(__FILE__"-%d: current_pll=0x%08x, new=%d, old=%d\n",__LINE__,
+ current_pll,new_ratio,old_ratio);
+#endif
+ /*
+ * Convert to halves
+ */
+ if(new_ratio>20) new_ratio=(new_ratio-10)<<1;
+ if(old_ratio>20) old_ratio=(old_ratio-10)<<1;
+
+ /*
+ * Make sure that we never shorten the sleep values
+ */
+ if(new_ratio>old_ratio)
+ {
+ loops_per_jiffy=pllNewLPJ(masked_boot_ratio,new_ratio,
+ boot_loops);
+#if DEBUG
+ printk(__FILE__"-%d: masked_boot_ratio=%d, new_ratio=%d, boot_loops=%d"
+ ", loops_per_jiffy=%d\n",__LINE__,masked_boot_ratio,new_ratio,
+ boot_loops,loops_per_jiffy);
+#endif
+
+ _set_PLL(current_pll);
+ }
+ else
+ {
+#if DEBUG
+ printk(__FILE__"-%d: masked_boot_ratio=%d, new_ratio=%d, "
+ "boot_loops=%d, loops_per_jiffy=%d\n",__LINE__,
+ masked_boot_ratio,new_ratio,boot_loops,
+ loops_per_jiffy);
+#endif
+ _set_PLL(current_pll);
+
+ loops_per_jiffy=pllNewLPJ(masked_boot_ratio,new_ratio,
+ boot_loops);
+#if DEBUG
+ printk(__FILE__"-%d: masked_boot_ratio=%d, new_ratio=%d, "
+ "boot_loops=%d, loops_per_jiffy=%d\n",__LINE__,
+ masked_boot_ratio,new_ratio,boot_loops,
+ loops_per_jiffy);
+#endif
+ }
+
+#if 0
+ save_flags(flags);
+ cli();
+
+ loops_per_jiffy=pllNewLPJ(masked_boot_ratio,new_ratio,boot_loops);
+
+ _set_PLL(current_pll);
+
+ restore_flags(flags);
+#endif
+}
+
+static void pllTimerF(unsigned long newPLL)
+{
+ if((unsigned int)newPLL) pllSwitchPLLs((unsigned int)newPLL);
+
+ /*
+ * Clear all lock bits
+ */
+ boot_ratio&=~(PLL_TIMER|PLL0_LOCK|PLL1_LOCK);
+}
+
+static int checkPLL(unsigned int pll)
+{
+unsigned int current_pll,work_mask,pll_x;
+int rval;
+
+ /*
+ * This is not reentrant
+ */
+ if(test_and_set_bit(PLL_LOCK_BIT,&boot_ratio)) return -EBUSY;
+
+ /*
+ * Don't allow any changes if a timer is pending
+ */
+ if(boot_ratio&PLL_TIMER) goto checkPLLBusy;
+
+ current_pll=_get_PLL();
+ work_mask=pll>>24;
+
+ /*
+ * Check to see if the currently selected PLL is being modified
+ */
+ pll_x=_get_active_PLL(current_pll);
+
+ if(pll_x==0 && work_mask&(PLL0_DO_CFG|PLL0_DO_RNG|PLL0_DO_CONTROL) ||
+ pll_x==1 && work_mask&(PLL1_DO_CFG|PLL1_DO_RNG))
+ goto checkPLLInVal;
+
+ /*
+ * Can't change to a PLL that is off. Also can't immediately change to
+ * one that is not locked. Catch that supposedly impossible condition.
+ */
+ if(work_mask&PLL_DO_SEL)
+ {
+ int next_ratio;
+ unsigned int which_config;
+
+ pll_x=_get_next_PLL(pll);
+
+ /*
+ * Figure out where the next ratio comes from. It will be from
+ * pll if we are changing the next pll and current_pll if not.
+ */
+ which_config=pll_x?((work_mask&PLL1_DO_CFG)?pll:current_pll):
+ ((work_mask&PLL0_DO_CFG)?pll:current_pll);
+ next_ratio=_get_PLL_ratio(pll_x,which_config);
+ if(next_ratio<4 || next_ratio>30) goto checkPLLInVal;
+
+ pll_x=(pll_x==0 && boot_ratio&PLL0_LOCK || pll_x==1 &&
+ boot_ratio&PLL1_LOCK)?1:0;
+
+ }
+ /*
+ * To avoid complications, don't allow both plls to be half ratios
+ */
+ if(work_mask&PLL0_DO_CFG)
+ {
+ int old_ratio1,new_ratio0;
+
+ old_ratio1=_get_PLL_ratio(1,current_pll);
+ new_ratio0=_get_PLL_ratio(0,pll);
+
+ if(old_ratio1>4 && old_ratio1<20 && new_ratio0>4 && new_ratio0<
+ 20 && (old_ratio1&0x1) & (new_ratio0&0x1))
+ goto checkPLLInVal;
+ }
+ else if(work_mask&PLL1_DO_CFG)
+ {
+ int old_ratio0,new_ratio1;
+
+ old_ratio0=_get_PLL_ratio(0,current_pll);
+ new_ratio1=_get_PLL_ratio(1,pll);
+
+ if(old_ratio0>4 && old_ratio0<20 && new_ratio1>4 && new_ratio1<
+ 20 && (old_ratio0&0x1) & (new_ratio1&0x1))
+ goto checkPLLInVal;
+ }
+
+ /*
+ * Determine if we will need to schedule a timer for a PLL relock. If
+ * any PLL config is being changed then a timer will be needed. Also
+ * need one if changing to a PLL that is not locked, though that should
+ * not happen.
+ */
+ if(work_mask&(PLL0_DO_CFG|PLL0_DO_RNG|PLL1_DO_CFG|PLL1_DO_RNG|
+ PLL0_DO_CONTROL) || work_mask&PLL_DO_SEL && pll_x)
+ {
+ unsigned int pll_mask,temp;
+
+ pll_mask=0;
+
+ if(work_mask&PLL0_DO_CFG)
+ {
+ pll_mask|=PLL0_CFG_MASK;
+
+ /*
+ * Flag that PLL0 needs to relock
+ */
+ boot_ratio|=PLL0_LOCK;
+ }
+
+ if(work_mask&PLL0_DO_RNG) pll_mask|=PLL0_RNG_MASK;
+
+ if(work_mask&PLL1_DO_CFG)
+ {
+ pll_mask|=PLL1_CFG_MASK;
+
+ /*
+ * Flag that PLL1 needs to relock
+ */
+ boot_ratio|=PLL1_LOCK;
+ }
+
+ if(work_mask&PLL1_DO_RNG) pll_mask|=PLL1_RNG_MASK;
+
+ temp=current_pll&~pll_mask|pll&pll_mask;
+
+ if(pll_mask) _set_PLL(temp);
+
+ /*
+ * Flag that a timer is pending
+ */
+ boot_ratio|=PLL_TIMER;
+
+ /*
+ * Schedule a timer to clear the PLL lock bits (and signal that
+ * it is ok to select the PLL)
+ */
+ init_timer(&pll_timer);
+
+ pll_timer.function=pllTimerF;
+ pll_timer.data=(work_mask&PLL_DO_SEL)?pll&
+ PLL_SEL_MASK:0;
+
+ /*
+ * Relock takes 100 us. See how many jiffies will take care of
+ * it.
+ */
+ pll_timer.expires=(100*HZ/1000000);
+ if(pll_timer.expires==0) pll_timer.expires=2;
+
+ pll_timer.expires=jiffies+pll_timer.expires;
+ add_timer(&pll_timer);
+ }
+ else if(work_mask&PLL_DO_SEL)
+ pllSwitchPLLs(pll&PLL_SEL_MASK);
+
+ rval=0;
+
+checkPLLErr:
+ clear_bit(PLL_LOCK_BIT,&boot_ratio);
+
+ return rval;
+checkPLLBusy:
+ rval=-EBUSY;
+ goto checkPLLErr;
+checkPLLInVal:
+ rval=-EINVAL;
+ goto checkPLLErr;
+}
+
+/*
+ * Handle accesses to the pll file. Examples for write:
+ * value CFGx/RNGx/res effect
+ * 0x08010000 switch to PLL1
+ * 0x08000000 switch to PLL0
+ * 0xc000fa00 1111 1/01/0 PLL0 off (CFG/RNG 31/1)
+ * 0xc000f200 1111 0/01/0 PLL0 to 20x (CFG/RNG 30/1)
+ * 0x30000004 0000 0/10/0 PLL1 off (CFG/RNG 0/2)
+ * 0x30000054 0101 0/10/0 PLL1 to 5x (CFG/RNG a/2)
+ */
+int proc_dopllvec(ctl_table *table, int write, struct file *filp,
+ void *buffer, size_t *lenp)
+{
+ int vleft, first=1, len, left, val;
+ char buf[TMPBUFLEN], *p;
+#if DEBUG
+ printk(__FILE__"-%d: int proc_dopllvec()\n",__LINE__);
+#endif
+ if (!(cur_cpu_spec[0]->cpu_features & CPU_FTR_DUALPLL))
+ return -EFAULT;
+
+#if DEBUG
+ printk(__FILE__"-%d: int proc_dopllvec()\n",__LINE__);
+#endif
+ if ( /*!table->maxlen ||*/ (filp->f_pos && !write)) {
+ *lenp = 0;
+ return 0;
+ }
+
+ vleft = table->maxlen / sizeof(int);
+ left = *lenp;
+
+ for (; left /*&& vleft--*/; first=0) {
+ if (write) {
+ while (left) {
+ char c;
+ if(get_user(c,(char *) buffer))
+ return -EFAULT;
+ if (!isspace(c))
+ break;
+ left--;
+ buffer++;
+ }
+ if (!left)
+ break;
+ len = left;
+ if (len > TMPBUFLEN-1)
+ len = TMPBUFLEN-1;
+ if(copy_from_user(buf, buffer, len))
+ return -EFAULT;
+ buf[len] = 0;
+ p = buf;
+ if (*p < '0' || *p > '9')
+ break;
+ val = simple_strtoul(p, &p, 0);
+ len = p-buf;
+ if ((len < left) && *p && !isspace(*p))
+ break;
+ buffer += len;
+ left -= len;
+ val=checkPLL(val);
+ } else {
+ static const char *range_string[]={"default","high","low",
+ "reserved"};
+ static const char *fmt_list[]={"off","bypass","%d","%d.5"};
+ char pll0_cfg_ext[8],pll0_cfg[8],pll1_cfg[8];
+ unsigned int pll,temp0,rng0_ext,rng0,rng1;
+
+#if DEBUG
+ printk(__FILE__"-%d: int proc_dopllvec()\n",__LINE__);
+#endif
+ val=0;
+
+ pll=_get_PLL();
+
+#if DEBUG
+ printk(__FILE__"-%d: pll=0x%08x\n",__LINE__,pll);
+#endif
+ temp0=pll>>27;
+
+ switch(temp0)
+ {
+ case 0: case 1: case 31:
+ rng0=0;
+ break;
+ case 2: case 3:
+ rng0=1;
+ break;
+ case 5: case 7: case 9: case 11: case 13:
+ case 15: case 17: case 19:
+ rng0=3;
+ break;
+ default:
+ rng0=2;
+ break;
+ }
+
+ if(temp0>20) temp0=(temp0-10)<<1;
+
+ sprintf(pll0_cfg_ext,fmt_list[rng0],temp0>>1);
+
+ rng0_ext=(pll>>25)&0x3;
+
+ temp0=_get_PLL_ratio(0,pll);
+
+ switch(temp0)
+ {
+ case 0: case 1: case 31:
+ rng0=0;
+ break;
+ case 2: case 3:
+ rng0=1;
+ break;
+ case 5: case 7: case 9: case 11: case 13:
+ case 15: case 17: case 19:
+ rng0=3;
+ break;
+ default:
+ rng0=2;
+ break;
+ }
+
+ if(temp0>20) temp0=(temp0-10)<<1;
+
+ sprintf(pll0_cfg,fmt_list[rng0],temp0>>1);
+
+ rng0=_get_PLL_range(0,pll);
+
+ temp0=_get_PLL_ratio(1,pll);
+
+ switch(temp0)
+ {
+ case 0: case 1: case 31:
+ rng1=0;
+ break;
+ case 2: case 3:
+ rng1=1;
+ break;
+ case 5: case 7: case 9: case 11: case 13:
+ case 15: case 17: case 19:
+ rng1=3;
+ break;
+ default:
+ rng1=2;
+ break;
+ }
+
+ if(temp0>20) temp0=(temp0-10)<<1;
+
+ sprintf(pll1_cfg,fmt_list[rng1],temp0>>1);
+
+ rng1=_get_PLL_range(1,pll);
+
+ sprintf(buf,"0x%08x: PLL0 external (%s, %s), PLL %d "
+ "selected, PLL0 %s, PLL0 (%s, %s), PLL1 (%s, "
+ "%s)\n",pll,pll0_cfg_ext,range_string[rng0_ext],
+ _get_active_PLL(pll),(pll>>17)&0x1?"internal":
+ "external",pll0_cfg,range_string[rng0],
+ pll1_cfg,range_string[rng1]);
+
+ len = strlen(buf);
+ if (len > left)
+ len = left;
+ if(copy_to_user(buffer, buf, len))
+ return -EFAULT;
+ left -= len;
+ buffer += len;
+ break;
+ }
+ }
+
+ if (!write && !first && left) {
+ if(put_user('\n', (char *) buffer))
+ return -EFAULT;
+ left--, buffer++;
+ }
+ if (write) {
+ p = (char *) buffer;
+ while (left) {
+ char c;
+ if(get_user(c, p++))
+ return -EFAULT;
+ if (!isspace(c))
+ break;
+ left--;
+ }
+ }
+ if (write && first)
+ return -EINVAL;
+ *lenp -= left;
+ filp->f_pos += *lenp;
+
+ return val;
+}
diff -Naur linux-2.4.30.orig/arch/ppc/kernel/ppc_htab.c linux-2.4.30/arch/ppc/kernel/ppc_htab.c
--- linux-2.4.30.orig/arch/ppc/kernel/ppc_htab.c Thu Apr 7 22:26:06 2005
+++ linux-2.4.30/arch/ppc/kernel/ppc_htab.c Wed Jun 22 10:41:26 2005
@@ -510,7 +510,15 @@
left -= len;
_set_L2CR(val);
} else {
- int is750fx = cur_cpu_spec[0]->cpu_features & CPU_FTR_750FX;
+ int is750fgx = cur_cpu_spec[0]->cpu_features &
+ (CPU_FTR_750FX | CPU_FTR_750GX);
+
+ /*
+ * For identifying memory size
+ */
+ if(is750fgx) is750fgx=(cur_cpu_spec[0]->cpu_features
+ & CPU_FTR_750GX)?3:2;
+
p = buf;
if (!first)
*p++ = '\t';
@@ -520,7 +528,7 @@
"disabled");
if (!(val>>30&1))
p += sprintf(p, "no ");
- if (is750fx)
+ if (is750fgx)
p += sprintf(p, "ECC checkstop");
else
p += sprintf(p, "parity");
@@ -528,7 +536,7 @@
/* 75x & 74x0 have different L2CR than 745x */
if (!(cur_cpu_spec[0]->cpu_features &
CPU_FTR_SPEC7450)) {
- if (!is750fx) {
+ if (!is750fgx) {
p += sprintf(p, ", %s",
sizestrings[(val >> 28) & 3]);
p += sprintf(p, ", %s",
@@ -536,9 +544,14 @@
p += sprintf(p, ", %s",
typestrings[(val >> 23) & 3]);
}
+ else
+ p += sprintf(p, ", %s, +1 clock, "
+ "on chip, ",sizestrings[
+ is750fgx]);
+
p += sprintf(p, "%s", (val>>22)&1 ?
", data only" : "");
- if (!is750fx) {
+ if (!is750fgx) {
p += sprintf(p, "%s", (val>>20)&1 ?
", ZZ enabled": "");
}
@@ -546,7 +559,7 @@
"write-through" : "copy-back");
p += sprintf(p, "%s", (val>>18)&1 ?
", testing" : "");
- if (!is750fx) {
+ if (!is750fgx) {
p += sprintf(p, ", %sns hold",
holdstrings[(val>>16)&3]);
p += sprintf(p, "%s", (val>>15)&1 ?
diff -Naur linux-2.4.30.orig/include/asm-ppc/cputable.h linux-2.4.30/include/asm-ppc/cputable.h
--- linux-2.4.30.orig/include/asm-ppc/cputable.h Thu Apr 7 22:26:22 2005
+++ linux-2.4.30/include/asm-ppc/cputable.h Tue Jun 14 01:52:54 2005
@@ -76,6 +76,8 @@
#define CPU_FTR_NO_DPM 0x00008000
#define CPU_FTR_HAS_HIGH_BATS 0x00010000
#define CPU_FTR_NEED_COHERENT 0x00020000
+#define CPU_FTR_750GX 0x00040000
+#define CPU_FTR_DUALPLL 0x00080000
#ifdef __ASSEMBLY__
diff -Naur linux-2.4.30.orig/include/asm-ppc/pll.h linux-2.4.30/include/asm-ppc/pll.h
--- linux-2.4.30.orig/include/asm-ppc/pll.h Wed Dec 31 16:00:00 1969
+++ linux-2.4.30/include/asm-ppc/pll.h Thu Jun 23 11:32:28 2005
@@ -0,0 +1,125 @@
+#ifndef __PPC_PLL_H
+#define __PPC_PLL_H
+/*
+ Dual PLL functions, for 750FX & 750GX
+ Copyright © 2005 by Kevin Diggs
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+*/
+/*
+ Tue, June 14, 2005.
+ - First public release, contributed by Kevin Diggs.
+ ***********
+ ***********
+
+ Author: Kevin Diggs ()
+ Please e-mail updates to this file to me, thanks!
+*/
+#include <linux/config.h>
+#include <asm/processor.h>
+#include <asm/cputable.h>
+#include <asm/ppc_asm.h>
+#include <asm/cache.h>
+
+/*
+ The layout of the PLL register (HID1) is:
+
+ 0 4|5 6|7|8| 9 11|12 13|14| 15 |16 20|21 22|23|24 28|29 30| 31
+ PCE |PRE|v|v| Res | Res |v | PS | PC0 | PR0 |v | PC1 | PR1 |Res
+ | | | |
+ PSTAT1 -| | | |
+ ECLK -----| | |
+ PI0 --------------------| |
+ Res ----------------------------------------|
+
+ PCE PLL0 read-only external config
+ PRE PLL0 read-only external range
+ PSTAT1 PLL status (0 -> PLL0, 1 -> PLL1)
+ ECLK 1 -> enable clkout pin
+ PI0 PLL0 control: 0 -> external
+ PS PLL select: 0 -> PLL0, 1 -> PLL1
+ PC0 PLL0 configuration
+ PR0 PLL0 range
+ PC1 PLL1 configuration
+ PR1 PLL1 range
+
+ PLL_CFG bus ratio PLL_CFG bus ratio
+ 00000 off 10000 8
+ 00001 off 10001 8.5
+ 00010 bypass 10010 9
+ 00011 bypass 10011 9.5
+ 00100 2 10100 10
+ 00101 2.5 10101 11
+ 00110 3 10110 12
+ 00111 3.5 10111 13
+ 01000 4 11000 14
+ 01001 4.5 11001 15
+ 01010 5 11010 16
+ 01011 5.5 11011 17
+ 01100 6 11100 18
+ 01101 6.5 11101 19
+ 01110 7 11110 20
+ 01111 7.5 11111 off
+
+ PLL_RNG range
+ 00 600 - 900
+ 01 900 - 1000
+ 10 500 - 600
+
+ * Update the value of the PLL configuration register based on the crap passed
+ * in. The upper 8 bits (0 - 7) are read only and will be used as flags to con-
+ * trol what we are doing:
+ * 0x80 PLL0 configuration is valid
+ * 0x40 PLL0 range is valid
+ * 0x20 PLL1 configuration is valid
+ * 0x10 PLL1 range is valid
+ * 0x08 PLL select is valid
+ * 0x04 PLL0 control is valid
+ *
+ * Make sure that sufficient time (100 us) is given for a PLL that is changed
+ * to relock before selecting it.
+ */
+
+#define PLL0_DO_CFG (0x80)
+#define PLL0_DO_RNG (0x40)
+#define PLL1_DO_CFG (0x20)
+#define PLL1_DO_RNG (0x10)
+#define PLL_DO_SEL (0x08)
+#define PLL0_DO_CONTROL (0x04)
+
+#define PLL0_CONTROL_MASK (0x20000)
+#define PLL_SEL_MASK (0x10000)
+#define PLL0_CFG_MASK (0x0f800)
+#define PLL0_RNG_MASK (0x00600)
+#define PLL1_CFG_MASK (0x000f8)
+#define PLL1_RNG_MASK (0x00006)
+
+#define PLL_LOCK (0x80000000) /* Code lock bit */
+#define PLL_LOCK_BIT (31)
+#define PLL_TIMER (0x40000000) /* Timer is scheduled */
+#define PLL_TIMER_BIT (30)
+#define PLL0_LOCK (0x20000000) /* PLL 0 unsynced */
+#define PLL0_LOCK_BIT (29)
+#define PLL1_LOCK (0x10000000) /* PLL 1 unsynced */
+#define PLL1_LOCK_BIT (28)
+
+extern int _get_PLL(void);
+extern int _get_active_PLL(unsigned int pll);
+extern int _get_next_PLL(unsigned int pll);
+extern int _get_PLL_ratio(int which, unsigned int pll);
+extern int _get_PLL_range(int which, unsigned int pll);
+extern int _set_PLL(unsigned int pll);
+
+#endif
diff -Naur linux-2.4.30.orig/include/linux/sysctl.h linux-2.4.30/include/linux/sysctl.h
--- linux-2.4.30.orig/include/linux/sysctl.h Sat May 28 22:47:35 2005
+++ linux-2.4.30/include/linux/sysctl.h Tue Jun 14 01:26:41 2005
@@ -128,6 +128,7 @@
KERN_PPC_L3CR=57, /* l3cr register on PPC */
KERN_EXCEPTION_TRACE=58, /* boolean: exception trace */
KERN_CORE_SETUID=59, /* int: set to allow core dumps of setuid apps */
+ KERN_PPC_PLL=60, /* PLL control register (HID1) on some PPC */
KERN_SPARC_SCONS_PWROFF=64, /* int: serial console power-off halt */
};
diff -Naur linux-2.4.30.orig/kernel/sysctl.c linux-2.4.30/kernel/sysctl.c
--- linux-2.4.30.orig/kernel/sysctl.c Thu Apr 7 22:27:17 2005
+++ linux-2.4.30/kernel/sysctl.c Tue Jun 21 20:22:23 2005
@@ -100,6 +100,8 @@
void *buffer, size_t *lenp);
int proc_dol3crvec(ctl_table *table, int write, struct file *filp,
void *buffer, size_t *lenp);
+int proc_dopllvec(ctl_table *table, int write, struct file *filp,
+ void *buffer, size_t *lenp);
#endif
#ifdef CONFIG_BSD_PROCESS_ACCT
@@ -210,6 +212,10 @@
0644, NULL, &proc_dol2crvec},
{KERN_PPC_L3CR, "l3cr", NULL, 0,
0644, NULL, &proc_dol3crvec},
+#ifdef CONFIG_DUAL_PLL
+ {KERN_PPC_PLL, "pll", NULL, 0,
+ 0644, NULL, &proc_dopllvec},
+#endif
#endif
{KERN_CTLALTDEL, "ctrl-alt-del", &C_A_D, sizeof(int),
0644, NULL, &proc_dointvec},
^ permalink raw reply
* Reducing glibc with mklibs.sh
From: Orlov, Leonid @ 2005-07-26 16:53 UTC (permalink / raw)
To: linuxppc-embedded
[-- Attachment #1: Type: text/plain, Size: 274 bytes --]
Do you have an example of library reduction experience using mklibs.
I created a library with 3 functions and use only 2 in main.
I have hard time to make it work in this simple environment.
I must be missing something.
Thanks for your help.
Leonid Orlov
Los Angeles
[-- Attachment #2: Type: text/html, Size: 1085 bytes --]
^ permalink raw reply
* Re: [PATCH 3/3] MTD support for the Bamboo board
From: Wade Farnsworth @ 2005-07-26 17:09 UTC (permalink / raw)
To: Eugene Surovegin; +Cc: linuxppc-embedded
In-Reply-To: <20050726164034.GE2906@gate.ebshome.net>
[-- Attachment #1: Type: text/plain, Size: 1286 bytes --]
On Tue, 2005-07-26 at 09:40, Eugene Surovegin wrote:
> On Tue, Jul 26, 2005 at 09:06:14AM -0700, Wade Farnsworth wrote:
> > This adds MTD support for the Bamboo board.
> >
> > Signed-off by: Wade Farnsworth <wfarnsworth@mvista.com>
>
> > diff -uprN linux-2.6.12/drivers/mtd/maps/Kconfig.orig linux-2.6.12-440ep/drivers/mtd/maps/Kconfig.orig
> > --- linux-2.6.12/drivers/mtd/maps/Kconfig.orig 1969-12-31 17:00:00.000000000 -0700
> > +++ linux-2.6.12-440ep/drivers/mtd/maps/Kconfig.orig 2005-07-25 11:31:51.000000000 -0700
>
> This hunk seems to be bogus.
>
> > diff -uprN linux-2.6.12/drivers/mtd/maps/Makefile.orig linux-2.6.12-440ep/drivers/mtd/maps/Makefile.orig
> > --- linux-2.6.12/drivers/mtd/maps/Makefile.orig 1969-12-31 17:00:00.000000000 -0700
> > +++ linux-2.6.12-440ep/drivers/mtd/maps/Makefile.orig 2005-07-25 11:31:51.000000000 -0700
>
> Ditto.
>
> > diff -uprN linux-2.6.12/drivers/mtd/nand/Kconfig.orig linux-2.6.12-440ep/drivers/mtd/nand/Kconfig.orig
> > --- linux-2.6.12/drivers/mtd/nand/Kconfig.orig 1969-12-31 17:00:00.000000000 -0700
> > +++ linux-2.6.12-440ep/drivers/mtd/nand/Kconfig.orig 2005-07-25 11:31:51.000000000 -0700
>
> Ditto
Oops. Sorry about that. This patch removes the bogus hunks.
Signed-off by: Wade Farnsworth <wfarnsworth@mvista.com>
[-- Attachment #2: 440ep-mtd.patch --]
[-- Type: text/x-patch, Size: 21076 bytes --]
diff -uprN linux-2.6/drivers/mtd/maps/Kconfig linux-2.6-440ep/drivers/mtd/maps/Kconfig
--- linux-2.6/drivers/mtd/maps/Kconfig 2005-06-28 10:49:46.000000000 -0700
+++ linux-2.6-440ep/drivers/mtd/maps/Kconfig 2005-06-28 12:42:54.000000000 -0700
@@ -396,6 +396,13 @@ config MTD_OCOTEA
This enables access routines for the flash chips on the IBM 440GX
Ocotea board. If you have one of these boards and would like to
use the flash chips on it, say 'Y'.
+config MTD_BAMBOO
+ tristate "Flash devices mapped on IBM 440EP Bamboo"
+ depends on MTD_CFI && PPC32 && 44x && BAMBOO
+ help
+ This enables access routined for the flash chips on the IBM 440EP
+ Bamboo board. If you have one of these boards and would like to
+ use the flash chips on it, say 'Y'.
config MTD_REDWOOD
tristate "CFI Flash devices mapped on IBM Redwood"
diff -uprN linux-2.6/drivers/mtd/maps/Makefile linux-2.6-440ep/drivers/mtd/maps/Makefile
--- linux-2.6/drivers/mtd/maps/Makefile 2005-06-28 10:49:46.000000000 -0700
+++ linux-2.6-440ep/drivers/mtd/maps/Makefile 2005-06-28 12:43:29.000000000 -0700
@@ -59,6 +59,7 @@ obj-$(CONFIG_MTD_NETtel) += nettel.o
obj-$(CONFIG_MTD_SCB2_FLASH) += scb2_flash.o
obj-$(CONFIG_MTD_EBONY) += ebony.o
obj-$(CONFIG_MTD_OCOTEA) += ocotea.o
+obj-$(CONFIG_MTD_BAMBOO) += bamboo.o
obj-$(CONFIG_MTD_BEECH) += beech-mtd.o
obj-$(CONFIG_MTD_ARCTIC) += arctic-mtd.o
obj-$(CONFIG_MTD_WALNUT) += walnut.o
diff -uprN linux-2.6/drivers/mtd/maps/bamboo.c linux-2.6-440ep/drivers/mtd/maps/bamboo.c
--- linux-2.6/drivers/mtd/maps/bamboo.c 1969-12-31 17:00:00.000000000 -0700
+++ linux-2.6-440ep/drivers/mtd/maps/bamboo.c 2005-06-28 12:43:58.000000000 -0700
@@ -0,0 +1,245 @@
+/*
+ * Mapping for Bamboo user flash
+ *
+ * Wade Farnsworth <wfarnsworth@mvista.com>
+ *
+ * Copyright 2005 MontaVista Software Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/map.h>
+#include <linux/mtd/partitions.h>
+#include <linux/config.h>
+#include <asm/io.h>
+#include <asm/ibm44x.h>
+#include <platforms/4xx/bamboo.h>
+
+static struct mtd_info *small_flash, *large_flash, *sram;
+
+static struct map_info bamboo_small_map = {
+ .name = "Bamboo small flash",
+ .size = BAMBOO_SMALL_FLASH_SIZE,
+ .bankwidth = 1,
+};
+
+static struct map_info bamboo_large_map = {
+ .name = "Bamboo large flash",
+ .size = BAMBOO_LARGE_FLASH_SIZE,
+ .bankwidth = 2,
+};
+
+static struct map_info bamboo_sram_map = {
+ .name = "Bamboo SRAM",
+ .size = BAMBOO_SRAM_SIZE,
+ .bankwidth = 2,
+};
+
+static struct mtd_partition bamboo_small_partitions[] = {
+ {
+ .name = "pibs",
+ .offset = 0x0,
+ .size = 0x100000,
+ .mask_flags = MTD_WRITEABLE,
+ }
+};
+
+static struct mtd_partition bamboo_large_partitions[] = {
+ {
+ .name = "filesystem",
+ .offset = 0x0,
+ .size = 0x400000,
+ }
+};
+
+static struct mtd_partition bamboo_sram_partitions[] = {
+ {
+ .name = "sram",
+ .offset = 0x0,
+ .size = 0x100000,
+ }
+};
+
+int __init
+init_bamboo(void)
+{
+ u8 setting_reg;
+ u8 *setting_adr;
+ unsigned long small_flash_base, large_flash_base, sram_base;
+ unsigned long *gpio_base;
+
+ setting_adr = ioremap64(BAMBOO_FPGA_SETTING_REG_ADDR, 8);
+ if (!setting_adr)
+ return -ENOMEM;
+ setting_reg = readb(setting_adr);
+ iounmap(setting_adr);
+
+ /*
+ * Some versions of PIBS don't set up the GPIO controller
+ * for the devices on chip select 4 (large flash and sram).
+ */
+ gpio_base = ioremap64(0x0EF600B00ULL, 0x80);
+ if (!gpio_base) {
+ printk("Failed to ioremap GPIO\n");
+ return -ENOMEM;
+ }
+ * (gpio_base + 0x02) |= 0x00001000;
+ * (gpio_base + 0x04) |= 0x00001000;
+ iounmap((void *) gpio_base);
+
+ /*
+ * Use the values in the FPGA Setting Register to determine where
+ * each flash bank is located.
+ */
+ if (!BAMBOO_BOOT_NAND_FLASH(setting_reg)) {
+ if (BAMBOO_BOOT_SMALL_FLASH(setting_reg)) {
+ small_flash_base = BAMBOO_SMALL_FLASH_HIGH;
+ } else {
+ small_flash_base = BAMBOO_SMALL_FLASH_LOW;
+ }
+
+ bamboo_small_map.phys = small_flash_base;
+ bamboo_small_map.virt =
+ (ulong *) ioremap64(small_flash_base,
+ bamboo_small_map.size);
+ if (!bamboo_small_map.virt) {
+ printk("Failed to ioremap flash\n");
+ return -EIO;
+ }
+
+ simple_map_init(&bamboo_small_map);
+
+ small_flash = do_map_probe("map_rom", &bamboo_small_map);
+ if (small_flash) {
+ small_flash->owner = THIS_MODULE;
+ add_mtd_partitions(small_flash, bamboo_small_partitions,
+ ARRAY_SIZE(bamboo_small_partitions));
+ } else {
+ printk(KERN_INFO
+ "small flash disabled: Probe failed due to probable hardware issue\n");
+ iounmap((void *) bamboo_small_map.virt);
+ bamboo_small_map.virt = 0;
+ }
+ } else
+ bamboo_small_map.virt = 0;
+
+ /*
+ * Wiring to the large flash on the Rev 0 Bamboo is incorrect, so
+ * this should fail.
+ *
+ * This has been fixed on the Rev 1.
+ */
+ if (BAMBOO_BOOT_NAND_FLASH(setting_reg) ||
+ BAMBOO_BOOT_SMALL_FLASH(setting_reg))
+ large_flash_base = BAMBOO_LARGE_FLASH_LOW;
+ else if (BAMBOO_LARGE_FLASH_EN(setting_reg))
+ large_flash_base = BAMBOO_LARGE_FLASH_HIGH1;
+ else
+ large_flash_base = BAMBOO_LARGE_FLASH_HIGH2;
+ bamboo_large_map.phys = large_flash_base;
+ bamboo_large_map.virt = (ulong *) ioremap64(large_flash_base,
+ bamboo_large_map.size);
+ if (!bamboo_large_map.virt) {
+ printk("Failed to ioremap flash\n");
+ return -EIO;
+ }
+
+ simple_map_init(&bamboo_large_map);
+ large_flash = do_map_probe("cfi_probe", &bamboo_large_map);
+ if (large_flash) {
+ large_flash->owner = THIS_MODULE;
+ add_mtd_partitions(large_flash, bamboo_large_partitions,
+ ARRAY_SIZE(bamboo_large_partitions));
+ } else {
+ printk(KERN_INFO
+ "large flash disabled: Probe failed due to probable hardware issue\n");
+ iounmap((void *) bamboo_large_map.virt);
+ bamboo_large_map.virt = 0;
+ }
+
+ if (BAMBOO_BOOT_NAND_FLASH(setting_reg) ||
+ BAMBOO_BOOT_SMALL_FLASH(setting_reg))
+ sram_base = BAMBOO_SRAM_LOW;
+ else if (BAMBOO_LARGE_FLASH_EN(setting_reg))
+ sram_base = BAMBOO_SRAM_HIGH2;
+ else
+ sram_base = BAMBOO_SRAM_HIGH1;
+
+ bamboo_sram_map.phys = sram_base;
+ bamboo_sram_map.virt = (ulong *) ioremap64(sram_base,
+ bamboo_sram_map.size);
+ if (!bamboo_sram_map.virt) {
+ printk("Failed to ioremap flash \n");
+ return -EIO;
+ }
+
+ simple_map_init(&bamboo_sram_map);
+
+ sram = do_map_probe("map_ram", &bamboo_sram_map);
+ if (sram) {
+ sram->owner = THIS_MODULE;
+ sram->erasesize = 0x10;
+ add_mtd_partitions(sram, bamboo_sram_partitions,
+ ARRAY_SIZE(bamboo_sram_partitions));
+ } else {
+ printk(KERN_INFO
+ "sram disabled: Probe failed due to probable hardware issue\n");
+ iounmap((void *) bamboo_sram_map.virt);
+ bamboo_sram_map.virt = 0;
+ }
+
+ if (!(small_flash || large_flash || sram))
+ return -ENXIO;
+
+ return 0;
+}
+
+static void __exit
+cleanup_bamboo(void)
+{
+ if (small_flash) {
+ del_mtd_partitions(small_flash);
+ map_destroy(small_flash);
+ }
+
+ if (large_flash) {
+ del_mtd_partitions(large_flash);
+ map_destroy(large_flash);
+ }
+
+ if (sram) {
+ del_mtd_partitions(sram);
+ map_destroy(sram);
+ }
+
+ if (bamboo_small_map.virt) {
+ iounmap((void *) bamboo_small_map.virt);
+ bamboo_small_map.virt = 0;
+ }
+
+ if (bamboo_large_map.virt) {
+ iounmap((void *) bamboo_large_map.virt);
+ bamboo_large_map.virt = 0;
+ }
+
+ if (bamboo_sram_map.virt) {
+ iounmap((void *) bamboo_sram_map.virt);
+ bamboo_sram_map.virt = 0;
+ }
+}
+
+module_init(init_bamboo);
+module_exit(cleanup_bamboo);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Wade Farnsworth <wfarnsworth@mvista.com>");
+MODULE_DESCRIPTION("MTD map and partitions for IBM 440EP Bamboo boards");
diff -uprN linux-2.6/drivers/mtd/nand/Kconfig linux-2.6-440ep/drivers/mtd/nand/Kconfig
--- linux-2.6/drivers/mtd/nand/Kconfig 2005-06-28 10:49:47.000000000 -0700
+++ linux-2.6-440ep/drivers/mtd/nand/Kconfig 2005-06-28 12:45:03.000000000 -0700
@@ -122,6 +122,13 @@ config MTD_NAND_S3C2410_HWECC
currently not be able to switch to software, as there is no
implementation for ECC method used by the S3C2410
+config MTD_NAND_BAMBOO
+ tristate "NAND flash support on IBM/AMCC 440EP Eval Board (Bamboo)"
+ depends on BAMBOO && MTD_NAND
+ help
+ This enables the NAND flash driver on the IBM/AMCC 440EP Eval Board
+ (Bamboo).
+
config MTD_NAND_DISKONCHIP
tristate "DiskOnChip 2000, Millennium and Millennium Plus (NAND reimplementation) (EXPERIMENTAL)"
depends on MTD_NAND && EXPERIMENTAL
diff -uprN linux-2.6/drivers/mtd/nand/Makefile linux-2.6-440ep/drivers/mtd/nand/Makefile
--- linux-2.6/drivers/mtd/nand/Makefile 2005-06-28 10:49:47.000000000 -0700
+++ linux-2.6-440ep/drivers/mtd/nand/Makefile 2005-06-28 12:45:34.000000000 -0700
@@ -15,6 +15,7 @@ obj-$(CONFIG_MTD_NAND_TX4938NDFMC) += tx
obj-$(CONFIG_MTD_NAND_AU1550) += au1550nd.o
obj-$(CONFIG_MTD_NAND_PPCHAMELEONEVB) += ppchameleonevb.o
obj-$(CONFIG_MTD_NAND_S3C2410) += s3c2410.o
+obj-$(CONFIG_MTD_NAND_BAMBOO) += bamboo_nand.o
obj-$(CONFIG_MTD_NAND_DISKONCHIP) += diskonchip.o
obj-$(CONFIG_MTD_NAND_H1900) += h1910.o
obj-$(CONFIG_MTD_NAND_RTC_FROM4) += rtc_from4.o
diff -uprN linux-2.6/drivers/mtd/nand/bamboo_nand.c linux-2.6-440ep/drivers/mtd/nand/bamboo_nand.c
--- linux-2.6/drivers/mtd/nand/bamboo_nand.c 1969-12-31 17:00:00.000000000 -0700
+++ linux-2.6-440ep/drivers/mtd/nand/bamboo_nand.c 2005-06-28 12:45:43.000000000 -0700
@@ -0,0 +1,467 @@
+/*
+ * drivers/mtd/bamboo_nand.c
+ *
+ * Overview:
+ * This is a device driver for the NAND flash devices found on the
+ * IBM 440EP Evaluation Board (Bamboo).
+ *
+ * Author: Wade Farnsworth <wfarnsworth@mvista.com>
+ *
+ * Copyright 2005 MontaVista Software Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/nand_ecc.h>
+#include <linux/mtd/partitions.h>
+#include <linux/config.h>
+#include <linux/delay.h>
+#include <linux/slab.h>
+#include <asm/io.h>
+#include <asm/ibm44x.h>
+#include <platforms/4xx/bamboo.h>
+
+struct ppc440ep_ndfc_regs {
+ uint cmd;
+ uint addr;
+ uint data;
+ uint reserved1;
+ uint ecc0;
+ uint ecc1;
+ uint ecc2;
+ uint ecc3;
+ uint ecc4;
+ uint ecc5;
+ uint ecc6;
+ uint ecc7;
+ uint b0cr;
+ uint b1cr;
+ uint b2cr;
+ uint b3cr;
+ uint cr;
+ uint sr;
+ uint hwctl;
+ uint reserved2;
+ uint revid;
+};
+
+static struct mtd_info *bamboo_nand0_mtd;
+static struct mtd_info *bamboo_nand1_mtd;
+static u8 hwctl;
+static struct ppc440ep_ndfc_regs *bamboo_ndfc;
+
+#define NAND0_NUM_PARTITIONS 1
+static struct mtd_partition nand0_partition_info[] = {
+ {
+ .name = "filesystem",
+ .offset = 0x0,
+ .size = 0x4000000,
+ },
+};
+
+#define NAND1_NUM_PARTITIONS 1
+static struct mtd_partition nand1_partition_info[] = {
+ {
+ .name = "filesystem",
+ .offset = 0x0,
+ .size = 0x10000000,
+ }
+};
+
+/*
+ * The 440EP has a NAND Flash Controller (NDFC) that handles all accesses to
+ * the NAND devices. The NDFC has command, address and data registers that
+ * when accessed will set up the NAND flash pins appropriately. We'll use the
+ * hwcontrol function to save the configuration in a global variable.
+ * We can then use this information in the read and write functions to
+ * determine which NDFC register to access. For the NCE commands, we'll just
+ * set or clear the Bank Enable bit in the NDFC Bank Config registers.
+ *
+ * There are 2 NAND devices on the board, a Samsung K9F1208U0A (64 MB) and a
+ * Samsung K9K2G08U0M (256 MB).
+ */
+static void
+bamboo_hwcontrol(struct mtd_info *mtd, int cmd)
+{
+ switch (cmd) {
+ case NAND_CTL_SETCLE:
+ hwctl |= 0x1;
+ break;
+ case NAND_CTL_CLRCLE:
+ hwctl &= ~0x1;
+ break;
+ case NAND_CTL_SETALE:
+ hwctl |= 0x2;
+ break;
+ case NAND_CTL_CLRALE:
+ hwctl &= ~0x2;
+ break;
+ }
+}
+
+static void
+bamboo_nand0_hwcontrol(struct mtd_info *mtd, int cmd)
+{
+ switch(cmd) {
+ case NAND_CTL_SETNCE:
+ bamboo_ndfc->b1cr |= 0x80000000;
+ break;
+ case NAND_CTL_CLRNCE:
+ bamboo_ndfc->b1cr &= ~0x80000000;
+ break;
+ default:
+ bamboo_hwcontrol(mtd, cmd);
+ }
+}
+
+static void
+bamboo_nand1_hwcontrol(struct mtd_info *mtd, int cmd)
+{
+ switch(cmd) {
+ case NAND_CTL_SETNCE:
+ bamboo_ndfc->b2cr |= 0x80000000;
+ break;
+ case NAND_CTL_CLRNCE:
+ bamboo_ndfc->b2cr &= ~0x80000000;
+ break;
+ default:
+ bamboo_hwcontrol(mtd, cmd);
+ }
+}
+
+static void
+bamboo_nand0_enable(void)
+{
+ bamboo_ndfc->cr = 0x01001000;
+}
+
+static void
+bamboo_nand1_enable(void)
+{
+ bamboo_ndfc->cr = 0x02003000;
+}
+
+static void
+bamboo_write_byte(struct mtd_info *mtd, u_char byte)
+{
+ if (hwctl & 0x1)
+ writeb(byte, &(bamboo_ndfc->cmd));
+ else if (hwctl & 0x2)
+ writeb(byte, &(bamboo_ndfc->addr));
+ else
+ writeb(byte, &(bamboo_ndfc->data));
+}
+
+static void
+bamboo_nand0_write_byte(struct mtd_info *mtd, u_char byte)
+{
+ bamboo_nand0_enable();
+ bamboo_write_byte(mtd, byte);
+}
+
+static void
+bamboo_nand1_write_byte(struct mtd_info *mtd, u_char byte)
+{
+ bamboo_nand1_enable();
+ bamboo_write_byte(mtd,byte);
+}
+
+static u_char
+bamboo_read_byte(struct mtd_info *mtd)
+{
+ u_char retval;
+ if (hwctl & 0x1)
+ retval = readb(&(bamboo_ndfc->cmd));
+ else if (hwctl & 0x2)
+ retval = readb(&(bamboo_ndfc->addr));
+ else
+ retval = readb(&(bamboo_ndfc->data));
+ return retval;
+}
+
+static u_char
+bamboo_nand0_read_byte(struct mtd_info *mtd)
+{
+ bamboo_nand0_enable();
+ return bamboo_read_byte(mtd);
+}
+
+static u_char
+bamboo_nand1_read_byte(struct mtd_info *mtd)
+{
+ bamboo_nand1_enable();
+ return bamboo_read_byte(mtd);
+}
+
+static void
+bamboo_nand_write_buf(struct mtd_info *mtd, const u_char * buf, int len)
+{
+ int i;
+ for (i = 0; i < len; i++) {
+ if (hwctl & 0x1)
+ writeb(buf[i], &(bamboo_ndfc->cmd));
+ else if (hwctl & 0x2)
+ writeb(buf[i], &(bamboo_ndfc->addr));
+ else
+ writeb(buf[i], &(bamboo_ndfc->data));
+ }
+}
+
+static void
+bamboo_nand0_write_buf(struct mtd_info *mtd, const u_char * buf, int len)
+{
+ bamboo_nand0_enable();
+ bamboo_nand_write_buf(mtd, buf, len);
+}
+
+static void
+bamboo_nand1_write_buf(struct mtd_info *mtd, const u_char * buf, int len)
+{
+ bamboo_nand1_enable();
+ bamboo_nand_write_buf(mtd, buf, len);
+}
+
+static void
+bamboo_nand_read_buf(struct mtd_info *mtd, u_char * buf, int len)
+{
+ int i;
+
+ for (i = 0; i < len; i++) {
+ if (hwctl & 0x1)
+ buf[i] = readb(&(bamboo_ndfc->cmd));
+ else if (hwctl & 0x2)
+ buf[i] = readb(&(bamboo_ndfc->addr));
+ else
+ buf[i] = readb(&(bamboo_ndfc->data));
+ }
+}
+
+static void
+bamboo_nand0_read_buf(struct mtd_info *mtd, u_char * buf, int len)
+{
+ bamboo_nand0_enable();
+ bamboo_nand_read_buf(mtd, buf, len);
+}
+
+static void
+bamboo_nand1_read_buf(struct mtd_info *mtd, u_char * buf, int len)
+{
+ bamboo_nand1_enable();
+ bamboo_nand_read_buf(mtd, buf, len);
+}
+
+static int
+bamboo_nand_verify_buf(struct mtd_info *mtd, const u_char * buf, int len)
+{
+ int i;
+
+ for (i = 0; i < len; i++) {
+ if (hwctl & 0x1) {
+ if (buf[i] != readb(&(bamboo_ndfc->cmd)))
+ return i;
+ } else if (hwctl & 0x2) {
+ if (buf[i] != readb(&(bamboo_ndfc->addr)))
+ return i;
+ } else {
+ if (buf[i] != readb(&(bamboo_ndfc->data)))
+ return i;
+ }
+
+ }
+
+ return 0;
+}
+
+static int
+bamboo_nand0_verify_buf(struct mtd_info *mtd, const u_char * buf, int len)
+{
+ bamboo_nand0_enable();
+ return bamboo_nand_verify_buf(mtd, buf, len);
+}
+
+static int
+bamboo_nand1_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
+{
+ bamboo_nand1_enable();
+ return bamboo_nand_verify_buf(mtd, buf, len);
+}
+
+static int
+bamboo_dev_ready(struct mtd_info *mtd)
+{
+ return ((bamboo_ndfc->sr) & 0x01000000) ? 1 : 0;
+}
+
+int __init
+bamboo_init(void)
+{
+ struct nand_chip *this;
+ uint * selection1_base, * gpio_base;
+ u8 selection1_val;
+ int err = 0;
+
+ hwctl = 0;
+
+ /*
+ * Bank 0 was set up by the firmware already. Bank 1 wasn't, so set it
+ * up now.
+ */
+
+ selection1_base = ioremap64(BAMBOO_FPGA_SELECTION1_REG_ADDR, 8);
+ if(!selection1_base){
+ printk("Ioremap to access FPGA Selection Register 1 failed \n");
+ err = -EIO;
+ goto out;
+ }
+ selection1_val = readb(selection1_base);
+ selection1_val |= 0x02;
+ writeb(selection1_val, selection1_base);
+ iounmap((void *)(selection1_base));
+
+ SDR_WRITE(DCRN_SDR_CUST0, SDR_READ(DCRN_SDR_CUST0) | 0x2);
+
+ gpio_base = ioremap64(0x0EF600B00ULL, 0x80);
+ if(!gpio_base) {
+ printk("Ioremap to access GPIO Registers failed \n");
+ err = -EIO;
+ goto out;
+ }
+ *(uint *) (gpio_base + 0x2) |= 0x00010000;
+ *(uint *) (gpio_base + 0x4) |= 0x00010000;
+ iounmap((void *) gpio_base);
+
+ bamboo_nand0_mtd = kmalloc(sizeof(struct mtd_info) +
+ sizeof(struct nand_chip),
+ GFP_KERNEL);
+
+ bamboo_nand1_mtd = kmalloc(sizeof (struct mtd_info) +
+ sizeof (struct nand_chip),
+ GFP_KERNEL);
+ if (!bamboo_nand1_mtd) {
+ printk("Unable to allocate NAND 1 MTD device structure.\n");
+ err = -ENOMEM;
+ goto out_mtd0;
+ }
+
+ bamboo_ndfc = ioremap64(BAMBOO_NAND_FLASH_REG_ADDR,
+ BAMBOO_NAND_FLASH_REG_SIZE);
+ if (!bamboo_ndfc) {
+ printk("Ioremap to access NDFC Registers failed \n");
+ err = -EIO;
+ goto out_mtd1;
+ }
+ bamboo_ndfc->b2cr = 0xC0007777;
+
+ /* Initialize structures */
+ memset((char *) bamboo_nand0_mtd, 0,
+ sizeof (struct mtd_info) + sizeof (struct nand_chip));
+
+ memset((char *) bamboo_nand1_mtd, 0,
+ sizeof (struct mtd_info) + sizeof (struct nand_chip));
+
+ /* Get pointer to private data */
+ this = (struct nand_chip *) (&bamboo_nand0_mtd[1]);
+ /* Link the private data with the MTD structure */
+ bamboo_nand0_mtd->priv = this;
+
+ /* Set address of NAND IO lines (Using Linear Data Access Region) */
+ this->IO_ADDR_R = (void __iomem *) ((ulong) bamboo_ndfc + 0x1000);
+ this->IO_ADDR_W = (void __iomem *) ((ulong) bamboo_ndfc + 0x1000);
+ /* Reference hardware control function */
+ this->hwcontrol = bamboo_nand0_hwcontrol;
+ /* Set command delay time */
+ this->chip_delay = 12;
+ this->eccmode = NAND_ECC_SOFT;
+ this->write_byte = bamboo_nand0_write_byte;
+ this->read_byte = bamboo_nand0_read_byte;
+ this->write_buf = bamboo_nand0_write_buf;
+ this->read_buf = bamboo_nand0_read_buf;
+ this->verify_buf = bamboo_nand0_verify_buf;
+ this->dev_ready = bamboo_dev_ready;
+
+ /* Scan to find existance of the device */
+ if (nand_scan(bamboo_nand0_mtd, 1)) {
+ err = -ENXIO;
+ goto out_ior;
+ }
+
+ /* Get pointer to private data */
+ this = (struct nand_chip *) (&bamboo_nand1_mtd[1]);
+ /* Link the private data with the MTD structure */
+ bamboo_nand1_mtd->priv = this;
+
+ /* Set address of NAND IO lines (Using Linear Data Access Region) */
+ this->IO_ADDR_R = (void __iomem *) ((ulong) bamboo_ndfc + 0x1000);
+ this->IO_ADDR_W = (void __iomem *) ((ulong) bamboo_ndfc + 0x1000);
+ /* Reference hardware control function */
+ this->hwcontrol = bamboo_nand1_hwcontrol;
+ /* Set command delay time */
+ this->chip_delay = 25;
+ this->eccmode = NAND_ECC_SOFT;
+ this->write_byte = bamboo_nand1_write_byte;
+ this->read_byte = bamboo_nand1_read_byte;
+ this->write_buf = bamboo_nand1_write_buf;
+ this->read_buf = bamboo_nand1_read_buf;
+ this->verify_buf = bamboo_nand1_verify_buf;
+ this->dev_ready = NULL;
+
+ /* Scan to find existance of the device */
+ if (nand_scan(bamboo_nand1_mtd, 1)) {
+ err = -ENXIO;
+ goto out_ior;
+ }
+
+
+ add_mtd_partitions(bamboo_nand0_mtd, nand0_partition_info,
+ NAND0_NUM_PARTITIONS);
+
+ add_mtd_partitions(bamboo_nand1_mtd, nand1_partition_info,
+ NAND1_NUM_PARTITIONS);
+ goto out;
+
+out_ior:
+ iounmap((void *)bamboo_ndfc);
+out_mtd1:
+ kfree(bamboo_nand1_mtd);
+out_mtd0:
+ kfree(bamboo_nand0_mtd);
+out:
+ return err;
+}
+
+static void __exit
+bamboo_cleanup(void)
+{
+ /* Unregister partitions */
+ del_mtd_partitions(bamboo_nand0_mtd);
+ del_mtd_partitions(bamboo_nand1_mtd);
+
+ /* Release resources, unregister device */
+ del_mtd_device(bamboo_nand0_mtd);
+ del_mtd_device(bamboo_nand1_mtd);
+
+ /* unmap physical address */
+ iounmap((void *) bamboo_ndfc);
+
+ /* Free the MTD device structure */
+ kfree(bamboo_nand0_mtd);
+ kfree(bamboo_nand1_mtd);
+}
+
+module_init(bamboo_init);
+module_exit(bamboo_cleanup);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Wade Farnsworth <wfarnsworth@mvista.com>");
+MODULE_DESCRIPTION
+ ("Board-specific glue layer for NAND flash on IBM 440EP eval board");
^ permalink raw reply
* Re: [PATCH 3/3] MTD support for the Bamboo board
From: Eugene Surovegin @ 2005-07-26 16:40 UTC (permalink / raw)
To: Wade Farnsworth; +Cc: linuxppc-embedded
In-Reply-To: <1122393974.10004.41.camel@rhino.az.mvista.com>
On Tue, Jul 26, 2005 at 09:06:14AM -0700, Wade Farnsworth wrote:
> This adds MTD support for the Bamboo board.
>
> Signed-off by: Wade Farnsworth <wfarnsworth@mvista.com>
> diff -uprN linux-2.6.12/drivers/mtd/maps/Kconfig.orig linux-2.6.12-440ep/drivers/mtd/maps/Kconfig.orig
> --- linux-2.6.12/drivers/mtd/maps/Kconfig.orig 1969-12-31 17:00:00.000000000 -0700
> +++ linux-2.6.12-440ep/drivers/mtd/maps/Kconfig.orig 2005-07-25 11:31:51.000000000 -0700
This hunk seems to be bogus.
> diff -uprN linux-2.6.12/drivers/mtd/maps/Makefile.orig linux-2.6.12-440ep/drivers/mtd/maps/Makefile.orig
> --- linux-2.6.12/drivers/mtd/maps/Makefile.orig 1969-12-31 17:00:00.000000000 -0700
> +++ linux-2.6.12-440ep/drivers/mtd/maps/Makefile.orig 2005-07-25 11:31:51.000000000 -0700
Ditto.
> diff -uprN linux-2.6.12/drivers/mtd/nand/Kconfig.orig linux-2.6.12-440ep/drivers/mtd/nand/Kconfig.orig
> --- linux-2.6.12/drivers/mtd/nand/Kconfig.orig 1969-12-31 17:00:00.000000000 -0700
> +++ linux-2.6.12-440ep/drivers/mtd/nand/Kconfig.orig 2005-07-25 11:31:51.000000000 -0700
Ditto
--
Eugene
^ permalink raw reply
* Re: [PATCH 3/3] MTD support for the Bamboo board
From: Wade Farnsworth @ 2005-07-26 16:06 UTC (permalink / raw)
To: linuxppc-embedded
In-Reply-To: <1122393818.22059.38.camel@rhino.az.mvista.com>
[-- Attachment #1: Type: text/plain, Size: 101 bytes --]
This adds MTD support for the Bamboo board.
Signed-off by: Wade Farnsworth <wfarnsworth@mvista.com>
[-- Attachment #2: 440ep-mtd.patch --]
[-- Type: text/x-patch, Size: 56380 bytes --]
diff -uprN linux-2.6.12/drivers/mtd/maps/Kconfig linux-2.6.12-440ep/drivers/mtd/maps/Kconfig
--- linux-2.6.12/drivers/mtd/maps/Kconfig 2005-07-25 12:57:05.000000000 -0700
+++ linux-2.6.12-440ep/drivers/mtd/maps/Kconfig 2005-07-25 11:32:32.000000000 -0700
@@ -331,6 +331,13 @@ config MTD_OCOTEA
This enables access routines for the flash chips on the IBM 440GX
Ocotea board. If you have one of these boards and would like to
use the flash chips on it, say 'Y'.
+config MTD_BAMBOO
+ tristate "Flash devices mapped on IBM 440EP Bamboo"
+ depends on MTD_CFI && PPC32 && 44x && BAMBOO
+ help
+ This enables access routined for the flash chips on the IBM 440EP
+ Bamboo board. If you have one of these boards and would like to
+ use the flash chips on it, say 'Y'.
config MTD_REDWOOD
tristate "CFI Flash devices mapped on IBM Redwood"
diff -uprN linux-2.6.12/drivers/mtd/maps/Kconfig.orig linux-2.6.12-440ep/drivers/mtd/maps/Kconfig.orig
--- linux-2.6.12/drivers/mtd/maps/Kconfig.orig 1969-12-31 17:00:00.000000000 -0700
+++ linux-2.6.12-440ep/drivers/mtd/maps/Kconfig.orig 2005-07-25 11:31:51.000000000 -0700
@@ -0,0 +1,628 @@
+# drivers/mtd/maps/Kconfig
+# $Id: Kconfig,v 1.55 2005/07/02 01:53:24 tpoynor Exp $
+
+menu "Mapping drivers for chip access"
+ depends on MTD!=n
+
+config MTD_COMPLEX_MAPPINGS
+ bool "Support non-linear mappings of flash chips"
+ depends on MTD
+ help
+ This causes the chip drivers to allow for complicated
+ paged mappings of flash chips.
+
+config MTD_PHYSMAP
+ tristate "CFI Flash device in physical memory map"
+ depends on MTD_CFI
+ help
+ This provides a 'mapping' driver which allows the CFI probe and
+ command set driver code to communicate with flash chips which
+ are mapped physically into the CPU's memory. You will need to
+ configure the physical address and size of the flash chips on
+ your particular board as well as the bus width, either statically
+ with config options or at run-time.
+
+config MTD_PHYSMAP_START
+ hex "Physical start address of flash mapping"
+ depends on MTD_PHYSMAP
+ default "0x8000000"
+ help
+ This is the physical memory location at which the flash chips
+ are mapped on your particular target board. Refer to the
+ memory map which should hopefully be in the documentation for
+ your board.
+ Ignore this option if you use run-time physmap configuration
+ (i.e., run-time calling physmap_configure()).
+
+config MTD_PHYSMAP_LEN
+ hex "Physical length of flash mapping"
+ depends on MTD_PHYSMAP
+ default "0x4000000"
+ help
+ This is the total length of the mapping of the flash chips on
+ your particular board. If there is space, or aliases, in the
+ physical memory map between the chips, this could be larger
+ than the total amount of flash present. Refer to the memory
+ map which should hopefully be in the documentation for your
+ board.
+ Ignore this option if you use run-time physmap configuration
+ (i.e., run-time calling physmap_configure()).
+
+config MTD_PHYSMAP_BANKWIDTH
+ int "Bank width in octets"
+ depends on MTD_PHYSMAP
+ default "2"
+ help
+ This is the total width of the data bus of the flash devices
+ in octets. For example, if you have a data bus width of 32
+ bits, you would set the bus width octect value to 4. This is
+ used internally by the CFI drivers.
+ Ignore this option if you use run-time physmap configuration
+ (i.e., run-time calling physmap_configure()).
+
+config MTD_SUN_UFLASH
+ tristate "Sun Microsystems userflash support"
+ depends on (SPARC32 || SPARC64) && MTD_CFI
+ help
+ This provides a 'mapping' driver which supports the way in
+ which user-programmable flash chips are connected on various
+ Sun Microsystems boardsets. This driver will require CFI support
+ in the kernel, so if you did not enable CFI previously, do that now.
+
+config MTD_PNC2000
+ tristate "CFI Flash device mapped on Photron PNC-2000"
+ depends on X86 && MTD_CFI && MTD_PARTITIONS
+ help
+ PNC-2000 is the name of Network Camera product from PHOTRON
+ Ltd. in Japan. It uses CFI-compliant flash.
+
+config MTD_SC520CDP
+ tristate "CFI Flash device mapped on AMD SC520 CDP"
+ depends on X86 && MTD_CFI
+ help
+ The SC520 CDP board has two banks of CFI-compliant chips and one
+ Dual-in-line JEDEC chip. This 'mapping' driver supports that
+ arrangement, implementing three MTD devices.
+
+config MTD_NETSC520
+ tristate "CFI Flash device mapped on AMD NetSc520"
+ depends on X86 && MTD_CFI && MTD_PARTITIONS
+ help
+ This enables access routines for the flash chips on the AMD NetSc520
+ demonstration board. If you have one of these boards and would like
+ to use the flash chips on it, say 'Y'.
+
+config MTD_TS5500
+ tristate "JEDEC Flash device mapped on Technologic Systems TS-5500"
+ depends on X86 && MTD_JEDECPROBE && MTD_PARTITIONS
+ help
+ This provides a driver for the on-board flash of the Technologic
+ System's TS-5500 board. The flash is split into 3 partitions
+ which are accessed as separate MTD devices.
+
+ mtd0 and mtd2 are the two BIOS drives. Unfortunately the BIOS
+ uses a proprietary flash translation layer from General Software,
+ which is not supported (the drives cannot be mounted). You can
+ create your own file system (jffs for example), but the BIOS
+ won't be able to boot from it.
+
+ mtd1 allows you to reprogram your BIOS. BE VERY CAREFUL.
+
+ Note that jumper 3 ("Write Enable Drive A") must be set
+ otherwise detection won't succeeed.
+
+config MTD_SBC_GXX
+ tristate "CFI Flash device mapped on Arcom SBC-GXx boards"
+ depends on X86 && MTD_CFI_INTELEXT && MTD_PARTITIONS && MTD_COMPLEX_MAPPINGS
+ help
+ This provides a driver for the on-board flash of Arcom Control
+ Systems' SBC-GXn family of boards, formerly known as SBC-MediaGX.
+ By default the flash is split into 3 partitions which are accessed
+ as separate MTD devices. This board utilizes Intel StrataFlash.
+ More info at
+ <http://www.arcomcontrols.com/products/icp/pc104/processors/SBC_GX1.htm>.
+
+config MTD_LUBBOCK
+ tristate "CFI Flash device mapped on Intel Lubbock XScale eval board"
+ depends on ARCH_LUBBOCK && MTD_CFI_INTELEXT && MTD_PARTITIONS
+ help
+ This provides a driver for the on-board flash of the Intel
+ 'Lubbock' XScale evaluation board.
+
+config MTD_MAINSTONE
+ tristate "CFI Flash device mapped on Intel Mainstone XScale eval board"
+ depends on MACH_MAINSTONE && MTD_CFI_INTELEXT
+ select MTD_PARTITIONS
+ help
+ This provides a driver for the on-board flash of the Intel
+ 'Mainstone PXA27x evaluation board.
+
+config MTD_OCTAGON
+ tristate "JEDEC Flash device mapped on Octagon 5066 SBC"
+ depends on X86 && MTD_JEDEC && MTD_COMPLEX_MAPPINGS
+ help
+ This provides a 'mapping' driver which supports the way in which
+ the flash chips are connected in the Octagon-5066 Single Board
+ Computer. More information on the board is available at
+ <http://www.octagonsystems.com/CPUpages/5066.html>.
+
+config MTD_VMAX
+ tristate "JEDEC Flash device mapped on Tempustech VMAX SBC301"
+ depends on X86 && MTD_JEDEC && MTD_COMPLEX_MAPPINGS
+ help
+ This provides a 'mapping' driver which supports the way in which
+ the flash chips are connected in the Tempustech VMAX SBC301 Single
+ Board Computer. More information on the board is available at
+ <http://www.tempustech.com/>.
+
+config MTD_SCx200_DOCFLASH
+ tristate "Flash device mapped with DOCCS on NatSemi SCx200"
+ depends on SCx200 && MTD_CFI && MTD_PARTITIONS
+ help
+ Enable support for a flash chip mapped using the DOCCS signal on a
+ National Semiconductor SCx200 processor.
+
+ If you don't know what to do here, say N.
+
+ If compiled as a module, it will be called scx200_docflash.
+
+config MTD_AMD76XROM
+ tristate "BIOS flash chip on AMD76x southbridge"
+ depends on X86 && MTD_JEDECPROBE
+ help
+ Support for treating the BIOS flash chip on AMD76x motherboards
+ as an MTD device - with this you can reprogram your BIOS.
+
+ BE VERY CAREFUL.
+
+config MTD_ICHXROM
+ tristate "BIOS flash chip on Intel Controller Hub 2/3/4/5"
+ depends on X86 && MTD_JEDECPROBE
+ help
+ Support for treating the BIOS flash chip on ICHX motherboards
+ as an MTD device - with this you can reprogram your BIOS.
+
+ BE VERY CAREFUL.
+
+config MTD_SCB2_FLASH
+ tristate "BIOS flash chip on Intel SCB2 boards"
+ depends on X86 && MTD_JEDECPROBE
+ help
+ Support for treating the BIOS flash chip on Intel SCB2 boards
+ as an MTD device - with this you can reprogram your BIOS.
+
+ BE VERY CAREFUL.
+
+config MTD_TSUNAMI
+ tristate "Flash chips on Tsunami TIG bus"
+ depends on ALPHA_TSUNAMI && MTD_COMPLEX_MAPPINGS
+ help
+ Support for the flash chip on Tsunami TIG bus.
+
+config MTD_LASAT
+ tristate "Flash chips on LASAT board"
+ depends on LASAT
+ help
+ Support for the flash chips on the Lasat 100 and 200 boards.
+
+config MTD_NETtel
+ tristate "CFI flash device on SnapGear/SecureEdge"
+ depends on X86 && MTD_PARTITIONS && MTD_JEDECPROBE
+ help
+ Support for flash chips on NETtel/SecureEdge/SnapGear boards.
+
+config MTD_ALCHEMY
+ tristate ' AMD Alchemy Pb1xxx/Db1xxx/RDK MTD support'
+ depends on MIPS && SOC_AU1X00
+ help
+ Flash memory access on AMD Alchemy Pb/Db/RDK Reference Boards
+
+config MTD_DILNETPC
+ tristate "CFI Flash device mapped on DIL/Net PC"
+ depends on X86 && MTD_CONCAT && MTD_PARTITIONS && MTD_CFI_INTELEXT
+ help
+ MTD map driver for SSV DIL/Net PC Boards "DNP" and "ADNP".
+ For details, see <http://www.ssv-embedded.de/ssv/pc104/p169.htm>
+ and <http://www.ssv-embedded.de/ssv/pc104/p170.htm>
+
+config MTD_DILNETPC_BOOTSIZE
+ hex "Size of DIL/Net PC flash boot partition"
+ depends on MTD_DILNETPC
+ default "0x80000"
+ help
+ The amount of space taken up by the kernel or Etherboot
+ on the DIL/Net PC flash chips.
+
+config MTD_L440GX
+ tristate "BIOS flash chip on Intel L440GX boards"
+ depends on X86 && MTD_JEDECPROBE
+ help
+ Support for treating the BIOS flash chip on Intel L440GX motherboards
+ as an MTD device - with this you can reprogram your BIOS.
+
+ BE VERY CAREFUL.
+
+config MTD_SBC8240
+ tristate "Flash device on SBC8240"
+ depends on PPC32 && MTD_JEDECPROBE && 6xx && 8260
+ help
+ Flash access on the SBC8240 board from Wind River. See
+ <http://www.windriver.com/products/sbc8240/>
+
+config MTD_TQM8XXL
+ tristate "CFI Flash device mapped on TQM8XXL"
+ depends on MTD_CFI && PPC32 && 8xx && TQM8xxL
+ help
+ The TQM8xxL PowerPC board has up to two banks of CFI-compliant
+ chips, currently uses AMD one. This 'mapping' driver supports
+ that arrangement, allowing the CFI probe and command set driver
+ code to communicate with the chips on the TQM8xxL board. More at
+ <http://www.denx.de/embedded-ppc-en.html>.
+
+config MTD_RPXLITE
+ tristate "CFI Flash device mapped on RPX Lite or CLLF"
+ depends on MTD_CFI && PPC32 && 8xx && (RPXCLASSIC || RPXLITE)
+ help
+ The RPXLite PowerPC board has CFI-compliant chips mapped in
+ a strange sparse mapping. This 'mapping' driver supports that
+ arrangement, allowing the CFI probe and command set driver code
+ to communicate with the chips on the RPXLite board. More at
+ <http://www.embeddedplanet.com/>.
+
+config MTD_MBX860
+ tristate "System flash on MBX860 board"
+ depends on MTD_CFI && PPC32 && 8xx && MBX
+ help
+ This enables access routines for the flash chips on the Motorola
+ MBX860 board. If you have one of these boards and would like
+ to use the flash chips on it, say 'Y'.
+
+config MTD_DBOX2
+ tristate "CFI Flash device mapped on D-Box2"
+ depends on PPC32 && 8xx && DBOX2 && MTD_CFI_INTELSTD && MTD_CFI_INTELEXT && MTD_CFI_AMDSTD
+ help
+ This enables access routines for the flash chips on the Nokia/Sagem
+ D-Box 2 board. If you have one of these boards and would like to use
+ the flash chips on it, say 'Y'.
+
+config MTD_CFI_FLAGADM
+ tristate "CFI Flash device mapping on FlagaDM"
+ depends on PPC32 && 8xx && MTD_CFI
+ help
+ Mapping for the Flaga digital module. If you don't have one, ignore
+ this setting.
+
+config MTD_BEECH
+ tristate "CFI Flash device mapped on IBM 405LP Beech"
+ depends on MTD_CFI && PPC32 && 40x && BEECH
+ help
+ This enables access routines for the flash chips on the IBM
+ 405LP Beech board. If you have one of these boards and would like
+ to use the flash chips on it, say 'Y'.
+
+config MTD_ARCTIC
+ tristate "CFI Flash device mapped on IBM 405LP Arctic"
+ depends on MTD_CFI && PPC32 && 40x && ARCTIC2
+ help
+ This enables access routines for the flash chips on the IBM 405LP
+ Arctic board. If you have one of these boards and would like to
+ use the flash chips on it, say 'Y'.
+
+config MTD_WALNUT
+ tristate "Flash device mapped on IBM 405GP Walnut"
+ depends on MTD_JEDECPROBE && PPC32 && 40x && WALNUT
+ help
+ This enables access routines for the flash chips on the IBM 405GP
+ Walnut board. If you have one of these boards and would like to
+ use the flash chips on it, say 'Y'.
+
+config MTD_EBONY
+ tristate "Flash devices mapped on IBM 440GP Ebony"
+ depends on MTD_JEDECPROBE && PPC32 && 44x && EBONY
+ help
+ This enables access routines for the flash chips on the IBM 440GP
+ Ebony board. If you have one of these boards and would like to
+ use the flash chips on it, say 'Y'.
+
+config MTD_OCOTEA
+ tristate "Flash devices mapped on IBM 440GX Ocotea"
+ depends on MTD_CFI && PPC32 && 44x && OCOTEA
+ help
+ This enables access routines for the flash chips on the IBM 440GX
+ Ocotea board. If you have one of these boards and would like to
+ use the flash chips on it, say 'Y'.
+
+config MTD_REDWOOD
+ tristate "CFI Flash devices mapped on IBM Redwood"
+ depends on MTD_CFI && PPC32 && 4xx && 40x && ( REDWOOD_4 || REDWOOD_5 || REDWOOD_6 )
+ help
+ This enables access routines for the flash chips on the IBM
+ Redwood board. If you have one of these boards and would like to
+ use the flash chips on it, say 'Y'.
+
+config MTD_CSTM_MIPS_IXX
+ tristate "Flash chip mapping on ITE QED-4N-S01B, Globespan IVR or custom board"
+ depends on MIPS && MTD_CFI && MTD_JEDECPROBE && MTD_PARTITIONS
+ help
+ This provides a mapping driver for the Integrated Technology
+ Express, Inc (ITE) QED-4N-S01B eval board and the Globespan IVR
+ Reference Board. It provides the necessary addressing, length,
+ buswidth, vpp code and addition setup of the flash device for
+ these boards. In addition, this mapping driver can be used for
+ other boards via setting of the CONFIG_MTD_CSTM_MIPS_IXX_START/
+ LEN/BUSWIDTH parameters. This mapping will provide one mtd device
+ using one partition. The start address can be offset from the
+ beginning of flash and the len can be less than the total flash
+ device size to allow a window into the flash. Both CFI and JEDEC
+ probes are called.
+
+config MTD_CSTM_MIPS_IXX_START
+ hex "Physical start address of flash mapping"
+ depends on MTD_CSTM_MIPS_IXX
+ default "0x8000000"
+ help
+ This is the physical memory location that the MTD driver will
+ use for the flash chips on your particular target board.
+ Refer to the memory map which should hopefully be in the
+ documentation for your board.
+
+config MTD_CSTM_MIPS_IXX_LEN
+ hex "Physical length of flash mapping"
+ depends on MTD_CSTM_MIPS_IXX
+ default "0x4000000"
+ help
+ This is the total length that the MTD driver will use for the
+ flash chips on your particular board. Refer to the memory
+ map which should hopefully be in the documentation for your
+ board.
+
+config MTD_CSTM_MIPS_IXX_BUSWIDTH
+ int "Bus width in octets"
+ depends on MTD_CSTM_MIPS_IXX
+ default "2"
+ help
+ This is the total bus width of the mapping of the flash chips
+ on your particular board.
+
+config MTD_OCELOT
+ tristate "Momenco Ocelot boot flash device"
+ depends on MIPS && MOMENCO_OCELOT
+ help
+ This enables access routines for the boot flash device and for the
+ NVRAM on the Momenco Ocelot board. If you have one of these boards
+ and would like access to either of these, say 'Y'.
+
+config MTD_SOLUTIONENGINE
+ tristate "CFI Flash device mapped on Hitachi SolutionEngine"
+ depends on SUPERH && MTD_CFI && MTD_REDBOOT_PARTS
+ help
+ This enables access to the flash chips on the Hitachi SolutionEngine and
+ similar boards. Say 'Y' if you are building a kernel for such a board.
+
+config MTD_ARM_INTEGRATOR
+ tristate "CFI Flash device mapped on ARM Integrator/P720T"
+ depends on ARM && MTD_CFI
+
+config MTD_CDB89712
+ tristate "Cirrus CDB89712 evaluation board mappings"
+ depends on ARM && MTD_CFI && ARCH_CDB89712
+ help
+ This enables access to the flash or ROM chips on the CDB89712 board.
+ If you have such a board, say 'Y'.
+
+config MTD_SA1100
+ tristate "CFI Flash device mapped on StrongARM SA11x0"
+ depends on ARM && MTD_CFI && ARCH_SA1100 && MTD_PARTITIONS
+ help
+ This enables access to the flash chips on most platforms based on
+ the SA1100 and SA1110, including the Assabet and the Compaq iPAQ.
+ If you have such a board, say 'Y'.
+
+config MTD_IPAQ
+ tristate "CFI Flash device mapped on Compaq/HP iPAQ"
+ depends on ARM && IPAQ_HANDHELD && MTD_CFI
+ help
+ This provides a driver for the on-board flash of the iPAQ.
+
+config MTD_DC21285
+ tristate "CFI Flash device mapped on DC21285 Footbridge"
+ depends on ARM && MTD_CFI && ARCH_FOOTBRIDGE && MTD_COMPLEX_MAPPINGS
+ help
+ This provides a driver for the flash accessed using Intel's
+ 21285 bridge used with Intel's StrongARM processors. More info at
+ <http://www.intel.com/design/bridge/docs/21285_documentation.htm>.
+
+config MTD_IQ80310
+ tristate "CFI Flash device mapped on the XScale IQ80310 board"
+ depends on ARM && MTD_CFI && ARCH_IQ80310
+ help
+ This enables access routines for the flash chips on the Intel XScale
+ IQ80310 evaluation board. If you have one of these boards and would
+ like to use the flash chips on it, say 'Y'.
+
+config MTD_IXP4XX
+ tristate "CFI Flash device mapped on Intel IXP4xx based systems"
+ depends on ARM && MTD_CFI && MTD_COMPLEX_MAPPINGS && ARCH_IXP4XX
+ help
+ This enables MTD access to flash devices on platforms based
+ on Intel's IXP4xx family of network processors such as the
+ IXDP425 and Coyote. If you have an IXP4xx based board and
+ would like to use the flash chips on it, say 'Y'.
+
+config MTD_IXP2000
+ tristate "CFI Flash device mapped on Intel IXP2000 based systems"
+ depends on ARM && MTD_CFI && MTD_COMPLEX_MAPPINGS && ARCH_IXP2000
+ help
+ This enables MTD access to flash devices on platforms based
+ on Intel's IXP2000 family of network processors such as the
+ IXDP425 and Coyote. If you have an IXP2000 based board and
+ would like to use the flash chips on it, say 'Y'.
+
+config MTD_EPXA10DB
+ tristate "CFI Flash device mapped on Epxa10db"
+ depends on ARM && MTD_CFI && MTD_PARTITIONS && ARCH_CAMELOT
+ help
+ This enables support for the flash devices on the Altera
+ Excalibur XA10 Development Board. If you are building a kernel
+ for on of these boards then you should say 'Y' otherwise say 'N'.
+
+config MTD_FORTUNET
+ tristate "CFI Flash device mapped on the FortuNet board"
+ depends on ARM && MTD_CFI && MTD_PARTITIONS && SA1100_FORTUNET
+ help
+ This enables access to the Flash on the FortuNet board. If you
+ have such a board, say 'Y'.
+
+config MTD_AUTCPU12
+ tristate "NV-RAM mapping AUTCPU12 board"
+ depends on ARM && ARCH_AUTCPU12
+ help
+ This enables access to the NV-RAM on autronix autcpu12 board.
+ If you have such a board, say 'Y'.
+
+config MTD_EDB7312
+ tristate "CFI Flash device mapped on EDB7312"
+ depends on ARM && MTD_CFI
+ help
+ This enables access to the CFI Flash on the Cogent EDB7312 board.
+ If you have such a board, say 'Y' here.
+
+config MTD_IMPA7
+ tristate "JEDEC Flash device mapped on impA7"
+ depends on ARM && MTD_JEDECPROBE
+ help
+ This enables access to the NOR Flash on the impA7 board of
+ implementa GmbH. If you have such a board, say 'Y' here.
+
+config MTD_CEIVA
+ tristate "JEDEC Flash device mapped on Ceiva/Polaroid PhotoMax Digital Picture Frame"
+ depends on ARM && MTD_JEDECPROBE && ARCH_CEIVA
+ help
+ This enables access to the flash chips on the Ceiva/Polaroid
+ PhotoMax Digital Picture Frame.
+ If you have such a device, say 'Y'.
+
+config MTD_NOR_TOTO
+ tristate "NOR Flash device on TOTO board"
+ depends on ARM && ARCH_OMAP && OMAP_TOTO
+ help
+ This enables access to the NOR flash on the Texas Instruments
+ TOTO board.
+
+config MTD_H720X
+ tristate "Hynix evaluation board mappings"
+ depends on ARM && MTD_CFI && ( ARCH_H7201 || ARCH_H7202 )
+ help
+ This enables access to the flash chips on the Hynix evaluation boards.
+ If you have such a board, say 'Y'.
+
+config MTD_MPC1211
+ tristate "CFI Flash device mapped on Interface MPC-1211"
+ depends on SUPERH && SH_MPC1211 && MTD_CFI
+ help
+ This enables access to the flash chips on the Interface MPC-1211(CTP/PCI/MPC-SH02).
+ If you have such a board, say 'Y'.
+
+config MTD_OMAP_NOR
+ tristate "TI OMAP board mappings"
+ depends on MTD_CFI && ARCH_OMAP
+ help
+ This enables access to the NOR flash chips on TI OMAP-based
+ boards defining flash platform devices and flash platform data.
+ These boards include the Innovator, H2, H3, OSK, Perseus2, and
+ more. If you have such a board, say 'Y'.
+
+# This needs CFI or JEDEC, depending on the cards found.
+config MTD_PCI
+ tristate "PCI MTD driver"
+ depends on MTD && PCI && MTD_COMPLEX_MAPPINGS
+ help
+ Mapping for accessing flash devices on add-in cards like the Intel XScale
+ IQ80310 card, and the Intel EBSA285 card in blank ROM programming mode
+ (please see the manual for the link settings).
+
+ If you are not sure, say N.
+
+config MTD_PCMCIA
+ tristate "PCMCIA MTD driver"
+ depends on MTD && PCMCIA && MTD_COMPLEX_MAPPINGS && BROKEN
+ help
+ Map driver for accessing PCMCIA linear flash memory cards. These
+ cards are usually around 4-16MiB in size. This does not include
+ Compact Flash cards which are treated as IDE devices.
+
+config MTD_PCMCIA_ANONYMOUS
+ bool "Use PCMCIA MTD drivers for anonymous PCMCIA cards"
+ depends on MTD_PCMCIA
+ default N
+ help
+ If this option is enabled, PCMCIA cards which do not report
+ anything about themselves are assumed to be MTD cards.
+
+ If unsure, say N.
+
+config MTD_UCLINUX
+ tristate "Generic uClinux RAM/ROM filesystem support"
+ depends on MTD_PARTITIONS && !MMU
+ help
+ Map driver to support image based filesystems for uClinux.
+
+config MTD_WRSBC8260
+ tristate "Map driver for WindRiver PowerQUICC II MPC82xx board"
+ depends on (SBC82xx || SBC8560)
+ select MTD_PARTITIONS
+ select MTD_MAP_BANK_WIDTH_4
+ select MTD_MAP_BANK_WIDTH_1
+ select MTD_CFI_I1
+ select MTD_CFI_I4
+ help
+ Map driver for WindRiver PowerQUICC II MPC82xx board. Drives
+ all three flash regions on CS0, CS1 and CS6 if they are configured
+ correctly by the boot loader.
+
+config MTD_DMV182
+ tristate "Map driver for Dy-4 SVME/DMV-182 board."
+ depends on DMV182
+ select MTD_PARTITIONS
+ select MTD_MAP_BANK_WIDTH_32
+ select MTD_CFI_I8
+ select MTD_CFI_AMDSTD
+ help
+ Map driver for Dy-4 SVME/DMV-182 board.
+
+config MTD_BAST
+ tristate "Map driver for Simtec BAST (EB2410ITX) or Thorcom VR1000"
+ depends on ARCH_BAST || MACH_VR1000
+ select MTD_PARTITIONS
+ select MTD_MAP_BANK_WIDTH_16
+ select MTD_JEDECPROBE
+ help
+ Map driver for NOR flash on the Simtec BAST (EB2410ITX), or the
+ Thorcom VR1000
+
+ Note, this driver *cannot* over-ride the WP link on the
+ board, or currently detect the state of the link.
+
+config MTD_BAST_MAXSIZE
+ int "Maximum size for BAST flash area (MiB)"
+ depends on MTD_BAST
+ default "4"
+
+config MTD_SHARP_SL
+ bool "ROM maped on Sharp SL Series"
+ depends on MTD && ARCH_PXA
+ help
+ This enables access to the flash chip on the Sharp SL Series of PDAs.
+
+config MTD_PLATRAM
+ tristate "Map driver for platform device RAM (mtd-ram)"
+ depends on MTD
+ select MTD_RAM
+ help
+ Map driver for RAM areas described via the platform device
+ system.
+
+ This selection automatically selects the map_ram driver.
+
+endmenu
+
diff -uprN linux-2.6.12/drivers/mtd/maps/Makefile linux-2.6.12-440ep/drivers/mtd/maps/Makefile
--- linux-2.6.12/drivers/mtd/maps/Makefile 2005-07-25 12:57:05.000000000 -0700
+++ linux-2.6.12-440ep/drivers/mtd/maps/Makefile 2005-07-25 11:32:32.000000000 -0700
@@ -56,6 +56,7 @@ obj-$(CONFIG_MTD_NETtel) += nettel.o
obj-$(CONFIG_MTD_SCB2_FLASH) += scb2_flash.o
obj-$(CONFIG_MTD_EBONY) += ebony.o
obj-$(CONFIG_MTD_OCOTEA) += ocotea.o
+obj-$(CONFIG_MTD_BAMBOO) += bamboo.o
obj-$(CONFIG_MTD_BEECH) += beech-mtd.o
obj-$(CONFIG_MTD_ARCTIC) += arctic-mtd.o
obj-$(CONFIG_MTD_WALNUT) += walnut.o
diff -uprN linux-2.6.12/drivers/mtd/maps/Makefile.orig linux-2.6.12-440ep/drivers/mtd/maps/Makefile.orig
--- linux-2.6.12/drivers/mtd/maps/Makefile.orig 1969-12-31 17:00:00.000000000 -0700
+++ linux-2.6.12-440ep/drivers/mtd/maps/Makefile.orig 2005-07-25 11:31:51.000000000 -0700
@@ -0,0 +1,72 @@
+#
+# linux/drivers/maps/Makefile
+#
+# $Id: Makefile.common,v 1.30 2005/07/02 01:53:24 tpoynor Exp $
+
+ifeq ($(CONFIG_MTD_COMPLEX_MAPPINGS),y)
+obj-$(CONFIG_MTD) += map_funcs.o
+endif
+
+# Chip mappings
+obj-$(CONFIG_MTD_CDB89712) += cdb89712.o
+obj-$(CONFIG_MTD_ARM_INTEGRATOR)+= integrator-flash.o
+obj-$(CONFIG_MTD_BAST) += bast-flash.o
+obj-$(CONFIG_MTD_CFI_FLAGADM) += cfi_flagadm.o
+obj-$(CONFIG_MTD_CSTM_MIPS_IXX) += cstm_mips_ixx.o
+obj-$(CONFIG_MTD_DC21285) += dc21285.o
+obj-$(CONFIG_MTD_DILNETPC) += dilnetpc.o
+obj-$(CONFIG_MTD_EPXA10DB) += epxa10db-flash.o
+obj-$(CONFIG_MTD_IQ80310) += iq80310.o
+obj-$(CONFIG_MTD_L440GX) += l440gx.o
+obj-$(CONFIG_MTD_AMD76XROM) += amd76xrom.o
+obj-$(CONFIG_MTD_ICHXROM) += ichxrom.o
+obj-$(CONFIG_MTD_TSUNAMI) += tsunami_flash.o
+obj-$(CONFIG_MTD_LUBBOCK) += lubbock-flash.o
+obj-$(CONFIG_MTD_MAINSTONE) += mainstone-flash.o
+obj-$(CONFIG_MTD_MBX860) += mbx860.o
+obj-$(CONFIG_MTD_CEIVA) += ceiva.o
+obj-$(CONFIG_MTD_OCTAGON) += octagon-5066.o
+obj-$(CONFIG_MTD_PHYSMAP) += physmap.o
+obj-$(CONFIG_MTD_PNC2000) += pnc2000.o
+obj-$(CONFIG_MTD_PCMCIA) += pcmciamtd.o
+obj-$(CONFIG_MTD_RPXLITE) += rpxlite.o
+obj-$(CONFIG_MTD_TQM8XXL) += tqm8xxl.o
+obj-$(CONFIG_MTD_SA1100) += sa1100-flash.o
+obj-$(CONFIG_MTD_IPAQ) += ipaq-flash.o
+obj-$(CONFIG_MTD_SBC_GXX) += sbc_gxx.o
+obj-$(CONFIG_MTD_SC520CDP) += sc520cdp.o
+obj-$(CONFIG_MTD_NETSC520) += netsc520.o
+obj-$(CONFIG_MTD_TS5500) += ts5500_flash.o
+obj-$(CONFIG_MTD_SUN_UFLASH) += sun_uflash.o
+obj-$(CONFIG_MTD_VMAX) += vmax301.o
+obj-$(CONFIG_MTD_SCx200_DOCFLASH)+= scx200_docflash.o
+obj-$(CONFIG_MTD_DBOX2) += dbox2-flash.o
+obj-$(CONFIG_MTD_OCELOT) += ocelot.o
+obj-$(CONFIG_MTD_SOLUTIONENGINE)+= solutionengine.o
+obj-$(CONFIG_MTD_PCI) += pci.o
+obj-$(CONFIG_MTD_ALCHEMY) += alchemy-flash.o
+obj-$(CONFIG_MTD_LASAT) += lasat.o
+obj-$(CONFIG_MTD_AUTCPU12) += autcpu12-nvram.o
+obj-$(CONFIG_MTD_EDB7312) += edb7312.o
+obj-$(CONFIG_MTD_IMPA7) += impa7.o
+obj-$(CONFIG_MTD_FORTUNET) += fortunet.o
+obj-$(CONFIG_MTD_REDWOOD) += redwood.o
+obj-$(CONFIG_MTD_UCLINUX) += uclinux.o
+obj-$(CONFIG_MTD_NETtel) += nettel.o
+obj-$(CONFIG_MTD_SCB2_FLASH) += scb2_flash.o
+obj-$(CONFIG_MTD_EBONY) += ebony.o
+obj-$(CONFIG_MTD_OCOTEA) += ocotea.o
+obj-$(CONFIG_MTD_BEECH) += beech-mtd.o
+obj-$(CONFIG_MTD_ARCTIC) += arctic-mtd.o
+obj-$(CONFIG_MTD_WALNUT) += walnut.o
+obj-$(CONFIG_MTD_H720X) += h720x-flash.o
+obj-$(CONFIG_MTD_SBC8240) += sbc8240.o
+obj-$(CONFIG_MTD_NOR_TOTO) += omap-toto-flash.o
+obj-$(CONFIG_MTD_MPC1211) += mpc1211.o
+obj-$(CONFIG_MTD_IXP4XX) += ixp4xx.o
+obj-$(CONFIG_MTD_IXP2000) += ixp2000.o
+obj-$(CONFIG_MTD_WRSBC8260) += wr_sbc82xx_flash.o
+obj-$(CONFIG_MTD_DMV182) += dmv182.o
+obj-$(CONFIG_MTD_SHARP_SL) += sharpsl-flash.o
+obj-$(CONFIG_MTD_PLATRAM) += plat-ram.o
+obj-$(CONFIG_MTD_OMAP_NOR) += omap_nor.o
diff -uprN linux-2.6.12/drivers/mtd/maps/bamboo.c linux-2.6.12-440ep/drivers/mtd/maps/bamboo.c
--- linux-2.6.12/drivers/mtd/maps/bamboo.c 1969-12-31 17:00:00.000000000 -0700
+++ linux-2.6.12-440ep/drivers/mtd/maps/bamboo.c 2005-07-25 11:32:32.000000000 -0700
@@ -0,0 +1,245 @@
+/*
+ * Mapping for Bamboo user flash
+ *
+ * Wade Farnsworth <wfarnsworth@mvista.com>
+ *
+ * Copyright 2005 MontaVista Software Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/map.h>
+#include <linux/mtd/partitions.h>
+#include <linux/config.h>
+#include <asm/io.h>
+#include <asm/ibm44x.h>
+#include <platforms/4xx/bamboo.h>
+
+static struct mtd_info *small_flash, *large_flash, *sram;
+
+static struct map_info bamboo_small_map = {
+ .name = "Bamboo small flash",
+ .size = BAMBOO_SMALL_FLASH_SIZE,
+ .bankwidth = 1,
+};
+
+static struct map_info bamboo_large_map = {
+ .name = "Bamboo large flash",
+ .size = BAMBOO_LARGE_FLASH_SIZE,
+ .bankwidth = 2,
+};
+
+static struct map_info bamboo_sram_map = {
+ .name = "Bamboo SRAM",
+ .size = BAMBOO_SRAM_SIZE,
+ .bankwidth = 2,
+};
+
+static struct mtd_partition bamboo_small_partitions[] = {
+ {
+ .name = "pibs",
+ .offset = 0x0,
+ .size = 0x100000,
+ .mask_flags = MTD_WRITEABLE,
+ }
+};
+
+static struct mtd_partition bamboo_large_partitions[] = {
+ {
+ .name = "filesystem",
+ .offset = 0x0,
+ .size = 0x400000,
+ }
+};
+
+static struct mtd_partition bamboo_sram_partitions[] = {
+ {
+ .name = "sram",
+ .offset = 0x0,
+ .size = 0x100000,
+ }
+};
+
+int __init
+init_bamboo(void)
+{
+ u8 setting_reg;
+ u8 *setting_adr;
+ unsigned long small_flash_base, large_flash_base, sram_base;
+ unsigned long *gpio_base;
+
+ setting_adr = ioremap64(BAMBOO_FPGA_SETTING_REG_ADDR, 8);
+ if (!setting_adr)
+ return -ENOMEM;
+ setting_reg = readb(setting_adr);
+ iounmap(setting_adr);
+
+ /*
+ * Some versions of PIBS don't set up the GPIO controller
+ * for the devices on chip select 4 (large flash and sram).
+ */
+ gpio_base = ioremap64(0x0EF600B00ULL, 0x80);
+ if (!gpio_base) {
+ printk("Failed to ioremap GPIO\n");
+ return -ENOMEM;
+ }
+ * (gpio_base + 0x02) |= 0x00001000;
+ * (gpio_base + 0x04) |= 0x00001000;
+ iounmap((void *) gpio_base);
+
+ /*
+ * Use the values in the FPGA Setting Register to determine where
+ * each flash bank is located.
+ */
+ if (!BAMBOO_BOOT_NAND_FLASH(setting_reg)) {
+ if (BAMBOO_BOOT_SMALL_FLASH(setting_reg)) {
+ small_flash_base = BAMBOO_SMALL_FLASH_HIGH;
+ } else {
+ small_flash_base = BAMBOO_SMALL_FLASH_LOW;
+ }
+
+ bamboo_small_map.phys = small_flash_base;
+ bamboo_small_map.virt =
+ (ulong *) ioremap64(small_flash_base,
+ bamboo_small_map.size);
+ if (!bamboo_small_map.virt) {
+ printk("Failed to ioremap flash\n");
+ return -EIO;
+ }
+
+ simple_map_init(&bamboo_small_map);
+
+ small_flash = do_map_probe("map_rom", &bamboo_small_map);
+ if (small_flash) {
+ small_flash->owner = THIS_MODULE;
+ add_mtd_partitions(small_flash, bamboo_small_partitions,
+ ARRAY_SIZE(bamboo_small_partitions));
+ } else {
+ printk(KERN_INFO
+ "small flash disabled: Probe failed due to probable hardware issue\n");
+ iounmap((void *) bamboo_small_map.virt);
+ bamboo_small_map.virt = 0;
+ }
+ } else
+ bamboo_small_map.virt = 0;
+
+ /*
+ * Wiring to the large flash on the Rev 0 Bamboo is incorrect, so
+ * this should fail.
+ *
+ * This has been fixed on the Rev 1.
+ */
+ if (BAMBOO_BOOT_NAND_FLASH(setting_reg) ||
+ BAMBOO_BOOT_SMALL_FLASH(setting_reg))
+ large_flash_base = BAMBOO_LARGE_FLASH_LOW;
+ else if (BAMBOO_LARGE_FLASH_EN(setting_reg))
+ large_flash_base = BAMBOO_LARGE_FLASH_HIGH1;
+ else
+ large_flash_base = BAMBOO_LARGE_FLASH_HIGH2;
+ bamboo_large_map.phys = large_flash_base;
+ bamboo_large_map.virt = (ulong *) ioremap64(large_flash_base,
+ bamboo_large_map.size);
+ if (!bamboo_large_map.virt) {
+ printk("Failed to ioremap flash\n");
+ return -EIO;
+ }
+
+ simple_map_init(&bamboo_large_map);
+ large_flash = do_map_probe("cfi_probe", &bamboo_large_map);
+ if (large_flash) {
+ large_flash->owner = THIS_MODULE;
+ add_mtd_partitions(large_flash, bamboo_large_partitions,
+ ARRAY_SIZE(bamboo_large_partitions));
+ } else {
+ printk(KERN_INFO
+ "large flash disabled: Probe failed due to probable hardware issue\n");
+ iounmap((void *) bamboo_large_map.virt);
+ bamboo_large_map.virt = 0;
+ }
+
+ if (BAMBOO_BOOT_NAND_FLASH(setting_reg) ||
+ BAMBOO_BOOT_SMALL_FLASH(setting_reg))
+ sram_base = BAMBOO_SRAM_LOW;
+ else if (BAMBOO_LARGE_FLASH_EN(setting_reg))
+ sram_base = BAMBOO_SRAM_HIGH2;
+ else
+ sram_base = BAMBOO_SRAM_HIGH1;
+
+ bamboo_sram_map.phys = sram_base;
+ bamboo_sram_map.virt = (ulong *) ioremap64(sram_base,
+ bamboo_sram_map.size);
+ if (!bamboo_sram_map.virt) {
+ printk("Failed to ioremap flash \n");
+ return -EIO;
+ }
+
+ simple_map_init(&bamboo_sram_map);
+
+ sram = do_map_probe("map_ram", &bamboo_sram_map);
+ if (sram) {
+ sram->owner = THIS_MODULE;
+ sram->erasesize = 0x10;
+ add_mtd_partitions(sram, bamboo_sram_partitions,
+ ARRAY_SIZE(bamboo_sram_partitions));
+ } else {
+ printk(KERN_INFO
+ "sram disabled: Probe failed due to probable hardware issue\n");
+ iounmap((void *) bamboo_sram_map.virt);
+ bamboo_sram_map.virt = 0;
+ }
+
+ if (!(small_flash || large_flash || sram))
+ return -ENXIO;
+
+ return 0;
+}
+
+static void __exit
+cleanup_bamboo(void)
+{
+ if (small_flash) {
+ del_mtd_partitions(small_flash);
+ map_destroy(small_flash);
+ }
+
+ if (large_flash) {
+ del_mtd_partitions(large_flash);
+ map_destroy(large_flash);
+ }
+
+ if (sram) {
+ del_mtd_partitions(sram);
+ map_destroy(sram);
+ }
+
+ if (bamboo_small_map.virt) {
+ iounmap((void *) bamboo_small_map.virt);
+ bamboo_small_map.virt = 0;
+ }
+
+ if (bamboo_large_map.virt) {
+ iounmap((void *) bamboo_large_map.virt);
+ bamboo_large_map.virt = 0;
+ }
+
+ if (bamboo_sram_map.virt) {
+ iounmap((void *) bamboo_sram_map.virt);
+ bamboo_sram_map.virt = 0;
+ }
+}
+
+module_init(init_bamboo);
+module_exit(cleanup_bamboo);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Wade Farnsworth <wfarnsworth@mvista.com>");
+MODULE_DESCRIPTION("MTD map and partitions for IBM 440EP Bamboo boards");
diff -uprN linux-2.6.12/drivers/mtd/nand/Kconfig linux-2.6.12-440ep/drivers/mtd/nand/Kconfig
--- linux-2.6.12/drivers/mtd/nand/Kconfig 2005-07-25 12:57:05.000000000 -0700
+++ linux-2.6.12-440ep/drivers/mtd/nand/Kconfig 2005-07-25 11:32:32.000000000 -0700
@@ -109,6 +109,13 @@ config MTD_NAND_S3C2410_HWECC
currently not be able to switch to software, as there is no
implementation for ECC method used by the S3C2410
+config MTD_NAND_BAMBOO
+ tristate "NAND flash support on IBM/AMCC 440EP Eval Board (Bamboo)"
+ depends on BAMBOO && MTD_NAND
+ help
+ This enables the NAND flash driver on the IBM/AMCC 440EP Eval Board
+ (Bamboo).
+
config MTD_NAND_DISKONCHIP
tristate "DiskOnChip 2000, Millennium and Millennium Plus (NAND reimplementation) (EXPERIMENTAL)"
depends on MTD_NAND && EXPERIMENTAL
diff -uprN linux-2.6.12/drivers/mtd/nand/Kconfig.orig linux-2.6.12-440ep/drivers/mtd/nand/Kconfig.orig
--- linux-2.6.12/drivers/mtd/nand/Kconfig.orig 1969-12-31 17:00:00.000000000 -0700
+++ linux-2.6.12-440ep/drivers/mtd/nand/Kconfig.orig 2005-07-25 11:31:51.000000000 -0700
@@ -0,0 +1,194 @@
+# drivers/mtd/nand/Kconfig
+# $Id: Kconfig,v 1.31 2005/06/20 12:03:21 bjd Exp $
+
+menu "NAND Flash Device Drivers"
+ depends on MTD!=n
+
+config MTD_NAND
+ tristate "NAND Device Support"
+ depends on MTD
+ select MTD_NAND_IDS
+ help
+ This enables support for accessing all type of NAND flash
+ devices. For further information see
+ <http://www.linux-mtd.infradead.org/tech/nand.html>.
+
+config MTD_NAND_VERIFY_WRITE
+ bool "Verify NAND page writes"
+ depends on MTD_NAND
+ help
+ This adds an extra check when data is written to the flash. The
+ NAND flash device internally checks only bits transitioning
+ from 1 to 0. There is a rare possibility that even though the
+ device thinks the write was successful, a bit could have been
+ flipped accidentaly due to device wear or something else.
+
+config MTD_NAND_AUTCPU12
+ tristate "SmartMediaCard on autronix autcpu12 board"
+ depends on ARM && MTD_NAND && ARCH_AUTCPU12
+ help
+ This enables the driver for the autronix autcpu12 board to
+ access the SmartMediaCard.
+
+config MTD_NAND_EDB7312
+ tristate "Support for Cirrus Logic EBD7312 evaluation board"
+ depends on ARM && MTD_NAND && ARCH_EDB7312
+ help
+ This enables the driver for the Cirrus Logic EBD7312 evaluation
+ board to access the onboard NAND Flash.
+
+config MTD_NAND_H1900
+ tristate "iPAQ H1900 flash"
+ depends on ARM && MTD_NAND && ARCH_PXA && MTD_PARTITIONS
+ help
+ This enables the driver for the iPAQ h1900 flash.
+
+config MTD_NAND_SPIA
+ tristate "NAND Flash device on SPIA board"
+ depends on ARM && ARCH_P720T && MTD_NAND
+ help
+ If you had to ask, you don't have one. Say 'N'.
+
+config MTD_NAND_TOTO
+ tristate "NAND Flash device on TOTO board"
+ depends on ARM && ARCH_OMAP && MTD_NAND
+ help
+ Support for NAND flash on Texas Instruments Toto platform.
+
+config MTD_NAND_IDS
+ tristate
+
+config MTD_NAND_AU1550
+ tristate "Au1550 NAND support"
+ depends on SOC_AU1550 && MTD_NAND
+ help
+ This enables the driver for the NAND flash controller on the
+ AMD/Alchemy 1550 SOC.
+
+config MTD_NAND_RTC_FROM4
+ tristate "Renesas Flash ROM 4-slot interface board (FROM_BOARD4)"
+ depends on MTD_NAND && SH_SOLUTION_ENGINE
+ select REED_SOLOMON
+ select REED_SOLOMON_DEC8
+ help
+ This enables the driver for the Renesas Technology AG-AND
+ flash interface board (FROM_BOARD4)
+
+config MTD_NAND_PPCHAMELEONEVB
+ tristate "NAND Flash device on PPChameleonEVB board"
+ depends on PPCHAMELEONEVB && MTD_NAND
+ help
+ This enables the NAND flash driver on the PPChameleon EVB Board.
+
+config MTD_NAND_S3C2410
+ tristate "NAND Flash support for S3C2410/S3C2440 SoC"
+ depends on ARCH_S3C2410 && MTD_NAND
+ help
+ This enables the NAND flash controller on the S3C2410 and S3C2440
+ SoCs
+
+ No board specfic support is done by this driver, each board
+ must advertise a platform_device for the driver to attach.
+
+config MTD_NAND_S3C2410_DEBUG
+ bool "S3C2410 NAND driver debug"
+ depends on MTD_NAND_S3C2410
+ help
+ Enable debugging of the S3C2410 NAND driver
+
+config MTD_NAND_S3C2410_HWECC
+ bool "S3C2410 NAND Hardware ECC"
+ depends on MTD_NAND_S3C2410
+ help
+ Enable the use of the S3C2410's internal ECC generator when
+ using NAND. Early versions of the chip have had problems with
+ incorrect ECC generation, and if using these, the default of
+ software ECC is preferable.
+
+ If you lay down a device with the hardware ECC, then you will
+ currently not be able to switch to software, as there is no
+ implementation for ECC method used by the S3C2410
+
+config MTD_NAND_DISKONCHIP
+ tristate "DiskOnChip 2000, Millennium and Millennium Plus (NAND reimplementation) (EXPERIMENTAL)"
+ depends on MTD_NAND && EXPERIMENTAL
+ select REED_SOLOMON
+ select REED_SOLOMON_DEC16
+ help
+ This is a reimplementation of M-Systems DiskOnChip 2000,
+ Millennium and Millennium Plus as a standard NAND device driver,
+ as opposed to the earlier self-contained MTD device drivers.
+ This should enable, among other things, proper JFFS2 operation on
+ these devices.
+
+config MTD_NAND_DISKONCHIP_PROBE_ADVANCED
+ bool "Advanced detection options for DiskOnChip"
+ depends on MTD_NAND_DISKONCHIP
+ help
+ This option allows you to specify nonstandard address at which to
+ probe for a DiskOnChip, or to change the detection options. You
+ are unlikely to need any of this unless you are using LinuxBIOS.
+ Say 'N'.
+
+config MTD_NAND_DISKONCHIP_PROBE_ADDRESS
+ hex "Physical address of DiskOnChip" if MTD_NAND_DISKONCHIP_PROBE_ADVANCED
+ depends on MTD_NAND_DISKONCHIP
+ default "0"
+ ---help---
+ By default, the probe for DiskOnChip devices will look for a
+ DiskOnChip at every multiple of 0x2000 between 0xC8000 and 0xEE000.
+ This option allows you to specify a single address at which to probe
+ for the device, which is useful if you have other devices in that
+ range which get upset when they are probed.
+
+ (Note that on PowerPC, the normal probe will only check at
+ 0xE4000000.)
+
+ Normally, you should leave this set to zero, to allow the probe at
+ the normal addresses.
+
+config MTD_NAND_DISKONCHIP_PROBE_HIGH
+ bool "Probe high addresses"
+ depends on MTD_NAND_DISKONCHIP_PROBE_ADVANCED
+ help
+ By default, the probe for DiskOnChip devices will look for a
+ DiskOnChip at every multiple of 0x2000 between 0xC8000 and 0xEE000.
+ This option changes to make it probe between 0xFFFC8000 and
+ 0xFFFEE000. Unless you are using LinuxBIOS, this is unlikely to be
+ useful to you. Say 'N'.
+
+config MTD_NAND_DISKONCHIP_BBTWRITE
+ bool "Allow BBT writes on DiskOnChip Millennium and 2000TSOP"
+ depends on MTD_NAND_DISKONCHIP
+ help
+ On DiskOnChip devices shipped with the INFTL filesystem (Millennium
+ and 2000 TSOP/Alon), Linux reserves some space at the end of the
+ device for the Bad Block Table (BBT). If you have existing INFTL
+ data on your device (created by non-Linux tools such as M-Systems'
+ DOS drivers), your data might overlap the area Linux wants to use for
+ the BBT. If this is a concern for you, leave this option disabled and
+ Linux will not write BBT data into this area.
+ The downside of leaving this option disabled is that if bad blocks
+ are detected by Linux, they will not be recorded in the BBT, which
+ could cause future problems.
+ Once you enable this option, new filesystems (INFTL or others, created
+ in Linux or other operating systems) will not use the reserved area.
+ The only reason not to enable this option is to prevent damage to
+ preexisting filesystems.
+ Even if you leave this disabled, you can enable BBT writes at module
+ load time (assuming you build diskonchip as a module) with the module
+ parameter "inftl_bbt_write=1".
+
+ config MTD_NAND_SHARPSL
+ bool "Support for NAND Flash on Sharp SL Series (C7xx + others)"
+ depends on MTD_NAND && ARCH_PXA
+
+ config MTD_NAND_NANDSIM
+ bool "Support for NAND Flash Simulator"
+ depends on MTD_NAND && MTD_PARTITIONS
+
+ help
+ The simulator may simulate verious NAND flash chips for the
+ MTD nand layer.
+
+endmenu
diff -uprN linux-2.6.12/drivers/mtd/nand/Makefile linux-2.6.12-440ep/drivers/mtd/nand/Makefile
--- linux-2.6.12/drivers/mtd/nand/Makefile 2005-07-25 12:57:05.000000000 -0700
+++ linux-2.6.12-440ep/drivers/mtd/nand/Makefile 2005-07-25 11:32:32.000000000 -0700
@@ -13,6 +13,7 @@ obj-$(CONFIG_MTD_NAND_EDB7312) += edb73
obj-$(CONFIG_MTD_NAND_AU1550) += au1550nd.o
obj-$(CONFIG_MTD_NAND_PPCHAMELEONEVB) += ppchameleonevb.o
obj-$(CONFIG_MTD_NAND_S3C2410) += s3c2410.o
+obj-$(CONFIG_MTD_NAND_BAMBOO) += bamboo_nand.o
obj-$(CONFIG_MTD_NAND_DISKONCHIP) += diskonchip.o
obj-$(CONFIG_MTD_NAND_H1900) += h1910.o
obj-$(CONFIG_MTD_NAND_RTC_FROM4) += rtc_from4.o
diff -uprN linux-2.6.12/drivers/mtd/nand/Makefile.orig linux-2.6.12-440ep/drivers/mtd/nand/Makefile.orig
--- linux-2.6.12/drivers/mtd/nand/Makefile.orig 1969-12-31 17:00:00.000000000 -0700
+++ linux-2.6.12-440ep/drivers/mtd/nand/Makefile.orig 2005-07-25 11:31:51.000000000 -0700
@@ -0,0 +1,22 @@
+#
+# linux/drivers/nand/Makefile
+#
+# $Id: Makefile.common,v 1.15 2004/11/26 12:28:22 dedekind Exp $
+
+obj-$(CONFIG_MTD_NAND) += nand.o nand_ecc.o
+obj-$(CONFIG_MTD_NAND_IDS) += nand_ids.o
+
+obj-$(CONFIG_MTD_NAND_SPIA) += spia.o
+obj-$(CONFIG_MTD_NAND_TOTO) += toto.o
+obj-$(CONFIG_MTD_NAND_AUTCPU12) += autcpu12.o
+obj-$(CONFIG_MTD_NAND_EDB7312) += edb7312.o
+obj-$(CONFIG_MTD_NAND_AU1550) += au1550nd.o
+obj-$(CONFIG_MTD_NAND_PPCHAMELEONEVB) += ppchameleonevb.o
+obj-$(CONFIG_MTD_NAND_S3C2410) += s3c2410.o
+obj-$(CONFIG_MTD_NAND_DISKONCHIP) += diskonchip.o
+obj-$(CONFIG_MTD_NAND_H1900) += h1910.o
+obj-$(CONFIG_MTD_NAND_RTC_FROM4) += rtc_from4.o
+obj-$(CONFIG_MTD_NAND_SHARPSL) += sharpsl.o
+obj-$(CONFIG_MTD_NAND_NANDSIM) += nandsim.o
+
+nand-objs = nand_base.o nand_bbt.o
diff -uprN linux-2.6.12/drivers/mtd/nand/bamboo_nand.c linux-2.6.12-440ep/drivers/mtd/nand/bamboo_nand.c
--- linux-2.6.12/drivers/mtd/nand/bamboo_nand.c 1969-12-31 17:00:00.000000000 -0700
+++ linux-2.6.12-440ep/drivers/mtd/nand/bamboo_nand.c 2005-07-25 11:32:32.000000000 -0700
@@ -0,0 +1,467 @@
+/*
+ * drivers/mtd/bamboo_nand.c
+ *
+ * Overview:
+ * This is a device driver for the NAND flash devices found on the
+ * IBM 440EP Evaluation Board (Bamboo).
+ *
+ * Author: Wade Farnsworth <wfarnsworth@mvista.com>
+ *
+ * Copyright 2005 MontaVista Software Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/nand_ecc.h>
+#include <linux/mtd/partitions.h>
+#include <linux/config.h>
+#include <linux/delay.h>
+#include <linux/slab.h>
+#include <asm/io.h>
+#include <asm/ibm44x.h>
+#include <platforms/4xx/bamboo.h>
+
+struct ppc440ep_ndfc_regs {
+ uint cmd;
+ uint addr;
+ uint data;
+ uint reserved1;
+ uint ecc0;
+ uint ecc1;
+ uint ecc2;
+ uint ecc3;
+ uint ecc4;
+ uint ecc5;
+ uint ecc6;
+ uint ecc7;
+ uint b0cr;
+ uint b1cr;
+ uint b2cr;
+ uint b3cr;
+ uint cr;
+ uint sr;
+ uint hwctl;
+ uint reserved2;
+ uint revid;
+};
+
+static struct mtd_info *bamboo_nand0_mtd;
+static struct mtd_info *bamboo_nand1_mtd;
+static u8 hwctl;
+static struct ppc440ep_ndfc_regs *bamboo_ndfc;
+
+#define NAND0_NUM_PARTITIONS 1
+static struct mtd_partition nand0_partition_info[] = {
+ {
+ .name = "filesystem",
+ .offset = 0x0,
+ .size = 0x4000000,
+ },
+};
+
+#define NAND1_NUM_PARTITIONS 1
+static struct mtd_partition nand1_partition_info[] = {
+ {
+ .name = "filesystem",
+ .offset = 0x0,
+ .size = 0x10000000,
+ }
+};
+
+/*
+ * The 440EP has a NAND Flash Controller (NDFC) that handles all accesses to
+ * the NAND devices. The NDFC has command, address and data registers that
+ * when accessed will set up the NAND flash pins appropriately. We'll use the
+ * hwcontrol function to save the configuration in a global variable.
+ * We can then use this information in the read and write functions to
+ * determine which NDFC register to access. For the NCE commands, we'll just
+ * set or clear the Bank Enable bit in the NDFC Bank Config registers.
+ *
+ * There are 2 NAND devices on the board, a Samsung K9F1208U0A (64 MB) and a
+ * Samsung K9K2G08U0M (256 MB).
+ */
+static void
+bamboo_hwcontrol(struct mtd_info *mtd, int cmd)
+{
+ switch (cmd) {
+ case NAND_CTL_SETCLE:
+ hwctl |= 0x1;
+ break;
+ case NAND_CTL_CLRCLE:
+ hwctl &= ~0x1;
+ break;
+ case NAND_CTL_SETALE:
+ hwctl |= 0x2;
+ break;
+ case NAND_CTL_CLRALE:
+ hwctl &= ~0x2;
+ break;
+ }
+}
+
+static void
+bamboo_nand0_hwcontrol(struct mtd_info *mtd, int cmd)
+{
+ switch(cmd) {
+ case NAND_CTL_SETNCE:
+ bamboo_ndfc->b1cr |= 0x80000000;
+ break;
+ case NAND_CTL_CLRNCE:
+ bamboo_ndfc->b1cr &= ~0x80000000;
+ break;
+ default:
+ bamboo_hwcontrol(mtd, cmd);
+ }
+}
+
+static void
+bamboo_nand1_hwcontrol(struct mtd_info *mtd, int cmd)
+{
+ switch(cmd) {
+ case NAND_CTL_SETNCE:
+ bamboo_ndfc->b2cr |= 0x80000000;
+ break;
+ case NAND_CTL_CLRNCE:
+ bamboo_ndfc->b2cr &= ~0x80000000;
+ break;
+ default:
+ bamboo_hwcontrol(mtd, cmd);
+ }
+}
+
+static void
+bamboo_nand0_enable(void)
+{
+ bamboo_ndfc->cr = 0x01001000;
+}
+
+static void
+bamboo_nand1_enable(void)
+{
+ bamboo_ndfc->cr = 0x02003000;
+}
+
+static void
+bamboo_write_byte(struct mtd_info *mtd, u_char byte)
+{
+ if (hwctl & 0x1)
+ writeb(byte, &(bamboo_ndfc->cmd));
+ else if (hwctl & 0x2)
+ writeb(byte, &(bamboo_ndfc->addr));
+ else
+ writeb(byte, &(bamboo_ndfc->data));
+}
+
+static void
+bamboo_nand0_write_byte(struct mtd_info *mtd, u_char byte)
+{
+ bamboo_nand0_enable();
+ bamboo_write_byte(mtd, byte);
+}
+
+static void
+bamboo_nand1_write_byte(struct mtd_info *mtd, u_char byte)
+{
+ bamboo_nand1_enable();
+ bamboo_write_byte(mtd,byte);
+}
+
+static u_char
+bamboo_read_byte(struct mtd_info *mtd)
+{
+ u_char retval;
+ if (hwctl & 0x1)
+ retval = readb(&(bamboo_ndfc->cmd));
+ else if (hwctl & 0x2)
+ retval = readb(&(bamboo_ndfc->addr));
+ else
+ retval = readb(&(bamboo_ndfc->data));
+ return retval;
+}
+
+static u_char
+bamboo_nand0_read_byte(struct mtd_info *mtd)
+{
+ bamboo_nand0_enable();
+ return bamboo_read_byte(mtd);
+}
+
+static u_char
+bamboo_nand1_read_byte(struct mtd_info *mtd)
+{
+ bamboo_nand1_enable();
+ return bamboo_read_byte(mtd);
+}
+
+static void
+bamboo_nand_write_buf(struct mtd_info *mtd, const u_char * buf, int len)
+{
+ int i;
+ for (i = 0; i < len; i++) {
+ if (hwctl & 0x1)
+ writeb(buf[i], &(bamboo_ndfc->cmd));
+ else if (hwctl & 0x2)
+ writeb(buf[i], &(bamboo_ndfc->addr));
+ else
+ writeb(buf[i], &(bamboo_ndfc->data));
+ }
+}
+
+static void
+bamboo_nand0_write_buf(struct mtd_info *mtd, const u_char * buf, int len)
+{
+ bamboo_nand0_enable();
+ bamboo_nand_write_buf(mtd, buf, len);
+}
+
+static void
+bamboo_nand1_write_buf(struct mtd_info *mtd, const u_char * buf, int len)
+{
+ bamboo_nand1_enable();
+ bamboo_nand_write_buf(mtd, buf, len);
+}
+
+static void
+bamboo_nand_read_buf(struct mtd_info *mtd, u_char * buf, int len)
+{
+ int i;
+
+ for (i = 0; i < len; i++) {
+ if (hwctl & 0x1)
+ buf[i] = readb(&(bamboo_ndfc->cmd));
+ else if (hwctl & 0x2)
+ buf[i] = readb(&(bamboo_ndfc->addr));
+ else
+ buf[i] = readb(&(bamboo_ndfc->data));
+ }
+}
+
+static void
+bamboo_nand0_read_buf(struct mtd_info *mtd, u_char * buf, int len)
+{
+ bamboo_nand0_enable();
+ bamboo_nand_read_buf(mtd, buf, len);
+}
+
+static void
+bamboo_nand1_read_buf(struct mtd_info *mtd, u_char * buf, int len)
+{
+ bamboo_nand1_enable();
+ bamboo_nand_read_buf(mtd, buf, len);
+}
+
+static int
+bamboo_nand_verify_buf(struct mtd_info *mtd, const u_char * buf, int len)
+{
+ int i;
+
+ for (i = 0; i < len; i++) {
+ if (hwctl & 0x1) {
+ if (buf[i] != readb(&(bamboo_ndfc->cmd)))
+ return i;
+ } else if (hwctl & 0x2) {
+ if (buf[i] != readb(&(bamboo_ndfc->addr)))
+ return i;
+ } else {
+ if (buf[i] != readb(&(bamboo_ndfc->data)))
+ return i;
+ }
+
+ }
+
+ return 0;
+}
+
+static int
+bamboo_nand0_verify_buf(struct mtd_info *mtd, const u_char * buf, int len)
+{
+ bamboo_nand0_enable();
+ return bamboo_nand_verify_buf(mtd, buf, len);
+}
+
+static int
+bamboo_nand1_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
+{
+ bamboo_nand1_enable();
+ return bamboo_nand_verify_buf(mtd, buf, len);
+}
+
+static int
+bamboo_dev_ready(struct mtd_info *mtd)
+{
+ return ((bamboo_ndfc->sr) & 0x01000000) ? 1 : 0;
+}
+
+int __init
+bamboo_init(void)
+{
+ struct nand_chip *this;
+ uint * selection1_base, * gpio_base;
+ u8 selection1_val;
+ int err = 0;
+
+ hwctl = 0;
+
+ /*
+ * Bank 0 was set up by the firmware already. Bank 1 wasn't, so set it
+ * up now.
+ */
+
+ selection1_base = ioremap64(BAMBOO_FPGA_SELECTION1_REG_ADDR, 8);
+ if(!selection1_base){
+ printk("Ioremap to access FPGA Selection Register 1 failed \n");
+ err = -EIO;
+ goto out;
+ }
+ selection1_val = readb(selection1_base);
+ selection1_val |= 0x02;
+ writeb(selection1_val, selection1_base);
+ iounmap((void *)(selection1_base));
+
+ SDR_WRITE(DCRN_SDR_CUST0, SDR_READ(DCRN_SDR_CUST0) | 0x2);
+
+ gpio_base = ioremap64(0x0EF600B00ULL, 0x80);
+ if(!gpio_base) {
+ printk("Ioremap to access GPIO Registers failed \n");
+ err = -EIO;
+ goto out;
+ }
+ *(uint *) (gpio_base + 0x2) |= 0x00010000;
+ *(uint *) (gpio_base + 0x4) |= 0x00010000;
+ iounmap((void *) gpio_base);
+
+ bamboo_nand0_mtd = kmalloc(sizeof(struct mtd_info) +
+ sizeof(struct nand_chip),
+ GFP_KERNEL);
+
+ bamboo_nand1_mtd = kmalloc(sizeof (struct mtd_info) +
+ sizeof (struct nand_chip),
+ GFP_KERNEL);
+ if (!bamboo_nand1_mtd) {
+ printk("Unable to allocate NAND 1 MTD device structure.\n");
+ err = -ENOMEM;
+ goto out_mtd0;
+ }
+
+ bamboo_ndfc = ioremap64(BAMBOO_NAND_FLASH_REG_ADDR,
+ BAMBOO_NAND_FLASH_REG_SIZE);
+ if (!bamboo_ndfc) {
+ printk("Ioremap to access NDFC Registers failed \n");
+ err = -EIO;
+ goto out_mtd1;
+ }
+ bamboo_ndfc->b2cr = 0xC0007777;
+
+ /* Initialize structures */
+ memset((char *) bamboo_nand0_mtd, 0,
+ sizeof (struct mtd_info) + sizeof (struct nand_chip));
+
+ memset((char *) bamboo_nand1_mtd, 0,
+ sizeof (struct mtd_info) + sizeof (struct nand_chip));
+
+ /* Get pointer to private data */
+ this = (struct nand_chip *) (&bamboo_nand0_mtd[1]);
+ /* Link the private data with the MTD structure */
+ bamboo_nand0_mtd->priv = this;
+
+ /* Set address of NAND IO lines (Using Linear Data Access Region) */
+ this->IO_ADDR_R = (void __iomem *) ((ulong) bamboo_ndfc + 0x1000);
+ this->IO_ADDR_W = (void __iomem *) ((ulong) bamboo_ndfc + 0x1000);
+ /* Reference hardware control function */
+ this->hwcontrol = bamboo_nand0_hwcontrol;
+ /* Set command delay time */
+ this->chip_delay = 12;
+ this->eccmode = NAND_ECC_SOFT;
+ this->write_byte = bamboo_nand0_write_byte;
+ this->read_byte = bamboo_nand0_read_byte;
+ this->write_buf = bamboo_nand0_write_buf;
+ this->read_buf = bamboo_nand0_read_buf;
+ this->verify_buf = bamboo_nand0_verify_buf;
+ this->dev_ready = bamboo_dev_ready;
+
+ /* Scan to find existance of the device */
+ if (nand_scan(bamboo_nand0_mtd, 1)) {
+ err = -ENXIO;
+ goto out_ior;
+ }
+
+ /* Get pointer to private data */
+ this = (struct nand_chip *) (&bamboo_nand1_mtd[1]);
+ /* Link the private data with the MTD structure */
+ bamboo_nand1_mtd->priv = this;
+
+ /* Set address of NAND IO lines (Using Linear Data Access Region) */
+ this->IO_ADDR_R = (void __iomem *) ((ulong) bamboo_ndfc + 0x1000);
+ this->IO_ADDR_W = (void __iomem *) ((ulong) bamboo_ndfc + 0x1000);
+ /* Reference hardware control function */
+ this->hwcontrol = bamboo_nand1_hwcontrol;
+ /* Set command delay time */
+ this->chip_delay = 25;
+ this->eccmode = NAND_ECC_SOFT;
+ this->write_byte = bamboo_nand1_write_byte;
+ this->read_byte = bamboo_nand1_read_byte;
+ this->write_buf = bamboo_nand1_write_buf;
+ this->read_buf = bamboo_nand1_read_buf;
+ this->verify_buf = bamboo_nand1_verify_buf;
+ this->dev_ready = NULL;
+
+ /* Scan to find existance of the device */
+ if (nand_scan(bamboo_nand1_mtd, 1)) {
+ err = -ENXIO;
+ goto out_ior;
+ }
+
+
+ add_mtd_partitions(bamboo_nand0_mtd, nand0_partition_info,
+ NAND0_NUM_PARTITIONS);
+
+ add_mtd_partitions(bamboo_nand1_mtd, nand1_partition_info,
+ NAND1_NUM_PARTITIONS);
+ goto out;
+
+out_ior:
+ iounmap((void *)bamboo_ndfc);
+out_mtd1:
+ kfree(bamboo_nand1_mtd);
+out_mtd0:
+ kfree(bamboo_nand0_mtd);
+out:
+ return err;
+}
+
+static void __exit
+bamboo_cleanup(void)
+{
+ /* Unregister partitions */
+ del_mtd_partitions(bamboo_nand0_mtd);
+ del_mtd_partitions(bamboo_nand1_mtd);
+
+ /* Release resources, unregister device */
+ del_mtd_device(bamboo_nand0_mtd);
+ del_mtd_device(bamboo_nand1_mtd);
+
+ /* unmap physical address */
+ iounmap((void *) bamboo_ndfc);
+
+ /* Free the MTD device structure */
+ kfree(bamboo_nand0_mtd);
+ kfree(bamboo_nand1_mtd);
+}
+
+module_init(bamboo_init);
+module_exit(bamboo_cleanup);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Wade Farnsworth <wfarnsworth@mvista.com>");
+MODULE_DESCRIPTION
+ ("Board-specific glue layer for NAND flash on IBM 440EP eval board");
^ permalink raw reply
* Re: [PATCH 2/3] IBM EMAC support for the PPC440EP
From: Wade Farnsworth @ 2005-07-26 16:03 UTC (permalink / raw)
To: linuxppc-embedded
In-Reply-To: <1122393448.22059.32.camel@rhino.az.mvista.com>
[-- Attachment #1: Type: text/plain, Size: 124 bytes --]
This adds support to the IBM EMAC ethernet driver for the 440EP.
Signed-off by: Wade Farnsworth <wfarnsworth@mvista.com>
[-- Attachment #2: 440ep-net.patch --]
[-- Type: text/x-patch, Size: 2788 bytes --]
diff -uprN linux-2.6.12/drivers/net/ibm_emac/ibm_emac_phy.c linux-2.6.12-440ep/drivers/net/ibm_emac/ibm_emac_phy.c
--- linux-2.6.12/drivers/net/ibm_emac/ibm_emac_phy.c 2005-06-17 12:48:29.000000000 -0700
+++ linux-2.6.12-440ep/drivers/net/ibm_emac/ibm_emac_phy.c 2005-07-25 11:32:38.000000000 -0700
@@ -24,6 +24,7 @@
#include <linux/mii.h>
#include <linux/ethtool.h>
#include <linux/delay.h>
+#include <linux/vmalloc.h>
#include "ibm_emac_phy.h"
@@ -78,6 +79,45 @@ static int cis8201_init(struct mii_phy *
return 0;
}
+#ifdef CONFIG_BAMBOO
+static int ac104_init(struct mii_phy *phy)
+{
+ /*
+ * SW2 on the Bamboo is used for ethernet configuration and is accessed
+ * via the CONFIG2 register in the FPGA. If the ANEG pin is set,
+ * overwrite the supported features with the settings in SW2.
+ */
+ u8 *config2_addr, config2_val;
+ config2_addr = ioremap64(BAMBOO_FPGA_CONFIG2_REG_ADDR, 0x8);
+ config2_val = * config2_addr;
+ iounmap(config2_addr);
+ if (BAMBOO_AUTONEGOTIATE(config2_val))
+ return 0;
+ phy->def->features = SUPPORTED_TP | SUPPORTED_MII;
+ if (BAMBOO_FORCE_100Mbps(config2_val)) {
+ phy->speed = SPEED_100;
+ if (BAMBOO_FULL_DUPLEX_EN(config2_val)) {
+ phy->def->features |= SUPPORTED_100baseT_Full;
+ phy->duplex = DUPLEX_FULL;
+ } else {
+ phy->def->features |= SUPPORTED_100baseT_Half;
+ phy->duplex = DUPLEX_HALF;
+ }
+ } else {
+ phy->speed = SPEED_10;
+ if (BAMBOO_FULL_DUPLEX_EN(config2_val)) {
+ phy->def->features |= SUPPORTED_10baseT_Full;
+ phy->duplex = DUPLEX_FULL;
+ } else {
+ phy->def->features |= SUPPORTED_10baseT_Half;
+ phy->duplex = DUPLEX_HALF;
+ }
+ }
+
+ return 0;
+}
+#endif
+
static int genmii_setup_aneg(struct mii_phy *phy, u32 advertise)
{
u16 ctl, adv;
@@ -226,6 +266,17 @@ static struct mii_phy_ops cis8201_phy_op
read_link:cis8201_read_link
};
+/* AC104 phy ops */
+static struct mii_phy_ops ac104_phy_ops = {
+#ifdef CONFIG_BAMBOO
+ init:ac104_init,
+#endif
+ setup_aneg:genmii_setup_aneg,
+ setup_forced:genmii_setup_forced,
+ poll_link:genmii_poll_link,
+ read_link:genmii_read_link
+};
+
/* Generic implementation for most 10/100 PHYs */
static struct mii_phy_ops generic_phy_ops = {
setup_aneg:genmii_setup_aneg,
@@ -234,6 +285,15 @@ static struct mii_phy_ops generic_phy_op
read_link:genmii_read_link
};
+static struct mii_phy_def ac104_phy_def = {
+ phy_id:0x00225540,
+ phy_id_mask:0x00fffff0,
+ name:"AC104 Ethernet",
+ features:MII_BASIC_FEATURES,
+ magic_aneg:0,
+ ops:&ac104_phy_ops
+};
+
static struct mii_phy_def cis8201_phy_def = {
phy_id:0x000fc410,
phy_id_mask:0x000ffff0,
@@ -254,6 +314,7 @@ static struct mii_phy_def genmii_phy_def
static struct mii_phy_def *mii_phy_table[] = {
&cis8201_phy_def,
+ &ac104_phy_def,
&genmii_phy_def,
NULL
};
^ permalink raw reply
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