* [RFC][PATCH] board-specific platform setup for mpc8272
From: Vitaly Bordug @ 2005-08-19 14:37 UTC (permalink / raw)
To: Kumar Gala; +Cc: Pantelis Antoniou, linuxppc-embedded list
[-- Attachment #1: Type: text/plain, Size: 394 bytes --]
This is platform setup for MPC8272ADS to use it with fs_enet driver.
Assumes that [PATCH] ppc32: Add ppc_sys descriptions for PowerQUICC II
devices is applied. This is not in the final state (since fs_enet will
be modified a bit),but it could be useful if someone does want to test
fs_enet on the likewise board.
Signed-off-by: Vitaly Bordug <vbordug@ru.mvista.com>
--
Sincerely,
Vitaly
[-- Attachment #2: mpc8272_platform_bsp.patch --]
[-- Type: text/x-patch, Size: 12224 bytes --]
diff --git a/arch/ppc/platforms/Makefile b/arch/ppc/platforms/Makefile
--- a/arch/ppc/platforms/Makefile
+++ b/arch/ppc/platforms/Makefile
@@ -19,6 +19,8 @@ ifeq ($(CONFIG_PPC_PMAC),y)
obj-$(CONFIG_NVRAM) += pmac_nvram.o
obj-$(CONFIG_CPU_FREQ_PMAC) += pmac_cpufreq.o
endif
+
+obj-$(CONFIG_ADS8272) += mpc8272ads_setup.o
obj-$(CONFIG_PMAC_BACKLIGHT) += pmac_backlight.o
obj-$(CONFIG_PREP_RESIDUAL) += residual.o
obj-$(CONFIG_ADIR) += adir_setup.o adir_pic.o adir_pci.o
diff --git a/arch/ppc/platforms/mpc8272ads_setup.c b/arch/ppc/platforms/mpc8272ads_setup.c
new file mode 100644
--- /dev/null
+++ b/arch/ppc/platforms/mpc8272ads_setup.c
@@ -0,0 +1,237 @@
+/*
+ * arch/ppc/platforms/82xx/pq2ads_pd.c
+ *
+ * MPC82xx Board-specific PlatformDevice descriptions
+ *
+ * Maintainer: Kumar Gala <kumar.gala@freescale.com>
+ *
+ * 2005 (c) MontaVista Software, Inc.
+ * Vitaly Bordug <vbordug@ru.mvista.com>
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/device.h>
+#include <linux/ioport.h>
+#include <linux/fs_enet_pd.h>
+
+#include <asm/io.h>
+#include <asm/mpc8260.h>
+#include <asm/cpm2.h>
+#include <asm/immap_cpm2.h>
+#include <asm/irq.h>
+#include <asm/ppc_sys.h>
+#include <asm/ppcboot.h>
+
+#include "pq2ads_pd.h"
+
+static struct fs_mii_bus_info mii_bus_info = {
+ .method = fsmii_bitbang,
+ .id = 0,
+ .i.bitbang = {
+ .mdio_port = fsiop_portc,
+ .mdio_bit = 18,
+ .mdc_port = fsiop_portc,
+ .mdc_bit = 19,
+ .delay = 1,
+ },
+};
+
+static struct fs_platform_info mpc82xx_fcc1_pdata = {
+ .fs_no = fsid_fcc1,
+ .cp_page = CPM_CR_FCC1_PAGE,
+ .cp_block = CPM_CR_FCC1_SBLOCK,
+ .clk_trx = (PC_F1RXCLK | PC_F1TXCLK),
+ .clk_route = CMX1_CLK_ROUTE,
+ .clk_mask = CMX1_CLK_MASK,
+
+
+ .phy_addr = 0,
+#ifdef PHY_INTERRUPT
+ .phy_irq = PHY_INTERRUPT,
+#endif
+ .mem_offset = FCC1_MEM_OFFSET,
+ .bus_info = &mii_bus_info,
+ .rx_ring = 32,
+ .tx_ring = 32,
+ .rx_copybreak = 240,
+ .use_napi = 0,
+ .napi_weight = 17,
+};
+
+static struct fs_platform_info mpc82xx_fcc2_pdata = {
+ .fs_no = fsid_fcc2,
+ .cp_page = CPM_CR_FCC2_PAGE,
+ .cp_block = CPM_CR_FCC2_SBLOCK,
+ .clk_trx = (PC_F2RXCLK | PC_F2TXCLK),
+ .clk_route = CMX2_CLK_ROUTE,
+ .clk_mask = CMX2_CLK_MASK,
+
+ .phy_addr = 3,
+#ifdef PHY_INTERRUPT
+ .phy_irq = PHY_INTERRUPT,
+#endif
+
+ .mem_offset = FCC2_MEM_OFFSET,
+ .bus_info = &mii_bus_info,
+ .rx_ring = 32,
+ .tx_ring = 32,
+ .rx_copybreak = 240,
+ .use_napi = 0,
+ .napi_weight = 17,
+};
+
+/* Initialize the I/O pins for the FCC Ethernet. */
+static void init_fcc_ioports(void)
+{
+ struct immap *immap;
+ struct io_port *io;
+ u32 tempval;
+
+ immap = cpm2_immr;
+
+ io = &immap->im_ioport;
+ /* FCC1 pins are on port A/C. FCC2/3 are port B/C. */
+ /* Configure port A and C pins for FCC1 Ethernet. */
+ tempval = in_be32(&io->iop_pdira);
+ tempval &= ~PA1_DIRA0;
+ tempval |= PA1_DIRA1;
+ out_be32(&io->iop_pdira, tempval);
+
+ tempval = in_be32(&io->iop_psora);
+ tempval &= ~PA1_PSORA0;
+ tempval |= PA1_PSORA1;
+ out_be32(&io->iop_psora, tempval);
+
+ tempval = in_be32(&io->iop_ppara);
+ tempval |= (PA1_DIRA0 | PA1_DIRA1);
+ out_be32(&io->iop_ppara, tempval);
+
+ tempval = in_be32(&io->iop_pdirb);
+ tempval &= ~PB2_DIRB0;
+ tempval |= PB2_DIRB1;
+ out_be32(&io->iop_pdirb, tempval);
+
+ tempval = in_be32(&io->iop_psorb);
+ tempval &= ~PB2_PSORB0;
+ tempval |= PB2_PSORB1;
+ out_be32(&io->iop_psorb, tempval);
+
+ tempval = in_be32(&io->iop_pparb);
+ tempval |= (PB2_DIRB0 | PB2_DIRB1);
+ out_be32(&io->iop_pparb, tempval);
+
+ /* Port C has clocks...... */
+ tempval = in_be32(&io->iop_psorc);
+ tempval &= ~(CLK_TRX);
+ out_be32(&io->iop_psorc, tempval);
+
+ tempval = in_be32(&io->iop_pdirc);
+ tempval &= ~(CLK_TRX);
+ out_be32(&io->iop_pdirc, tempval);
+
+ tempval = in_be32(&io->iop_pparc);
+ tempval |= (CLK_TRX);
+ out_be32(&io->iop_pparc, tempval);
+
+ /* ....and the MII serial clock/data. */
+ io->iop_pdatc |= (PC_MDIO | PC_MDCK);
+ io->iop_podrc &= ~(PC_MDIO | PC_MDCK);
+ io->iop_pdirc |= (PC_MDIO | PC_MDCK);
+ io->iop_pparc &= ~(PC_MDIO | PC_MDCK);
+
+ /* Configure Serial Interface clock routing.
+ * First, clear all FCC bits to zero,
+ * then set the ones we want.
+ */
+ immap->im_cpmux.cmx_fcr &= ~(CPMUX_CLK_MASK);
+ immap->im_cpmux.cmx_fcr |= CPMUX_CLK_ROUTE;
+}
+
+
+static void __init mpc8272ads_fixup_enet_pdata(struct platform_device *pdev,
+ int idx)
+{
+ bd_t* bi = (void*)__res;
+ cpm2_map_t* immr = (cpm2_map_t *)CPM_MAP_ADDR;
+ int fs_no = fsid_fcc1+pdev->id-1;
+
+ /*all-in-one for now*/
+ init_fcc_ioports();
+
+ mpc82xx_fcc1_pdata.dpram_offset = mpc82xx_fcc2_pdata.dpram_offset = (u32)immr->im_dprambase;
+ mpc82xx_fcc1_pdata.fcc_regs_c = mpc82xx_fcc2_pdata.fcc_regs_c = (u32)immr->im_fcc_c;
+
+ /* At last wi fill the platform_data pointers with respective data */
+ switch(fs_no) {
+ case fsid_fcc1:
+ memcpy(&mpc82xx_fcc1_pdata.macaddr,bi->bi_enetaddr,6);
+ pdev->dev.platform_data = &mpc82xx_fcc1_pdata;
+ break;
+ case fsid_fcc2:
+ memcpy(&mpc82xx_fcc2_pdata.macaddr,bi->bi_enetaddr,6);
+ mpc82xx_fcc2_pdata.macaddr[5] ^= 1;
+ pdev->dev.platform_data = &mpc82xx_fcc2_pdata;
+ break;
+ }
+}
+
+static int __init mpc8272ads_platform_notify(struct device *dev)
+{
+ static struct {
+ const char *bus_id;
+ void (*rtn) (struct platform_device * pdev, int idx);
+ } dev_map[] = {
+ {"fsl-cpm-fcc", mpc8272ads_fixup_enet_pdata},
+ };
+ struct platform_device *pdev;
+ int i, j, idx;
+ const char *s;
+ if (dev && dev->bus_id)
+ for (i = 0; i < ARRAY_SIZE(dev_map); i++) {
+ idx = -1;
+
+ if ((s = strrchr(dev->bus_id, '.')) != NULL)
+ idx = (int)simple_strtol(s + 1, NULL, 10);
+ else
+ s = dev->bus_id;
+ j = s - dev->bus_id;
+ if (!strncmp(dev->bus_id, dev_map[i].bus_id, j)) {
+ pdev =
+ container_of(dev, struct platform_device,
+ dev);
+ dev_map[i].rtn(pdev, idx);
+ }
+ }
+ return 0;
+}
+
+int __init mpc8272ads_init(void)
+{
+ cpm2_map_t* immr = (cpm2_map_t *)CPM_MAP_ADDR;
+
+ printk(KERN_NOTICE "mpc8272ads: Init\n");
+
+ platform_notify = mpc8272ads_platform_notify;
+
+ identify_ppc_sys_by_name_and_id(BOARD_NAME,cpm2_immr->im_memctl.memc_immr);
+
+ identify_ppc_sys_by_name(BOARD_NAME);
+
+ /*Remove stuff does not utilized platform way*/
+ ppc_sys_device_remove(MPC82xx_CPM_SCC1);
+ ppc_sys_device_remove(MPC82xx_CPM_SCC2);
+ ppc_sys_device_remove(MPC82xx_CPM_SCC3);
+ ppc_sys_device_remove(MPC82xx_CPM_SCC4);
+ ppc_sys_device_remove(MPC82xx_CPM_SMC1);
+ ppc_sys_device_remove(MPC82xx_CPM_SMC2);
+
+ return 0;
+}
+
+arch_initcall(mpc8272ads_init);
diff --git a/arch/ppc/platforms/pq2ads.h b/arch/ppc/platforms/pq2ads.h
--- a/arch/ppc/platforms/pq2ads.h
+++ b/arch/ppc/platforms/pq2ads.h
@@ -13,6 +13,10 @@
#include <asm/ppcboot.h>
+#if defined(CONFIG_ADS8272)
+#define BOARD_NAME "8272"
+#endif
+
/* Memory map is configured by the PROM startup.
* We just map a few things we need. The CSR is actually 4 byte-wide
* registers that can be accessed as 8-, 16-, or 32-bit values.
diff --git a/arch/ppc/platforms/pq2ads_pd.h b/arch/ppc/platforms/pq2ads_pd.h
new file mode 100644
--- /dev/null
+++ b/arch/ppc/platforms/pq2ads_pd.h
@@ -0,0 +1,135 @@
+#ifndef __PQ2ADS_PD_H
+#define __PQ2ADS_PD_H
+/*
+ * arch/ppc/platforms/82xx/pq2ads_pd.h
+ *
+ * Some defines for MPC82xx board-specific PlatformDevice descriptions
+ *
+ * Maintainer: Kumar Gala <kumar.gala@freescale.com>
+ *
+ * 2005 (c) MontaVista Software, Inc.
+ * Vitaly Bordug <vbordug@ru.mvista.com>
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+/* FCC1 Clock Source Configuration. These can be redefined in the board specific file.
+ Can only choose from CLK9-12 */
+
+#define F1_RXCLK 11
+#define F1_TXCLK 10
+
+/* FCC2 Clock Source Configuration. These can be redefined in the board specific file.
+ Can only choose from CLK13-16 */
+#define F2_RXCLK 15
+#define F2_TXCLK 16
+
+/* FCC3 Clock Source Configuration. These can be redefined in the board specific file.
+ Can only choose from CLK13-16 */
+#define F3_RXCLK 15
+#define F3_TXCLK 16
+
+/* MDIO and MDCK settings. These can be redefined in the board specific file.*/
+#define PC_MDIO 0x00002000U
+#define PC_MDCK 0x00001000U
+
+/* Automatically generates register configurations */
+#define PC_CLK(x) ((uint)(1<<(x-1))) /* FCC CLK I/O ports */
+
+#define CMXFCR_RF1CS(x) ((uint)((x-5)<<27)) /* FCC1 Receive Clock Source */
+#define CMXFCR_TF1CS(x) ((uint)((x-5)<<24)) /* FCC1 Transmit Clock Source */
+#define CMXFCR_RF2CS(x) ((uint)((x-9)<<19)) /* FCC2 Receive Clock Source */
+#define CMXFCR_TF2CS(x) ((uint)((x-9)<<16)) /* FCC2 Transmit Clock Source */
+#define CMXFCR_RF3CS(x) ((uint)((x-9)<<11)) /* FCC3 Receive Clock Source */
+#define CMXFCR_TF3CS(x) ((uint)((x-9)<<8)) /* FCC3 Transmit Clock Source */
+
+#define PC_F1RXCLK PC_CLK(F1_RXCLK)
+#define PC_F1TXCLK PC_CLK(F1_TXCLK)
+#define CMX1_CLK_ROUTE (CMXFCR_RF1CS(F1_RXCLK) | CMXFCR_TF1CS(F1_TXCLK))
+#define CMX1_CLK_MASK ((uint)0xff000000)
+
+#define PC_F2RXCLK PC_CLK(F2_RXCLK)
+#define PC_F2TXCLK PC_CLK(F2_TXCLK)
+#define CMX2_CLK_ROUTE (CMXFCR_RF2CS(F2_RXCLK) | CMXFCR_TF2CS(F2_TXCLK))
+#define CMX2_CLK_MASK ((uint)0x00ff0000)
+
+#define PC_F3RXCLK PC_CLK(F3_RXCLK)
+#define PC_F3TXCLK PC_CLK(F3_TXCLK)
+#define CMX3_CLK_ROUTE (CMXFCR_RF3CS(F3_RXCLK) | CMXFCR_TF3CS(F3_TXCLK))
+#define CMX3_CLK_MASK ((uint)0x0000ff00)
+
+/* Some board-specific defines here... Temporary I hope -vb*/
+#ifdef CONFIG_ADS8272
+#define CPMUX_CLK_MASK (CMX1_CLK_MASK | CMX2_CLK_MASK)
+#define CPMUX_CLK_ROUTE (CMX1_CLK_ROUTE | CMX2_CLK_ROUTE)
+#else
+#error You need to define cpmux setup for your board
+#endif
+
+#ifdef CONFIG_ADS8272
+#define CLK_TRX (F1_TXCLK | F1_TXCLK | F2_TXCLK | F2_RXCLK)
+#else
+#error You need to define clock source for your board
+#endif
+
+
+/* I/O Pin assignment for FCC1. I don't yet know the best way to do this,
+ * but there is little variation among the choices.
+ */
+#define PA1_COL 0x00000001U
+#define PA1_CRS 0x00000002U
+#define PA1_TXER 0x00000004U
+#define PA1_TXEN 0x00000008U
+#define PA1_RXDV 0x00000010U
+#define PA1_RXER 0x00000020U
+#define PA1_TXDAT 0x00003c00U
+#define PA1_RXDAT 0x0003c000U
+#define PA1_PSORA0 (PA1_RXDAT | PA1_TXDAT)
+#define PA1_PSORA1 (PA1_COL | PA1_CRS | PA1_TXER | PA1_TXEN | \
+ PA1_RXDV | PA1_RXER)
+#define PA1_DIRA0 (PA1_RXDAT | PA1_CRS | PA1_COL | PA1_RXER | PA1_RXDV)
+#define PA1_DIRA1 (PA1_TXDAT | PA1_TXEN | PA1_TXER)
+
+
+/* I/O Pin assignment for FCC2. I don't yet know the best way to do this,
+ * but there is little variation among the choices.
+ */
+#define PB2_TXER 0x00000001U
+#define PB2_RXDV 0x00000002U
+#define PB2_TXEN 0x00000004U
+#define PB2_RXER 0x00000008U
+#define PB2_COL 0x00000010U
+#define PB2_CRS 0x00000020U
+#define PB2_TXDAT 0x000003c0U
+#define PB2_RXDAT 0x00003c00U
+#define PB2_PSORB0 (PB2_RXDAT | PB2_TXDAT | PB2_CRS | PB2_COL | \
+ PB2_RXER | PB2_RXDV | PB2_TXER)
+#define PB2_PSORB1 (PB2_TXEN)
+#define PB2_DIRB0 (PB2_RXDAT | PB2_CRS | PB2_COL | PB2_RXER | PB2_RXDV)
+#define PB2_DIRB1 (PB2_TXDAT | PB2_TXEN | PB2_TXER)
+
+
+/* I/O Pin assignment for FCC3. I don't yet know the best way to do this,
+ * but there is little variation among the choices.
+ */
+#define PB3_RXDV 0x00004000U
+#define PB3_RXER 0x00008000U
+#define PB3_TXER 0x00010000U
+#define PB3_TXEN 0x00020000U
+#define PB3_COL 0x00040000U
+#define PB3_CRS 0x00080000U
+#define PB3_TXDAT 0x0f000000U
+#define PB3_RXDAT 0x00f00000U
+#define PB3_PSORB0 (PB3_RXDAT | PB3_TXDAT | PB3_CRS | PB3_COL | \
+ PB3_RXER | PB3_RXDV | PB3_TXER | PB3_TXEN)
+#define PB3_PSORB1 0
+#define PB3_DIRB0 (PB3_RXDAT | PB3_CRS | PB3_COL | PB3_RXER | PB3_RXDV)
+#define PB3_DIRB1 (PB3_TXDAT | PB3_TXEN | PB3_TXER)
+
+#define FCC_MEM_OFFSET(x) (CPM_FCC_SPECIAL_BASE + (x*128))
+#define FCC1_MEM_OFFSET FCC_MEM_OFFSET(0)
+#define FCC2_MEM_OFFSET FCC_MEM_OFFSET(1)
+
+#endif
^ permalink raw reply
* Re: [RFC][PATCH] [1/2] 8xx platform definitions
From: Vitaly Bordug @ 2005-08-19 13:31 UTC (permalink / raw)
To: Kumar Gala; +Cc: Schaefer-Hutter, Peter, linuxppc-embedded list
In-Reply-To: <8E342283C2100540AAC5D1030970547774A3D9@rcexc.racoms.loc>
[-- Attachment #1: Type: text/plain, Size: 152 bytes --]
Strange but one hunk header is missing in original patch.
Here's it again.
Signed-off-by: Vitaly Bordug <vbordug@ru.mvista.com>
--
Sincerely,
Vitaly
[-- Attachment #2: bsp_plat_defs_885.1.patch --]
[-- Type: text/x-patch, Size: 23709 bytes --]
diff --git a/arch/ppc/Kconfig b/arch/ppc/Kconfig
--- a/arch/ppc/Kconfig
+++ b/arch/ppc/Kconfig
@@ -527,6 +527,42 @@ config WINCEPT
endchoice
+menu "Freescale Ethernet driver platform-specific options"
+ depends on FS_ENET
+
+ config MPC8xx_SECOND_ETH
+ bool "Second Ethernet channel"
+ depends on (MPC885ADS || MPC86xADS)
+ default y
+ help
+ This enables support for second Ethernet on MPC885ADS and MPC86xADS boards.
+ The latter will use SCC1, for 885ADS you can select it below.
+
+ choice
+ prompt "Second Ethernet channel"
+ depends on MPC8xx_SECOND_ETH
+ default MPC885ADS_SECOND_ETH_FEC2
+
+ config MPC885ADS_SECOND_ETH_FEC2
+ bool "FEC2"
+ help
+ Enable FEC2 to serve as 2-nd Ethernet channel. Note that SMC2
+ (often 2-nd UART) will not work if this is enabled.
+
+ config MPC885ADS_SECOND_ETH_SCC
+ bool "SCC3"
+ help
+ Enable SCC3 to serve as 2-nd Ethernet channel. Note that SMC2
+ (often 1-nd UART) will not work if this is enabled.
+
+ endchoice
+
+ config MPC885ADS_SCC_ENET_FIXED
+ depends on MPC885ADS_SECOND_ETH_SCC
+ default n
+ bool "Use fixed MII-less mode for SCC Ethernet"
+endmenu
+
choice
prompt "Machine Type"
depends on 6xx || POWER3 || POWER4
diff --git a/arch/ppc/platforms/Makefile b/arch/ppc/platforms/Makefile
--- a/arch/ppc/platforms/Makefile
+++ b/arch/ppc/platforms/Makefile
@@ -46,6 +46,7 @@ obj-$(CONFIG_SANDPOINT) += sandpoint.o
obj-$(CONFIG_SBC82xx) += sbc82xx.o
obj-$(CONFIG_SPRUCE) += spruce.o
obj-$(CONFIG_LITE5200) += lite5200.o
+obj-$(CONFIG_MPC885ADS) += mpc885ads_setup.o
ifeq ($(CONFIG_SMP),y)
obj-$(CONFIG_PPC_PMAC) += pmac_smp.o
diff --git a/arch/ppc/platforms/mpc885ads.h b/arch/ppc/platforms/mpc885ads.h
--- a/arch/ppc/platforms/mpc885ads.h
+++ b/arch/ppc/platforms/mpc885ads.h
@@ -88,5 +88,7 @@
#define SICR_ENET_MASK ((uint)0x00ff0000)
#define SICR_ENET_CLKRT ((uint)0x002c0000)
+#define BOARD_NAME "MPC885"
+
#endif /* __ASM_MPC885ADS_H__ */
#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/mpc885ads_setup.c b/arch/ppc/platforms/mpc885ads_setup.c
new file mode 100644
--- /dev/null
+++ b/arch/ppc/platforms/mpc885ads_setup.c
@@ -0,0 +1,404 @@
+/*arch/ppc/platforms/mpc885ads-setup.c
+ *
+ * Platform setup for the Freescale mpc885ads board
+ *
+ * Vitaly Bordug <vbordug@ru.mvista.com>
+ *
+ * Copyright 2005 MontaVista Software Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/param.h>
+#include <linux/string.h>
+#include <linux/ioport.h>
+#include <linux/device.h>
+
+#include <linux/fs_enet_pd.h>
+#include <linux/mii.h>
+
+#include <asm/delay.h>
+#include <asm/io.h>
+#include <asm/machdep.h>
+#include <asm/page.h>
+#include <asm/processor.h>
+#include <asm/system.h>
+#include <asm/time.h>
+#include <asm/ppcboot.h>
+#include <asm/8xx_immap.h>
+#include <asm/commproc.h>
+#include <asm/ppc_sys.h>
+
+extern unsigned char __res[];
+
+/* access ports */
+#define setbits32(_addr, _v) out_be32(&(_addr), in_be32(&(_addr)) | (_v))
+#define clrbits32(_addr, _v) out_be32(&(_addr), in_be32(&(_addr)) & ~(_v))
+
+#define setbits16(_addr, _v) out_be16(&(_addr), in_be16(&(_addr)) | (_v))
+#define clrbits16(_addr, _v) out_be16(&(_addr), in_be16(&(_addr)) & ~(_v))
+
+void __init mpc885ads_scc_phy_init(void);
+static void setup_fec1_ioports(void);
+static void setup_fec2_ioports(void);
+static void setup_scc3_ioports(void);
+
+
+static struct fs_mii_bus_info fec_mii_bus_info = {
+ .method = fsmii_fec,
+ .id = 0,
+};
+
+static struct fs_mii_bus_info scc_mii_bus_info = {
+#ifdef CONFIG_MPC885ADS_SCC_ENET_FIXED
+ .method = fsmii_fixed,
+#else
+ .method = fsmii_fec,
+#endif
+
+ .id = 0,
+};
+
+static struct fs_platform_info mpc8xx_fec_pdata[] = {
+ {
+ .rx_ring = 128,
+ .tx_ring = 16,
+ .rx_copybreak = 240,
+
+ .use_napi = 1,
+ .napi_weight = 17,
+ .phy_irq = SIU_IRQ7,
+ .phy_addr = 0,
+ .bus_info = &fec_mii_bus_info,
+ .init_ioports = &setup_fec1_ioports,
+ }, {
+ .rx_ring = 128,
+ .tx_ring = 16,
+ .rx_copybreak = 240,
+
+ .use_napi = 1,
+ .napi_weight = 17,
+ .phy_irq = SIU_IRQ7,
+ .phy_addr = 1,
+
+ .bus_info = &fec_mii_bus_info,
+ .init_ioports = &setup_fec2_ioports,
+ }
+};
+
+static struct fs_platform_info mpc8xx_scc_pdata = {
+ .rx_ring = 64,
+ .tx_ring = 8,
+ .rx_copybreak = 240,
+
+ .use_napi = 1,
+ .napi_weight = 17,
+#ifdef CONFIG_MPC885ADS_SCC_ENET_FIXED
+ .phy_irq = -1,
+ .phy_addr = -1,
+#else
+ .phy_irq = SIU_IRQ7,
+ .phy_addr = 2,
+#endif
+ .bus_info = &scc_mii_bus_info,
+ .init_ioports = &setup_scc3_ioports,
+
+};
+
+static void __init mpc885_nonplatform_device_init(void)
+{
+ immap_t *immap = (immap_t *) IMAP_ADDR;
+ volatile cpm8xx_t *cp = cpmp;
+ unsigned long *bcsr_io;
+
+ bcsr_io = ioremap(BCSR1, sizeof(unsigned long));
+#ifdef CONFIG_SERIAL_CPM_SMC1
+ cp->cp_simode &= ~(0xe0000000 >> 17); /* brg1 */
+ out_be32((volatile unsigned __iomem *)bcsr_io,
+ in_be32((volatile unsigned __iomem *)bcsr_io) &
+ ~BCSR1_RS232EN_1);
+#else
+ out_be32((volatile unsigned __iomem *)bcsr_io,
+ in_be32((volatile unsigned __iomem *)bcsr_io) |
+ BCSR1_RS232EN_1);
+ cp->cp_smc[0].smc_smcmr = 0;
+ cp->cp_smc[0].smc_smce = 0;
+#endif
+
+#ifdef CONFIG_SERIAL_CPM_SMC2
+ cp->cp_simode &= ~(0xe0000000 >> 1);
+ cp->cp_simode |= (0x20000000 >> 1); /* brg2 */
+ out_be32((volatile unsigned __iomem *)bcsr_io,
+ in_be32((volatile unsigned __iomem *)bcsr_io) &
+ ~BCSR1_RS232EN_2);
+#else
+ out_be32((volatile unsigned __iomem *)bcsr_io,
+ in_be32((volatile unsigned __iomem *)bcsr_io) |
+ BCSR1_RS232EN_2);
+ cp->cp_smc[1].smc_smcmr = 0;
+ cp->cp_smc[1].smc_smce = 0;
+#endif
+ iounmap(bcsr_io);
+
+#ifdef CONFIG_FS_ENET
+ /* use MDC for MII (common) */
+ setbits16(immap->im_ioport.iop_pdpar, 0x0080);
+ clrbits16(immap->im_ioport.iop_pddir, 0x0080);
+#endif
+}
+
+static void setup_fec1_ioports(void)
+{
+ immap_t *immap = (immap_t *) IMAP_ADDR;
+
+ /* configure FEC1 pins */
+ setbits16(immap->im_ioport.iop_papar, 0xf830);
+ setbits16(immap->im_ioport.iop_padir, 0x0830);
+ clrbits16(immap->im_ioport.iop_padir, 0xf000);
+ setbits32(immap->im_cpm.cp_pbpar, 0x00001001);
+
+ clrbits32(immap->im_cpm.cp_pbdir, 0x00001001);
+ setbits16(immap->im_ioport.iop_pcpar, 0x000c);
+ clrbits16(immap->im_ioport.iop_pcdir, 0x000c);
+ setbits32(immap->im_cpm.cp_pepar, 0x00000003);
+
+ setbits32(immap->im_cpm.cp_pedir, 0x00000003);
+ clrbits32(immap->im_cpm.cp_peso, 0x00000003);
+ clrbits32(immap->im_cpm.cp_cptr, 0x00000100);
+}
+
+static void setup_fec2_ioports(void)
+{
+ immap_t *immap = (immap_t *) IMAP_ADDR;
+
+ /* configure FEC2 pins */
+ setbits32(immap->im_cpm.cp_pepar, 0x0003fffc);
+ setbits32(immap->im_cpm.cp_pedir, 0x0003fffc);
+ setbits32(immap->im_cpm.cp_peso, 0x00037800);
+ clrbits32(immap->im_cpm.cp_peso, 0x000087fc);
+ clrbits32(immap->im_cpm.cp_cptr, 0x00000080);
+}
+
+static void setup_scc3_ioports(void)
+{
+ immap_t *immap = (immap_t *) IMAP_ADDR;
+ unsigned long *bcsr_io;
+
+ bcsr_io = ioremap(BCSR0, sizeof(unsigned long) * 5);
+ /* Enable the PHY.
+ */
+ out_be32((volatile void __iomem *)(bcsr_io + 4),
+ (in_be32((volatile void __iomem *)(bcsr_io + 4)) |
+ BCSR4_ETH10_RST));
+
+ /* Configure port A pins for Txd and Rxd.
+ */
+ setbits16(immap->im_ioport.iop_papar, PA_ENET_RXD | PA_ENET_TXD);
+ clrbits16(immap->im_ioport.iop_padir, PA_ENET_RXD | PA_ENET_TXD);
+
+ /* Configure port C pins to enable CLSN and RENA.
+ */
+ clrbits16(immap->im_ioport.iop_pcpar, PC_ENET_CLSN | PC_ENET_RENA);
+ clrbits16(immap->im_ioport.iop_pcdir, PC_ENET_CLSN | PC_ENET_RENA);
+ setbits16(immap->im_ioport.iop_pcso, PC_ENET_CLSN | PC_ENET_RENA);
+
+ /* Configure port E for TCLK and RCLK.
+ */
+ setbits32(immap->im_cpm.cp_pepar, PE_ENET_TCLK | PE_ENET_RCLK);
+ clrbits32(immap->im_cpm.cp_pepar, PE_ENET_TENA);
+ clrbits32(immap->im_cpm.cp_pedir,
+ PE_ENET_TCLK | PE_ENET_RCLK | PE_ENET_TENA);
+ clrbits32(immap->im_cpm.cp_peso, PE_ENET_TCLK | PE_ENET_RCLK);
+ setbits32(immap->im_cpm.cp_peso, PE_ENET_TENA);
+
+ /* Configure Serial Interface clock routing.
+ * First, clear all SCC bits to zero, then set the ones we want.
+ */
+ clrbits32(immap->im_cpm.cp_sicr, SICR_ENET_MASK);
+ setbits32(immap->im_cpm.cp_sicr, SICR_ENET_CLKRT);
+
+ /* Disable Rx and Tx. SMC1 sshould be stopped if SCC3 eternet are used.
+ */
+ immap->im_cpm.cp_smc[0].smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
+ /* On the MPC885ADS SCC ethernet PHY is initialized in the full duplex mode
+ * by H/W setting after reset. SCC ethernet controller support only half duplex.
+ * This discrepancy of modes causes a lot of carrier lost errors.
+ */
+
+ /* In the original SCC enet driver the following code is placed at the end of the initialization */
+ setbits32(immap->im_cpm.cp_pepar, PE_ENET_TENA);
+ clrbits32(immap->im_cpm.cp_pedir, PE_ENET_TENA);
+ setbits32(immap->im_cpm.cp_peso, PE_ENET_TENA);
+
+ out_be32(((volatile void __iomem *)(bcsr_io + 1)),
+ (in_be32((volatile void __iomem *)(bcsr_io + 1)) |
+ BCSR1_ETHEN));
+ iounmap(bcsr_io);
+
+}
+
+static void __init mpc885ads_fixup_enet_pdata(struct platform_device *pdev,
+ int fs_no)
+{
+ struct fs_platform_info *fpi = pdev->dev.platform_data;
+
+ volatile cpm8xx_t *cp;
+ bd_t *bd = (bd_t *) __res;
+ char *e;
+ int i;
+
+ /* Get pointer to Communication Processor */
+ cp = cpmp;
+ switch (fs_no) {
+ case fsid_fec1:
+ fpi = &mpc8xx_fec_pdata[fs_get_fec_index(fs_no)];
+ break;
+ case fsid_fec2:
+ fpi = &mpc8xx_fec_pdata[fs_get_fec_index(fs_no)];
+ break;
+ case fsid_scc3:
+ fpi = &mpc8xx_scc_pdata;
+ mpc885ads_scc_phy_init();
+ break;
+ default:
+ break;
+ }
+
+ pdev->dev.platform_data = fpi;
+ fpi->fs_no = fs_no;
+ e = (unsigned char *)&bd->bi_enetaddr;
+ for (i = 0; i < 6; i++)
+ fpi->macaddr[i] = *e++;
+
+ fpi->macaddr[5 - pdev->id]++;
+
+}
+
+static void __init mpc885ads_fixup_fec_enet_pdata(struct platform_device* pdev, int idx)
+{
+ int fs_no = fsid_fec1 + pdev->id -1;
+ mpc885ads_fixup_enet_pdata(pdev, fs_no);
+}
+
+static void __init mpc885ads_fixup_scc_enet_pdata(struct platform_device* pdev, int idx)
+{
+ int fs_no = fsid_scc1 + pdev->id -1;
+ mpc885ads_fixup_enet_pdata(pdev, fs_no);
+}
+
+/* SCC ethernet controller does not have MII management channel. FEC1 MII
+ * channel is used to communicate with the 10Mbit PHY.
+ */
+
+#define PHY_ADDR 0x2
+
+#define MII_ECNTRL_PINMUX 0x4
+#define FEC_ECNTRL_PINMUX 0x00000004
+#define FEC_RCNTRL_MII_MODE 0x00000004
+
+/* Make MII read/write commands.
+ */
+#define mk_mii_write(REG, VAL) (0x50020000 | (((REG) & 0x1f) << 18) | \
+ ((VAL) & 0xffff) | (PHY_ADDR << 23))
+
+void __init mpc885ads_scc_phy_init(void)
+{
+ volatile immap_t *immap;
+ volatile fec_t *fecp;
+ bd_t *bd;
+
+ bd = (bd_t *) __res;
+ immap = (immap_t *) IMAP_ADDR; /* pointer to internal registers */
+ fecp = &(immap->im_cpm.cp_fec);
+
+ /* Enable MII pins of the FEC1
+ */
+ immap->im_ioport.iop_pdpar |= 0x0080;
+ immap->im_ioport.iop_pddir &= ~0x0080;
+ /* Set MII speed to 2.5 MHz
+ */
+ fecp->fec_mii_speed =
+ ((((bd->bi_intfreq + 4999999) / 2500000) / 2) & 0x3F) << 1;
+
+ /* Enable FEC pin MUX
+ */
+ fecp->fec_ecntrl |= MII_ECNTRL_PINMUX;
+ fecp->fec_r_cntrl |= FEC_RCNTRL_MII_MODE;
+
+ fecp->fec_mii_data = mk_mii_write(MII_BMCR, BMCR_ISOLATE);
+ udelay(100);
+ fecp->fec_mii_data =
+ mk_mii_write(MII_ADVERTISE, ADVERTISE_10HALF | ADVERTISE_CSMA);
+ udelay(100);
+
+ /* Disable FEC MII settings
+ */
+ fecp->fec_ecntrl &= ~MII_ECNTRL_PINMUX;
+ fecp->fec_r_cntrl &= ~FEC_RCNTRL_MII_MODE;
+ fecp->fec_mii_speed = 0;
+}
+
+static int __init mpc885ads_platform_notify(struct device *dev)
+{
+ static struct {
+ const char *bus_id;
+ void (*rtn) (struct platform_device * pdev, int idx);
+ } dev_map[] = {
+ {"fsl-cpm-fec", mpc885ads_fixup_fec_enet_pdata},
+ {"fsl-cpm-scc", mpc885ads_fixup_scc_enet_pdata},
+ };
+ struct platform_device *pdev;
+ int i, j, idx;
+ const char *s;
+ if (dev && dev->bus_id)
+ for (i = 0; i < ARRAY_SIZE(dev_map); i++) {
+ idx = -1;
+
+ if ((s = strrchr(dev->bus_id, '.')) != NULL)
+ idx = (int)simple_strtol(s + 1, NULL, 10);
+ else
+ s = dev->bus_id;
+ j = s - dev->bus_id;
+ if (!strncmp(dev->bus_id, dev_map[i].bus_id, j)) {
+ pdev =
+ container_of(dev, struct platform_device,
+ dev);
+ dev_map[i].rtn(pdev, idx);
+ }
+ }
+ return 0;
+}
+
+int __init mpc885ads_init(void)
+{
+ printk(KERN_NOTICE "mpc885ads: Init\n");
+
+ mpc885_nonplatform_device_init();
+ platform_notify = mpc885ads_platform_notify;
+
+ identify_ppc_sys_by_name(BOARD_NAME);
+
+ /*take care of pin multiplexing*/
+#ifdef CONFIG_MPC885ADS_SECOND_ETH_SCC
+ ppc_sys_device_remove(MPC8xx_CPM_FEC2);
+#endif
+#ifdef CONFIG_MPC885ADS_SECOND_ETH_FEC2
+ ppc_sys_device_remove(MPC8xx_CPM_SCC3);
+#endif
+ /*Remove stuff does not utilized platform way*/
+ ppc_sys_device_remove(MPC8xx_CPM_SCC1);
+ ppc_sys_device_remove(MPC8xx_CPM_SCC1);
+ ppc_sys_device_remove(MPC8xx_CPM_SCC2);
+ ppc_sys_device_remove(MPC8xx_CPM_SCC4);
+ ppc_sys_device_remove(MPC8xx_CPM_SMC1);
+ ppc_sys_device_remove(MPC8xx_CPM_SMC2);
+
+ return 0;
+}
+
+arch_initcall(mpc885ads_init);
diff --git a/arch/ppc/syslib/Makefile b/arch/ppc/syslib/Makefile
--- a/arch/ppc/syslib/Makefile
+++ b/arch/ppc/syslib/Makefile
@@ -34,7 +34,8 @@ ifeq ($(CONFIG_40x),y)
obj-$(CONFIG_PCI) += indirect_pci.o pci_auto.o ppc405_pci.o
endif
endif
-obj-$(CONFIG_8xx) += m8xx_setup.o ppc8xx_pic.o $(wdt-mpc8xx-y)
+obj-$(CONFIG_8xx) += m8xx_setup.o ppc8xx_pic.o $(wdt-mpc8xx-y) \
+ ppc_sys.o mpc8xx_devices.o mpc8xx_sys.o
ifeq ($(CONFIG_8xx),y)
obj-$(CONFIG_PCI) += qspan_pci.o i8259.o
endif
diff --git a/arch/ppc/syslib/mpc8xx_devices.c b/arch/ppc/syslib/mpc8xx_devices.c
new file mode 100644
--- /dev/null
+++ b/arch/ppc/syslib/mpc8xx_devices.c
@@ -0,0 +1,274 @@
+/*
+ * arch/ppc/syslib/mpc8xx_devices.c
+ *
+ * MPC8xx Device descriptions
+ *
+ * Maintainer: Kumar Gala <kumar.gala@freescale.com>
+ *
+ * Copyright 2005 MontaVista Software, Inc. by Vitaly Bordug<vbordug@ru.mvista.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/device.h>
+#include <linux/serial_8250.h>
+#include <linux/fsl_devices.h>
+#include <linux/fs_enet_pd.h>
+#include <linux/mii.h>
+#include <asm/commproc.h>
+#include <asm/mpc8xx.h>
+#include <asm/irq.h>
+#include <asm/ppc_sys.h>
+
+/* access ports */
+#define setbits32(_addr, _v) out_be32(&(_addr), in_be32(&(_addr)) | (_v))
+#define clrbits32(_addr, _v) out_be32(&(_addr), in_be32(&(_addr)) & ~(_v))
+
+#define setbits16(_addr, _v) out_be16(&(_addr), in_be16(&(_addr)) | (_v))
+#define clrbits16(_addr, _v) out_be16(&(_addr), in_be16(&(_addr)) & ~(_v))
+
+#define MPC8xx_INT_FEC1 SIU_LEVEL1
+#define MPC8xx_INT_FEC2 SIU_LEVEL3
+
+#define MPC8xx_INT_SCC1 (CPM_IRQ_OFFSET + CPMVEC_SCC1)
+#define MPC8xx_INT_SCC2 (CPM_IRQ_OFFSET + CPMVEC_SCC2)
+#define MPC8xx_INT_SCC3 (CPM_IRQ_OFFSET + CPMVEC_SCC3)
+#define MPC8xx_INT_SCC4 (CPM_IRQ_OFFSET + CPMVEC_SCC4)
+#define MPC8xx_INT_SMC1 (CPM_IRQ_OFFSET + CPMVEC_SMC1)
+#define MPC8xx_INT_SMC2 (CPM_IRQ_OFFSET + CPMVEC_SMC2)
+
+/* Offset from IMMAP base address */
+#define MPC8xx_SCC1_OFFSET (0xa00)
+#define MPC8xx_SCC1_SIZE (0x18)
+#define MPC8xx_SCC2_OFFSET (0xa20)
+#define MPC8xx_SCC2_SIZE (0x18)
+#define MPC8xx_SCC3_OFFSET (0xa40)
+#define MPC8xx_SCC3_SIZE (0x18)
+#define MPC8xx_SCC4_OFFSET (0xa60)
+#define MPC8xx_SCC4_SIZE (0x18)
+#define MPC8xx_SMC1_OFFSET (0xa82)
+#define MPC8xx_SMC1_SIZE (0x0f)
+#define MPC8xx_SMC2_OFFSET (0xa92)
+#define MPC8xx_SMC2_SIZE (0x0d)
+#define MPC8xx_FEC1_OFFSET (0xe00)
+#define MPC8xx_FEC1_SIZE (0x88)
+#define MPC8xx_FEC2_OFFSET (0x1e00)
+#define MPC8xx_FEC2_SIZE (0x88)
+
+#define MPC8xx_DPARAM_SCC1_OFFSET (0x3C00)
+#define MPC8xx_DPARAM_SCC1_SIZE (0x80)
+#define MPC8xx_DPARAM_SCC2_OFFSET (0x3D00)
+#define MPC8xx_DPARAM_SCC2_SIZE (0x80)
+#define MPC8xx_DPARAM_SCC3_OFFSET (0x3E00)
+#define MPC8xx_DPARAM_SCC3_SIZE (0x80)
+#define MPC8xx_DPARAM_SCC4_OFFSET (0x3F00)
+#define MPC8xx_DPARAM_SCC4_SIZE (0x80)
+#define MPC8xx_DPARAM_SMC1_OFFSET (0x3E80)
+#define MPC8xx_DPARAM_SMC1_SIZE (0x40)
+#define MPC8xx_DPARAM_SMC2_OFFSET (0x3F80)
+#define MPC8xx_DPARAM_SMC2_SIZE (0x40)
+
+/* We use offsets for IORESOURCE_MEM to do not set dependences at compile time.
+ * They will get fixed up by mach_mpc8xx_fixup
+ */
+
+struct platform_device ppc_sys_platform_devices[] = {
+ [MPC8xx_CPM_FEC1] = {
+ .name = "fsl-cpm-fec",
+ .id = 1,
+ .num_resources = 2,
+ .resource = (struct resource[]) {
+ {
+ .name = "regs",
+ .start = MPC8xx_FEC1_OFFSET,
+ .end = MPC8xx_FEC1_OFFSET + MPC8xx_FEC1_SIZE,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .name = "interrupt",
+ .start = MPC8xx_INT_FEC1,
+ .end = MPC8xx_INT_FEC1,
+ .flags = IORESOURCE_IRQ,
+ },
+ },
+ },
+ [MPC8xx_CPM_FEC2] = {
+ .name = "fsl-cpm-fec",
+ .id = 2,
+ .num_resources = 2,
+ .resource = (struct resource[]) {
+ {
+ .name = "regs",
+ .start = MPC8xx_FEC2_OFFSET,
+ .end = MPC8xx_FEC2_OFFSET + MPC8xx_FEC2_SIZE,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .name = "interrupt",
+ .start = MPC8xx_INT_FEC2,
+ .end = MPC8xx_INT_FEC2,
+ .flags = IORESOURCE_IRQ,
+ },
+ },
+ },
+ [MPC8xx_CPM_SCC1] = {
+ .name = "fsl-cpm-scc",
+ .id = 1,
+ .num_resources = 3,
+ .resource = (struct resource[]) {
+ {
+ .name = "regs",
+ .start = MPC8xx_SCC1_OFFSET,
+ .end = MPC8xx_SCC1_OFFSET + MPC8xx_SCC1_SIZE,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .name = "pram",
+ .start = MPC8xx_DPARAM_SCC1_OFFSET,
+ .end = MPC8xx_DPARAM_SCC1_OFFSET + MPC8xx_DPARAM_SCC1_SIZE,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .name = "interrupt",
+ .start = MPC8xx_INT_SCC1,
+ .end = MPC8xx_INT_SCC1,
+ .flags = IORESOURCE_IRQ,
+ },
+ },
+ },
+ [MPC8xx_CPM_SCC2] = {
+ .name = "fsl-cpm-scc",
+ .id = 2,
+ .num_resources = 3,
+ .resource = (struct resource[]) {
+ {
+ .name = "regs",
+ .start = MPC8xx_SCC2_OFFSET,
+ .end = MPC8xx_SCC2_OFFSET + MPC8xx_SCC2_SIZE,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .name = "pram",
+ .start = MPC8xx_DPARAM_SCC2_OFFSET,
+ .end = MPC8xx_DPARAM_SCC2_OFFSET + MPC8xx_DPARAM_SCC2_SIZE,
+ .flags = IORESOURCE_MEM,
+ },
+
+ {
+ .name = "interrupt",
+ .start = MPC8xx_INT_SCC2,
+ .end = MPC8xx_INT_SCC2,
+ .flags = IORESOURCE_IRQ,
+ },
+ },
+ },
+ [MPC8xx_CPM_SCC3] = {
+ .name = "fsl-cpm-scc",
+ .id = 3,
+ .num_resources = 3,
+ .resource = (struct resource[]) {
+ {
+ .name = "regs",
+ .start = MPC8xx_SCC3_OFFSET,
+ .end = MPC8xx_SCC3_OFFSET + MPC8xx_SCC3_SIZE,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .name = "pram",
+ .start = MPC8xx_DPARAM_SCC3_OFFSET,
+ .end = MPC8xx_DPARAM_SCC3_OFFSET + MPC8xx_DPARAM_SCC3_SIZE,
+ .flags = IORESOURCE_MEM,
+ },
+
+ {
+ .name = "interrupt",
+ .start = MPC8xx_INT_SCC3,
+ .end = MPC8xx_INT_SCC3,
+ .flags = IORESOURCE_IRQ,
+ },
+ },
+ },
+ [MPC8xx_CPM_SCC4] = {
+ .name = "fsl-cpm-scc",
+ .id = 4,
+ .num_resources = 3,
+ .resource = (struct resource[]) {
+ {
+ .name = "regs",
+ .start = MPC8xx_SCC4_OFFSET,
+ .end = MPC8xx_SCC3_OFFSET + MPC8xx_SCC1_SIZE,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .name = "pram",
+ .start = MPC8xx_DPARAM_SCC4_OFFSET,
+ .end = MPC8xx_DPARAM_SCC4_OFFSET + MPC8xx_DPARAM_SCC4_SIZE,
+ .flags = IORESOURCE_MEM,
+ },
+
+ {
+ .name = "interrupt",
+ .start = MPC8xx_INT_SCC4,
+ .end = MPC8xx_INT_SCC4,
+ .flags = IORESOURCE_IRQ,
+ },
+ },
+ },
+ [MPC8xx_CPM_SMC1] = {
+ .name = "fsl-cpm-smc",
+ .id = 1,
+ .num_resources = 2,
+ .resource = (struct resource[]) {
+ {
+ .name = "regs",
+ .start = MPC8xx_SMC1_OFFSET,
+ .end = MPC8xx_SCC3_OFFSET + MPC8xx_SMC1_SIZE,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .name = "interrupt",
+ .start = MPC8xx_INT_SMC1,
+ .end = MPC8xx_INT_SMC1,
+ .flags = IORESOURCE_IRQ,
+ },
+ },
+ },
+ [MPC8xx_CPM_SMC2] = {
+ .name = "fsl-cpm-smc",
+ .id = 2,
+ .num_resources = 2,
+ .resource = (struct resource[]) {
+ {
+ .name = "regs",
+ .start = MPC8xx_SMC2_OFFSET,
+ .end = MPC8xx_SMC2_OFFSET + MPC8xx_SMC2_SIZE,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .name = "interrupt",
+ .start = MPC8xx_INT_SMC2,
+ .end = MPC8xx_INT_SMC2,
+ .flags = IORESOURCE_IRQ,
+ },
+ },
+ },
+};
+
+static int __init mach_mpc8xx_fixup(struct platform_device *pdev)
+{
+ ppc_sys_fixup_mem_resource (pdev, IMAP_ADDR);
+ return 0;
+}
+
+static int __init mach_mpc8xx_init(void)
+{
+ ppc_sys_device_fixup = mach_mpc8xx_fixup;
+ return 0;
+}
+
+postcore_initcall(mach_mpc8xx_init);
diff --git a/arch/ppc/syslib/mpc8xx_sys.c b/arch/ppc/syslib/mpc8xx_sys.c
new file mode 100644
--- /dev/null
+++ b/arch/ppc/syslib/mpc8xx_sys.c
@@ -0,0 +1,61 @@
+/*
+ * arch/ppc/platforms/mpc8xx_sys.c
+ *
+ * MPC8xx System descriptions
+ *
+ * Maintainer: Kumar Gala <kumar.gala@freescale.com>
+ *
+ * Copyright 2005 MontaVista Software, Inc. by Vitaly Bordug <vbordug@ru.mvista.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/device.h>
+#include <asm/ppc_sys.h>
+
+struct ppc_sys_spec *cur_ppc_sys_spec;
+struct ppc_sys_spec ppc_sys_specs[] = {
+ {
+ .ppc_sys_name = "MPC86X",
+ .mask = 0xFFFFFFFF,
+ .value = 0x00000000,
+ .num_devices = 2,
+ .device_list = (enum ppc_sys_devices[])
+ {
+ MPC8xx_CPM_FEC1,
+ MPC8xx_CPM_SCC1,
+ MPC8xx_CPM_SCC2,
+ MPC8xx_CPM_SCC3,
+ MPC8xx_CPM_SCC4,
+ MPC8xx_CPM_SMC1,
+ MPC8xx_CPM_SMC2,
+ },
+ },
+ {
+ .ppc_sys_name = "MPC885",
+ .mask = 0xFFFFFFFF,
+ .value = 0x00000000,
+ .num_devices = 3,
+ .device_list = (enum ppc_sys_devices[])
+ {
+ MPC8xx_CPM_FEC1,
+ MPC8xx_CPM_FEC2,
+ MPC8xx_CPM_SCC1,
+ MPC8xx_CPM_SCC2,
+ MPC8xx_CPM_SCC3,
+ MPC8xx_CPM_SCC4,
+ MPC8xx_CPM_SMC1,
+ MPC8xx_CPM_SMC2,
+ },
+ },
+ { /* default match */
+ .ppc_sys_name = "",
+ .mask = 0x00000000,
+ .value = 0x00000000,
+ },
+};
diff --git a/include/asm-ppc/mpc8xx.h b/include/asm-ppc/mpc8xx.h
--- a/include/asm-ppc/mpc8xx.h
+++ b/include/asm-ppc/mpc8xx.h
@@ -101,6 +105,22 @@ extern unsigned char __res[];
struct pt_regs;
+enum ppc_sys_devices {
+ MPC8xx_CPM_FEC1,
+ MPC8xx_CPM_FEC2,
+ MPC8xx_CPM_I2C,
+ MPC8xx_CPM_SCC1,
+ MPC8xx_CPM_SCC2,
+ MPC8xx_CPM_SCC3,
+ MPC8xx_CPM_SCC4,
+ MPC8xx_CPM_SPI,
+ MPC8xx_CPM_MCC1,
+ MPC8xx_CPM_MCC2,
+ MPC8xx_CPM_SMC1,
+ MPC8xx_CPM_SMC2,
+ MPC8xx_CPM_USB,
+};
+
#endif /* !__ASSEMBLY__ */
#endif /* CONFIG_8xx */
#endif /* __CONFIG_8xx_DEFS */
diff --git a/include/asm-ppc/ppc_sys.h b/include/asm-ppc/ppc_sys.h
--- a/include/asm-ppc/ppc_sys.h
+++ b/include/asm-ppc/ppc_sys.h
@@ -25,6 +25,8 @@
#include <asm/mpc83xx.h>
#elif defined(CONFIG_85xx)
#include <asm/mpc85xx.h>
+#elif defined(CONFIG_8xx)
+#include <asm/mpc8xx.h>
#elif defined(CONFIG_PPC_MPC52xx)
#include <asm/mpc52xx.h>
#elif defined(CONFIG_MPC10X_BRIDGE)
^ permalink raw reply
* Re: [RFC][PATCH] [1/2] 8xx platform definitions
From: Vitaly Bordug @ 2005-08-19 13:14 UTC (permalink / raw)
To: Schaefer-Hutter, Peter; +Cc: linuxppc-embedded list
In-Reply-To: <8E342283C2100540AAC5D1030970547774A3D9@rcexc.racoms.loc>
Schaefer-Hutter, Peter wrote:
> Hello!
>
> The last hunk in this patch looks a bit strange to me:
>
>
>>--- /dev/null
>>+++ b/arch/ppc/syslib/mpc8xx_sys.c
>>
>> [ ... ]
>>
>>+ .mask = 0x00000000,
>>+ .value = 0x00000000,
>>+ },
>>+};
>>@@ -101,6 +105,22 @@ extern unsigned char __res[];
>>
>>struct pt_regs;
>>
>>+enum ppc_sys_devices {
>
>
> Seems a bit inbetween is missing...
>
It's OK, just the default match for the list.
--
Sincerely,
Vitaly
^ permalink raw reply
* [RFC][PATCH][2/2] 8xx board-specific platform setup for fs_enet
From: Vitaly Bordug @ 2005-08-19 13:12 UTC (permalink / raw)
To: Kumar Gala; +Cc: Schaefer-Hutter, Peter, linuxppc-embedded list
[-- Attachment #1: Type: text/plain, Size: 199 bytes --]
This is board-specific platform setup for MPC885ADS evaluation board for
the upcoming combined Freescale Ethernet driver.
Signed-off-by: Vitaly Bordug <vbordug@ru.mvista.com>
--
Sincerely,
Vitaly
[-- Attachment #2: 8xx_platform_bsp.patch --]
[-- Type: text/x-patch, Size: 13354 bytes --]
diff --git a/arch/ppc/Kconfig b/arch/ppc/Kconfig
--- a/arch/ppc/Kconfig
+++ b/arch/ppc/Kconfig
@@ -527,6 +527,42 @@ config WINCEPT
endchoice
+menu "Freescale Ethernet driver platform-specific options"
+ depends on FS_ENET
+
+ config MPC8xx_SECOND_ETH
+ bool "Second Ethernet channel"
+ depends on (MPC885ADS || MPC86xADS)
+ default y
+ help
+ This enables support for second Ethernet on MPC885ADS and MPC86xADS boards.
+ The latter will use SCC1, for 885ADS you can select it below.
+
+ choice
+ prompt "Second Ethernet channel"
+ depends on MPC8xx_SECOND_ETH
+ default MPC885ADS_SECOND_ETH_FEC2
+
+ config MPC885ADS_SECOND_ETH_FEC2
+ bool "FEC2"
+ help
+ Enable FEC2 to serve as 2-nd Ethernet channel. Note that SMC2
+ (often 2-nd UART) will not work if this is enabled.
+
+ config MPC885ADS_SECOND_ETH_SCC
+ bool "SCC3"
+ help
+ Enable SCC3 to serve as 2-nd Ethernet channel. Note that SMC2
+ (often 1-nd UART) will not work if this is enabled.
+
+ endchoice
+
+ config MPC885ADS_SCC_ENET_FIXED
+ depends on MPC885ADS_SECOND_ETH_SCC
+ default n
+ bool "Use fixed MII-less mode for SCC Ethernet"
+endmenu
+
choice
prompt "Machine Type"
depends on 6xx || POWER3 || POWER4
diff --git a/arch/ppc/platforms/Makefile b/arch/ppc/platforms/Makefile
--- a/arch/ppc/platforms/Makefile
+++ b/arch/ppc/platforms/Makefile
@@ -46,6 +46,7 @@ obj-$(CONFIG_SANDPOINT) += sandpoint.o
obj-$(CONFIG_SBC82xx) += sbc82xx.o
obj-$(CONFIG_SPRUCE) += spruce.o
obj-$(CONFIG_LITE5200) += lite5200.o
+obj-$(CONFIG_MPC885ADS) += mpc885ads_setup.o
ifeq ($(CONFIG_SMP),y)
obj-$(CONFIG_PPC_PMAC) += pmac_smp.o
diff --git a/arch/ppc/platforms/mpc885ads.h b/arch/ppc/platforms/mpc885ads.h
--- a/arch/ppc/platforms/mpc885ads.h
+++ b/arch/ppc/platforms/mpc885ads.h
@@ -88,5 +88,7 @@
#define SICR_ENET_MASK ((uint)0x00ff0000)
#define SICR_ENET_CLKRT ((uint)0x002c0000)
+#define BOARD_NAME "MPC885"
+
#endif /* __ASM_MPC885ADS_H__ */
#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/mpc885ads_setup.c b/arch/ppc/platforms/mpc885ads_setup.c
new file mode 100644
--- /dev/null
+++ b/arch/ppc/platforms/mpc885ads_setup.c
@@ -0,0 +1,403 @@
+/*arch/ppc/platforms/mpc885ads-setup.c
+ *
+ * Platform setup for the Freescale mpc885ads board
+ *
+ * Vitaly Bordug <vbordug@ru.mvista.com>
+ *
+ * Copyright 2005 MontaVista Software Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/param.h>
+#include <linux/string.h>
+#include <linux/ioport.h>
+#include <linux/device.h>
+
+#include <linux/fs_enet_pd.h>
+#include <linux/mii.h>
+
+#include <asm/delay.h>
+#include <asm/io.h>
+#include <asm/machdep.h>
+#include <asm/page.h>
+#include <asm/processor.h>
+#include <asm/system.h>
+#include <asm/time.h>
+#include <asm/ppcboot.h>
+#include <asm/8xx_immap.h>
+#include <asm/commproc.h>
+#include <asm/ppc_sys.h>
+
+extern unsigned char __res[];
+
+/* access ports */
+#define setbits32(_addr, _v) out_be32(&(_addr), in_be32(&(_addr)) | (_v))
+#define clrbits32(_addr, _v) out_be32(&(_addr), in_be32(&(_addr)) & ~(_v))
+
+#define setbits16(_addr, _v) out_be16(&(_addr), in_be16(&(_addr)) | (_v))
+#define clrbits16(_addr, _v) out_be16(&(_addr), in_be16(&(_addr)) & ~(_v))
+
+void __init mpc885ads_scc_phy_init(void);
+static void setup_fec1_ioports(void);
+static void setup_fec2_ioports(void);
+static void setup_scc3_ioports(void);
+
+
+static struct fs_mii_bus_info fec_mii_bus_info = {
+ .method = fsmii_fec,
+ .id = 0,
+};
+
+static struct fs_mii_bus_info scc_mii_bus_info = {
+#ifdef CONFIG_MPC885ADS_SCC_ENET_FIXED
+ .method = fsmii_fixed,
+#else
+ .method = fsmii_fec,
+#endif
+
+ .id = 0,
+};
+
+static struct fs_platform_info mpc8xx_fec_pdata[] = {
+ {
+ .rx_ring = 128,
+ .tx_ring = 16,
+ .rx_copybreak = 240,
+
+ .use_napi = 1,
+ .napi_weight = 17,
+ .phy_irq = SIU_IRQ7,
+ .phy_addr = 0,
+ .bus_info = &fec_mii_bus_info,
+ .init_ioports = &setup_fec1_ioports,
+ }, {
+ .rx_ring = 128,
+ .tx_ring = 16,
+ .rx_copybreak = 240,
+
+ .use_napi = 1,
+ .napi_weight = 17,
+ .phy_irq = SIU_IRQ7,
+ .phy_addr = 1,
+
+ .bus_info = &fec_mii_bus_info,
+ .init_ioports = &setup_fec2_ioports,
+ }
+};
+
+static struct fs_platform_info mpc8xx_scc_pdata = {
+ .rx_ring = 64,
+ .tx_ring = 8,
+ .rx_copybreak = 240,
+
+ .use_napi = 1,
+ .napi_weight = 17,
+#ifdef CONFIG_MPC885ADS_SCC_ENET_FIXED
+ .phy_irq = -1,
+ .phy_addr = -1,
+#else
+ .phy_irq = SIU_IRQ7,
+ .phy_addr = 2,
+#endif
+ .bus_info = &scc_mii_bus_info,
+ .init_ioports = &setup_scc3_ioports,
+
+};
+
+static void __init mpc885_nonplatform_device_init(void)
+{
+ immap_t *immap = (immap_t *) IMAP_ADDR;
+ volatile cpm8xx_t *cp = cpmp;
+ unsigned long *bcsr_io;
+
+ bcsr_io = ioremap(BCSR1, sizeof(unsigned long));
+#ifdef CONFIG_SERIAL_CPM_SMC1
+ cp->cp_simode &= ~(0xe0000000 >> 17); /* brg1 */
+ out_be32((volatile unsigned __iomem *)bcsr_io,
+ in_be32((volatile unsigned __iomem *)bcsr_io) &
+ ~BCSR1_RS232EN_1);
+#else
+ out_be32((volatile unsigned __iomem *)bcsr_io,
+ in_be32((volatile unsigned __iomem *)bcsr_io) |
+ BCSR1_RS232EN_1);
+ cp->cp_smc[0].smc_smcmr = 0;
+ cp->cp_smc[0].smc_smce = 0;
+#endif
+
+#ifdef CONFIG_SERIAL_CPM_SMC2
+ cp->cp_simode &= ~(0xe0000000 >> 1);
+ cp->cp_simode |= (0x20000000 >> 1); /* brg2 */
+ out_be32((volatile unsigned __iomem *)bcsr_io,
+ in_be32((volatile unsigned __iomem *)bcsr_io) &
+ ~BCSR1_RS232EN_2);
+#else
+ out_be32((volatile unsigned __iomem *)bcsr_io,
+ in_be32((volatile unsigned __iomem *)bcsr_io) |
+ BCSR1_RS232EN_2);
+ cp->cp_smc[1].smc_smcmr = 0;
+ cp->cp_smc[1].smc_smce = 0;
+#endif
+ iounmap(bcsr_io);
+
+#ifdef CONFIG_FS_ENET
+ /* use MDC for MII (common) */
+ setbits16(immap->im_ioport.iop_pdpar, 0x0080);
+ clrbits16(immap->im_ioport.iop_pddir, 0x0080);
+#endif
+}
+
+static void setup_fec1_ioports(void)
+{
+ immap_t *immap = (immap_t *) IMAP_ADDR;
+
+ /* configure FEC1 pins */
+ setbits16(immap->im_ioport.iop_papar, 0xf830);
+ setbits16(immap->im_ioport.iop_padir, 0x0830);
+ clrbits16(immap->im_ioport.iop_padir, 0xf000);
+ setbits32(immap->im_cpm.cp_pbpar, 0x00001001);
+
+ clrbits32(immap->im_cpm.cp_pbdir, 0x00001001);
+ setbits16(immap->im_ioport.iop_pcpar, 0x000c);
+ clrbits16(immap->im_ioport.iop_pcdir, 0x000c);
+ setbits32(immap->im_cpm.cp_pepar, 0x00000003);
+
+ setbits32(immap->im_cpm.cp_pedir, 0x00000003);
+ clrbits32(immap->im_cpm.cp_peso, 0x00000003);
+ clrbits32(immap->im_cpm.cp_cptr, 0x00000100);
+}
+
+static void setup_fec2_ioports(void)
+{
+ immap_t *immap = (immap_t *) IMAP_ADDR;
+
+ /* configure FEC2 pins */
+ setbits32(immap->im_cpm.cp_pepar, 0x0003fffc);
+ setbits32(immap->im_cpm.cp_pedir, 0x0003fffc);
+ setbits32(immap->im_cpm.cp_peso, 0x00037800);
+ clrbits32(immap->im_cpm.cp_peso, 0x000087fc);
+ clrbits32(immap->im_cpm.cp_cptr, 0x00000080);
+}
+
+static void setup_scc3_ioports(void)
+{
+ immap_t *immap = (immap_t *) IMAP_ADDR;
+ unsigned long *bcsr_io;
+
+ bcsr_io = ioremap(BCSR0, sizeof(unsigned long) * 5);
+ /* Enable the PHY.
+ */
+ out_be32((volatile void __iomem *)(bcsr_io + 4),
+ (in_be32((volatile void __iomem *)(bcsr_io + 4)) |
+ BCSR4_ETH10_RST));
+
+ /* Configure port A pins for Txd and Rxd.
+ */
+ setbits16(immap->im_ioport.iop_papar, PA_ENET_RXD | PA_ENET_TXD);
+ clrbits16(immap->im_ioport.iop_padir, PA_ENET_RXD | PA_ENET_TXD);
+
+ /* Configure port C pins to enable CLSN and RENA.
+ */
+ clrbits16(immap->im_ioport.iop_pcpar, PC_ENET_CLSN | PC_ENET_RENA);
+ clrbits16(immap->im_ioport.iop_pcdir, PC_ENET_CLSN | PC_ENET_RENA);
+ setbits16(immap->im_ioport.iop_pcso, PC_ENET_CLSN | PC_ENET_RENA);
+
+ /* Configure port E for TCLK and RCLK.
+ */
+ setbits32(immap->im_cpm.cp_pepar, PE_ENET_TCLK | PE_ENET_RCLK);
+ clrbits32(immap->im_cpm.cp_pepar, PE_ENET_TENA);
+ clrbits32(immap->im_cpm.cp_pedir,
+ PE_ENET_TCLK | PE_ENET_RCLK | PE_ENET_TENA);
+ clrbits32(immap->im_cpm.cp_peso, PE_ENET_TCLK | PE_ENET_RCLK);
+ setbits32(immap->im_cpm.cp_peso, PE_ENET_TENA);
+
+ /* Configure Serial Interface clock routing.
+ * First, clear all SCC bits to zero, then set the ones we want.
+ */
+ clrbits32(immap->im_cpm.cp_sicr, SICR_ENET_MASK);
+ setbits32(immap->im_cpm.cp_sicr, SICR_ENET_CLKRT);
+
+ /* Disable Rx and Tx. SMC1 sshould be stopped if SCC3 eternet are used.
+ */
+ immap->im_cpm.cp_smc[0].smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
+ /* On the MPC885ADS SCC ethernet PHY is initialized in the full duplex mode
+ * by H/W setting after reset. SCC ethernet controller support only half duplex.
+ * This discrepancy of modes causes a lot of carrier lost errors.
+ */
+
+ /* In the original SCC enet driver the following code is placed at the end of the initialization */
+ setbits32(immap->im_cpm.cp_pepar, PE_ENET_TENA);
+ clrbits32(immap->im_cpm.cp_pedir, PE_ENET_TENA);
+ setbits32(immap->im_cpm.cp_peso, PE_ENET_TENA);
+
+ out_be32(((volatile void __iomem *)(bcsr_io + 1)),
+ (in_be32((volatile void __iomem *)(bcsr_io + 1)) |
+ BCSR1_ETHEN));
+ iounmap(bcsr_io);
+
+}
+
+static void __init mpc885ads_fixup_enet_pdata(struct platform_device *pdev,
+ int fs_no)
+{
+ struct fs_platform_info *fpi = pdev->dev.platform_data;
+
+ volatile cpm8xx_t *cp;
+ bd_t *bd = (bd_t *) __res;
+ char *e;
+ int i;
+
+ /* Get pointer to Communication Processor */
+ cp = cpmp;
+ switch (fs_no) {
+ case fsid_fec1:
+ fpi = &mpc8xx_fec_pdata[fs_get_fec_index(fs_no)];
+ break;
+ case fsid_fec2:
+ fpi = &mpc8xx_fec_pdata[fs_get_fec_index(fs_no)];
+ break;
+ case fsid_scc3:
+ fpi = &mpc8xx_scc_pdata;
+ mpc885ads_scc_phy_init();
+ break;
+ default:
+ break;
+ }
+
+ pdev->dev.platform_data = fpi;
+ fpi->fs_no = fs_no;
+ e = (unsigned char *)&bd->bi_enetaddr;
+ for (i = 0; i < 6; i++)
+ fpi->macaddr[i] = *e++;
+
+ fpi->macaddr[5 - pdev->id]++;
+
+}
+
+static void __init mpc885ads_fixup_fec_enet_pdata(struct platform_device* pdev, int idx)
+{
+ int fs_no = fsid_fec1 + pdev->id -1;
+ mpc885ads_fixup_enet_pdata(pdev, fs_no);
+}
+
+static void __init mpc885ads_fixup_scc_enet_pdata(struct platform_device* pdev, int idx)
+{
+ int fs_no = fsid_scc1 + pdev->id -1;
+ mpc885ads_fixup_enet_pdata(pdev, fs_no);
+}
+
+/* SCC ethernet controller does not have MII management channel. FEC1 MII
+ * channel is used to communicate with the 10Mbit PHY.
+ */
+
+#define PHY_ADDR 0x2
+
+#define MII_ECNTRL_PINMUX 0x4
+#define FEC_ECNTRL_PINMUX 0x00000004
+#define FEC_RCNTRL_MII_MODE 0x00000004
+
+/* Make MII read/write commands.
+ */
+#define mk_mii_write(REG, VAL) (0x50020000 | (((REG) & 0x1f) << 18) | \
+ ((VAL) & 0xffff) | (PHY_ADDR << 23))
+
+void __init mpc885ads_scc_phy_init(void)
+{
+ volatile immap_t *immap;
+ volatile fec_t *fecp;
+ bd_t *bd;
+
+ bd = (bd_t *) __res;
+ immap = (immap_t *) IMAP_ADDR; /* pointer to internal registers */
+ fecp = &(immap->im_cpm.cp_fec);
+
+ /* Enable MII pins of the FEC1
+ */
+ immap->im_ioport.iop_pdpar |= 0x0080;
+ immap->im_ioport.iop_pddir &= ~0x0080;
+ /* Set MII speed to 2.5 MHz
+ */
+ fecp->fec_mii_speed =
+ ((((bd->bi_intfreq + 4999999) / 2500000) / 2) & 0x3F) << 1;
+
+ /* Enable FEC pin MUX
+ */
+ fecp->fec_ecntrl |= MII_ECNTRL_PINMUX;
+ fecp->fec_r_cntrl |= FEC_RCNTRL_MII_MODE;
+
+ fecp->fec_mii_data = mk_mii_write(MII_BMCR, BMCR_ISOLATE);
+ udelay(100);
+ fecp->fec_mii_data =
+ mk_mii_write(MII_ADVERTISE, ADVERTISE_10HALF | ADVERTISE_CSMA);
+ udelay(100);
+
+ /* Disable FEC MII settings
+ */
+ fecp->fec_ecntrl &= ~MII_ECNTRL_PINMUX;
+ fecp->fec_r_cntrl &= ~FEC_RCNTRL_MII_MODE;
+ fecp->fec_mii_speed = 0;
+}
+
+static int __init mpc885ads_platform_notify(struct device *dev)
+{
+ static struct {
+ const char *bus_id;
+ void (*rtn) (struct platform_device * pdev, int idx);
+ } dev_map[] = {
+ {"fsl-cpm-fec", mpc885ads_fixup_fec_enet_pdata},
+ {"fsl-cpm-scc", mpc885ads_fixup_scc_enet_pdata},
+ };
+ struct platform_device *pdev;
+ int i, j, idx;
+ const char *s;
+ if (dev && dev->bus_id)
+ for (i = 0; i < ARRAY_SIZE(dev_map); i++) {
+ idx = -1;
+
+ if ((s = strrchr(dev->bus_id, '.')) != NULL)
+ idx = (int)simple_strtol(s + 1, NULL, 10);
+ else
+ s = dev->bus_id;
+ j = s - dev->bus_id;
+ if (!strncmp(dev->bus_id, dev_map[i].bus_id, j)) {
+ pdev =
+ container_of(dev, struct platform_device,
+ dev);
+ dev_map[i].rtn(pdev, idx);
+ }
+ }
+ return 0;
+}
+
+int __init mpc885ads_init(void)
+{
+ printk(KERN_NOTICE "mpc885ads: Init\n");
+
+ mpc885_nonplatform_device_init();
+ platform_notify = mpc885ads_platform_notify;
+
+ identify_ppc_sys_by_name(BOARD_NAME);
+
+ /*take care of pin multiplexing*/
+#ifdef CONFIG_MPC885ADS_SECOND_ETH_SCC
+ ppc_sys_device_remove(MPC8xx_CPM_FEC2);
+#endif
+#ifdef CONFIG_MPC885ADS_SECOND_ETH_FEC2
+ ppc_sys_device_remove(MPC8xx_CPM_SCC3);
+#endif
+ /*Remove stuff does not utilized platform way*/
+ ppc_sys_device_remove(MPC8xx_CPM_SCC1);
+ ppc_sys_device_remove(MPC8xx_CPM_SCC2);
+ ppc_sys_device_remove(MPC8xx_CPM_SCC4);
+ ppc_sys_device_remove(MPC8xx_CPM_SMC1);
+ ppc_sys_device_remove(MPC8xx_CPM_SMC2);
+
+ return 0;
+}
+
+arch_initcall(mpc885ads_init);
^ permalink raw reply
* RE: [RFC][PATCH] [1/2] 8xx platform definitions
From: Schaefer-Hutter, Peter @ 2005-08-19 13:11 UTC (permalink / raw)
To: Vitaly Bordug, Kumar Gala; +Cc: linuxppc-embedded list
Hello!
The last hunk in this patch looks a bit strange to me:
> --- /dev/null
> +++ b/arch/ppc/syslib/mpc8xx_sys.c
>
> [ ... ]
>
> + .mask =3D 0x00000000,
> + .value =3D 0x00000000,
> + },
> +};
> @@ -101,6 +105,22 @@ extern unsigned char __res[];
>
> struct pt_regs;
>
> +enum ppc_sys_devices {
Seems a bit inbetween is missing...
Best regards,
Peter
-----Original Message-----
From: Vitaly Bordug [mailto:vbordug@ru.mvista.com]=20
Sent: Friday, August 19, 2005 2:44 PM
To: Kumar Gala
Cc: linuxppc-embedded list; Schaefer-Hutter, Peter
Subject: [RFC][PATCH] [1/2] 8xx platform definitions
This is preliminary version of 8xx platform definitions. Currently sys=20
section contains only MPC885 and MPC866. Working example of=20
board-specific setup will follow.
Signed-off-by: Vitaly Bordug <vbordug@ru.mvista.com>
--=20
Sincerely,
Vitaly
^ permalink raw reply
* [RFC][PATCH] [1/2] 8xx platform definitions
From: Vitaly Bordug @ 2005-08-19 12:44 UTC (permalink / raw)
To: Kumar Gala; +Cc: Schaefer-Hutter, Peter, linuxppc-embedded list
[-- Attachment #1: Type: text/plain, Size: 244 bytes --]
This is preliminary version of 8xx platform definitions. Currently sys
section contains only MPC885 and MPC866. Working example of
board-specific setup will follow.
Signed-off-by: Vitaly Bordug <vbordug@ru.mvista.com>
--
Sincerely,
Vitaly
[-- Attachment #2: 8xx_platform_devices.patch --]
[-- Type: text/x-patch, Size: 10822 bytes --]
8xx platform stuff
---
commit e4c1c9d34899352dd332c63dea090e8ba9bbe757
tree 1b6484c6cac83d6e851854fe5c73357e014f2819
parent 7e49f04f36830c7d1ee442447e46dba3a0a1b58d
author Vitaly Bordug <vbordug@ru.mvista.com> Fri, 19 Aug 2005 16:37:50 +0400
committer Vitaly Bordug <vbordug@ru.mvista.com> Fri, 19 Aug 2005 16:37:50 +0400
arch/ppc/syslib/Makefile | 3
arch/ppc/syslib/mpc8xx_devices.c | 274 ++++++++++++++++++++++++++++++++++++++
arch/ppc/syslib/mpc8xx_sys.c | 61 ++++++++
include/asm-ppc/mpc8xx.h | 20 +++
include/asm-ppc/ppc_sys.h | 2
5 files changed, 359 insertions(+), 1 deletions(-)
diff --git a/arch/ppc/syslib/Makefile b/arch/ppc/syslib/Makefile
--- a/arch/ppc/syslib/Makefile
+++ b/arch/ppc/syslib/Makefile
@@ -34,7 +34,8 @@ ifeq ($(CONFIG_40x),y)
obj-$(CONFIG_PCI) += indirect_pci.o pci_auto.o ppc405_pci.o
endif
endif
-obj-$(CONFIG_8xx) += m8xx_setup.o ppc8xx_pic.o $(wdt-mpc8xx-y)
+obj-$(CONFIG_8xx) += m8xx_setup.o ppc8xx_pic.o $(wdt-mpc8xx-y) \
+ ppc_sys.o mpc8xx_devices.o mpc8xx_sys.o
ifeq ($(CONFIG_8xx),y)
obj-$(CONFIG_PCI) += qspan_pci.o i8259.o
endif
diff --git a/arch/ppc/syslib/mpc8xx_devices.c b/arch/ppc/syslib/mpc8xx_devices.c
new file mode 100644
--- /dev/null
+++ b/arch/ppc/syslib/mpc8xx_devices.c
@@ -0,0 +1,274 @@
+/*
+ * arch/ppc/syslib/mpc8xx_devices.c
+ *
+ * MPC8xx Device descriptions
+ *
+ * Maintainer: Kumar Gala <kumar.gala@freescale.com>
+ *
+ * Copyright 2005 MontaVista Software, Inc. by Vitaly Bordug<vbordug@ru.mvista.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/device.h>
+#include <linux/serial_8250.h>
+#include <linux/fsl_devices.h>
+#include <linux/fs_enet_pd.h>
+#include <linux/mii.h>
+#include <asm/commproc.h>
+#include <asm/mpc8xx.h>
+#include <asm/irq.h>
+#include <asm/ppc_sys.h>
+
+/* access ports */
+#define setbits32(_addr, _v) out_be32(&(_addr), in_be32(&(_addr)) | (_v))
+#define clrbits32(_addr, _v) out_be32(&(_addr), in_be32(&(_addr)) & ~(_v))
+
+#define setbits16(_addr, _v) out_be16(&(_addr), in_be16(&(_addr)) | (_v))
+#define clrbits16(_addr, _v) out_be16(&(_addr), in_be16(&(_addr)) & ~(_v))
+
+#define MPC8xx_INT_FEC1 SIU_LEVEL1
+#define MPC8xx_INT_FEC2 SIU_LEVEL3
+
+#define MPC8xx_INT_SCC1 (CPM_IRQ_OFFSET + CPMVEC_SCC1)
+#define MPC8xx_INT_SCC2 (CPM_IRQ_OFFSET + CPMVEC_SCC2)
+#define MPC8xx_INT_SCC3 (CPM_IRQ_OFFSET + CPMVEC_SCC3)
+#define MPC8xx_INT_SCC4 (CPM_IRQ_OFFSET + CPMVEC_SCC4)
+#define MPC8xx_INT_SMC1 (CPM_IRQ_OFFSET + CPMVEC_SMC1)
+#define MPC8xx_INT_SMC2 (CPM_IRQ_OFFSET + CPMVEC_SMC2)
+
+/* Offset from IMMAP base address */
+#define MPC8xx_SCC1_OFFSET (0xa00)
+#define MPC8xx_SCC1_SIZE (0x18)
+#define MPC8xx_SCC2_OFFSET (0xa20)
+#define MPC8xx_SCC2_SIZE (0x18)
+#define MPC8xx_SCC3_OFFSET (0xa40)
+#define MPC8xx_SCC3_SIZE (0x18)
+#define MPC8xx_SCC4_OFFSET (0xa60)
+#define MPC8xx_SCC4_SIZE (0x18)
+#define MPC8xx_SMC1_OFFSET (0xa82)
+#define MPC8xx_SMC1_SIZE (0x0f)
+#define MPC8xx_SMC2_OFFSET (0xa92)
+#define MPC8xx_SMC2_SIZE (0x0d)
+#define MPC8xx_FEC1_OFFSET (0xe00)
+#define MPC8xx_FEC1_SIZE (0x88)
+#define MPC8xx_FEC2_OFFSET (0x1e00)
+#define MPC8xx_FEC2_SIZE (0x88)
+
+#define MPC8xx_DPARAM_SCC1_OFFSET (0x3C00)
+#define MPC8xx_DPARAM_SCC1_SIZE (0x80)
+#define MPC8xx_DPARAM_SCC2_OFFSET (0x3D00)
+#define MPC8xx_DPARAM_SCC2_SIZE (0x80)
+#define MPC8xx_DPARAM_SCC3_OFFSET (0x3E00)
+#define MPC8xx_DPARAM_SCC3_SIZE (0x80)
+#define MPC8xx_DPARAM_SCC4_OFFSET (0x3F00)
+#define MPC8xx_DPARAM_SCC4_SIZE (0x80)
+#define MPC8xx_DPARAM_SMC1_OFFSET (0x3E80)
+#define MPC8xx_DPARAM_SMC1_SIZE (0x40)
+#define MPC8xx_DPARAM_SMC2_OFFSET (0x3F80)
+#define MPC8xx_DPARAM_SMC2_SIZE (0x40)
+
+/* We use offsets for IORESOURCE_MEM to do not set dependences at compile time.
+ * They will get fixed up by mach_mpc8xx_fixup
+ */
+
+struct platform_device ppc_sys_platform_devices[] = {
+ [MPC8xx_CPM_FEC1] = {
+ .name = "fsl-cpm-fec",
+ .id = 1,
+ .num_resources = 2,
+ .resource = (struct resource[]) {
+ {
+ .name = "regs",
+ .start = MPC8xx_FEC1_OFFSET,
+ .end = MPC8xx_FEC1_OFFSET + MPC8xx_FEC1_SIZE,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .name = "interrupt",
+ .start = MPC8xx_INT_FEC1,
+ .end = MPC8xx_INT_FEC1,
+ .flags = IORESOURCE_IRQ,
+ },
+ },
+ },
+ [MPC8xx_CPM_FEC2] = {
+ .name = "fsl-cpm-fec",
+ .id = 2,
+ .num_resources = 2,
+ .resource = (struct resource[]) {
+ {
+ .name = "regs",
+ .start = MPC8xx_FEC2_OFFSET,
+ .end = MPC8xx_FEC2_OFFSET + MPC8xx_FEC2_SIZE,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .name = "interrupt",
+ .start = MPC8xx_INT_FEC2,
+ .end = MPC8xx_INT_FEC2,
+ .flags = IORESOURCE_IRQ,
+ },
+ },
+ },
+ [MPC8xx_CPM_SCC1] = {
+ .name = "fsl-cpm-scc",
+ .id = 1,
+ .num_resources = 3,
+ .resource = (struct resource[]) {
+ {
+ .name = "regs",
+ .start = MPC8xx_SCC1_OFFSET,
+ .end = MPC8xx_SCC1_OFFSET + MPC8xx_SCC1_SIZE,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .name = "pram",
+ .start = MPC8xx_DPARAM_SCC1_OFFSET,
+ .end = MPC8xx_DPARAM_SCC1_OFFSET + MPC8xx_DPARAM_SCC1_SIZE,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .name = "interrupt",
+ .start = MPC8xx_INT_SCC1,
+ .end = MPC8xx_INT_SCC1,
+ .flags = IORESOURCE_IRQ,
+ },
+ },
+ },
+ [MPC8xx_CPM_SCC2] = {
+ .name = "fsl-cpm-scc",
+ .id = 2,
+ .num_resources = 3,
+ .resource = (struct resource[]) {
+ {
+ .name = "regs",
+ .start = MPC8xx_SCC2_OFFSET,
+ .end = MPC8xx_SCC2_OFFSET + MPC8xx_SCC2_SIZE,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .name = "pram",
+ .start = MPC8xx_DPARAM_SCC2_OFFSET,
+ .end = MPC8xx_DPARAM_SCC2_OFFSET + MPC8xx_DPARAM_SCC2_SIZE,
+ .flags = IORESOURCE_MEM,
+ },
+
+ {
+ .name = "interrupt",
+ .start = MPC8xx_INT_SCC2,
+ .end = MPC8xx_INT_SCC2,
+ .flags = IORESOURCE_IRQ,
+ },
+ },
+ },
+ [MPC8xx_CPM_SCC3] = {
+ .name = "fsl-cpm-scc",
+ .id = 3,
+ .num_resources = 3,
+ .resource = (struct resource[]) {
+ {
+ .name = "regs",
+ .start = MPC8xx_SCC3_OFFSET,
+ .end = MPC8xx_SCC3_OFFSET + MPC8xx_SCC3_SIZE,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .name = "pram",
+ .start = MPC8xx_DPARAM_SCC3_OFFSET,
+ .end = MPC8xx_DPARAM_SCC3_OFFSET + MPC8xx_DPARAM_SCC3_SIZE,
+ .flags = IORESOURCE_MEM,
+ },
+
+ {
+ .name = "interrupt",
+ .start = MPC8xx_INT_SCC3,
+ .end = MPC8xx_INT_SCC3,
+ .flags = IORESOURCE_IRQ,
+ },
+ },
+ },
+ [MPC8xx_CPM_SCC4] = {
+ .name = "fsl-cpm-scc",
+ .id = 4,
+ .num_resources = 3,
+ .resource = (struct resource[]) {
+ {
+ .name = "regs",
+ .start = MPC8xx_SCC4_OFFSET,
+ .end = MPC8xx_SCC3_OFFSET + MPC8xx_SCC1_SIZE,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .name = "pram",
+ .start = MPC8xx_DPARAM_SCC4_OFFSET,
+ .end = MPC8xx_DPARAM_SCC4_OFFSET + MPC8xx_DPARAM_SCC4_SIZE,
+ .flags = IORESOURCE_MEM,
+ },
+
+ {
+ .name = "interrupt",
+ .start = MPC8xx_INT_SCC4,
+ .end = MPC8xx_INT_SCC4,
+ .flags = IORESOURCE_IRQ,
+ },
+ },
+ },
+ [MPC8xx_CPM_SMC1] = {
+ .name = "fsl-cpm-smc",
+ .id = 1,
+ .num_resources = 2,
+ .resource = (struct resource[]) {
+ {
+ .name = "regs",
+ .start = MPC8xx_SMC1_OFFSET,
+ .end = MPC8xx_SCC3_OFFSET + MPC8xx_SMC1_SIZE,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .name = "interrupt",
+ .start = MPC8xx_INT_SMC1,
+ .end = MPC8xx_INT_SMC1,
+ .flags = IORESOURCE_IRQ,
+ },
+ },
+ },
+ [MPC8xx_CPM_SMC2] = {
+ .name = "fsl-cpm-smc",
+ .id = 2,
+ .num_resources = 2,
+ .resource = (struct resource[]) {
+ {
+ .name = "regs",
+ .start = MPC8xx_SMC2_OFFSET,
+ .end = MPC8xx_SMC2_OFFSET + MPC8xx_SMC2_SIZE,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .name = "interrupt",
+ .start = MPC8xx_INT_SMC2,
+ .end = MPC8xx_INT_SMC2,
+ .flags = IORESOURCE_IRQ,
+ },
+ },
+ },
+};
+
+static int __init mach_mpc8xx_fixup(struct platform_device *pdev)
+{
+ ppc_sys_fixup_mem_resource (pdev, IMAP_ADDR);
+ return 0;
+}
+
+static int __init mach_mpc8xx_init(void)
+{
+ ppc_sys_device_fixup = mach_mpc8xx_fixup;
+ return 0;
+}
+
+postcore_initcall(mach_mpc8xx_init);
diff --git a/arch/ppc/syslib/mpc8xx_sys.c b/arch/ppc/syslib/mpc8xx_sys.c
new file mode 100644
--- /dev/null
+++ b/arch/ppc/syslib/mpc8xx_sys.c
@@ -0,0 +1,61 @@
+/*
+ * arch/ppc/platforms/mpc8xx_sys.c
+ *
+ * MPC8xx System descriptions
+ *
+ * Maintainer: Kumar Gala <kumar.gala@freescale.com>
+ *
+ * Copyright 2005 MontaVista Software, Inc. by Vitaly Bordug <vbordug@ru.mvista.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/device.h>
+#include <asm/ppc_sys.h>
+
+struct ppc_sys_spec *cur_ppc_sys_spec;
+struct ppc_sys_spec ppc_sys_specs[] = {
+ {
+ .ppc_sys_name = "MPC86X",
+ .mask = 0xFFFFFFFF,
+ .value = 0x00000000,
+ .num_devices = 2,
+ .device_list = (enum ppc_sys_devices[])
+ {
+ MPC8xx_CPM_FEC1,
+ MPC8xx_CPM_SCC1,
+ MPC8xx_CPM_SCC2,
+ MPC8xx_CPM_SCC3,
+ MPC8xx_CPM_SCC4,
+ MPC8xx_CPM_SMC1,
+ MPC8xx_CPM_SMC2,
+ },
+ },
+ {
+ .ppc_sys_name = "MPC885",
+ .mask = 0xFFFFFFFF,
+ .value = 0x00000000,
+ .num_devices = 3,
+ .device_list = (enum ppc_sys_devices[])
+ {
+ MPC8xx_CPM_FEC1,
+ MPC8xx_CPM_FEC2,
+ MPC8xx_CPM_SCC1,
+ MPC8xx_CPM_SCC2,
+ MPC8xx_CPM_SCC3,
+ MPC8xx_CPM_SCC4,
+ MPC8xx_CPM_SMC1,
+ MPC8xx_CPM_SMC2,
+ },
+ },
+ { /* default match */
+ .ppc_sys_name = "",
+ .mask = 0x00000000,
+ .value = 0x00000000,
+ },
+};
@@ -101,6 +105,22 @@ extern unsigned char __res[];
struct pt_regs;
+enum ppc_sys_devices {
+ MPC8xx_CPM_FEC1,
+ MPC8xx_CPM_FEC2,
+ MPC8xx_CPM_I2C,
+ MPC8xx_CPM_SCC1,
+ MPC8xx_CPM_SCC2,
+ MPC8xx_CPM_SCC3,
+ MPC8xx_CPM_SCC4,
+ MPC8xx_CPM_SPI,
+ MPC8xx_CPM_MCC1,
+ MPC8xx_CPM_MCC2,
+ MPC8xx_CPM_SMC1,
+ MPC8xx_CPM_SMC2,
+ MPC8xx_CPM_USB,
+};
+
#endif /* !__ASSEMBLY__ */
#endif /* CONFIG_8xx */
#endif /* __CONFIG_8xx_DEFS */
diff --git a/include/asm-ppc/ppc_sys.h b/include/asm-ppc/ppc_sys.h
--- a/include/asm-ppc/ppc_sys.h
+++ b/include/asm-ppc/ppc_sys.h
@@ -25,6 +25,8 @@
#include <asm/mpc83xx.h>
#elif defined(CONFIG_85xx)
#include <asm/mpc85xx.h>
+#elif defined(CONFIG_8xx)
+#include <asm/mpc8xx.h>
#elif defined(CONFIG_PPC_MPC52xx)
#include <asm/mpc52xx.h>
#elif defined(CONFIG_MPC10X_BRIDGE)
^ permalink raw reply
* RE: segmentaion fault with array[4096]
From: Studencki Pawel @ 2005-08-19 7:17 UTC (permalink / raw)
To: 'Marcelo Tosatti'; +Cc: 'linuxppc-embedded@ozlabs.org'
hello,
it is very strange, I found that SIGSEGV is generated in function
do_page_fault() in arch/ppc/mm/fault.c
------------------------------------------------------------------
int do_page_fault(struct pt_regs *regs, unsigned long address,
unsigned long error_code)
{
struct vm_area_struct * vma;
struct mm_struct *mm = current->mm;
siginfo_t info;
int code = SEGV_MAPERR;
#if defined(CONFIG_4xx) || defined (CONFIG_BOOKE)
int is_write = error_code & ESR_DST;
#else
int is_write = 0;
/*
* Fortunately the bit assignments in SRR1 for an instruction
* fault and DSISR for a data fault are mostly the same for the
* bits we are interested in. But there are some bits which
* indicate errors in DSISR but can validly be set in SRR1.
*/
// printk("fault bad_area is_write is NULL %x\n", regs->dsisr);
if (TRAP(regs) == 0x400)
error_code &= 0x48200000;
else
{
// printk("fault bad_area is_write err = %x %x\n", error_code,
TRAP(regs));
is_write = error_code & 0x02000000;
}
#endif /* CONFIG_4xx || CONFIG_BOOKE */
---------------------------------------------------------------
It is in DSI Exception, so it goes to "else" and sets is_write to value
error_code & 0x02000000, where error_code is DSISR.
it is better, when is_write != 0, because if it's NULL, a few lines below
there
is an "goto" to bad_area:
if (!is_write)
{
goto bad_area;
}
and I get exception.
At exception error_code is 0x4821, but in User Manual MPC866 in chapter
6.1.2.3
in table 6-7, they write that bits 0-14 in DSISR are NULL. I'm confused and
I don't know how should I interpret this. Where does value 0x4821 come
from??? most of the time it is 0x82000000...
best regards
Pawel
> -----Original Message-----
> From: Marcelo Tosatti [mailto:marcelo.tosatti@cyclades.com]
> Sent: Thursday, August 18, 2005 8:01 PM
> To: Studencki Pawel
> Cc: 'linuxppc-embedded@ozlabs.org'
> Subject: Re: segmentaion fault with array[4096]
>
> Hi!
> On Thu, Aug 18, 2005 at 11:45:04AM +0200, Studencki Pawel wrote:
> > hello,
> >
> > because I want to do some tests with fusion/RTAI on my mpc852,
> > I had to downgrade my system to kernel 2.6.10
>
> Downgrade from what?
>
> > And I get a strange problem: if I start application with
> char array size
> > 4096 (or even smaller 2600) I get "segmentation fault".
> >
> > Could someone gives me a hint? Is this kernel configuration problem?
> > Where can I start looking for a reason?
>
> Have you tried to debug the application with gdb to spot more
> precisely
> what is it doing that makes it receive a segfault?
>
> Most likely its doing an invalid memory access.
>
^ permalink raw reply
* [PATCH] (22/46) Kconfig fix (IRQ_ALL_CPUS vs. MV64360)
From: Al Viro @ 2005-08-19 6:51 UTC (permalink / raw)
To: torvalds; +Cc: linuxppc-dev
MV64360 does not support IRQ_ALL_CPUS - see arch/ppc/syslib/mv64360_pic.c.
Signed-off-by: Al Viro <viro@parcelfarce.linux.theplanet.co.uk>
----
diff -urN RC13-rc6-git10-ppc-SMP/arch/ppc/Kconfig RC13-rc6-git10-mv64360-irq/arch/ppc/Kconfig
--- RC13-rc6-git10-ppc-SMP/arch/ppc/Kconfig 2005-08-18 14:23:24.000000000 -0400
+++ RC13-rc6-git10-mv64360-irq/arch/ppc/Kconfig 2005-08-18 14:23:25.000000000 -0400
@@ -931,7 +931,7 @@
config IRQ_ALL_CPUS
bool "Distribute interrupts on all CPUs by default"
- depends on SMP
+ depends on SMP && !MV64360
help
This option gives the kernel permission to distribute IRQs across
multiple CPUs. Saying N here will route all IRQs to the first
^ permalink raw reply
* [PATCH] (21/46) Kconfig fix (ppc32 SMP dependencies)
From: Al Viro @ 2005-08-19 6:51 UTC (permalink / raw)
To: torvalds; +Cc: linuxppc-dev
ppc SMP is supported only for 6xx/POWER3/POWER4 - i.e. ones that have
PPC_STD_MMU. Dependency fixed.
Signed-off-by: Al Viro <viro@parcelfarce.linux.theplanet.co.uk>
----
diff -urN RC13-rc6-git10-vga/arch/ppc/Kconfig RC13-rc6-git10-ppc-SMP/arch/ppc/Kconfig
--- RC13-rc6-git10-vga/arch/ppc/Kconfig 2005-08-18 14:23:09.000000000 -0400
+++ RC13-rc6-git10-ppc-SMP/arch/ppc/Kconfig 2005-08-18 14:23:24.000000000 -0400
@@ -911,6 +911,7 @@
default y if PPC_PREP
config SMP
+ depends on PPC_STD_MMU || BROKEN
bool "Symmetric multi-processing support"
---help---
This enables support for systems with more than one CPU. If you have
^ permalink raw reply
* [PATCH] (23/46) Kconfig fix (ppc 4xx and early serial)
From: Al Viro @ 2005-08-19 6:52 UTC (permalink / raw)
To: torvalds; +Cc: linuxppc-dev
a bunch of ppc 4xx variants unconditionally calls early_serial_setup() and
therefore needs SERIAL_8250
Signed-off-by: Al Viro <viro@parcelfarce.linux.theplanet.co.uk>
----
diff -urN RC13-rc6-git10-mv64360-irq/arch/ppc/platforms/4xx/Kconfig RC13-rc6-git10-4xx-early-serial/arch/ppc/platforms/4xx/Kconfig
--- RC13-rc6-git10-mv64360-irq/arch/ppc/platforms/4xx/Kconfig 2005-08-10 10:37:46.000000000 -0400
+++ RC13-rc6-git10-4xx-early-serial/arch/ppc/platforms/4xx/Kconfig 2005-08-18 14:23:26.000000000 -0400
@@ -3,6 +3,11 @@
depends on 40x || 44x
default y
+config WANT_EARLY_SERIAL
+ bool
+ select SERIAL_8250
+ default n
+
menu "IBM 4xx options"
depends on 4xx
@@ -18,6 +23,7 @@
config BUBINGA
bool "Bubinga"
+ select WANT_EARLY_SERIAL
help
This option enables support for the IBM 405EP evaluation board.
@@ -70,21 +76,25 @@
config BAMBOO
bool "Bamboo"
+ select WANT_EARLY_SERIAL
help
This option enables support for the IBM PPC440EP evaluation board.
config EBONY
bool "Ebony"
+ select WANT_EARLY_SERIAL
help
This option enables support for the IBM PPC440GP evaluation board.
config LUAN
bool "Luan"
+ select WANT_EARLY_SERIAL
help
This option enables support for the IBM PPC440SP evaluation board.
config OCOTEA
bool "Ocotea"
+ select WANT_EARLY_SERIAL
help
This option enables support for the IBM PPC440GX evaluation board.
^ permalink raw reply
* Timer modification
From: smiling_23 @ 2005-08-18 23:03 UTC (permalink / raw)
To: linuxppc-embedded
Hi all,
Can any one know how the "timer_adj" calculation is working in
timer.c in linuxkernle2.6.12.5
If we change the HZ value to more than 1000. What hapens to the wall clock.
And i have seen different "time_adj" calculations for HZ 100 and 1000.
How to change this calculation for new HZ value.
Thanks,
Cjag
^ permalink raw reply
* Re: How to build more than 16M ramdisk for u-boot
From: Grant Likely @ 2005-08-19 6:15 UTC (permalink / raw)
To: ?????????, linuxppc-embedded
In-Reply-To: <1124416918.6752.1.camel@banana>
On Fri, Aug 19, 2005 at 10:01:58AM +0800, ????????? wrote:
> Hi all:
>
> I found if i build ramdisk more than 16M, i'll got error at using
> mke2fs command.
>
> dd if=/dev/zero of=ramdisk bs=1024k count=20
>
> /sbin/mke2fs -F m0 ramdisk
> mke2fs 1.36 (05-Feb-2005)
> mke2fs: bad blocks count - ramdisk
typo?
try: /sbin/mke2fs -F -m0 ramdisk
^ permalink raw reply
* How to build more than 16M ramdisk for u-boot
From: 徐小威 @ 2005-08-19 2:01 UTC (permalink / raw)
To: linuxppc-embedded
Hi all:
I found if i build ramdisk more than 16M, i'll got error at using
mke2fs command.
dd if=/dev/zero of=ramdisk bs=1024k count=20
/sbin/mke2fs -F m0 ramdisk
mke2fs 1.36 (05-Feb-2005)
mke2fs: bad blocks count - ramdisk
why ?
I used FC3 & eldk 3.1.1.
Best Regard,
Rober Hsu
^ permalink raw reply
* jffs2 image upgrade on running root
From: Tony Hardie @ 2005-08-18 23:22 UTC (permalink / raw)
To: linuxppc-embedded
Hi Guys,
I have a running embedded 2.6.11 distro with a busybox type jffs2 rfs.
Not I am trying to upgrade that jffs2 imaged and tried something like to
following.
Have a temp ext2 ramdisk mounted in /mnt
pivot_root . oldroot
exec chroot . /linuxrc <dev/console >dev/console 2>&1
or
exec chroot . /sbin/init <dev/console >dev/console 2>&1
all "seem" to work bit init is still running I think on the /oldroot/ as
well so when I try to umount /oldroot is just get device or resource
busy.
Any ideas?
Tony Hardie B.Sc
SHOUTIP Software Architect
Net.com
6900 Paseo Padre Parkway
Fremont
CA, 94555
Ph: 510-574-2386
Mob: 510-449-4339
^ permalink raw reply
* Re: [PATCH] ppc32: removed usage of <asm/segment.h>
From: Paul Mackerras @ 2005-08-18 23:40 UTC (permalink / raw)
To: Kumar Gala
Cc: akpm, zach, Miklos Szeredi, linux-kernel, hch, linuxppc-dev,
Gala Kumar K.-galak, davem
In-Reply-To: <A4C8B92D-B390-4BF8-A6D5-106ACBD0E716@freescale.com>
Kumar Gala writes:
> So after all of this its not clear to me if its acceptable to kill
> all users of <asm/segment.h> in the kernel and to move code that
> exists in <asm/segment.h> to <asm/uaccess.h> for arch's that need it.
<asm/segment.h> doesn't describe any part of the user/kernel ABI, so
we should be OK to kill it. I would say we should remove the ppc and
ppc64 versions of it once 2.6.13 is out, and offer the other arch
maintainers a patch that moves their stuff as you suggest. I think
also we could submit patches to remove the places where it is included
in generic kernel code post 2.6.13.
Paul.
^ permalink raw reply
* [PATCH] Fix for TLB errata on early Xilinx Virtex-II Pro silicon
From: Grant Likely @ 2005-08-18 19:04 UTC (permalink / raw)
To: linuxppc-embedded
[PATCH] Early versions of the Xilinx Virtex-II Pro have a TLB errata where
only even numbered TLB entries work correctly. Occurs on chips where
PVR == 0x20010820 || 0x20010860
See Record #14052, solution #12 in the Xilinx answers database
http://www.xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=14052
This patch adds a config option to use only even TLB entries on the V2Pro
It also makes a trivial change to the Kconfig so that Xilinx options depend
on VIRTEX_II_PRO instead of XILINX_ML300. Also fixes incorrect comment
Signed-off-by: Grant Likely <grant.likely@gdcanada.com>
---
arch/ppc/kernel/head_4xx.S | 18 ++++++++++++++----
arch/ppc/platforms/4xx/Kconfig | 26 +++++++++++++++++++++-----
2 files changed, 35 insertions(+), 9 deletions(-)
b9dd781e27bc3ddce51141b3d9844ebec1e424f2
diff --git a/arch/ppc/kernel/head_4xx.S b/arch/ppc/kernel/head_4xx.S
--- a/arch/ppc/kernel/head_4xx.S
+++ b/arch/ppc/kernel/head_4xx.S
@@ -769,7 +769,11 @@ finish_tlb_load:
/* load the next available TLB index.
*/
lwz r9, tlb_4xx_index@l(0)
+#if defined(CONFIG_VIRTEX_II_PRO_TLB_FIX)
+ addi r9, r9, 2
+#else
addi r9, r9, 1
+#endif
andi. r9, r9, (PPC4XX_TLB_SIZE-1)
stw r9, tlb_4xx_index@l(0)
@@ -915,10 +919,9 @@ initial_mmu:
mtspr SPRN_PID,r0
sync
- /* Configure and load two entries into TLB slots 62 and 63.
- * In case we are pinning TLBs, these are reserved in by the
- * other TLB functions. If not reserving, then it doesn't
- * matter where they are loaded.
+ /* Configure and load a temporary TLB entry into slot 63 (or 62 when
+ * CONFIG_VIRTEX_II_PRO_TLB_FIX is enabled). This entry is
+ * invalidated once the page tables are set up.
*/
clrrwi r4,r4,10 /* Mask off the real page number */
ori r4,r4,(TLB_WR | TLB_EX) /* Set the write and execute bits */
@@ -926,7 +929,14 @@ initial_mmu:
clrrwi r3,r3,10 /* Mask off the effective page number */ ori r3,r3,(TLB_VALID | TLB_PAGESZ(PAGESZ_16M))
+#if defined(CONFIG_VIRTEX_II_PRO_TLB_FIX)
+ /* Odd numbered TLB slots are broken on Xilinx V2Pro processors
+ * where PVR = 20010820 | 20010860
+ */
+ li r0,62 /* TLB slot 62 */
+#else
li r0,63 /* TLB slot 63 */
+#endif
tlbwe r4,r0,TLB_DATA /* Load the data portion of the entry */ tlbwe r3,r0,TLB_TAG /* Load the tag portion of the entry */
diff --git a/arch/ppc/platforms/4xx/Kconfig b/arch/ppc/platforms/4xx/Kconfig
--- a/arch/ppc/platforms/4xx/Kconfig
+++ b/arch/ppc/platforms/4xx/Kconfig
@@ -161,11 +161,6 @@ config IBM_OCP
depends on ASH || BAMBOO || BUBINGA || CPCI405 || EBONY || EP405 || LUAN || OCOTEA || REDWOOD_5 || REDWOOD_6 || SYCAMORE || WALNUT
default y
-config XILINX_OCP
- bool
- depends on XILINX_ML300
- default y
-
config IBM_EMAC4
bool
depends on 440GX || 440SP
@@ -201,6 +196,27 @@ config VIRTEX_II_PRO
depends on XILINX_ML300
default y
+config VIRTEX_II_PRO_TLB_FIX
+ bool "Virtex-II Pro TLB bugfix"
+ depends on VIRTEX_II_PRO
+ default n
+ help
+ Early versions of the Xilinx Virtex-II Pro have a TLB errata where
+ only even numbered TLB entries work correctly. Say Y here if
+ PVR == 0x20010820 || 0x20010860, or if your board crashes early
+ after enabling the MMU
+
+ See Record #14052, solution #12 in the Xilinx answers database
+ http://www.xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=14052
+
+ It is safe to say Y here, but there is a performance impact.
+ Say N if unsure.
+
+config XILINX_OCP
+ bool
+ depends on VIRTEX_II_PRO
+ default y
+
config STB03xxx
bool
depends on REDWOOD_5 || REDWOOD_6
^ permalink raw reply
* Re: Best kernel for Xilinx VirtexII Pro/PPC405 ?
From: Keith J Outwater @ 2005-08-18 18:13 UTC (permalink / raw)
To: Peter Ryser; +Cc: linuxppc-embedded
In-Reply-To: <43049D99.6090908@xilinx.com>
Hi Peter -
Well, the good news is that it works, and works well. In my humble
opinion, supporting it would be pretty simple, but I completely understand
why RHEL is the supported distribution. I would much rather see effort
put into polishing up EDK under Linux than in supporting every Linux
distro out there.
For me, the bottom line was this: do I want to migrate all of other
development activities from FC4 to RHEL for the sake of EDK, or try to run
EDK under FC4? I tried the latter approach, and now that the Jungo
WinDriver v7.1 is out, parallel port debugging works by simply using
WinDriver 7.1 and patching the Xilinx XPC4 parport driver.
I now have the kernel booting on a Memec 2VP50 eval board using U-Boot as
the bootloader. I used the linuxppc-2.4 kernel rsynced from MontaVista.
That particular kernel did not have support for U-Boot but it did support
the ML300 and a Memec 2VP40/2VP70 board. I had to modify the kernel to
accept a board description structure from U-Boot and I added a new board
type for my custom hardware.
The approach I took was definitely the "roll your own approach", but then
again I've done this (Linux board ports) a couple times and I know U-Boot
well.
Keith
Peter Ryser <peter.ryser@xilinx.com> wrote on 08/18/2005 07:39:21 AM:
>
> > I am running all of my development tools (EDK, ISE, ELDK, etc...)
under
> >Fedora Core 4, so I am looking for a publicly accessible kernel source
> >tree that best supports the PPC405 in the Virtex II Pro.
> >
> Keep in mind that EDK and ISE are not "officially" supported on FC4.
> Anyway, with EDK, ISE, and ELDK you seem to have all that is needed to
> get started with Linux on Virtex-II Pro and Virtex-4.
>
> - Peter
>
>
^ permalink raw reply
* Re: segmentaion fault with array[4096]
From: Marcelo Tosatti @ 2005-08-18 18:01 UTC (permalink / raw)
To: Studencki Pawel; +Cc: 'linuxppc-embedded@ozlabs.org'
In-Reply-To: <291992F9ECD9AB4F995C7E96B9A30DC008E081@nbgh103a.nbg6.siemens.de>
Hi!
On Thu, Aug 18, 2005 at 11:45:04AM +0200, Studencki Pawel wrote:
> hello,
>
> because I want to do some tests with fusion/RTAI on my mpc852,
> I had to downgrade my system to kernel 2.6.10
Downgrade from what?
> And I get a strange problem: if I start application with char array size
> 4096 (or even smaller 2600) I get "segmentation fault".
>
> Could someone gives me a hint? Is this kernel configuration problem?
> Where can I start looking for a reason?
Have you tried to debug the application with gdb to spot more precisely
what is it doing that makes it receive a segfault?
Most likely its doing an invalid memory access.
^ permalink raw reply
* Re: [PATCH] PPC: Don't sleep in flush_dcache_icache_page()
From: Matt Porter @ 2005-08-18 18:08 UTC (permalink / raw)
To: Marcelo Tosatti; +Cc: Roland Dreier, linuxppc-embedded
In-Reply-To: <20050818175642.GA7523@dmt.cnet>
On Thu, Aug 18, 2005 at 02:56:42PM -0300, Marcelo Tosatti wrote:
>
> Hi Roland,
>
> On Tue, Aug 16, 2005 at 01:56:49PM -0700, Roland Dreier wrote:
> > flush_dcache_icache_page() will be called on an instruction page
> > fault. We can't sleep in the fault handler, so use kmap_atomic()
> > instead of just kmap() for the Book-E case.
> >
> > Signed-off-by: Roland Dreier <rolandd@cisco.com>
>
> Why do you need to disable interrupts during the kmap_atomic/flush_dcache_icache
> operation ?
>
> I fail to see how an interrupt could have any reference to the data
> being dealt with here (the user page).
We just took care of this offline. The original patch is sharing
a kmap slot with another kmap_atomic user I put in before...the
sync page user. If an interrupt came in causing the DMA API to
be used, we would have a problem.
The clean solution was to use a different kmap slot.
-Matt
^ permalink raw reply
* [RFC] MPC5200 BestComm microcode [en]/[de]coding draft
From: Andrey Volkov @ 2005-08-18 18:05 UTC (permalink / raw)
To: Sylvain Munaut; +Cc: linuxppc-embedded
[-- Attachment #1: Type: text/plain, Size: 432 bytes --]
Hello Sylvain,
This a draft of Documentation/powerpc/bestcomm.txt,
it was born since I couldn't find DRD/LCD description and
"... graphical task builder are currently in development"
(quotation from AN2604) :(, so I try write doco by myself.
Here result of my reverse engineering.
If you or somebody have more information or found some
bugs, please, fix/expand my text, especially places marked by "?".
--
Regards
Andrey Volkov
[-- Attachment #2: bestcomm.diff --]
[-- Type: text/plain, Size: 5973 bytes --]
Draft
---
commit 8a3ea9eb0933e43b8fad1f50ef566b6145202e25
tree 7d9356ec710b68c159c8ad95c49ea1c2439beb74
parent 825f973a6a6e12ff0c9d5bc10a74b4cae3687db5
author Andrey Volkov <avolkov@varma-el.com> Thu, 18 Aug 2005 21:58:24 +0400
committer Andrey Volkov <avolkov@varma-el.com> Thu, 18 Aug 2005 21:58:24 +0400
Documentation/powerpc/bestcomm.txt | 143 ++++++++++++++++++++++++++++++++++++
1 files changed, 143 insertions(+), 0 deletions(-)
diff --git a/Documentation/powerpc/bestcomm.txt b/Documentation/powerpc/bestcomm.txt
new file mode 100644
--- /dev/null
+++ b/Documentation/powerpc/bestcomm.txt
@@ -0,0 +1,143 @@
+ Microcode description of MPC5200 Bestcomm DMA
+=====================================================================
+
+Please mail me (Andrey Volkov, avolkov@varma-el.com) if you have
+questions, comments or corrections.
+
+All instructions of Bestcomm microcode are divided on
+two main types: LCD (Loop Control Descriptor) and
+DRD (Data Routing Descriptor). Any Task must started from
+LCD[EX] instruction and finished by DRD instruction (usually NOP).
+Each of instruction types, in one's turn, are divided on two
+and three subtypes accordingly, which are described below:
+
+1) DRD1A - load/store data, and, optionally, made some operation
+on it (depend on what loaded to FDT). Here is fields description
+of this DRD:
+
+Bits num. Name Desc.
+[31:29] Reserved, must be 0
+[28:28] MORE ?????, if set then idx/var
+ dst/src fields are changed. I.e.
+ [16:10] contain SOURCE,
+ and [09:03] contain DESTINATION.
+[27:27] TFD Transfer Frame Done. Assert frame
+ done Transfer Frame Done line of
+ selected (in INIT field) periphery.
+[26:26] INT Interrupt. If set to 1,
+ then generate core interrupt
+[25:21] INIT Initiator (aka requestor) number.
+[20:19] RS Read Size (0 - 32bit word, 1 - byte,
+ 2 - 16 bit word, 3 - dynamic/reserved??
+ (masked in real time?))
+[18:17] WS Write Size (see above)
+[16:16] ??????????????
+[15:15] Destination index prefix,
+ if set (i.e. =1), then bitfield [13:10]
+ contain index number, and [14:14] have
+ meaning of indirect addressing flag.
+ If this field cleared then field
+ [14:10] contain index of VARIABLE.
+[14:14] Indirect addressing by idx,
+ (and only by idx) flag, or high bit of
+ variable index.
+[13:10] index of DESTINATION/SOURCE idx/var.
+
+[09:09] ???? For some cases 1, for another 0.????
+
+[08:08] Same as in [14:10], but for source.
+[07:03] Same as in [14:10], but for source.
+[02:00] EU3 Number of function, which will execute
+ on EU#3.
+Note: For DRD1A exist special case, aka NOP, which act as
+task terminator. Fields, in this case, have next meanings:
+
+[31:28] Reserved must be 0.
+[27:27] TFD Transfer Frame Done.
+[26:26] INT Interrupt.
+[25:21] INIT Initiator (aka requestor) number. Usually 0,
+ or ALWAYS INITIATOR.
+[16:00] NOP code Must be 0x1f8
+
+Ex. Please, pay attention to first two lines: since MORE is set,
+codes for idx2 and var13 are in different fields, then for case
+where MORE is not set (var4 = var2).:
+ 0x10601010 -- DRD1A: var4 = var2; FN=0 MORE init=3 WS=0 RS=0
+ 0x00008868 -- DRD1A: idx2 = var13; FN=0 init=0 WS=0 RS=0
+ 0x0404c999 -- DRD1A: *idx2 = EU3(); FN=1 INT init=0 WS=2 RS=0
+ 0x000001f8 -- DRD1A: NOP
+ 0x040001f8 -- DRD1A: INT init=0
+
+Next two DRDs are ALWAYS coupled, i.e it is impossible to using
+DRD2B1 without preceded DRD2A, but any (?fixme?) number DRD2B1
+may followed by DRD2A.
+
+2) DRD2A - setup bestcomm Execution Unit (EU)
+Bitfields encodings:
+
+Bits num. Name Desc
+[31:31] MORE ?????????
+[30:29] EXT must be always initialized
+ by 3 (binary 11)
+[27:27] TFD Transfer Frame Done.
+[26:21] INIT Initiator number.
+[20:19] RS Read Size
+[18:17] WS Write Size
+[16:04] reserved, must be 0
+[03:00] EU3 Number of function, which will execute
+ on EU#3 at DRD2B1 time.
+Ex:
+ 0x60140002 -- DRD2A: EU3=2 EXT init=0 WS=2 RS=2
+
+3) DRD2B1 - execute function and store result of it.
+
+Bits num. Name Desc
+[31:28] Reserved must be 0.
+
+[27:22] DST Result destination (var/idx/*idx).
+ See description of field [15:10] of DRD1A
+ section.
+[21:20] WS ?? Write Size for dst ??
+[19:18] EU# Since MPC5200 have only EU#3, this filed
+ always must contain 3
+[17:12] ???? (Reserved, must be 0x0f),
+ may be encoded operands sizes????
+[11:06] OP1 operand 1 of EU#3
+ See description of field [15:10] in DRD1A
+ section.
+[05:00] OP2 operand 2 of EU#3
+ See description of field [15:10] in DRD1A
+ section, or, if for EU#3 function needed
+ only one operand (like CRC), then this field
+ must contain 0x1f
+
+Ex:
+ 0x0d0cf247 -- DRD2B1: *idx4 = EU3(); EU3(var9,var7)
+ 0x0c8cfc5f -- DRD2B1: *idx2 = EU3(); EU3(*idx1)
+
+4) LCD - run followed loop microcode, or may be used for checking
+some conditions. LCD may be nested (only two levels are supported).
+
+Bits num. Name Desc
+[31:31] LOOP Loop prefix, always 1
+[30:30] ???????????????????
+[29:23] INIT1 ???Initializition part of first init expression.???
+[22:11] ???????????????????
+[10:06] CMP_VAR Variable to which idx compared. Part of
+ Termination control.
+[05:03] INC1 increment1
+[02:00] INC2 increment2, if unsused may be any value
+
+5) LCDEXT - If in yours loop used more then 2 indexes, then
+this record MUST PRECEDED LCD. Also loop end condition MAY pointed HERE,
+then it not pointed in LCD.
+
+Bits num. Name Desc
+[31:31] LOOP Loop prefix, always 1
+[30:30] ???????????????????
+[29:23] INIT1 ???Initializition part of first init expression.???
+[22:11] ???????????????????
+[10:06] CMP_VAR Variable to which idx compared. Part of
+ Termination control.
+[05:03] INC1 increment1
+[02:00] INC2 increment2, if unsused may be any value
^ permalink raw reply
* Re: [PATCH] PPC: Don't sleep in flush_dcache_icache_page()
From: Marcelo Tosatti @ 2005-08-18 17:56 UTC (permalink / raw)
To: Roland Dreier; +Cc: linuxppc-embedded
In-Reply-To: <521x4tha7i.fsf@cisco.com>
Hi Roland,
On Tue, Aug 16, 2005 at 01:56:49PM -0700, Roland Dreier wrote:
> flush_dcache_icache_page() will be called on an instruction page
> fault. We can't sleep in the fault handler, so use kmap_atomic()
> instead of just kmap() for the Book-E case.
>
> Signed-off-by: Roland Dreier <rolandd@cisco.com>
Why do you need to disable interrupts during the kmap_atomic/flush_dcache_icache
operation ?
I fail to see how an interrupt could have any reference to the data
being dealt with here (the user page).
> diff --git a/arch/ppc/mm/init.c b/arch/ppc/mm/init.c
> --- a/arch/ppc/mm/init.c
> +++ b/arch/ppc/mm/init.c
> @@ -560,8 +560,16 @@ void flush_dcache_page(struct page *page
> void flush_dcache_icache_page(struct page *page)
> {
> #ifdef CONFIG_BOOKE
> - __flush_dcache_icache(kmap(page));
> - kunmap(page);
> + unsigned long flags;
> + void *start;
> +
> + local_irq_save(flags);
> +
> + start = kmap_atomic(page, KM_PPC_SYNC_PAGE);
> + __flush_dcache_icache(start);
> + kunmap_atomic(start, KM_PPC_SYNC_PAGE);
> +
> + local_irq_restore(flags);
> #elif CONFIG_8xx
> /* On 8xx there is no need to kmap since highmem is not supported */
> __flush_dcache_icache(page_address(page));
^ permalink raw reply
* Re: [PATCH] ppc32: ppc_sys SOC identification additions
From: Vitaly Bordug @ 2005-08-18 18:01 UTC (permalink / raw)
To: Kumar Gala; +Cc: linuxppc-embedded list
In-Reply-To: <20050817204932.D1C22353CE9@atlas.denx.de>
[-- Attachment #1: Type: text/plain, Size: 116 bytes --]
Here's the same but without strcmp().
Signed-off-by: Vitaly Bordug <vbordug@ru.mvista.com>
--
Sincerely,
Vitaly
[-- Attachment #2: ppc_sys_add.patch --]
[-- Type: text/x-patch, Size: 2491 bytes --]
diff --git a/arch/ppc/syslib/ppc_sys.c b/arch/ppc/syslib/ppc_sys.c
--- a/arch/ppc/syslib/ppc_sys.c
+++ b/arch/ppc/syslib/ppc_sys.c
@@ -6,6 +6,7 @@
* Maintainer: Kumar Gala <kumar.gala@freescale.com>
*
* Copyright 2005 Freescale Semiconductor Inc.
+ * Copyright 2005 MontaVista, Inc. by Vitaly Bordug <vbordug@ru.mvista.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
@@ -35,10 +36,58 @@ void __init identify_ppc_sys_by_id(u32 i
void __init identify_ppc_sys_by_name(char *name)
{
- /* TODO */
+ unsigned int i = 0;
+ while (strcmp(ppc_sys_specs[i].ppc_sys_name, "")) {
+ if (!strcmp(ppc_sys_specs[i].ppc_sys_name, name))
+ break;
+ i++;
+ }
+ cur_ppc_sys_spec = &ppc_sys_specs[i];
return;
}
+static int __init count_sys_specs(void)
+{
+ int i = 0;
+ while (ppc_sys_specs[i].ppc_sys_name[0])
+ i++;
+ return i;
+}
+
+static int __init find_chip_by_name_and_id(char *name, u32 id)
+{
+ int ret = -1;
+ unsigned int i = 0;
+ unsigned int j = 0;
+ unsigned int dups = 0;
+
+ unsigned char matched[count_sys_specs()];
+
+ while (ppc_sys_specs[i].ppc_sys_name[0]) {
+ if (!strcmp(ppc_sys_specs[i].ppc_sys_name, name))
+ matched[j++] = i;
+ i++;
+ }
+ if (j != 0) {
+ for (i = 0; i < j; i++) {
+ if ((ppc_sys_specs[matched[i]].mask & id) ==
+ ppc_sys_specs[matched[i]].value) {
+ ret = matched[i];
+ dups++;
+ }
+ }
+ ret = (dups == 1) ? ret : (-1 * dups);
+ }
+ return ret;
+}
+
+void __init identify_ppc_sys_by_name_and_id(char *name, u32 id)
+{
+ int i = find_chip_by_name_and_id(name, id);
+ BUG_ON(i < 0);
+ cur_ppc_sys_spec = &ppc_sys_specs[i];
+}
+
/* Update all memory resources by paddr, call before platform_device_register */
void __init
ppc_sys_fixup_mem_resource(struct platform_device *pdev, phys_addr_t paddr)
diff --git a/include/asm-ppc/ppc_sys.h b/include/asm-ppc/ppc_sys.h
--- a/include/asm-ppc/ppc_sys.h
+++ b/include/asm-ppc/ppc_sys.h
@@ -49,7 +49,8 @@ extern struct ppc_sys_spec *cur_ppc_sys_
/* determine which specific SOC we are */
extern void identify_ppc_sys_by_id(u32 id) __init;
-extern void identify_ppc_sys_by_name(char *name) __init;
+extern void identify_ppc_sys_by_name(char* name) __init;
+extern void identify_ppc_sys_by_name_and_id(char *name, u32 id) __init;
/* describes all devices that may exist in a given family of processors */
extern struct platform_device ppc_sys_platform_devices[];
^ permalink raw reply
* Re: [PATCH] ppc32: removed usage of <asm/segment.h>
From: Kumar Gala @ 2005-08-18 16:25 UTC (permalink / raw)
To: Miklos Szeredi
Cc: akpm, zach, linux-kernel, hch, linuxppc-dev, Gala Kumar K.-galak,
davem
In-Reply-To: <E1E5KpP-0004dy-00@dorka.pomaz.szeredi.hu>
On Aug 17, 2005, at 5:07 AM, Miklos Szeredi wrote:
>>> They are provided by _one_ kernel, not necessarily the running
>>>
> kernel.
>
>>
>> No, they're provided by packages like glibc-kernheaders or similar
>> that are maintained separately.
>>
>
> Yes. And "maintenance" I presume means "copy" the kernel headers and
> do some cleanup to be compliant to the relevant standards (which the
> kernel maintainers couldn't be bothered to do).
>
>
>> They're split from the kernel headers and we don't need to keep
>> obsolete junk around.
>>
>
> I agree about obsolete junk.
>
> However statements like "No kernel headers can be included by userland
> anymore" can be slightly misleading.
So after all of this its not clear to me if its acceptable to kill
all users of <asm/segment.h> in the kernel and to move code that
exists in <asm/segment.h> to <asm/uaccess.h> for arch's that need it.
- kumar
^ permalink raw reply
* Re: linuxppc cross compiler
From: Grant Likely @ 2005-08-18 15:31 UTC (permalink / raw)
To: somshekar chandrashekar kadam, linuxppc-dev
In-Reply-To: <20050818065554.28998.qmail@webmail30.rediffmail.com>
On Thu, Aug 18, 2005 at 06:55:54AM -0000, somshekar chandrashekar kadam wrote:
> HI ,
>
> need to set the cross compiler for Linux 2.6 PPC from scratch on X86 host , is there any howto or anyother document , i saw only denx eldk supporting it . wanted to build entire cross compiler from scratch , please direct me to any good link if it is there , tried to open the link given on Embedded PowerPC linux howto , that page doesnt exist anymore ,please suggest guys which one is better
I second te recommendation for crosstool. You COULD unpack and build
binutils/gcc/glibc step by step, but you really don't want to unless you
enjoy beating you head against the wall.
http://www.kegel.com/crosstool
Also, subscribe to the crossgcc mailing list:
http://sources.redhat.com/ml/crossgcc/
Cheers,
g.
^ permalink raw reply
* Re: Multiple I2C busses on PPC405
From: Tolunay Orkun @ 2005-08-18 15:06 UTC (permalink / raw)
To: Tolunay Orkun; +Cc: linuxppc-embedded
In-Reply-To: <42FD248D.2040508@orkun.us>
I've not received any reply to my inquiry. Since it was last Friday
afternoon it might have been missed.
I really do appreciate if someone would suggest a bitbang I2C interface
driver generic enough to modify. I only need /dev/i2c? support from the
driver.
Tolunay
Tolunay Orkun wrote:
> I have a working embedded linux on Cogent CSB472 board (PPC405GP)
> currently based on off 2.4.31. We are already using the I2C bus on
> PowerPC using hardware I2C driver (IBM IIC I2C Interface) at Fast
> (400khz) mode.
>
> We need to add support for yet another (slow) I2C bus with PPC405 being
> the master and I'm looking at implementing bit bang interface using GPIO
> pins.
>
> What is the best way to get this going? I am looking at modifying the
> bit bang driver (PPC_405_I2C_Algorithm?) for the I/O pins I'll use.
> Anyone has done something similar. I appreciate all the advice I can get.
>
> Best Regards,
> Tolunay
>
>
>
^ permalink raw reply
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