* oil press
From: mach @ 2005-09-06 7:37 UTC (permalink / raw)
To: linuxppc-dev
Dear Sir/Madam,
It's our pleasure to send the business letter to your esteemed company. We are a professional trading company in
China. In the past ten years, our grain and oil machinery were exported to many countries and areas in the world
,and have won a good reputation from our customers .
I am very glad to get the e-mail address by Internet. So we specially introduce our oil press equipment and oil
refining equipment and hulling equipment and other agricultural machinery to satisfy your needs. We hope to build a
mutual beneficial business relationship with your esteemed company.
The quotation of our extraction machinery as follows:
1)Model 6YL-68
Capacity: 0.8-1ton/24h.
Power: 5.5kw
Net Weight: 140kg
Packing Dimensions: 920*480*760
2) Model 6YL-80
Capacity: 2-3ton/24h
Power: 5.5kw
Net Weight: 330kg
Packing Dimensions(mm): 1370*570*1080
3) Model 6YL-95
Capacity: 3-4ton/24h.
Power: 7.5-11kw
Net Weight: 620kg
Packing Dimensions(mm):1940*700*780
4) Model 6YL-100
Capacity: 4-5Ton/24h.
Power: 7.5kw
Net Weight: 480kg
Packing Dimensions(mm):1700*600*1130
5) 6YL-120
Capacity: 6Ton/24h.
Power: 15kw
Net Weight: 650kg
Packing Dimensions (mm): 1970*700*780
6) 6YL-80A Integrated oil press
Capacity: 2-3Ton/24h
Power: 5.5 +0.75kw
Net Weight: 520kg
Packing Dimensions(mm): 1420*635*1480 & 1135*530*520
7) 6YL-100A Integrated Oil press
Capacity: 5Ton/24h.
Power: 7.5+1.1 kw
Net Weight: 780kg
Packing dimensions (mm): 2270*1100*1950 & 1170*660*760
8) LYZX18 Cold Press Expeller
Capacity: 6-10Ton/24h(taking non-shell rapeseed as an example)
Residual Oil Content in Cake: 4-13%
Total Power: 27.2KW
Net Weight: 3500KG
Boundary Dimensions(mm): 3176*1850*2600
9) 202-3 Screw Pre-press Expeller
Capacity: 45-50Ton/24h(sunflower kernel or rapeseed serving as an example)
Residual Oil Content in Cake: 13% approx(under normal conditions)
Electric Motor: Y225-M-6,1000R.P.M.30KW.220/380V,50Hz
Net Weight: 5500KG.approx
Boundary Dimensions(mm): 2900*1850*3640
10) ZY283-3 Screw Pre-press Expeller
Capacity: 140-460Ton/24h(sunflower kernel or rapeseed serving as an example)
Residual Oil Content in Cake: 15-20%(under the normal conditions)
Total Power: 55KW 15KW
Net Weight: 9380KG.approx
Boundary Dimensions(mm): 3708*1920*3843
11) Generator
950 Generator
3900 Generator
7800 Generator
12) Peanut Sheller
Model 6B-180
Capacity: 7.2 Ton/24h.
Power: 1.5kw
Net Weight: 100kg
Packing Dimensions: 1280*670*1200
Model 6BH-45
Capacity: 12 Ton/24h.
Power: 4kw
Net Weight: 380kg
Packing Dimensions: 1200*990*2090
Model 6BH-65
Capacity: 24 Ton/24h.
Power: 7.5kw
Net Weight: 700kg
Packing Dimensions: 2000*1400*3010
13) Rice Mill
14) Flour Mill
15) Combine Harvest
16) Tractor
17) The Complete Plant of Hulling Sesame Equipment
18) The Complete Plant of All Kinds of Oil Corps(Extraction and Refinery), 10MTPD-3000MTPD
19) The Complete Plant of Tomato Paste
If you want to get further information that you are interested in products, please send me
the concrete request, I will do my best to supply you with the satisfying service with the
competitive price.
I will appreciate you very much, if I can receive your reply.
Best regards
Alisa Zhao
Anyang General International Trading Co., Ltd.
Address: Jiefang Rd No.99,Anyang , Henan, China
Tel:86-372-5953961 Fax:86-372-5951936
E-mail:mach@e-century.com.cn
http://www.ayimpex.com
^ permalink raw reply
* PCI on MPC827x
From: Alex Zeffertt @ 2005-09-06 12:31 UTC (permalink / raw)
To: linuxppc-embedded
Hi list,
Does the linuxppc kernel support PCI on PowerQUICC II chips? If so, in which patch/release was it
added?
Thanks in advance,
Alex
^ permalink raw reply
* Re: PCI on MPC827x
From: Vitaly Bordug @ 2005-09-06 12:45 UTC (permalink / raw)
To: Alex Zeffertt; +Cc: linuxppc-embedded
In-Reply-To: <20050906133122.225a0922.ajz@cambridgebroadband.com>
Alex Zeffertt wrote:
> Hi list,
>
> Does the linuxppc kernel support PCI on PowerQUICC II chips? If so, in which patch/release was it
> added?
>
The PCI bridge for 8272ADS has been added in 2.6.12-rc6. This stuff
should work on PQ2FADS as well.
--
Sincerely,
Vitaly
^ permalink raw reply
* Regarding the PPC board bringup with Linux 2.6 kernel
From: vinay hegde @ 2005-09-06 13:00 UTC (permalink / raw)
To: linuxppc-embedded
Hi All,
I am working on bringing up a PowerPC based board
with Linux 2.6 kernel (Board supoort package).
However, I am facing some problem with respect to
debugging.
When I boot the board with the Linux kernel (BSP),
the board hangs after printing the following
information.
>>>>>>>>>>>>>>>>>>>>>>>
Network Loading from: /dev/enet0
Client IP Address = 192.168.4.38
Server IP Address = 192.168.4.101
Gateway IP Address = 192.168.4.253
Subnet IP Address Mask = 255.255.255.0
Boot File Name = developer.kdi
Load Address = 04000000
Buffer Size = 2000000
Network Boot File Load Start - Press <ESC> to
Bypass, <SPC> to Continue
Bytes Received =&6141952, Bytes Loaded =&6141952
Bytes/Second =&511829, Elapsed Time =12 Second(s)
Boot Device =/dev/enet0
Boot File =developer.kdi
Load Address =04000000
Load Size =005DB800
Execution Address =04000020
Execution Offset =00000020
Passing control to the loaded file/image.
loaded at: 00800000 00DD8800
zimage at: 008058E0 009933BB
initrd at: 00998000 00DD8800
avail ram: 00400000 00800000
Linux/PPC load: console=ttyS0,9600 console=tty0
root=/dev/sda2 console=ttyS0,9600 root=/dev/ram rw
Uncompressing Linux...done.
Now booting the kernel
>>>>>>>>>>>>>>>>>>>>>.
I am going through the source code to figure out the
problem, but unable to find out what is going wrong
here.
Does anybody have any idea about the problem? Also,
is it possible to print some debug messages at this
point of booting? {Note that, in the early stage of
booting process the serial is initialized and all
the above mentioned messages (like Uncomressing
Linux, Now booting the kernel etc) are printed. And
immediately after printing the "now booting the
kernel message,the serial is closed. This code is in
uncompress_kernel() function in
arch/ppc/boot/simple/misc.c file).
Can somebody help me with the above problem?
Thank you,
vinay hegde.
__________________________________________________________
Yahoo! India Matrimony: Find your partner online. Go to http://yahoo.shaadi.com
^ permalink raw reply
* Re: PCI on MPC827x
From: Alex Zeffertt @ 2005-09-06 13:48 UTC (permalink / raw)
To: Vitaly Bordug; +Cc: linuxppc-embedded
In-Reply-To: <431D8F5B.9050803@ru.mvista.com>
On Tue, 06 Sep 2005 16:45:15 +0400
Vitaly Bordug <vbordug@ru.mvista.com> wrote:
> Alex Zeffertt wrote:
> > Hi list,
> >
> > Does the linuxppc kernel support PCI on PowerQUICC II chips? If so, in which patch/release was
> > it added?
> >
> The PCI bridge for 8272ADS has been added in 2.6.12-rc6. This stuff
> should work on PQ2FADS as well.
Thanks Vitaly. Unfortunately we're using linux-2.4.25.
Has anybody backported the PCI bridge to 2.4? If not, do you think it's a lot of work?
Alex
^ permalink raw reply
* Re: PCI on MPC827x
From: Vitaly Bordug @ 2005-09-06 14:04 UTC (permalink / raw)
To: Alex Zeffertt; +Cc: linuxppc-embedded
In-Reply-To: <20050906144845.1e603c72.ajz@cambridgebroadband.com>
[-- Attachment #1: Type: text/plain, Size: 963 bytes --]
Alex Zeffertt wrote:
> On Tue, 06 Sep 2005 16:45:15 +0400
> Vitaly Bordug <vbordug@ru.mvista.com> wrote:
>
>
>>Alex Zeffertt wrote:
>>
>>>Hi list,
>>>
>>>Does the linuxppc kernel support PCI on PowerQUICC II chips? If so, in which patch/release was
>>>it added?
>>>
>>
>>The PCI bridge for 8272ADS has been added in 2.6.12-rc6. This stuff
>>should work on PQ2FADS as well.
>
>
> Thanks Vitaly. Unfortunately we're using linux-2.4.25.
>
> Has anybody backported the PCI bridge to 2.4? If not, do you think it's a lot of work?
>
> Alex
>
>
I've done it already. The source was in the latest linux-2.4, at the end
of the bitkeeper times (I guess rsync copy from source.mvista.com is
still available - refer to http://penguinppc.org/kernel/ for details).
This is one of the latest versions - AFAIR there were one issue on
PQ2FADS that's not fixed here. Also, you may search list archives - the
patch should be there as well.
--
Sincerely,
Vitaly
[-- Attachment #2: pq2-pci.patch --]
[-- Type: text/x-patch, Size: 20111 bytes --]
# This is a BitKeeper generated diff -Nru style patch.
#
# ChangeSet
# 2005/02/18 17:11:57+03:00 vbordug@ru.mvista.com
# Fixed compilation warnings for 8260-like boards when CONFIG_PCI=y
#
# include/asm-ppc/mpc8260.h
# 2005/02/18 17:11:54+03:00 vbordug@ru.mvista.com +2 -0
# Fixed compilation warnings when CONFIG_PCI=y
#
# ChangeSet
# 2005/02/18 16:17:49+03:00 vbordug@ru.mvista.com
# Added support for PCI bridge on MPC8272 and PQ2FADS boards
#
# arch/ppc/platforms/pq2ads.h
# 2005/02/18 16:17:47+03:00 vbordug@ru.mvista.com +88 -5
# Added support for PCI bridge on MPC8272 and PQ2FADS
#
# arch/ppc/platforms/Makefile
# 2005/02/18 16:17:47+03:00 vbordug@ru.mvista.com +5 -0
# Added support for PCI bridge on MPC8272 and PQ2FADS
#
# arch/ppc/kernel/m8260_setup.c
# 2005/02/18 16:17:47+03:00 vbordug@ru.mvista.com +17 -0
# Added support for PCI bridge on MPC8272 and PQ2FADS
#
# arch/ppc/kernel/Makefile
# 2005/02/18 16:17:47+03:00 vbordug@ru.mvista.com +8 -0
# Modules needed for PCI Bridge support on MPC8272 and PQ2FADS
#
# arch/ppc/platforms/pq2ads_pci.c
# 2005/02/18 16:15:29+03:00 vbordug@ru.mvista.com +361 -0
# PCI Bridge setup routines for MPC8272ADS and PQ2FADS (initial revision)
#
# arch/ppc/platforms/pq2ads_pci.c
# 2005/02/18 16:15:29+03:00 vbordug@ru.mvista.com +0 -0
# BitKeeper file /home/common/work/community/kernel/linuxppc-2.4/arch/ppc/platforms/pq2ads_pci.c
#
diff -Nru a/arch/ppc/kernel/Makefile b/arch/ppc/kernel/Makefile
--- a/arch/ppc/kernel/Makefile 2005-02-18 17:14:12 +03:00
+++ b/arch/ppc/kernel/Makefile 2005-02-18 17:14:12 +03:00
@@ -108,6 +108,14 @@
obj-$(CONFIG_PCI) += indirect_pci.o pci_auto.o
endif
+ifeq ($(CONFIG_ADS8272),y)
+obj-$(CONFIG_PCI) += indirect_pci.o pci_auto.o
+endif
+
+ifeq ($(CONFIG_PQ2FADS),y)
+obj-$(CONFIG_PCI) += indirect_pci.o pci_auto.o
+endif
+
include $(TOPDIR)/Rules.make
entry.o: entry.S ppc_defs.h
diff -Nru a/arch/ppc/kernel/m8260_setup.c b/arch/ppc/kernel/m8260_setup.c
--- a/arch/ppc/kernel/m8260_setup.c 2005-02-18 17:14:12 +03:00
+++ b/arch/ppc/kernel/m8260_setup.c 2005-02-18 17:14:12 +03:00
@@ -54,6 +54,7 @@
unsigned char __res[sizeof(bd_t)];
extern void cpm2_reset(void);
+extern void pq2ads_init_irq(void);
static void __init
m8260_setup_arch(void)
@@ -61,6 +62,12 @@
/* Reset the Communication Processor Module.
*/
cpm2_reset();
+
+#ifdef CONFIG_PCI
+ /* Lookup PCI host bridges */
+ m8260_find_bridges();
+#endif
+
}
static void
@@ -184,6 +191,13 @@
cpm2_immr->im_intctl.ic_siprr = 0x05309770;
cpm2_immr->im_intctl.ic_scprrh = 0x05309770;
cpm2_immr->im_intctl.ic_scprrl = 0x05309770;
+#if defined (CONFIG_PCI) && ( defined (CONFIG_ADS8272) || defined (CONFIG_PQ2FADS) )
+ /* Install the handlers for the external interrupt controller on the
+ * MPC8272ADS and PQ2FADS boards.
+ */
+ pq2ads_init_irq();
+#endif
+
}
@@ -209,6 +223,9 @@
static void __init
m8260_map_io(void)
{
+#if defined (CONFIG_PCI) && ( defined (CONFIG_ADS8272) || defined (CONFIG_PQ2FADS) )
+ io_block_mapping(0x80000000, 0x80000000, 0x10000000, _PAGE_IO);
+#endif
io_block_mapping(0xf0000000, 0xf0000000, 0x10000000, _PAGE_IO);
io_block_mapping(0xe0000000, 0xe0000000, 0x10000000, _PAGE_IO);
}
diff -Nru a/arch/ppc/platforms/Makefile b/arch/ppc/platforms/Makefile
--- a/arch/ppc/platforms/Makefile 2005-02-18 17:14:12 +03:00
+++ b/arch/ppc/platforms/Makefile 2005-02-18 17:14:12 +03:00
@@ -98,6 +98,11 @@
obj-$(CONFIG_MPC85xx_CDS) += mpc85xx_cds_common.o
endif
+ifeq ($(CONFIG_PCI),y)
+obj-$(CONFIG_ADS8272) += pq2ads_pci.o
+obj-$(CONFIG_PQ2FADS) += pq2ads_pci.o
+endif
+
ifeq ($(CONFIG_SMP),y)
obj-$(CONFIG_ALL_PPC) += pmac_smp.o chrp_smp.o
endif
diff -Nru a/arch/ppc/platforms/pq2ads.h b/arch/ppc/platforms/pq2ads.h
--- a/arch/ppc/platforms/pq2ads.h 2005-02-18 17:14:12 +03:00
+++ b/arch/ppc/platforms/pq2ads.h 2005-02-18 17:14:12 +03:00
@@ -14,6 +14,10 @@
#include <asm/ppcboot.h>
+#ifdef CONFIG_PCI
+#include <linux/pci_ids.h>
+#endif
+
/* Memory map is configured by the PROM startup.
* We just map a few things we need. The CSR is actually 4 byte-wide
* registers that can be accessed as 8-, 16-, or 32-bit values.
@@ -40,7 +44,79 @@
#define PHY_INTERRUPT SIU_INT_IRQ7
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration Register 4-31
+ */
+#define SIUMCR_BBD 0x80000000 /* Bus Busy Disable */
+#define SIUMCR_ESE 0x40000000 /* External Snoop Enable */
+#define SIUMCR_PBSE 0x20000000 /* Parity Byte Select Enable */
+#define SIUMCR_CDIS 0x10000000 /* Core Disable */
+#define SIUMCR_DPPC00 0x00000000 /* Data Parity Pins Configuration*/
+#define SIUMCR_DPPC01 0x04000000 /* - " - */
+#define SIUMCR_DPPC10 0x08000000 /* - " - */
+#define SIUMCR_DPPC11 0x0c000000 /* - " - */
+#define SIUMCR_L2CPC00 0x00000000 /* L2 Cache Pins Configuration */
+#define SIUMCR_L2CPC01 0x01000000 /* - " - */
+#define SIUMCR_L2CPC10 0x02000000 /* - " - */
+#define SIUMCR_L2CPC11 0x03000000 /* - " - */
+#define SIUMCR_LBPC00 0x00000000 /* Local Bus Pins Configuration */
+#define SIUMCR_LBPC01 0x00400000 /* - " - */
+#define SIUMCR_LBPC10 0x00800000 /* - " - */
+#define SIUMCR_LBPC11 0x00c00000 /* - " - */
+#define SIUMCR_APPC00 0x00000000 /* Address Parity Pins Configuration*/
+#define SIUMCR_APPC01 0x00100000 /* - " - */
+#define SIUMCR_APPC10 0x00200000 /* - " - */
+#define SIUMCR_APPC11 0x00300000 /* - " - */
+#define SIUMCR_CS10PC00 0x00000000 /* CS10 Pin Configuration */
+#define SIUMCR_CS10PC01 0x00040000 /* - " - */
+#define SIUMCR_CS10PC10 0x00080000 /* - " - */
+#define SIUMCR_CS10PC11 0x000c0000 /* - " - */
+#define SIUMCR_BCTLC00 0x00000000 /* Buffer Control Configuration */
+#define SIUMCR_BCTLC01 0x00010000 /* - " - */
+#define SIUMCR_BCTLC10 0x00020000 /* - " - */
+#define SIUMCR_BCTLC11 0x00030000 /* - " - */
+#define SIUMCR_MMR00 0x00000000 /* Mask Masters Requests */
+#define SIUMCR_MMR01 0x00004000 /* - " - */
+#define SIUMCR_MMR10 0x00008000 /* - " - */
+#define SIUMCR_MMR11 0x0000c000 /* - " - */
+#define SIUMCR_LPBSE 0x00002000 /* LocalBus Parity Byte Select Enable*/
+
+
#ifdef CONFIG_PCI
+/*
+ * Define the vendor/device ID for the MPC82XX.
+ */
+#define PCI_DEVICE_ID_MPC8265 ((0x18C0 << 16) | PCI_VENDOR_ID_MOTOROLA)
+#define PCI_DEVICE_ID_MPC8272 ((0x18C1 << 16) | PCI_VENDOR_ID_MOTOROLA)
+
+
+/* Bit definitions for PCIBR registers */
+
+#define PCIBR_ENABLE 0x00000001
+
+/* Bit definitions for POMCR registers */
+#define POCMR_ENABLE 0x80000000
+#define POCMR_PCI_IO 0x40000000
+#define POCMR_PREFETCH_EN 0x20000000
+#define POTA_ADDR_SHIFT 12
+
+/* Bit definitions for PCI Inbound Comparison Mask registers */
+#define PICMR_ENABLE 0x80000000
+#define PICMR_NO_SNOOP_EN 0x40000000
+#define PICMR_PREFETCH_EN 0x20000000
+#define PITA_ADDR_SHIFT 12
+
+/* Bit definitions for PCI_GCR register */
+
+#define PCIGCR_PCI_BUS_EN 0x1
+
+/* Bus parking decides where the bus control sits when idle */
+/* If modifying memory controllers for PCI park on the core */
+
+#define PPC_ACR_BUS_PARK_CORE 0x6
+#define PPC_ACR_BUS_PARK_PCI 0x3
+
+
/* PCI interrupt controller */
#define PCI_INT_STAT_REG 0xF8200000
#define PCI_INT_MASK_REG 0xF8200004
@@ -50,22 +126,23 @@
#define PIRQD (NR_SIU_INTS + 3)
/*
- * PCI memory map definitions for MPC8266ADS-PCI.
+ * PCI memory map definitions for MPC82XXADS.
*
* processor view
* local address PCI address target
* 0x80000000-0x9FFFFFFF 0x80000000-0x9FFFFFFF PCI mem with prefetch
* 0xA0000000-0xBFFFFFFF 0xA0000000-0xBFFFFFFF PCI mem w/o prefetch
- * 0xF4000000-0xF7FFFFFF 0x00000000-0x03FFFFFF PCI IO
+ * 0xF6000000-0xF7FFFFFF 0x00000000-0x01FFFFFF PCI IO
*
* PCI master view
* local address PCI address target
- * 0x00000000-0x1FFFFFFF 0x00000000-0x1FFFFFFF MPC8266 local memory
+ * 0x00000000-0x1FFFFFFF 0x00000000-0x1FFFFFFF MPC82XXADS local memory
*/
/* window for a PCI master to access MPC8266 memory */
#define PCI_SLV_MEM_LOCAL 0x00000000 /* Local base */
#define PCI_SLV_MEM_BUS 0x00000000 /* PCI base */
+#define PCI_SLV_MEM_SIZE 0x10000000 /* 256Mb */
/* window for the processor to access PCI memory with prefetching */
#define PCI_MSTR_MEM_LOCAL 0x80000000 /* Local base */
@@ -78,9 +155,15 @@
#define PCI_MSTR_MEMIO_SIZE 0x20000000 /* 512MB */
/* window for the processor to access PCI I/O */
-#define PCI_MSTR_IO_LOCAL 0xF4000000 /* Local base */
+#define PCI_MSTR_IO_LOCAL 0xF6000000 /* Local base */
#define PCI_MSTR_IO_BUS 0x00000000 /* PCI base */
-#define PCI_MSTR_IO_SIZE 0x04000000 /* 64MB */
+#define PCI_MSTR_IO_SIZE 0x02000000 /* 32MB */
+
+#if defined CONFIG_ADS8272
+#define PCI_INT_TO_SIU SIU_INT_IRQ2
+#elif defined CONFIG_PQ2FADS
+#define PCI_INT_TO_SIU SIU_INT_IRQ6
+#endif
#define _IO_BASE PCI_MSTR_IO_LOCAL
#define _ISA_MEM_BASE PCI_MSTR_MEMIO_LOCAL
diff -Nru a/arch/ppc/platforms/pq2ads_pci.c b/arch/ppc/platforms/pq2ads_pci.c
--- /dev/null Wed Dec 31 16:00:00 196900
+++ b/arch/ppc/platforms/pq2ads_pci.c 2005-02-18 17:14:12 +03:00
@@ -0,0 +1,361 @@
+/*
+ * arch/ppc/platforms/pq2fads_pci.c
+ *
+ * PCI Bridge setup routines for MPC8272 and PQ2FADS boards
+ *
+ * Based on: PCI setup routines for the Motorola SPS MPC8266ADS-PCI
+ * reference board by andy_lowe@mvista.com
+ *
+ * Author: Vitaly Bordug <vbordug@ru.mvista.com>
+ *
+ * 2003 (c) MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/pci.h>
+#include <linux/slab.h>
+#include <linux/irq.h>
+
+#include <asm/byteorder.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/uaccess.h>
+#include <asm/machdep.h>
+#include <asm/pci-bridge.h>
+#include <asm/immap_cpm2.h>
+//#include <asm/m8260_pci.h>
+#include <asm/delay.h>
+
+#include "pq2ads.h"
+
+extern void setup_m8260_indirect_pci(struct pci_controller* hose,
+ u32 cfg_addr,
+ u32 cfg_data);
+
+/*
+ * interrupt routing
+ */
+
+static inline int
+pq2ads_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
+{
+ static char pci_irq_table[][4] =
+ /*
+ * PCI IDSEL/INTPIN->INTLINE
+ * A B C D
+ */
+ {
+ { PIRQA, PIRQB, PIRQC, PIRQD }, /* IDSEL 22 - PCI slot 0 */
+ { PIRQD, PIRQA, PIRQB, PIRQC }, /* IDSEL 23 - PCI slot 1 */
+ { PIRQC, PIRQD, PIRQA, PIRQB }, /* IDSEL 24 - PCI slot 2 */
+ };
+
+ const long min_idsel = 22, max_idsel = 24, irqs_per_slot = 4;
+ return PCI_IRQ_TABLE_LOOKUP;
+}
+
+static void
+pq2ads_mask_irq(unsigned int irq)
+{
+ int bit = irq - NR_SIU_INTS;
+
+ *(volatile unsigned long *) PCI_INT_MASK_REG |= (1 << (31 - bit));
+ return;
+}
+
+static void
+pq2ads_unmask_irq(unsigned int irq)
+{
+ int bit = irq - NR_SIU_INTS;
+
+ *(volatile unsigned long *) PCI_INT_MASK_REG &= ~(1 << (31 - bit));
+ return;
+}
+
+static void
+pq2ads_mask_and_ack(unsigned int irq)
+{
+ int bit = irq - NR_SIU_INTS;
+
+ *(volatile unsigned long *) PCI_INT_MASK_REG |= (1 << (31 - bit));
+ return;
+}
+
+static void
+pq2ads_end_irq(unsigned int irq)
+{
+ int bit = irq - NR_SIU_INTS;
+
+ *(volatile unsigned long *) PCI_INT_MASK_REG &= ~(1 << (31 - bit));
+ return;
+}
+
+struct hw_interrupt_type pq2ads_ic = {
+ "PQ2ADS PCI IC",
+ NULL,
+ NULL,
+ pq2ads_unmask_irq,
+ pq2ads_mask_irq,
+ pq2ads_mask_and_ack,
+ pq2ads_end_irq,
+ 0
+};
+
+static void
+pci_irq_demux(int irq, void *dev_id, struct pt_regs *regs)
+{
+ unsigned long stat, mask, pend;
+ int bit;
+
+ for(;;) {
+ stat = *(volatile unsigned long *) PCI_INT_STAT_REG;
+ mask = *(volatile unsigned long *) PCI_INT_MASK_REG;
+ pend = stat & ~mask & 0xf0000000;
+ if (!pend)
+ break;
+ for (bit = 0; pend != 0; ++bit, pend <<= 1) {
+ if (pend & 0x80000000)
+ ppc_irq_dispatch_handler(regs, NR_SIU_INTS + bit);
+ }
+ }
+
+ return;
+}
+
+void
+pq2ads_init_irq(void)
+{
+ int irq;
+ volatile cpm2_map_t* immap = cpm2_immr;
+#ifdef CONFIG_ADS8272
+ /* configure chip select for PCI interrupt controller */
+ immap->im_memctl.memc_br3 = PCI_INT_STAT_REG | 0x00001801;
+ immap->im_memctl.memc_or3 = 0xffff8010;
+#elif defined CONFIG_PQ2FADS
+ /* configure chip select for PCI interrupt controller */
+ immap->im_memctl.memc_br8 = PCI_INT_STAT_REG | 0x00001801;
+ immap->im_memctl.memc_or8 = 0xffff8010;
+#else
+#error This software is not intended to support this chip!
+#endif
+
+ for (irq = NR_SIU_INTS; irq < NR_SIU_INTS + 4; irq++)
+ irq_desc[irq].handler = &pq2ads_ic;
+
+ /* make PCI IRQ level sensitive */
+ immap->im_intctl.ic_siexr &=
+ ~(1 << (14 - (PCI_INT_TO_SIU - SIU_INT_IRQ1)));
+
+ /* mask all PCI interrupts */
+ *(volatile unsigned long *) PCI_INT_MASK_REG |= 0xfff00000;
+
+ /* install the demultiplexer for the PCI cascade interrupt */
+ if (request_irq(PCI_INT_TO_SIU, pci_irq_demux, SA_INTERRUPT,
+ "PCI IRQ demux", 0))
+ {
+ printk("Installation of PCI IRQ demux handler failed.\n");
+ }
+ return;
+}
+
+static int
+pq2ads_exclude_device(u_char bus, u_char devfn)
+{
+ return PCIBIOS_SUCCESSFUL;
+}
+
+static void
+pq2ads_hw_init(struct pci_controller *hose)
+{
+ __u32 val;
+ volatile cpm2_map_t *immap = cpm2_immr;
+ /* PCI int lowest prio */
+ /* Each 4 bits is a device bus request and the MS 4bits
+ is highest priority */
+ /* Bus 4bit value
+ --- ----------
+ CPM high 0b0000
+ CPM middle 0b0001
+ CPM low 0b0010
+ PCI reguest 0b0011
+ Reserved 0b0100
+ Reserved 0b0101
+ Internal Core 0b0110
+ External Master 1 0b0111
+ External Master 2 0b1000
+ External Master 3 0b1001
+ The rest are reserved
+ */
+ immap->im_siu_conf.siu_82xx.sc_ppc_alrh = 0x61207893;
+ /* park bus on core */
+ immap->im_siu_conf.siu_82xx.sc_ppc_acr = PPC_ACR_BUS_PARK_CORE;
+ /*
+ * Set up master windows that allow the CPU to access PCI space. These
+ * windows are set up using the two SIU PCIBR registers.
+ */
+
+ immap->im_memctl.memc_pcimsk0 = ~(PCI_MSTR_IO_SIZE - 1U);
+ immap->im_memctl.memc_pcibr0 = PCI_MSTR_IO_LOCAL | PCIBR_ENABLE;
+
+ immap->im_memctl.memc_pcimsk1 = ~(PCI_MSTR_MEM_SIZE + PCI_MSTR_MEMIO_SIZE - 1U);
+ immap->im_memctl.memc_pcibr1 = PCI_MSTR_MEM_LOCAL | PCIBR_ENABLE;
+#ifdef CONFIG_ADS8272
+ immap->im_siu_conf.siu_82xx.sc_siumcr = (immap->im_siu_conf.siu_82xx.sc_siumcr &
+ ~SIUMCR_BBD &
+ ~SIUMCR_ESE &
+ ~SIUMCR_PBSE &
+ ~SIUMCR_CDIS &
+ ~SIUMCR_DPPC11 &
+ ~SIUMCR_L2CPC11 &
+ ~SIUMCR_LBPC11 &
+ ~SIUMCR_APPC11 &
+ ~SIUMCR_CS10PC11 &
+ ~SIUMCR_BCTLC11 &
+ ~SIUMCR_MMR11)
+ | SIUMCR_DPPC11 | SIUMCR_L2CPC01 | SIUMCR_LBPC00
+ | SIUMCR_APPC10 | SIUMCR_CS10PC00 | SIUMCR_BCTLC00 | SIUMCR_MMR11;
+#elif defined CONFIG_PQ2FADS
+ /*
+ * Setting required to enable IRQ1-IRQ7 (SIUMCR [DPPC]),
+ * and local bus for PCI (SIUMCR [LBPC]).
+ */
+ immap->im_siu_conf.siu_82xx.sc_siumcr = (immap->im_siu_conf.sc_siumcr &
+ ~SIUMCR_LBPC11 &
+ ~SIUMCR_CS10PC11 &
+ ~SIUMCR_LBPC11) |
+ SIUMCR_LBPC01 | SIUMCR_CS10PC01 | SIUMCR_APPC10;
+#endif
+ /* Enable PCI */
+ immap->im_pci.pci_gcr = cpu_to_le32(PCIGCR_PCI_BUS_EN);
+ {
+ /* give it some time */
+ int i;
+ for(i=0;i<100;i++)
+ udelay(100);
+ }
+
+ /* setup ATU registers */
+ immap->im_pci.pci_pocmr0 = cpu_to_le32(POCMR_ENABLE | POCMR_PCI_IO |
+ ((~(PCI_MSTR_IO_SIZE - 1U)) >> POTA_ADDR_SHIFT));
+ immap->im_pci.pci_potar0 = cpu_to_le32(PCI_MSTR_IO_BUS >> POTA_ADDR_SHIFT);
+ immap->im_pci.pci_pobar0 = cpu_to_le32(PCI_MSTR_IO_LOCAL >> POTA_ADDR_SHIFT);
+
+ /* Set-up non-prefetchable window */
+ immap->im_pci.pci_pocmr1 = cpu_to_le32(POCMR_ENABLE | ((~(PCI_MSTR_MEMIO_SIZE-1U)) >> POTA_ADDR_SHIFT));
+ immap->im_pci.pci_potar1 = cpu_to_le32(PCI_MSTR_MEMIO_BUS >> POTA_ADDR_SHIFT);
+ immap->im_pci.pci_pobar1 = cpu_to_le32(PCI_MSTR_MEMIO_LOCAL >> POTA_ADDR_SHIFT);
+
+ /* Set-up prefetchable window */
+ immap->im_pci.pci_pocmr2 = cpu_to_le32(POCMR_ENABLE |POCMR_PREFETCH_EN |
+ (~(PCI_MSTR_MEM_SIZE-1U) >> POTA_ADDR_SHIFT));
+ immap->im_pci.pci_potar2 = cpu_to_le32((PCI_MSTR_MEM_BUS+PCI_MSTR_MEM_SIZE) >> POTA_ADDR_SHIFT);
+ immap->im_pci.pci_pobar2 = cpu_to_le32((PCI_MSTR_MEM_LOCAL+PCI_MSTR_MEM_SIZE) >> POTA_ADDR_SHIFT);
+
+ /* Inbound transactions from PCI memory space */
+ immap->im_pci.pci_picmr0 = cpu_to_le32(PICMR_ENABLE | PICMR_PREFETCH_EN |
+ ((~(PCI_SLV_MEM_SIZE-1U)) >> PITA_ADDR_SHIFT));
+ immap->im_pci.pci_pibar0 = cpu_to_le32(PCI_SLV_MEM_BUS >> PITA_ADDR_SHIFT);
+ immap->im_pci.pci_pitar0 = cpu_to_le32(PCI_SLV_MEM_LOCAL>> PITA_ADDR_SHIFT);
+
+#if defined CONFIG_ADS8272
+ /* PCI int highest prio */
+ immap->im_siu_conf.siu_82xx.sc_ppc_alrh = 0x01236745;
+#elif defined CONFIG_PQ2FADS
+ immap->im_siu_conf.siu_82xx.sc_ppc_alrh = 0x03124567;
+#endif
+ /* park bus on PCI */
+ immap->im_siu_conf.siu_82xx.sc_ppc_acr = PPC_ACR_BUS_PARK_PCI;
+
+ /* Enable bus mastering and inbound memory transactions */
+ early_read_config_dword(hose, hose->first_busno, 0, PCI_COMMAND, &val);
+ val &= 0xffff0000;
+ val |= PCI_COMMAND_MEMORY|PCI_COMMAND_MASTER;
+ early_write_config_dword(hose, hose->first_busno, 0, PCI_COMMAND, val);
+
+}
+
+
+void __init
+m8260_find_bridges(void)
+{
+ struct pci_controller *hose;
+ int host_bridge;
+ volatile cpm2_map_t *immap = cpm2_immr;
+
+ hose = pcibios_alloc_controller();
+
+ if (!hose)
+ return;
+
+ hose->first_busno = 0;
+ hose->last_busno = 0xff;
+ hose->bus_offset = 0;
+ hose->set_cfg_type = 1;
+
+ setup_indirect_pci(hose,
+ (ulong)&immap->im_pci.pci_cfg_addr,
+ (ulong)&immap->im_pci.pci_cfg_data);
+
+
+ /* Make sure it is a supported bridge */
+ early_read_config_dword(hose,
+ 0,
+ PCI_DEVFN(0,0),
+ PCI_VENDOR_ID,
+ &host_bridge);
+
+ switch (host_bridge) {
+ case PCI_DEVICE_ID_MPC8265:
+ break;
+ case PCI_DEVICE_ID_MPC8272:
+ break;
+
+ default:
+ printk("Attempting to use unrecognized host bridge ID"
+ " 0x%08x.\n", host_bridge);
+ break;
+ }
+
+ pq2ads_hw_init(hose);
+
+ hose->pci_mem_offset = PCI_MSTR_MEM_LOCAL - PCI_MSTR_MEM_BUS;
+ hose->io_space.start = PCI_MSTR_IO_BUS;
+ hose->io_space.end = PCI_MSTR_IO_BUS + PCI_MSTR_IO_SIZE - 1U;
+ hose->mem_space.start = PCI_MSTR_MEM_BUS;
+ hose->mem_space.end = PCI_MSTR_MEMIO_BUS + PCI_MSTR_MEMIO_SIZE - 1U;
+ hose->io_base_virt = (void *)PCI_MSTR_IO_LOCAL;
+ isa_io_base = PCI_MSTR_IO_LOCAL;
+
+ pci_init_resource(&hose->io_resource,
+ PCI_MSTR_IO_BUS,
+ PCI_MSTR_IO_BUS + PCI_MSTR_IO_SIZE - 1U,
+ IORESOURCE_IO,
+ "PCI host bridge");
+
+ pci_init_resource(&hose->mem_resources[0],
+ PCI_MSTR_MEMIO_BUS,
+ PCI_MSTR_MEMIO_BUS + PCI_MSTR_MEMIO_SIZE - 1U,
+ IORESOURCE_MEM,
+ "PCI host bridge");
+
+ pci_init_resource(&hose->mem_resources[1],
+ PCI_MSTR_MEM_BUS,
+ PCI_MSTR_MEM_BUS + PCI_MSTR_MEM_SIZE - 1U,
+ IORESOURCE_MEM | IORESOURCE_PREFETCH,
+ "PCI host bridge");
+
+ pci_dram_offset = PCI_SLV_MEM_LOCAL;
+
+ ppc_md.pci_exclude_device = pq2ads_exclude_device;
+ hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
+
+ ppc_md.pcibios_fixup = NULL;
+ ppc_md.pcibios_fixup_bus = NULL;
+ ppc_md.pci_swizzle = common_swizzle;
+ ppc_md.pci_map_irq = pq2ads_map_irq;
+
+ return;
+}
diff -Nru a/include/asm-ppc/mpc8260.h b/include/asm-ppc/mpc8260.h
--- a/include/asm-ppc/mpc8260.h 2005-02-18 17:14:12 +03:00
+++ b/include/asm-ppc/mpc8260.h 2005-02-18 17:14:12 +03:00
@@ -24,12 +24,14 @@
#include <platforms/pq2ads.h>
#endif
+#ifndef CONFIG_PCI
/* I don't yet have the ISA or PCI stuff done....no 8260 with
* such thing.....
*/
#define _IO_BASE 0
#define _ISA_MEM_BASE 0
#define PCI_DRAM_OFFSET 0
+#endif
#ifndef __ASSEMBLY__
/* The "residual" data board information structure the boot loader
^ permalink raw reply
* Re: PCI on MPC827x
From: Jaap-Jan Boor @ 2005-09-06 13:59 UTC (permalink / raw)
To: Alex Zeffertt; +Cc: linuxppc-embedded
In-Reply-To: <20050906144845.1e603c72.ajz@cambridgebroadband.com>
We use it with 2.4.25. I think you should take a look at Wolfang Denx'
2.4 kernel
Jaap-Jan
Alex Zeffertt wrote:
>On Tue, 06 Sep 2005 16:45:15 +0400
>Vitaly Bordug <vbordug@ru.mvista.com> wrote:
>
>
>
>>Alex Zeffertt wrote:
>>
>>
>>>Hi list,
>>>
>>>Does the linuxppc kernel support PCI on PowerQUICC II chips? If so, in which patch/release was
>>>it added?
>>>
>>>
>>>
>>The PCI bridge for 8272ADS has been added in 2.6.12-rc6. This stuff
>>should work on PQ2FADS as well.
>>
>>
>
>Thanks Vitaly. Unfortunately we're using linux-2.4.25.
>
>Has anybody backported the PCI bridge to 2.4? If not, do you think it's a lot of work?
>
>Alex
>_______________________________________________
>Linuxppc-embedded mailing list
>Linuxppc-embedded@ozlabs.org
>https://ozlabs.org/mailman/listinfo/linuxppc-embedded
>
>
--
J.G.J. Boor Anton Philipsweg 1
Software Engineer 1223 KZ Hilversum
AimSys bv tel. +31 35 689 1941
Postbus 2194, 1200 CD Hilversum mailto:jjboor@aimsys.nl
^ permalink raw reply
* Re: Regarding the PPC board bringup with Linux 2.6 kernel
From: Wolfgang Denk @ 2005-09-06 14:54 UTC (permalink / raw)
To: vinay hegde; +Cc: linuxppc-embedded
In-Reply-To: <20050906130029.74727.qmail@web8405.mail.in.yahoo.com>
In message <20050906130029.74727.qmail@web8405.mail.in.yahoo.com> you wrote:
>
> Does anybody have any idea about the problem? Also,
Yes.
> is it possible to print some debug messages at this
> point of booting? {Note that, in the early stage of
Use a BDI2000.
> Can somebody help me with the above problem?
Maybe you start reading the FAQ... See
http://www.denx.de/twiki/bin/view/DULG/LinuxHangsAfterUncompressingKernel
Best regards,
Wolfgang Denk
--
Software Engineering: Embedded and Realtime Systems, Embedded Linux
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de
A wise person makes his own decisions, a weak one obeys public
opinion. -- Chinese proverb
^ permalink raw reply
* Re: Regarding the PPC board bringup with Linux 2.6 kernel
From: Clemens Koller @ 2005-09-06 16:09 UTC (permalink / raw)
Cc: linuxppc-embedded
In-Reply-To: <20050906145405.BFEC5352661@atlas.denx.de>
Hi, Vinay
Please reply to the list also!
I can guess your problem, but you should give more
information about your system i.e.
Processor / Board / Kernel version, ...
vinay hegde wrote:
> I do not have the board in my possesion. Actually, I
> am using the board through virtual network. Hence, I
> am unable to use any of the debugging techniques
> (JTAG, logic analyzer etc) except going through the
> source code and printing some messages.
Then you depend on the console output at least.
-> early printk.
> Also, how do I enable early printk option? I did not
> find any such option under kernel configuration.
i.e. if you use one of the latest 2.6 kernels,
turn on "Support for early boot texts over serial port"
(That's in in "Kernel hacking")
Verify your console settings twice.
You can even start to poke out some characters manually
to the serial port to see if (where) it really hangs if
you cannot use or don't want to spend lots of money to
get a hw debugger just for this.
> And, thanks for referring me to the mailing
> addresses. I will immediately subscribe to Ozlabs!
Read the list archives and the FAQ's mentioned
in here and ask google. You will get good answers there,
too!
Best greets,
Clemens Koller
_______________________________
R&D Imaging Devices
Anagramm GmbH
Rupert-Mayer-Str. 45/1
81379 Muenchen
Germany
http://www.anagramm.de
Phone: +49-89-741518-50
Fax: +49-89-741518-19
^ permalink raw reply
* [PATCH] ppc32: Fix Kconfig mismerge
From: Kumar Gala @ 2005-09-06 16:46 UTC (permalink / raw)
To: Andrew Morton; +Cc: linuxppc-dev, linux-kernel
Looks like the help comment for MPC834x got merged incorrectly.
Signed-off-by: Kumar Gala <kumar.gala@freescale.com>
---
commit 28806bb4f8992eb46d2d788a00d08f62b4559d61
tree de364c30cb32f279b3b01f13f683d0fd88416bb9
parent 2dcbb32c37cd71d9f4a7f5530af896a18d859ef5
author Kumar K. Gala <kumar.gala@freescale.com> Tue, 06 Sep 2005 11:24:52 -0500
committer Kumar K. Gala <kumar.gala@freescale.com> Tue, 06 Sep 2005 11:24:52 -0500
arch/ppc/Kconfig | 10 +++++-----
1 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/ppc/Kconfig b/arch/ppc/Kconfig
--- a/arch/ppc/Kconfig
+++ b/arch/ppc/Kconfig
@@ -495,11 +495,6 @@ config WINCEPT
MPC821 PowerPC, introduced in 1998 and designed to be used in
thin-client machines. Say Y to support it directly.
- Be aware that PCI buses can only function when SYS board is plugged
- into the PIB (Platform IO Board) board from Freescale which provide
- 3 PCI slots. The PIBs PCI initialization is the bootloader's
- responsiblilty.
-
endchoice
choice
@@ -675,6 +670,11 @@ config MPC834x_SYS
bool "Freescale MPC834x SYS"
help
This option enables support for the MPC 834x SYS evaluation board.
+
+ Be aware that PCI buses can only function when SYS board is plugged
+ into the PIB (Platform IO Board) board from Freescale which provide
+ 3 PCI slots. The PIBs PCI initialization is the bootloader's
+ responsiblilty.
config EV64360
bool "Marvell-EV64360BP"
^ permalink raw reply
* Re: Regarding the PPC board bringup with Linux 2.6 kernel
From: Robert P. J. Day @ 2005-09-06 16:34 UTC (permalink / raw)
To: Clemens Koller; +Cc: linuxppc-embedded
In-Reply-To: <431DBF34.2040000@anagramm.de>
On Tue, 6 Sep 2005, Clemens Koller wrote:
> Hi, Vinay
>
> Please reply to the list also!
>
> I can guess your problem, but you should give more
> information about your system i.e.
> Processor / Board / Kernel version, ...
i missed the first part of this. i've booted a 2.6 kernel on an 8xx
board and got to the command prompt. is that of any use here?
rday
p.s. i'm not using u-boot as the bootloader but that shouldn't be an
unmanageable difference.
^ permalink raw reply
* Xilinx SystemACE driver for 2.6
From: Grant Likely @ 2005-09-06 18:26 UTC (permalink / raw)
To: linuxppc-embedded
Has anybody ported the SystemACE driver from 2.4 to 2.6 yet? If so,
where can I pull a patch from? Otherwise I'll start work on it.
Thanks,
g.
^ permalink raw reply
* Re: [PATCH 0/3] Start the merge
From: Jon Loeliger @ 2005-09-06 20:12 UTC (permalink / raw)
To: linuxppc64-dev, linuxppc-dev@ozlabs.org
In-Reply-To: <200508290845.34544.arnd@arndb.de>
On Mon, 2005-08-29 at 01:45, Arnd Bergmann wrote:
> On Maandag 29 August 2005 05:01, Stephen Rothwell wrote:
>
> > Please send at least the first upstream. The other two can also probably
> > be sent.
>
> These certainly look good to me.
>
> This is another patch to merge the atomic.h file. It is not completely
> trivial and changes the semantics for 32 bit SMP systems, which previously
> did not do EIEIO_ON_SMP within the atomic operations. AFAICT, that was
> a bug in the 32 bit version, which is now fixed as a side-effect of
> the merge.
>
> The combined version of this file also prevents building user space
> applications using atomic.h on ppc64. That was already impossible
> on 32 bit ppc, but probably also created broken output on ppc64.
>
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
>
> --
>
> include/asm-ppc/atomic.h | 214 ------------------------------
> include/asm-ppc64/atomic.h | 197 ---------------------------
> include/asm-ppc64/memory.h | 59 --------
> linux-2.6.12/include/asm-powerpc/atomic.h | 209 +++++++++++++++++++++++++++++
> linux-2.6.12/include/asm-powerpc/memory.h | 59 ++++++++
> linux-2.6.12/include/asm-ppc/io.h | 11 -
> 6 files changed, 269 insertions(+), 480 deletions(-)
Paul,
I'd like to call attention to this buried patch. It appears that
it might be lost due to Subject: line swiping; it likely hasn't
gotten first class status as its own independent patch.
Any chance we can get this one reviewed and pushed upstream too?
Thanks,
jdl
^ permalink raw reply
* Re: PATCH Merge more include files
From: Jon Loeliger @ 2005-09-06 20:45 UTC (permalink / raw)
To: Stephen Rothwell; +Cc: linuxppc64-dev, linuxppc-dev@ozlabs.org
In-Reply-To: <20050902163708.12c1abe3.sfr@canb.auug.org.au>
On Fri, 2005-09-02 at 01:37, Stephen Rothwell wrote:
> On Thu, 01 Sep 2005 15:51:52 -0500 Jon Loeliger <jdl@freescale.com> wrote:
> >
> > This patch merges several include files from
> > asm-ppc and asm-ppc64 into the new asm-powerpc.
> >
> > Signed-off-by: Jon Loeliger <jdl@freescale.com>
> > Signed-off-by: Kumar Gala <kumar.gala@freescale.com>
>
> > +#ifndef _POWERPC_BUGS_H
>
> I would use _ASM_POWERPC_... but that is just me.
I'll start using _ASM_POWERPC_ from now on. I will
also submit a different patch to do a round of this
sort of cleanup.
Can we get an official call on the GPL header in
include files? I'm defaulting to adding them for now.
> Looks good.
Thanks. More coming, of course.
So, will you resubmit patches based on your 3/3 patch
that cover the slid-through the cracks set, or shall I?
I'm thinking pmac_features.h, dbdma.h, keylargo.h, etc.
Thanks,
jdl
^ permalink raw reply
* Re: PATCH Merge more include files
From: Jon Loeliger @ 2005-09-06 20:46 UTC (permalink / raw)
Cc: linuxppc64-dev, Arnd Bergmann, linuxppc-dev@ozlabs.org
In-Reply-To: <B6241EC1-429C-4286-BCF0-E0D3DC5049BF@freescale.com>
On Fri, 2005-09-02 at 08:38, Kumar Gala wrote:
> On Sep 1, 2005, at 10:18 PM, Arnd Bergmann wrote:
>
> > On Dunnersdag 01 September 2005 22:51, Jon Loeliger wrote:
> >
> >> +/*
> >> + * This file is included by 'init/main.c' to check for
> >> + * architecture-dependent bugs.
> >> + */
> >> +
> >> +extern void check_bugs(void);
> >> +
> >>
> >
> > Actually, I think this could to be
> >
> > +static inline void check_bugs(void)
> > +{
> > +}
> >
> > The function is empty on both ppc and ppc64, so we can just as
> > well get rid of the symbol as well.
> > The rest of the patch looks perfect to me.
>
> We just have to make sure to get ride of the implementation in arch/
> ppc*/kernel/syscalls.c if we do this.
>
> - kumar
Arnd,
If you'd like, I'll submit a patch to use the static inline
variant and rip out the definiton in the syscalls.c files.
jdl
^ permalink raw reply
* PATCH Merge kmap_types.h
From: Jon Loeliger @ 2005-09-06 20:51 UTC (permalink / raw)
To: linuxppc-dev@ozlabs.org, linuxppc64-dev
Here is a patch to merge the ppc and pp64 version of kmap_types.h
Signed-off-by: Jon Loeliger <jdl@freescale.com>
Signed-off-by: Kumar Gala <kumar.gala@freescale.com>
---
diff --git a/include/asm-powerpc/kmap_types.h b/include/asm-powerpc/kmap_types.h
new file mode 100644
--- /dev/null
+++ b/include/asm-powerpc/kmap_types.h
@@ -0,0 +1,33 @@
+#ifndef _ASM_POWERPC_KMAP_TYPES_H
+#define _ASM_POWERPC_KMAP_TYPES_H
+
+#ifdef __KERNEL__
+
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+enum km_type {
+ KM_BOUNCE_READ,
+ KM_SKB_SUNRPC_DATA,
+ KM_SKB_DATA_SOFTIRQ,
+ KM_USER0,
+ KM_USER1,
+ KM_BIO_SRC_IRQ,
+ KM_BIO_DST_IRQ,
+ KM_PTE0,
+ KM_PTE1,
+ KM_IRQ0,
+ KM_IRQ1,
+ KM_SOFTIRQ0,
+ KM_SOFTIRQ1,
+ KM_PPC_SYNC_PAGE,
+ KM_PPC_SYNC_ICACHE,
+ KM_TYPE_NR
+};
+
+#endif /* __KERNEL__ */
+#endif /* _ASM_POWERPC_KMAP_TYPES_H */
diff --git a/include/asm-ppc/kmap_types.h b/include/asm-ppc/kmap_types.h
deleted file mode 100644
--- a/include/asm-ppc/kmap_types.h
+++ /dev/null
@@ -1,25 +0,0 @@
-#ifdef __KERNEL__
-#ifndef _ASM_KMAP_TYPES_H
-#define _ASM_KMAP_TYPES_H
-
-enum km_type {
- KM_BOUNCE_READ,
- KM_SKB_SUNRPC_DATA,
- KM_SKB_DATA_SOFTIRQ,
- KM_USER0,
- KM_USER1,
- KM_BIO_SRC_IRQ,
- KM_BIO_DST_IRQ,
- KM_PTE0,
- KM_PTE1,
- KM_IRQ0,
- KM_IRQ1,
- KM_SOFTIRQ0,
- KM_SOFTIRQ1,
- KM_PPC_SYNC_PAGE,
- KM_PPC_SYNC_ICACHE,
- KM_TYPE_NR
-};
-
-#endif
-#endif /* __KERNEL__ */
diff --git a/include/asm-ppc64/kmap_types.h b/include/asm-ppc64/kmap_types.h
deleted file mode 100644
--- a/include/asm-ppc64/kmap_types.h
+++ /dev/null
@@ -1,23 +0,0 @@
-#ifdef __KERNEL__
-#ifndef _ASM_KMAP_TYPES_H
-#define _ASM_KMAP_TYPES_H
-
-enum km_type {
- KM_BOUNCE_READ,
- KM_SKB_SUNRPC_DATA,
- KM_SKB_DATA_SOFTIRQ,
- KM_USER0,
- KM_USER1,
- KM_BIO_SRC_IRQ,
- KM_BIO_DST_IRQ,
- KM_PTE0,
- KM_PTE1,
- KM_IRQ0,
- KM_IRQ1,
- KM_SOFTIRQ0,
- KM_SOFTIRQ1,
- KM_TYPE_NR
-};
-
-#endif
-#endif /* __KERNEL__ */
^ permalink raw reply
* Re: PATCH Merge more include files
From: Arnd Bergmann @ 2005-09-06 22:14 UTC (permalink / raw)
To: Jon Loeliger; +Cc: linuxppc64-dev, linuxppc-dev@ozlabs.org
In-Reply-To: <1126039597.25148.59.camel@cashmere.sps.mot.com>
On Dinsdag 06 September 2005 22:46, Jon Loeliger wrote:
>
> If you'd like, I'll submit a patch to use the static inline
> variant and rip out the definiton in the syscalls.c files.
Yes, that sounds good.
Thanks,
Arnd <><
^ permalink raw reply
* Re: [PATCH 0/3] Start the merge
From: Paul Mackerras @ 2005-09-06 22:49 UTC (permalink / raw)
To: Jon Loeliger; +Cc: linuxppc64-dev, linuxppc-dev@ozlabs.org
In-Reply-To: <1126037554.25148.41.camel@cashmere.sps.mot.com>
Jon Loeliger writes:
> I'd like to call attention to this buried patch. It appears that
> it might be lost due to Subject: line swiping; it likely hasn't
> gotten first class status as its own independent patch.
>
> Any chance we can get this one reviewed and pushed upstream too?
I went to send it on yesterday and found that it doesn't apply any
more. If Arnd or someone would like to update it, I'll send it on.
Paul.
^ permalink raw reply
* Re: [PATCH 0/3] Start the merge
From: Arnd Bergmann @ 2005-09-07 0:07 UTC (permalink / raw)
To: linuxppc64-dev; +Cc: linuxppc-dev@ozlabs.org
In-Reply-To: <17182.7390.886339.12876@cargo.ozlabs.ibm.com>
On Middeweken 07 September 2005 00:49, Paul Mackerras wrote:
> I went to send it on yesterday and found that it doesn't apply any
> more. If Arnd or someone would like to update it, I'll send it on.
>
Hmm. I don't get rejects against the git head. For which tree do
you want the patch?
Arnd <><
^ permalink raw reply
* Re: PATCH Merge more include files
From: Stephen Rothwell @ 2005-09-07 1:02 UTC (permalink / raw)
To: Jon Loeliger; +Cc: linuxppc64-dev, linuxppc-dev
In-Reply-To: <1126039509.25148.54.camel@cashmere.sps.mot.com>
[-- Attachment #1: Type: text/plain, Size: 955 bytes --]
On Tue, 06 Sep 2005 15:45:09 -0500 Jon Loeliger <jdl@freescale.com> wrote:
>
> I'll start using _ASM_POWERPC_ from now on. I will
> also submit a different patch to do a round of this
> sort of cleanup.
OK, thanks.
> Can we get an official call on the GPL header in
> include files? I'm defaulting to adding them for now.
And I've been removing them :-)
It actually often depends on which of the asm-ppc or asm-ppc64 files you actually
copy.
You are right, we need a statement.
> Thanks. More coming, of course.
Great.
> So, will you resubmit patches based on your 3/3 patch
> that cover the slid-through the cracks set, or shall I?
> I'm thinking pmac_features.h, dbdma.h, keylargo.h, etc.
I took those out because they were controversial and may require
some more thought about where they actually end up.
--
Cheers,
Stephen Rothwell sfr@canb.auug.org.au
http://www.canb.auug.org.au/~sfr/
[-- Attachment #2: Type: application/pgp-signature, Size: 189 bytes --]
^ permalink raw reply
* How can I compile the module into kernel
From: zhonglei @ 2005-09-07 7:34 UTC (permalink / raw)
To: linuxppc-embedded
hi:
My driver is a char device driver htm.o. How can I compile it into my kernel?
BestRegards
zhonglei
^ permalink raw reply
* lost "Using multi-level CPM interrupts" option
From: 徐小威的EMAIL @ 2005-09-07 8:43 UTC (permalink / raw)
To: linuxppc-embedded
Hi All:
I used patch file (patch-denx-linuxppc_2_4_devel-2005_06_23_1722)
to patch 2.4.25 Linux,
but this patch file didn't contain " Using multi-level CPM interrupts"
option.Why?
I used RTAI that version is stromboli and I want to run example
cpm_irqs.c.
Best Regards,
Rober Hsu
^ permalink raw reply
* ads8272 SEC problem on 2.4.18
From: Markus @ 2005-09-07 9:20 UTC (permalink / raw)
To: linuxppc-embedded
HiHo!
I am trying to get the SEC engine running on a ads8272
but i am completely stuck now. (It feels like the problem
we saw on this list last month, but there is still no solution
to that issue yet.
Quick Problem description:
initialize seems, ok, yet when i feed a single
dpd (for DES EU) into channel 0, the engine
seems to stuck during fetch. Nothing happens.
Questions:
- Can someone help me out? (Not sure if this is the right list for this?)
- Do (open) sources for the SEC1 (motorola/freescale) engine exist for vanilla linux?
(I know of Arabella, but they are neither open nor for vanilla linux)
ciao
Markus
P.S. some more details below
--------------------------------------------
more info:
- i hopefully initialized it correctly
- prepared a dpd
- wrote it into fetch register
- see that something happens: CurrentDescriptorPR changes
- boing, that's it... no more
some dumps:
Before writing the fetch register:
CryptoChannelConfigRegister (f0042008), 0x00000000 0x0000071c
CryptoChannelPointerStatusRegister (f0042010), 0x00000000 0x00000007
CryptoChannelCurrentDescriptorPointerRegister (f0042040), 0x00000000 0x00000000
CryptoChannelFetchDescriptorRegister (f0042048), 0x00000000 0x00000000
CryptoChannelDescriptorBufferRegister 0 (f0042080), 0x00000000
after writing to fetch register
CryptoChannelConfigRegister (f0042008), 0x00000000 0x0000071c
CryptoChannelPointerStatusRegister (f0042010), 0x00000002 0x00000007
CryptoChannelCurrentDescriptorPointerRegister (f0042040), 0x00000000 0x002e9a98
CryptoChannelFetchDescriptorRegister (f0042048), 0x00000000 0x00000000
CryptoChannelDescriptorBufferRegister 0 (f0042080), 0x00000000
CCPSR changes to 2 (error), but i don't know why?
Nothing else (at least nothing i can see) happens.
------------------------------------------------------
markus schaefer --- software engineer
epygi labs de gmbh
herrenstrasse 23
d-76133 karlsruhe, germany
tel: +49 (721) 205 96 30 -- fax: +49 (721) 205 96 59
sip: 20444@sip.epygi.com
*email removed, but it is easy to guess*
http://www.epygi.de
^ permalink raw reply
* Re: ads8272 SEC problem on 2.4.18
From: Vikas Aggarwal @ 2005-09-07 9:56 UTC (permalink / raw)
To: Markus; +Cc: linuxppc-embedded
In-Reply-To: <BDEHJGPIKNLKJJBCCFPLCEOOCPAA.listuser@epygi.de>
I had the similar error with SEC1 for 8248. My RNG DPD could not generate
desired result. After DPD address written my ISR was invoked but all i had
is TEA error, or bus error etc when i checked the Status Registers.
regards
-vikas
> HiHo!
>
> I am trying to get the SEC engine running on a ads8272
> but i am completely stuck now. (It feels like the problem
> we saw on this list last month, but there is still no solution
> to that issue yet.
>
> Quick Problem description:
> initialize seems, ok, yet when i feed a single
> dpd (for DES EU) into channel 0, the engine
> seems to stuck during fetch. Nothing happens.
>
> Questions:
> - Can someone help me out? (Not sure if this is the right list for this?)
> - Do (open) sources for the SEC1 (motorola/freescale) engine exist for
> vanilla linux?
> (I know of Arabella, but they are neither open nor for vanilla linux)
>
> ciao
> Markus
>
> P.S. some more details below
> --------------------------------------------
> more info:
> - i hopefully initialized it correctly
> - prepared a dpd
> - wrote it into fetch register
> - see that something happens: CurrentDescriptorPR changes
> - boing, that's it... no more
>
> some dumps:
> Before writing the fetch register:
> CryptoChannelConfigRegister (f0042008), 0x00000000 0x0000071c
> CryptoChannelPointerStatusRegister (f0042010), 0x00000000 0x00000007
> CryptoChannelCurrentDescriptorPointerRegister (f0042040), 0x00000000
> 0x00000000
> CryptoChannelFetchDescriptorRegister (f0042048), 0x00000000 0x00000000
> CryptoChannelDescriptorBufferRegister 0 (f0042080), 0x00000000
>
> after writing to fetch register
> CryptoChannelConfigRegister (f0042008), 0x00000000 0x0000071c
> CryptoChannelPointerStatusRegister (f0042010), 0x00000002 0x00000007
> CryptoChannelCurrentDescriptorPointerRegister (f0042040), 0x00000000
> 0x002e9a98
> CryptoChannelFetchDescriptorRegister (f0042048), 0x00000000 0x00000000
> CryptoChannelDescriptorBufferRegister 0 (f0042080), 0x00000000
>
> CCPSR changes to 2 (error), but i don't know why?
> Nothing else (at least nothing i can see) happens.
> ------------------------------------------------------
> markus schaefer --- software engineer
> epygi labs de gmbh
> herrenstrasse 23
> d-76133 karlsruhe, germany
> tel: +49 (721) 205 96 30 -- fax: +49 (721) 205 96 59
> sip: 20444@sip.epygi.com
> *email removed, but it is easy to guess*
> http://www.epygi.de
>
> _______________________________________________
> Linuxppc-embedded mailing list
> Linuxppc-embedded@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-embedded
>
^ permalink raw reply
* newbie question : how to register for a new interrupt
From: Nuguru Susheel @ 2005-09-07 14:14 UTC (permalink / raw)
To: linuxppc-embedded
Hi all,
I have written an service routine for handling the GPIO_WAKEUP
interrupt PSC2_4 pin (MPC5200 Core), but I donno how to register this
routine into the kernel.
I have connected an external circuit which generates interrupts to this
PSC2_4 pin, but I believe the Core doesnt know what to do when this
interrupt is generated without registering this routine ...
Help/Suggestions/Redirections please .......
--Cheers
nSr
^ permalink raw reply
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