* Re: cpu features testing 32 vs 64 bit
From: Pantelis Antoniou @ 2005-09-08 21:08 UTC (permalink / raw)
To: linuxppc-embedded; +Cc: linuxppc-dev, linuxppc64-dev
In-Reply-To: <1729b6f2a199a759c4daeadd3ddcdc4a@freescale.com>
On Friday 09 September 2005 00:02, Becky Bruce wrote:
> So,
>
> in include/asm-ppc64/cacheflush.h is the following:
>
> static inline void flush_icache_range(unsigned long start, unsigned
> long stop)
> {
> if (!cpu_has_feature(CPU_FTR_COHERENT_ICACHE))
> __flush_icache_range(start, stop);
> }
>
> On the 32-bit side, we don't need the feature test -
> CPU_FTR_COHERENT_CACHE is only defined in 64-bit land, and has bits set
> in the upper 32.
>
Oh yes we need it. 8xx is non coherent.
> There's a couple of ways to deal with merging this:
>
> 1) The ever-so-popular #ifdef __powerpc64__around the cpu_has_feature
> test
> 2) No ifdef in the code itself, but #define CPU_FTR_WHATEVER to be 0
> when !__powerpc64__ in cputable.h so that the cpu_has_feature test will
> always fail for 32-bit.
>
> I'd like to get some opinions on this. Do folks feel like the
> performance hit of doing the compare is enough to justify going with
> method 1? Should we be using likely/unlikely with the feature test?
>
> This is just one code example - I suspect there will be others as we
> continue the merge, and the importance of performance may differ
> depending on where in the code we are.
>
> Thanks!
> -B
>
Regards
Pantelis
^ permalink raw reply
* [PATCH] ppc: Merge tlb.h
From: Kumar Gala @ 2005-09-08 21:11 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev, linux-kernel, linuxppc64-dev
Merged tlb.h between asm-ppc32 and asm-ppc64 into asm-powerpc. Also, fixed
a compiler warning in arch/ppc/mm/tlb.c since it was roughly related.
Signed-off-by: Kumar K. Gala <kumar.gala@freescale.com>
---
commit c5f0c343d08ad9c6862c1755e7b2239f31a2a633
tree c80721ace951bc55b14a8f2a3bf69599bca2e8e9
parent cebb2b156319990fc2fba615bbfeac81be62a86a
author Kumar K. Gala <kumar.gala@freescale.com> Thu, 08 Sep 2005 16:09:42 -0500
committer Kumar K. Gala <kumar.gala@freescale.com> Thu, 08 Sep 2005 16:09:42 -0500
arch/ppc/mm/tlb.c | 1 +
include/asm-powerpc/tlb.h | 50 +++++++++++++++++++++++++++++++++++++++
include/asm-ppc/tlb.h | 57 ---------------------------------------------
include/asm-ppc64/tlb.h | 39 -------------------------------
4 files changed, 51 insertions(+), 96 deletions(-)
diff --git a/arch/ppc/mm/tlb.c b/arch/ppc/mm/tlb.c
--- a/arch/ppc/mm/tlb.c
+++ b/arch/ppc/mm/tlb.c
@@ -28,6 +28,7 @@
#include <linux/mm.h>
#include <linux/init.h>
#include <linux/highmem.h>
+#include <linux/pagemap.h>
#include <asm/tlbflush.h>
#include <asm/tlb.h>
diff --git a/include/asm-powerpc/tlb.h b/include/asm-powerpc/tlb.h
new file mode 100644
--- /dev/null
+++ b/include/asm-powerpc/tlb.h
@@ -0,0 +1,50 @@
+#ifndef _ASM_POWERPC_TLB_H
+#define _ASM_POWERPC_TLB_H
+
+#include <asm/tlbflush.h>
+#include <asm/page.h>
+
+/* Nothing needed here in fact... */
+#define tlb_start_vma(tlb, vma) do { } while (0)
+#define tlb_end_vma(tlb, vma) do { } while (0)
+
+/* Avoid pulling in another include just for this */
+#define check_pgt_cache() do { } while (0)
+
+#if defined(CONFIG_PPC64)
+struct mmu_gather;
+
+extern void pte_free_finish(void);
+
+#define __tlb_remove_tlb_entry(tlb, pte, address) do { } while (0)
+static inline void tlb_flush(struct mmu_gather *tlb)
+{
+ flush_tlb_pending();
+ pte_free_finish();
+}
+#elif defined(CONFIG_PPC_STD_MMU)
+/* Classic PPC with hash-table based MMU... */
+
+struct mmu_gather;
+extern void tlb_flush(struct mmu_gather *tlb);
+extern void flush_hash_entry(struct mm_struct *mm, pte_t *ptep,
+ unsigned long address);
+#else
+/* Embedded PPC with software-loaded TLB, very simple... */
+
+#define __tlb_remove_tlb_entry(tlb, pte, address) do { } while (0)
+#define tlb_flush(tlb) flush_tlb_mm((tlb)->mm)
+#endif /* CONFIG_PPC64 */
+
+/* Get the generic bits... */
+#include <asm-generic/tlb.h>
+
+#ifdef CONFIG_PPC_STD_MMU
+static inline void __tlb_remove_tlb_entry(struct mmu_gather *tlb, pte_t *ptep,
+ unsigned long address)
+{
+ if (pte_val(*ptep) & _PAGE_HASHPTE)
+ flush_hash_entry(tlb->mm, ptep, address);
+}
+#endif /* CONFIG_PPC_STD_MMU */
+#endif /* _ASM_POWERPC_TLB_H */
diff --git a/include/asm-ppc/tlb.h b/include/asm-ppc/tlb.h
deleted file mode 100644
--- a/include/asm-ppc/tlb.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * TLB shootdown specifics for PPC
- *
- * Copyright (C) 2002 Paul Mackerras, IBM Corp.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-#ifndef _PPC_TLB_H
-#define _PPC_TLB_H
-
-#include <linux/config.h>
-#include <asm/pgtable.h>
-#include <asm/pgalloc.h>
-#include <asm/tlbflush.h>
-#include <asm/page.h>
-#include <asm/mmu.h>
-
-#ifdef CONFIG_PPC_STD_MMU
-/* Classic PPC with hash-table based MMU... */
-
-struct mmu_gather;
-extern void tlb_flush(struct mmu_gather *tlb);
-
-/* Get the generic bits... */
-#include <asm-generic/tlb.h>
-
-/* Nothing needed here in fact... */
-#define tlb_start_vma(tlb, vma) do { } while (0)
-#define tlb_end_vma(tlb, vma) do { } while (0)
-
-extern void flush_hash_entry(struct mm_struct *mm, pte_t *ptep,
- unsigned long address);
-
-static inline void __tlb_remove_tlb_entry(struct mmu_gather *tlb, pte_t *ptep,
- unsigned long address)
-{
- if (pte_val(*ptep) & _PAGE_HASHPTE)
- flush_hash_entry(tlb->mm, ptep, address);
-}
-
-#else
-/* Embedded PPC with software-loaded TLB, very simple... */
-
-#define tlb_start_vma(tlb, vma) do { } while (0)
-#define tlb_end_vma(tlb, vma) do { } while (0)
-#define __tlb_remove_tlb_entry(tlb, pte, address) do { } while (0)
-#define tlb_flush(tlb) flush_tlb_mm((tlb)->mm)
-
-/* Get the generic bits... */
-#include <asm-generic/tlb.h>
-
-#endif /* CONFIG_PPC_STD_MMU */
-
-#endif /* __PPC_TLB_H */
diff --git a/include/asm-ppc64/tlb.h b/include/asm-ppc64/tlb.h
deleted file mode 100644
--- a/include/asm-ppc64/tlb.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * TLB shootdown specifics for PPC64
- *
- * Copyright (C) 2002 Anton Blanchard, IBM Corp.
- * Copyright (C) 2002 Paul Mackerras, IBM Corp.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-#ifndef _PPC64_TLB_H
-#define _PPC64_TLB_H
-
-#include <asm/tlbflush.h>
-
-struct mmu_gather;
-
-extern void pte_free_finish(void);
-
-static inline void tlb_flush(struct mmu_gather *tlb)
-{
- flush_tlb_pending();
- pte_free_finish();
-}
-
-/* Avoid pulling in another include just for this */
-#define check_pgt_cache() do { } while (0)
-
-/* Get the generic bits... */
-#include <asm-generic/tlb.h>
-
-/* Nothing needed here in fact... */
-#define tlb_start_vma(tlb, vma) do { } while (0)
-#define tlb_end_vma(tlb, vma) do { } while (0)
-
-#define __tlb_remove_tlb_entry(tlb, pte, address) do { } while (0)
-
-#endif /* _PPC64_TLB_H */
^ permalink raw reply
* Re: cpu features testing 32 vs 64 bit
From: Kumar Gala @ 2005-09-08 21:20 UTC (permalink / raw)
To: pantelis.antoniou; +Cc: linuxppc64-dev, linuxppc-dev, linuxppc-embedded
In-Reply-To: <200509090008.39692.pantelis.antoniou@gmail.com>
On Sep 8, 2005, at 4:08 PM, Pantelis Antoniou wrote:
> On Friday 09 September 2005 00:02, Becky Bruce wrote:
>
>> So,
>>
>> in include/asm-ppc64/cacheflush.h is the following:
>>
>> static inline void flush_icache_range(unsigned long start, unsigned
>> long stop)
>> {
>> if (!cpu_has_feature(CPU_FTR_COHERENT_ICACHE))
>> __flush_icache_range(start, stop);
>> }
>>
>> On the 32-bit side, we don't need the feature test -
>> CPU_FTR_COHERENT_CACHE is only defined in 64-bit land, and has
>> bits set
>> in the upper 32.
>>
>>
>
> Oh yes we need it. 8xx is non coherent.
I think she lost the I in ICACHE... its a power5 only feature at this
point.
- kumar
^ permalink raw reply
* Re: cpu features testing 32 vs 64 bit
From: Dan Malek @ 2005-09-08 21:48 UTC (permalink / raw)
To: Kumar Gala
Cc: linuxppc64-dev, linuxppc-dev, pantelis.antoniou,
linuxppc-embedded
In-Reply-To: <D8DEC759-EAB9-457F-AF7B-A10D6593B27A@freescale.com>
On Sep 8, 2005, at 5:20 PM, Kumar Gala wrote:
>>> if (!cpu_has_feature(CPU_FTR_COHERENT_ICACHE))
>>> __flush_icache_range(start, stop);
>>> }
If we #define CPU_FTR_xxx as a 0 or all 1's for processors that have
or don't have these features, will the compiler be smart enough to
recognize an always true or false condition and remove the
test (or code as appropriate)?
Thanks.
-- Dan
^ permalink raw reply
* Re: r13 is non-volatile?
From: Benjamin Herrenschmidt @ 2005-09-08 21:53 UTC (permalink / raw)
To: linas; +Cc: ppc64-dev, linuxppc-dev list
In-Reply-To: <20050908193053.GO30028@austin.ibm.com>
> There's a different value in R13 depending on which cpu you're on,
> so one mustn't save R13 on one CPU and attempt to restore it on
> another.
>
> Maybe, for ppc32, you can pretend that r13 "is like a paca"? So
> that instead of saving/restoring r13 like this, you could set it up
> at the same time/instead of setting up the paca r13?
ppc32 uses r2 for that, it contains "current".
I don't think we need to bother merging those low level CPU specific
things. We need to have a cpu32 and a cpu64 subdirs in there for things
like these, memory management, etc... imho.
Ben.
^ permalink raw reply
* Re: cpu features testing 32 vs 64 bit
From: Kumar Gala @ 2005-09-08 22:02 UTC (permalink / raw)
To: Dan Malek
Cc: linuxppc64-dev, linuxppc-dev, pantelis.antoniou,
linuxppc-embedded
In-Reply-To: <f2ea45e1b2a9689c450811a61ed46183@embeddededge.com>
On Sep 8, 2005, at 4:48 PM, Dan Malek wrote:
>
> On Sep 8, 2005, at 5:20 PM, Kumar Gala wrote:
>
>
>>>> if (!cpu_has_feature(CPU_FTR_COHERENT_ICACHE))
>>>> __flush_icache_range(start, stop);
>>>> }
>>>>
>
> If we #define CPU_FTR_xxx as a 0 or all 1's for processors that have
> or don't have these features, will the compiler be smart enough to
> recognize an always true or false condition and remove the
> test (or code as appropriate)?
The compiler is smart enough in this case since cpu_has_feature() is
an inline function.
- kumar
^ permalink raw reply
* Re: cpu features testing 32 vs 64 bit
From: Dan Malek @ 2005-09-08 22:20 UTC (permalink / raw)
To: Kumar Gala
Cc: linuxppc64-dev, linuxppc-dev, linuxppc-embedded,
pantelis.antoniou
In-Reply-To: <39A39EEE-E3B1-4D34-BC6E-854C3EF56C7D@freescale.com>
On Sep 8, 2005, at 6:02 PM, Kumar Gala wrote:
> The compiler is smart enough in this case since cpu_has_feature() is
> an inline function.
I guess I didn't read Becky's comments close enough, but she did
suggest this. I was trying to eliminate the #ifdef, but I guess we will
need it some place.
Thanks.
-- Dan
^ permalink raw reply
* Re: MPC5200 Linux Init Problem
From: Frank Beesley @ 2005-09-08 22:19 UTC (permalink / raw)
To: Bob Peterson; +Cc: Jeff Angielski, linuxppc-embedded
In-Reply-To: <6.2.3.4.1.20050908091250.01eea878@mail.int.acdstar.com>
> Hi Frank,
>
> I recommend you first try to boot using tftp to get your kernel and
> nfs to get
> your root filesystem. Once that boots, you can play with MTD to make
> sure
> your flash chips have full addressability and all, and you can mount your
> jffs partition manually and look at it from the client.
>
> Also, it would be interesting to see what u-boot messages you receive at
> power-on. You may also want to do a printenv command in u-boot and
> post what your u-boot settings are.
>
> Regards,
>
> Bob Peterson
> Advanced Communication Design
>
Here is the Uboot message and env:
U-Boot 1.1.3-ppc-0_3 (Aug 31 2005 - 17:55:35)
CPU: MPC5200 v1.2 at 396
MHz
Bus 132 MHz, IPB 66 MHz, PCI 66
MHz
Board: Aeroflex-Wichita
CAI
DRAM: 128
MB
FLASH: 32
MB
Using default
environment
In:
serial
Out:
serial
Err:
serial
Autostarting. Press any key to
abort..
Hit any key to stop autoboot:
0
Eric-CAI=>
printenv
bootcmd=bootm
FA200000
bootdelay=10
baudrate=115200
preboot=echo;echo Autostarting. Press any key to
abort..;echo
bootargs=root=/dev/mtdblock2
Environment size: 144/65532 bytes
I don't have an ethernet connection on my custom board - bummer. TFTP
and NFS are out. To further explain my custom board, I have an Intel
host (running linux also) that is connected to an FPGA over the PCI bus.
The FPGA then shares the flash interface with the MPC5200. The Intel
host maps the flash using MTD drivers, writes the images, then releases
the flash to the MPC5200. At that point the MPC5200 is brought out of
reset and boots from flash. I have the flash partitioned for uboot,
kernel, rootfs, and a spare data partition. Uboot is at FA000000 (CS1
after initial assembly setup), kernel is at FA200000, rootfs is at
FA800000, spare is at FB800000.
0x00000000-0x00200000 :
"UBoot"
0x00200000-0x00800000 :
"Kernel"
0x00800000-0x01800000 :
"Rootfs"
0x01800000-0x02000000 :
"Cals"
The rootfs is crossing my CS1-CS2 boundary (FA000000, FB000000). I tried
putting my rootfs image in the cals partitions and changed my boot args
to /dev/mtdblock3. This didn't seem to change things. I believe my chip
selects are working properly - this does not rule out the MTD driver
though. I am working on a test now that tests (from uboot) the 30 MB of
flash area beyond uboot.
Any other ideas?
Frank
^ permalink raw reply
* Re: cpu features testing 32 vs 64 bit
From: Arnd Bergmann @ 2005-09-08 22:36 UTC (permalink / raw)
To: linuxppc64-dev; +Cc: linuxppc-dev, linuxppc-embedded, pantelis.antoniou
In-Reply-To: <39A39EEE-E3B1-4D34-BC6E-854C3EF56C7D@freescale.com>
On Freedag 09 September 2005 00:02, Kumar Gala wrote:
>
> On Sep 8, 2005, at 4:48 PM, Dan Malek wrote:
> >
> > If we #define CPU_FTR_xxx as a 0 or all 1's for processors that have
> > or don't have these features, will the compiler be smart enough to
> > recognize an always true or false condition and remove the
> > test (or code as appropriate)?
>
> The compiler is smart enough in this case since cpu_has_feature() is
> an inline function.
I actually wrote a patch that solves the problem in a very generic way,
see http://patchwork.ozlabs.org/linuxppc/patch?id=1048 .
I don't remember exactly if there were serious objections against
the patch at that time, but it looks like a much cleaner solution to me
than defining CPU_FTR_xxx to different values depending on the
configuration.
Arnd <><
^ permalink raw reply
* Re: [PATCH] ppc: Merge tlb.h
From: Benjamin Herrenschmidt @ 2005-09-08 23:56 UTC (permalink / raw)
To: Kumar Gala; +Cc: linuxppc-dev, linux-kernel, linuxppc64-dev
In-Reply-To: <Pine.LNX.4.61.0509081611230.5055@nylon.am.freescale.net>
On Thu, 2005-09-08 at 16:11 -0500, Kumar Gala wrote:
> Merged tlb.h between asm-ppc32 and asm-ppc64 into asm-powerpc. Also, fixed
> a compiler warning in arch/ppc/mm/tlb.c since it was roughly related.
>
> Signed-off-by: Kumar K. Gala <kumar.gala@freescale.com>
Do we want to do that ?
Replacing 2 different files with one split in #ifdef isn't a progress...
As I said, I think we need two subdirs for the low level stuffs that is
different, and that includes at this point all of the memory management
related stuff.
In addition, I'd appreciate if we could avoid touching ppc64 mm related
files completely for a couple of weeks as I'm working on a fairly big
patch that I'm really tired of having to rebase all the time ;)
Ben.
^ permalink raw reply
* Re: cpu features testing 32 vs 64 bit
From: David Gibson @ 2005-09-09 0:08 UTC (permalink / raw)
To: Arnd Bergmann
Cc: linuxppc64-dev, pantelis.antoniou, linuxppc-embedded,
linuxppc-dev
In-Reply-To: <200509090036.39992.arnd@arndb.de>
On Fri, Sep 09, 2005 at 12:36:39AM +0200, Arnd Bergmann wrote:
> On Freedag 09 September 2005 00:02, Kumar Gala wrote:
> >
> > On Sep 8, 2005, at 4:48 PM, Dan Malek wrote:
> > >
> > > If we #define CPU_FTR_xxx as a 0 or all 1's for processors that have
> > > or don't have these features, will the compiler be smart enough to
> > > recognize an always true or false condition and remove the
> > > test (or code as appropriate)?
> >
> > The compiler is smart enough in this case since cpu_has_feature() is
> > an inline function.
>
> I actually wrote a patch that solves the problem in a very generic way,
> see http://patchwork.ozlabs.org/linuxppc/patch?id=1048 .
> I don't remember exactly if there were serious objections against
> the patch at that time, but it looks like a much cleaner solution to me
> than defining CPU_FTR_xxx to different values depending on the
> configuration.
And we already use a mechanism essentially identical to Arnd's for
fw_has_feature().
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/people/dgibson
^ permalink raw reply
* Re: r13 is non-volatile?
From: Kumar Gala @ 2005-09-09 1:30 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: ppc64-dev, linas, linuxppc-dev list
In-Reply-To: <1126216432.29803.31.camel@gaston>
On Sep 8, 2005, at 4:53 PM, Benjamin Herrenschmidt wrote:
>
>
>> There's a different value in R13 depending on which cpu you're on,
>> so one mustn't save R13 on one CPU and attempt to restore it on
>> another.
>>
>> Maybe, for ppc32, you can pretend that r13 "is like a paca"? So
>> that instead of saving/restoring r13 like this, you could set it up
>> at the same time/instead of setting up the paca r13?
>>
>
> ppc32 uses r2 for that, it contains "current".
>
> I don't think we need to bother merging those low level CPU specific
> things. We need to have a cpu32 and a cpu64 subdirs in there for
> things
> like these, memory management, etc... imho.
My intent is to see if we can make a change so that there isn't an
ifdef.
- kumar
^ permalink raw reply
* Re: [PATCH] ppc: Merge tlb.h
From: Kumar Gala @ 2005-09-09 1:34 UTC (permalink / raw)
To: Benjamin Herrenschmidt
Cc: linuxppc-dev, linux-kernel, Gala Kumar K.-galak, linuxppc64-dev
In-Reply-To: <1126223767.29803.34.camel@gaston>
On Sep 8, 2005, at 6:56 PM, Benjamin Herrenschmidt wrote:
> On Thu, 2005-09-08 at 16:11 -0500, Kumar Gala wrote:
>
>> Merged tlb.h between asm-ppc32 and asm-ppc64 into asm-powerpc. Also,
>>
> fixed
>
>> a compiler warning in arch/ppc/mm/tlb.c since it was roughly related.
>>
>> Signed-off-by: Kumar K. Gala <kumar.gala@freescale.com>
>>
>
> Do we want to do that ?
>
> Replacing 2 different files with one split in #ifdef isn't a
> progress...
> As I said, I think we need two subdirs for the low level stuffs
> that is
> different, and that includes at this point all of the memory
> management
> related stuff.
I understand, but I'm also not sure if its progress to duplicate a
major of a file that is common.
In this case it might be better handled by having specific versions
per "sub-arch". I think the key is determining which files should be
handled via sub-arch diffs and which should be handled via ifdef's in
the file.
Some cases like ppc_asm are so similar that it seems better to have a
single file and ifdef the specific case.
> In addition, I'd appreciate if we could avoid touching ppc64 mm
> related
> files completely for a couple of weeks as I'm working on a fairly big
> patch that I'm really tired of having to rebase all the time ;)
Will avoid touch any other mm related headers than :)
- kumar
^ permalink raw reply
* Time for linuxpowerpc-dev?
From: Michael Ellerman @ 2005-09-09 2:25 UTC (permalink / raw)
To: linuxppc64-dev, linuxppc-dev
[-- Attachment #1: Type: text/plain, Size: 406 bytes --]
With the arch's merging, and all this cross-posting maddness, is it time to
start a linuxpowerpc-dev mailing list?
cheers
--
Michael Ellerman
IBM OzLabs
email: michael:ellerman.id.au
inmsg: mpe:jabber.org
wwweb: http://michael.ellerman.id.au
phone: +61 2 6212 1183 (tie line 70 21183)
We do not inherit the earth from our ancestors,
we borrow it from our children. - S.M.A.R.T Person
[-- Attachment #2: Type: application/pgp-signature, Size: 189 bytes --]
^ permalink raw reply
* [PATCH] powerpc: merge include/asm/cputable.h
From: Arnd Bergmann @ 2005-09-09 4:23 UTC (permalink / raw)
To: linuxppc64-dev; +Cc: linuxppc-dev, pantelis.antoniou, linuxppc-embedded
In-Reply-To: <200509090036.39992.arnd@arndb.de>
This is an updated version of my old patch that creates a more optimized
version of cpu_has_feature(). This version actually combines
asm-ppc/cputable.h and asm-ppc64/cputable.h, which turned out to be
a lot more work than only the 64 bit version.
The 64 bit parts a relatively straightforward port of my earlier work
which I tested in a number of configurations. The 32 bit parts are
not tested at all, all I did was compiling the ppc defconfig with this.
I think it is best if I hand the patch over to Kumar and Becky for
further testing and cleaning up the remaining bits in the new
file, as they appear to have invested some thought in it already.
This version still has a number of #ifdef __powerpc64__ that should
probably go away in the process.
The patch also relies on having the ASM_CONST() macro in ppc_asm.h,
as proposed by Kumar Gala, so it won't work on the current git
head without that change.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
--
clean-cg/arch/ppc/kernel/cputable.c | 401 +++++----------------------
clean-cg/arch/ppc64/Kconfig | 30 ++
clean-cg/arch/ppc64/kernel/cputable.c | 82 +----
clean-cg/include/asm-powerpc/cputable.h | 475 ++++++++++++++++++++++++++++++++
include/asm-ppc/cputable.h | 128 --------
include/asm-ppc64/cputable.h | 167 -----------
Index: clean-cg/include/asm-ppc64/cputable.h
===================================================================
--- clean-cg.orig/include/asm-ppc64/cputable.h
+++ /dev/null
@@ -1,167 +0,0 @@
-/*
- * include/asm-ppc64/cputable.h
- *
- * Copyright (C) 2001 Ben. Herrenschmidt (benh@kernel.crashing.org)
- *
- * Modifications for ppc64:
- * Copyright (C) 2003 Dave Engebretsen <engebret@us.ibm.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef __ASM_PPC_CPUTABLE_H
-#define __ASM_PPC_CPUTABLE_H
-
-#include <linux/config.h>
-#include <asm/page.h> /* for ASM_CONST */
-
-/* Exposed to userland CPU features - Must match ppc32 definitions */
-#define PPC_FEATURE_32 0x80000000
-#define PPC_FEATURE_64 0x40000000
-#define PPC_FEATURE_601_INSTR 0x20000000
-#define PPC_FEATURE_HAS_ALTIVEC 0x10000000
-#define PPC_FEATURE_HAS_FPU 0x08000000
-#define PPC_FEATURE_HAS_MMU 0x04000000
-#define PPC_FEATURE_HAS_4xxMAC 0x02000000
-#define PPC_FEATURE_UNIFIED_CACHE 0x01000000
-
-#ifdef __KERNEL__
-
-#ifndef __ASSEMBLY__
-
-/* This structure can grow, it's real size is used by head.S code
- * via the mkdefs mechanism.
- */
-struct cpu_spec;
-struct op_ppc64_model;
-
-typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec);
-
-struct cpu_spec {
- /* CPU is matched via (PVR & pvr_mask) == pvr_value */
- unsigned int pvr_mask;
- unsigned int pvr_value;
-
- char *cpu_name;
- unsigned long cpu_features; /* Kernel features */
- unsigned int cpu_user_features; /* Userland features */
-
- /* cache line sizes */
- unsigned int icache_bsize;
- unsigned int dcache_bsize;
-
- /* number of performance monitor counters */
- unsigned int num_pmcs;
-
- /* this is called to initialize various CPU bits like L1 cache,
- * BHT, SPD, etc... from head.S before branching to identify_machine
- */
- cpu_setup_t cpu_setup;
-
- /* Used by oprofile userspace to select the right counters */
- char *oprofile_cpu_type;
-
- /* Processor specific oprofile operations */
- struct op_ppc64_model *oprofile_model;
-};
-
-extern struct cpu_spec cpu_specs[];
-extern struct cpu_spec *cur_cpu_spec;
-
-static inline unsigned long cpu_has_feature(unsigned long feature)
-{
- return cur_cpu_spec->cpu_features & feature;
-}
-
-#endif /* __ASSEMBLY__ */
-
-/* CPU kernel features */
-
-/* Retain the 32b definitions for the time being - use bottom half of word */
-#define CPU_FTR_SPLIT_ID_CACHE ASM_CONST(0x0000000000000001)
-#define CPU_FTR_L2CR ASM_CONST(0x0000000000000002)
-#define CPU_FTR_SPEC7450 ASM_CONST(0x0000000000000004)
-#define CPU_FTR_ALTIVEC ASM_CONST(0x0000000000000008)
-#define CPU_FTR_TAU ASM_CONST(0x0000000000000010)
-#define CPU_FTR_CAN_DOZE ASM_CONST(0x0000000000000020)
-#define CPU_FTR_USE_TB ASM_CONST(0x0000000000000040)
-#define CPU_FTR_604_PERF_MON ASM_CONST(0x0000000000000080)
-#define CPU_FTR_601 ASM_CONST(0x0000000000000100)
-#define CPU_FTR_HPTE_TABLE ASM_CONST(0x0000000000000200)
-#define CPU_FTR_CAN_NAP ASM_CONST(0x0000000000000400)
-#define CPU_FTR_L3CR ASM_CONST(0x0000000000000800)
-#define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x0000000000001000)
-#define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x0000000000002000)
-#define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x0000000000004000)
-
-/* Add the 64b processor unique features in the top half of the word */
-#define CPU_FTR_SLB ASM_CONST(0x0000000100000000)
-#define CPU_FTR_16M_PAGE ASM_CONST(0x0000000200000000)
-#define CPU_FTR_TLBIEL ASM_CONST(0x0000000400000000)
-#define CPU_FTR_NOEXECUTE ASM_CONST(0x0000000800000000)
-#define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000001000000000)
-#define CPU_FTR_IABR ASM_CONST(0x0000002000000000)
-#define CPU_FTR_MMCRA ASM_CONST(0x0000004000000000)
-/* unused ASM_CONST(0x0000008000000000) */
-#define CPU_FTR_SMT ASM_CONST(0x0000010000000000)
-#define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x0000020000000000)
-#define CPU_FTR_LOCKLESS_TLBIE ASM_CONST(0x0000040000000000)
-#define CPU_FTR_MMCRA_SIHV ASM_CONST(0x0000080000000000)
-#define CPU_FTR_CTRL ASM_CONST(0x0000100000000000)
-
-#ifndef __ASSEMBLY__
-
-#define COMMON_USER_PPC64 (PPC_FEATURE_32 | PPC_FEATURE_64 | \
- PPC_FEATURE_HAS_FPU | PPC_FEATURE_HAS_MMU)
-
-#define CPU_FTR_PPCAS_ARCH_V2_BASE (CPU_FTR_SLB | \
- CPU_FTR_TLBIEL | CPU_FTR_NOEXECUTE | \
- CPU_FTR_NODSISRALIGN | CPU_FTR_CTRL)
-
-/* iSeries doesn't support large pages */
-#ifdef CONFIG_PPC_ISERIES
-#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_PPCAS_ARCH_V2_BASE)
-#else
-#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_PPCAS_ARCH_V2_BASE | CPU_FTR_16M_PAGE)
-#endif /* CONFIG_PPC_ISERIES */
-
-#endif /* __ASSEMBLY */
-
-#ifdef __ASSEMBLY__
-
-#define BEGIN_FTR_SECTION 98:
-
-#define END_FTR_SECTION(msk, val) \
-99: \
- .section __ftr_fixup,"a"; \
- .align 3; \
- .llong msk; \
- .llong val; \
- .llong 98b; \
- .llong 99b; \
- .previous
-
-#else
-
-#define BEGIN_FTR_SECTION "98:\n"
-#define END_FTR_SECTION(msk, val) \
-"99:\n" \
-" .section __ftr_fixup,\"a\";\n" \
-" .align 3;\n" \
-" .llong "#msk";\n" \
-" .llong "#val";\n" \
-" .llong 98b;\n" \
-" .llong 99b;\n" \
-" .previous\n"
-
-#endif /* __ASSEMBLY__ */
-
-#define END_FTR_SECTION_IFSET(msk) END_FTR_SECTION((msk), (msk))
-#define END_FTR_SECTION_IFCLR(msk) END_FTR_SECTION((msk), 0)
-
-#endif /* __ASM_PPC_CPUTABLE_H */
-#endif /* __KERNEL__ */
-
Index: clean-cg/arch/ppc64/Kconfig
===================================================================
--- clean-cg.orig/arch/ppc64/Kconfig
+++ clean-cg/arch/ppc64/Kconfig
@@ -125,6 +125,36 @@ config BPA_IIC
bool
default y
+config CPU_POWER3
+ bool
+ default y
+ depends on (PPC_ISERIES || PPC_PSERIES) && !POWER4_ONLY
+
+config CPU_RS64
+ bool
+ default y
+ depends on (PPC_ISERIES || PPC_PSERIES) && !POWER4_ONLY
+
+config CPU_POWER4
+ bool
+ default y
+ depends on PPC_ISERIES || PPC_PSERIES
+
+config CPU_PPC970
+ bool
+ default y
+ depends on PPC_PSERIES || PPC_PMAC || PPC_MAPLE
+
+config CPU_POWER5
+ bool
+ default y
+ depends on PPC_PSERIES
+
+config CPU_CELL
+ bool
+ default y
+ depends on PPC_BPA
+
# VMX is pSeries only for now until somebody writes the iSeries
# exception vectors for it
config ALTIVEC
Index: clean-cg/arch/ppc64/kernel/cputable.c
===================================================================
--- clean-cg.orig/arch/ppc64/kernel/cputable.c
+++ clean-cg/arch/ppc64/kernel/cputable.c
@@ -37,26 +37,13 @@ extern void __setup_cpu_power4(unsigned
extern void __setup_cpu_ppc970(unsigned long offset, struct cpu_spec* spec);
extern void __setup_cpu_be(unsigned long offset, struct cpu_spec* spec);
-
-/* We only set the altivec features if the kernel was compiled with altivec
- * support
- */
-#ifdef CONFIG_ALTIVEC
-#define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC
-#define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
-#else
-#define CPU_FTR_ALTIVEC_COMP 0
-#define PPC_FEATURE_HAS_ALTIVEC_COMP 0
-#endif
-
struct cpu_spec cpu_specs[] = {
{ /* Power3 */
.pvr_mask = 0xffff0000,
.pvr_value = 0x00400000,
.cpu_name = "POWER3 (630)",
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
- CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR,
- .cpu_user_features = COMMON_USER_PPC64,
+ .cpu_features = CPU_FTR_POWER3,
+ .cpu_user_features = COMMON_USER_PPC64,
.icache_bsize = 128,
.dcache_bsize = 128,
.num_pmcs = 8,
@@ -70,8 +57,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffff0000,
.pvr_value = 0x00410000,
.cpu_name = "POWER3 (630+)",
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
- CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR,
+ .cpu_features = CPU_FTR_POWER3,
.cpu_user_features = COMMON_USER_PPC64,
.icache_bsize = 128,
.dcache_bsize = 128,
@@ -86,9 +72,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffff0000,
.pvr_value = 0x00330000,
.cpu_name = "RS64-II (northstar)",
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
- CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
- CPU_FTR_MMCRA | CPU_FTR_CTRL,
+ .cpu_features = CPU_FTR_RS64,
.cpu_user_features = COMMON_USER_PPC64,
.icache_bsize = 128,
.dcache_bsize = 128,
@@ -103,9 +87,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffff0000,
.pvr_value = 0x00340000,
.cpu_name = "RS64-III (pulsar)",
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
- CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
- CPU_FTR_MMCRA | CPU_FTR_CTRL,
+ .cpu_features = CPU_FTR_RS64,
.cpu_user_features = COMMON_USER_PPC64,
.icache_bsize = 128,
.dcache_bsize = 128,
@@ -120,9 +102,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffff0000,
.pvr_value = 0x00360000,
.cpu_name = "RS64-III (icestar)",
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
- CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
- CPU_FTR_MMCRA | CPU_FTR_CTRL,
+ .cpu_features = CPU_FTR_RS64,
.cpu_user_features = COMMON_USER_PPC64,
.icache_bsize = 128,
.dcache_bsize = 128,
@@ -137,9 +117,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffff0000,
.pvr_value = 0x00370000,
.cpu_name = "RS64-IV (sstar)",
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
- CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
- CPU_FTR_MMCRA | CPU_FTR_CTRL,
+ .cpu_features = CPU_FTR_RS64,
.cpu_user_features = COMMON_USER_PPC64,
.icache_bsize = 128,
.dcache_bsize = 128,
@@ -154,9 +132,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffff0000,
.pvr_value = 0x00350000,
.cpu_name = "POWER4 (gp)",
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
- CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
- CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_MMCRA,
+ .cpu_features = CPU_FTR_POWER4,
.cpu_user_features = COMMON_USER_PPC64,
.icache_bsize = 128,
.dcache_bsize = 128,
@@ -171,9 +147,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffff0000,
.pvr_value = 0x00380000,
.cpu_name = "POWER4+ (gq)",
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
- CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
- CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_MMCRA,
+ .cpu_features = CPU_FTR_POWER4,
.cpu_user_features = COMMON_USER_PPC64,
.icache_bsize = 128,
.dcache_bsize = 128,
@@ -188,10 +162,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffff0000,
.pvr_value = 0x00390000,
.cpu_name = "PPC970",
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
- CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
- CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP |
- CPU_FTR_CAN_NAP | CPU_FTR_MMCRA,
+ .cpu_features = CPU_FTR_PPC970,
.cpu_user_features = COMMON_USER_PPC64 |
PPC_FEATURE_HAS_ALTIVEC_COMP,
.icache_bsize = 128,
@@ -207,10 +178,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffff0000,
.pvr_value = 0x003c0000,
.cpu_name = "PPC970FX",
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
- CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
- CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP |
- CPU_FTR_CAN_NAP | CPU_FTR_MMCRA,
+ .cpu_features = CPU_FTR_PPC970,
.cpu_user_features = COMMON_USER_PPC64 |
PPC_FEATURE_HAS_ALTIVEC_COMP,
.icache_bsize = 128,
@@ -226,10 +194,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffff0000,
.pvr_value = 0x00440000,
.cpu_name = "PPC970MP",
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
- CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
- CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP |
- CPU_FTR_CAN_NAP | CPU_FTR_MMCRA,
+ .cpu_features = CPU_FTR_PPC970,
.cpu_user_features = COMMON_USER_PPC64 |
PPC_FEATURE_HAS_ALTIVEC_COMP,
.icache_bsize = 128,
@@ -244,11 +209,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffff0000,
.pvr_value = 0x003a0000,
.cpu_name = "POWER5 (gr)",
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
- CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
- CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_MMCRA | CPU_FTR_SMT |
- CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE |
- CPU_FTR_MMCRA_SIHV,
+ .cpu_features = CPU_FTR_POWER5,
.cpu_user_features = COMMON_USER_PPC64,
.icache_bsize = 128,
.dcache_bsize = 128,
@@ -263,11 +224,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffff0000,
.pvr_value = 0x003b0000,
.cpu_name = "POWER5 (gs)",
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
- CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
- CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_MMCRA | CPU_FTR_SMT |
- CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE |
- CPU_FTR_MMCRA_SIHV,
+ .cpu_features = CPU_FTR_POWER5,
.cpu_user_features = COMMON_USER_PPC64,
.icache_bsize = 128,
.dcache_bsize = 128,
@@ -281,11 +238,8 @@ struct cpu_spec cpu_specs[] = {
{ /* BE DD1.x */
.pvr_mask = 0xffff0000,
.pvr_value = 0x00700000,
- .cpu_name = "Broadband Engine",
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
- CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
- CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP |
- CPU_FTR_SMT,
+ .cpu_name = "Cell Broadband Engine",
+ .cpu_features = CPU_FTR_CELL,
.cpu_user_features = COMMON_USER_PPC64 |
PPC_FEATURE_HAS_ALTIVEC_COMP,
.icache_bsize = 128,
@@ -296,9 +250,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0x00000000,
.pvr_value = 0x00000000,
.cpu_name = "POWER4 (compatible)",
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
- CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
- CPU_FTR_PPCAS_ARCH_V2,
+ .cpu_features = CPU_FTR_COMPATIBLE,
.cpu_user_features = COMMON_USER_PPC64,
.icache_bsize = 128,
.dcache_bsize = 128,
Index: clean-cg/arch/ppc/kernel/cputable.c
===================================================================
--- clean-cg.orig/arch/ppc/kernel/cputable.c
+++ clean-cg/arch/ppc/kernel/cputable.c
@@ -42,17 +42,6 @@ extern void __setup_cpu_generic(unsigned
#define COMMON_PPC (PPC_FEATURE_32 | PPC_FEATURE_HAS_FPU | \
PPC_FEATURE_HAS_MMU)
-/* We only set the altivec features if the kernel was compiled with altivec
- * support
- */
-#ifdef CONFIG_ALTIVEC
-#define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC
-#define PPC_FEATURE_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
-#else
-#define CPU_FTR_ALTIVEC_COMP 0
-#define PPC_FEATURE_ALTIVEC_COMP 0
-#endif
-
/* We only set the spe features if the kernel was compiled with
* spe support
*/
@@ -62,34 +51,13 @@ extern void __setup_cpu_generic(unsigned
#define PPC_FEATURE_SPE_COMP 0
#endif
-/* We need to mark all pages as being coherent if we're SMP or we
- * have a 74[45]x and an MPC107 host bridge.
- */
-#if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE)
-#define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT
-#else
-#define CPU_FTR_COMMON 0
-#endif
-
-/* The powersave features NAP & DOZE seems to confuse BDI when
- debugging. So if a BDI is used, disable theses
- */
-#ifndef CONFIG_BDI_SWITCH
-#define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE
-#define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP
-#else
-#define CPU_FTR_MAYBE_CAN_DOZE 0
-#define CPU_FTR_MAYBE_CAN_NAP 0
-#endif
-
struct cpu_spec cpu_specs[] = {
#if CLASSIC_PPC
{ /* 601 */
.pvr_mask = 0xffff0000,
.pvr_value = 0x00010000,
.cpu_name = "601",
- .cpu_features = CPU_FTR_COMMON | CPU_FTR_601 |
- CPU_FTR_HPTE_TABLE,
+ .cpu_features = CPU_FTR_PPC601,
.cpu_user_features = COMMON_PPC | PPC_FEATURE_601_INSTR |
PPC_FEATURE_UNIFIED_CACHE,
.icache_bsize = 32,
@@ -100,9 +68,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffff0000,
.pvr_value = 0x00030000,
.cpu_name = "603",
- .cpu_features = CPU_FTR_COMMON |
- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
- CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP,
+ .cpu_features = CPU_FTR_603,
.cpu_user_features = COMMON_PPC,
.icache_bsize = 32,
.dcache_bsize = 32,
@@ -112,9 +78,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffff0000,
.pvr_value = 0x00060000,
.cpu_name = "603e",
- .cpu_features = CPU_FTR_COMMON |
- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
- CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP,
+ .cpu_features = CPU_FTR_603,
.cpu_user_features = COMMON_PPC,
.icache_bsize = 32,
.dcache_bsize = 32,
@@ -124,9 +88,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffff0000,
.pvr_value = 0x00070000,
.cpu_name = "603ev",
- .cpu_features = CPU_FTR_COMMON |
- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
- CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP,
+ .cpu_features = CPU_FTR_603,
.cpu_user_features = COMMON_PPC,
.icache_bsize = 32,
.dcache_bsize = 32,
@@ -136,9 +98,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffff0000,
.pvr_value = 0x00040000,
.cpu_name = "604",
- .cpu_features = CPU_FTR_COMMON |
- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
- CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE,
+ .cpu_features = CPU_FTR_604,
.cpu_user_features = COMMON_PPC,
.icache_bsize = 32,
.dcache_bsize = 32,
@@ -149,9 +109,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xfffff000,
.pvr_value = 0x00090000,
.cpu_name = "604e",
- .cpu_features = CPU_FTR_COMMON |
- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
- CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE,
+ .cpu_features = CPU_FTR_604,
.cpu_user_features = COMMON_PPC,
.icache_bsize = 32,
.dcache_bsize = 32,
@@ -162,9 +120,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffff0000,
.pvr_value = 0x00090000,
.cpu_name = "604r",
- .cpu_features = CPU_FTR_COMMON |
- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
- CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE,
+ .cpu_features = CPU_FTR_604,
.cpu_user_features = COMMON_PPC,
.icache_bsize = 32,
.dcache_bsize = 32,
@@ -175,9 +131,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffff0000,
.pvr_value = 0x000a0000,
.cpu_name = "604ev",
- .cpu_features = CPU_FTR_COMMON |
- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
- CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE,
+ .cpu_features = CPU_FTR_604,
.cpu_user_features = COMMON_PPC,
.icache_bsize = 32,
.dcache_bsize = 32,
@@ -188,10 +142,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffffffff,
.pvr_value = 0x00084202,
.cpu_name = "740/750",
- .cpu_features = CPU_FTR_COMMON |
- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
- CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_HPTE_TABLE |
- CPU_FTR_MAYBE_CAN_NAP,
+ .cpu_features = CPU_FTR_740_NOTAU,
.cpu_user_features = COMMON_PPC,
.icache_bsize = 32,
.dcache_bsize = 32,
@@ -202,10 +153,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xfffffff0,
.pvr_value = 0x00080100,
.cpu_name = "750CX",
- .cpu_features = CPU_FTR_COMMON |
- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
- CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
- CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
+ .cpu_features = CPU_FTR_750,
.cpu_user_features = COMMON_PPC,
.icache_bsize = 32,
.dcache_bsize = 32,
@@ -216,10 +164,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xfffffff0,
.pvr_value = 0x00082200,
.cpu_name = "750CX",
- .cpu_features = CPU_FTR_COMMON |
- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
- CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
- CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
+ .cpu_features = CPU_FTR_750,
.cpu_user_features = COMMON_PPC,
.icache_bsize = 32,
.dcache_bsize = 32,
@@ -230,10 +175,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xfffffff0,
.pvr_value = 0x00082210,
.cpu_name = "750CXe",
- .cpu_features = CPU_FTR_COMMON |
- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
- CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
- CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
+ .cpu_features = CPU_FTR_750,
.cpu_user_features = COMMON_PPC,
.icache_bsize = 32,
.dcache_bsize = 32,
@@ -244,10 +186,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffffffff,
.pvr_value = 0x00083214,
.cpu_name = "750CXe",
- .cpu_features = CPU_FTR_COMMON |
- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
- CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
- CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
+ .cpu_features = CPU_FTR_750,
.cpu_user_features = COMMON_PPC,
.icache_bsize = 32,
.dcache_bsize = 32,
@@ -258,10 +197,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xfffff000,
.pvr_value = 0x00083000,
.cpu_name = "745/755",
- .cpu_features = CPU_FTR_COMMON |
- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
- CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
- CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
+ .cpu_features = CPU_FTR_750,
.cpu_user_features = COMMON_PPC,
.icache_bsize = 32,
.dcache_bsize = 32,
@@ -272,11 +208,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffffff00,
.pvr_value = 0x70000100,
.cpu_name = "750FX",
- .cpu_features = CPU_FTR_COMMON |
- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
- CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
- CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
- CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM,
+ .cpu_features = CPU_FTR_750FX1,
.cpu_user_features = COMMON_PPC,
.icache_bsize = 32,
.dcache_bsize = 32,
@@ -287,11 +219,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffffffff,
.pvr_value = 0x70000200,
.cpu_name = "750FX",
- .cpu_features = CPU_FTR_COMMON |
- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
- CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
- CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
- CPU_FTR_NO_DPM,
+ .cpu_features = CPU_FTR_750FX2,
.cpu_user_features = COMMON_PPC,
.icache_bsize = 32,
.dcache_bsize = 32,
@@ -302,11 +230,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffff0000,
.pvr_value = 0x70000000,
.cpu_name = "750FX",
- .cpu_features = CPU_FTR_COMMON |
- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
- CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
- CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
- CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS,
+ .cpu_features = CPU_FTR_750FX,
.cpu_user_features = COMMON_PPC,
.icache_bsize = 32,
.dcache_bsize = 32,
@@ -317,11 +241,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffff0000,
.pvr_value = 0x70020000,
.cpu_name = "750GX",
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
- CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
- CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE |
- CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_DUAL_PLL_750FX |
- CPU_FTR_HAS_HIGH_BATS,
+ .cpu_features = CPU_FTR_750GX,
.cpu_user_features = COMMON_PPC,
.icache_bsize = 32,
.dcache_bsize = 32,
@@ -332,10 +252,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffff0000,
.pvr_value = 0x00080000,
.cpu_name = "740/750",
- .cpu_features = CPU_FTR_COMMON |
- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
- CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
- CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
+ .cpu_features = CPU_FTR_740,
.cpu_user_features = COMMON_PPC,
.icache_bsize = 32,
.dcache_bsize = 32,
@@ -346,11 +263,8 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffffffff,
.pvr_value = 0x000c1101,
.cpu_name = "7400 (1.1)",
- .cpu_features = CPU_FTR_COMMON |
- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
- CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
- CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
- .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
+ .cpu_features = CPU_FTR_7400_NOTAU,
+ .cpu_user_features = COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC_COMP,
.icache_bsize = 32,
.dcache_bsize = 32,
.num_pmcs = 4,
@@ -360,12 +274,8 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffff0000,
.pvr_value = 0x000c0000,
.cpu_name = "7400",
- .cpu_features = CPU_FTR_COMMON |
- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
- CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
- CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
- CPU_FTR_MAYBE_CAN_NAP,
- .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
+ .cpu_features = CPU_FTR_7400,
+ .cpu_user_features = COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC_COMP,
.icache_bsize = 32,
.dcache_bsize = 32,
.num_pmcs = 4,
@@ -375,12 +285,8 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffff0000,
.pvr_value = 0x800c0000,
.cpu_name = "7410",
- .cpu_features = CPU_FTR_COMMON |
- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
- CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
- CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
- CPU_FTR_MAYBE_CAN_NAP,
- .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
+ .cpu_features = CPU_FTR_7400,
+ .cpu_user_features = COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC_COMP,
.icache_bsize = 32,
.dcache_bsize = 32,
.num_pmcs = 4,
@@ -390,12 +296,8 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffffffff,
.pvr_value = 0x80000200,
.cpu_name = "7450",
- .cpu_features = CPU_FTR_COMMON |
- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
- CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
- CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
- CPU_FTR_NEED_COHERENT,
- .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
+ .cpu_features = CPU_FTR_7450_20,
+ .cpu_user_features = COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC_COMP,
.icache_bsize = 32,
.dcache_bsize = 32,
.num_pmcs = 6,
@@ -405,14 +307,8 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffffffff,
.pvr_value = 0x80000201,
.cpu_name = "7450",
- .cpu_features = CPU_FTR_COMMON |
- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
- CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
- CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
- CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
- CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP |
- CPU_FTR_NEED_COHERENT,
- .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
+ .cpu_features = CPU_FTR_7450_21,
+ .cpu_user_features = COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC_COMP,
.icache_bsize = 32,
.dcache_bsize = 32,
.num_pmcs = 6,
@@ -422,13 +318,8 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffff0000,
.pvr_value = 0x80000000,
.cpu_name = "7450",
- .cpu_features = CPU_FTR_COMMON |
- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
- CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
- CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
- CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
- CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT,
- .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
+ .cpu_features = CPU_FTR_7450_23,
+ .cpu_user_features = COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC_COMP,
.icache_bsize = 32,
.dcache_bsize = 32,
.num_pmcs = 6,
@@ -438,12 +329,8 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffffff00,
.pvr_value = 0x80010100,
.cpu_name = "7455",
- .cpu_features = CPU_FTR_COMMON |
- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
- CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
- CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
- CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT,
- .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
+ .cpu_features = CPU_FTR_7455_1,
+ .cpu_user_features = COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC_COMP,
.icache_bsize = 32,
.dcache_bsize = 32,
.num_pmcs = 6,
@@ -453,14 +340,8 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffffffff,
.pvr_value = 0x80010200,
.cpu_name = "7455",
- .cpu_features = CPU_FTR_COMMON |
- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
- CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
- CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
- CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
- CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP |
- CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS,
- .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
+ .cpu_features = CPU_FTR_7455_20,
+ .cpu_user_features = COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC_COMP,
.icache_bsize = 32,
.dcache_bsize = 32,
.num_pmcs = 6,
@@ -470,14 +351,8 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffff0000,
.pvr_value = 0x80010000,
.cpu_name = "7455",
- .cpu_features = CPU_FTR_COMMON |
- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
- CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
- CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
- CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
- CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
- CPU_FTR_NEED_COHERENT,
- .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
+ .cpu_features = CPU_FTR_7455,
+ .cpu_user_features = COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC_COMP,
.icache_bsize = 32,
.dcache_bsize = 32,
.num_pmcs = 6,
@@ -487,14 +362,8 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffffffff,
.pvr_value = 0x80020100,
.cpu_name = "7447/7457",
- .cpu_features = CPU_FTR_COMMON |
- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
- CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
- CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
- CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
- CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
- CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC,
- .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
+ .cpu_features = CPU_FTR_7447_10,
+ .cpu_user_features = COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC_COMP,
.icache_bsize = 32,
.dcache_bsize = 32,
.num_pmcs = 6,
@@ -504,14 +373,8 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffffffff,
.pvr_value = 0x80020101,
.cpu_name = "7447/7457",
- .cpu_features = CPU_FTR_COMMON |
- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
- CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
- CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
- CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
- CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
- CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC,
- .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
+ .cpu_features = CPU_FTR_7447_10,
+ .cpu_user_features = COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC_COMP,
.icache_bsize = 32,
.dcache_bsize = 32,
.num_pmcs = 6,
@@ -521,14 +384,8 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffff0000,
.pvr_value = 0x80020000,
.cpu_name = "7447/7457",
- .cpu_features = CPU_FTR_COMMON |
- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
- CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
- CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
- CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
- CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
- CPU_FTR_NEED_COHERENT,
- .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
+ .cpu_features = CPU_FTR_7447,
+ .cpu_user_features = COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC_COMP,
.icache_bsize = 32,
.dcache_bsize = 32,
.num_pmcs = 6,
@@ -538,13 +395,8 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffff0000,
.pvr_value = 0x80030000,
.cpu_name = "7447A",
- .cpu_features = CPU_FTR_COMMON |
- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
- CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
- CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
- CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
- CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT,
- .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
+ .cpu_features = CPU_FTR_7447A,
+ .cpu_user_features = COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC_COMP,
.icache_bsize = 32,
.dcache_bsize = 32,
.num_pmcs = 6,
@@ -554,13 +406,8 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffff0000,
.pvr_value = 0x80040000,
.cpu_name = "7448",
- .cpu_features = CPU_FTR_COMMON |
- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
- CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
- CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
- CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
- CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT,
- .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
+ .cpu_features = CPU_FTR_7447A,
+ .cpu_user_features = COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC_COMP,
.icache_bsize = 32,
.dcache_bsize = 32,
.num_pmcs = 6,
@@ -570,9 +417,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0x7fff0000,
.pvr_value = 0x00810000,
.cpu_name = "82xx",
- .cpu_features = CPU_FTR_COMMON |
- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
- CPU_FTR_USE_TB,
+ .cpu_features = CPU_FTR_82XX,
.cpu_user_features = COMMON_PPC,
.icache_bsize = 32,
.dcache_bsize = 32,
@@ -582,9 +427,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0x7fff0000,
.pvr_value = 0x00820000,
.cpu_name = "G2_LE",
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
- CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
- CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS,
+ .cpu_features = CPU_FTR_G2_LE,
.cpu_user_features = COMMON_PPC,
.icache_bsize = 32,
.dcache_bsize = 32,
@@ -594,9 +437,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0x7fff0000,
.pvr_value = 0x00830000,
.cpu_name = "e300",
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
- CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
- CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS,
+ .cpu_features = CPU_FTR_E300,
.cpu_user_features = COMMON_PPC,
.icache_bsize = 32,
.dcache_bsize = 32,
@@ -606,9 +447,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0x00000000,
.pvr_value = 0x00000000,
.cpu_name = "(generic PPC)",
- .cpu_features = CPU_FTR_COMMON |
- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
- CPU_FTR_HPTE_TABLE,
+ .cpu_features = CPU_FTR_CLASSIC32,
.cpu_user_features = COMMON_PPC,
.icache_bsize = 32,
.dcache_bsize = 32,
@@ -620,9 +459,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffff0000,
.pvr_value = 0x00400000,
.cpu_name = "Power3 (630)",
- .cpu_features = CPU_FTR_COMMON |
- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
- CPU_FTR_HPTE_TABLE,
+ .cpu_features = CPU_FTR_POWER3_32,
.cpu_user_features = COMMON_PPC | PPC_FEATURE_64,
.icache_bsize = 128,
.dcache_bsize = 128,
@@ -633,9 +470,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffff0000,
.pvr_value = 0x00410000,
.cpu_name = "Power3 (630+)",
- .cpu_features = CPU_FTR_COMMON |
- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
- CPU_FTR_HPTE_TABLE,
+ .cpu_features = CPU_FTR_POWER3_32,
.cpu_user_features = COMMON_PPC | PPC_FEATURE_64,
.icache_bsize = 128,
.dcache_bsize = 128,
@@ -646,9 +481,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffff0000,
.pvr_value = 0x00360000,
.cpu_name = "I-star",
- .cpu_features = CPU_FTR_COMMON |
- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
- CPU_FTR_HPTE_TABLE,
+ .cpu_features = CPU_FTR_POWER3_32,
.cpu_user_features = COMMON_PPC | PPC_FEATURE_64,
.icache_bsize = 128,
.dcache_bsize = 128,
@@ -659,55 +492,19 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffff0000,
.pvr_value = 0x00370000,
.cpu_name = "S-star",
- .cpu_features = CPU_FTR_COMMON |
- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
- CPU_FTR_HPTE_TABLE,
+ .cpu_features = CPU_FTR_POWER3_32,
.cpu_user_features = COMMON_PPC | PPC_FEATURE_64,
.icache_bsize = 128,
.dcache_bsize = 128,
.num_pmcs = 8,
.cpu_setup = __setup_cpu_power3
},
-#endif /* CONFIG_PPC64BRIDGE */
-#ifdef CONFIG_POWER4
- { /* Power4 */
- .pvr_mask = 0xffff0000,
- .pvr_value = 0x00350000,
- .cpu_name = "Power4",
- .cpu_features = CPU_FTR_COMMON |
- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
- CPU_FTR_HPTE_TABLE,
- .cpu_user_features = COMMON_PPC | PPC_FEATURE_64,
- .icache_bsize = 128,
- .dcache_bsize = 128,
- .num_pmcs = 8,
- .cpu_setup = __setup_cpu_power4
- },
- { /* PPC970 */
- .pvr_mask = 0xffff0000,
- .pvr_value = 0x00390000,
- .cpu_name = "PPC970",
- .cpu_features = CPU_FTR_COMMON |
- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
- CPU_FTR_HPTE_TABLE |
- CPU_FTR_ALTIVEC_COMP | CPU_FTR_MAYBE_CAN_NAP,
- .cpu_user_features = COMMON_PPC | PPC_FEATURE_64 |
- PPC_FEATURE_ALTIVEC_COMP,
- .icache_bsize = 128,
- .dcache_bsize = 128,
- .num_pmcs = 8,
- .cpu_setup = __setup_cpu_ppc970
- },
{ /* PPC970FX */
.pvr_mask = 0xffff0000,
.pvr_value = 0x003c0000,
.cpu_name = "PPC970FX",
- .cpu_features = CPU_FTR_COMMON |
- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
- CPU_FTR_HPTE_TABLE |
- CPU_FTR_ALTIVEC_COMP | CPU_FTR_MAYBE_CAN_NAP,
- .cpu_user_features = COMMON_PPC | PPC_FEATURE_64 |
- PPC_FEATURE_ALTIVEC_COMP,
+ .cpu_features = CPU_FTR_970_32,
+ .cpu_user_features = COMMON_PPC | PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC_COMP,
.icache_bsize = 128,
.dcache_bsize = 128,
.num_pmcs = 8,
@@ -721,8 +518,7 @@ struct cpu_spec cpu_specs[] = {
.cpu_name = "8xx",
/* CPU_FTR_MAYBE_CAN_DOZE is possible,
* if the 8xx code is there.... */
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
- CPU_FTR_USE_TB,
+ .cpu_features = CPU_FTR_8XX,
.cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
.icache_bsize = 16,
.dcache_bsize = 16,
@@ -733,8 +529,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffffff00,
.pvr_value = 0x00200200,
.cpu_name = "403GC",
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
- CPU_FTR_USE_TB,
+ .cpu_features = CPU_FTR_40X,
.cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
.icache_bsize = 16,
.dcache_bsize = 16,
@@ -743,8 +538,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffffff00,
.pvr_value = 0x00201400,
.cpu_name = "403GCX",
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
- CPU_FTR_USE_TB,
+ .cpu_features = CPU_FTR_40X,
.cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
.icache_bsize = 16,
.dcache_bsize = 16,
@@ -753,8 +547,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffff0000,
.pvr_value = 0x00200000,
.cpu_name = "403G ??",
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
- CPU_FTR_USE_TB,
+ .cpu_features = CPU_FTR_40X,
.cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
.icache_bsize = 16,
.dcache_bsize = 16,
@@ -763,8 +556,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffff0000,
.pvr_value = 0x40110000,
.cpu_name = "405GP",
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
- CPU_FTR_USE_TB,
+ .cpu_features = CPU_FTR_40X,
.cpu_user_features = PPC_FEATURE_32 |
PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
.icache_bsize = 32,
@@ -774,8 +566,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffff0000,
.pvr_value = 0x40130000,
.cpu_name = "STB03xxx",
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
- CPU_FTR_USE_TB,
+ .cpu_features = CPU_FTR_40X,
.cpu_user_features = PPC_FEATURE_32 |
PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
.icache_bsize = 32,
@@ -785,8 +576,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffff0000,
.pvr_value = 0x41810000,
.cpu_name = "STB04xxx",
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
- CPU_FTR_USE_TB,
+ .cpu_features = CPU_FTR_40X,
.cpu_user_features = PPC_FEATURE_32 |
PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
.icache_bsize = 32,
@@ -796,8 +586,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffff0000,
.pvr_value = 0x41610000,
.cpu_name = "NP405L",
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
- CPU_FTR_USE_TB,
+ .cpu_features = CPU_FTR_40X,
.cpu_user_features = PPC_FEATURE_32 |
PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
.icache_bsize = 32,
@@ -807,8 +596,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffff0000,
.pvr_value = 0x40B10000,
.cpu_name = "NP4GS3",
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
- CPU_FTR_USE_TB,
+ .cpu_features = CPU_FTR_40X,
.cpu_user_features = PPC_FEATURE_32 |
PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
.icache_bsize = 32,
@@ -818,8 +606,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffff0000,
.pvr_value = 0x41410000,
.cpu_name = "NP405H",
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
- CPU_FTR_USE_TB,
+ .cpu_features = CPU_FTR_40X,
.cpu_user_features = PPC_FEATURE_32 |
PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
.icache_bsize = 32,
@@ -829,8 +616,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffff0000,
.pvr_value = 0x50910000,
.cpu_name = "405GPr",
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
- CPU_FTR_USE_TB,
+ .cpu_features = CPU_FTR_40X,
.cpu_user_features = PPC_FEATURE_32 |
PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
.icache_bsize = 32,
@@ -840,8 +626,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffff0000,
.pvr_value = 0x51510000,
.cpu_name = "STBx25xx",
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
- CPU_FTR_USE_TB,
+ .cpu_features = CPU_FTR_40X,
.cpu_user_features = PPC_FEATURE_32 |
PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
.icache_bsize = 32,
@@ -851,8 +636,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffff0000,
.pvr_value = 0x41F10000,
.cpu_name = "405LP",
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
- CPU_FTR_USE_TB,
+ .cpu_features = CPU_FTR_40X,
.cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
.icache_bsize = 32,
.dcache_bsize = 32,
@@ -861,8 +645,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffff0000,
.pvr_value = 0x20010000,
.cpu_name = "Virtex-II Pro",
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
- CPU_FTR_USE_TB,
+ .cpu_features = CPU_FTR_40X,
.cpu_user_features = PPC_FEATURE_32 |
PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
.icache_bsize = 32,
@@ -872,8 +655,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffff0000,
.pvr_value = 0x51210000,
.cpu_name = "405EP",
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
- CPU_FTR_USE_TB,
+ .cpu_features = CPU_FTR_40X,
.cpu_user_features = PPC_FEATURE_32 |
PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
.icache_bsize = 32,
@@ -886,8 +668,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xf0000fff,
.pvr_value = 0x40000850,
.cpu_name = "440EP Rev. A",
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
- CPU_FTR_USE_TB,
+ .cpu_features = CPU_FTR_44X,
.cpu_user_features = COMMON_PPC, /* 440EP has an FPU */
.icache_bsize = 32,
.dcache_bsize = 32,
@@ -896,8 +677,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xf0000fff,
.pvr_value = 0x400008d3,
.cpu_name = "440EP Rev. B",
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
- CPU_FTR_USE_TB,
+ .cpu_features = CPU_FTR_44X,
.cpu_user_features = COMMON_PPC, /* 440EP has an FPU */
.icache_bsize = 32,
.dcache_bsize = 32,
@@ -906,8 +686,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xf0000fff,
.pvr_value = 0x40000440,
.cpu_name = "440GP Rev. B",
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
- CPU_FTR_USE_TB,
+ .cpu_features = CPU_FTR_44X,
.cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
.icache_bsize = 32,
.dcache_bsize = 32,
@@ -916,8 +695,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xf0000fff,
.pvr_value = 0x40000481,
.cpu_name = "440GP Rev. C",
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
- CPU_FTR_USE_TB,
+ .cpu_features = CPU_FTR_44X,
.cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
.icache_bsize = 32,
.dcache_bsize = 32,
@@ -926,8 +704,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xf0000fff,
.pvr_value = 0x50000850,
.cpu_name = "440GX Rev. A",
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
- CPU_FTR_USE_TB,
+ .cpu_features = CPU_FTR_44X,
.cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
.icache_bsize = 32,
.dcache_bsize = 32,
@@ -936,8 +713,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xf0000fff,
.pvr_value = 0x50000851,
.cpu_name = "440GX Rev. B",
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
- CPU_FTR_USE_TB,
+ .cpu_features = CPU_FTR_44X,
.cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
.icache_bsize = 32,
.dcache_bsize = 32,
@@ -946,8 +722,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xf0000fff,
.pvr_value = 0x50000892,
.cpu_name = "440GX Rev. C",
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
- CPU_FTR_USE_TB,
+ .cpu_features = CPU_FTR_44X,
.cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
.icache_bsize = 32,
.dcache_bsize = 32,
@@ -956,8 +731,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xf0000fff,
.pvr_value = 0x50000894,
.cpu_name = "440GX Rev. F",
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
- CPU_FTR_USE_TB,
+ .cpu_features = CPU_FTR_44X,
.cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
.icache_bsize = 32,
.dcache_bsize = 32,
@@ -966,8 +740,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xff000fff,
.pvr_value = 0x53000891,
.cpu_name = "440SP Rev. A",
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
- CPU_FTR_USE_TB,
+ .cpu_features = CPU_FTR_44X,
.cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
.icache_bsize = 32,
.dcache_bsize = 32,
@@ -979,7 +752,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_value = 0x81000000,
.cpu_name = "e200z5",
/* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
- .cpu_features = CPU_FTR_USE_TB,
+ .cpu_features = CPU_FTR_E200,
.cpu_user_features = PPC_FEATURE_32 |
PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_EFP_SINGLE |
PPC_FEATURE_UNIFIED_CACHE,
@@ -990,7 +763,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_value = 0x81100000,
.cpu_name = "e200z6",
/* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
- .cpu_features = CPU_FTR_USE_TB,
+ .cpu_features = CPU_FTR_E200,
.cpu_user_features = PPC_FEATURE_32 |
PPC_FEATURE_HAS_MMU | PPC_FEATURE_SPE_COMP |
PPC_FEATURE_HAS_EFP_SINGLE |
@@ -1002,8 +775,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_value = 0x80200000,
.cpu_name = "e500",
/* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
- CPU_FTR_USE_TB,
+ .cpu_features = CPU_FTR_E500,
.cpu_user_features = PPC_FEATURE_32 |
PPC_FEATURE_HAS_MMU | PPC_FEATURE_SPE_COMP |
PPC_FEATURE_HAS_EFP_SINGLE,
@@ -1016,8 +788,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_value = 0x80210000,
.cpu_name = "e500v2",
/* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
- CPU_FTR_USE_TB | CPU_FTR_BIG_PHYS,
+ .cpu_features = CPU_FTR_E500_2,
.cpu_user_features = PPC_FEATURE_32 |
PPC_FEATURE_HAS_MMU | PPC_FEATURE_SPE_COMP |
PPC_FEATURE_HAS_EFP_SINGLE | PPC_FEATURE_HAS_EFP_DOUBLE,
@@ -1031,7 +802,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0x00000000,
.pvr_value = 0x00000000,
.cpu_name = "(generic PPC)",
- .cpu_features = CPU_FTR_COMMON,
+ .cpu_features = CPU_FTR_GENERIC_32,
.cpu_user_features = PPC_FEATURE_32,
.icache_bsize = 32,
.dcache_bsize = 32,
Index: clean-cg/include/asm-powerpc/cputable.h
===================================================================
--- /dev/null
+++ clean-cg/include/asm-powerpc/cputable.h
@@ -0,0 +1,475 @@
+#ifndef __ASM_POWERPC_CPUTABLE_H
+#define __ASM_POWERPC_CPUTABLE_H
+
+#ifdef __KERNEL__
+#include <linux/config.h>
+#include <asm/ppc_asm.h> /* for ASM_CONST */
+
+#define PPC_FEATURE_32 0x80000000
+#define PPC_FEATURE_64 0x40000000
+#define PPC_FEATURE_601_INSTR 0x20000000
+#define PPC_FEATURE_HAS_ALTIVEC 0x10000000
+#define PPC_FEATURE_HAS_FPU 0x08000000
+#define PPC_FEATURE_HAS_MMU 0x04000000
+#define PPC_FEATURE_HAS_4xxMAC 0x02000000
+#define PPC_FEATURE_UNIFIED_CACHE 0x01000000
+#define PPC_FEATURE_HAS_SPE 0x00800000
+#define PPC_FEATURE_HAS_EFP_SINGLE 0x00400000
+#define PPC_FEATURE_HAS_EFP_DOUBLE 0x00200000
+
+#ifndef __ASSEMBLY__
+
+/* This structure can grow, it's real size is used by head.S code
+ * via the mkdefs mechanism.
+ */
+struct cpu_spec;
+struct op_ppc64_model;
+
+#ifndef __powerpc64__
+typedef void (*cpu_setup_t)(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
+#else /* __powerpc64__ */
+typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec);
+#endif /* __powerpc64__ */
+
+struct cpu_spec {
+ /* CPU is matched via (PVR & pvr_mask) == pvr_value */
+ unsigned int pvr_mask;
+ unsigned int pvr_value;
+
+ char *cpu_name;
+ unsigned long cpu_features; /* Kernel features */
+ unsigned int cpu_user_features; /* Userland features */
+
+ /* cache line sizes */
+ unsigned int icache_bsize;
+ unsigned int dcache_bsize;
+
+ /* number of performance monitor counters */
+ unsigned int num_pmcs;
+
+ /* this is called to initialize various CPU bits like L1 cache,
+ * BHT, SPD, etc... from head.S before branching to identify_machine
+ */
+ cpu_setup_t cpu_setup;
+#ifdef __powerpc64__
+
+ /* Used by oprofile userspace to select the right counters */
+ char *oprofile_cpu_type;
+
+ /* Processor specific oprofile operations */
+ struct op_ppc64_model *oprofile_model;
+#endif /* __powerpc64__ */
+};
+
+extern struct cpu_spec cpu_specs[];
+
+#ifndef __powerpc64__
+extern struct cpu_spec *cur_cpu_spec[];
+#else /* __powerpc64__ */
+extern struct cpu_spec *cur_cpu_spec;
+#endif /* __powerpc64__ */
+
+#endif /* __ASSEMBLY__ */
+
+/* CPU kernel features */
+
+/* Retain the 32b definitions all use bottom half of word */
+#define CPU_FTR_SPLIT_ID_CACHE ASM_CONST(0x0000000000000001)
+#define CPU_FTR_L2CR ASM_CONST(0x0000000000000002)
+#define CPU_FTR_SPEC7450 ASM_CONST(0x0000000000000004)
+#define CPU_FTR_ALTIVEC ASM_CONST(0x0000000000000008)
+#define CPU_FTR_TAU ASM_CONST(0x0000000000000010)
+#define CPU_FTR_CAN_DOZE ASM_CONST(0x0000000000000020)
+#define CPU_FTR_USE_TB ASM_CONST(0x0000000000000040)
+#define CPU_FTR_604_PERF_MON ASM_CONST(0x0000000000000080)
+#define CPU_FTR_601 ASM_CONST(0x0000000000000100)
+#define CPU_FTR_HPTE_TABLE ASM_CONST(0x0000000000000200)
+#define CPU_FTR_CAN_NAP ASM_CONST(0x0000000000000400)
+#define CPU_FTR_L3CR ASM_CONST(0x0000000000000800)
+#define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x0000000000001000)
+#define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x0000000000002000)
+#define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x0000000000004000)
+#define CPU_FTR_NO_DPM ASM_CONST(0x0000000000008000)
+#define CPU_FTR_HAS_HIGH_BATS ASM_CONST(0x0000000000010000)
+#define CPU_FTR_NEED_COHERENT ASM_CONST(0x0000000000020000)
+#define CPU_FTR_NO_BTIC ASM_CONST(0x0000000000040000)
+#define CPU_FTR_BIG_PHYS ASM_CONST(0x0000000000080000)
+
+#ifdef __powerpc64__
+/* Add the 64b processor unique features in the top half of the word */
+#define CPU_FTR_SLB ASM_CONST(0x0000000100000000)
+#define CPU_FTR_16M_PAGE ASM_CONST(0x0000000200000000)
+#define CPU_FTR_TLBIEL ASM_CONST(0x0000000400000000)
+#define CPU_FTR_NOEXECUTE ASM_CONST(0x0000000800000000)
+#define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000001000000000)
+#define CPU_FTR_IABR ASM_CONST(0x0000002000000000)
+#define CPU_FTR_MMCRA ASM_CONST(0x0000004000000000)
+/* unused ASM_CONST(0x0000008000000000) */
+#define CPU_FTR_SMT ASM_CONST(0x0000010000000000)
+#define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x0000020000000000)
+#define CPU_FTR_LOCKLESS_TLBIE ASM_CONST(0x0000040000000000)
+#define CPU_FTR_MMCRA_SIHV ASM_CONST(0x0000080000000000)
+#define CPU_FTR_CTRL ASM_CONST(0x0000100000000000)
+#endif
+
+#ifndef __ASSEMBLY__
+
+#define COMMON_USER_PPC64 (PPC_FEATURE_32 | PPC_FEATURE_64 | \
+ PPC_FEATURE_HAS_FPU | PPC_FEATURE_HAS_MMU)
+
+#define CPU_FTR_PPCAS_ARCH_V2_BASE (CPU_FTR_SLB | \
+ CPU_FTR_TLBIEL | CPU_FTR_NOEXECUTE | \
+ CPU_FTR_NODSISRALIGN | CPU_FTR_CTRL)
+
+/* iSeries doesn't support large pages */
+#ifdef CONFIG_PPC_ISERIES
+#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_PPCAS_ARCH_V2_BASE)
+#else
+#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_PPCAS_ARCH_V2_BASE | CPU_FTR_16M_PAGE)
+#endif /* CONFIG_PPC_ISERIES */
+
+/* We only set the altivec features if the kernel was compiled with altivec
+ * support
+ */
+#ifdef CONFIG_ALTIVEC
+#define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC
+#define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
+#else
+#define CPU_FTR_ALTIVEC_COMP 0
+#define PPC_FEATURE_HAS_ALTIVEC_COMP 0
+#endif
+
+/* We need to mark all pages as being coherent if we're SMP or we
+ * have a 74[45]x and an MPC107 host bridge.
+ */
+#if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE)
+#define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT
+#else
+#define CPU_FTR_COMMON 0
+#endif
+
+/* The powersave features NAP & DOZE seems to confuse BDI when
+ debugging. So if a BDI is used, disable theses
+ */
+#ifndef CONFIG_BDI_SWITCH
+#define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE
+#define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP
+#else
+#define CPU_FTR_MAYBE_CAN_DOZE 0
+#define CPU_FTR_MAYBE_CAN_NAP 0
+#endif
+
+#define CLASSIC_PPC (!defined(CONFIG_8xx) && !defined(CONFIG_4xx) && \
+ !defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \
+ !defined(CONFIG_BOOKE))
+
+enum {
+ CPU_FTR_PPC601 = CPU_FTR_COMMON | CPU_FTR_601 | CPU_FTR_HPTE_TABLE,
+ CPU_FTR_603 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+ CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
+ CPU_FTR_MAYBE_CAN_NAP,
+ CPU_FTR_604 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+ CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE,
+ CPU_FTR_740_NOTAU = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+ CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
+ CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
+ CPU_FTR_740 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+ CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
+ CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
+ CPU_FTR_750 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+ CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
+ CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
+ CPU_FTR_750FX1 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+ CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
+ CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
+ CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM,
+ CPU_FTR_750FX2 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+ CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
+ CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
+ CPU_FTR_NO_DPM,
+ CPU_FTR_750FX = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+ CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
+ CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
+ CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS,
+ CPU_FTR_750GX = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
+ CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
+ CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
+ CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS,
+ CPU_FTR_7400_NOTAU = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+ CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
+ CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
+ CPU_FTR_MAYBE_CAN_NAP,
+ CPU_FTR_7400 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+ CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
+ CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
+ CPU_FTR_MAYBE_CAN_NAP,
+ CPU_FTR_7450_20 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+ CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
+ CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
+ CPU_FTR_NEED_COHERENT,
+ CPU_FTR_7450_21 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+ CPU_FTR_USE_TB |
+ CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
+ CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
+ CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP |
+ CPU_FTR_NEED_COHERENT,
+ CPU_FTR_7450_23 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+ CPU_FTR_USE_TB |
+ CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
+ CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
+ CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT,
+ CPU_FTR_7455_1 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+ CPU_FTR_USE_TB |
+ CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
+ CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_HAS_HIGH_BATS |
+ CPU_FTR_NEED_COHERENT,
+ CPU_FTR_7455_20 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+ CPU_FTR_USE_TB |
+ CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
+ CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
+ CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP |
+ CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS,
+ CPU_FTR_7455 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+ CPU_FTR_USE_TB |
+ CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
+ CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
+ CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
+ CPU_FTR_NEED_COHERENT,
+ CPU_FTR_7447_10 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+ CPU_FTR_USE_TB |
+ CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
+ CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
+ CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
+ CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC,
+ CPU_FTR_7447 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+ CPU_FTR_USE_TB |
+ CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
+ CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
+ CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
+ CPU_FTR_NEED_COHERENT,
+ CPU_FTR_7447A = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+ CPU_FTR_USE_TB |
+ CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
+ CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
+ CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
+ CPU_FTR_NEED_COHERENT,
+ CPU_FTR_82XX = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+ CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB,
+ CPU_FTR_G2_LE = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
+ CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS,
+ CPU_FTR_E300 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
+ CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS,
+ CPU_FTR_CLASSIC32 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+ CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
+ CPU_FTR_POWER3_32 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+ CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
+ CPU_FTR_POWER4_32 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+ CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
+ CPU_FTR_970_32 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+ CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_ALTIVEC_COMP |
+ CPU_FTR_MAYBE_CAN_NAP,
+ CPU_FTR_8XX = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
+ CPU_FTR_40X = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
+ CPU_FTR_44X = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
+ CPU_FTR_E200 = CPU_FTR_USE_TB,
+ CPU_FTR_E500 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
+ CPU_FTR_E500_2 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
+ CPU_FTR_BIG_PHYS,
+ CPU_FTR_GENERIC_32 = CPU_FTR_COMMON,
+#ifdef __powerpc64__
+ CPU_FTR_POWER3 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
+ CPU_FTR_HPTE_TABLE | CPU_FTR_IABR,
+ CPU_FTR_RS64 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
+ CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
+ CPU_FTR_MMCRA | CPU_FTR_CTRL,
+ CPU_FTR_POWER4 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
+ CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_MMCRA,
+ CPU_FTR_PPC970 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
+ CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 |
+ CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA,
+ CPU_FTR_POWER5 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
+ CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 |
+ CPU_FTR_MMCRA | CPU_FTR_SMT |
+ CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE |
+ CPU_FTR_MMCRA_SIHV,
+ CPU_FTR_CELL = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
+ CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 |
+ CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT,
+ CPU_FTR_COMPATIBLE = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
+ CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2,
+#endif
+ CPU_FTR_POSSIBLE =
+#if CLASSIC_PPC
+ CPU_FTR_601 | CPU_FTR_603 | CPU_FTR_604 | CPU_FTR_740_NOTAU |
+ CPU_FTR_740 | CPU_FTR_750 | CPU_FTR_750FX1 |
+ CPU_FTR_750FX2 | CPU_FTR_750FX | CPU_FTR_750GX |
+ CPU_FTR_7400_NOTAU | CPU_FTR_7400 | CPU_FTR_7450_20 |
+ CPU_FTR_7450_21 | CPU_FTR_7450_23 | CPU_FTR_7455_1 |
+ CPU_FTR_7455_20 | CPU_FTR_7455 | CPU_FTR_7447_10 |
+ CPU_FTR_7447 | CPU_FTR_7447A | CPU_FTR_82XX |
+ CPU_FTR_G2_LE | CPU_FTR_E300 | CPU_FTR_CLASSIC32 |
+#else
+ CPU_FTR_GENERIC_32 |
+#endif
+#ifdef CONFIG_PPC64BRIDGE
+ CPU_FTR_POWER3_32 |
+#endif
+#ifdef CONFIG_POWER4
+ CPU_FTR_POWER4_32 | CPU_FTR_970_32 |
+#endif
+#ifdef CONFIG_8xx
+ CPU_FTR_8XX |
+#endif
+#ifdef CONFIG_40x
+ CPU_FTR_40X |
+#endif
+#ifdef CONFIG_44x
+ CPU_FTR_44X |
+#endif
+#ifdef CONFIG_FSL_BOOKE
+ CPU_FTR_E200 | CPU_FTR_E500 | CPU_FTR_E500_2 |
+#endif
+#ifdef CONFIG_CPU_POWER3
+ CPU_FTR_POWER3 |
+#endif
+#ifdef CONFIG_CPU_RS64
+ CPU_FTR_RS64 |
+#endif
+#ifdef CONFIG_CPU_POWER4
+ CPU_FTR_POWER4 |
+#endif
+#ifdef CONFIG_CPU_PPC970
+ CPU_FTR_PPC970 |
+#endif
+#ifdef CONFIG_CPU_POWER5
+ CPU_FTR_POWER5 |
+#endif
+#ifdef CONFIG_CPU_CELL
+ CPU_FTR_CELL |
+#endif
+ 0,
+ CPU_FTR_ALWAYS =
+#if CLASSIC_PPC
+ CPU_FTR_601 & CPU_FTR_603 & CPU_FTR_604 & CPU_FTR_740_NOTAU &
+ CPU_FTR_740 & CPU_FTR_750 & CPU_FTR_750FX1 &
+ CPU_FTR_750FX2 & CPU_FTR_750FX & CPU_FTR_750GX &
+ CPU_FTR_7400_NOTAU & CPU_FTR_7400 & CPU_FTR_7450_20 &
+ CPU_FTR_7450_21 & CPU_FTR_7450_23 & CPU_FTR_7455_1 &
+ CPU_FTR_7455_20 & CPU_FTR_7455 & CPU_FTR_7447_10 &
+ CPU_FTR_7447 & CPU_FTR_7447A & CPU_FTR_82XX &
+ CPU_FTR_G2_LE & CPU_FTR_E300 & CPU_FTR_CLASSIC32 &
+#else
+ CPU_FTR_GENERIC_32 &
+#endif
+#ifdef CONFIG_PPC64BRIDGE
+ CPU_FTR_POWER3_32 &
+#endif
+#ifdef CONFIG_POWER4
+ CPU_FTR_POWER4_32 & CPU_FTR_970_32 &
+#endif
+#ifdef CONFIG_8xx
+ CPU_FTR_8XX &
+#endif
+#ifdef CONFIG_40x
+ CPU_FTR_40X &
+#endif
+#ifdef CONFIG_44x
+ CPU_FTR_44X &
+#endif
+#ifdef CONFIG_FSL_BOOKE
+ CPU_FTR_E200 & CPU_FTR_E500 & CPU_FTR_E500_2 &
+#endif
+#ifdef CONFIG_CPU_POWER3
+ CPU_FTR_POWER3 &
+#endif
+#ifdef CONFIG_CPU_RS64
+ CPU_FTR_RS64 &
+#endif
+#ifdef CONFIG_CPU_POWER4
+ CPU_FTR_POWER4 &
+#endif
+#ifdef CONFIG_CPU_PPC970
+ CPU_FTR_PPC970 &
+#endif
+#ifdef CONFIG_CPU_POWER5
+ CPU_FTR_POWER5 &
+#endif
+#ifdef CONFIG_CPU_CELL
+ CPU_FTR_CELL &
+#endif
+ CPU_FTR_POSSIBLE,
+};
+
+static inline int cpu_has_feature(unsigned long feature)
+{
+ return (CPU_FTR_ALWAYS & feature) ||
+ (CPU_FTR_POSSIBLE
+#ifndef __powerpc64__
+ & cur_cpu_spec[0]->cpu_features
+#else
+ & cur_cpu_spec->cpu_features
+#endif
+ & feature);
+}
+
+#endif /* __ASSEMBLY */
+
+#ifdef __ASSEMBLY__
+
+#define BEGIN_FTR_SECTION 98:
+
+#ifndef __powerpc64__
+#define END_FTR_SECTION(msk, val) \
+99: \
+ .section __ftr_fixup,"a"; \
+ .align 2; \
+ .long msk; \
+ .long val; \
+ .long 98b; \
+ .long 99b; \
+ .previous
+#else /* __powerpc64__ */
+#define END_FTR_SECTION(msk, val) \
+99: \
+ .section __ftr_fixup,"a"; \
+ .align 3; \
+ .llong msk; \
+ .llong val; \
+ .llong 98b; \
+ .llong 99b; \
+ .previous
+#endif /* __powerpc64__ */
+
+#else
+
+#define BEGIN_FTR_SECTION "98:\n"
+
+#ifndef __powerpc64__
+#define END_FTR_SECTION(msk, val) \
+"99:\n" \
+" .section __ftr_fixup,\"a\";\n" \
+" .align 2;\n" \
+" .long "#msk";\n" \
+" .long "#val";\n" \
+" .long 98b;\n" \
+" .long 99b;\n" \
+" .previous\n"
+#else /* __powerpc64__ */
+#define END_FTR_SECTION(msk, val) \
+"99:\n" \
+" .section __ftr_fixup,\"a\";\n" \
+" .align 3;\n" \
+" .llong "#msk";\n" \
+" .llong "#val";\n" \
+" .llong 98b;\n" \
+" .llong 99b;\n" \
+" .previous\n"
+#endif /* __powerpc64__ */
+
+#endif /* __ASSEMBLY__ */
+
+#define END_FTR_SECTION_IFSET(msk) END_FTR_SECTION((msk), (msk))
+#define END_FTR_SECTION_IFCLR(msk) END_FTR_SECTION((msk), 0)
+
+#endif /* __KERNEL__ */
+#endif /* __ASM_POWERPC_CPUTABLE_H */
Index: clean-cg/include/asm-ppc/cputable.h
===================================================================
--- clean-cg.orig/include/asm-ppc/cputable.h
+++ /dev/null
@@ -1,128 +0,0 @@
-/*
- * include/asm-ppc/cputable.h
- *
- * Copyright (C) 2001 Ben. Herrenschmidt (benh@kernel.crashing.org)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef __ASM_PPC_CPUTABLE_H
-#define __ASM_PPC_CPUTABLE_H
-
-/* Exposed to userland CPU features */
-#define PPC_FEATURE_32 0x80000000
-#define PPC_FEATURE_64 0x40000000
-#define PPC_FEATURE_601_INSTR 0x20000000
-#define PPC_FEATURE_HAS_ALTIVEC 0x10000000
-#define PPC_FEATURE_HAS_FPU 0x08000000
-#define PPC_FEATURE_HAS_MMU 0x04000000
-#define PPC_FEATURE_HAS_4xxMAC 0x02000000
-#define PPC_FEATURE_UNIFIED_CACHE 0x01000000
-#define PPC_FEATURE_HAS_SPE 0x00800000
-#define PPC_FEATURE_HAS_EFP_SINGLE 0x00400000
-#define PPC_FEATURE_HAS_EFP_DOUBLE 0x00200000
-
-#ifdef __KERNEL__
-
-#ifndef __ASSEMBLY__
-
-/* This structure can grow, it's real size is used by head.S code
- * via the mkdefs mecanism.
- */
-struct cpu_spec;
-
-typedef void (*cpu_setup_t)(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
-
-struct cpu_spec {
- /* CPU is matched via (PVR & pvr_mask) == pvr_value */
- unsigned int pvr_mask;
- unsigned int pvr_value;
-
- char *cpu_name;
- unsigned int cpu_features; /* Kernel features */
- unsigned int cpu_user_features; /* Userland features */
-
- /* cache line sizes */
- unsigned int icache_bsize;
- unsigned int dcache_bsize;
-
- /* number of performance monitor counters */
- unsigned int num_pmcs;
-
- /* this is called to initialize various CPU bits like L1 cache,
- * BHT, SPD, etc... from head.S before branching to identify_machine
- */
- cpu_setup_t cpu_setup;
-};
-
-extern struct cpu_spec cpu_specs[];
-extern struct cpu_spec *cur_cpu_spec[];
-
-static inline unsigned int cpu_has_feature(unsigned int feature)
-{
- return cur_cpu_spec[0]->cpu_features & feature;
-}
-
-#endif /* __ASSEMBLY__ */
-
-/* CPU kernel features */
-#define CPU_FTR_SPLIT_ID_CACHE 0x00000001
-#define CPU_FTR_L2CR 0x00000002
-#define CPU_FTR_SPEC7450 0x00000004
-#define CPU_FTR_ALTIVEC 0x00000008
-#define CPU_FTR_TAU 0x00000010
-#define CPU_FTR_CAN_DOZE 0x00000020
-#define CPU_FTR_USE_TB 0x00000040
-#define CPU_FTR_604_PERF_MON 0x00000080
-#define CPU_FTR_601 0x00000100
-#define CPU_FTR_HPTE_TABLE 0x00000200
-#define CPU_FTR_CAN_NAP 0x00000400
-#define CPU_FTR_L3CR 0x00000800
-#define CPU_FTR_L3_DISABLE_NAP 0x00001000
-#define CPU_FTR_NAP_DISABLE_L2_PR 0x00002000
-#define CPU_FTR_DUAL_PLL_750FX 0x00004000
-#define CPU_FTR_NO_DPM 0x00008000
-#define CPU_FTR_HAS_HIGH_BATS 0x00010000
-#define CPU_FTR_NEED_COHERENT 0x00020000
-#define CPU_FTR_NO_BTIC 0x00040000
-#define CPU_FTR_BIG_PHYS 0x00080000
-
-#ifdef __ASSEMBLY__
-
-#define BEGIN_FTR_SECTION 98:
-
-#define END_FTR_SECTION(msk, val) \
-99: \
- .section __ftr_fixup,"a"; \
- .align 2; \
- .long msk; \
- .long val; \
- .long 98b; \
- .long 99b; \
- .previous
-
-#else
-
-#define BEGIN_FTR_SECTION "98:\n"
-#define END_FTR_SECTION(msk, val) \
-"99:\n" \
-" .section __ftr_fixup,\"a\";\n" \
-" .align 2;\n" \
-" .long "#msk";\n" \
-" .long "#val";\n" \
-" .long 98b;\n" \
-" .long 99b;\n" \
-" .previous\n"
-
-
-#endif /* __ASSEMBLY__ */
-
-#define END_FTR_SECTION_IFSET(msk) END_FTR_SECTION((msk), (msk))
-#define END_FTR_SECTION_IFCLR(msk) END_FTR_SECTION((msk), 0)
-
-#endif /* __ASM_PPC_CPUTABLE_H */
-#endif /* __KERNEL__ */
-
^ permalink raw reply
* Re: can we kill CONFIG_PPC64BRIDGE?
From: Heikki Lindholm @ 2005-09-09 5:54 UTC (permalink / raw)
To: Kumar Gala; +Cc: linuxppc-dev list, ppc64-dev
In-Reply-To: <5AB80D6D-C8B0-4F08-9C06-A56119D5D696@freescale.com>
Kumar Gala kirjoitti:
> Paul,
>
> Can we kill CONFIG_PPC64BRIDGE for ppc32... Not sure if anyone is using
> this or not?
It has been useful when porting stuff over to ppc64. Though, if nobody
will maintain it...
-- Heikki Lindholm
^ permalink raw reply
* Can the mpc8270 provide the direct IDE interface?
From: FCG WANG Baohua @ 2005-09-09 6:19 UTC (permalink / raw)
To: thomas, Steven.Scholz; +Cc: mattl, linuxppc-embedded
[-- Attachment #1: Type: text/plain, Size: 568 bytes --]
Dear All:
I have a question when I port the PCMCIA driver to MPC8270 board:
Can the mpc8270 provide the direct IDE interface without using the PCMCIA controller? If it can, what's the different with the
drivers\ide\ppc\mpc8xx.c ? Can you provide some resource about the "direct IDE interface " on MPC82xx ?
My PCMCIA CF card has a specially CPLD to read/write the status of the CF card. What's the codes need to be modified if using
the Card Services package? What's the performance between the direct IDE mode and card service?
thanks a lot!
[-- Attachment #2: Type: text/html, Size: 1514 bytes --]
^ permalink raw reply
* Serial driver problem from 2.6.12 kernel
From: goog long @ 2005-09-09 15:17 UTC (permalink / raw)
To: linuxppc-dev
Hi all,
I backported MPSC driver from 2.6.12 to my kernel
2.6.10. However, the driver can send characters, but
cannot receive any characters. Have anyone seen this
before?
Please also send your feedback to cecolong@yahoo.com
Thanks and best regards,
cecolong
__________________________________________________
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http://mail.yahoo.com
^ permalink raw reply
* Marvell MV64360 interrupt question
From: Walter L. Wimer III @ 2005-09-09 17:31 UTC (permalink / raw)
To: Linux PPC Embedded list
Hi All,
I'm looking at arch/ppc/syslib/mv64360_pic.c in the 2.6.13 kernel and I
see the following code:
int
mv64360_get_irq(struct pt_regs *regs)
{
.
.
.
if (irq == -1) {
irq = mv64x60_read(&bh, MV64360_IC_MAIN_CAUSE_HI);
irq = __ilog2((irq & 0x1f0003f7) & ppc_cached_irq_mask[1]);
if (irq == -1)
irq = -2; /* bogus interrupt, should never happen */
else {
if ((irq >= 24) && (irq < MV64x60_IRQ_DOORBELL)) {
irq_gpp = mv64x60_read(&bh, MV64x60_GPP_INTR_CAUSE);
irq_gpp = __ilog2(irq_gpp & ppc_cached_irq_mask[2]);
if (irq_gpp == -1)
irq = -2;
else {
irq = irq_gpp + 64;
mv64x60_write(&bh,
MV64x60_GPP_INTR_CAUSE,
(1 << (irq - 64)));
}
}
else
irq += 32;
}
}
(void)mv64x60_read(&bh, MV64x60_GPP_INTR_CAUSE);
.
.
.
}
Does anybody know what the last mv64x60_read() is intended to do? It
*looks* like it's clearing/acknowledging the interrupt, but I don't see
anything in the Marvell documentation that suggests that *reading* the
interrupt cause register has such an effect. From my reading, the
documentation says that you should write a '0' into the appropriate bit
position to clear the interrupt.
Hmmm... There's an mv64x60_write() a little earlier in the code... Is
the "extra" mv64x60_read() here to enforce ordering? If so, should it
be moved inside the "if" statement so that it's only executed when
actually necessary?
And what about locking? The mv64x60_xxxx() functions are protected by a
spinlock, but if we're trying to enforce ordering, shouldn't we hold the
lock during the entire write+read operation, rather than dropping and
reacquiring the lock in between?
At the moment, I'm not running into any actual problems here; this just
caught my eye and I started wondering about it.
BTW, the reason I'm looking at this code is that the board I'm working
on has a cascaded interrupt controller (implemented in an FPGA) feeding
into the MV64360 interrupt controller. I'm thinking about adding a
cascade mechanism to mv64360_pic.c similar to the one in the OpenPIC
code (i.e. like the openpic_hookup_cascade() function). Any opinions on
whether this is a good idea or a bad one?
Thanks!!!
Walt
^ permalink raw reply
* [PATCH] ppc/ppc64: Merge bug.h into include/asm-powerpc
From: Becky Bruce @ 2005-09-09 18:52 UTC (permalink / raw)
To: linuxppc64-dev, linuxppc-dev
This patch merges bug.h into include/asm-powerpc. Changed the data
structure for bug_entry such that line is always an int on both 32 and
64-bit platforms; removed casts to int from the 64-bit trap code to
reflect this.
Signed-off-by: Kumar Gala <kumar.gala@freescale.com>
Signed-off-by: Becky Bruce <Becky.Bruce@freescale.com>
---
commit fcaf8560dc918048b43867d79efa5b26bd6a9a81
tree 079802fdb229c0e3721b893235e2ef912e30d7cd
parent dfe2ac4994952cadc891f095668f9e582d4402b3
author Becky Bruce <becky.bruce@freescale.com> Fri, 09 Sep 2005 11:15:22 -0500
committer Becky Bruce <becky.bruce@freescale.com> Fri, 09 Sep 2005 11:15:22 -0500
arch/ppc/kernel/traps.c | 2 +
arch/ppc64/kernel/traps.c | 4 +-
include/asm-powerpc/bug.h | 81 +++++++++++++++++++++++++++++++++++++++++++++
include/asm-ppc/bug.h | 58 --------------------------------
include/asm-ppc64/bug.h | 69 --------------------------------------
5 files changed, 84 insertions(+), 130 deletions(-)
diff --git a/arch/ppc/kernel/traps.c b/arch/ppc/kernel/traps.c
--- a/arch/ppc/kernel/traps.c
+++ b/arch/ppc/kernel/traps.c
@@ -553,7 +553,7 @@ extern struct bug_entry __start___bug_ta
#define module_find_bug(x) NULL
#endif
-static struct bug_entry *find_bug(unsigned long bugaddr)
+struct bug_entry *find_bug(unsigned long bugaddr)
{
struct bug_entry *bug;
diff --git a/arch/ppc64/kernel/traps.c b/arch/ppc64/kernel/traps.c
--- a/arch/ppc64/kernel/traps.c
+++ b/arch/ppc64/kernel/traps.c
@@ -389,12 +389,12 @@ check_bug_trap(struct pt_regs *regs)
/* this is a WARN_ON rather than BUG/BUG_ON */
printk(KERN_ERR "Badness in %s at %s:%d\n",
bug->function, bug->file,
- (unsigned int)bug->line & ~BUG_WARNING_TRAP);
+ bug->line & ~BUG_WARNING_TRAP);
show_stack(current, (void *)regs->gpr[1]);
return 1;
}
printk(KERN_CRIT "kernel BUG in %s at %s:%d!\n",
- bug->function, bug->file, (unsigned int)bug->line);
+ bug->function, bug->file, bug->line);
return 0;
}
diff --git a/include/asm-powerpc/bug.h b/include/asm-powerpc/bug.h
new file mode 100644
--- /dev/null
+++ b/include/asm-powerpc/bug.h
@@ -0,0 +1,81 @@
+#ifndef _ASM_POWERPC_BUG_H
+#define _ASM_POWERPC_BUG_H
+
+/*
+ * Define an illegal instr to trap on the bug.
+ * We don't use 0 because that marks the end of a function
+ * in the ELF ABI. That's "Boo Boo" in case you wonder...
+ */
+#define BUG_OPCODE .long 0x00b00b00 /* For asm */
+#define BUG_ILLEGAL_INSTR "0x00b00b00" /* For BUG macro */
+
+#ifndef __ASSEMBLY__
+
+#ifdef __powerpc64__
+#define BUG_TABLE_ENTRY(label, line, file, func) \
+ ".llong " #label "\n .long " #line "\n .llong " #file ", " #func "\n"
+#define TRAP_OP(ra, rb) "1: tdnei " #ra ", " #rb "\n"
+#define DATA_TYPE long long
+#else
+#define BUG_TABLE_ENTRY(label, line, file, func) \
+ ".long " #label ", " #line ", " #file ", " #func "\n"
+#define TRAP_OP(ra, rb) "1: twnei " #ra ", " #rb "\n"
+#define DATA_TYPE int
+#endif /* __powerpc64__ */
+
+struct bug_entry {
+ unsigned long bug_addr;
+ int line;
+ const char *file;
+ const char *function;
+};
+
+struct bug_entry *find_bug(unsigned long bugaddr);
+
+/*
+ * If this bit is set in the line number it means that the trap
+ * is for WARN_ON rather than BUG or BUG_ON.
+ */
+#define BUG_WARNING_TRAP 0x1000000
+
+#ifdef CONFIG_BUG
+
+#define BUG() do { \
+ __asm__ __volatile__( \
+ "1: twi 31,0,0\n" \
+ ".section __bug_table,\"a\"\n\t" \
+ BUG_TABLE_ENTRY(1b,%0,%1,%2) \
+ ".previous" \
+ : : "i" (__LINE__), "i" (__FILE__), "i" (__FUNCTION__)); \
+} while (0)
+
+#define BUG_ON(x) do { \
+ __asm__ __volatile__( \
+ TRAP_OP(%0,0) \
+ ".section __bug_table,\"a\"\n\t" \
+ BUG_TABLE_ENTRY(1b,%1,%2,%3) \
+ ".previous" \
+ : : "r" ((DATA_TYPE)(x)), "i" (__LINE__), \
+ "i" (__FILE__), "i" (__FUNCTION__)); \
+} while (0)
+
+#define WARN_ON(x) do { \
+ __asm__ __volatile__( \
+ TRAP_OP(%0,0) \
+ ".section __bug_table,\"a\"\n\t" \
+ BUG_TABLE_ENTRY(1b,%1,%2,%3) \
+ ".previous" \
+ : : "r" ((DATA_TYPE)(x)), \
+ "i" (__LINE__ + BUG_WARNING_TRAP), \
+ "i" (__FILE__), "i" (__FUNCTION__)); \
+} while (0)
+
+#define HAVE_ARCH_BUG
+#define HAVE_ARCH_BUG_ON
+#define HAVE_ARCH_WARN_ON
+#endif /* CONFIG_BUG */
+#endif /* __ASSEMBLY __ */
+
+#include <asm-generic/bug.h>
+
+#endif /* _ASM_POWERPC_BUG_H */
diff --git a/include/asm-ppc/bug.h b/include/asm-ppc/bug.h
deleted file mode 100644
--- a/include/asm-ppc/bug.h
+++ /dev/null
@@ -1,58 +0,0 @@
-#ifndef _PPC_BUG_H
-#define _PPC_BUG_H
-
-struct bug_entry {
- unsigned long bug_addr;
- int line;
- const char *file;
- const char *function;
-};
-
-/*
- * If this bit is set in the line number it means that the trap
- * is for WARN_ON rather than BUG or BUG_ON.
- */
-#define BUG_WARNING_TRAP 0x1000000
-
-#ifdef CONFIG_BUG
-#define BUG() do { \
- __asm__ __volatile__( \
- "1: twi 31,0,0\n" \
- ".section __bug_table,\"a\"\n\t" \
- " .long 1b,%0,%1,%2\n" \
- ".previous" \
- : : "i" (__LINE__), "i" (__FILE__), "i" (__FUNCTION__)); \
-} while (0)
-
-#define BUG_ON(x) do { \
- if (!__builtin_constant_p(x) || (x)) { \
- __asm__ __volatile__( \
- "1: twnei %0,0\n" \
- ".section __bug_table,\"a\"\n\t" \
- " .long 1b,%1,%2,%3\n" \
- ".previous" \
- : : "r" (x), "i" (__LINE__), "i" (__FILE__), \
- "i" (__FUNCTION__)); \
- } \
-} while (0)
-
-#define WARN_ON(x) do { \
- if (!__builtin_constant_p(x) || (x)) { \
- __asm__ __volatile__( \
- "1: twnei %0,0\n" \
- ".section __bug_table,\"a\"\n\t" \
- " .long 1b,%1,%2,%3\n" \
- ".previous" \
- : : "r" (x), "i" (__LINE__ + BUG_WARNING_TRAP), \
- "i" (__FILE__), "i" (__FUNCTION__)); \
- } \
-} while (0)
-
-#define HAVE_ARCH_BUG
-#define HAVE_ARCH_BUG_ON
-#define HAVE_ARCH_WARN_ON
-#endif
-
-#include <asm-generic/bug.h>
-
-#endif
diff --git a/include/asm-ppc64/bug.h b/include/asm-ppc64/bug.h
deleted file mode 100644
--- a/include/asm-ppc64/bug.h
+++ /dev/null
@@ -1,69 +0,0 @@
-#ifndef _PPC64_BUG_H
-#define _PPC64_BUG_H
-
-/*
- * Define an illegal instr to trap on the bug.
- * We don't use 0 because that marks the end of a function
- * in the ELF ABI. That's "Boo Boo" in case you wonder...
- */
-#define BUG_OPCODE .long 0x00b00b00 /* For asm */
-#define BUG_ILLEGAL_INSTR "0x00b00b00" /* For BUG macro */
-
-#ifndef __ASSEMBLY__
-
-struct bug_entry {
- unsigned long bug_addr;
- long line;
- const char *file;
- const char *function;
-};
-
-struct bug_entry *find_bug(unsigned long bugaddr);
-
-/*
- * If this bit is set in the line number it means that the trap
- * is for WARN_ON rather than BUG or BUG_ON.
- */
-#define BUG_WARNING_TRAP 0x1000000
-
-#ifdef CONFIG_BUG
-
-#define BUG() do { \
- __asm__ __volatile__( \
- "1: twi 31,0,0\n" \
- ".section __bug_table,\"a\"\n\t" \
- " .llong 1b,%0,%1,%2\n" \
- ".previous" \
- : : "i" (__LINE__), "i" (__FILE__), "i" (__FUNCTION__)); \
-} while (0)
-
-#define BUG_ON(x) do { \
- __asm__ __volatile__( \
- "1: tdnei %0,0\n" \
- ".section __bug_table,\"a\"\n\t" \
- " .llong 1b,%1,%2,%3\n" \
- ".previous" \
- : : "r" ((long long)(x)), "i" (__LINE__), \
- "i" (__FILE__), "i" (__FUNCTION__)); \
-} while (0)
-
-#define WARN_ON(x) do { \
- __asm__ __volatile__( \
- "1: tdnei %0,0\n" \
- ".section __bug_table,\"a\"\n\t" \
- " .llong 1b,%1,%2,%3\n" \
- ".previous" \
- : : "r" ((long long)(x)), \
- "i" (__LINE__ + BUG_WARNING_TRAP), \
- "i" (__FILE__), "i" (__FUNCTION__)); \
-} while (0)
-
-#define HAVE_ARCH_BUG
-#define HAVE_ARCH_BUG_ON
-#define HAVE_ARCH_WARN_ON
-#endif
-#endif
-
-#include <asm-generic/bug.h>
-
-#endif
^ permalink raw reply
* Re: Marvell MV64360 interrupt question
From: Walter L. Wimer III @ 2005-09-09 19:09 UTC (permalink / raw)
To: Linux PPC Embedded list
In-Reply-To: <1126287092.21092.14.camel@excalibur.timesys.com>
Thinking about this some more, I think the cascade mechanism I suggested
earlier is backwards. Architecturally, I think it makes more sense to
define a platform-specific function like boardXYZ_get_irq() in
boardXYZ_setup.c that knows all of the idiosyncrasies of the board and
calls whatever standard PIC libraries it needs in order to do the right
thing. Then we set ppc_md.get_irq = boardXYZ_get_irq;
I looked around, and lo and behold, the Radstone PPC7D already "stole"
my idea. :-) :-)
static int ppc7d_get_irq(struct pt_regs *regs)
{
int irq;
irq = mv64360_get_irq(regs);
if (irq == (mv64360_irq_base + MV64x60_IRQ_GPP28))
irq = i8259_irq(regs);
return irq;
}
Any comments on the "extra" mv64x60_read() call in mv64360_get_irq() are
still welcome.
Thanks!
Walt
On Fri, 2005-09-09 at 13:31 -0400, Walter L. Wimer III wrote:
> BTW, the reason I'm looking at this code is that the board I'm working
> on has a cascaded interrupt controller (implemented in an FPGA) feeding
> into the MV64360 interrupt controller. I'm thinking about adding a
> cascade mechanism to mv64360_pic.c similar to the one in the OpenPIC
> code (i.e. like the openpic_hookup_cascade() function). Any opinions on
> whether this is a good idea or a bad one?
>
>
>
> Thanks!!!
>
> Walt
^ permalink raw reply
* Re: Marvell MV64360 interrupt question
From: Dale Farnsworth @ 2005-09-09 19:27 UTC (permalink / raw)
To: linuxppc-embedded
In-Reply-To: <1126287092.21092.14.camel@excalibur.timesys.com>
On Fri, Sep 09, 2005 at 05:31:32PM +0000, Walter L. Wimer III wrote:
> I'm looking at arch/ppc/syslib/mv64360_pic.c in the 2.6.13 kernel and I
> see the following code:
>
> int
> mv64360_get_irq(struct pt_regs *regs)
> {
> .
> .
> .
> if (irq == -1) {
> irq = mv64x60_read(&bh, MV64360_IC_MAIN_CAUSE_HI);
> irq = __ilog2((irq & 0x1f0003f7) & ppc_cached_irq_mask[1]);
>
> if (irq == -1)
> irq = -2; /* bogus interrupt, should never happen */
> else {
> if ((irq >= 24) && (irq < MV64x60_IRQ_DOORBELL)) {
> irq_gpp = mv64x60_read(&bh, MV64x60_GPP_INTR_CAUSE);
> irq_gpp = __ilog2(irq_gpp & ppc_cached_irq_mask[2]);
>
> if (irq_gpp == -1)
> irq = -2;
> else {
> irq = irq_gpp + 64;
> mv64x60_write(&bh,
> MV64x60_GPP_INTR_CAUSE,
> (1 << (irq - 64)));
You dropped a ~ on the above line. It confused me for a bit.
> }
> }
> else
> irq += 32;
> }
> }
>
> (void)mv64x60_read(&bh, MV64x60_GPP_INTR_CAUSE);
> .
> .
> .
> }
>
> Does anybody know what the last mv64x60_read() is intended to do? It
> *looks* like it's clearing/acknowledging the interrupt, but I don't see
> anything in the Marvell documentation that suggests that *reading* the
> interrupt cause register has such an effect. From my reading, the
> documentation says that you should write a '0' into the appropriate bit
> position to clear the interrupt.
>
> Hmmm... There's an mv64x60_write() a little earlier in the code... Is
> the "extra" mv64x60_read() here to enforce ordering? If so, should it
> be moved inside the "if" statement so that it's only executed when
> actually necessary?
Yes. It's there to make sure that the clearing of the GPP interrupt
is seen by the hardware and takes effect before we return from the function.
> And what about locking? The mv64x60_xxxx() functions are protected by a
> spinlock, but if we're trying to enforce ordering, shouldn't we hold the
> lock during the entire write+read operation, rather than dropping and
> reacquiring the lock in between?
No additional locking is necessary. In fact, it seems to me that the 32-bit
register reads and writes are already atomic and all of the locking using
mv64x60_lock is superfluous.
> At the moment, I'm not running into any actual problems here; this just
> caught my eye and I started wondering about it.
>
> BTW, the reason I'm looking at this code is that the board I'm working
> on has a cascaded interrupt controller (implemented in an FPGA) feeding
> into the MV64360 interrupt controller. I'm thinking about adding a
> cascade mechanism to mv64360_pic.c similar to the one in the OpenPIC
> code (i.e. like the openpic_hookup_cascade() function). Any opinions on
> whether this is a good idea or a bad one?
Sounds reasonable to me.
-Dale
^ permalink raw reply
* [PATCH] cpm_uart: Made non-console uart work
From: Murch, Christopher @ 2005-09-09 19:21 UTC (permalink / raw)
To: linuxppc-embedded
We've recently applied the 2.6.13 patch. We're running on an embedded
platform using 3 of the cpm uart ports on an 8xx cpu. After applying the
2.6.13 patch the non-console uarts no longer work. Upon investigation, we
have found that cpu2cpm_addr() is giving us invalid results for memory
addresses derived from dma_alloc_coherent(). This causes the cpm to hang.
We believe that the better approach would be to use the dma address supplied
by the call to dma_alloc_coherent() instead of trying to convert using
bus_to_virt() and virt_to_bus(). We believe this is the approach taken by
other drivers in the 2.6 kernel. Any comments?
Thanks for your help.
-Chris
cmurch@mrv.com
^ permalink raw reply
* Re: Marvell MV64360 interrupt question
From: Walter L. Wimer III @ 2005-09-09 19:52 UTC (permalink / raw)
To: Linux PPC Embedded list
In-Reply-To: <20050909192739.GA5171@xyzzy.farnsworth.org>
Thanks for your response, Dale!
Walt
On Fri, 2005-09-09 at 12:27 -0700, Dale Farnsworth wrote:
> On Fri, Sep 09, 2005 at 05:31:32PM +0000, Walter L. Wimer III wrote:
> > mv64x60_write(&bh,
> > MV64x60_GPP_INTR_CAUSE,
> > (1 << (irq - 64)));
>
> You dropped a ~ on the above line. It confused me for a bit.
>
Ooops! Sorry about that!!! Yikes!
> > Hmmm... There's an mv64x60_write() a little earlier in the code... Is
> > the "extra" mv64x60_read() here to enforce ordering? If so, should it
> > be moved inside the "if" statement so that it's only executed when
> > actually necessary?
>
> Yes. It's there to make sure that the clearing of the GPP interrupt
> is seen by the hardware and takes effect before we return from the function.
>
> > And what about locking? The mv64x60_xxxx() functions are protected by a
> > spinlock, but if we're trying to enforce ordering, shouldn't we hold the
> > lock during the entire write+read operation, rather than dropping and
> > reacquiring the lock in between?
>
> No additional locking is necessary. In fact, it seems to me that the 32-bit
> register reads and writes are already atomic and all of the locking using
> mv64x60_lock is superfluous.
I wondered about that, too....
>
> -Dale
> _______________________________________________
> Linuxppc-embedded mailing list
> Linuxppc-embedded@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-embedded
^ permalink raw reply
* Re: [PATCH] cpm_uart: Made non-console uart work
From: Pantelis Antoniou @ 2005-09-09 19:59 UTC (permalink / raw)
To: linuxppc-embedded
In-Reply-To: <19EE6EC66973A5408FBE4CB7772F6F0A02FA20CD@ltnmail.xyplex.com>
On Friday 09 September 2005 22:21, Murch, Christopher wrote:
> We've recently applied the 2.6.13 patch. We're running on an embedded
> platform using 3 of the cpm uart ports on an 8xx cpu. After applying the
> 2.6.13 patch the non-console uarts no longer work. Upon investigation, we
> have found that cpu2cpm_addr() is giving us invalid results for memory
> addresses derived from dma_alloc_coherent(). This causes the cpm to hang.
> We believe that the better approach would be to use the dma address
> supplied by the call to dma_alloc_coherent() instead of trying to convert
> using bus_to_virt() and virt_to_bus(). We believe this is the approach
> taken by other drivers in the 2.6 kernel. Any comments?
> Thanks for your help.
>
Yes, it would be proper. This is a temporary hack.
What is the IMAP_ADDR value?
And where is the consistent pool located at your board?
> -Chris
> cmurch@mrv.com
Regards
Pantelis
^ permalink raw reply
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