* [PATCH 1/2] Move Virtex-II Pro / ML300 port over to the platform bus.
From: Grant Likely @ 2005-09-10 7:36 UTC (permalink / raw)
To: linuxppc-embedded
This is a large patch that moves the ML300 to the platform bus.
It also isolates most of the linux tree from changes to the xparameters.h
file. Ultimately, the goal is to move everything over to the flattened
device tree for telling the kernel about devices. That way xparameters.h
can go away entirely for the kernel proper. (Isolated to the bootloader)
This patch will be split up into smaller parts before submitting to mainlin=
e
Comments are appreciated.
---
arch/ppc/Kconfig.debug | 2 -
arch/ppc/boot/common/ns16550.c | 15 ++++
arch/ppc/boot/simple/embed_config.c | 3 +
arch/ppc/platforms/4xx/Kconfig | 5 -
arch/ppc/platforms/4xx/Makefile | 3 -
arch/ppc/platforms/4xx/virtex-ii_pro.c | 60 ------------------
arch/ppc/platforms/4xx/virtex-ii_pro.h | 74 ++----------------=
----
arch/ppc/platforms/4xx/xilinx_ml300.c | 60 +++++++++++-------
arch/ppc/platforms/4xx/xilinx_ml300.h | 2 -
arch/ppc/platforms/4xx/xilinx_ml300_devices.c | 71 ++++++++++++++++++=
+++
arch/ppc/platforms/4xx/xparameters/xparameters.h | 51 +++++++++++++++
arch/ppc/syslib/Makefile | 2 -
arch/ppc/syslib/gen550_dbg.c | 2 +
arch/ppc/syslib/xilinx_pic.c | 12 ++--
include/asm-ppc/ppc_sys.h | 2 +
include/asm-ppc/xparameters.h | 18 -----
16 files changed, 196 insertions(+), 186 deletions(-)
delete mode 100644 arch/ppc/platforms/4xx/virtex-ii_pro.c
create mode 100644 arch/ppc/platforms/4xx/xilinx_ml300_devices.c
create mode 100644 arch/ppc/platforms/4xx/xparameters/xparameters.h
delete mode 100644 include/asm-ppc/xparameters.h
c434b6a7edfa498ed01ee9c3677e687bad87d805
diff --git a/arch/ppc/Kconfig.debug b/arch/ppc/Kconfig.debug
--- a/arch/ppc/Kconfig.debug
+++ b/arch/ppc/Kconfig.debug
@@ -66,7 +66,7 @@ config SERIAL_TEXT_DEBUG
=20
config PPC_OCP
=09bool
-=09depends on IBM_OCP || XILINX_OCP
+=09depends on IBM_OCP
=09default y
=20
endmenu
diff --git a/arch/ppc/boot/common/ns16550.c b/arch/ppc/boot/common/ns16550.=
c
--- a/arch/ppc/boot/common/ns16550.c
+++ b/arch/ppc/boot/common/ns16550.c
@@ -11,6 +11,10 @@
#include "nonstdio.h"
#include "serial.h"
=20
+#if defined(CONFIG_VIRTEX_II_PRO)
+#include <platforms/4xx/xparameters/xparameters.h>
+#endif
+
#define SERIAL_BAUD=099600
=20
extern unsigned long ISA_io;
@@ -25,6 +29,7 @@ unsigned long serial_init(int chan, void
{
=09unsigned long com_port;
=09unsigned char lcr, dlm;
+=09unsigned long baud_base;
=20
=09/* We need to find out which type io we're expecting. If it's
=09 * 'SERIAL_IO_PORT', we get an offset from the isa_io_base.
@@ -43,6 +48,12 @@ unsigned long serial_init(int chan, void
=20
=09/* How far apart the registers are. */
=09shift =3D rs_table[chan].iomem_reg_shift;
+=09baud_base =3D rs_table[chan].baud_base;
+#if defined(BASE_BAUD)
+=09if (!baud_base)
+=09=09baud_base =3D BASE_BAUD;
+#endif
+
=09
=09/* save the LCR */
=09lcr =3D inb(com_port + (UART_LCR << shift));
@@ -62,9 +73,9 @@ unsigned long serial_init(int chan, void
=09else {
=09=09/* Input clock. */
=09=09outb(com_port + (UART_DLL << shift),
-=09=09 (BASE_BAUD / SERIAL_BAUD) & 0xFF);
+=09=09 (baud_base / SERIAL_BAUD) & 0xFF);
=09=09outb(com_port + (UART_DLM << shift),
-=09=09 (BASE_BAUD / SERIAL_BAUD) >> 8);
+=09=09 (baud_base / SERIAL_BAUD) >> 8);
=09=09/* 8 data, 1 stop, no parity */
=09=09outb(com_port + (UART_LCR << shift), 0x03);
=09=09/* RTS/DTR */
diff --git a/arch/ppc/boot/simple/embed_config.c
b/arch/ppc/boot/simple/embed_config.c
--- a/arch/ppc/boot/simple/embed_config.c
+++ b/arch/ppc/boot/simple/embed_config.c
@@ -21,6 +21,9 @@
#ifdef CONFIG_40x
#include <asm/io.h>
#endif
+#ifdef CONFIG_VIRTEX_II_PRO
+#include <platforms/4xx/xparameters/xparameters.h>
+#endif
extern unsigned long timebase_period_ns;
=20
/* For those boards that don't provide one.
diff --git a/arch/ppc/platforms/4xx/Kconfig b/arch/ppc/platforms/4xx/Kconfi=
g
--- a/arch/ppc/platforms/4xx/Kconfig
+++ b/arch/ppc/platforms/4xx/Kconfig
@@ -212,11 +212,6 @@ config VIRTEX_II_PRO_TLB_FIX
=09 It is safe to say Y here, but there is a performance impact.
=09 Say N if unsure.
=20
-config XILINX_OCP
-=09bool
-=09depends on VIRTEX_II_PRO
-=09default y
-
config STB03xxx
=09bool
=09depends on REDWOOD_5 || REDWOOD_6
diff --git a/arch/ppc/platforms/4xx/Makefile b/arch/ppc/platforms/4xx/Makef=
ile
--- a/arch/ppc/platforms/4xx/Makefile
+++ b/arch/ppc/platforms/4xx/Makefile
@@ -14,7 +14,7 @@ obj-$(CONFIG_REDWOOD_5)=09=09+=3D redwood5.o
obj-$(CONFIG_REDWOOD_6)=09=09+=3D redwood6.o
obj-$(CONFIG_SYCAMORE)=09=09+=3D sycamore.o
obj-$(CONFIG_WALNUT)=09=09+=3D walnut.o
-obj-$(CONFIG_XILINX_ML300)=09+=3D xilinx_ml300.o
+obj-$(CONFIG_XILINX_ML300)=09+=3D xilinx_ml300.o xilinx_ml300_devices.o
=20
obj-$(CONFIG_405GP)=09=09+=3D ibm405gp.o
obj-$(CONFIG_REDWOOD_5)=09=09+=3D ibmstb4.o
@@ -26,4 +26,3 @@ obj-$(CONFIG_440GX)=09=09+=3D ibm440gx.o
obj-$(CONFIG_440SP)=09=09+=3D ibm440sp.o
obj-$(CONFIG_405EP)=09=09+=3D ibm405ep.o
obj-$(CONFIG_405GPR)=09=09+=3D ibm405gpr.o
-obj-$(CONFIG_VIRTEX_II_PRO)=09+=3D virtex-ii_pro.o
diff --git a/arch/ppc/platforms/4xx/virtex-ii_pro.c
b/arch/ppc/platforms/4xx/virtex-ii_pro.c
deleted file mode 100644
--- a/arch/ppc/platforms/4xx/virtex-ii_pro.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * arch/ppc/platforms/4xx/virtex-ii_pro.c
- *
- * Author: MontaVista Software, Inc.
- * source@mvista.com
- *
- * 2002-2004 (c) MontaVista Software, Inc. This file is licensed under th=
e
- * terms of the GNU General Public License version 2. This program is lic=
ensed
- * "as is" without any warranty of any kind, whether express or implied.
- */
-
-#include <linux/config.h>
-#include <linux/init.h>
-#include <asm/ocp.h>
-#include "virtex-ii_pro.h"
-
-/* Have OCP take care of the serial ports. */
-struct ocp_def core_ocp[] =3D {
-#ifdef XPAR_UARTNS550_0_BASEADDR
-=09{ .vendor=09=3D OCP_VENDOR_XILINX,
-=09 .function=09=3D OCP_FUNC_16550,
-=09 .index=09=3D 0,
-=09 .paddr=09=3D XPAR_UARTNS550_0_BASEADDR,
-=09 .irq=09=09=3D XPAR_INTC_0_UARTNS550_0_VEC_ID,
-=09 .pm=09=09=3D OCP_CPM_NA
-=09},
-#ifdef XPAR_UARTNS550_1_BASEADDR
-=09{ .vendor=09=3D OCP_VENDOR_XILINX,
-=09 .function=09=3D OCP_FUNC_16550,
-=09 .index=09=3D 1,
-=09 .paddr=09=3D XPAR_UARTNS550_1_BASEADDR,
-=09 .irq=09=09=3D XPAR_INTC_0_UARTNS550_1_VEC_ID,
-=09 .pm=09=09=3D OCP_CPM_NA
-=09},
-#ifdef XPAR_UARTNS550_2_BASEADDR
-=09{ .vendor=09=3D OCP_VENDOR_XILINX,
-=09 .function=09=3D OCP_FUNC_16550,
-=09 .index=09=3D 2,
-=09 .paddr=09=3D XPAR_UARTNS550_2_BASEADDR,
-=09 .irq=09=09=3D XPAR_INTC_0_UARTNS550_2_VEC_ID,
-=09 .pm=09=09=3D OCP_CPM_NA
-=09},
-#ifdef XPAR_UARTNS550_3_BASEADDR
-=09{ .vendor=09=3D OCP_VENDOR_XILINX,
-=09 .function=09=3D OCP_FUNC_16550,
-=09 .index=09=3D 3,
-=09 .paddr=09=3D XPAR_UARTNS550_3_BASEADDR,
-=09 .irq=09=09=3D XPAR_INTC_0_UARTNS550_3_VEC_ID,
-=09 .pm=09=09=3D OCP_CPM_NA
-=09},
-#ifdef XPAR_UARTNS550_4_BASEADDR
-#error Edit this file to add more devices.
-#endif=09=09=09/* 4 */
-#endif=09=09=09/* 3 */
-#endif=09=09=09/* 2 */
-#endif=09=09=09/* 1 */
-#endif=09=09=09/* 0 */
-=09{ .vendor=09=3D OCP_VENDOR_INVALID
-=09}
-};
diff --git a/arch/ppc/platforms/4xx/virtex-ii_pro.h
b/arch/ppc/platforms/4xx/virtex-ii_pro.h
--- a/arch/ppc/platforms/4xx/virtex-ii_pro.h
+++ b/arch/ppc/platforms/4xx/virtex-ii_pro.h
@@ -15,84 +15,26 @@
#ifndef __ASM_VIRTEXIIPRO_H__
#define __ASM_VIRTEXIIPRO_H__
=20
-#include <linux/config.h>
-#include <asm/xparameters.h>
-
/* serial defines */
=20
#define RS_TABLE_SIZE 4=09/* change this and add more devices below
=09=09=09=09 if you have more then 4 16x50 UARTs */
=20
-#define BASE_BAUD=09=09(XPAR_UARTNS550_0_CLOCK_FREQ_HZ/16)
-
-/* The serial ports in the Virtex-II Pro have each I/O byte in the
- * LSByte of a word. This means that iomem_reg_shift needs to be 2 to
- * change the byte offsets into word offsets. In addition the base
- * addresses need to have 3 added to them to get to the LSByte.
+/* Ugly, ugly, ugly! BASE_BAUD defined here to keep 8250.c happy.
*/
-#define STD_UART_OP(num)=09=09=09=09=09=09 \
-=09{ 0, BASE_BAUD, 0, XPAR_INTC_0_UARTNS550_##num##_VEC_ID,=09 \
-=09=09ASYNC_BOOT_AUTOCONF,=09=09 =09=09=09 \
-=09=09.iomem_base =3D (u8 *)XPAR_UARTNS550_##num##_BASEADDR + 3, \
-=09=09.iomem_reg_shift =3D 2,=09=09=09=09=09 \
-=09=09.io_type =3D SERIAL_IO_MEM},
-
-#if defined(XPAR_INTC_0_UARTNS550_0_VEC_ID)
-#define ML300_UART0 STD_UART_OP(0)
-#else
-#define ML300_UART0
-#endif
-
-#if defined(XPAR_INTC_0_UARTNS550_1_VEC_ID)
-#define ML300_UART1 STD_UART_OP(1)
-#else
-#define ML300_UART1
+#if !defined(BASE_BAUD)
+ #define BASE_BAUD=09=09(0) /* dummy value; not used */
#endif
=20
-#if defined(XPAR_INTC_0_UARTNS550_2_VEC_ID)
-#define ML300_UART2 STD_UART_OP(2)
-#else
-#define ML300_UART2
-#endif
+#ifndef __ASSEMBLY__
=20
-#if defined(XPAR_INTC_0_UARTNS550_3_VEC_ID)
-#define ML300_UART3 STD_UART_OP(3)
-#else
-#define ML300_UART3
-#endif
+/* Device type enumeration for platform bus definitions */
+enum ppc_sys_devices {
+=09V2PRO_UART,
+};
=20
-#if defined(XPAR_INTC_0_UARTNS550_4_VEC_ID)
-#error Edit this file to add more devices.
-#elif defined(XPAR_INTC_0_UARTNS550_3_VEC_ID)
-#define NR_SER_PORTS=094
-#elif defined(XPAR_INTC_0_UARTNS550_2_VEC_ID)
-#define NR_SER_PORTS=093
-#elif defined(XPAR_INTC_0_UARTNS550_1_VEC_ID)
-#define NR_SER_PORTS=092
-#elif defined(XPAR_INTC_0_UARTNS550_0_VEC_ID)
-#define NR_SER_PORTS=091
-#else
-#define NR_SER_PORTS=090
#endif
=20
-#if defined(CONFIG_UART0_TTYS0)
-#define SERIAL_PORT_DFNS=09\
-=09ML300_UART0=09=09\
-=09ML300_UART1=09=09\
-=09ML300_UART2=09=09\
-=09ML300_UART3
-#endif
-
-#if defined(CONFIG_UART0_TTYS1)
-#define SERIAL_PORT_DFNS=09\
-=09ML300_UART1=09=09\
-=09ML300_UART0=09=09\
-=09ML300_UART2=09=09\
-=09ML300_UART3
-#endif
-
-#define DCRN_CPMFR_BASE=090
-
#include <asm/ibm405.h>
=20
#endif=09=09=09=09/* __ASM_VIRTEXIIPRO_H__ */
diff --git a/arch/ppc/platforms/4xx/xilinx_ml300.c
b/arch/ppc/platforms/4xx/xilinx_ml300.c
--- a/arch/ppc/platforms/4xx/xilinx_ml300.c
+++ b/arch/ppc/platforms/4xx/xilinx_ml300.c
@@ -17,12 +17,14 @@
#include <linux/tty.h>
#include <linux/serial.h>
#include <linux/serial_core.h>
+#include <linux/serial_8250.h>
#include <linux/serialP.h>
#include <asm/io.h>
#include <asm/machdep.h>
-#include <asm/ocp.h>
+#include <asm/ppc_sys.h>
=20
-#include <platforms/4xx/virtex-ii_pro.h>=09/* for NR_SER_PORTS */
+#include <syslib/gen550.h>
+#include "xparameters/xparameters.h"
=20
/*
* As an overview of how the following functions (platform_init,
@@ -80,38 +82,46 @@ ml300_map_io(void)
#endif
}
=20
+#ifdef CONFIG_SERIAL_8250
static void __init
ml300_early_serial_map(void)
{
-#ifdef CONFIG_SERIAL_8250
-=09struct serial_state old_ports[] =3D { SERIAL_PORT_DFNS };
-=09struct uart_port port;
-=09int i;
-
-=09/* Setup ioremapped serial port access */
-=09for (i =3D 0; i < ARRAY_SIZE(old_ports); i++ ) {
-=09=09memset(&port, 0, sizeof(port));
-=09=09port.membase =3D ioremap((phys_addr_t)(old_ports[i].iomem_base), 16)=
;
-=09=09port.irq =3D old_ports[i].irq;
-=09=09port.uartclk =3D old_ports[i].baud_base * 16;
-=09=09port.regshift =3D old_ports[i].iomem_reg_shift;
-=09=09port.iotype =3D SERIAL_IO_MEM;
-=09=09port.flags =3D ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST;
-=09=09port.line =3D i;
-
-=09=09if (early_serial_setup(&port) !=3D 0) {
-=09=09=09printk("Early serial init of port %d failed\n", i);
-=09=09}
+#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
+=09struct uart_port serial_req;
+#endif
+=09struct plat_serial8250_port *pdata;
+=09int i =3D 0;
+
+=09pdata =3D (struct plat_serial8250_port *) ppc_sys_get_pdata(V2PRO_UART)=
;
+=09while(pdata && pdata->flags)
+=09{
+=09=09pdata->membase =3D ioremap(pdata->mapbase, 0x100);
+
+#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
+=09=09memset(&serial_req, 0, sizeof(serial_req));
+=09=09serial_req.mapbase=09=3D pdata->mapbase;
+=09=09serial_req.membase=09=3D pdata->membase;
+=09=09serial_req.irq=09=09=3D pdata->irq;
+=09=09serial_req.uartclk=09=3D pdata->uartclk;
+=09=09serial_req.regshift=09=3D pdata->regshift;
+=09=09serial_req.iotype=09=3D pdata->iotype;
+=09=09serial_req.flags=09=3D pdata->flags;
+=09=09gen550_init(i, &serial_req);
+#endif
+=09=09pdata++;
+=09=09i++;
=09}
-#endif /* CONFIG_SERIAL_8250 */
}
+#endif /* CONFIG_SERIAL_8250 */
=20
void __init
ml300_setup_arch(void)
{
-=09ppc4xx_setup_arch();=09/* calls ppc4xx_find_bridges() */
-
+#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_KGDB)
=09ml300_early_serial_map();
+#endif
+
+=09ppc4xx_setup_arch();=09/* calls ppc4xx_find_bridges() */
=20
=09/* Identify the system */
=09printk(KERN_INFO "Xilinx Virtex-II Pro port\n");
@@ -131,6 +141,8 @@ platform_init(unsigned long r3, unsigned
{
=09ppc4xx_init(r3, r4, r5, r6, r7);
=20
+=09identify_ppc_sys_by_id(mfspr(SPRN_PVR));
+
=09ppc_md.setup_arch =3D ml300_setup_arch;
=09ppc_md.setup_io_mappings =3D ml300_map_io;
=09ppc_md.init_IRQ =3D ml300_init_irq;
diff --git a/arch/ppc/platforms/4xx/xilinx_ml300.h
b/arch/ppc/platforms/4xx/xilinx_ml300.h
--- a/arch/ppc/platforms/4xx/xilinx_ml300.h
+++ b/arch/ppc/platforms/4xx/xilinx_ml300.h
@@ -41,7 +41,7 @@ typedef struct board_info {
#define PPC4xx_ONB_IO_VADDR=090u
#define PPC4xx_ONB_IO_SIZE=090u
=20
-#define PPC4xx_MACHINE_NAME "Xilinx ML300"
+#define PPC4xx_MACHINE_NAME "Xilinx ML300 Reference System"
=20
#endif /* __ASM_XILINX_ML300_H__ */
#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/xilinx_ml300_devices.c
b/arch/ppc/platforms/4xx/xilinx_ml300_devices.c
new file mode 100644
--- /dev/null
+++ b/arch/ppc/platforms/4xx/xilinx_ml300_devices.c
@@ -0,0 +1,71 @@
+/*
+ * arch/ppc/syslib/virtex2pro_devices.c
+ *
+ * Virtex-II Pro Device descriptions
+ *
+ * Maintainer: Grant Likely <grant.likely@gdcanada.com>
+ *
+ * Copyright 2005 General Dynamics Canada Ltd.
+ * Copyright 2005 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify i=
t
+ * under the terms of the GNU General Public License as published by th=
e
+ * Free Software Foundation; either version 2 of the License, or (at you=
r
+ * option) any later version.
+ */
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/device.h>
+#include <linux/serial_8250.h>
+#include <asm/ppc_sys.h>
+#include "virtex-ii_pro.h"
+#include "xparameters/xparameters.h"
+
+struct plat_serial8250_port serial_platform_data[] =3D {
+#ifdef XPAR_OPB_UART16550_0_BASEADDR
+=09{
+=09=09.mapbase =3D XPAR_OPB_UART16550_0_BASEADDR + 3,
+=09=09.irq=09 =3D XPAR_DCR_INTC_0_OPB_UART16550_0_IP2INTC_IRPT_INTR,
+=09=09.iotype=09 =3D UPIO_MEM,
+=09=09.uartclk =3D XPAR_XUARTNS550_CLOCK_HZ,
+=09=09.flags=09 =3D UPF_BOOT_AUTOCONF,
+=09=09.regshift =3D 2,
+=09},
+#endif
+#ifdef XPAR_OPB_UART16550_1_BASEADDR
+=09{
+=09=09.mapbase =3D XPAR_OPB_UART16550_1_BASEADDR + 3,
+=09=09.irq=09 =3D XPAR_DCR_INTC_0_OPB_UART16550_1_IP2INTC_IRPT_INTR,
+=09=09.iotype=09 =3D UPIO_MEM,
+=09=09.uartclk =3D XPAR_XUARTNS550_CLOCK_HZ,
+=09=09.flags=09 =3D UPF_BOOT_AUTOCONF,
+=09=09.regshift =3D 2,
+=09},
+#endif
+=09{ }, /* terminated by empty record */
+};
+
+struct platform_device ppc_sys_platform_devices[] =3D {
+=09[V2PRO_UART] =3D {
+=09=09.name=09=09=3D "serial8250",
+=09=09.id=09=09=3D 0,
+=09=09.dev.platform_data =3D serial_platform_data,
+=09},
+};
+
+struct ppc_sys_spec *cur_ppc_sys_spec;
+struct ppc_sys_spec ppc_sys_specs[] =3D {
+=09{
+=09=09/* Only one entry, always assume the same design */
+=09=09.ppc_sys_name=09=3D "Xilinx ML300 Reference Design",
+=09=09.mask =09=09=3D 0x00000000,
+=09=09.value =09=09=3D 0x00000000,
+=09=09.num_devices=09=3D 1,
+=09=09.device_list=09=3D (enum ppc_sys_devices[])
+=09=09{
+=09=09=09V2PRO_UART,
+=09=09},
+=09},
+};
+
diff --git a/arch/ppc/platforms/4xx/xparameters/xparameters.h
b/arch/ppc/platforms/4xx/xparameters/xparameters.h
new file mode 100644
--- /dev/null
+++ b/arch/ppc/platforms/4xx/xparameters/xparameters.h
@@ -0,0 +1,51 @@
+/*
+ * arch/ppc/platforms/4xx/xparameters/xparameters.h
+ *
+ * This file includes the correct xparameters.h for the CONFIG'ed board
+ *
+ * Authors:
+ * Grant C. Likely, glikely@gmail.com
+ * MontaVista Software, Inc. source@mvista.com
+ *
+ * 2005 (c) Grant C. Likely, glikely@gmail.com
+ * 2004 (c) MontaVista Software, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of an=
y
+ * kind, whether express or implied.
+ */
+
+/*
+ * This file has three purposes:
+ * 1. Include the correct xparameters.h for the configured design
+ * 2. Translate design specific macros from xparam to common names
+ * 3. Provide a SERIAL_PORT_DFNS macro to setup up very early serial ports
+ * zImage debug. Later serial ports are advertised via the platform bu=
s
+ *
+ * The xparameters.h file is the pristine copy generated from Xilinx EDK
+ * toolset. If you need to make changes, make the changes in this file
+ * rather than modifying the generated file. That way if the design chang=
es
+ * then you just need to drop in the new xparameters.h
+ */
+
+#if defined(CONFIG_XILINX_ML300)
+ #include "xparameters_ml300.h"
+
+ /* Values for setting up interrupt controller */
+ #define V2PRO_XINTC_USE_DCR XPAR_XINTC_USE_DCR
+ #define V2PRO_INTC_BASEADDR XPAR_INTC_0_BASEADDR
+ #define V2PRO_INTC_KIND_OF_INTR XPAR_INTC_0_KIND_OF_INTR
+
+ /* zImage serial port definitions */
+ #define SERIAL_PORT_DFNS { \
+ .baud_base =3D XPAR_XUARTNS550_CLOCK_HZ/16, =
\
+ .irq =3D XPAR_DCR_INTC_0_OPB_UART16550_0_IP2INTC_IRPT_=
INTR, \
+ .flags =3D ASYNC_BOOT_AUTOCONF, =
\
+ .iomem_base =3D (u8 *)XPAR_OPB_UART16550_0_BASEADDR + 3, =
\
+ .iomem_reg_shift =3D 2, =
\
+ .io_type =3D SERIAL_IO_MEM, =
\
+ },
+#else
+ /* Add other board xparameter includes here before the #else */
+ #error No *_xparameters.h file included
+#endif
diff --git a/arch/ppc/syslib/Makefile b/arch/ppc/syslib/Makefile
--- a/arch/ppc/syslib/Makefile
+++ b/arch/ppc/syslib/Makefile
@@ -17,7 +17,7 @@ obj-$(CONFIG_440GX)=09=09+=3D ibm440gx_common.
obj-$(CONFIG_440SP)=09=09+=3D ibm440gx_common.o ibm440sp_common.o
ifeq ($(CONFIG_4xx),y)
ifeq ($(CONFIG_VIRTEX_II_PRO),y)
-obj-$(CONFIG_40x)=09=09+=3D xilinx_pic.o
+obj-$(CONFIG_40x)=09=09+=3D xilinx_pic.o ppc_sys.o
else
ifeq ($(CONFIG_403),y)
obj-$(CONFIG_40x)=09=09+=3D ppc403_pic.o
diff --git a/arch/ppc/syslib/gen550_dbg.c b/arch/ppc/syslib/gen550_dbg.c
--- a/arch/ppc/syslib/gen550_dbg.c
+++ b/arch/ppc/syslib/gen550_dbg.c
@@ -155,6 +155,8 @@ serial_close(unsigned long com_port)
void
gen550_init(int i, struct uart_port *serial_req)
{
+=09if (i > RS_TABLE_SIZE)
+=09=09return;
=09rs_table[i].io_type =3D serial_req->iotype;
=09rs_table[i].port =3D serial_req->iobase;
=09rs_table[i].iomem_base =3D serial_req->membase;
diff --git a/arch/ppc/syslib/xilinx_pic.c b/arch/ppc/syslib/xilinx_pic.c
--- a/arch/ppc/syslib/xilinx_pic.c
+++ b/arch/ppc/syslib/xilinx_pic.c
@@ -15,7 +15,7 @@
#include <linux/init.h>
#include <linux/irq.h>
#include <asm/io.h>
-#include <asm/xparameters.h>
+#include <platforms/4xx/xparameters/xparameters.h>
#include <asm/ibm4xx.h>
=20
/* No one else should require these constants, so define them locally here=
. */
@@ -122,14 +122,14 @@ ppc4xx_pic_init(void)
#error NR_IRQS > 32 not supported
#endif
=20
-#if XPAR_XINTC_USE_DCR =3D=3D 0
-=09intc =3D ioremap(XPAR_INTC_0_BASEADDR, 32);
+#if V2PRO_XINTC_USE_DCR =3D=3D 0
+=09intc =3D ioremap(V2PRO_INTC_BASEADDR, 32);
=20
=09printk(KERN_INFO "Xilinx INTC #0 at 0x%08lX mapped to 0x%08lX\n",
-=09 (unsigned long) XPAR_INTC_0_BASEADDR, (unsigned long) intc);
+=09 (unsigned long) V2PRO_INTC_BASEADDR, (unsigned long) intc);
#else
=09printk(KERN_INFO "Xilinx INTC #0 at 0x%08lX (DCR)\n",
-=09 (unsigned long) XPAR_INTC_0_BASEADDR);
+=09 (unsigned long) V2PRO_INTC_BASEADDR);
#endif
=20
=09/*
@@ -149,7 +149,7 @@ ppc4xx_pic_init(void)
=09for (i =3D 0; i < NR_IRQS; ++i) {
=09=09irq_desc[i].handler =3D &xilinx_intc;
=20
-=09=09if (XPAR_INTC_0_KIND_OF_INTR & (0x00000001 << i))
+=09=09if (V2PRO_INTC_KIND_OF_INTR & (0x00000001 << i))
=09=09=09irq_desc[i].status &=3D ~IRQ_LEVEL;
=09=09else
=09=09=09irq_desc[i].status |=3D IRQ_LEVEL;
diff --git a/include/asm-ppc/ppc_sys.h b/include/asm-ppc/ppc_sys.h
--- a/include/asm-ppc/ppc_sys.h
+++ b/include/asm-ppc/ppc_sys.h
@@ -29,6 +29,8 @@
#include <asm/mpc52xx.h>
#elif defined(CONFIG_MPC10X_BRIDGE)
#include <asm/mpc10x.h>
+#elif defined(CONFIG_VIRTEX_II_PRO)
+#include <platforms/4xx/virtex-ii_pro.h>
#else
#error "need definition of ppc_sys_devices"
#endif
diff --git a/include/asm-ppc/xparameters.h b/include/asm-ppc/xparameters.h
deleted file mode 100644
--- a/include/asm-ppc/xparameters.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * include/asm-ppc/xparameters.h
- *
- * This file includes the correct xparameters.h for the CONFIG'ed board
- *
- * Author: MontaVista Software, Inc.
- * source@mvista.com
- *
- * 2004 (c) MontaVista Software, Inc. This file is licensed under the ter=
ms
- * of the GNU General Public License version 2. This program is licensed
- * "as is" without any warranty of any kind, whether express or implied.
- */
-
-#include <linux/config.h>
-
-#if defined(CONFIG_XILINX_ML300)
-#include <platforms/4xx/xparameters/xparameters_ml300.h>
-#endif
^ permalink raw reply
* [PATCH 0/2] RFC: Port Virtex-II Pro code to use the platform bus
From: Grant Likely @ 2005-09-10 7:33 UTC (permalink / raw)
To: linuxppc-embedded
Here is my work to date to bring the V2Pro port over to the platform
bus. I don't expect these to be accepted as-is, but I'm looking for
comments before I get it polished.
Should apply cleanly against 2.6.13 (but may require the TLB patch first)
http://patchwork.ozlabs.org/linuxppc/patch?id=3D2058
Patch 1: changes from the ML300 perspective. I temporarly don't have
access to an ML300 so this is untested (but it compiles). Could
somebody please test this for me?
Patch 2: example patch for another V2PRO based board. This isn't
really acceptable for mainline because it's not based on a reference
or published FPGA design, but it shows the work required to bring up
another board. It also shines some light on what code should be
common between all V2Pro ports (which I'm working on). This one runs
on a 2VP4-FG456 eval board (pls ignore all the references to 2VP30).
^ permalink raw reply
* Re: cpu features testing 32 vs 64 bit
From: Benjamin Herrenschmidt @ 2005-09-09 22:19 UTC (permalink / raw)
To: Kumar Gala
Cc: linuxppc-dev, linuxppc64-dev, linuxppc-embedded,
pantelis.antoniou
In-Reply-To: <D8DEC759-EAB9-457F-AF7B-A10D6593B27A@freescale.com>
>
> I think she lost the I in ICACHE... its a power5 only feature at this
> point.
And good old 601 too :) It has a unified cache. We could make a common
feature bit for these.
Ben.
^ permalink raw reply
* PATCH ppc Merge asm-ppc*/posix_types.h
From: jdl @ 2005-09-09 21:43 UTC (permalink / raw)
To: linuxppc-dev, linuxppc64-dev
Merge asm-ppc/posix_types.h and asm-ppc64/posix_types.h.
include/asm-powerpc/posix_types.h | 129 +++++++++++++++++++++++++++++++++++++
include/asm-ppc/posix_types.h | 111 --------------------------------
include/asm-ppc64/posix_types.h | 119 ----------------------------------
3 files changed, 129 insertions(+), 230 deletions(-)
Signed-off-by: Jon Loeliger <jdl@freescale.com>
Signed-off-by: Kumar Gala <kumar.gala@freescale.com>
---
diff --git a/include/asm-powerpc/posix_types.h b/include/asm-powerpc/posix_types.h
new file mode 100644
--- /dev/null
+++ b/include/asm-powerpc/posix_types.h
@@ -0,0 +1,129 @@
+#ifndef _ASM_POWERPC_POSIX_TYPES_H
+#define _ASM_POWERPC_POSIX_TYPES_H
+
+/*
+ * This file is generally used by user-level software, so you need to
+ * be a little careful about namespace pollution etc. Also, we cannot
+ * assume GCC is being used.
+ */
+
+typedef unsigned long __kernel_ino_t;
+typedef unsigned int __kernel_mode_t;
+typedef long __kernel_off_t;
+typedef int __kernel_pid_t;
+typedef unsigned int __kernel_uid_t;
+typedef unsigned int __kernel_gid_t;
+typedef long __kernel_ptrdiff_t;
+typedef long __kernel_time_t;
+typedef long __kernel_clock_t;
+typedef int __kernel_timer_t;
+typedef int __kernel_clockid_t;
+typedef long __kernel_suseconds_t;
+typedef int __kernel_daddr_t;
+typedef char * __kernel_caddr_t;
+typedef unsigned short __kernel_uid16_t;
+typedef unsigned short __kernel_gid16_t;
+typedef unsigned int __kernel_uid32_t;
+typedef unsigned int __kernel_gid32_t;
+typedef unsigned int __kernel_old_uid_t;
+typedef unsigned int __kernel_old_gid_t;
+
+#ifdef __powerpc64__
+typedef unsigned long __kernel_nlink_t;
+typedef int __kernel_ipc_pid_t;
+typedef unsigned long __kernel_size_t;
+typedef long __kernel_ssize_t;
+typedef unsigned long __kernel_old_dev_t;
+#else
+typedef unsigned short __kernel_nlink_t;
+typedef short __kernel_ipc_pid_t;
+typedef unsigned int __kernel_size_t;
+typedef int __kernel_ssize_t;
+typedef unsigned int __kernel_old_dev_t;
+#endif
+
+#ifdef __powerpc64__
+typedef long long __kernel_loff_t;
+#else
+#ifdef __GNUC__
+typedef long long __kernel_loff_t;
+#endif
+#endif
+
+typedef struct {
+ int val[2];
+} __kernel_fsid_t;
+
+#ifndef __GNUC__
+
+#define __FD_SET(d, set) ((set)->fds_bits[__FDELT(d)] |= __FDMASK(d))
+#define __FD_CLR(d, set) ((set)->fds_bits[__FDELT(d)] &= ~__FDMASK(d))
+#define __FD_ISSET(d, set) (((set)->fds_bits[__FDELT(d)] & __FDMASK(d)) != 0)
+#define __FD_ZERO(set) \
+ ((void) memset ((__ptr_t) (set), 0, sizeof (__kernel_fd_set)))
+
+#else /* __GNUC__ */
+
+#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) \
+ || (__GLIBC__ == 2 && __GLIBC_MINOR__ == 0)
+/* With GNU C, use inline functions instead so args are evaluated only once: */
+
+#undef __FD_SET
+static __inline__ void __FD_SET(unsigned long fd, __kernel_fd_set *fdsetp)
+{
+ unsigned long _tmp = fd / __NFDBITS;
+ unsigned long _rem = fd % __NFDBITS;
+ fdsetp->fds_bits[_tmp] |= (1UL<<_rem);
+}
+
+#undef __FD_CLR
+static __inline__ void __FD_CLR(unsigned long fd, __kernel_fd_set *fdsetp)
+{
+ unsigned long _tmp = fd / __NFDBITS;
+ unsigned long _rem = fd % __NFDBITS;
+ fdsetp->fds_bits[_tmp] &= ~(1UL<<_rem);
+}
+
+#undef __FD_ISSET
+static __inline__ int __FD_ISSET(unsigned long fd, __kernel_fd_set *p)
+{
+ unsigned long _tmp = fd / __NFDBITS;
+ unsigned long _rem = fd % __NFDBITS;
+ return (p->fds_bits[_tmp] & (1UL<<_rem)) != 0;
+}
+
+/*
+ * This will unroll the loop for the normal constant case (8 ints,
+ * for a 256-bit fd_set)
+ */
+#undef __FD_ZERO
+static __inline__ void __FD_ZERO(__kernel_fd_set *p)
+{
+ unsigned long *tmp = (unsigned long *)p->fds_bits;
+ int i;
+
+ if (__builtin_constant_p(__FDSET_LONGS)) {
+ switch (__FDSET_LONGS) {
+ case 16:
+ tmp[12] = 0; tmp[13] = 0; tmp[14] = 0; tmp[15] = 0;
+ tmp[ 8] = 0; tmp[ 9] = 0; tmp[10] = 0; tmp[11] = 0;
+
+ case 8:
+ tmp[ 4] = 0; tmp[ 5] = 0; tmp[ 6] = 0; tmp[ 7] = 0;
+
+ case 4:
+ tmp[ 0] = 0; tmp[ 1] = 0; tmp[ 2] = 0; tmp[ 3] = 0;
+ return;
+ }
+ }
+ i = __FDSET_LONGS;
+ while (i) {
+ i--;
+ *tmp = 0;
+ tmp++;
+ }
+}
+
+#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */
+#endif /* __GNUC__ */
+#endif /* _ASM_POWERPC_POSIX_TYPES_H */
diff --git a/include/asm-ppc/posix_types.h b/include/asm-ppc/posix_types.h
deleted file mode 100644
--- a/include/asm-ppc/posix_types.h
+++ /dev/null
@@ -1,111 +0,0 @@
-#ifndef _PPC_POSIX_TYPES_H
-#define _PPC_POSIX_TYPES_H
-
-/*
- * This file is generally used by user-level software, so you need to
- * be a little careful about namespace pollution etc. Also, we cannot
- * assume GCC is being used.
- */
-
-typedef unsigned long __kernel_ino_t;
-typedef unsigned int __kernel_mode_t;
-typedef unsigned short __kernel_nlink_t;
-typedef long __kernel_off_t;
-typedef int __kernel_pid_t;
-typedef unsigned int __kernel_uid_t;
-typedef unsigned int __kernel_gid_t;
-typedef unsigned int __kernel_size_t;
-typedef int __kernel_ssize_t;
-typedef long __kernel_ptrdiff_t;
-typedef long __kernel_time_t;
-typedef long __kernel_suseconds_t;
-typedef long __kernel_clock_t;
-typedef int __kernel_timer_t;
-typedef int __kernel_clockid_t;
-typedef int __kernel_daddr_t;
-typedef char * __kernel_caddr_t;
-typedef short __kernel_ipc_pid_t;
-typedef unsigned short __kernel_uid16_t;
-typedef unsigned short __kernel_gid16_t;
-typedef unsigned int __kernel_uid32_t;
-typedef unsigned int __kernel_gid32_t;
-
-typedef unsigned int __kernel_old_uid_t;
-typedef unsigned int __kernel_old_gid_t;
-typedef unsigned int __kernel_old_dev_t;
-
-#ifdef __GNUC__
-typedef long long __kernel_loff_t;
-#endif
-
-typedef struct {
- int val[2];
-} __kernel_fsid_t;
-
-#ifndef __GNUC__
-
-#define __FD_SET(d, set) ((set)->fds_bits[__FDELT(d)] |= __FDMASK(d))
-#define __FD_CLR(d, set) ((set)->fds_bits[__FDELT(d)] &= ~__FDMASK(d))
-#define __FD_ISSET(d, set) ((set)->fds_bits[__FDELT(d)] & __FDMASK(d))
-#define __FD_ZERO(set) \
- ((void) memset ((__ptr_t) (set), 0, sizeof (__kernel_fd_set)))
-
-#else /* __GNUC__ */
-
-#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) \
- || (__GLIBC__ == 2 && __GLIBC_MINOR__ == 0)
-/* With GNU C, use inline functions instead so args are evaluated only once: */
-
-#undef __FD_SET
-static __inline__ void __FD_SET(unsigned long fd, __kernel_fd_set *fdsetp)
-{
- unsigned long _tmp = fd / __NFDBITS;
- unsigned long _rem = fd % __NFDBITS;
- fdsetp->fds_bits[_tmp] |= (1UL<<_rem);
-}
-
-#undef __FD_CLR
-static __inline__ void __FD_CLR(unsigned long fd, __kernel_fd_set *fdsetp)
-{
- unsigned long _tmp = fd / __NFDBITS;
- unsigned long _rem = fd % __NFDBITS;
- fdsetp->fds_bits[_tmp] &= ~(1UL<<_rem);
-}
-
-#undef __FD_ISSET
-static __inline__ int __FD_ISSET(unsigned long fd, __kernel_fd_set *p)
-{
- unsigned long _tmp = fd / __NFDBITS;
- unsigned long _rem = fd % __NFDBITS;
- return (p->fds_bits[_tmp] & (1UL<<_rem)) != 0;
-}
-
-/*
- * This will unroll the loop for the normal constant case (8 ints,
- * for a 256-bit fd_set)
- */
-#undef __FD_ZERO
-static __inline__ void __FD_ZERO(__kernel_fd_set *p)
-{
- unsigned int *tmp = (unsigned int *)p->fds_bits;
- int i;
-
- if (__builtin_constant_p(__FDSET_LONGS)) {
- switch (__FDSET_LONGS) {
- case 8:
- tmp[0] = 0; tmp[1] = 0; tmp[2] = 0; tmp[3] = 0;
- tmp[4] = 0; tmp[5] = 0; tmp[6] = 0; tmp[7] = 0;
- return;
- }
- }
- i = __FDSET_LONGS;
- while (i) {
- i--;
- *tmp = 0;
- tmp++;
- }
-}
-
-#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */
-#endif /* __GNUC__ */
-#endif /* _PPC_POSIX_TYPES_H */
diff --git a/include/asm-ppc64/posix_types.h b/include/asm-ppc64/posix_types.h
deleted file mode 100644
--- a/include/asm-ppc64/posix_types.h
+++ /dev/null
@@ -1,119 +0,0 @@
-#ifndef _PPC64_POSIX_TYPES_H
-#define _PPC64_POSIX_TYPES_H
-
-/*
- * This file is generally used by user-level software, so you need to
- * be a little careful about namespace pollution etc. Also, we cannot
- * assume GCC is being used.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-typedef unsigned long __kernel_ino_t;
-typedef unsigned long __kernel_nlink_t;
-typedef unsigned int __kernel_mode_t;
-typedef long __kernel_off_t;
-typedef long long __kernel_loff_t;
-typedef int __kernel_pid_t;
-typedef int __kernel_ipc_pid_t;
-typedef unsigned int __kernel_uid_t;
-typedef unsigned int __kernel_gid_t;
-typedef unsigned long __kernel_size_t;
-typedef long __kernel_ssize_t;
-typedef long __kernel_ptrdiff_t;
-typedef long __kernel_time_t;
-typedef int __kernel_timer_t;
-typedef int __kernel_clockid_t;
-typedef long __kernel_suseconds_t;
-typedef long __kernel_clock_t;
-typedef int __kernel_daddr_t;
-typedef char * __kernel_caddr_t;
-typedef unsigned short __kernel_uid16_t;
-typedef unsigned short __kernel_gid16_t;
-typedef unsigned int __kernel_uid32_t;
-typedef unsigned int __kernel_gid32_t;
-
-typedef unsigned int __kernel_old_uid_t;
-typedef unsigned int __kernel_old_gid_t;
-typedef unsigned long __kernel_old_dev_t;
-
-typedef struct {
- int val[2];
-} __kernel_fsid_t;
-
-#ifndef __GNUC__
-
-#define __FD_SET(d, set) ((set)->fds_bits[__FDELT(d)] |= __FDMASK(d))
-#define __FD_CLR(d, set) ((set)->fds_bits[__FDELT(d)] &= ~__FDMASK(d))
-#define __FD_ISSET(d, set) (((set)->fds_bits[__FDELT(d)] & __FDMASK(d)) != 0)
-#define __FD_ZERO(set) \
- ((void) memset ((__ptr_t) (set), 0, sizeof (__kernel_fd_set)))
-
-#else /* __GNUC__ */
-
-#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) \
- || (__GLIBC__ == 2 && __GLIBC_MINOR__ == 0)
-/* With GNU C, use inline functions instead so args are evaluated only once: */
-
-#undef __FD_SET
-static __inline__ void __FD_SET(unsigned long fd, __kernel_fd_set *fdsetp)
-{
- unsigned long _tmp = fd / __NFDBITS;
- unsigned long _rem = fd % __NFDBITS;
- fdsetp->fds_bits[_tmp] |= (1UL<<_rem);
-}
-
-#undef __FD_CLR
-static __inline__ void __FD_CLR(unsigned long fd, __kernel_fd_set *fdsetp)
-{
- unsigned long _tmp = fd / __NFDBITS;
- unsigned long _rem = fd % __NFDBITS;
- fdsetp->fds_bits[_tmp] &= ~(1UL<<_rem);
-}
-
-#undef __FD_ISSET
-static __inline__ int __FD_ISSET(unsigned long fd, __kernel_fd_set *p)
-{
- unsigned long _tmp = fd / __NFDBITS;
- unsigned long _rem = fd % __NFDBITS;
- return (p->fds_bits[_tmp] & (1UL<<_rem)) != 0;
-}
-
-/*
- * This will unroll the loop for the normal constant case (8 ints,
- * for a 256-bit fd_set)
- */
-#undef __FD_ZERO
-static __inline__ void __FD_ZERO(__kernel_fd_set *p)
-{
- unsigned long *tmp = (unsigned long *)p->fds_bits;
- int i;
-
- if (__builtin_constant_p(__FDSET_LONGS)) {
- switch (__FDSET_LONGS) {
- case 16:
- tmp[12] = 0; tmp[13] = 0; tmp[14] = 0; tmp[15] = 0;
- tmp[ 8] = 0; tmp[ 9] = 0; tmp[10] = 0; tmp[11] = 0;
-
- case 8:
- tmp[ 4] = 0; tmp[ 5] = 0; tmp[ 6] = 0; tmp[ 7] = 0;
-
- case 4:
- tmp[ 0] = 0; tmp[ 1] = 0; tmp[ 2] = 0; tmp[ 3] = 0;
- return;
- }
- }
- i = __FDSET_LONGS;
- while (i) {
- i--;
- *tmp = 0;
- tmp++;
- }
-}
-
-#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */
-#endif /* __GNUC__ */
-#endif /* _PPC64_POSIX_TYPES_H */
^ permalink raw reply
* Re: Serial driver problem from 2.6.12 kernel
From: Mark A. Greer @ 2005-09-09 21:32 UTC (permalink / raw)
To: goog long; +Cc: linuxppc-dev
In-Reply-To: <20050909151714.68070.qmail@web33410.mail.mud.yahoo.com>
On Fri, Sep 09, 2005 at 08:17:14AM -0700, goog long wrote:
> Hi all,
>
> I backported MPSC driver from 2.6.12 to my kernel
> 2.6.10. However, the driver can send characters, but
> cannot receive any characters. Have anyone seen this
> before?
>
> Please also send your feedback to cecolong@yahoo.com
Hmm, a little sparse on info here so its hard to guess.
The mpsc driver is very much influenced by the platform_data that you
pass to it (since there are so many options). One possibility
is that you have the max_idle platform_data field set to 0 which means
that the mpsc reciever will not timeout and therefore the mpsc will not
pass to the driver whatever you've typed until your receive buffer fills up
(which you may not have done in your testing). Try a max_idle value of 40
which seems to work fine for me. Another possibility, of course, is that
you passed in the wrong irq in the platform_data and therefore are not
getting recieving interrupts.
Mark
^ permalink raw reply
* Re: Marvell MV64360 interrupt question
From: Mark A. Greer @ 2005-09-09 21:18 UTC (permalink / raw)
To: Dale Farnsworth; +Cc: linuxppc-embedded
In-Reply-To: <20050909204955.GA15260@xyzzy.farnsworth.org>
On Fri, Sep 09, 2005 at 01:49:55PM -0700, Dale Farnsworth wrote:
> On Fri, Sep 09, 2005 at 08:20:20PM +0000, Walter L. Wimer III wrote:
> > On Fri, 2005-09-09 at 12:27 -0700, Dale Farnsworth wrote:
> > >
> > > No additional locking is necessary. In fact, it seems to me that the 32-bit
> > > register reads and writes are already atomic and all of the locking using
> > > mv64x60_lock is superfluous.
> >
> > Ah ha. mv64x60.h also defines an mv64x60_modify() function that isn't
> > intrinsically atomic, so it needs the spinlock. That in turn requires
> > mv64x60_read() and mv64x60_write() to play along too.
>
> Yes, the lock is needed for mv64x60_modify(), mv64x60_write(). I still
> don't think it's needed for mv64x60_read().
IMHO, the mv64x60_read/write/modify routines should be deleted and the
locking + I/O done explicitly. That makes it more obvious, more
efficient in places where there are multiple writes, etc. in a row (not
as much grabbing/releasing of the spinlock), and is the preferred way to do
things in linux.
A few times now, I almost started to do that...looked at it and went off
to do something else. :) Yes, I'm lazy. Yes, I should do it.
Eventually, I will (however, if you want to, I won't complain ;).
Mark
^ permalink raw reply
* Re: Marvell MV64360 interrupt question
From: Dale Farnsworth @ 2005-09-09 20:49 UTC (permalink / raw)
To: linuxppc-embedded
In-Reply-To: <1126297220.21092.45.camel@excalibur.timesys.com>
On Fri, Sep 09, 2005 at 08:20:20PM +0000, Walter L. Wimer III wrote:
> On Fri, 2005-09-09 at 12:27 -0700, Dale Farnsworth wrote:
> >
> > No additional locking is necessary. In fact, it seems to me that the 32-bit
> > register reads and writes are already atomic and all of the locking using
> > mv64x60_lock is superfluous.
>
> Ah ha. mv64x60.h also defines an mv64x60_modify() function that isn't
> intrinsically atomic, so it needs the spinlock. That in turn requires
> mv64x60_read() and mv64x60_write() to play along too.
Yes, the lock is needed for mv64x60_modify(), mv64x60_write(). I still
don't think it's needed for mv64x60_read().
-Dale
^ permalink raw reply
* Re: Marvell MV64360 interrupt question
From: Walter L. Wimer III @ 2005-09-09 20:20 UTC (permalink / raw)
To: Linux PPC Embedded list
In-Reply-To: <20050909192739.GA5171@xyzzy.farnsworth.org>
On Fri, 2005-09-09 at 12:27 -0700, Dale Farnsworth wrote:
>
> No additional locking is necessary. In fact, it seems to me that the 32-bit
> register reads and writes are already atomic and all of the locking using
> mv64x60_lock is superfluous.
Ah ha. mv64x60.h also defines an mv64x60_modify() function that isn't
intrinsically atomic, so it needs the spinlock. That in turn requires
mv64x60_read() and mv64x60_write() to play along too.
At least in the general case....
Walt
^ permalink raw reply
* [PATCH] powerpc: Merged ppc_asm.h
From: Kumar Gala @ 2005-09-09 20:02 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev, linuxppc64-dev
Merged ppc_asm.h between ppc32 & ppc64. The majority of the file is
common between the two architectures excluding how a single GPR is
saved/restored and which GPRs are non-volatile.
Additionally, moved the ASM_CONST macro used on ppc64 into ppc_asm.h.
Signed-off-by: Kumar Gala <kumar.gala@freescale.com>
---
commit ba0d4d2e26509b73b7daed0c203f481d0bb06ea0
tree fa78f19160a9174f1fec441c4f3351962c75dad4
parent bbe4b1a6e25818f03d09f3260345bfa4442acca0
author Kumar K. Gala <kumar.gala@freescale.com> Fri, 09 Sep 2005 15:01:18 -0500
committer Kumar K. Gala <kumar.gala@freescale.com> Fri, 09 Sep 2005 15:01:18 -0500
arch/ppc/kernel/head.S | 6 -
arch/ppc/kernel/head_fsl_booke.S | 6 -
include/asm-powerpc/ppc_asm.h | 437 ++++++++++++++++++++++++++++++++++++++
include/asm-ppc/ppc_asm.h | 350 ------------------------------
include/asm-ppc64/cputable.h | 2
include/asm-ppc64/mmu.h | 1
include/asm-ppc64/page.h | 8 -
include/asm-ppc64/ppc_asm.h | 242 ---------------------
8 files changed, 446 insertions(+), 606 deletions(-)
diff --git a/arch/ppc/kernel/head.S b/arch/ppc/kernel/head.S
--- a/arch/ppc/kernel/head.S
+++ b/arch/ppc/kernel/head.S
@@ -804,7 +804,7 @@ load_up_altivec:
beq 1f
add r4,r4,r6
addi r4,r4,THREAD /* want THREAD of last_task_used_altivec */
- SAVE_32VR(0,r10,r4)
+ SAVE_32VRS(0,r10,r4)
mfvscr vr0
li r10,THREAD_VSCR
stvx vr0,r10,r4
@@ -824,7 +824,7 @@ load_up_altivec:
stw r4,THREAD_USED_VR(r5)
lvx vr0,r10,r5
mtvscr vr0
- REST_32VR(0,r10,r5)
+ REST_32VRS(0,r10,r5)
#ifndef CONFIG_SMP
subi r4,r5,THREAD
sub r4,r4,r6
@@ -870,7 +870,7 @@ giveup_altivec:
addi r3,r3,THREAD /* want THREAD of task */
lwz r5,PT_REGS(r3)
cmpwi 0,r5,0
- SAVE_32VR(0, r4, r3)
+ SAVE_32VRS(0, r4, r3)
mfvscr vr0
li r4,THREAD_VSCR
stvx vr0,r4,r3
diff --git a/arch/ppc/kernel/head_fsl_booke.S b/arch/ppc/kernel/head_fsl_booke.S
--- a/arch/ppc/kernel/head_fsl_booke.S
+++ b/arch/ppc/kernel/head_fsl_booke.S
@@ -853,7 +853,7 @@ load_up_spe:
cmpi 0,r4,0
beq 1f
addi r4,r4,THREAD /* want THREAD of last_task_used_spe */
- SAVE_32EVR(0,r10,r4)
+ SAVE_32EVRS(0,r10,r4)
evxor evr10, evr10, evr10 /* clear out evr10 */
evmwumiaa evr10, evr10, evr10 /* evr10 <- ACC = 0 * 0 + ACC */
li r5,THREAD_ACC
@@ -873,7 +873,7 @@ load_up_spe:
stw r4,THREAD_USED_SPE(r5)
evlddx evr4,r10,r5
evmra evr4,evr4
- REST_32EVR(0,r10,r5)
+ REST_32EVRS(0,r10,r5)
#ifndef CONFIG_SMP
subi r4,r5,THREAD
stw r4,last_task_used_spe@l(r3)
@@ -963,7 +963,7 @@ _GLOBAL(giveup_spe)
addi r3,r3,THREAD /* want THREAD of task */
lwz r5,PT_REGS(r3)
cmpi 0,r5,0
- SAVE_32EVR(0, r4, r3)
+ SAVE_32EVRS(0, r4, r3)
evxor evr6, evr6, evr6 /* clear out evr6 */
evmwumiaa evr6, evr6, evr6 /* evr6 <- ACC = 0 * 0 + ACC */
li r4,THREAD_ACC
diff --git a/include/asm-powerpc/ppc_asm.h b/include/asm-powerpc/ppc_asm.h
new file mode 100644
--- /dev/null
+++ b/include/asm-powerpc/ppc_asm.h
@@ -0,0 +1,437 @@
+/*
+ * Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan.
+ */
+
+#ifndef _ASM_POWERPC_PPC_ASM_H
+#define _ASM_POWERPC_PPC_ASM_H
+
+#ifdef __ASSEMBLY__
+
+/*
+ * Macros for storing registers into and loading registers from
+ * exception frames.
+ */
+#ifdef __powerpc64__
+#define SAVE_GPR(n, base) std n,GPR0+8*(n)(base)
+#define REST_GPR(n, base) ld n,GPR0+8*(n)(base)
+#define SAVE_NVGPRS(base) SAVE_8GPRS(14, base); SAVE_10GPRS(22, base)
+#define REST_NVGPRS(base) REST_8GPRS(14, base); REST_10GPRS(22, base)
+#else
+#define SAVE_GPR(n, base) stw n,GPR0+4*(n)(base)
+#define REST_GPR(n, base) lwz n,GPR0+4*(n)(base)
+#define SAVE_NVGPRS(base) SAVE_GPR(13, base); SAVE_8GPRS(14, base); \
+ SAVE_10GPRS(22, base)
+#define REST_NVGPRS(base) REST_GPR(13, base); REST_8GPRS(14, base); \
+ REST_10GPRS(22, base)
+#endif
+
+
+#define SAVE_2GPRS(n, base) SAVE_GPR(n, base); SAVE_GPR(n+1, base)
+#define SAVE_4GPRS(n, base) SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base)
+#define SAVE_8GPRS(n, base) SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base)
+#define SAVE_10GPRS(n, base) SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base)
+#define REST_2GPRS(n, base) REST_GPR(n, base); REST_GPR(n+1, base)
+#define REST_4GPRS(n, base) REST_2GPRS(n, base); REST_2GPRS(n+2, base)
+#define REST_8GPRS(n, base) REST_4GPRS(n, base); REST_4GPRS(n+4, base)
+#define REST_10GPRS(n, base) REST_8GPRS(n, base); REST_2GPRS(n+8, base)
+
+#define SAVE_FPR(n, base) stfd n,THREAD_FPR0+8*(n)(base)
+#define SAVE_2FPRS(n, base) SAVE_FPR(n, base); SAVE_FPR(n+1, base)
+#define SAVE_4FPRS(n, base) SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base)
+#define SAVE_8FPRS(n, base) SAVE_4FPRS(n, base); SAVE_4FPRS(n+4, base)
+#define SAVE_16FPRS(n, base) SAVE_8FPRS(n, base); SAVE_8FPRS(n+8, base)
+#define SAVE_32FPRS(n, base) SAVE_16FPRS(n, base); SAVE_16FPRS(n+16, base)
+#define REST_FPR(n, base) lfd n,THREAD_FPR0+8*(n)(base)
+#define REST_2FPRS(n, base) REST_FPR(n, base); REST_FPR(n+1, base)
+#define REST_4FPRS(n, base) REST_2FPRS(n, base); REST_2FPRS(n+2, base)
+#define REST_8FPRS(n, base) REST_4FPRS(n, base); REST_4FPRS(n+4, base)
+#define REST_16FPRS(n, base) REST_8FPRS(n, base); REST_8FPRS(n+8, base)
+#define REST_32FPRS(n, base) REST_16FPRS(n, base); REST_16FPRS(n+16, base)
+
+#define SAVE_VR(n,b,base) li b,THREAD_VR0+(16*(n)); stvx n,b,base
+#define SAVE_2VRS(n,b,base) SAVE_VR(n,b,base); SAVE_VR(n+1,b,base)
+#define SAVE_4VRS(n,b,base) SAVE_2VRS(n,b,base); SAVE_2VRS(n+2,b,base)
+#define SAVE_8VRS(n,b,base) SAVE_4VRS(n,b,base); SAVE_4VRS(n+4,b,base)
+#define SAVE_16VRS(n,b,base) SAVE_8VRS(n,b,base); SAVE_8VRS(n+8,b,base)
+#define SAVE_32VRS(n,b,base) SAVE_16VRS(n,b,base); SAVE_16VRS(n+16,b,base)
+#define REST_VR(n,b,base) li b,THREAD_VR0+(16*(n)); lvx n,b,base
+#define REST_2VRS(n,b,base) REST_VR(n,b,base); REST_VR(n+1,b,base)
+#define REST_4VRS(n,b,base) REST_2VRS(n,b,base); REST_2VRS(n+2,b,base)
+#define REST_8VRS(n,b,base) REST_4VRS(n,b,base); REST_4VRS(n+4,b,base)
+#define REST_16VRS(n,b,base) REST_8VRS(n,b,base); REST_8VRS(n+8,b,base)
+#define REST_32VRS(n,b,base) REST_16VRS(n,b,base); REST_16VRS(n+16,b,base)
+
+#define SAVE_EVR(n,s,base) evmergehi s,s,n; stw s,THREAD_EVR0+4*(n)(base)
+#define SAVE_2EVRS(n,s,base) SAVE_EVR(n,s,base); SAVE_EVR(n+1,s,base)
+#define SAVE_4EVRS(n,s,base) SAVE_2EVRS(n,s,base); SAVE_2EVRS(n+2,s,base)
+#define SAVE_8EVRS(n,s,base) SAVE_4EVRS(n,s,base); SAVE_4EVRS(n+4,s,base)
+#define SAVE_16EVRS(n,s,base) SAVE_8EVRS(n,s,base); SAVE_8EVRS(n+8,s,base)
+#define SAVE_32EVRS(n,s,base) SAVE_16EVRS(n,s,base); SAVE_16EVRS(n+16,s,base)
+#define REST_EVR(n,s,base) lwz s,THREAD_EVR0+4*(n)(base); evmergelo n,s,n
+#define REST_2EVRS(n,s,base) REST_EVR(n,s,base); REST_EVR(n+1,s,base)
+#define REST_4EVRS(n,s,base) REST_2EVRS(n,s,base); REST_2EVRS(n+2,s,base)
+#define REST_8EVRS(n,s,base) REST_4EVRS(n,s,base); REST_4EVRS(n+4,s,base)
+#define REST_16EVRS(n,s,base) REST_8EVRS(n,s,base); REST_8EVRS(n+8,s,base)
+#define REST_32EVRS(n,s,base) REST_16EVRS(n,s,base); REST_16EVRS(n+16,s,base)
+
+/* Macros to adjust thread priority for Iseries hardware multithreading */
+#define HMT_LOW or 1,1,1
+#define HMT_MEDIUM or 2,2,2
+#define HMT_HIGH or 3,3,3
+
+/* handle instructions that older assemblers may not know */
+#define RFCI .long 0x4c000066 /* rfci instruction */
+#define RFDI .long 0x4c00004e /* rfdi instruction */
+#define RFMCI .long 0x4c00004c /* rfmci instruction */
+
+/*
+ * LOADADDR( rn, name )
+ * loads the address of 'name' into 'rn'
+ *
+ * LOADBASE( rn, name )
+ * loads the address (less the low 16 bits) of 'name' into 'rn'
+ * suitable for base+disp addressing
+ */
+#ifdef __powerpc64__
+#define LOADADDR(rn,name) \
+ lis rn,name##@highest; \
+ ori rn,rn,name##@higher; \
+ rldicr rn,rn,32,31; \
+ oris rn,rn,name##@h; \
+ ori rn,rn,name##@l
+
+#define LOADBASE(rn,name) \
+ lis rn,name@highest; \
+ ori rn,rn,name@higher; \
+ rldicr rn,rn,32,31; \
+ oris rn,rn,name@ha
+
+
+#define SET_REG_TO_CONST(reg, value) \
+ lis reg,(((value)>>48)&0xFFFF); \
+ ori reg,reg,(((value)>>32)&0xFFFF); \
+ rldicr reg,reg,32,31; \
+ oris reg,reg,(((value)>>16)&0xFFFF); \
+ ori reg,reg,((value)&0xFFFF);
+
+#define SET_REG_TO_LABEL(reg, label) \
+ lis reg,(label)@highest; \
+ ori reg,reg,(label)@higher; \
+ rldicr reg,reg,32,31; \
+ oris reg,reg,(label)@h; \
+ ori reg,reg,(label)@l;
+#endif
+
+/* various errata or part fixups */
+#ifdef CONFIG_PPC601_SYNC_FIX
+#define SYNC \
+BEGIN_FTR_SECTION \
+ sync; \
+ isync; \
+END_FTR_SECTION_IFSET(CPU_FTR_601)
+#define SYNC_601 \
+BEGIN_FTR_SECTION \
+ sync; \
+END_FTR_SECTION_IFSET(CPU_FTR_601)
+#define ISYNC_601 \
+BEGIN_FTR_SECTION \
+ isync; \
+END_FTR_SECTION_IFSET(CPU_FTR_601)
+#else
+#define SYNC
+#define SYNC_601
+#define ISYNC_601
+#endif
+
+
+#ifndef CONFIG_SMP
+#define TLBSYNC
+#else /* CONFIG_SMP */
+/* tlbsync is not implemented on 601 */
+#define TLBSYNC \
+BEGIN_FTR_SECTION \
+ tlbsync; \
+ sync; \
+END_FTR_SECTION_IFCLR(CPU_FTR_601)
+#endif
+
+
+/*
+ * This instruction is not implemented on the PPC 603 or 601; however, on
+ * the 403GCX and 405GP tlbia IS defined and tlbie is not.
+ * All of these instructions exist in the 8xx, they have magical powers,
+ * and they must be used.
+ */
+
+#if !defined(CONFIG_4xx) && !defined(CONFIG_8xx)
+#define tlbia \
+ li r4,1024; \
+ mtctr r4; \
+ lis r4,KERNELBASE@h; \
+0: tlbie r4; \
+ addi r4,r4,0x1000; \
+ bdnz 0b
+#endif
+
+
+#ifdef CONFIG_IBM405_ERR77
+#define PPC405_ERR77(ra,rb) dcbt ra, rb;
+#define PPC405_ERR77_SYNC sync;
+#else
+#define PPC405_ERR77(ra,rb)
+#define PPC405_ERR77_SYNC
+#endif
+
+
+#ifdef CONFIG_IBM440EP_ERR42
+#define PPC440EP_ERR42 isync
+#else
+#define PPC440EP_ERR42
+#endif
+
+
+#if defined(CONFIG_BOOKE)
+#define tophys(rd,rs) \
+ addis rd,rs,0
+
+#define tovirt(rd,rs) \
+ addis rd,rs,0
+
+#elif defined(CONFIG_PPC64)
+/* PPPBBB - DRENG If KERNELBASE is always 0xC0...,
+ * Then we can easily do this with one asm insn. -Peter
+ */
+#define tophys(rd,rs) \
+ lis rd,((KERNELBASE>>48)&0xFFFF); \
+ rldicr rd,rd,32,31; \
+ sub rd,rs,rd
+
+#define tovirt(rd,rs) \
+ lis rd,((KERNELBASE>>48)&0xFFFF); \
+ rldicr rd,rd,32,31; \
+ add rd,rs,rd
+#else
+/*
+ * On APUS (Amiga PowerPC cpu upgrade board), we don't know the
+ * physical base address of RAM at compile time.
+ */
+#define tophys(rd,rs) \
+0: addis rd,rs,-KERNELBASE@h; \
+ .section ".vtop_fixup","aw"; \
+ .align 1; \
+ .long 0b; \
+ .previous
+
+#define tovirt(rd,rs) \
+0: addis rd,rs,KERNELBASE@h; \
+ .section ".ptov_fixup","aw"; \
+ .align 1; \
+ .long 0b; \
+ .previous
+#endif
+
+/*
+ * On 64-bit cpus, we use the rfid instruction instead of rfi, but
+ * we then have to make sure we preserve the top 32 bits except for
+ * the 64-bit mode bit, which we clear.
+ */
+#if defined(CONFIG_PPC64BRIDGE)
+#define FIX_SRR1(ra, rb) \
+ mr rb,ra; \
+ mfmsr ra; \
+ clrldi ra,ra,1; /* turn off 64-bit mode */ \
+ rldimi ra,rb,0,32
+#define RFI .long 0x4c000024 /* rfid instruction */
+#define MTMSRD(r) .long (0x7c000164 + ((r) << 21)) /* mtmsrd */
+#define CLR_TOP32(r) rlwinm (r),(r),0,0,31 /* clear top 32 bits */
+#elif defined(CONFIG_PPC64)
+/* Insert the high 32 bits of the MSR into what will be the new
+ MSR (via SRR1 and rfid) This preserves the MSR.SF and MSR.ISF
+ bits. */
+
+#define FIX_SRR1(ra, rb) \
+ mr rb,ra; \
+ mfmsr ra; \
+ rldimi ra,rb,0,32
+
+#define CLR_TOP32(r) rlwinm (r),(r),0,0,31 /* clear top 32 bits */
+
+#else
+#define FIX_SRR1(ra, rb)
+#ifndef CONFIG_40x
+#define RFI rfi
+#else
+#define RFI rfi; b . /* Prevent prefetch past rfi */
+#endif
+#define MTMSRD(r) mtmsr r
+#define CLR_TOP32(r)
+#endif
+
+/* The boring bits... */
+
+/* Condition Register Bit Fields */
+
+#define cr0 0
+#define cr1 1
+#define cr2 2
+#define cr3 3
+#define cr4 4
+#define cr5 5
+#define cr6 6
+#define cr7 7
+
+
+/* General Purpose Registers (GPRs) */
+
+#define r0 0
+#define r1 1
+#define r2 2
+#define r3 3
+#define r4 4
+#define r5 5
+#define r6 6
+#define r7 7
+#define r8 8
+#define r9 9
+#define r10 10
+#define r11 11
+#define r12 12
+#define r13 13
+#define r14 14
+#define r15 15
+#define r16 16
+#define r17 17
+#define r18 18
+#define r19 19
+#define r20 20
+#define r21 21
+#define r22 22
+#define r23 23
+#define r24 24
+#define r25 25
+#define r26 26
+#define r27 27
+#define r28 28
+#define r29 29
+#define r30 30
+#define r31 31
+
+
+/* Floating Point Registers (FPRs) */
+
+#define fr0 0
+#define fr1 1
+#define fr2 2
+#define fr3 3
+#define fr4 4
+#define fr5 5
+#define fr6 6
+#define fr7 7
+#define fr8 8
+#define fr9 9
+#define fr10 10
+#define fr11 11
+#define fr12 12
+#define fr13 13
+#define fr14 14
+#define fr15 15
+#define fr16 16
+#define fr17 17
+#define fr18 18
+#define fr19 19
+#define fr20 20
+#define fr21 21
+#define fr22 22
+#define fr23 23
+#define fr24 24
+#define fr25 25
+#define fr26 26
+#define fr27 27
+#define fr28 28
+#define fr29 29
+#define fr30 30
+#define fr31 31
+
+/* AltiVec Registers (VPRs) */
+
+#define vr0 0
+#define vr1 1
+#define vr2 2
+#define vr3 3
+#define vr4 4
+#define vr5 5
+#define vr6 6
+#define vr7 7
+#define vr8 8
+#define vr9 9
+#define vr10 10
+#define vr11 11
+#define vr12 12
+#define vr13 13
+#define vr14 14
+#define vr15 15
+#define vr16 16
+#define vr17 17
+#define vr18 18
+#define vr19 19
+#define vr20 20
+#define vr21 21
+#define vr22 22
+#define vr23 23
+#define vr24 24
+#define vr25 25
+#define vr26 26
+#define vr27 27
+#define vr28 28
+#define vr29 29
+#define vr30 30
+#define vr31 31
+
+/* SPE Registers (EVPRs) */
+
+#define evr0 0
+#define evr1 1
+#define evr2 2
+#define evr3 3
+#define evr4 4
+#define evr5 5
+#define evr6 6
+#define evr7 7
+#define evr8 8
+#define evr9 9
+#define evr10 10
+#define evr11 11
+#define evr12 12
+#define evr13 13
+#define evr14 14
+#define evr15 15
+#define evr16 16
+#define evr17 17
+#define evr18 18
+#define evr19 19
+#define evr20 20
+#define evr21 21
+#define evr22 22
+#define evr23 23
+#define evr24 24
+#define evr25 25
+#define evr26 26
+#define evr27 27
+#define evr28 28
+#define evr29 29
+#define evr30 30
+#define evr31 31
+
+/* some stab codes */
+#define N_FUN 36
+#define N_RSYM 64
+#define N_SLINE 68
+#define N_SO 100
+
+#define ASM_CONST(x) x
+#else
+ #define __ASM_CONST(x) x##UL
+ #define ASM_CONST(x) __ASM_CONST(x)
+#endif /* __ASSEMBLY__ */
+
+#endif /* _ASM_POWERPC_PPC_ASM_H */
diff --git a/include/asm-ppc/ppc_asm.h b/include/asm-ppc/ppc_asm.h
deleted file mode 100644
--- a/include/asm-ppc/ppc_asm.h
+++ /dev/null
@@ -1,350 +0,0 @@
-/*
- * include/asm-ppc/ppc_asm.h
- *
- * Definitions used by various bits of low-level assembly code on PowerPC.
- *
- * Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <linux/config.h>
-
-/*
- * Macros for storing registers into and loading registers from
- * exception frames.
- */
-#define SAVE_GPR(n, base) stw n,GPR0+4*(n)(base)
-#define SAVE_2GPRS(n, base) SAVE_GPR(n, base); SAVE_GPR(n+1, base)
-#define SAVE_4GPRS(n, base) SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base)
-#define SAVE_8GPRS(n, base) SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base)
-#define SAVE_10GPRS(n, base) SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base)
-#define REST_GPR(n, base) lwz n,GPR0+4*(n)(base)
-#define REST_2GPRS(n, base) REST_GPR(n, base); REST_GPR(n+1, base)
-#define REST_4GPRS(n, base) REST_2GPRS(n, base); REST_2GPRS(n+2, base)
-#define REST_8GPRS(n, base) REST_4GPRS(n, base); REST_4GPRS(n+4, base)
-#define REST_10GPRS(n, base) REST_8GPRS(n, base); REST_2GPRS(n+8, base)
-
-#define SAVE_NVGPRS(base) SAVE_GPR(13, base); SAVE_8GPRS(14, base); \
- SAVE_10GPRS(22, base)
-#define REST_NVGPRS(base) REST_GPR(13, base); REST_8GPRS(14, base); \
- REST_10GPRS(22, base)
-
-#define SAVE_FPR(n, base) stfd n,THREAD_FPR0+8*(n)(base)
-#define SAVE_2FPRS(n, base) SAVE_FPR(n, base); SAVE_FPR(n+1, base)
-#define SAVE_4FPRS(n, base) SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base)
-#define SAVE_8FPRS(n, base) SAVE_4FPRS(n, base); SAVE_4FPRS(n+4, base)
-#define SAVE_16FPRS(n, base) SAVE_8FPRS(n, base); SAVE_8FPRS(n+8, base)
-#define SAVE_32FPRS(n, base) SAVE_16FPRS(n, base); SAVE_16FPRS(n+16, base)
-#define REST_FPR(n, base) lfd n,THREAD_FPR0+8*(n)(base)
-#define REST_2FPRS(n, base) REST_FPR(n, base); REST_FPR(n+1, base)
-#define REST_4FPRS(n, base) REST_2FPRS(n, base); REST_2FPRS(n+2, base)
-#define REST_8FPRS(n, base) REST_4FPRS(n, base); REST_4FPRS(n+4, base)
-#define REST_16FPRS(n, base) REST_8FPRS(n, base); REST_8FPRS(n+8, base)
-#define REST_32FPRS(n, base) REST_16FPRS(n, base); REST_16FPRS(n+16, base)
-
-#define SAVE_VR(n,b,base) li b,THREAD_VR0+(16*(n)); stvx n,b,base
-#define SAVE_2VR(n,b,base) SAVE_VR(n,b,base); SAVE_VR(n+1,b,base)
-#define SAVE_4VR(n,b,base) SAVE_2VR(n,b,base); SAVE_2VR(n+2,b,base)
-#define SAVE_8VR(n,b,base) SAVE_4VR(n,b,base); SAVE_4VR(n+4,b,base)
-#define SAVE_16VR(n,b,base) SAVE_8VR(n,b,base); SAVE_8VR(n+8,b,base)
-#define SAVE_32VR(n,b,base) SAVE_16VR(n,b,base); SAVE_16VR(n+16,b,base)
-#define REST_VR(n,b,base) li b,THREAD_VR0+(16*(n)); lvx n,b,base
-#define REST_2VR(n,b,base) REST_VR(n,b,base); REST_VR(n+1,b,base)
-#define REST_4VR(n,b,base) REST_2VR(n,b,base); REST_2VR(n+2,b,base)
-#define REST_8VR(n,b,base) REST_4VR(n,b,base); REST_4VR(n+4,b,base)
-#define REST_16VR(n,b,base) REST_8VR(n,b,base); REST_8VR(n+8,b,base)
-#define REST_32VR(n,b,base) REST_16VR(n,b,base); REST_16VR(n+16,b,base)
-
-#define SAVE_EVR(n,s,base) evmergehi s,s,n; stw s,THREAD_EVR0+4*(n)(base)
-#define SAVE_2EVR(n,s,base) SAVE_EVR(n,s,base); SAVE_EVR(n+1,s,base)
-#define SAVE_4EVR(n,s,base) SAVE_2EVR(n,s,base); SAVE_2EVR(n+2,s,base)
-#define SAVE_8EVR(n,s,base) SAVE_4EVR(n,s,base); SAVE_4EVR(n+4,s,base)
-#define SAVE_16EVR(n,s,base) SAVE_8EVR(n,s,base); SAVE_8EVR(n+8,s,base)
-#define SAVE_32EVR(n,s,base) SAVE_16EVR(n,s,base); SAVE_16EVR(n+16,s,base)
-
-#define REST_EVR(n,s,base) lwz s,THREAD_EVR0+4*(n)(base); evmergelo n,s,n
-#define REST_2EVR(n,s,base) REST_EVR(n,s,base); REST_EVR(n+1,s,base)
-#define REST_4EVR(n,s,base) REST_2EVR(n,s,base); REST_2EVR(n+2,s,base)
-#define REST_8EVR(n,s,base) REST_4EVR(n,s,base); REST_4EVR(n+4,s,base)
-#define REST_16EVR(n,s,base) REST_8EVR(n,s,base); REST_8EVR(n+8,s,base)
-#define REST_32EVR(n,s,base) REST_16EVR(n,s,base); REST_16EVR(n+16,s,base)
-
-#ifdef CONFIG_PPC601_SYNC_FIX
-#define SYNC \
-BEGIN_FTR_SECTION \
- sync; \
- isync; \
-END_FTR_SECTION_IFSET(CPU_FTR_601)
-#define SYNC_601 \
-BEGIN_FTR_SECTION \
- sync; \
-END_FTR_SECTION_IFSET(CPU_FTR_601)
-#define ISYNC_601 \
-BEGIN_FTR_SECTION \
- isync; \
-END_FTR_SECTION_IFSET(CPU_FTR_601)
-#else
-#define SYNC
-#define SYNC_601
-#define ISYNC_601
-#endif
-
-#ifndef CONFIG_SMP
-#define TLBSYNC
-#else /* CONFIG_SMP */
-/* tlbsync is not implemented on 601 */
-#define TLBSYNC \
-BEGIN_FTR_SECTION \
- tlbsync; \
- sync; \
-END_FTR_SECTION_IFCLR(CPU_FTR_601)
-#endif
-
-/*
- * This instruction is not implemented on the PPC 603 or 601; however, on
- * the 403GCX and 405GP tlbia IS defined and tlbie is not.
- * All of these instructions exist in the 8xx, they have magical powers,
- * and they must be used.
- */
-
-#if !defined(CONFIG_4xx) && !defined(CONFIG_8xx)
-#define tlbia \
- li r4,1024; \
- mtctr r4; \
- lis r4,KERNELBASE@h; \
-0: tlbie r4; \
- addi r4,r4,0x1000; \
- bdnz 0b
-#endif
-
-#ifdef CONFIG_BOOKE
-#define tophys(rd,rs) \
- addis rd,rs,0
-
-#define tovirt(rd,rs) \
- addis rd,rs,0
-
-#else /* CONFIG_BOOKE */
-/*
- * On APUS (Amiga PowerPC cpu upgrade board), we don't know the
- * physical base address of RAM at compile time.
- */
-#define tophys(rd,rs) \
-0: addis rd,rs,-KERNELBASE@h; \
- .section ".vtop_fixup","aw"; \
- .align 1; \
- .long 0b; \
- .previous
-
-#define tovirt(rd,rs) \
-0: addis rd,rs,KERNELBASE@h; \
- .section ".ptov_fixup","aw"; \
- .align 1; \
- .long 0b; \
- .previous
-#endif /* CONFIG_BOOKE */
-
-/*
- * On 64-bit cpus, we use the rfid instruction instead of rfi, but
- * we then have to make sure we preserve the top 32 bits except for
- * the 64-bit mode bit, which we clear.
- */
-#ifdef CONFIG_PPC64BRIDGE
-#define FIX_SRR1(ra, rb) \
- mr rb,ra; \
- mfmsr ra; \
- clrldi ra,ra,1; /* turn off 64-bit mode */ \
- rldimi ra,rb,0,32
-#define RFI .long 0x4c000024 /* rfid instruction */
-#define MTMSRD(r) .long (0x7c000164 + ((r) << 21)) /* mtmsrd */
-#define CLR_TOP32(r) rlwinm (r),(r),0,0,31 /* clear top 32 bits */
-
-#else
-#define FIX_SRR1(ra, rb)
-#ifndef CONFIG_40x
-#define RFI rfi
-#else
-#define RFI rfi; b . /* Prevent prefetch past rfi */
-#endif
-#define MTMSRD(r) mtmsr r
-#define CLR_TOP32(r)
-#endif /* CONFIG_PPC64BRIDGE */
-
-#define RFCI .long 0x4c000066 /* rfci instruction */
-#define RFDI .long 0x4c00004e /* rfdi instruction */
-#define RFMCI .long 0x4c00004c /* rfmci instruction */
-
-#ifdef CONFIG_IBM405_ERR77
-#define PPC405_ERR77(ra,rb) dcbt ra, rb;
-#define PPC405_ERR77_SYNC sync;
-#else
-#define PPC405_ERR77(ra,rb)
-#define PPC405_ERR77_SYNC
-#endif
-
-#ifdef CONFIG_IBM440EP_ERR42
-#define PPC440EP_ERR42 isync
-#else
-#define PPC440EP_ERR42
-#endif
-
-/* The boring bits... */
-
-/* Condition Register Bit Fields */
-
-#define cr0 0
-#define cr1 1
-#define cr2 2
-#define cr3 3
-#define cr4 4
-#define cr5 5
-#define cr6 6
-#define cr7 7
-
-
-/* General Purpose Registers (GPRs) */
-
-#define r0 0
-#define r1 1
-#define r2 2
-#define r3 3
-#define r4 4
-#define r5 5
-#define r6 6
-#define r7 7
-#define r8 8
-#define r9 9
-#define r10 10
-#define r11 11
-#define r12 12
-#define r13 13
-#define r14 14
-#define r15 15
-#define r16 16
-#define r17 17
-#define r18 18
-#define r19 19
-#define r20 20
-#define r21 21
-#define r22 22
-#define r23 23
-#define r24 24
-#define r25 25
-#define r26 26
-#define r27 27
-#define r28 28
-#define r29 29
-#define r30 30
-#define r31 31
-
-
-/* Floating Point Registers (FPRs) */
-
-#define fr0 0
-#define fr1 1
-#define fr2 2
-#define fr3 3
-#define fr4 4
-#define fr5 5
-#define fr6 6
-#define fr7 7
-#define fr8 8
-#define fr9 9
-#define fr10 10
-#define fr11 11
-#define fr12 12
-#define fr13 13
-#define fr14 14
-#define fr15 15
-#define fr16 16
-#define fr17 17
-#define fr18 18
-#define fr19 19
-#define fr20 20
-#define fr21 21
-#define fr22 22
-#define fr23 23
-#define fr24 24
-#define fr25 25
-#define fr26 26
-#define fr27 27
-#define fr28 28
-#define fr29 29
-#define fr30 30
-#define fr31 31
-
-#define vr0 0
-#define vr1 1
-#define vr2 2
-#define vr3 3
-#define vr4 4
-#define vr5 5
-#define vr6 6
-#define vr7 7
-#define vr8 8
-#define vr9 9
-#define vr10 10
-#define vr11 11
-#define vr12 12
-#define vr13 13
-#define vr14 14
-#define vr15 15
-#define vr16 16
-#define vr17 17
-#define vr18 18
-#define vr19 19
-#define vr20 20
-#define vr21 21
-#define vr22 22
-#define vr23 23
-#define vr24 24
-#define vr25 25
-#define vr26 26
-#define vr27 27
-#define vr28 28
-#define vr29 29
-#define vr30 30
-#define vr31 31
-
-#define evr0 0
-#define evr1 1
-#define evr2 2
-#define evr3 3
-#define evr4 4
-#define evr5 5
-#define evr6 6
-#define evr7 7
-#define evr8 8
-#define evr9 9
-#define evr10 10
-#define evr11 11
-#define evr12 12
-#define evr13 13
-#define evr14 14
-#define evr15 15
-#define evr16 16
-#define evr17 17
-#define evr18 18
-#define evr19 19
-#define evr20 20
-#define evr21 21
-#define evr22 22
-#define evr23 23
-#define evr24 24
-#define evr25 25
-#define evr26 26
-#define evr27 27
-#define evr28 28
-#define evr29 29
-#define evr30 30
-#define evr31 31
-
-/* some stab codes */
-#define N_FUN 36
-#define N_RSYM 64
-#define N_SLINE 68
-#define N_SO 100
diff --git a/include/asm-ppc64/cputable.h b/include/asm-ppc64/cputable.h
--- a/include/asm-ppc64/cputable.h
+++ b/include/asm-ppc64/cputable.h
@@ -16,7 +16,7 @@
#define __ASM_PPC_CPUTABLE_H
#include <linux/config.h>
-#include <asm/page.h> /* for ASM_CONST */
+#include <asm/ppc_asm.h> /* for ASM_CONST */
/* Exposed to userland CPU features - Must match ppc32 definitions */
#define PPC_FEATURE_32 0x80000000
diff --git a/include/asm-ppc64/mmu.h b/include/asm-ppc64/mmu.h
--- a/include/asm-ppc64/mmu.h
+++ b/include/asm-ppc64/mmu.h
@@ -14,6 +14,7 @@
#define _PPC64_MMU_H_
#include <linux/config.h>
+#include <asm/ppc_asm.h> /* for ASM_CONST */
#include <asm/page.h>
/*
diff --git a/include/asm-ppc64/page.h b/include/asm-ppc64/page.h
--- a/include/asm-ppc64/page.h
+++ b/include/asm-ppc64/page.h
@@ -11,13 +11,7 @@
*/
#include <linux/config.h>
-
-#ifdef __ASSEMBLY__
- #define ASM_CONST(x) x
-#else
- #define __ASM_CONST(x) x##UL
- #define ASM_CONST(x) __ASM_CONST(x)
-#endif
+#include <asm/ppc_asm.h> /* for ASM_CONST */
/* PAGE_SHIFT determines the page size */
#define PAGE_SHIFT 12
diff --git a/include/asm-ppc64/ppc_asm.h b/include/asm-ppc64/ppc_asm.h
deleted file mode 100644
--- a/include/asm-ppc64/ppc_asm.h
+++ /dev/null
@@ -1,242 +0,0 @@
-/*
- * arch/ppc64/kernel/ppc_asm.h
- *
- * Definitions used by various bits of low-level assembly code on PowerPC.
- *
- * Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _PPC64_PPC_ASM_H
-#define _PPC64_PPC_ASM_H
-/*
- * Macros for storing registers into and loading registers from
- * exception frames.
- */
-#define SAVE_GPR(n, base) std n,GPR0+8*(n)(base)
-#define SAVE_2GPRS(n, base) SAVE_GPR(n, base); SAVE_GPR(n+1, base)
-#define SAVE_4GPRS(n, base) SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base)
-#define SAVE_8GPRS(n, base) SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base)
-#define SAVE_10GPRS(n, base) SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base)
-#define REST_GPR(n, base) ld n,GPR0+8*(n)(base)
-#define REST_2GPRS(n, base) REST_GPR(n, base); REST_GPR(n+1, base)
-#define REST_4GPRS(n, base) REST_2GPRS(n, base); REST_2GPRS(n+2, base)
-#define REST_8GPRS(n, base) REST_4GPRS(n, base); REST_4GPRS(n+4, base)
-#define REST_10GPRS(n, base) REST_8GPRS(n, base); REST_2GPRS(n+8, base)
-
-#define SAVE_NVGPRS(base) SAVE_8GPRS(14, base); SAVE_10GPRS(22, base)
-#define REST_NVGPRS(base) REST_8GPRS(14, base); REST_10GPRS(22, base)
-
-#define SAVE_FPR(n, base) stfd n,THREAD_FPR0+8*(n)(base)
-#define SAVE_2FPRS(n, base) SAVE_FPR(n, base); SAVE_FPR(n+1, base)
-#define SAVE_4FPRS(n, base) SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base)
-#define SAVE_8FPRS(n, base) SAVE_4FPRS(n, base); SAVE_4FPRS(n+4, base)
-#define SAVE_16FPRS(n, base) SAVE_8FPRS(n, base); SAVE_8FPRS(n+8, base)
-#define SAVE_32FPRS(n, base) SAVE_16FPRS(n, base); SAVE_16FPRS(n+16, base)
-#define REST_FPR(n, base) lfd n,THREAD_FPR0+8*(n)(base)
-#define REST_2FPRS(n, base) REST_FPR(n, base); REST_FPR(n+1, base)
-#define REST_4FPRS(n, base) REST_2FPRS(n, base); REST_2FPRS(n+2, base)
-#define REST_8FPRS(n, base) REST_4FPRS(n, base); REST_4FPRS(n+4, base)
-#define REST_16FPRS(n, base) REST_8FPRS(n, base); REST_8FPRS(n+8, base)
-#define REST_32FPRS(n, base) REST_16FPRS(n, base); REST_16FPRS(n+16, base)
-
-#define SAVE_VR(n,b,base) li b,THREAD_VR0+(16*(n)); stvx n,b,base
-#define SAVE_2VRS(n,b,base) SAVE_VR(n,b,base); SAVE_VR(n+1,b,base)
-#define SAVE_4VRS(n,b,base) SAVE_2VRS(n,b,base); SAVE_2VRS(n+2,b,base)
-#define SAVE_8VRS(n,b,base) SAVE_4VRS(n,b,base); SAVE_4VRS(n+4,b,base)
-#define SAVE_16VRS(n,b,base) SAVE_8VRS(n,b,base); SAVE_8VRS(n+8,b,base)
-#define SAVE_32VRS(n,b,base) SAVE_16VRS(n,b,base); SAVE_16VRS(n+16,b,base)
-#define REST_VR(n,b,base) li b,THREAD_VR0+(16*(n)); lvx n,b,base
-#define REST_2VRS(n,b,base) REST_VR(n,b,base); REST_VR(n+1,b,base)
-#define REST_4VRS(n,b,base) REST_2VRS(n,b,base); REST_2VRS(n+2,b,base)
-#define REST_8VRS(n,b,base) REST_4VRS(n,b,base); REST_4VRS(n+4,b,base)
-#define REST_16VRS(n,b,base) REST_8VRS(n,b,base); REST_8VRS(n+8,b,base)
-#define REST_32VRS(n,b,base) REST_16VRS(n,b,base); REST_16VRS(n+16,b,base)
-
-/* Macros to adjust thread priority for Iseries hardware multithreading */
-#define HMT_LOW or 1,1,1
-#define HMT_MEDIUM or 2,2,2
-#define HMT_HIGH or 3,3,3
-
-/* Insert the high 32 bits of the MSR into what will be the new
- MSR (via SRR1 and rfid) This preserves the MSR.SF and MSR.ISF
- bits. */
-
-#define FIX_SRR1(ra, rb) \
- mr rb,ra; \
- mfmsr ra; \
- rldimi ra,rb,0,32
-
-#define CLR_TOP32(r) rlwinm (r),(r),0,0,31 /* clear top 32 bits */
-
-/*
- * LOADADDR( rn, name )
- * loads the address of 'name' into 'rn'
- *
- * LOADBASE( rn, name )
- * loads the address (less the low 16 bits) of 'name' into 'rn'
- * suitable for base+disp addressing
- */
-#define LOADADDR(rn,name) \
- lis rn,name##@highest; \
- ori rn,rn,name##@higher; \
- rldicr rn,rn,32,31; \
- oris rn,rn,name##@h; \
- ori rn,rn,name##@l
-
-#define LOADBASE(rn,name) \
- lis rn,name@highest; \
- ori rn,rn,name@higher; \
- rldicr rn,rn,32,31; \
- oris rn,rn,name@ha
-
-
-#define SET_REG_TO_CONST(reg, value) \
- lis reg,(((value)>>48)&0xFFFF); \
- ori reg,reg,(((value)>>32)&0xFFFF); \
- rldicr reg,reg,32,31; \
- oris reg,reg,(((value)>>16)&0xFFFF); \
- ori reg,reg,((value)&0xFFFF);
-
-#define SET_REG_TO_LABEL(reg, label) \
- lis reg,(label)@highest; \
- ori reg,reg,(label)@higher; \
- rldicr reg,reg,32,31; \
- oris reg,reg,(label)@h; \
- ori reg,reg,(label)@l;
-
-
-/* PPPBBB - DRENG If KERNELBASE is always 0xC0...,
- * Then we can easily do this with one asm insn. -Peter
- */
-#define tophys(rd,rs) \
- lis rd,((KERNELBASE>>48)&0xFFFF); \
- rldicr rd,rd,32,31; \
- sub rd,rs,rd
-
-#define tovirt(rd,rs) \
- lis rd,((KERNELBASE>>48)&0xFFFF); \
- rldicr rd,rd,32,31; \
- add rd,rs,rd
-
-/* Condition Register Bit Fields */
-
-#define cr0 0
-#define cr1 1
-#define cr2 2
-#define cr3 3
-#define cr4 4
-#define cr5 5
-#define cr6 6
-#define cr7 7
-
-
-/* General Purpose Registers (GPRs) */
-
-#define r0 0
-#define r1 1
-#define r2 2
-#define r3 3
-#define r4 4
-#define r5 5
-#define r6 6
-#define r7 7
-#define r8 8
-#define r9 9
-#define r10 10
-#define r11 11
-#define r12 12
-#define r13 13
-#define r14 14
-#define r15 15
-#define r16 16
-#define r17 17
-#define r18 18
-#define r19 19
-#define r20 20
-#define r21 21
-#define r22 22
-#define r23 23
-#define r24 24
-#define r25 25
-#define r26 26
-#define r27 27
-#define r28 28
-#define r29 29
-#define r30 30
-#define r31 31
-
-
-/* Floating Point Registers (FPRs) */
-
-#define fr0 0
-#define fr1 1
-#define fr2 2
-#define fr3 3
-#define fr4 4
-#define fr5 5
-#define fr6 6
-#define fr7 7
-#define fr8 8
-#define fr9 9
-#define fr10 10
-#define fr11 11
-#define fr12 12
-#define fr13 13
-#define fr14 14
-#define fr15 15
-#define fr16 16
-#define fr17 17
-#define fr18 18
-#define fr19 19
-#define fr20 20
-#define fr21 21
-#define fr22 22
-#define fr23 23
-#define fr24 24
-#define fr25 25
-#define fr26 26
-#define fr27 27
-#define fr28 28
-#define fr29 29
-#define fr30 30
-#define fr31 31
-
-#define vr0 0
-#define vr1 1
-#define vr2 2
-#define vr3 3
-#define vr4 4
-#define vr5 5
-#define vr6 6
-#define vr7 7
-#define vr8 8
-#define vr9 9
-#define vr10 10
-#define vr11 11
-#define vr12 12
-#define vr13 13
-#define vr14 14
-#define vr15 15
-#define vr16 16
-#define vr17 17
-#define vr18 18
-#define vr19 19
-#define vr20 20
-#define vr21 21
-#define vr22 22
-#define vr23 23
-#define vr24 24
-#define vr25 25
-#define vr26 26
-#define vr27 27
-#define vr28 28
-#define vr29 29
-#define vr30 30
-#define vr31 31
-
-#endif /* _PPC64_PPC_ASM_H */
^ permalink raw reply
* Re: [PATCH] cpm_uart: Made non-console uart work
From: Pantelis Antoniou @ 2005-09-09 19:59 UTC (permalink / raw)
To: linuxppc-embedded
In-Reply-To: <19EE6EC66973A5408FBE4CB7772F6F0A02FA20CD@ltnmail.xyplex.com>
On Friday 09 September 2005 22:21, Murch, Christopher wrote:
> We've recently applied the 2.6.13 patch. We're running on an embedded
> platform using 3 of the cpm uart ports on an 8xx cpu. After applying the
> 2.6.13 patch the non-console uarts no longer work. Upon investigation, we
> have found that cpu2cpm_addr() is giving us invalid results for memory
> addresses derived from dma_alloc_coherent(). This causes the cpm to hang.
> We believe that the better approach would be to use the dma address
> supplied by the call to dma_alloc_coherent() instead of trying to convert
> using bus_to_virt() and virt_to_bus(). We believe this is the approach
> taken by other drivers in the 2.6 kernel. Any comments?
> Thanks for your help.
>
Yes, it would be proper. This is a temporary hack.
What is the IMAP_ADDR value?
And where is the consistent pool located at your board?
> -Chris
> cmurch@mrv.com
Regards
Pantelis
^ permalink raw reply
* Re: Marvell MV64360 interrupt question
From: Walter L. Wimer III @ 2005-09-09 19:52 UTC (permalink / raw)
To: Linux PPC Embedded list
In-Reply-To: <20050909192739.GA5171@xyzzy.farnsworth.org>
Thanks for your response, Dale!
Walt
On Fri, 2005-09-09 at 12:27 -0700, Dale Farnsworth wrote:
> On Fri, Sep 09, 2005 at 05:31:32PM +0000, Walter L. Wimer III wrote:
> > mv64x60_write(&bh,
> > MV64x60_GPP_INTR_CAUSE,
> > (1 << (irq - 64)));
>
> You dropped a ~ on the above line. It confused me for a bit.
>
Ooops! Sorry about that!!! Yikes!
> > Hmmm... There's an mv64x60_write() a little earlier in the code... Is
> > the "extra" mv64x60_read() here to enforce ordering? If so, should it
> > be moved inside the "if" statement so that it's only executed when
> > actually necessary?
>
> Yes. It's there to make sure that the clearing of the GPP interrupt
> is seen by the hardware and takes effect before we return from the function.
>
> > And what about locking? The mv64x60_xxxx() functions are protected by a
> > spinlock, but if we're trying to enforce ordering, shouldn't we hold the
> > lock during the entire write+read operation, rather than dropping and
> > reacquiring the lock in between?
>
> No additional locking is necessary. In fact, it seems to me that the 32-bit
> register reads and writes are already atomic and all of the locking using
> mv64x60_lock is superfluous.
I wondered about that, too....
>
> -Dale
> _______________________________________________
> Linuxppc-embedded mailing list
> Linuxppc-embedded@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-embedded
^ permalink raw reply
* [PATCH] cpm_uart: Made non-console uart work
From: Murch, Christopher @ 2005-09-09 19:21 UTC (permalink / raw)
To: linuxppc-embedded
We've recently applied the 2.6.13 patch. We're running on an embedded
platform using 3 of the cpm uart ports on an 8xx cpu. After applying the
2.6.13 patch the non-console uarts no longer work. Upon investigation, we
have found that cpu2cpm_addr() is giving us invalid results for memory
addresses derived from dma_alloc_coherent(). This causes the cpm to hang.
We believe that the better approach would be to use the dma address supplied
by the call to dma_alloc_coherent() instead of trying to convert using
bus_to_virt() and virt_to_bus(). We believe this is the approach taken by
other drivers in the 2.6 kernel. Any comments?
Thanks for your help.
-Chris
cmurch@mrv.com
^ permalink raw reply
* Re: Marvell MV64360 interrupt question
From: Dale Farnsworth @ 2005-09-09 19:27 UTC (permalink / raw)
To: linuxppc-embedded
In-Reply-To: <1126287092.21092.14.camel@excalibur.timesys.com>
On Fri, Sep 09, 2005 at 05:31:32PM +0000, Walter L. Wimer III wrote:
> I'm looking at arch/ppc/syslib/mv64360_pic.c in the 2.6.13 kernel and I
> see the following code:
>
> int
> mv64360_get_irq(struct pt_regs *regs)
> {
> .
> .
> .
> if (irq == -1) {
> irq = mv64x60_read(&bh, MV64360_IC_MAIN_CAUSE_HI);
> irq = __ilog2((irq & 0x1f0003f7) & ppc_cached_irq_mask[1]);
>
> if (irq == -1)
> irq = -2; /* bogus interrupt, should never happen */
> else {
> if ((irq >= 24) && (irq < MV64x60_IRQ_DOORBELL)) {
> irq_gpp = mv64x60_read(&bh, MV64x60_GPP_INTR_CAUSE);
> irq_gpp = __ilog2(irq_gpp & ppc_cached_irq_mask[2]);
>
> if (irq_gpp == -1)
> irq = -2;
> else {
> irq = irq_gpp + 64;
> mv64x60_write(&bh,
> MV64x60_GPP_INTR_CAUSE,
> (1 << (irq - 64)));
You dropped a ~ on the above line. It confused me for a bit.
> }
> }
> else
> irq += 32;
> }
> }
>
> (void)mv64x60_read(&bh, MV64x60_GPP_INTR_CAUSE);
> .
> .
> .
> }
>
> Does anybody know what the last mv64x60_read() is intended to do? It
> *looks* like it's clearing/acknowledging the interrupt, but I don't see
> anything in the Marvell documentation that suggests that *reading* the
> interrupt cause register has such an effect. From my reading, the
> documentation says that you should write a '0' into the appropriate bit
> position to clear the interrupt.
>
> Hmmm... There's an mv64x60_write() a little earlier in the code... Is
> the "extra" mv64x60_read() here to enforce ordering? If so, should it
> be moved inside the "if" statement so that it's only executed when
> actually necessary?
Yes. It's there to make sure that the clearing of the GPP interrupt
is seen by the hardware and takes effect before we return from the function.
> And what about locking? The mv64x60_xxxx() functions are protected by a
> spinlock, but if we're trying to enforce ordering, shouldn't we hold the
> lock during the entire write+read operation, rather than dropping and
> reacquiring the lock in between?
No additional locking is necessary. In fact, it seems to me that the 32-bit
register reads and writes are already atomic and all of the locking using
mv64x60_lock is superfluous.
> At the moment, I'm not running into any actual problems here; this just
> caught my eye and I started wondering about it.
>
> BTW, the reason I'm looking at this code is that the board I'm working
> on has a cascaded interrupt controller (implemented in an FPGA) feeding
> into the MV64360 interrupt controller. I'm thinking about adding a
> cascade mechanism to mv64360_pic.c similar to the one in the OpenPIC
> code (i.e. like the openpic_hookup_cascade() function). Any opinions on
> whether this is a good idea or a bad one?
Sounds reasonable to me.
-Dale
^ permalink raw reply
* Re: Marvell MV64360 interrupt question
From: Walter L. Wimer III @ 2005-09-09 19:09 UTC (permalink / raw)
To: Linux PPC Embedded list
In-Reply-To: <1126287092.21092.14.camel@excalibur.timesys.com>
Thinking about this some more, I think the cascade mechanism I suggested
earlier is backwards. Architecturally, I think it makes more sense to
define a platform-specific function like boardXYZ_get_irq() in
boardXYZ_setup.c that knows all of the idiosyncrasies of the board and
calls whatever standard PIC libraries it needs in order to do the right
thing. Then we set ppc_md.get_irq = boardXYZ_get_irq;
I looked around, and lo and behold, the Radstone PPC7D already "stole"
my idea. :-) :-)
static int ppc7d_get_irq(struct pt_regs *regs)
{
int irq;
irq = mv64360_get_irq(regs);
if (irq == (mv64360_irq_base + MV64x60_IRQ_GPP28))
irq = i8259_irq(regs);
return irq;
}
Any comments on the "extra" mv64x60_read() call in mv64360_get_irq() are
still welcome.
Thanks!
Walt
On Fri, 2005-09-09 at 13:31 -0400, Walter L. Wimer III wrote:
> BTW, the reason I'm looking at this code is that the board I'm working
> on has a cascaded interrupt controller (implemented in an FPGA) feeding
> into the MV64360 interrupt controller. I'm thinking about adding a
> cascade mechanism to mv64360_pic.c similar to the one in the OpenPIC
> code (i.e. like the openpic_hookup_cascade() function). Any opinions on
> whether this is a good idea or a bad one?
>
>
>
> Thanks!!!
>
> Walt
^ permalink raw reply
* [PATCH] ppc/ppc64: Merge bug.h into include/asm-powerpc
From: Becky Bruce @ 2005-09-09 18:52 UTC (permalink / raw)
To: linuxppc64-dev, linuxppc-dev
This patch merges bug.h into include/asm-powerpc. Changed the data
structure for bug_entry such that line is always an int on both 32 and
64-bit platforms; removed casts to int from the 64-bit trap code to
reflect this.
Signed-off-by: Kumar Gala <kumar.gala@freescale.com>
Signed-off-by: Becky Bruce <Becky.Bruce@freescale.com>
---
commit fcaf8560dc918048b43867d79efa5b26bd6a9a81
tree 079802fdb229c0e3721b893235e2ef912e30d7cd
parent dfe2ac4994952cadc891f095668f9e582d4402b3
author Becky Bruce <becky.bruce@freescale.com> Fri, 09 Sep 2005 11:15:22 -0500
committer Becky Bruce <becky.bruce@freescale.com> Fri, 09 Sep 2005 11:15:22 -0500
arch/ppc/kernel/traps.c | 2 +
arch/ppc64/kernel/traps.c | 4 +-
include/asm-powerpc/bug.h | 81 +++++++++++++++++++++++++++++++++++++++++++++
include/asm-ppc/bug.h | 58 --------------------------------
include/asm-ppc64/bug.h | 69 --------------------------------------
5 files changed, 84 insertions(+), 130 deletions(-)
diff --git a/arch/ppc/kernel/traps.c b/arch/ppc/kernel/traps.c
--- a/arch/ppc/kernel/traps.c
+++ b/arch/ppc/kernel/traps.c
@@ -553,7 +553,7 @@ extern struct bug_entry __start___bug_ta
#define module_find_bug(x) NULL
#endif
-static struct bug_entry *find_bug(unsigned long bugaddr)
+struct bug_entry *find_bug(unsigned long bugaddr)
{
struct bug_entry *bug;
diff --git a/arch/ppc64/kernel/traps.c b/arch/ppc64/kernel/traps.c
--- a/arch/ppc64/kernel/traps.c
+++ b/arch/ppc64/kernel/traps.c
@@ -389,12 +389,12 @@ check_bug_trap(struct pt_regs *regs)
/* this is a WARN_ON rather than BUG/BUG_ON */
printk(KERN_ERR "Badness in %s at %s:%d\n",
bug->function, bug->file,
- (unsigned int)bug->line & ~BUG_WARNING_TRAP);
+ bug->line & ~BUG_WARNING_TRAP);
show_stack(current, (void *)regs->gpr[1]);
return 1;
}
printk(KERN_CRIT "kernel BUG in %s at %s:%d!\n",
- bug->function, bug->file, (unsigned int)bug->line);
+ bug->function, bug->file, bug->line);
return 0;
}
diff --git a/include/asm-powerpc/bug.h b/include/asm-powerpc/bug.h
new file mode 100644
--- /dev/null
+++ b/include/asm-powerpc/bug.h
@@ -0,0 +1,81 @@
+#ifndef _ASM_POWERPC_BUG_H
+#define _ASM_POWERPC_BUG_H
+
+/*
+ * Define an illegal instr to trap on the bug.
+ * We don't use 0 because that marks the end of a function
+ * in the ELF ABI. That's "Boo Boo" in case you wonder...
+ */
+#define BUG_OPCODE .long 0x00b00b00 /* For asm */
+#define BUG_ILLEGAL_INSTR "0x00b00b00" /* For BUG macro */
+
+#ifndef __ASSEMBLY__
+
+#ifdef __powerpc64__
+#define BUG_TABLE_ENTRY(label, line, file, func) \
+ ".llong " #label "\n .long " #line "\n .llong " #file ", " #func "\n"
+#define TRAP_OP(ra, rb) "1: tdnei " #ra ", " #rb "\n"
+#define DATA_TYPE long long
+#else
+#define BUG_TABLE_ENTRY(label, line, file, func) \
+ ".long " #label ", " #line ", " #file ", " #func "\n"
+#define TRAP_OP(ra, rb) "1: twnei " #ra ", " #rb "\n"
+#define DATA_TYPE int
+#endif /* __powerpc64__ */
+
+struct bug_entry {
+ unsigned long bug_addr;
+ int line;
+ const char *file;
+ const char *function;
+};
+
+struct bug_entry *find_bug(unsigned long bugaddr);
+
+/*
+ * If this bit is set in the line number it means that the trap
+ * is for WARN_ON rather than BUG or BUG_ON.
+ */
+#define BUG_WARNING_TRAP 0x1000000
+
+#ifdef CONFIG_BUG
+
+#define BUG() do { \
+ __asm__ __volatile__( \
+ "1: twi 31,0,0\n" \
+ ".section __bug_table,\"a\"\n\t" \
+ BUG_TABLE_ENTRY(1b,%0,%1,%2) \
+ ".previous" \
+ : : "i" (__LINE__), "i" (__FILE__), "i" (__FUNCTION__)); \
+} while (0)
+
+#define BUG_ON(x) do { \
+ __asm__ __volatile__( \
+ TRAP_OP(%0,0) \
+ ".section __bug_table,\"a\"\n\t" \
+ BUG_TABLE_ENTRY(1b,%1,%2,%3) \
+ ".previous" \
+ : : "r" ((DATA_TYPE)(x)), "i" (__LINE__), \
+ "i" (__FILE__), "i" (__FUNCTION__)); \
+} while (0)
+
+#define WARN_ON(x) do { \
+ __asm__ __volatile__( \
+ TRAP_OP(%0,0) \
+ ".section __bug_table,\"a\"\n\t" \
+ BUG_TABLE_ENTRY(1b,%1,%2,%3) \
+ ".previous" \
+ : : "r" ((DATA_TYPE)(x)), \
+ "i" (__LINE__ + BUG_WARNING_TRAP), \
+ "i" (__FILE__), "i" (__FUNCTION__)); \
+} while (0)
+
+#define HAVE_ARCH_BUG
+#define HAVE_ARCH_BUG_ON
+#define HAVE_ARCH_WARN_ON
+#endif /* CONFIG_BUG */
+#endif /* __ASSEMBLY __ */
+
+#include <asm-generic/bug.h>
+
+#endif /* _ASM_POWERPC_BUG_H */
diff --git a/include/asm-ppc/bug.h b/include/asm-ppc/bug.h
deleted file mode 100644
--- a/include/asm-ppc/bug.h
+++ /dev/null
@@ -1,58 +0,0 @@
-#ifndef _PPC_BUG_H
-#define _PPC_BUG_H
-
-struct bug_entry {
- unsigned long bug_addr;
- int line;
- const char *file;
- const char *function;
-};
-
-/*
- * If this bit is set in the line number it means that the trap
- * is for WARN_ON rather than BUG or BUG_ON.
- */
-#define BUG_WARNING_TRAP 0x1000000
-
-#ifdef CONFIG_BUG
-#define BUG() do { \
- __asm__ __volatile__( \
- "1: twi 31,0,0\n" \
- ".section __bug_table,\"a\"\n\t" \
- " .long 1b,%0,%1,%2\n" \
- ".previous" \
- : : "i" (__LINE__), "i" (__FILE__), "i" (__FUNCTION__)); \
-} while (0)
-
-#define BUG_ON(x) do { \
- if (!__builtin_constant_p(x) || (x)) { \
- __asm__ __volatile__( \
- "1: twnei %0,0\n" \
- ".section __bug_table,\"a\"\n\t" \
- " .long 1b,%1,%2,%3\n" \
- ".previous" \
- : : "r" (x), "i" (__LINE__), "i" (__FILE__), \
- "i" (__FUNCTION__)); \
- } \
-} while (0)
-
-#define WARN_ON(x) do { \
- if (!__builtin_constant_p(x) || (x)) { \
- __asm__ __volatile__( \
- "1: twnei %0,0\n" \
- ".section __bug_table,\"a\"\n\t" \
- " .long 1b,%1,%2,%3\n" \
- ".previous" \
- : : "r" (x), "i" (__LINE__ + BUG_WARNING_TRAP), \
- "i" (__FILE__), "i" (__FUNCTION__)); \
- } \
-} while (0)
-
-#define HAVE_ARCH_BUG
-#define HAVE_ARCH_BUG_ON
-#define HAVE_ARCH_WARN_ON
-#endif
-
-#include <asm-generic/bug.h>
-
-#endif
diff --git a/include/asm-ppc64/bug.h b/include/asm-ppc64/bug.h
deleted file mode 100644
--- a/include/asm-ppc64/bug.h
+++ /dev/null
@@ -1,69 +0,0 @@
-#ifndef _PPC64_BUG_H
-#define _PPC64_BUG_H
-
-/*
- * Define an illegal instr to trap on the bug.
- * We don't use 0 because that marks the end of a function
- * in the ELF ABI. That's "Boo Boo" in case you wonder...
- */
-#define BUG_OPCODE .long 0x00b00b00 /* For asm */
-#define BUG_ILLEGAL_INSTR "0x00b00b00" /* For BUG macro */
-
-#ifndef __ASSEMBLY__
-
-struct bug_entry {
- unsigned long bug_addr;
- long line;
- const char *file;
- const char *function;
-};
-
-struct bug_entry *find_bug(unsigned long bugaddr);
-
-/*
- * If this bit is set in the line number it means that the trap
- * is for WARN_ON rather than BUG or BUG_ON.
- */
-#define BUG_WARNING_TRAP 0x1000000
-
-#ifdef CONFIG_BUG
-
-#define BUG() do { \
- __asm__ __volatile__( \
- "1: twi 31,0,0\n" \
- ".section __bug_table,\"a\"\n\t" \
- " .llong 1b,%0,%1,%2\n" \
- ".previous" \
- : : "i" (__LINE__), "i" (__FILE__), "i" (__FUNCTION__)); \
-} while (0)
-
-#define BUG_ON(x) do { \
- __asm__ __volatile__( \
- "1: tdnei %0,0\n" \
- ".section __bug_table,\"a\"\n\t" \
- " .llong 1b,%1,%2,%3\n" \
- ".previous" \
- : : "r" ((long long)(x)), "i" (__LINE__), \
- "i" (__FILE__), "i" (__FUNCTION__)); \
-} while (0)
-
-#define WARN_ON(x) do { \
- __asm__ __volatile__( \
- "1: tdnei %0,0\n" \
- ".section __bug_table,\"a\"\n\t" \
- " .llong 1b,%1,%2,%3\n" \
- ".previous" \
- : : "r" ((long long)(x)), \
- "i" (__LINE__ + BUG_WARNING_TRAP), \
- "i" (__FILE__), "i" (__FUNCTION__)); \
-} while (0)
-
-#define HAVE_ARCH_BUG
-#define HAVE_ARCH_BUG_ON
-#define HAVE_ARCH_WARN_ON
-#endif
-#endif
-
-#include <asm-generic/bug.h>
-
-#endif
^ permalink raw reply
* Marvell MV64360 interrupt question
From: Walter L. Wimer III @ 2005-09-09 17:31 UTC (permalink / raw)
To: Linux PPC Embedded list
Hi All,
I'm looking at arch/ppc/syslib/mv64360_pic.c in the 2.6.13 kernel and I
see the following code:
int
mv64360_get_irq(struct pt_regs *regs)
{
.
.
.
if (irq == -1) {
irq = mv64x60_read(&bh, MV64360_IC_MAIN_CAUSE_HI);
irq = __ilog2((irq & 0x1f0003f7) & ppc_cached_irq_mask[1]);
if (irq == -1)
irq = -2; /* bogus interrupt, should never happen */
else {
if ((irq >= 24) && (irq < MV64x60_IRQ_DOORBELL)) {
irq_gpp = mv64x60_read(&bh, MV64x60_GPP_INTR_CAUSE);
irq_gpp = __ilog2(irq_gpp & ppc_cached_irq_mask[2]);
if (irq_gpp == -1)
irq = -2;
else {
irq = irq_gpp + 64;
mv64x60_write(&bh,
MV64x60_GPP_INTR_CAUSE,
(1 << (irq - 64)));
}
}
else
irq += 32;
}
}
(void)mv64x60_read(&bh, MV64x60_GPP_INTR_CAUSE);
.
.
.
}
Does anybody know what the last mv64x60_read() is intended to do? It
*looks* like it's clearing/acknowledging the interrupt, but I don't see
anything in the Marvell documentation that suggests that *reading* the
interrupt cause register has such an effect. From my reading, the
documentation says that you should write a '0' into the appropriate bit
position to clear the interrupt.
Hmmm... There's an mv64x60_write() a little earlier in the code... Is
the "extra" mv64x60_read() here to enforce ordering? If so, should it
be moved inside the "if" statement so that it's only executed when
actually necessary?
And what about locking? The mv64x60_xxxx() functions are protected by a
spinlock, but if we're trying to enforce ordering, shouldn't we hold the
lock during the entire write+read operation, rather than dropping and
reacquiring the lock in between?
At the moment, I'm not running into any actual problems here; this just
caught my eye and I started wondering about it.
BTW, the reason I'm looking at this code is that the board I'm working
on has a cascaded interrupt controller (implemented in an FPGA) feeding
into the MV64360 interrupt controller. I'm thinking about adding a
cascade mechanism to mv64360_pic.c similar to the one in the OpenPIC
code (i.e. like the openpic_hookup_cascade() function). Any opinions on
whether this is a good idea or a bad one?
Thanks!!!
Walt
^ permalink raw reply
* Serial driver problem from 2.6.12 kernel
From: goog long @ 2005-09-09 15:17 UTC (permalink / raw)
To: linuxppc-dev
Hi all,
I backported MPSC driver from 2.6.12 to my kernel
2.6.10. However, the driver can send characters, but
cannot receive any characters. Have anyone seen this
before?
Please also send your feedback to cecolong@yahoo.com
Thanks and best regards,
cecolong
__________________________________________________
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Tired of spam? Yahoo! Mail has the best spam protection around
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^ permalink raw reply
* Can the mpc8270 provide the direct IDE interface?
From: FCG WANG Baohua @ 2005-09-09 6:19 UTC (permalink / raw)
To: thomas, Steven.Scholz; +Cc: mattl, linuxppc-embedded
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Dear All:
I have a question when I port the PCMCIA driver to MPC8270 board:
Can the mpc8270 provide the direct IDE interface without using the PCMCIA controller? If it can, what's the different with the
drivers\ide\ppc\mpc8xx.c ? Can you provide some resource about the "direct IDE interface " on MPC82xx ?
My PCMCIA CF card has a specially CPLD to read/write the status of the CF card. What's the codes need to be modified if using
the Card Services package? What's the performance between the direct IDE mode and card service?
thanks a lot!
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^ permalink raw reply
* Re: can we kill CONFIG_PPC64BRIDGE?
From: Heikki Lindholm @ 2005-09-09 5:54 UTC (permalink / raw)
To: Kumar Gala; +Cc: linuxppc-dev list, ppc64-dev
In-Reply-To: <5AB80D6D-C8B0-4F08-9C06-A56119D5D696@freescale.com>
Kumar Gala kirjoitti:
> Paul,
>
> Can we kill CONFIG_PPC64BRIDGE for ppc32... Not sure if anyone is using
> this or not?
It has been useful when porting stuff over to ppc64. Though, if nobody
will maintain it...
-- Heikki Lindholm
^ permalink raw reply
* [PATCH] powerpc: merge include/asm/cputable.h
From: Arnd Bergmann @ 2005-09-09 4:23 UTC (permalink / raw)
To: linuxppc64-dev; +Cc: linuxppc-dev, pantelis.antoniou, linuxppc-embedded
In-Reply-To: <200509090036.39992.arnd@arndb.de>
This is an updated version of my old patch that creates a more optimized
version of cpu_has_feature(). This version actually combines
asm-ppc/cputable.h and asm-ppc64/cputable.h, which turned out to be
a lot more work than only the 64 bit version.
The 64 bit parts a relatively straightforward port of my earlier work
which I tested in a number of configurations. The 32 bit parts are
not tested at all, all I did was compiling the ppc defconfig with this.
I think it is best if I hand the patch over to Kumar and Becky for
further testing and cleaning up the remaining bits in the new
file, as they appear to have invested some thought in it already.
This version still has a number of #ifdef __powerpc64__ that should
probably go away in the process.
The patch also relies on having the ASM_CONST() macro in ppc_asm.h,
as proposed by Kumar Gala, so it won't work on the current git
head without that change.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
--
clean-cg/arch/ppc/kernel/cputable.c | 401 +++++----------------------
clean-cg/arch/ppc64/Kconfig | 30 ++
clean-cg/arch/ppc64/kernel/cputable.c | 82 +----
clean-cg/include/asm-powerpc/cputable.h | 475 ++++++++++++++++++++++++++++++++
include/asm-ppc/cputable.h | 128 --------
include/asm-ppc64/cputable.h | 167 -----------
Index: clean-cg/include/asm-ppc64/cputable.h
===================================================================
--- clean-cg.orig/include/asm-ppc64/cputable.h
+++ /dev/null
@@ -1,167 +0,0 @@
-/*
- * include/asm-ppc64/cputable.h
- *
- * Copyright (C) 2001 Ben. Herrenschmidt (benh@kernel.crashing.org)
- *
- * Modifications for ppc64:
- * Copyright (C) 2003 Dave Engebretsen <engebret@us.ibm.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef __ASM_PPC_CPUTABLE_H
-#define __ASM_PPC_CPUTABLE_H
-
-#include <linux/config.h>
-#include <asm/page.h> /* for ASM_CONST */
-
-/* Exposed to userland CPU features - Must match ppc32 definitions */
-#define PPC_FEATURE_32 0x80000000
-#define PPC_FEATURE_64 0x40000000
-#define PPC_FEATURE_601_INSTR 0x20000000
-#define PPC_FEATURE_HAS_ALTIVEC 0x10000000
-#define PPC_FEATURE_HAS_FPU 0x08000000
-#define PPC_FEATURE_HAS_MMU 0x04000000
-#define PPC_FEATURE_HAS_4xxMAC 0x02000000
-#define PPC_FEATURE_UNIFIED_CACHE 0x01000000
-
-#ifdef __KERNEL__
-
-#ifndef __ASSEMBLY__
-
-/* This structure can grow, it's real size is used by head.S code
- * via the mkdefs mechanism.
- */
-struct cpu_spec;
-struct op_ppc64_model;
-
-typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec);
-
-struct cpu_spec {
- /* CPU is matched via (PVR & pvr_mask) == pvr_value */
- unsigned int pvr_mask;
- unsigned int pvr_value;
-
- char *cpu_name;
- unsigned long cpu_features; /* Kernel features */
- unsigned int cpu_user_features; /* Userland features */
-
- /* cache line sizes */
- unsigned int icache_bsize;
- unsigned int dcache_bsize;
-
- /* number of performance monitor counters */
- unsigned int num_pmcs;
-
- /* this is called to initialize various CPU bits like L1 cache,
- * BHT, SPD, etc... from head.S before branching to identify_machine
- */
- cpu_setup_t cpu_setup;
-
- /* Used by oprofile userspace to select the right counters */
- char *oprofile_cpu_type;
-
- /* Processor specific oprofile operations */
- struct op_ppc64_model *oprofile_model;
-};
-
-extern struct cpu_spec cpu_specs[];
-extern struct cpu_spec *cur_cpu_spec;
-
-static inline unsigned long cpu_has_feature(unsigned long feature)
-{
- return cur_cpu_spec->cpu_features & feature;
-}
-
-#endif /* __ASSEMBLY__ */
-
-/* CPU kernel features */
-
-/* Retain the 32b definitions for the time being - use bottom half of word */
-#define CPU_FTR_SPLIT_ID_CACHE ASM_CONST(0x0000000000000001)
-#define CPU_FTR_L2CR ASM_CONST(0x0000000000000002)
-#define CPU_FTR_SPEC7450 ASM_CONST(0x0000000000000004)
-#define CPU_FTR_ALTIVEC ASM_CONST(0x0000000000000008)
-#define CPU_FTR_TAU ASM_CONST(0x0000000000000010)
-#define CPU_FTR_CAN_DOZE ASM_CONST(0x0000000000000020)
-#define CPU_FTR_USE_TB ASM_CONST(0x0000000000000040)
-#define CPU_FTR_604_PERF_MON ASM_CONST(0x0000000000000080)
-#define CPU_FTR_601 ASM_CONST(0x0000000000000100)
-#define CPU_FTR_HPTE_TABLE ASM_CONST(0x0000000000000200)
-#define CPU_FTR_CAN_NAP ASM_CONST(0x0000000000000400)
-#define CPU_FTR_L3CR ASM_CONST(0x0000000000000800)
-#define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x0000000000001000)
-#define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x0000000000002000)
-#define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x0000000000004000)
-
-/* Add the 64b processor unique features in the top half of the word */
-#define CPU_FTR_SLB ASM_CONST(0x0000000100000000)
-#define CPU_FTR_16M_PAGE ASM_CONST(0x0000000200000000)
-#define CPU_FTR_TLBIEL ASM_CONST(0x0000000400000000)
-#define CPU_FTR_NOEXECUTE ASM_CONST(0x0000000800000000)
-#define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000001000000000)
-#define CPU_FTR_IABR ASM_CONST(0x0000002000000000)
-#define CPU_FTR_MMCRA ASM_CONST(0x0000004000000000)
-/* unused ASM_CONST(0x0000008000000000) */
-#define CPU_FTR_SMT ASM_CONST(0x0000010000000000)
-#define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x0000020000000000)
-#define CPU_FTR_LOCKLESS_TLBIE ASM_CONST(0x0000040000000000)
-#define CPU_FTR_MMCRA_SIHV ASM_CONST(0x0000080000000000)
-#define CPU_FTR_CTRL ASM_CONST(0x0000100000000000)
-
-#ifndef __ASSEMBLY__
-
-#define COMMON_USER_PPC64 (PPC_FEATURE_32 | PPC_FEATURE_64 | \
- PPC_FEATURE_HAS_FPU | PPC_FEATURE_HAS_MMU)
-
-#define CPU_FTR_PPCAS_ARCH_V2_BASE (CPU_FTR_SLB | \
- CPU_FTR_TLBIEL | CPU_FTR_NOEXECUTE | \
- CPU_FTR_NODSISRALIGN | CPU_FTR_CTRL)
-
-/* iSeries doesn't support large pages */
-#ifdef CONFIG_PPC_ISERIES
-#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_PPCAS_ARCH_V2_BASE)
-#else
-#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_PPCAS_ARCH_V2_BASE | CPU_FTR_16M_PAGE)
-#endif /* CONFIG_PPC_ISERIES */
-
-#endif /* __ASSEMBLY */
-
-#ifdef __ASSEMBLY__
-
-#define BEGIN_FTR_SECTION 98:
-
-#define END_FTR_SECTION(msk, val) \
-99: \
- .section __ftr_fixup,"a"; \
- .align 3; \
- .llong msk; \
- .llong val; \
- .llong 98b; \
- .llong 99b; \
- .previous
-
-#else
-
-#define BEGIN_FTR_SECTION "98:\n"
-#define END_FTR_SECTION(msk, val) \
-"99:\n" \
-" .section __ftr_fixup,\"a\";\n" \
-" .align 3;\n" \
-" .llong "#msk";\n" \
-" .llong "#val";\n" \
-" .llong 98b;\n" \
-" .llong 99b;\n" \
-" .previous\n"
-
-#endif /* __ASSEMBLY__ */
-
-#define END_FTR_SECTION_IFSET(msk) END_FTR_SECTION((msk), (msk))
-#define END_FTR_SECTION_IFCLR(msk) END_FTR_SECTION((msk), 0)
-
-#endif /* __ASM_PPC_CPUTABLE_H */
-#endif /* __KERNEL__ */
-
Index: clean-cg/arch/ppc64/Kconfig
===================================================================
--- clean-cg.orig/arch/ppc64/Kconfig
+++ clean-cg/arch/ppc64/Kconfig
@@ -125,6 +125,36 @@ config BPA_IIC
bool
default y
+config CPU_POWER3
+ bool
+ default y
+ depends on (PPC_ISERIES || PPC_PSERIES) && !POWER4_ONLY
+
+config CPU_RS64
+ bool
+ default y
+ depends on (PPC_ISERIES || PPC_PSERIES) && !POWER4_ONLY
+
+config CPU_POWER4
+ bool
+ default y
+ depends on PPC_ISERIES || PPC_PSERIES
+
+config CPU_PPC970
+ bool
+ default y
+ depends on PPC_PSERIES || PPC_PMAC || PPC_MAPLE
+
+config CPU_POWER5
+ bool
+ default y
+ depends on PPC_PSERIES
+
+config CPU_CELL
+ bool
+ default y
+ depends on PPC_BPA
+
# VMX is pSeries only for now until somebody writes the iSeries
# exception vectors for it
config ALTIVEC
Index: clean-cg/arch/ppc64/kernel/cputable.c
===================================================================
--- clean-cg.orig/arch/ppc64/kernel/cputable.c
+++ clean-cg/arch/ppc64/kernel/cputable.c
@@ -37,26 +37,13 @@ extern void __setup_cpu_power4(unsigned
extern void __setup_cpu_ppc970(unsigned long offset, struct cpu_spec* spec);
extern void __setup_cpu_be(unsigned long offset, struct cpu_spec* spec);
-
-/* We only set the altivec features if the kernel was compiled with altivec
- * support
- */
-#ifdef CONFIG_ALTIVEC
-#define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC
-#define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
-#else
-#define CPU_FTR_ALTIVEC_COMP 0
-#define PPC_FEATURE_HAS_ALTIVEC_COMP 0
-#endif
-
struct cpu_spec cpu_specs[] = {
{ /* Power3 */
.pvr_mask = 0xffff0000,
.pvr_value = 0x00400000,
.cpu_name = "POWER3 (630)",
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
- CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR,
- .cpu_user_features = COMMON_USER_PPC64,
+ .cpu_features = CPU_FTR_POWER3,
+ .cpu_user_features = COMMON_USER_PPC64,
.icache_bsize = 128,
.dcache_bsize = 128,
.num_pmcs = 8,
@@ -70,8 +57,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffff0000,
.pvr_value = 0x00410000,
.cpu_name = "POWER3 (630+)",
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
- CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR,
+ .cpu_features = CPU_FTR_POWER3,
.cpu_user_features = COMMON_USER_PPC64,
.icache_bsize = 128,
.dcache_bsize = 128,
@@ -86,9 +72,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffff0000,
.pvr_value = 0x00330000,
.cpu_name = "RS64-II (northstar)",
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
- CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
- CPU_FTR_MMCRA | CPU_FTR_CTRL,
+ .cpu_features = CPU_FTR_RS64,
.cpu_user_features = COMMON_USER_PPC64,
.icache_bsize = 128,
.dcache_bsize = 128,
@@ -103,9 +87,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffff0000,
.pvr_value = 0x00340000,
.cpu_name = "RS64-III (pulsar)",
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
- CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
- CPU_FTR_MMCRA | CPU_FTR_CTRL,
+ .cpu_features = CPU_FTR_RS64,
.cpu_user_features = COMMON_USER_PPC64,
.icache_bsize = 128,
.dcache_bsize = 128,
@@ -120,9 +102,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffff0000,
.pvr_value = 0x00360000,
.cpu_name = "RS64-III (icestar)",
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
- CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
- CPU_FTR_MMCRA | CPU_FTR_CTRL,
+ .cpu_features = CPU_FTR_RS64,
.cpu_user_features = COMMON_USER_PPC64,
.icache_bsize = 128,
.dcache_bsize = 128,
@@ -137,9 +117,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffff0000,
.pvr_value = 0x00370000,
.cpu_name = "RS64-IV (sstar)",
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
- CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
- CPU_FTR_MMCRA | CPU_FTR_CTRL,
+ .cpu_features = CPU_FTR_RS64,
.cpu_user_features = COMMON_USER_PPC64,
.icache_bsize = 128,
.dcache_bsize = 128,
@@ -154,9 +132,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffff0000,
.pvr_value = 0x00350000,
.cpu_name = "POWER4 (gp)",
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
- CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
- CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_MMCRA,
+ .cpu_features = CPU_FTR_POWER4,
.cpu_user_features = COMMON_USER_PPC64,
.icache_bsize = 128,
.dcache_bsize = 128,
@@ -171,9 +147,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffff0000,
.pvr_value = 0x00380000,
.cpu_name = "POWER4+ (gq)",
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
- CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
- CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_MMCRA,
+ .cpu_features = CPU_FTR_POWER4,
.cpu_user_features = COMMON_USER_PPC64,
.icache_bsize = 128,
.dcache_bsize = 128,
@@ -188,10 +162,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffff0000,
.pvr_value = 0x00390000,
.cpu_name = "PPC970",
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
- CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
- CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP |
- CPU_FTR_CAN_NAP | CPU_FTR_MMCRA,
+ .cpu_features = CPU_FTR_PPC970,
.cpu_user_features = COMMON_USER_PPC64 |
PPC_FEATURE_HAS_ALTIVEC_COMP,
.icache_bsize = 128,
@@ -207,10 +178,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffff0000,
.pvr_value = 0x003c0000,
.cpu_name = "PPC970FX",
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
- CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
- CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP |
- CPU_FTR_CAN_NAP | CPU_FTR_MMCRA,
+ .cpu_features = CPU_FTR_PPC970,
.cpu_user_features = COMMON_USER_PPC64 |
PPC_FEATURE_HAS_ALTIVEC_COMP,
.icache_bsize = 128,
@@ -226,10 +194,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffff0000,
.pvr_value = 0x00440000,
.cpu_name = "PPC970MP",
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
- CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
- CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP |
- CPU_FTR_CAN_NAP | CPU_FTR_MMCRA,
+ .cpu_features = CPU_FTR_PPC970,
.cpu_user_features = COMMON_USER_PPC64 |
PPC_FEATURE_HAS_ALTIVEC_COMP,
.icache_bsize = 128,
@@ -244,11 +209,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffff0000,
.pvr_value = 0x003a0000,
.cpu_name = "POWER5 (gr)",
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
- CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
- CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_MMCRA | CPU_FTR_SMT |
- CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE |
- CPU_FTR_MMCRA_SIHV,
+ .cpu_features = CPU_FTR_POWER5,
.cpu_user_features = COMMON_USER_PPC64,
.icache_bsize = 128,
.dcache_bsize = 128,
@@ -263,11 +224,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffff0000,
.pvr_value = 0x003b0000,
.cpu_name = "POWER5 (gs)",
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
- CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
- CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_MMCRA | CPU_FTR_SMT |
- CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE |
- CPU_FTR_MMCRA_SIHV,
+ .cpu_features = CPU_FTR_POWER5,
.cpu_user_features = COMMON_USER_PPC64,
.icache_bsize = 128,
.dcache_bsize = 128,
@@ -281,11 +238,8 @@ struct cpu_spec cpu_specs[] = {
{ /* BE DD1.x */
.pvr_mask = 0xffff0000,
.pvr_value = 0x00700000,
- .cpu_name = "Broadband Engine",
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
- CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
- CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP |
- CPU_FTR_SMT,
+ .cpu_name = "Cell Broadband Engine",
+ .cpu_features = CPU_FTR_CELL,
.cpu_user_features = COMMON_USER_PPC64 |
PPC_FEATURE_HAS_ALTIVEC_COMP,
.icache_bsize = 128,
@@ -296,9 +250,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0x00000000,
.pvr_value = 0x00000000,
.cpu_name = "POWER4 (compatible)",
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
- CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
- CPU_FTR_PPCAS_ARCH_V2,
+ .cpu_features = CPU_FTR_COMPATIBLE,
.cpu_user_features = COMMON_USER_PPC64,
.icache_bsize = 128,
.dcache_bsize = 128,
Index: clean-cg/arch/ppc/kernel/cputable.c
===================================================================
--- clean-cg.orig/arch/ppc/kernel/cputable.c
+++ clean-cg/arch/ppc/kernel/cputable.c
@@ -42,17 +42,6 @@ extern void __setup_cpu_generic(unsigned
#define COMMON_PPC (PPC_FEATURE_32 | PPC_FEATURE_HAS_FPU | \
PPC_FEATURE_HAS_MMU)
-/* We only set the altivec features if the kernel was compiled with altivec
- * support
- */
-#ifdef CONFIG_ALTIVEC
-#define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC
-#define PPC_FEATURE_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
-#else
-#define CPU_FTR_ALTIVEC_COMP 0
-#define PPC_FEATURE_ALTIVEC_COMP 0
-#endif
-
/* We only set the spe features if the kernel was compiled with
* spe support
*/
@@ -62,34 +51,13 @@ extern void __setup_cpu_generic(unsigned
#define PPC_FEATURE_SPE_COMP 0
#endif
-/* We need to mark all pages as being coherent if we're SMP or we
- * have a 74[45]x and an MPC107 host bridge.
- */
-#if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE)
-#define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT
-#else
-#define CPU_FTR_COMMON 0
-#endif
-
-/* The powersave features NAP & DOZE seems to confuse BDI when
- debugging. So if a BDI is used, disable theses
- */
-#ifndef CONFIG_BDI_SWITCH
-#define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE
-#define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP
-#else
-#define CPU_FTR_MAYBE_CAN_DOZE 0
-#define CPU_FTR_MAYBE_CAN_NAP 0
-#endif
-
struct cpu_spec cpu_specs[] = {
#if CLASSIC_PPC
{ /* 601 */
.pvr_mask = 0xffff0000,
.pvr_value = 0x00010000,
.cpu_name = "601",
- .cpu_features = CPU_FTR_COMMON | CPU_FTR_601 |
- CPU_FTR_HPTE_TABLE,
+ .cpu_features = CPU_FTR_PPC601,
.cpu_user_features = COMMON_PPC | PPC_FEATURE_601_INSTR |
PPC_FEATURE_UNIFIED_CACHE,
.icache_bsize = 32,
@@ -100,9 +68,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffff0000,
.pvr_value = 0x00030000,
.cpu_name = "603",
- .cpu_features = CPU_FTR_COMMON |
- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
- CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP,
+ .cpu_features = CPU_FTR_603,
.cpu_user_features = COMMON_PPC,
.icache_bsize = 32,
.dcache_bsize = 32,
@@ -112,9 +78,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffff0000,
.pvr_value = 0x00060000,
.cpu_name = "603e",
- .cpu_features = CPU_FTR_COMMON |
- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
- CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP,
+ .cpu_features = CPU_FTR_603,
.cpu_user_features = COMMON_PPC,
.icache_bsize = 32,
.dcache_bsize = 32,
@@ -124,9 +88,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffff0000,
.pvr_value = 0x00070000,
.cpu_name = "603ev",
- .cpu_features = CPU_FTR_COMMON |
- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
- CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP,
+ .cpu_features = CPU_FTR_603,
.cpu_user_features = COMMON_PPC,
.icache_bsize = 32,
.dcache_bsize = 32,
@@ -136,9 +98,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffff0000,
.pvr_value = 0x00040000,
.cpu_name = "604",
- .cpu_features = CPU_FTR_COMMON |
- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
- CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE,
+ .cpu_features = CPU_FTR_604,
.cpu_user_features = COMMON_PPC,
.icache_bsize = 32,
.dcache_bsize = 32,
@@ -149,9 +109,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xfffff000,
.pvr_value = 0x00090000,
.cpu_name = "604e",
- .cpu_features = CPU_FTR_COMMON |
- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
- CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE,
+ .cpu_features = CPU_FTR_604,
.cpu_user_features = COMMON_PPC,
.icache_bsize = 32,
.dcache_bsize = 32,
@@ -162,9 +120,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffff0000,
.pvr_value = 0x00090000,
.cpu_name = "604r",
- .cpu_features = CPU_FTR_COMMON |
- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
- CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE,
+ .cpu_features = CPU_FTR_604,
.cpu_user_features = COMMON_PPC,
.icache_bsize = 32,
.dcache_bsize = 32,
@@ -175,9 +131,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffff0000,
.pvr_value = 0x000a0000,
.cpu_name = "604ev",
- .cpu_features = CPU_FTR_COMMON |
- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
- CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE,
+ .cpu_features = CPU_FTR_604,
.cpu_user_features = COMMON_PPC,
.icache_bsize = 32,
.dcache_bsize = 32,
@@ -188,10 +142,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffffffff,
.pvr_value = 0x00084202,
.cpu_name = "740/750",
- .cpu_features = CPU_FTR_COMMON |
- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
- CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_HPTE_TABLE |
- CPU_FTR_MAYBE_CAN_NAP,
+ .cpu_features = CPU_FTR_740_NOTAU,
.cpu_user_features = COMMON_PPC,
.icache_bsize = 32,
.dcache_bsize = 32,
@@ -202,10 +153,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xfffffff0,
.pvr_value = 0x00080100,
.cpu_name = "750CX",
- .cpu_features = CPU_FTR_COMMON |
- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
- CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
- CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
+ .cpu_features = CPU_FTR_750,
.cpu_user_features = COMMON_PPC,
.icache_bsize = 32,
.dcache_bsize = 32,
@@ -216,10 +164,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xfffffff0,
.pvr_value = 0x00082200,
.cpu_name = "750CX",
- .cpu_features = CPU_FTR_COMMON |
- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
- CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
- CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
+ .cpu_features = CPU_FTR_750,
.cpu_user_features = COMMON_PPC,
.icache_bsize = 32,
.dcache_bsize = 32,
@@ -230,10 +175,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xfffffff0,
.pvr_value = 0x00082210,
.cpu_name = "750CXe",
- .cpu_features = CPU_FTR_COMMON |
- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
- CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
- CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
+ .cpu_features = CPU_FTR_750,
.cpu_user_features = COMMON_PPC,
.icache_bsize = 32,
.dcache_bsize = 32,
@@ -244,10 +186,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffffffff,
.pvr_value = 0x00083214,
.cpu_name = "750CXe",
- .cpu_features = CPU_FTR_COMMON |
- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
- CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
- CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
+ .cpu_features = CPU_FTR_750,
.cpu_user_features = COMMON_PPC,
.icache_bsize = 32,
.dcache_bsize = 32,
@@ -258,10 +197,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xfffff000,
.pvr_value = 0x00083000,
.cpu_name = "745/755",
- .cpu_features = CPU_FTR_COMMON |
- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
- CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
- CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
+ .cpu_features = CPU_FTR_750,
.cpu_user_features = COMMON_PPC,
.icache_bsize = 32,
.dcache_bsize = 32,
@@ -272,11 +208,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffffff00,
.pvr_value = 0x70000100,
.cpu_name = "750FX",
- .cpu_features = CPU_FTR_COMMON |
- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
- CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
- CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
- CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM,
+ .cpu_features = CPU_FTR_750FX1,
.cpu_user_features = COMMON_PPC,
.icache_bsize = 32,
.dcache_bsize = 32,
@@ -287,11 +219,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffffffff,
.pvr_value = 0x70000200,
.cpu_name = "750FX",
- .cpu_features = CPU_FTR_COMMON |
- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
- CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
- CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
- CPU_FTR_NO_DPM,
+ .cpu_features = CPU_FTR_750FX2,
.cpu_user_features = COMMON_PPC,
.icache_bsize = 32,
.dcache_bsize = 32,
@@ -302,11 +230,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffff0000,
.pvr_value = 0x70000000,
.cpu_name = "750FX",
- .cpu_features = CPU_FTR_COMMON |
- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
- CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
- CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
- CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS,
+ .cpu_features = CPU_FTR_750FX,
.cpu_user_features = COMMON_PPC,
.icache_bsize = 32,
.dcache_bsize = 32,
@@ -317,11 +241,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffff0000,
.pvr_value = 0x70020000,
.cpu_name = "750GX",
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
- CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
- CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE |
- CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_DUAL_PLL_750FX |
- CPU_FTR_HAS_HIGH_BATS,
+ .cpu_features = CPU_FTR_750GX,
.cpu_user_features = COMMON_PPC,
.icache_bsize = 32,
.dcache_bsize = 32,
@@ -332,10 +252,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffff0000,
.pvr_value = 0x00080000,
.cpu_name = "740/750",
- .cpu_features = CPU_FTR_COMMON |
- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
- CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
- CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
+ .cpu_features = CPU_FTR_740,
.cpu_user_features = COMMON_PPC,
.icache_bsize = 32,
.dcache_bsize = 32,
@@ -346,11 +263,8 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffffffff,
.pvr_value = 0x000c1101,
.cpu_name = "7400 (1.1)",
- .cpu_features = CPU_FTR_COMMON |
- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
- CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
- CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
- .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
+ .cpu_features = CPU_FTR_7400_NOTAU,
+ .cpu_user_features = COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC_COMP,
.icache_bsize = 32,
.dcache_bsize = 32,
.num_pmcs = 4,
@@ -360,12 +274,8 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffff0000,
.pvr_value = 0x000c0000,
.cpu_name = "7400",
- .cpu_features = CPU_FTR_COMMON |
- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
- CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
- CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
- CPU_FTR_MAYBE_CAN_NAP,
- .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
+ .cpu_features = CPU_FTR_7400,
+ .cpu_user_features = COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC_COMP,
.icache_bsize = 32,
.dcache_bsize = 32,
.num_pmcs = 4,
@@ -375,12 +285,8 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffff0000,
.pvr_value = 0x800c0000,
.cpu_name = "7410",
- .cpu_features = CPU_FTR_COMMON |
- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
- CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
- CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
- CPU_FTR_MAYBE_CAN_NAP,
- .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
+ .cpu_features = CPU_FTR_7400,
+ .cpu_user_features = COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC_COMP,
.icache_bsize = 32,
.dcache_bsize = 32,
.num_pmcs = 4,
@@ -390,12 +296,8 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffffffff,
.pvr_value = 0x80000200,
.cpu_name = "7450",
- .cpu_features = CPU_FTR_COMMON |
- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
- CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
- CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
- CPU_FTR_NEED_COHERENT,
- .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
+ .cpu_features = CPU_FTR_7450_20,
+ .cpu_user_features = COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC_COMP,
.icache_bsize = 32,
.dcache_bsize = 32,
.num_pmcs = 6,
@@ -405,14 +307,8 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffffffff,
.pvr_value = 0x80000201,
.cpu_name = "7450",
- .cpu_features = CPU_FTR_COMMON |
- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
- CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
- CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
- CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
- CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP |
- CPU_FTR_NEED_COHERENT,
- .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
+ .cpu_features = CPU_FTR_7450_21,
+ .cpu_user_features = COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC_COMP,
.icache_bsize = 32,
.dcache_bsize = 32,
.num_pmcs = 6,
@@ -422,13 +318,8 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffff0000,
.pvr_value = 0x80000000,
.cpu_name = "7450",
- .cpu_features = CPU_FTR_COMMON |
- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
- CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
- CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
- CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
- CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT,
- .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
+ .cpu_features = CPU_FTR_7450_23,
+ .cpu_user_features = COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC_COMP,
.icache_bsize = 32,
.dcache_bsize = 32,
.num_pmcs = 6,
@@ -438,12 +329,8 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffffff00,
.pvr_value = 0x80010100,
.cpu_name = "7455",
- .cpu_features = CPU_FTR_COMMON |
- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
- CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
- CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
- CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT,
- .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
+ .cpu_features = CPU_FTR_7455_1,
+ .cpu_user_features = COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC_COMP,
.icache_bsize = 32,
.dcache_bsize = 32,
.num_pmcs = 6,
@@ -453,14 +340,8 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffffffff,
.pvr_value = 0x80010200,
.cpu_name = "7455",
- .cpu_features = CPU_FTR_COMMON |
- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
- CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
- CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
- CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
- CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP |
- CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS,
- .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
+ .cpu_features = CPU_FTR_7455_20,
+ .cpu_user_features = COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC_COMP,
.icache_bsize = 32,
.dcache_bsize = 32,
.num_pmcs = 6,
@@ -470,14 +351,8 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffff0000,
.pvr_value = 0x80010000,
.cpu_name = "7455",
- .cpu_features = CPU_FTR_COMMON |
- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
- CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
- CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
- CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
- CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
- CPU_FTR_NEED_COHERENT,
- .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
+ .cpu_features = CPU_FTR_7455,
+ .cpu_user_features = COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC_COMP,
.icache_bsize = 32,
.dcache_bsize = 32,
.num_pmcs = 6,
@@ -487,14 +362,8 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffffffff,
.pvr_value = 0x80020100,
.cpu_name = "7447/7457",
- .cpu_features = CPU_FTR_COMMON |
- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
- CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
- CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
- CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
- CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
- CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC,
- .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
+ .cpu_features = CPU_FTR_7447_10,
+ .cpu_user_features = COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC_COMP,
.icache_bsize = 32,
.dcache_bsize = 32,
.num_pmcs = 6,
@@ -504,14 +373,8 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffffffff,
.pvr_value = 0x80020101,
.cpu_name = "7447/7457",
- .cpu_features = CPU_FTR_COMMON |
- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
- CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
- CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
- CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
- CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
- CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC,
- .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
+ .cpu_features = CPU_FTR_7447_10,
+ .cpu_user_features = COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC_COMP,
.icache_bsize = 32,
.dcache_bsize = 32,
.num_pmcs = 6,
@@ -521,14 +384,8 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffff0000,
.pvr_value = 0x80020000,
.cpu_name = "7447/7457",
- .cpu_features = CPU_FTR_COMMON |
- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
- CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
- CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
- CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
- CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
- CPU_FTR_NEED_COHERENT,
- .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
+ .cpu_features = CPU_FTR_7447,
+ .cpu_user_features = COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC_COMP,
.icache_bsize = 32,
.dcache_bsize = 32,
.num_pmcs = 6,
@@ -538,13 +395,8 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffff0000,
.pvr_value = 0x80030000,
.cpu_name = "7447A",
- .cpu_features = CPU_FTR_COMMON |
- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
- CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
- CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
- CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
- CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT,
- .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
+ .cpu_features = CPU_FTR_7447A,
+ .cpu_user_features = COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC_COMP,
.icache_bsize = 32,
.dcache_bsize = 32,
.num_pmcs = 6,
@@ -554,13 +406,8 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffff0000,
.pvr_value = 0x80040000,
.cpu_name = "7448",
- .cpu_features = CPU_FTR_COMMON |
- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
- CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
- CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
- CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
- CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT,
- .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
+ .cpu_features = CPU_FTR_7447A,
+ .cpu_user_features = COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC_COMP,
.icache_bsize = 32,
.dcache_bsize = 32,
.num_pmcs = 6,
@@ -570,9 +417,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0x7fff0000,
.pvr_value = 0x00810000,
.cpu_name = "82xx",
- .cpu_features = CPU_FTR_COMMON |
- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
- CPU_FTR_USE_TB,
+ .cpu_features = CPU_FTR_82XX,
.cpu_user_features = COMMON_PPC,
.icache_bsize = 32,
.dcache_bsize = 32,
@@ -582,9 +427,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0x7fff0000,
.pvr_value = 0x00820000,
.cpu_name = "G2_LE",
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
- CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
- CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS,
+ .cpu_features = CPU_FTR_G2_LE,
.cpu_user_features = COMMON_PPC,
.icache_bsize = 32,
.dcache_bsize = 32,
@@ -594,9 +437,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0x7fff0000,
.pvr_value = 0x00830000,
.cpu_name = "e300",
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
- CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
- CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS,
+ .cpu_features = CPU_FTR_E300,
.cpu_user_features = COMMON_PPC,
.icache_bsize = 32,
.dcache_bsize = 32,
@@ -606,9 +447,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0x00000000,
.pvr_value = 0x00000000,
.cpu_name = "(generic PPC)",
- .cpu_features = CPU_FTR_COMMON |
- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
- CPU_FTR_HPTE_TABLE,
+ .cpu_features = CPU_FTR_CLASSIC32,
.cpu_user_features = COMMON_PPC,
.icache_bsize = 32,
.dcache_bsize = 32,
@@ -620,9 +459,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffff0000,
.pvr_value = 0x00400000,
.cpu_name = "Power3 (630)",
- .cpu_features = CPU_FTR_COMMON |
- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
- CPU_FTR_HPTE_TABLE,
+ .cpu_features = CPU_FTR_POWER3_32,
.cpu_user_features = COMMON_PPC | PPC_FEATURE_64,
.icache_bsize = 128,
.dcache_bsize = 128,
@@ -633,9 +470,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffff0000,
.pvr_value = 0x00410000,
.cpu_name = "Power3 (630+)",
- .cpu_features = CPU_FTR_COMMON |
- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
- CPU_FTR_HPTE_TABLE,
+ .cpu_features = CPU_FTR_POWER3_32,
.cpu_user_features = COMMON_PPC | PPC_FEATURE_64,
.icache_bsize = 128,
.dcache_bsize = 128,
@@ -646,9 +481,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffff0000,
.pvr_value = 0x00360000,
.cpu_name = "I-star",
- .cpu_features = CPU_FTR_COMMON |
- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
- CPU_FTR_HPTE_TABLE,
+ .cpu_features = CPU_FTR_POWER3_32,
.cpu_user_features = COMMON_PPC | PPC_FEATURE_64,
.icache_bsize = 128,
.dcache_bsize = 128,
@@ -659,55 +492,19 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffff0000,
.pvr_value = 0x00370000,
.cpu_name = "S-star",
- .cpu_features = CPU_FTR_COMMON |
- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
- CPU_FTR_HPTE_TABLE,
+ .cpu_features = CPU_FTR_POWER3_32,
.cpu_user_features = COMMON_PPC | PPC_FEATURE_64,
.icache_bsize = 128,
.dcache_bsize = 128,
.num_pmcs = 8,
.cpu_setup = __setup_cpu_power3
},
-#endif /* CONFIG_PPC64BRIDGE */
-#ifdef CONFIG_POWER4
- { /* Power4 */
- .pvr_mask = 0xffff0000,
- .pvr_value = 0x00350000,
- .cpu_name = "Power4",
- .cpu_features = CPU_FTR_COMMON |
- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
- CPU_FTR_HPTE_TABLE,
- .cpu_user_features = COMMON_PPC | PPC_FEATURE_64,
- .icache_bsize = 128,
- .dcache_bsize = 128,
- .num_pmcs = 8,
- .cpu_setup = __setup_cpu_power4
- },
- { /* PPC970 */
- .pvr_mask = 0xffff0000,
- .pvr_value = 0x00390000,
- .cpu_name = "PPC970",
- .cpu_features = CPU_FTR_COMMON |
- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
- CPU_FTR_HPTE_TABLE |
- CPU_FTR_ALTIVEC_COMP | CPU_FTR_MAYBE_CAN_NAP,
- .cpu_user_features = COMMON_PPC | PPC_FEATURE_64 |
- PPC_FEATURE_ALTIVEC_COMP,
- .icache_bsize = 128,
- .dcache_bsize = 128,
- .num_pmcs = 8,
- .cpu_setup = __setup_cpu_ppc970
- },
{ /* PPC970FX */
.pvr_mask = 0xffff0000,
.pvr_value = 0x003c0000,
.cpu_name = "PPC970FX",
- .cpu_features = CPU_FTR_COMMON |
- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
- CPU_FTR_HPTE_TABLE |
- CPU_FTR_ALTIVEC_COMP | CPU_FTR_MAYBE_CAN_NAP,
- .cpu_user_features = COMMON_PPC | PPC_FEATURE_64 |
- PPC_FEATURE_ALTIVEC_COMP,
+ .cpu_features = CPU_FTR_970_32,
+ .cpu_user_features = COMMON_PPC | PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC_COMP,
.icache_bsize = 128,
.dcache_bsize = 128,
.num_pmcs = 8,
@@ -721,8 +518,7 @@ struct cpu_spec cpu_specs[] = {
.cpu_name = "8xx",
/* CPU_FTR_MAYBE_CAN_DOZE is possible,
* if the 8xx code is there.... */
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
- CPU_FTR_USE_TB,
+ .cpu_features = CPU_FTR_8XX,
.cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
.icache_bsize = 16,
.dcache_bsize = 16,
@@ -733,8 +529,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffffff00,
.pvr_value = 0x00200200,
.cpu_name = "403GC",
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
- CPU_FTR_USE_TB,
+ .cpu_features = CPU_FTR_40X,
.cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
.icache_bsize = 16,
.dcache_bsize = 16,
@@ -743,8 +538,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffffff00,
.pvr_value = 0x00201400,
.cpu_name = "403GCX",
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
- CPU_FTR_USE_TB,
+ .cpu_features = CPU_FTR_40X,
.cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
.icache_bsize = 16,
.dcache_bsize = 16,
@@ -753,8 +547,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffff0000,
.pvr_value = 0x00200000,
.cpu_name = "403G ??",
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
- CPU_FTR_USE_TB,
+ .cpu_features = CPU_FTR_40X,
.cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
.icache_bsize = 16,
.dcache_bsize = 16,
@@ -763,8 +556,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffff0000,
.pvr_value = 0x40110000,
.cpu_name = "405GP",
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
- CPU_FTR_USE_TB,
+ .cpu_features = CPU_FTR_40X,
.cpu_user_features = PPC_FEATURE_32 |
PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
.icache_bsize = 32,
@@ -774,8 +566,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffff0000,
.pvr_value = 0x40130000,
.cpu_name = "STB03xxx",
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
- CPU_FTR_USE_TB,
+ .cpu_features = CPU_FTR_40X,
.cpu_user_features = PPC_FEATURE_32 |
PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
.icache_bsize = 32,
@@ -785,8 +576,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffff0000,
.pvr_value = 0x41810000,
.cpu_name = "STB04xxx",
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
- CPU_FTR_USE_TB,
+ .cpu_features = CPU_FTR_40X,
.cpu_user_features = PPC_FEATURE_32 |
PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
.icache_bsize = 32,
@@ -796,8 +586,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffff0000,
.pvr_value = 0x41610000,
.cpu_name = "NP405L",
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
- CPU_FTR_USE_TB,
+ .cpu_features = CPU_FTR_40X,
.cpu_user_features = PPC_FEATURE_32 |
PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
.icache_bsize = 32,
@@ -807,8 +596,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffff0000,
.pvr_value = 0x40B10000,
.cpu_name = "NP4GS3",
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
- CPU_FTR_USE_TB,
+ .cpu_features = CPU_FTR_40X,
.cpu_user_features = PPC_FEATURE_32 |
PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
.icache_bsize = 32,
@@ -818,8 +606,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffff0000,
.pvr_value = 0x41410000,
.cpu_name = "NP405H",
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
- CPU_FTR_USE_TB,
+ .cpu_features = CPU_FTR_40X,
.cpu_user_features = PPC_FEATURE_32 |
PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
.icache_bsize = 32,
@@ -829,8 +616,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffff0000,
.pvr_value = 0x50910000,
.cpu_name = "405GPr",
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
- CPU_FTR_USE_TB,
+ .cpu_features = CPU_FTR_40X,
.cpu_user_features = PPC_FEATURE_32 |
PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
.icache_bsize = 32,
@@ -840,8 +626,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffff0000,
.pvr_value = 0x51510000,
.cpu_name = "STBx25xx",
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
- CPU_FTR_USE_TB,
+ .cpu_features = CPU_FTR_40X,
.cpu_user_features = PPC_FEATURE_32 |
PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
.icache_bsize = 32,
@@ -851,8 +636,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffff0000,
.pvr_value = 0x41F10000,
.cpu_name = "405LP",
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
- CPU_FTR_USE_TB,
+ .cpu_features = CPU_FTR_40X,
.cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
.icache_bsize = 32,
.dcache_bsize = 32,
@@ -861,8 +645,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffff0000,
.pvr_value = 0x20010000,
.cpu_name = "Virtex-II Pro",
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
- CPU_FTR_USE_TB,
+ .cpu_features = CPU_FTR_40X,
.cpu_user_features = PPC_FEATURE_32 |
PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
.icache_bsize = 32,
@@ -872,8 +655,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xffff0000,
.pvr_value = 0x51210000,
.cpu_name = "405EP",
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
- CPU_FTR_USE_TB,
+ .cpu_features = CPU_FTR_40X,
.cpu_user_features = PPC_FEATURE_32 |
PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
.icache_bsize = 32,
@@ -886,8 +668,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xf0000fff,
.pvr_value = 0x40000850,
.cpu_name = "440EP Rev. A",
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
- CPU_FTR_USE_TB,
+ .cpu_features = CPU_FTR_44X,
.cpu_user_features = COMMON_PPC, /* 440EP has an FPU */
.icache_bsize = 32,
.dcache_bsize = 32,
@@ -896,8 +677,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xf0000fff,
.pvr_value = 0x400008d3,
.cpu_name = "440EP Rev. B",
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
- CPU_FTR_USE_TB,
+ .cpu_features = CPU_FTR_44X,
.cpu_user_features = COMMON_PPC, /* 440EP has an FPU */
.icache_bsize = 32,
.dcache_bsize = 32,
@@ -906,8 +686,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xf0000fff,
.pvr_value = 0x40000440,
.cpu_name = "440GP Rev. B",
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
- CPU_FTR_USE_TB,
+ .cpu_features = CPU_FTR_44X,
.cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
.icache_bsize = 32,
.dcache_bsize = 32,
@@ -916,8 +695,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xf0000fff,
.pvr_value = 0x40000481,
.cpu_name = "440GP Rev. C",
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
- CPU_FTR_USE_TB,
+ .cpu_features = CPU_FTR_44X,
.cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
.icache_bsize = 32,
.dcache_bsize = 32,
@@ -926,8 +704,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xf0000fff,
.pvr_value = 0x50000850,
.cpu_name = "440GX Rev. A",
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
- CPU_FTR_USE_TB,
+ .cpu_features = CPU_FTR_44X,
.cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
.icache_bsize = 32,
.dcache_bsize = 32,
@@ -936,8 +713,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xf0000fff,
.pvr_value = 0x50000851,
.cpu_name = "440GX Rev. B",
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
- CPU_FTR_USE_TB,
+ .cpu_features = CPU_FTR_44X,
.cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
.icache_bsize = 32,
.dcache_bsize = 32,
@@ -946,8 +722,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xf0000fff,
.pvr_value = 0x50000892,
.cpu_name = "440GX Rev. C",
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
- CPU_FTR_USE_TB,
+ .cpu_features = CPU_FTR_44X,
.cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
.icache_bsize = 32,
.dcache_bsize = 32,
@@ -956,8 +731,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xf0000fff,
.pvr_value = 0x50000894,
.cpu_name = "440GX Rev. F",
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
- CPU_FTR_USE_TB,
+ .cpu_features = CPU_FTR_44X,
.cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
.icache_bsize = 32,
.dcache_bsize = 32,
@@ -966,8 +740,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0xff000fff,
.pvr_value = 0x53000891,
.cpu_name = "440SP Rev. A",
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
- CPU_FTR_USE_TB,
+ .cpu_features = CPU_FTR_44X,
.cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
.icache_bsize = 32,
.dcache_bsize = 32,
@@ -979,7 +752,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_value = 0x81000000,
.cpu_name = "e200z5",
/* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
- .cpu_features = CPU_FTR_USE_TB,
+ .cpu_features = CPU_FTR_E200,
.cpu_user_features = PPC_FEATURE_32 |
PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_EFP_SINGLE |
PPC_FEATURE_UNIFIED_CACHE,
@@ -990,7 +763,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_value = 0x81100000,
.cpu_name = "e200z6",
/* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
- .cpu_features = CPU_FTR_USE_TB,
+ .cpu_features = CPU_FTR_E200,
.cpu_user_features = PPC_FEATURE_32 |
PPC_FEATURE_HAS_MMU | PPC_FEATURE_SPE_COMP |
PPC_FEATURE_HAS_EFP_SINGLE |
@@ -1002,8 +775,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_value = 0x80200000,
.cpu_name = "e500",
/* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
- CPU_FTR_USE_TB,
+ .cpu_features = CPU_FTR_E500,
.cpu_user_features = PPC_FEATURE_32 |
PPC_FEATURE_HAS_MMU | PPC_FEATURE_SPE_COMP |
PPC_FEATURE_HAS_EFP_SINGLE,
@@ -1016,8 +788,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_value = 0x80210000,
.cpu_name = "e500v2",
/* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
- CPU_FTR_USE_TB | CPU_FTR_BIG_PHYS,
+ .cpu_features = CPU_FTR_E500_2,
.cpu_user_features = PPC_FEATURE_32 |
PPC_FEATURE_HAS_MMU | PPC_FEATURE_SPE_COMP |
PPC_FEATURE_HAS_EFP_SINGLE | PPC_FEATURE_HAS_EFP_DOUBLE,
@@ -1031,7 +802,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_mask = 0x00000000,
.pvr_value = 0x00000000,
.cpu_name = "(generic PPC)",
- .cpu_features = CPU_FTR_COMMON,
+ .cpu_features = CPU_FTR_GENERIC_32,
.cpu_user_features = PPC_FEATURE_32,
.icache_bsize = 32,
.dcache_bsize = 32,
Index: clean-cg/include/asm-powerpc/cputable.h
===================================================================
--- /dev/null
+++ clean-cg/include/asm-powerpc/cputable.h
@@ -0,0 +1,475 @@
+#ifndef __ASM_POWERPC_CPUTABLE_H
+#define __ASM_POWERPC_CPUTABLE_H
+
+#ifdef __KERNEL__
+#include <linux/config.h>
+#include <asm/ppc_asm.h> /* for ASM_CONST */
+
+#define PPC_FEATURE_32 0x80000000
+#define PPC_FEATURE_64 0x40000000
+#define PPC_FEATURE_601_INSTR 0x20000000
+#define PPC_FEATURE_HAS_ALTIVEC 0x10000000
+#define PPC_FEATURE_HAS_FPU 0x08000000
+#define PPC_FEATURE_HAS_MMU 0x04000000
+#define PPC_FEATURE_HAS_4xxMAC 0x02000000
+#define PPC_FEATURE_UNIFIED_CACHE 0x01000000
+#define PPC_FEATURE_HAS_SPE 0x00800000
+#define PPC_FEATURE_HAS_EFP_SINGLE 0x00400000
+#define PPC_FEATURE_HAS_EFP_DOUBLE 0x00200000
+
+#ifndef __ASSEMBLY__
+
+/* This structure can grow, it's real size is used by head.S code
+ * via the mkdefs mechanism.
+ */
+struct cpu_spec;
+struct op_ppc64_model;
+
+#ifndef __powerpc64__
+typedef void (*cpu_setup_t)(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
+#else /* __powerpc64__ */
+typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec);
+#endif /* __powerpc64__ */
+
+struct cpu_spec {
+ /* CPU is matched via (PVR & pvr_mask) == pvr_value */
+ unsigned int pvr_mask;
+ unsigned int pvr_value;
+
+ char *cpu_name;
+ unsigned long cpu_features; /* Kernel features */
+ unsigned int cpu_user_features; /* Userland features */
+
+ /* cache line sizes */
+ unsigned int icache_bsize;
+ unsigned int dcache_bsize;
+
+ /* number of performance monitor counters */
+ unsigned int num_pmcs;
+
+ /* this is called to initialize various CPU bits like L1 cache,
+ * BHT, SPD, etc... from head.S before branching to identify_machine
+ */
+ cpu_setup_t cpu_setup;
+#ifdef __powerpc64__
+
+ /* Used by oprofile userspace to select the right counters */
+ char *oprofile_cpu_type;
+
+ /* Processor specific oprofile operations */
+ struct op_ppc64_model *oprofile_model;
+#endif /* __powerpc64__ */
+};
+
+extern struct cpu_spec cpu_specs[];
+
+#ifndef __powerpc64__
+extern struct cpu_spec *cur_cpu_spec[];
+#else /* __powerpc64__ */
+extern struct cpu_spec *cur_cpu_spec;
+#endif /* __powerpc64__ */
+
+#endif /* __ASSEMBLY__ */
+
+/* CPU kernel features */
+
+/* Retain the 32b definitions all use bottom half of word */
+#define CPU_FTR_SPLIT_ID_CACHE ASM_CONST(0x0000000000000001)
+#define CPU_FTR_L2CR ASM_CONST(0x0000000000000002)
+#define CPU_FTR_SPEC7450 ASM_CONST(0x0000000000000004)
+#define CPU_FTR_ALTIVEC ASM_CONST(0x0000000000000008)
+#define CPU_FTR_TAU ASM_CONST(0x0000000000000010)
+#define CPU_FTR_CAN_DOZE ASM_CONST(0x0000000000000020)
+#define CPU_FTR_USE_TB ASM_CONST(0x0000000000000040)
+#define CPU_FTR_604_PERF_MON ASM_CONST(0x0000000000000080)
+#define CPU_FTR_601 ASM_CONST(0x0000000000000100)
+#define CPU_FTR_HPTE_TABLE ASM_CONST(0x0000000000000200)
+#define CPU_FTR_CAN_NAP ASM_CONST(0x0000000000000400)
+#define CPU_FTR_L3CR ASM_CONST(0x0000000000000800)
+#define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x0000000000001000)
+#define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x0000000000002000)
+#define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x0000000000004000)
+#define CPU_FTR_NO_DPM ASM_CONST(0x0000000000008000)
+#define CPU_FTR_HAS_HIGH_BATS ASM_CONST(0x0000000000010000)
+#define CPU_FTR_NEED_COHERENT ASM_CONST(0x0000000000020000)
+#define CPU_FTR_NO_BTIC ASM_CONST(0x0000000000040000)
+#define CPU_FTR_BIG_PHYS ASM_CONST(0x0000000000080000)
+
+#ifdef __powerpc64__
+/* Add the 64b processor unique features in the top half of the word */
+#define CPU_FTR_SLB ASM_CONST(0x0000000100000000)
+#define CPU_FTR_16M_PAGE ASM_CONST(0x0000000200000000)
+#define CPU_FTR_TLBIEL ASM_CONST(0x0000000400000000)
+#define CPU_FTR_NOEXECUTE ASM_CONST(0x0000000800000000)
+#define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000001000000000)
+#define CPU_FTR_IABR ASM_CONST(0x0000002000000000)
+#define CPU_FTR_MMCRA ASM_CONST(0x0000004000000000)
+/* unused ASM_CONST(0x0000008000000000) */
+#define CPU_FTR_SMT ASM_CONST(0x0000010000000000)
+#define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x0000020000000000)
+#define CPU_FTR_LOCKLESS_TLBIE ASM_CONST(0x0000040000000000)
+#define CPU_FTR_MMCRA_SIHV ASM_CONST(0x0000080000000000)
+#define CPU_FTR_CTRL ASM_CONST(0x0000100000000000)
+#endif
+
+#ifndef __ASSEMBLY__
+
+#define COMMON_USER_PPC64 (PPC_FEATURE_32 | PPC_FEATURE_64 | \
+ PPC_FEATURE_HAS_FPU | PPC_FEATURE_HAS_MMU)
+
+#define CPU_FTR_PPCAS_ARCH_V2_BASE (CPU_FTR_SLB | \
+ CPU_FTR_TLBIEL | CPU_FTR_NOEXECUTE | \
+ CPU_FTR_NODSISRALIGN | CPU_FTR_CTRL)
+
+/* iSeries doesn't support large pages */
+#ifdef CONFIG_PPC_ISERIES
+#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_PPCAS_ARCH_V2_BASE)
+#else
+#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_PPCAS_ARCH_V2_BASE | CPU_FTR_16M_PAGE)
+#endif /* CONFIG_PPC_ISERIES */
+
+/* We only set the altivec features if the kernel was compiled with altivec
+ * support
+ */
+#ifdef CONFIG_ALTIVEC
+#define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC
+#define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
+#else
+#define CPU_FTR_ALTIVEC_COMP 0
+#define PPC_FEATURE_HAS_ALTIVEC_COMP 0
+#endif
+
+/* We need to mark all pages as being coherent if we're SMP or we
+ * have a 74[45]x and an MPC107 host bridge.
+ */
+#if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE)
+#define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT
+#else
+#define CPU_FTR_COMMON 0
+#endif
+
+/* The powersave features NAP & DOZE seems to confuse BDI when
+ debugging. So if a BDI is used, disable theses
+ */
+#ifndef CONFIG_BDI_SWITCH
+#define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE
+#define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP
+#else
+#define CPU_FTR_MAYBE_CAN_DOZE 0
+#define CPU_FTR_MAYBE_CAN_NAP 0
+#endif
+
+#define CLASSIC_PPC (!defined(CONFIG_8xx) && !defined(CONFIG_4xx) && \
+ !defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \
+ !defined(CONFIG_BOOKE))
+
+enum {
+ CPU_FTR_PPC601 = CPU_FTR_COMMON | CPU_FTR_601 | CPU_FTR_HPTE_TABLE,
+ CPU_FTR_603 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+ CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
+ CPU_FTR_MAYBE_CAN_NAP,
+ CPU_FTR_604 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+ CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE,
+ CPU_FTR_740_NOTAU = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+ CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
+ CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
+ CPU_FTR_740 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+ CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
+ CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
+ CPU_FTR_750 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+ CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
+ CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
+ CPU_FTR_750FX1 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+ CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
+ CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
+ CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM,
+ CPU_FTR_750FX2 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+ CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
+ CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
+ CPU_FTR_NO_DPM,
+ CPU_FTR_750FX = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+ CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
+ CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
+ CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS,
+ CPU_FTR_750GX = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
+ CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
+ CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
+ CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS,
+ CPU_FTR_7400_NOTAU = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+ CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
+ CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
+ CPU_FTR_MAYBE_CAN_NAP,
+ CPU_FTR_7400 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+ CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
+ CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
+ CPU_FTR_MAYBE_CAN_NAP,
+ CPU_FTR_7450_20 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+ CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
+ CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
+ CPU_FTR_NEED_COHERENT,
+ CPU_FTR_7450_21 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+ CPU_FTR_USE_TB |
+ CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
+ CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
+ CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP |
+ CPU_FTR_NEED_COHERENT,
+ CPU_FTR_7450_23 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+ CPU_FTR_USE_TB |
+ CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
+ CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
+ CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT,
+ CPU_FTR_7455_1 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+ CPU_FTR_USE_TB |
+ CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
+ CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_HAS_HIGH_BATS |
+ CPU_FTR_NEED_COHERENT,
+ CPU_FTR_7455_20 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+ CPU_FTR_USE_TB |
+ CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
+ CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
+ CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP |
+ CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS,
+ CPU_FTR_7455 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+ CPU_FTR_USE_TB |
+ CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
+ CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
+ CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
+ CPU_FTR_NEED_COHERENT,
+ CPU_FTR_7447_10 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+ CPU_FTR_USE_TB |
+ CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
+ CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
+ CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
+ CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC,
+ CPU_FTR_7447 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+ CPU_FTR_USE_TB |
+ CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
+ CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
+ CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
+ CPU_FTR_NEED_COHERENT,
+ CPU_FTR_7447A = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+ CPU_FTR_USE_TB |
+ CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
+ CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
+ CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
+ CPU_FTR_NEED_COHERENT,
+ CPU_FTR_82XX = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+ CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB,
+ CPU_FTR_G2_LE = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
+ CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS,
+ CPU_FTR_E300 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
+ CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS,
+ CPU_FTR_CLASSIC32 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+ CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
+ CPU_FTR_POWER3_32 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+ CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
+ CPU_FTR_POWER4_32 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+ CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
+ CPU_FTR_970_32 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
+ CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_ALTIVEC_COMP |
+ CPU_FTR_MAYBE_CAN_NAP,
+ CPU_FTR_8XX = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
+ CPU_FTR_40X = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
+ CPU_FTR_44X = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
+ CPU_FTR_E200 = CPU_FTR_USE_TB,
+ CPU_FTR_E500 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
+ CPU_FTR_E500_2 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
+ CPU_FTR_BIG_PHYS,
+ CPU_FTR_GENERIC_32 = CPU_FTR_COMMON,
+#ifdef __powerpc64__
+ CPU_FTR_POWER3 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
+ CPU_FTR_HPTE_TABLE | CPU_FTR_IABR,
+ CPU_FTR_RS64 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
+ CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
+ CPU_FTR_MMCRA | CPU_FTR_CTRL,
+ CPU_FTR_POWER4 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
+ CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_MMCRA,
+ CPU_FTR_PPC970 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
+ CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 |
+ CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA,
+ CPU_FTR_POWER5 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
+ CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 |
+ CPU_FTR_MMCRA | CPU_FTR_SMT |
+ CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE |
+ CPU_FTR_MMCRA_SIHV,
+ CPU_FTR_CELL = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
+ CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 |
+ CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT,
+ CPU_FTR_COMPATIBLE = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
+ CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2,
+#endif
+ CPU_FTR_POSSIBLE =
+#if CLASSIC_PPC
+ CPU_FTR_601 | CPU_FTR_603 | CPU_FTR_604 | CPU_FTR_740_NOTAU |
+ CPU_FTR_740 | CPU_FTR_750 | CPU_FTR_750FX1 |
+ CPU_FTR_750FX2 | CPU_FTR_750FX | CPU_FTR_750GX |
+ CPU_FTR_7400_NOTAU | CPU_FTR_7400 | CPU_FTR_7450_20 |
+ CPU_FTR_7450_21 | CPU_FTR_7450_23 | CPU_FTR_7455_1 |
+ CPU_FTR_7455_20 | CPU_FTR_7455 | CPU_FTR_7447_10 |
+ CPU_FTR_7447 | CPU_FTR_7447A | CPU_FTR_82XX |
+ CPU_FTR_G2_LE | CPU_FTR_E300 | CPU_FTR_CLASSIC32 |
+#else
+ CPU_FTR_GENERIC_32 |
+#endif
+#ifdef CONFIG_PPC64BRIDGE
+ CPU_FTR_POWER3_32 |
+#endif
+#ifdef CONFIG_POWER4
+ CPU_FTR_POWER4_32 | CPU_FTR_970_32 |
+#endif
+#ifdef CONFIG_8xx
+ CPU_FTR_8XX |
+#endif
+#ifdef CONFIG_40x
+ CPU_FTR_40X |
+#endif
+#ifdef CONFIG_44x
+ CPU_FTR_44X |
+#endif
+#ifdef CONFIG_FSL_BOOKE
+ CPU_FTR_E200 | CPU_FTR_E500 | CPU_FTR_E500_2 |
+#endif
+#ifdef CONFIG_CPU_POWER3
+ CPU_FTR_POWER3 |
+#endif
+#ifdef CONFIG_CPU_RS64
+ CPU_FTR_RS64 |
+#endif
+#ifdef CONFIG_CPU_POWER4
+ CPU_FTR_POWER4 |
+#endif
+#ifdef CONFIG_CPU_PPC970
+ CPU_FTR_PPC970 |
+#endif
+#ifdef CONFIG_CPU_POWER5
+ CPU_FTR_POWER5 |
+#endif
+#ifdef CONFIG_CPU_CELL
+ CPU_FTR_CELL |
+#endif
+ 0,
+ CPU_FTR_ALWAYS =
+#if CLASSIC_PPC
+ CPU_FTR_601 & CPU_FTR_603 & CPU_FTR_604 & CPU_FTR_740_NOTAU &
+ CPU_FTR_740 & CPU_FTR_750 & CPU_FTR_750FX1 &
+ CPU_FTR_750FX2 & CPU_FTR_750FX & CPU_FTR_750GX &
+ CPU_FTR_7400_NOTAU & CPU_FTR_7400 & CPU_FTR_7450_20 &
+ CPU_FTR_7450_21 & CPU_FTR_7450_23 & CPU_FTR_7455_1 &
+ CPU_FTR_7455_20 & CPU_FTR_7455 & CPU_FTR_7447_10 &
+ CPU_FTR_7447 & CPU_FTR_7447A & CPU_FTR_82XX &
+ CPU_FTR_G2_LE & CPU_FTR_E300 & CPU_FTR_CLASSIC32 &
+#else
+ CPU_FTR_GENERIC_32 &
+#endif
+#ifdef CONFIG_PPC64BRIDGE
+ CPU_FTR_POWER3_32 &
+#endif
+#ifdef CONFIG_POWER4
+ CPU_FTR_POWER4_32 & CPU_FTR_970_32 &
+#endif
+#ifdef CONFIG_8xx
+ CPU_FTR_8XX &
+#endif
+#ifdef CONFIG_40x
+ CPU_FTR_40X &
+#endif
+#ifdef CONFIG_44x
+ CPU_FTR_44X &
+#endif
+#ifdef CONFIG_FSL_BOOKE
+ CPU_FTR_E200 & CPU_FTR_E500 & CPU_FTR_E500_2 &
+#endif
+#ifdef CONFIG_CPU_POWER3
+ CPU_FTR_POWER3 &
+#endif
+#ifdef CONFIG_CPU_RS64
+ CPU_FTR_RS64 &
+#endif
+#ifdef CONFIG_CPU_POWER4
+ CPU_FTR_POWER4 &
+#endif
+#ifdef CONFIG_CPU_PPC970
+ CPU_FTR_PPC970 &
+#endif
+#ifdef CONFIG_CPU_POWER5
+ CPU_FTR_POWER5 &
+#endif
+#ifdef CONFIG_CPU_CELL
+ CPU_FTR_CELL &
+#endif
+ CPU_FTR_POSSIBLE,
+};
+
+static inline int cpu_has_feature(unsigned long feature)
+{
+ return (CPU_FTR_ALWAYS & feature) ||
+ (CPU_FTR_POSSIBLE
+#ifndef __powerpc64__
+ & cur_cpu_spec[0]->cpu_features
+#else
+ & cur_cpu_spec->cpu_features
+#endif
+ & feature);
+}
+
+#endif /* __ASSEMBLY */
+
+#ifdef __ASSEMBLY__
+
+#define BEGIN_FTR_SECTION 98:
+
+#ifndef __powerpc64__
+#define END_FTR_SECTION(msk, val) \
+99: \
+ .section __ftr_fixup,"a"; \
+ .align 2; \
+ .long msk; \
+ .long val; \
+ .long 98b; \
+ .long 99b; \
+ .previous
+#else /* __powerpc64__ */
+#define END_FTR_SECTION(msk, val) \
+99: \
+ .section __ftr_fixup,"a"; \
+ .align 3; \
+ .llong msk; \
+ .llong val; \
+ .llong 98b; \
+ .llong 99b; \
+ .previous
+#endif /* __powerpc64__ */
+
+#else
+
+#define BEGIN_FTR_SECTION "98:\n"
+
+#ifndef __powerpc64__
+#define END_FTR_SECTION(msk, val) \
+"99:\n" \
+" .section __ftr_fixup,\"a\";\n" \
+" .align 2;\n" \
+" .long "#msk";\n" \
+" .long "#val";\n" \
+" .long 98b;\n" \
+" .long 99b;\n" \
+" .previous\n"
+#else /* __powerpc64__ */
+#define END_FTR_SECTION(msk, val) \
+"99:\n" \
+" .section __ftr_fixup,\"a\";\n" \
+" .align 3;\n" \
+" .llong "#msk";\n" \
+" .llong "#val";\n" \
+" .llong 98b;\n" \
+" .llong 99b;\n" \
+" .previous\n"
+#endif /* __powerpc64__ */
+
+#endif /* __ASSEMBLY__ */
+
+#define END_FTR_SECTION_IFSET(msk) END_FTR_SECTION((msk), (msk))
+#define END_FTR_SECTION_IFCLR(msk) END_FTR_SECTION((msk), 0)
+
+#endif /* __KERNEL__ */
+#endif /* __ASM_POWERPC_CPUTABLE_H */
Index: clean-cg/include/asm-ppc/cputable.h
===================================================================
--- clean-cg.orig/include/asm-ppc/cputable.h
+++ /dev/null
@@ -1,128 +0,0 @@
-/*
- * include/asm-ppc/cputable.h
- *
- * Copyright (C) 2001 Ben. Herrenschmidt (benh@kernel.crashing.org)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef __ASM_PPC_CPUTABLE_H
-#define __ASM_PPC_CPUTABLE_H
-
-/* Exposed to userland CPU features */
-#define PPC_FEATURE_32 0x80000000
-#define PPC_FEATURE_64 0x40000000
-#define PPC_FEATURE_601_INSTR 0x20000000
-#define PPC_FEATURE_HAS_ALTIVEC 0x10000000
-#define PPC_FEATURE_HAS_FPU 0x08000000
-#define PPC_FEATURE_HAS_MMU 0x04000000
-#define PPC_FEATURE_HAS_4xxMAC 0x02000000
-#define PPC_FEATURE_UNIFIED_CACHE 0x01000000
-#define PPC_FEATURE_HAS_SPE 0x00800000
-#define PPC_FEATURE_HAS_EFP_SINGLE 0x00400000
-#define PPC_FEATURE_HAS_EFP_DOUBLE 0x00200000
-
-#ifdef __KERNEL__
-
-#ifndef __ASSEMBLY__
-
-/* This structure can grow, it's real size is used by head.S code
- * via the mkdefs mecanism.
- */
-struct cpu_spec;
-
-typedef void (*cpu_setup_t)(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
-
-struct cpu_spec {
- /* CPU is matched via (PVR & pvr_mask) == pvr_value */
- unsigned int pvr_mask;
- unsigned int pvr_value;
-
- char *cpu_name;
- unsigned int cpu_features; /* Kernel features */
- unsigned int cpu_user_features; /* Userland features */
-
- /* cache line sizes */
- unsigned int icache_bsize;
- unsigned int dcache_bsize;
-
- /* number of performance monitor counters */
- unsigned int num_pmcs;
-
- /* this is called to initialize various CPU bits like L1 cache,
- * BHT, SPD, etc... from head.S before branching to identify_machine
- */
- cpu_setup_t cpu_setup;
-};
-
-extern struct cpu_spec cpu_specs[];
-extern struct cpu_spec *cur_cpu_spec[];
-
-static inline unsigned int cpu_has_feature(unsigned int feature)
-{
- return cur_cpu_spec[0]->cpu_features & feature;
-}
-
-#endif /* __ASSEMBLY__ */
-
-/* CPU kernel features */
-#define CPU_FTR_SPLIT_ID_CACHE 0x00000001
-#define CPU_FTR_L2CR 0x00000002
-#define CPU_FTR_SPEC7450 0x00000004
-#define CPU_FTR_ALTIVEC 0x00000008
-#define CPU_FTR_TAU 0x00000010
-#define CPU_FTR_CAN_DOZE 0x00000020
-#define CPU_FTR_USE_TB 0x00000040
-#define CPU_FTR_604_PERF_MON 0x00000080
-#define CPU_FTR_601 0x00000100
-#define CPU_FTR_HPTE_TABLE 0x00000200
-#define CPU_FTR_CAN_NAP 0x00000400
-#define CPU_FTR_L3CR 0x00000800
-#define CPU_FTR_L3_DISABLE_NAP 0x00001000
-#define CPU_FTR_NAP_DISABLE_L2_PR 0x00002000
-#define CPU_FTR_DUAL_PLL_750FX 0x00004000
-#define CPU_FTR_NO_DPM 0x00008000
-#define CPU_FTR_HAS_HIGH_BATS 0x00010000
-#define CPU_FTR_NEED_COHERENT 0x00020000
-#define CPU_FTR_NO_BTIC 0x00040000
-#define CPU_FTR_BIG_PHYS 0x00080000
-
-#ifdef __ASSEMBLY__
-
-#define BEGIN_FTR_SECTION 98:
-
-#define END_FTR_SECTION(msk, val) \
-99: \
- .section __ftr_fixup,"a"; \
- .align 2; \
- .long msk; \
- .long val; \
- .long 98b; \
- .long 99b; \
- .previous
-
-#else
-
-#define BEGIN_FTR_SECTION "98:\n"
-#define END_FTR_SECTION(msk, val) \
-"99:\n" \
-" .section __ftr_fixup,\"a\";\n" \
-" .align 2;\n" \
-" .long "#msk";\n" \
-" .long "#val";\n" \
-" .long 98b;\n" \
-" .long 99b;\n" \
-" .previous\n"
-
-
-#endif /* __ASSEMBLY__ */
-
-#define END_FTR_SECTION_IFSET(msk) END_FTR_SECTION((msk), (msk))
-#define END_FTR_SECTION_IFCLR(msk) END_FTR_SECTION((msk), 0)
-
-#endif /* __ASM_PPC_CPUTABLE_H */
-#endif /* __KERNEL__ */
-
^ permalink raw reply
* Time for linuxpowerpc-dev?
From: Michael Ellerman @ 2005-09-09 2:25 UTC (permalink / raw)
To: linuxppc64-dev, linuxppc-dev
[-- Attachment #1: Type: text/plain, Size: 406 bytes --]
With the arch's merging, and all this cross-posting maddness, is it time to
start a linuxpowerpc-dev mailing list?
cheers
--
Michael Ellerman
IBM OzLabs
email: michael:ellerman.id.au
inmsg: mpe:jabber.org
wwweb: http://michael.ellerman.id.au
phone: +61 2 6212 1183 (tie line 70 21183)
We do not inherit the earth from our ancestors,
we borrow it from our children. - S.M.A.R.T Person
[-- Attachment #2: Type: application/pgp-signature, Size: 189 bytes --]
^ permalink raw reply
* Re: [PATCH] ppc: Merge tlb.h
From: Kumar Gala @ 2005-09-09 1:34 UTC (permalink / raw)
To: Benjamin Herrenschmidt
Cc: linuxppc-dev, linux-kernel, Gala Kumar K.-galak, linuxppc64-dev
In-Reply-To: <1126223767.29803.34.camel@gaston>
On Sep 8, 2005, at 6:56 PM, Benjamin Herrenschmidt wrote:
> On Thu, 2005-09-08 at 16:11 -0500, Kumar Gala wrote:
>
>> Merged tlb.h between asm-ppc32 and asm-ppc64 into asm-powerpc. Also,
>>
> fixed
>
>> a compiler warning in arch/ppc/mm/tlb.c since it was roughly related.
>>
>> Signed-off-by: Kumar K. Gala <kumar.gala@freescale.com>
>>
>
> Do we want to do that ?
>
> Replacing 2 different files with one split in #ifdef isn't a
> progress...
> As I said, I think we need two subdirs for the low level stuffs
> that is
> different, and that includes at this point all of the memory
> management
> related stuff.
I understand, but I'm also not sure if its progress to duplicate a
major of a file that is common.
In this case it might be better handled by having specific versions
per "sub-arch". I think the key is determining which files should be
handled via sub-arch diffs and which should be handled via ifdef's in
the file.
Some cases like ppc_asm are so similar that it seems better to have a
single file and ifdef the specific case.
> In addition, I'd appreciate if we could avoid touching ppc64 mm
> related
> files completely for a couple of weeks as I'm working on a fairly big
> patch that I'm really tired of having to rebase all the time ;)
Will avoid touch any other mm related headers than :)
- kumar
^ permalink raw reply
* Re: r13 is non-volatile?
From: Kumar Gala @ 2005-09-09 1:30 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: ppc64-dev, linas, linuxppc-dev list
In-Reply-To: <1126216432.29803.31.camel@gaston>
On Sep 8, 2005, at 4:53 PM, Benjamin Herrenschmidt wrote:
>
>
>> There's a different value in R13 depending on which cpu you're on,
>> so one mustn't save R13 on one CPU and attempt to restore it on
>> another.
>>
>> Maybe, for ppc32, you can pretend that r13 "is like a paca"? So
>> that instead of saving/restoring r13 like this, you could set it up
>> at the same time/instead of setting up the paca r13?
>>
>
> ppc32 uses r2 for that, it contains "current".
>
> I don't think we need to bother merging those low level CPU specific
> things. We need to have a cpu32 and a cpu64 subdirs in there for
> things
> like these, memory management, etc... imho.
My intent is to see if we can make a change so that there isn't an
ifdef.
- kumar
^ permalink raw reply
* Re: cpu features testing 32 vs 64 bit
From: David Gibson @ 2005-09-09 0:08 UTC (permalink / raw)
To: Arnd Bergmann
Cc: linuxppc64-dev, pantelis.antoniou, linuxppc-embedded,
linuxppc-dev
In-Reply-To: <200509090036.39992.arnd@arndb.de>
On Fri, Sep 09, 2005 at 12:36:39AM +0200, Arnd Bergmann wrote:
> On Freedag 09 September 2005 00:02, Kumar Gala wrote:
> >
> > On Sep 8, 2005, at 4:48 PM, Dan Malek wrote:
> > >
> > > If we #define CPU_FTR_xxx as a 0 or all 1's for processors that have
> > > or don't have these features, will the compiler be smart enough to
> > > recognize an always true or false condition and remove the
> > > test (or code as appropriate)?
> >
> > The compiler is smart enough in this case since cpu_has_feature() is
> > an inline function.
>
> I actually wrote a patch that solves the problem in a very generic way,
> see http://patchwork.ozlabs.org/linuxppc/patch?id=1048 .
> I don't remember exactly if there were serious objections against
> the patch at that time, but it looks like a much cleaner solution to me
> than defining CPU_FTR_xxx to different values depending on the
> configuration.
And we already use a mechanism essentially identical to Arnd's for
fw_has_feature().
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/people/dgibson
^ permalink raw reply
* Re: [PATCH] ppc: Merge tlb.h
From: Benjamin Herrenschmidt @ 2005-09-08 23:56 UTC (permalink / raw)
To: Kumar Gala; +Cc: linuxppc-dev, linux-kernel, linuxppc64-dev
In-Reply-To: <Pine.LNX.4.61.0509081611230.5055@nylon.am.freescale.net>
On Thu, 2005-09-08 at 16:11 -0500, Kumar Gala wrote:
> Merged tlb.h between asm-ppc32 and asm-ppc64 into asm-powerpc. Also, fixed
> a compiler warning in arch/ppc/mm/tlb.c since it was roughly related.
>
> Signed-off-by: Kumar K. Gala <kumar.gala@freescale.com>
Do we want to do that ?
Replacing 2 different files with one split in #ifdef isn't a progress...
As I said, I think we need two subdirs for the low level stuffs that is
different, and that includes at this point all of the memory management
related stuff.
In addition, I'd appreciate if we could avoid touching ppc64 mm related
files completely for a couple of weeks as I'm working on a fairly big
patch that I'm really tired of having to rebase all the time ;)
Ben.
^ permalink raw reply
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