* 1161 host
From: 汪 秀平 @ 2005-09-14 7:27 UTC (permalink / raw)
To: linuxppc-embedded
hello
1161 connect question:
don't connect usboperational state
bases: ISP1161xProgramming_Guide.pdf
_________________________________________________________________
享用世界上最大的电子邮件系统― MSN Hotmail。 http://www.hotmail.com
^ permalink raw reply
* Account Review Team
From: PayPal @ 2005-09-13 20:48 UTC (permalink / raw)
To: linuxppc-dev
[-- Attachment #1: Type: text/html, Size: 5299 bytes --]
^ permalink raw reply
* Account Review Team
From: PayPal @ 2005-09-13 20:48 UTC (permalink / raw)
To: linuxppc-embedded
[-- Attachment #1: Type: text/html, Size: 5299 bytes --]
^ permalink raw reply
* How to support LFS on ppc
From: JohnsonCheng @ 2005-09-14 9:12 UTC (permalink / raw)
To: linux-ppc-embedded
[-- Attachment #1: Type: text/plain, Size: 689 bytes --]
Dear All,
I have a problem about Large File System on ppc. The following is my example
code:
#define _FILE_OFFSET_BITS 64
#include <sys/stat.h>
#include <unistd.h>
Int main()
{
struct stat buf;
stat64("/3G",&buf);
printf("size of test = %ld \n",buf.st_size);
lstat64("/3G",&buf);
printf("size of test 2= %ld\n",buf.st_size);
return 0;
}
The conclusion is as following:
size of test = 2141735952
size of test 2= 805910402
But the real size of 3G file is 3145728000. I think it maybe the offset is
wrong, but I don't know how to correct it. Can someone give me some advise.
Thanks,
Johnson Cheng
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^ permalink raw reply
* SRAM support for the Pegasos II platform
From: Nicolas DET @ 2005-09-14 10:07 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Andrew Morton, Sven Luther, David Holm
[-- Attachment #1: Type: text/plain, Size: 307 bytes --]
Amiga............: SimpleMail http://simplemail.sourceforge.net/
Unix.............: Metamail ftp://ftp.bellcore.com/nsb/
Windows/Macintosh: Eudora http://www.qualcomm.com/
General info about MIME can be found at:
http://www.cis.ohio-state.edu/hypertext/faq/usenet/mail/mime-faq/top.html
[-- Attachment #2: Type: text/plain, Size: 412 bytes --]
Hello,
You can find enclosed or at the URL a patch for the 2.6.14-rc1.
http://arrakin.homedns.org/~nicolas/mv643xx_eth_chrp_pegasos_eth.c.2.6.14-rc1.diff
It allows (with drivers/net/mv643xx_eth.*) to take advantage of the SRAM of
the Marvell Discovery II for the network driver.
Reviews and comments welcome.
I hope it could be include in upcomming 2.6.14.
Regards,
--
Nicolas DET
MorphOS & Linux developer
[-- Attachment #3: mv643xx_eth_chrp_pegasos_eth.c.2.6.14-rc1.diff --]
[-- Type: application/octet-stream, Size: 4868 bytes --]
--- linux-2.6.14-rc1/arch/ppc/platforms/chrp_pegasos_eth.c 2005-09-14 08:14:44.275127904 +0200
+++ linux-2.6.14-rc1_nico/arch/ppc/platforms/chrp_pegasos_eth.c 2005-09-14 10:48:26.566874500 +0200
@@ -17,6 +17,21 @@
#include <linux/mv643xx.h>
#include <linux/pci.h>
+// Pegasos II location and size for the SRAM stuff
+// Only used for the ethernet driver ATM
+#define PEGASOS2_MARVELL_REGBASE (0xf1000000)
+#define PEGASOS2_MARVELL_REGSIZE (0x00004000)
+#define PEGASOS2_SRAM_BASE (0xf2000000)
+#define PEGASOS2_SRAM_SIZE (0x00008000)
+
+#define PEGASOS2_SRAM_BASE_ETH0 (PEGASOS2_SRAM_BASE)
+#define PEGASOS2_SRAM_BASE_ETH1 (PEGASOS2_SRAM_BASE_ETH0 + (PEGASOS2_SRAM_SIZE / 2) )
+
+#define PEGASOS2_SRAM_RXRING_SIZE (PEGASOS2_SRAM_SIZE/4)
+#define PEGASOS2_SRAM_TXRING_SIZE (PEGASOS2_SRAM_SIZE/4)
+
+//#define BE_VERBOSE
+
/* Pegasos 2 specific Marvell MV 64361 gigabit ethernet port setup */
static struct resource mv643xx_eth_shared_resources[] = {
[0] = {
@@ -44,7 +59,15 @@
},
};
-static struct mv643xx_eth_platform_data eth0_pd;
+static struct mv643xx_eth_platform_data eth0_pd = {
+ .tx_sram_addr = PEGASOS2_SRAM_BASE_ETH0,
+ .tx_sram_size = PEGASOS2_SRAM_TXRING_SIZE,
+ .tx_queue_size = PEGASOS2_SRAM_TXRING_SIZE/16,
+
+ .rx_sram_addr = PEGASOS2_SRAM_BASE + PEGASOS2_SRAM_TXRING_SIZE,
+ .rx_sram_size = PEGASOS2_SRAM_RXRING_SIZE,
+ .rx_queue_size = PEGASOS2_SRAM_RXRING_SIZE/16,
+};
static struct platform_device eth0_device = {
.name = MV643XX_ETH_NAME,
@@ -65,7 +88,15 @@
},
};
-static struct mv643xx_eth_platform_data eth1_pd;
+static struct mv643xx_eth_platform_data eth1_pd = {
+ .tx_sram_addr = PEGASOS2_SRAM_BASE_ETH1,
+ .tx_sram_size = PEGASOS2_SRAM_TXRING_SIZE,
+ .tx_queue_size = PEGASOS2_SRAM_TXRING_SIZE/16,
+
+ .rx_sram_addr = PEGASOS2_SRAM_BASE_ETH1 + PEGASOS2_SRAM_TXRING_SIZE,
+ .rx_sram_size = PEGASOS2_SRAM_RXRING_SIZE,
+ .rx_queue_size = PEGASOS2_SRAM_RXRING_SIZE/16,
+};
static struct platform_device eth1_device = {
.name = MV643XX_ETH_NAME,
@@ -83,7 +114,68 @@
ð1_device,
};
+/***********/
+/***********/
+#define MV_READ(offset,val) { val = readl(mv643xx_reg_base + offset); }
+#define MV_WRITE(offset,data) writel(data, mv643xx_reg_base + offset)
+
+static void __iomem *mv643xx_reg_base = NULL;
+
+static int Enable_SRAM(void)
+{
+ u32 ALong;
+
+ // Let's io remap the mv register to touch the SRAM config
+ if (mv643xx_reg_base == NULL)
+ mv643xx_reg_base = ioremap(PEGASOS2_MARVELL_REGBASE, PEGASOS2_MARVELL_REGSIZE);
+
+ if (mv643xx_reg_base == NULL)
+ return -ENOMEM;
+
+#ifdef BE_VERBOSE
+ printk("Pegasos II/Marvell MV64361: register remapped from %p to %p\n", (void *)PEGASOS2_MARVELL_REGBASE, (void *)mv643xx_reg_base);
+#endif
+
+ // First the SRAM config register
+ // We set it to 0 ATM -> No cache coherency, no parity check
+ MV_WRITE(MV64340_SRAM_CONFIG, 0);
+
+ // set the SRAM address on the CPU side
+ MV_WRITE(MV64340_INTEGRATED_SRAM_BASE_ADDR, PEGASOS2_SRAM_BASE >> 16);
+
+ // Now enable it (CPU side)
+ MV_READ(MV64340_BASE_ADDR_ENABLE, ALong);
+ ALong &= ~(1 << 19);
+ MV_WRITE(MV64340_BASE_ADDR_ENABLE, ALong);
+
+ // And now to the GB side on WB 4 (0->3) can be use for DRAM stuff
+ ALong = 0x02; // Integrated SRAM value
+ ALong |= PEGASOS2_SRAM_BASE & 0xffff0000; // Finally set the SRAM adress in the uppter par of the register
+ MV_WRITE(MV643XX_ETH_BAR_4, ALong);
+
+ // and the size ...
+ MV_WRITE(MV643XX_ETH_SIZE_REG_4, PEGASOS2_SRAM_SIZE & 0xffff0000);
+
+ // Finaly enable the window
+ MV_READ(MV643XX_ETH_BASE_ADDR_ENABLE_REG, ALong);
+ ALong &= ~(1 << 4);
+ MV_WRITE(MV643XX_ETH_BASE_ADDR_ENABLE_REG, ALong);
+
+#ifdef BE_VERBOSE
+ printk("Pegasos II/Marvell MV64361: register unmapped\n");
+ printk("Pegasos II/Marvell MV64361: SRAM at %p, size=%x\n", (void*) PEGASOS2_SRAM_BASE, PEGASOS2_SRAM_SIZE);
+#endif
+
+ iounmap(mv643xx_reg_base);
+ mv643xx_reg_base = NULL;
+
+ return 1;
+}
+
+
+/***********/
+/***********/
int
mv643xx_eth_add_pds(void)
{
@@ -93,9 +185,38 @@
{ }
};
- if (pci_dev_present(pci_marvell_mv64360)) {
+#ifdef BE_VERBOSE
+ printk("Pegasos II/Marvell MV64361: init\n");
+#endif
+
+ if (pci_dev_present(pci_marvell_mv64360))
+ {
ret = platform_add_devices(mv643xx_eth_pd_devs, ARRAY_SIZE(mv643xx_eth_pd_devs));
+
+ if ( Enable_SRAM() < 0)
+ {
+ // Humm, disable SRAM stuff
+ eth0_pd.tx_sram_addr = 0;
+ eth0_pd.tx_sram_size = 0;
+ eth0_pd.rx_sram_addr = 0;
+ eth0_pd.rx_sram_size = 0;
+
+ eth1_pd.tx_sram_addr = 0;
+ eth1_pd.tx_sram_size = 0;
+ eth1_pd.rx_sram_addr = 0;
+ eth1_pd.rx_sram_size = 0;
+
+#ifdef BE_VERBOSE
+ printk("Pegasos II/Marvell MV64361: Can't enable the SRAM\n");
+#endif
+ }
}
+
+#ifdef BE_VERBOSE
+
+ printk("Pegasos II/Marvell MV64361: init is over\n");
+#endif
+
return ret;
}
device_initcall(mv643xx_eth_add_pds);
^ permalink raw reply
* Re: How to modify MTD driver for MX29LV320ABTC-90?
From: Debora Liu @ 2005-09-14 9:42 UTC (permalink / raw)
To: ÐìСÍþµÄEMAIL; +Cc: linuxppc-embedded
Hello, ???
In message < 2005-09-14 14:10:17 rober@opnet.com.tw> you wrote:
> init_tqm_mtd: chip probing count 0
> init_tqm_mtd: chip probing count 1
> TQM8xxL: No support flash chips found!
Creat yourself coder in drivers/mtd/maps
Debora Liu
deboralh@sinovee.com
2005-09-14
^ permalink raw reply
* RE: How to support LFS on ppc
From: Fillod Stephane @ 2005-09-14 9:47 UTC (permalink / raw)
To: linux-ppc-embedded
>I have a problem about Large File System on ppc. The following is my =
example code:
Actually not problem with LFS, but with int types.
>#define _FILE_OFFSET_BITS 64
>#include <sys/stat.h>
>#include <unistd.h>
>Int main()
>{
>=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 struct stat buf;
>=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 stat64("/3G",&buf);
>=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 printf("size of test =3D %ld =
\n",buf.st_size);
^^^
Try %lld instead. Or to be portable, #include <inttypes.h>
and printf("size of test =3D %" PRId64 "\n", buf.st_size);
--=20
Stephane
^ permalink raw reply
* Re: PATCH powerpc: Merge asm-ppc*/hardirq.h
From: Christoph Hellwig @ 2005-09-14 11:05 UTC (permalink / raw)
To: Jon Loeliger; +Cc: linuxppc-dev@ozlabs.org, linuxppc64-dev
In-Reply-To: <1126643920.11056.53.camel@cashmere.sps.mot.com>
On Tue, Sep 13, 2005 at 03:38:40PM -0500, Jon Loeliger wrote:
> +#ifndef _ASM_POWERPC_HARDIRQ_H
> +#define _ASM_POWERPC_HARDIRQ_H
> +#ifdef __KERNEL__
the __KERNEL__ ifdefs is not needed. <asm/hardirq.h> is only included
from <linux/hardirq.h> which doesn't have anything user-visible.
> +
> +#include <linux/config.h>
not needed.
> +#include <linux/cache.h>
> +
> +#ifdef __powerpc64__
> +#include <linux/preempt.h>
> +#else
> +#include <linux/smp_lock.h>
> +#include <asm/irq.h>
> +#endif
We shouldn't need either of these include blocks at all.
> +
> +/* The __last_jiffy_stamp field is needed to ensure that no decrementer
> + * interrupt is lost on SMP machines. Since on most CPUs it is in the same
> + * cache line as local_irq_count, it is cheap to access and is also used on UP
> + * for uniformity.
> + */
> +typedef struct {
> + unsigned int __softirq_pending; /* set_bit is used on this */
> + unsigned int __last_jiffy_stamp;
> +} ____cacheline_aligned irq_cpustat_t;
I'd suggest just using a DECLARE_PER_CPU variable for last_jiffy_stamp.
In facct I plan to get rid of irq_cpustat_t completely at some point.
^ permalink raw reply
* RE: How to support LFS on ppc
From: JohnsonCheng @ 2005-09-14 11:45 UTC (permalink / raw)
To: 'Fillod Stephane', 'linux-ppc-embedded'
In-Reply-To: <1CFEB358338412458B21FAA0D78FE86D4F0DD5@rennsmail02.eu.thmulti.com>
Dear Stephane,
Great. It's work when I use %lld instead of %ld.
Thanks,
Johnson Cheng
-----Original Message-----
From: Fillod Stephane [mailto:stephane.fillod@thomson.net]=20
Sent: Wednesday, September 14, 2005 5:48 PM
To: linux-ppc-embedded
Cc: JohnsonCheng
Subject: RE: How to support LFS on ppc=20
>I have a problem about Large File System on ppc. The following is my
example code:
Actually not problem with LFS, but with int types.
>#define _FILE_OFFSET_BITS 64
>#include <sys/stat.h>
>#include <unistd.h>
>Int main()
>{
>=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 struct stat buf;
>=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 stat64("/3G",&buf);
>=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 printf("size of test =3D %ld =
\n",buf.st_size);
^^^
Try %lld instead. Or to be portable, #include <inttypes.h>
and printf("size of test =3D %" PRId64 "\n", buf.st_size);
--=20
Stephane
^ permalink raw reply
* How to access linux symbols from dynamically loaded .so (dlopen)
From: Nishant Galange @ 2005-09-14 9:12 UTC (permalink / raw)
To: linuxppc-embedded
Hi all
Help needed desperately. Some background on the problem:
The embedded linux (built as one large elf
file) contains an important function called "board_init()"
A test module (built as a shared object test.so) contains a function
called start_test()
void start_test() {
=09board_init(); /* The shared object has to call a function defined in the=
embedded linux elf image */
=09/*Do board tests here... */
}
1. Linux comes up to the command prompt on the board.
2. A GUI application communicates with the board via Ethernet=20
3. The GUI
transfers the test module test.so over Ethernet=20
4. The downloaded test.so is loaded via dlopen().=20
5. dlopen() and dlsym() calls succeed. start_test() starts executing=20
6. It barfs at board_init() saying "Undefined symbol: board_init"
So the dynamically loaded shared object cannot get a reference to a functio=
n define in the linux that loaded it...
How do we solve this problem? How do I make sure that symbols in the linux =
image are exposed to dynamically loaded libraries?
Most probably, it has a simple solution to tweak some compiler/linker
options. But I may be wrong...
Waiting,
Nishant
^ permalink raw reply
* Re: [PATCH 1/2] New PowerPC 4xx on-chip ethernet controller driver
From: Jeff Garzik @ 2005-09-14 12:45 UTC (permalink / raw)
To: Eugene Surovegin; +Cc: netdev, linuxppc-embedded
In-Reply-To: <20050831050048.GB17017@gate.ebshome.net>
Eugene Surovegin wrote:
> Remove old PPC4xx EMAC driver
>
> Signed-off-by: Eugene Surovegin <ebs@ebshome.net>
Please post a diff, along with a description of the changes.
One huge patch to "remove emac driver" and another huge patch to "add
emac driver" is quite silly.
Jeff
^ permalink raw reply
* MPC5200 : BAPI versions & processor revision
From: Frederic Janot @ 2005-09-14 12:49 UTC (permalink / raw)
To: linuxppc-embedded
Hi all,
I'm a bit confused about Bestcomm on MPC5200 and I need yours lights :)
Since a while, and I don't know why, I believe that Rev. A (L25R) and Rev.
B1 (M08A) of the MPC5200 processor can run well with BAPI v2.1. And with
Rev. B2 (M62C), we have to used BAPI v2.2.
Am I right or should I used BAPI v2.2 with all Rev B ?
Does BAPI v2.2 is backward compatible with Rev A ?
Thanks for your reply,
Frederic
^ permalink raw reply
* Re: PATCH powerpc: Merge asm-ppc*/hardirq.h
From: Jon Loeliger @ 2005-09-14 13:41 UTC (permalink / raw)
To: Christoph Hellwig; +Cc: linuxppc-dev@ozlabs.org, linuxppc64-dev
In-Reply-To: <20050914110506.GA7049@lst.de>
On Wed, 2005-09-14 at 06:05, Christoph Hellwig wrote:
> On Tue, Sep 13, 2005 at 03:38:40PM -0500, Jon Loeliger wrote:
> > +#ifndef _ASM_POWERPC_HARDIRQ_H
> > +#define _ASM_POWERPC_HARDIRQ_H
> > +#ifdef __KERNEL__
>
> the __KERNEL__ ifdefs is not needed. <asm/hardirq.h> is only included
> from <linux/hardirq.h> which doesn't have anything user-visible.
Will do.
> > +
> > +#include <linux/config.h>
>
> not needed.
>
> > +#include <linux/cache.h>
> > +
> > +#ifdef __powerpc64__
> > +#include <linux/preempt.h>
> > +#else
> > +#include <linux/smp_lock.h>
> > +#include <asm/irq.h>
> > +#endif
>
> We shouldn't need either of these include blocks at all.
OK. I'll do some out-ripping and verify that it
all compiles still.
> > +
> > +/* The __last_jiffy_stamp field is needed to ensure that no decrementer
> > + * interrupt is lost on SMP machines. Since on most CPUs it is in the same
> > + * cache line as local_irq_count, it is cheap to access and is also used on UP
> > + * for uniformity.
> > + */
> > +typedef struct {
> > + unsigned int __softirq_pending; /* set_bit is used on this */
> > + unsigned int __last_jiffy_stamp;
> > +} ____cacheline_aligned irq_cpustat_t;
>
> I'd suggest just using a DECLARE_PER_CPU variable for last_jiffy_stamp.
> In facct I plan to get rid of irq_cpustat_t completely at some point.
Hmmm... So, I don't want to mess that up. How about I leave it
as I've suggested and leave that step up to you as a follow on?
Thanks,
jdl
^ permalink raw reply
* Re: PATCH powerpc: Merge asm-ppc*/hardirq.h
From: Christoph Hellwig @ 2005-09-14 13:43 UTC (permalink / raw)
To: Jon Loeliger; +Cc: linuxppc-dev@ozlabs.org, linuxppc64-dev
In-Reply-To: <1126705294.14036.4.camel@cashmere.sps.mot.com>
On Wed, Sep 14, 2005 at 08:41:34AM -0500, Jon Loeliger wrote:
> > I'd suggest just using a DECLARE_PER_CPU variable for last_jiffy_stamp.
> > In facct I plan to get rid of irq_cpustat_t completely at some point.
>
> Hmmm... So, I don't want to mess that up. How about I leave it
> as I've suggested and leave that step up to you as a follow on?
ok.
^ permalink raw reply
* Re: PATCH powerpc: Merge asm-ppc*/sections.h
From: Jon Loeliger @ 2005-09-14 13:46 UTC (permalink / raw)
To: Arnd Bergmann; +Cc: linuxppc64-dev, linuxppc-dev@ozlabs.org
In-Reply-To: <200509140435.21916.arnd@arndb.de>
On Tue, 2005-09-13 at 21:35, Arnd Bergmann wrote:
> On Dinsdag 13 September 2005 22:43, Jon Loeliger wrote:
> > Here is a patch to merge asm-ppc*/sections.h.
> >
> > If anyone knows if we can do better here,
> > please feel free to abuse, er, let me know!
>
> Ok, I don't like this patch.
You will be pleased to know, then, that Becky and I both
didn't like this patch either. :-)
> IMHO for the architecture merge, we should
> have a common implementation of this, either always using per-platform
> sections or never using them, meaning that we get rid of this file.
Yeah.
> At the very least, the __*func() macros should go away, they are completely
> bogus.
I'll work on eliminating those (at least) and submitting a
cleanup patch for that as needed.
> Using the sections in arch/powerpc has the obvious advantage that it
> reduces the size of the running kernel, but also has a certain amount
> of bug-potential or at least makes the code slightly more ugly.
> It is also easier to remove the feature in ppc than adding it in ppc64.
In the Grand Scheme of Things, removing things and making them
simpler seems a lofty goal. :-) Anyone know of any pitfalls that
await me if I try to remove these sections, a la pmac and friends?
And I assume that the obvious mappings can take place (ie, that
"pmac.text" can just be placed in regular .text, etc), right?
> The users of the ppc64 function in_kernel_text() can probably be converted
> to the generic is_kernel_text() function.
I'll peer into that a bit too.
> Arnd <><
Thanks!
jdl
^ permalink raw reply
* Re: [PATCH] MPC8xx PCMCIA driver
From: Marcelo Tosatti @ 2005-09-14 14:11 UTC (permalink / raw)
To: Dominik Brodowski, linux-ppc-embedded, linux-kernel,
Pantelis Antoniou, Dan Malek
In-Reply-To: <20050901085319.GB6285@isilmar.linta.de>
On Thu, Sep 01, 2005 at 10:53:19AM +0200, Dominik Brodowski wrote:
> > +typedef struct {
> > + u_int regbit;
> > + u_int eventbit;
> > +} event_table_t;
>
> No typedefs, please.
OK, I've converted it to a plain "struct".
I think this code is just following PCMCIA style:
typedef struct pccard_mem_map {
u_char map;
u_char flags;
u_short speed;
u_long static_start;
u_int card_start;
struct resource *res;
} pccard_mem_map;
Any reason why this typedef and similar ones in ss.h
are wanted?
PCMCIA is also using u_xxx "weird data types" extensively.
^ permalink raw reply
* A question regarding the Marvel 64360 and a MPC7447A
From: Adrian B. Weissman @ 2005-09-14 14:18 UTC (permalink / raw)
To: linuxppc-embedded
Hello:
I am having some issues with the Marvell 64360
Driver, mv643xx_eth.c on an MPC7447A. I am writing
this email in the hopes that someone has seen the
type of behavior that I am seeing with this
combination.
My company has taken an existing board that had
an MPC7447 with 64360, and dropped down a MPC7447A.
On the original board that had the MPC7447, the
Marvell Driver works just fine. The MPC7447A was
supposed to be a pin-for-pin compatible replacement,
with some minor resistor bootstrapping changes to
set the processor speed.
Here are my problems:
1. Rx Resource Error with Priority Queue 0
eth_int_cause 0x00000c00 Port-0
eth_int_cause_ext 0x00000000 Port-0
rx queue cmd 0x0000fe00 Port-0
rx status 0x0000042e Port-0
tx queue cmd 0x0000ff00 Port-0
rx dropped 0x00000003 Port-0
sdma Cfg 0x00800004 Port-0
SDMA Cause Reg = 0x00000000
Using the configuration that worked just fine
on the MPC7447, I try and bring up the interface.
When I do, I immediately get an Rx Resource Error
with priority queue 0.
After thinking about what could cause an
Rx Resource error, I decided to increase the number
of Rx Buffer Descriptors to 2000, from 400. When I
did this, the Rx Resource error disappeared.
However, when thinking about this problem,
I realize that the MPX bus speed, and DDR speed has
not changed from the MPC7447 to the MPC7447A.
Given this point, why does increasing the number of
Rx Buffer Descriptors have any affect.
Thus, I think this first problem is on the
perifery of what the real problem is. This leads me
to my next problem, which I think is also on the
perifery.
2. Transmit Buffer descriptor does not relinquish
ownership of the descriptor to the processor.
eth_int_cause 0x00000005 Port-0
eth_int_cause_ext 0x00000000 Port-0
rx queue cmd 0x0003fe01 Port-0 <-----\
rx status 0x0000042e Port-0 |
tx queue cmd 0x0000fe00 Port-0 <------|
rx dropped 0x00000000 Port-0 |
sdma Cfg 0x00800004 Port-0 |
SDMA Cause Reg = 0x00000000 |
|
Here we can see that the Rx Queue and Tx Queue
is enabled.
------mv643xx_private: ----------
port num: 0
port_config: 0x00000000
port_config_extend: 0x00000000
port_sdma_config: 0x00800004
port_serial_control: 0x0164260f
port_tx_queue_command: 0x00000001
port_rx_queue_command: 0x00000001
rx_sram_addr: 0x00000000
rx_sram_size: 0x00000000
tx_sram_addr: 0x00000000
tx_sram_size: 0x00000000
rx_resource_err: 0x0
tx_resource_err: 0x0
-Rx-Buffer-Descriptor: ----------
byte_cnt: 0x0068
buf_size: 0x05f8
Command and Status: 0x2fc7555e
Next Descriptor Ptr: 0x00aa8020
Buffer Ptr: 0x00a81010
mv643xx_eth.c eth_port_send() Enableing Tx Queue
-Tx-Buffer-Descriptor: ----------
byte_cnt: 0x002a
l4i_chk: 0x0000
Command and Status: 0x80f82800
Next Descriptor Ptr: 0x00aa0030
Buffer Ptr: 0x1fdba2e2
Here, the "Command and Status" element in the
Transmit descriptor indicates that the DMA engine
still owns the descriptor. I don't see this problem,
running the same software on the MPC7447.
So, in both error conditions, there is something
screwed up with the DMA engine. In the first issue,
I was thinking that maybe the increase of descriptors
slowed down the interface enough to make it work, and
on the transmit side, the DMA error still exists.
From here, I tryed changing the SDMA config to
0 thus changing the burst size to 1, and I have tried
changing the burst size up to 16.
I also tried enabling the Tx Interrupts and only
saw them on the MPC7447, not on the MPC7447A. Thus,
the DMA engine does not think it has completed a
transaction.
I was also curious if anyone has tried using the
internal SRAM in the MV64360?
In addition, another data point I saw was that
the tx_packets is incremented when I send out an
ethernet frame, but the good_frames_sent is not
incremented.
ethtool -S eth0
NIC statistics:
rx_packets: 3
tx_packets: 3
rx_bytes: 342
tx_bytes: 126
rx_errors: 0
tx_errors: 0
rx_dropped: 0
tx_dropped: 0
good_octets_received: 342
bad_octets_received: 0
internal_mac_transmit_err: 0
good_frames_received: 3
bad_frames_received: 0
broadcast_frames_received: 1
multicast_frames_received: 0
frames_64_octets: 0
frames_65_to_127_octets: 2
frames_128_to_255_octets: 1
frames_256_to_511_octets: 0
frames_512_to_1023_octets: 0
frames_1024_to_max_octets: 0
good_octets_sent: 0
good_frames_sent: 0
excessive_collision: 0
multicast_frames_sent: 0
broadcast_frames_sent: 0
unrec_mac_control_received: 0
fc_sent: 0
good_fc_received: 0
bad_fc_received: 0
undersize_received: 0
fragments_received: 0
oversize_received: 0
jabber_received: 0
mac_receive_error: 0
bad_crc_event: 0
collision: 0
late_collision: 0
Any comments, help, questions or advice would
be greatly appreciated!!
Regards,
Adrian
__________________________________
Yahoo! Mail - PC Magazine Editors' Choice 2005
http://mail.yahoo.com
^ permalink raw reply
* Re: [PATCH] MPC8xx PCMCIA driver
From: Dominik Brodowski @ 2005-09-14 14:27 UTC (permalink / raw)
To: Marcelo Tosatti; +Cc: linux-kernel, linux-ppc-embedded
In-Reply-To: <20050914141131.GA6830@dmt.cnet>
On Wed, Sep 14, 2005 at 11:11:31AM -0300, Marcelo Tosatti wrote:
> On Thu, Sep 01, 2005 at 10:53:19AM +0200, Dominik Brodowski wrote:
>
> > > +typedef struct {
> > > + u_int regbit;
> > > + u_int eventbit;
> > > +} event_table_t;
> >
> > No typedefs, please.
>
> OK, I've converted it to a plain "struct".
Thanks.
> I think this code is just following PCMCIA style:
>
> typedef struct pccard_mem_map {
> u_char map;
> u_char flags;
> u_short speed;
> u_long static_start;
> u_int card_start;
> struct resource *res;
> } pccard_mem_map;
>
> Any reason why this typedef and similar ones in ss.h
> are wanted?
There's no reason for this being typedef'ed, and it is contrary to the
kernel source CodingStyle. However, all pcmcia code was external at first,
that's why the CodingStyle differs.
> PCMCIA is also using u_xxx "weird data types" extensively.
Unfortunately, yes. However, I'm in the process of adapting it to the kernel
CodingStyle. I don't change something from "u_int" to "unsigned int" just for
the naming of it, though, but when I'm in the same area fixing one thing or
another, I try to take care of it. New structs, like struct pcmcia_device,
already adhere the normal kernel policy on structs and typedefs.
Thanks,
Dominik
^ permalink raw reply
* Re: [PATCH] powerpc: Merged ppc_asm.h
From: Kumar Gala @ 2005-09-14 15:41 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev list, linuxppc64-dev
In-Reply-To: <Pine.LNX.4.61.0509091501510.8000@nylon.am.freescale.net>
Paul,
What's the status of applying this to your tree?
http://patchwork.ozlabs.org/linuxppc/patch?id=2330
- kumar
On Sep 9, 2005, at 3:02 PM, Gala Kumar K.-galak wrote:
> Merged ppc_asm.h between ppc32 & ppc64. The majority of the file is
> common between the two architectures excluding how a single GPR is
> saved/restored and which GPRs are non-volatile.
>
> Additionally, moved the ASM_CONST macro used on ppc64 into ppc_asm.h.
>
> Signed-off-by: Kumar Gala <kumar.gala@freescale.com>
>
> ---
> commit ba0d4d2e26509b73b7daed0c203f481d0bb06ea0
> tree fa78f19160a9174f1fec441c4f3351962c75dad4
> parent bbe4b1a6e25818f03d09f3260345bfa4442acca0
> author Kumar K. Gala <kumar.gala@freescale.com> Fri, 09 Sep 2005
> 15:01:18 -0500
> committer Kumar K. Gala <kumar.gala@freescale.com> Fri, 09 Sep 2005
> 15:01:18 -0500
>
> arch/ppc/kernel/head.S | 6 -
> arch/ppc/kernel/head_fsl_booke.S | 6 -
> include/asm-powerpc/ppc_asm.h | 437
> ++++++++++++++++++++++++++++++++++++++
> include/asm-ppc/ppc_asm.h | 350
> ------------------------------
> include/asm-ppc64/cputable.h | 2
> include/asm-ppc64/mmu.h | 1
> include/asm-ppc64/page.h | 8 -
> include/asm-ppc64/ppc_asm.h | 242 ---------------------
> 8 files changed, 446 insertions(+), 606 deletions(-)
>
> diff --git a/arch/ppc/kernel/head.S b/arch/ppc/kernel/head.S
> --- a/arch/ppc/kernel/head.S
> +++ b/arch/ppc/kernel/head.S
> @@ -804,7 +804,7 @@ load_up_altivec:
> beq 1f
> add r4,r4,r6
> addi r4,r4,THREAD /* want THREAD of last_task_used_altivec
> */
> - SAVE_32VR(0,r10,r4)
> + SAVE_32VRS(0,r10,r4)
> mfvscr vr0
> li r10,THREAD_VSCR
> stvx vr0,r10,r4
> @@ -824,7 +824,7 @@ load_up_altivec:
> stw r4,THREAD_USED_VR(r5)
> lvx vr0,r10,r5
> mtvscr vr0
> - REST_32VR(0,r10,r5)
> + REST_32VRS(0,r10,r5)
> #ifndef CONFIG_SMP
> subi r4,r5,THREAD
> sub r4,r4,r6
> @@ -870,7 +870,7 @@ giveup_altivec:
> addi r3,r3,THREAD /* want THREAD of task */
> lwz r5,PT_REGS(r3)
> cmpwi 0,r5,0
> - SAVE_32VR(0, r4, r3)
> + SAVE_32VRS(0, r4, r3)
> mfvscr vr0
> li r4,THREAD_VSCR
> stvx vr0,r4,r3
> diff --git a/arch/ppc/kernel/head_fsl_booke.S
> b/arch/ppc/kernel/head_fsl_booke.S
> --- a/arch/ppc/kernel/head_fsl_booke.S
> +++ b/arch/ppc/kernel/head_fsl_booke.S
> @@ -853,7 +853,7 @@ load_up_spe:
> cmpi 0,r4,0
> beq 1f
> addi r4,r4,THREAD /* want THREAD of last_task_used_spe */
> - SAVE_32EVR(0,r10,r4)
> + SAVE_32EVRS(0,r10,r4)
> evxor evr10, evr10, evr10 /* clear out evr10 */
> evmwumiaa evr10, evr10, evr10 /* evr10 <- ACC = 0 * 0 + ACC */
> li r5,THREAD_ACC
> @@ -873,7 +873,7 @@ load_up_spe:
> stw r4,THREAD_USED_SPE(r5)
> evlddx evr4,r10,r5
> evmra evr4,evr4
> - REST_32EVR(0,r10,r5)
> + REST_32EVRS(0,r10,r5)
> #ifndef CONFIG_SMP
> subi r4,r5,THREAD
> stw r4,last_task_used_spe@l(r3)
> @@ -963,7 +963,7 @@ _GLOBAL(giveup_spe)
> addi r3,r3,THREAD /* want THREAD of task */
> lwz r5,PT_REGS(r3)
> cmpi 0,r5,0
> - SAVE_32EVR(0, r4, r3)
> + SAVE_32EVRS(0, r4, r3)
> evxor evr6, evr6, evr6 /* clear out evr6 */
> evmwumiaa evr6, evr6, evr6 /* evr6 <- ACC = 0 * 0 + ACC */
> li r4,THREAD_ACC
> diff --git a/include/asm-powerpc/ppc_asm.h
> b/include/asm-powerpc/ppc_asm.h
> new file mode 100644
> --- /dev/null
> +++ b/include/asm-powerpc/ppc_asm.h
> @@ -0,0 +1,437 @@
> +/*
> + * Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan.
> + */
> +
> +#ifndef _ASM_POWERPC_PPC_ASM_H
> +#define _ASM_POWERPC_PPC_ASM_H
> +
> +#ifdef __ASSEMBLY__
> +
> +/*
> + * Macros for storing registers into and loading registers from
> + * exception frames.
> + */
> +#ifdef __powerpc64__
> +#define SAVE_GPR(n, base) std n,GPR0+8*(n)(base)
> +#define REST_GPR(n, base) ld n,GPR0+8*(n)(base)
> +#define SAVE_NVGPRS(base) SAVE_8GPRS(14, base); SAVE_10GPRS(22,
> base)
> +#define REST_NVGPRS(base) REST_8GPRS(14, base); REST_10GPRS(22,
> base)
> +#else
> +#define SAVE_GPR(n, base) stw n,GPR0+4*(n)(base)
> +#define REST_GPR(n, base) lwz n,GPR0+4*(n)(base)
> +#define SAVE_NVGPRS(base) SAVE_GPR(13, base); SAVE_8GPRS(14,
> base); \
> + SAVE_10GPRS(22, base)
> +#define REST_NVGPRS(base) REST_GPR(13, base); REST_8GPRS(14,
> base); \
> + REST_10GPRS(22, base)
> +#endif
> +
> +
> +#define SAVE_2GPRS(n, base) SAVE_GPR(n, base); SAVE_GPR(n+1, base)
> +#define SAVE_4GPRS(n, base) SAVE_2GPRS(n, base); SAVE_2GPRS(n+2,
> base)
> +#define SAVE_8GPRS(n, base) SAVE_4GPRS(n, base); SAVE_4GPRS(n+4,
> base)
> +#define SAVE_10GPRS(n, base) SAVE_8GPRS(n, base); SAVE_2GPRS(n+8,
> base)
> +#define REST_2GPRS(n, base) REST_GPR(n, base); REST_GPR(n+1, base)
> +#define REST_4GPRS(n, base) REST_2GPRS(n, base); REST_2GPRS(n+2,
> base)
> +#define REST_8GPRS(n, base) REST_4GPRS(n, base); REST_4GPRS(n+4,
> base)
> +#define REST_10GPRS(n, base) REST_8GPRS(n, base); REST_2GPRS(n+8,
> base)
> +
> +#define SAVE_FPR(n, base) stfd n,THREAD_FPR0+8*(n)(base)
> +#define SAVE_2FPRS(n, base) SAVE_FPR(n, base); SAVE_FPR(n+1, base)
> +#define SAVE_4FPRS(n, base) SAVE_2FPRS(n, base); SAVE_2FPRS(n+2,
> base)
> +#define SAVE_8FPRS(n, base) SAVE_4FPRS(n, base); SAVE_4FPRS(n+4,
> base)
> +#define SAVE_16FPRS(n, base) SAVE_8FPRS(n, base); SAVE_8FPRS(n+8,
> base)
> +#define SAVE_32FPRS(n, base) SAVE_16FPRS(n, base); SAVE_16FPRS(n
> +16,
> base)
> +#define REST_FPR(n, base) lfd n,THREAD_FPR0+8*(n)(base)
> +#define REST_2FPRS(n, base) REST_FPR(n, base); REST_FPR(n+1, base)
> +#define REST_4FPRS(n, base) REST_2FPRS(n, base); REST_2FPRS(n+2,
> base)
> +#define REST_8FPRS(n, base) REST_4FPRS(n, base); REST_4FPRS(n+4,
> base)
> +#define REST_16FPRS(n, base) REST_8FPRS(n, base); REST_8FPRS(n+8,
> base)
> +#define REST_32FPRS(n, base) REST_16FPRS(n, base); REST_16FPRS(n
> +16,
> base)
> +
> +#define SAVE_VR(n,b,base) li b,THREAD_VR0+(16*(n)); stvx n,b,base
> +#define SAVE_2VRS(n,b,base) SAVE_VR(n,b,base); SAVE_VR(n+1,b,base)
> +#define SAVE_4VRS(n,b,base) SAVE_2VRS(n,b,base);
> SAVE_2VRS(n+2,b,base)
> +#define SAVE_8VRS(n,b,base) SAVE_4VRS(n,b,base);
> SAVE_4VRS(n+4,b,base)
> +#define SAVE_16VRS(n,b,base) SAVE_8VRS(n,b,base);
> SAVE_8VRS(n+8,b,base)
> +#define SAVE_32VRS(n,b,base) SAVE_16VRS(n,b,base);
> SAVE_16VRS(n+16,b,base)
> +#define REST_VR(n,b,base) li b,THREAD_VR0+(16*(n)); lvx n,b,base
> +#define REST_2VRS(n,b,base) REST_VR(n,b,base); REST_VR(n+1,b,base)
> +#define REST_4VRS(n,b,base) REST_2VRS(n,b,base);
> REST_2VRS(n+2,b,base)
> +#define REST_8VRS(n,b,base) REST_4VRS(n,b,base);
> REST_4VRS(n+4,b,base)
> +#define REST_16VRS(n,b,base) REST_8VRS(n,b,base);
> REST_8VRS(n+8,b,base)
> +#define REST_32VRS(n,b,base) REST_16VRS(n,b,base);
> REST_16VRS(n+16,b,base)
> +
> +#define SAVE_EVR(n,s,base) evmergehi s,s,n; stw
> s,THREAD_EVR0+4*(n)(base)
> +#define SAVE_2EVRS(n,s,base) SAVE_EVR(n,s,base); SAVE_EVR(n
> +1,s,base)
> +#define SAVE_4EVRS(n,s,base) SAVE_2EVRS(n,s,base);
> SAVE_2EVRS(n+2,s,base)
> +#define SAVE_8EVRS(n,s,base) SAVE_4EVRS(n,s,base);
> SAVE_4EVRS(n+4,s,base)
> +#define SAVE_16EVRS(n,s,base) SAVE_8EVRS(n,s,base);
> SAVE_8EVRS(n+8,s,base)
> +#define SAVE_32EVRS(n,s,base) SAVE_16EVRS(n,s,base);
> SAVE_16EVRS(n+16,s,base)
> +#define REST_EVR(n,s,base) lwz s,THREAD_EVR0+4*(n)(base);
> evmergelo
> n,s,n
> +#define REST_2EVRS(n,s,base) REST_EVR(n,s,base); REST_EVR(n
> +1,s,base)
> +#define REST_4EVRS(n,s,base) REST_2EVRS(n,s,base);
> REST_2EVRS(n+2,s,base)
> +#define REST_8EVRS(n,s,base) REST_4EVRS(n,s,base);
> REST_4EVRS(n+4,s,base)
> +#define REST_16EVRS(n,s,base) REST_8EVRS(n,s,base);
> REST_8EVRS(n+8,s,base)
> +#define REST_32EVRS(n,s,base) REST_16EVRS(n,s,base);
> REST_16EVRS(n+16,s,base)
> +
> +/* Macros to adjust thread priority for Iseries hardware
> multithreading
> */
> +#define HMT_LOW or 1,1,1
> +#define HMT_MEDIUM or 2,2,2
> +#define HMT_HIGH or 3,3,3
> +
> +/* handle instructions that older assemblers may not know */
> +#define RFCI .long 0x4c000066 /* rfci instruction */
> +#define RFDI .long 0x4c00004e /* rfdi instruction */
> +#define RFMCI .long 0x4c00004c /* rfmci instruction */
> +
> +/*
> + * LOADADDR( rn, name )
> + * loads the address of 'name' into 'rn'
> + *
> + * LOADBASE( rn, name )
> + * loads the address (less the low 16 bits) of 'name' into 'rn'
> + * suitable for base+disp addressing
> + */
> +#ifdef __powerpc64__
> +#define LOADADDR(rn,name) \
> + lis rn,name##@highest; \
> + ori rn,rn,name##@higher; \
> + rldicr rn,rn,32,31; \
> + oris rn,rn,name##@h; \
> + ori rn,rn,name##@l
> +
> +#define LOADBASE(rn,name) \
> + lis rn,name@highest; \
> + ori rn,rn,name@higher; \
> + rldicr rn,rn,32,31; \
> + oris rn,rn,name@ha
> +
> +
> +#define SET_REG_TO_CONST(reg, value) \
> + lis reg,(((value)>>48)&0xFFFF); \
> + ori reg,reg,(((value)>>32)&0xFFFF); \
> + rldicr reg,reg,32,31; \
> + oris reg,reg,(((value)>>16)&0xFFFF); \
> + ori reg,reg,((value)&0xFFFF);
> +
> +#define SET_REG_TO_LABEL(reg, label) \
> + lis reg,(label)@highest; \
> + ori reg,reg,(label)@higher; \
> + rldicr reg,reg,32,31; \
> + oris reg,reg,(label)@h; \
> + ori reg,reg,(label)@l;
> +#endif
> +
> +/* various errata or part fixups */
> +#ifdef CONFIG_PPC601_SYNC_FIX
> +#define SYNC \
> +BEGIN_FTR_SECTION \
> + sync; \
> + isync; \
> +END_FTR_SECTION_IFSET(CPU_FTR_601)
> +#define SYNC_601 \
> +BEGIN_FTR_SECTION \
> + sync; \
> +END_FTR_SECTION_IFSET(CPU_FTR_601)
> +#define ISYNC_601 \
> +BEGIN_FTR_SECTION \
> + isync; \
> +END_FTR_SECTION_IFSET(CPU_FTR_601)
> +#else
> +#define SYNC
> +#define SYNC_601
> +#define ISYNC_601
> +#endif
> +
> +
> +#ifndef CONFIG_SMP
> +#define TLBSYNC
> +#else /* CONFIG_SMP */
> +/* tlbsync is not implemented on 601 */
> +#define TLBSYNC \
> +BEGIN_FTR_SECTION \
> + tlbsync; \
> + sync; \
> +END_FTR_SECTION_IFCLR(CPU_FTR_601)
> +#endif
> +
> +
> +/*
> + * This instruction is not implemented on the PPC 603 or 601;
> however,
> on
> + * the 403GCX and 405GP tlbia IS defined and tlbie is not.
> + * All of these instructions exist in the 8xx, they have magical
> powers,
> + * and they must be used.
> + */
> +
> +#if !defined(CONFIG_4xx) && !defined(CONFIG_8xx)
> +#define tlbia \
> + li r4,1024; \
> + mtctr r4; \
> + lis r4,KERNELBASE@h; \
> +0: tlbie r4; \
> + addi r4,r4,0x1000; \
> + bdnz 0b
> +#endif
> +
> +
> +#ifdef CONFIG_IBM405_ERR77
> +#define PPC405_ERR77(ra,rb) dcbt ra, rb;
> +#define PPC405_ERR77_SYNC sync;
> +#else
> +#define PPC405_ERR77(ra,rb)
> +#define PPC405_ERR77_SYNC
> +#endif
> +
> +
> +#ifdef CONFIG_IBM440EP_ERR42
> +#define PPC440EP_ERR42 isync
> +#else
> +#define PPC440EP_ERR42
> +#endif
> +
> +
> +#if defined(CONFIG_BOOKE)
> +#define tophys(rd,rs) \
> + addis rd,rs,0
> +
> +#define tovirt(rd,rs) \
> + addis rd,rs,0
> +
> +#elif defined(CONFIG_PPC64)
> +/* PPPBBB - DRENG If KERNELBASE is always 0xC0...,
> + * Then we can easily do this with one asm insn. -Peter
> + */
> +#define tophys(rd,rs) \
> + lis rd,((KERNELBASE>>48)&0xFFFF); \
> + rldicr rd,rd,32,31; \
> + sub rd,rs,rd
> +
> +#define tovirt(rd,rs) \
> + lis rd,((KERNELBASE>>48)&0xFFFF); \
> + rldicr rd,rd,32,31; \
> + add rd,rs,rd
> +#else
> +/*
> + * On APUS (Amiga PowerPC cpu upgrade board), we don't know the
> + * physical base address of RAM at compile time.
> + */
> +#define tophys(rd,rs) \
> +0: addis rd,rs,-KERNELBASE@h; \
> + .section ".vtop_fixup","aw"; \
> + .align 1; \
> + .long 0b; \
> + .previous
> +
> +#define tovirt(rd,rs) \
> +0: addis rd,rs,KERNELBASE@h; \
> + .section ".ptov_fixup","aw"; \
> + .align 1; \
> + .long 0b; \
> + .previous
> +#endif
> +
> +/*
> + * On 64-bit cpus, we use the rfid instruction instead of rfi, but
> + * we then have to make sure we preserve the top 32 bits except for
> + * the 64-bit mode bit, which we clear.
> + */
> +#if defined(CONFIG_PPC64BRIDGE)
> +#define FIX_SRR1(ra, rb) \
> + mr rb,ra; \
> + mfmsr ra; \
> + clrldi ra,ra,1; /* turn off 64-bit mode */ \
> + rldimi ra,rb,0,32
> +#define RFI .long 0x4c000024 /* rfid
> instruction */
> +#define MTMSRD(r) .long (0x7c000164 + ((r) << 21)) /*
> mtmsrd */
> +#define CLR_TOP32(r) rlwinm (r),(r),0,0,31 /* clear top
> 32 bits */
> +#elif defined(CONFIG_PPC64)
> +/* Insert the high 32 bits of the MSR into what will be the new
> + MSR (via SRR1 and rfid) This preserves the MSR.SF and MSR.ISF
> + bits. */
> +
> +#define FIX_SRR1(ra, rb) \
> + mr rb,ra; \
> + mfmsr ra; \
> + rldimi ra,rb,0,32
> +
> +#define CLR_TOP32(r) rlwinm (r),(r),0,0,31 /* clear top
> 32 bits */
> +
> +#else
> +#define FIX_SRR1(ra, rb)
> +#ifndef CONFIG_40x
> +#define RFI rfi
> +#else
> +#define RFI rfi; b . /* Prevent prefetch past rfi */
> +#endif
> +#define MTMSRD(r) mtmsr r
> +#define CLR_TOP32(r)
> +#endif
> +
> +/* The boring bits... */
> +
> +/* Condition Register Bit Fields */
> +
> +#define cr0 0
> +#define cr1 1
> +#define cr2 2
> +#define cr3 3
> +#define cr4 4
> +#define cr5 5
> +#define cr6 6
> +#define cr7 7
> +
> +
> +/* General Purpose Registers (GPRs) */
> +
> +#define r0 0
> +#define r1 1
> +#define r2 2
> +#define r3 3
> +#define r4 4
> +#define r5 5
> +#define r6 6
> +#define r7 7
> +#define r8 8
> +#define r9 9
> +#define r10 10
> +#define r11 11
> +#define r12 12
> +#define r13 13
> +#define r14 14
> +#define r15 15
> +#define r16 16
> +#define r17 17
> +#define r18 18
> +#define r19 19
> +#define r20 20
> +#define r21 21
> +#define r22 22
> +#define r23 23
> +#define r24 24
> +#define r25 25
> +#define r26 26
> +#define r27 27
> +#define r28 28
> +#define r29 29
> +#define r30 30
> +#define r31 31
> +
> +
> +/* Floating Point Registers (FPRs) */
> +
> +#define fr0 0
> +#define fr1 1
> +#define fr2 2
> +#define fr3 3
> +#define fr4 4
> +#define fr5 5
> +#define fr6 6
> +#define fr7 7
> +#define fr8 8
> +#define fr9 9
> +#define fr10 10
> +#define fr11 11
> +#define fr12 12
> +#define fr13 13
> +#define fr14 14
> +#define fr15 15
> +#define fr16 16
> +#define fr17 17
> +#define fr18 18
> +#define fr19 19
> +#define fr20 20
> +#define fr21 21
> +#define fr22 22
> +#define fr23 23
> +#define fr24 24
> +#define fr25 25
> +#define fr26 26
> +#define fr27 27
> +#define fr28 28
> +#define fr29 29
> +#define fr30 30
> +#define fr31 31
> +
> +/* AltiVec Registers (VPRs) */
> +
> +#define vr0 0
> +#define vr1 1
> +#define vr2 2
> +#define vr3 3
> +#define vr4 4
> +#define vr5 5
> +#define vr6 6
> +#define vr7 7
> +#define vr8 8
> +#define vr9 9
> +#define vr10 10
> +#define vr11 11
> +#define vr12 12
> +#define vr13 13
> +#define vr14 14
> +#define vr15 15
> +#define vr16 16
> +#define vr17 17
> +#define vr18 18
> +#define vr19 19
> +#define vr20 20
> +#define vr21 21
> +#define vr22 22
> +#define vr23 23
> +#define vr24 24
> +#define vr25 25
> +#define vr26 26
> +#define vr27 27
> +#define vr28 28
> +#define vr29 29
> +#define vr30 30
> +#define vr31 31
> +
> +/* SPE Registers (EVPRs) */
> +
> +#define evr0 0
> +#define evr1 1
> +#define evr2 2
> +#define evr3 3
> +#define evr4 4
> +#define evr5 5
> +#define evr6 6
> +#define evr7 7
> +#define evr8 8
> +#define evr9 9
> +#define evr10 10
> +#define evr11 11
> +#define evr12 12
> +#define evr13 13
> +#define evr14 14
> +#define evr15 15
> +#define evr16 16
> +#define evr17 17
> +#define evr18 18
> +#define evr19 19
> +#define evr20 20
> +#define evr21 21
> +#define evr22 22
> +#define evr23 23
> +#define evr24 24
> +#define evr25 25
> +#define evr26 26
> +#define evr27 27
> +#define evr28 28
> +#define evr29 29
> +#define evr30 30
> +#define evr31 31
> +
> +/* some stab codes */
> +#define N_FUN 36
> +#define N_RSYM 64
> +#define N_SLINE 68
> +#define N_SO 100
> +
> +#define ASM_CONST(x) x
> +#else
> + #define __ASM_CONST(x) x##UL
> + #define ASM_CONST(x) __ASM_CONST(x)
> +#endif /* __ASSEMBLY__ */
> +
> +#endif /* _ASM_POWERPC_PPC_ASM_H */
> diff --git a/include/asm-ppc/ppc_asm.h b/include/asm-ppc/ppc_asm.h
> deleted file mode 100644
> --- a/include/asm-ppc/ppc_asm.h
> +++ /dev/null
> @@ -1,350 +0,0 @@
> -/*
> - * include/asm-ppc/ppc_asm.h
> - *
> - * Definitions used by various bits of low-level assembly code on
> PowerPC.
> - *
> - * Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan.
> - *
> - * This program is free software; you can redistribute it and/or
> - * modify it under the terms of the GNU General Public License
> - * as published by the Free Software Foundation; either version
> - * 2 of the License, or (at your option) any later version.
> - */
> -
> -#include <linux/config.h>
> -
> -/*
> - * Macros for storing registers into and loading registers from
> - * exception frames.
> - */
> -#define SAVE_GPR(n, base) stw n,GPR0+4*(n)(base)
> -#define SAVE_2GPRS(n, base) SAVE_GPR(n, base); SAVE_GPR(n+1, base)
> -#define SAVE_4GPRS(n, base) SAVE_2GPRS(n, base); SAVE_2GPRS(n+2,
> base)
> -#define SAVE_8GPRS(n, base) SAVE_4GPRS(n, base); SAVE_4GPRS(n+4,
> base)
> -#define SAVE_10GPRS(n, base) SAVE_8GPRS(n, base); SAVE_2GPRS(n+8,
> base)
> -#define REST_GPR(n, base) lwz n,GPR0+4*(n)(base)
> -#define REST_2GPRS(n, base) REST_GPR(n, base); REST_GPR(n+1, base)
> -#define REST_4GPRS(n, base) REST_2GPRS(n, base); REST_2GPRS(n+2,
> base)
> -#define REST_8GPRS(n, base) REST_4GPRS(n, base); REST_4GPRS(n+4,
> base)
> -#define REST_10GPRS(n, base) REST_8GPRS(n, base); REST_2GPRS(n+8,
> base)
> -
> -#define SAVE_NVGPRS(base) SAVE_GPR(13, base); SAVE_8GPRS(14,
> base); \
> - SAVE_10GPRS(22, base)
> -#define REST_NVGPRS(base) REST_GPR(13, base); REST_8GPRS(14,
> base); \
> - REST_10GPRS(22, base)
> -
> -#define SAVE_FPR(n, base) stfd n,THREAD_FPR0+8*(n)(base)
> -#define SAVE_2FPRS(n, base) SAVE_FPR(n, base); SAVE_FPR(n+1, base)
> -#define SAVE_4FPRS(n, base) SAVE_2FPRS(n, base); SAVE_2FPRS(n+2,
> base)
> -#define SAVE_8FPRS(n, base) SAVE_4FPRS(n, base); SAVE_4FPRS(n+4,
> base)
> -#define SAVE_16FPRS(n, base) SAVE_8FPRS(n, base); SAVE_8FPRS(n+8,
> base)
> -#define SAVE_32FPRS(n, base) SAVE_16FPRS(n, base); SAVE_16FPRS(n
> +16,
> base)
> -#define REST_FPR(n, base) lfd n,THREAD_FPR0+8*(n)(base)
> -#define REST_2FPRS(n, base) REST_FPR(n, base); REST_FPR(n+1, base)
> -#define REST_4FPRS(n, base) REST_2FPRS(n, base); REST_2FPRS(n+2,
> base)
> -#define REST_8FPRS(n, base) REST_4FPRS(n, base); REST_4FPRS(n+4,
> base)
> -#define REST_16FPRS(n, base) REST_8FPRS(n, base); REST_8FPRS(n+8,
> base)
> -#define REST_32FPRS(n, base) REST_16FPRS(n, base); REST_16FPRS(n
> +16,
> base)
> -
> -#define SAVE_VR(n,b,base) li b,THREAD_VR0+(16*(n)); stvx n,b,base
> -#define SAVE_2VR(n,b,base) SAVE_VR(n,b,base); SAVE_VR(n+1,b,base)
> -#define SAVE_4VR(n,b,base) SAVE_2VR(n,b,base); SAVE_2VR(n
> +2,b,base)
> -#define SAVE_8VR(n,b,base) SAVE_4VR(n,b,base); SAVE_4VR(n
> +4,b,base)
> -#define SAVE_16VR(n,b,base) SAVE_8VR(n,b,base); SAVE_8VR(n
> +8,b,base)
> -#define SAVE_32VR(n,b,base) SAVE_16VR(n,b,base);
> SAVE_16VR(n+16,b,base)
> -#define REST_VR(n,b,base) li b,THREAD_VR0+(16*(n)); lvx n,b,base
> -#define REST_2VR(n,b,base) REST_VR(n,b,base); REST_VR(n+1,b,base)
> -#define REST_4VR(n,b,base) REST_2VR(n,b,base); REST_2VR(n
> +2,b,base)
> -#define REST_8VR(n,b,base) REST_4VR(n,b,base); REST_4VR(n
> +4,b,base)
> -#define REST_16VR(n,b,base) REST_8VR(n,b,base); REST_8VR(n
> +8,b,base)
> -#define REST_32VR(n,b,base) REST_16VR(n,b,base);
> REST_16VR(n+16,b,base)
> -
> -#define SAVE_EVR(n,s,base) evmergehi s,s,n; stw
> s,THREAD_EVR0+4*(n)(base)
> -#define SAVE_2EVR(n,s,base) SAVE_EVR(n,s,base); SAVE_EVR(n
> +1,s,base)
> -#define SAVE_4EVR(n,s,base) SAVE_2EVR(n,s,base);
> SAVE_2EVR(n+2,s,base)
> -#define SAVE_8EVR(n,s,base) SAVE_4EVR(n,s,base);
> SAVE_4EVR(n+4,s,base)
> -#define SAVE_16EVR(n,s,base) SAVE_8EVR(n,s,base);
> SAVE_8EVR(n+8,s,base)
> -#define SAVE_32EVR(n,s,base) SAVE_16EVR(n,s,base);
> SAVE_16EVR(n+16,s,base)
> -
> -#define REST_EVR(n,s,base) lwz s,THREAD_EVR0+4*(n)(base);
> evmergelo
> n,s,n
> -#define REST_2EVR(n,s,base) REST_EVR(n,s,base); REST_EVR(n
> +1,s,base)
> -#define REST_4EVR(n,s,base) REST_2EVR(n,s,base);
> REST_2EVR(n+2,s,base)
> -#define REST_8EVR(n,s,base) REST_4EVR(n,s,base);
> REST_4EVR(n+4,s,base)
> -#define REST_16EVR(n,s,base) REST_8EVR(n,s,base);
> REST_8EVR(n+8,s,base)
> -#define REST_32EVR(n,s,base) REST_16EVR(n,s,base);
> REST_16EVR(n+16,s,base)
> -
> -#ifdef CONFIG_PPC601_SYNC_FIX
> -#define SYNC \
> -BEGIN_FTR_SECTION \
> - sync; \
> - isync; \
> -END_FTR_SECTION_IFSET(CPU_FTR_601)
> -#define SYNC_601 \
> -BEGIN_FTR_SECTION \
> - sync; \
> -END_FTR_SECTION_IFSET(CPU_FTR_601)
> -#define ISYNC_601 \
> -BEGIN_FTR_SECTION \
> - isync; \
> -END_FTR_SECTION_IFSET(CPU_FTR_601)
> -#else
> -#define SYNC
> -#define SYNC_601
> -#define ISYNC_601
> -#endif
> -
> -#ifndef CONFIG_SMP
> -#define TLBSYNC
> -#else /* CONFIG_SMP */
> -/* tlbsync is not implemented on 601 */
> -#define TLBSYNC \
> -BEGIN_FTR_SECTION \
> - tlbsync; \
> - sync; \
> -END_FTR_SECTION_IFCLR(CPU_FTR_601)
> -#endif
> -
> -/*
> - * This instruction is not implemented on the PPC 603 or 601;
> however,
> on
> - * the 403GCX and 405GP tlbia IS defined and tlbie is not.
> - * All of these instructions exist in the 8xx, they have magical
> powers,
> - * and they must be used.
> - */
> -
> -#if !defined(CONFIG_4xx) && !defined(CONFIG_8xx)
> -#define tlbia \
> - li r4,1024; \
> - mtctr r4; \
> - lis r4,KERNELBASE@h; \
> -0: tlbie r4; \
> - addi r4,r4,0x1000; \
> - bdnz 0b
> -#endif
> -
> -#ifdef CONFIG_BOOKE
> -#define tophys(rd,rs) \
> - addis rd,rs,0
> -
> -#define tovirt(rd,rs) \
> - addis rd,rs,0
> -
> -#else /* CONFIG_BOOKE */
> -/*
> - * On APUS (Amiga PowerPC cpu upgrade board), we don't know the
> - * physical base address of RAM at compile time.
> - */
> -#define tophys(rd,rs) \
> -0: addis rd,rs,-KERNELBASE@h; \
> - .section ".vtop_fixup","aw"; \
> - .align 1; \
> - .long 0b; \
> - .previous
> -
> -#define tovirt(rd,rs) \
> -0: addis rd,rs,KERNELBASE@h; \
> - .section ".ptov_fixup","aw"; \
> - .align 1; \
> - .long 0b; \
> - .previous
> -#endif /* CONFIG_BOOKE */
> -
> -/*
> - * On 64-bit cpus, we use the rfid instruction instead of rfi, but
> - * we then have to make sure we preserve the top 32 bits except for
> - * the 64-bit mode bit, which we clear.
> - */
> -#ifdef CONFIG_PPC64BRIDGE
> -#define FIX_SRR1(ra, rb) \
> - mr rb,ra; \
> - mfmsr ra; \
> - clrldi ra,ra,1; /* turn off 64-bit mode */ \
> - rldimi ra,rb,0,32
> -#define RFI .long 0x4c000024 /* rfid
> instruction */
> -#define MTMSRD(r) .long (0x7c000164 + ((r) << 21)) /*
> mtmsrd */
> -#define CLR_TOP32(r) rlwinm (r),(r),0,0,31 /* clear top
> 32 bits */
> -
> -#else
> -#define FIX_SRR1(ra, rb)
> -#ifndef CONFIG_40x
> -#define RFI rfi
> -#else
> -#define RFI rfi; b . /* Prevent prefetch past rfi */
> -#endif
> -#define MTMSRD(r) mtmsr r
> -#define CLR_TOP32(r)
> -#endif /* CONFIG_PPC64BRIDGE */
> -
> -#define RFCI .long 0x4c000066 /* rfci instruction */
> -#define RFDI .long 0x4c00004e /* rfdi instruction */
> -#define RFMCI .long 0x4c00004c /* rfmci instruction */
> -
> -#ifdef CONFIG_IBM405_ERR77
> -#define PPC405_ERR77(ra,rb) dcbt ra, rb;
> -#define PPC405_ERR77_SYNC sync;
> -#else
> -#define PPC405_ERR77(ra,rb)
> -#define PPC405_ERR77_SYNC
> -#endif
> -
> -#ifdef CONFIG_IBM440EP_ERR42
> -#define PPC440EP_ERR42 isync
> -#else
> -#define PPC440EP_ERR42
> -#endif
> -
> -/* The boring bits... */
> -
> -/* Condition Register Bit Fields */
> -
> -#define cr0 0
> -#define cr1 1
> -#define cr2 2
> -#define cr3 3
> -#define cr4 4
> -#define cr5 5
> -#define cr6 6
> -#define cr7 7
> -
> -
> -/* General Purpose Registers (GPRs) */
> -
> -#define r0 0
> -#define r1 1
> -#define r2 2
> -#define r3 3
> -#define r4 4
> -#define r5 5
> -#define r6 6
> -#define r7 7
> -#define r8 8
> -#define r9 9
> -#define r10 10
> -#define r11 11
> -#define r12 12
> -#define r13 13
> -#define r14 14
> -#define r15 15
> -#define r16 16
> -#define r17 17
> -#define r18 18
> -#define r19 19
> -#define r20 20
> -#define r21 21
> -#define r22 22
> -#define r23 23
> -#define r24 24
> -#define r25 25
> -#define r26 26
> -#define r27 27
> -#define r28 28
> -#define r29 29
> -#define r30 30
> -#define r31 31
> -
> -
> -/* Floating Point Registers (FPRs) */
> -
> -#define fr0 0
> -#define fr1 1
> -#define fr2 2
> -#define fr3 3
> -#define fr4 4
> -#define fr5 5
> -#define fr6 6
> -#define fr7 7
> -#define fr8 8
> -#define fr9 9
> -#define fr10 10
> -#define fr11 11
> -#define fr12 12
> -#define fr13 13
> -#define fr14 14
> -#define fr15 15
> -#define fr16 16
> -#define fr17 17
> -#define fr18 18
> -#define fr19 19
> -#define fr20 20
> -#define fr21 21
> -#define fr22 22
> -#define fr23 23
> -#define fr24 24
> -#define fr25 25
> -#define fr26 26
> -#define fr27 27
> -#define fr28 28
> -#define fr29 29
> -#define fr30 30
> -#define fr31 31
> -
> -#define vr0 0
> -#define vr1 1
> -#define vr2 2
> -#define vr3 3
> -#define vr4 4
> -#define vr5 5
> -#define vr6 6
> -#define vr7 7
> -#define vr8 8
> -#define vr9 9
> -#define vr10 10
> -#define vr11 11
> -#define vr12 12
> -#define vr13 13
> -#define vr14 14
> -#define vr15 15
> -#define vr16 16
> -#define vr17 17
> -#define vr18 18
> -#define vr19 19
> -#define vr20 20
> -#define vr21 21
> -#define vr22 22
> -#define vr23 23
> -#define vr24 24
> -#define vr25 25
> -#define vr26 26
> -#define vr27 27
> -#define vr28 28
> -#define vr29 29
> -#define vr30 30
> -#define vr31 31
> -
> -#define evr0 0
> -#define evr1 1
> -#define evr2 2
> -#define evr3 3
> -#define evr4 4
> -#define evr5 5
> -#define evr6 6
> -#define evr7 7
> -#define evr8 8
> -#define evr9 9
> -#define evr10 10
> -#define evr11 11
> -#define evr12 12
> -#define evr13 13
> -#define evr14 14
> -#define evr15 15
> -#define evr16 16
> -#define evr17 17
> -#define evr18 18
> -#define evr19 19
> -#define evr20 20
> -#define evr21 21
> -#define evr22 22
> -#define evr23 23
> -#define evr24 24
> -#define evr25 25
> -#define evr26 26
> -#define evr27 27
> -#define evr28 28
> -#define evr29 29
> -#define evr30 30
> -#define evr31 31
> -
> -/* some stab codes */
> -#define N_FUN 36
> -#define N_RSYM 64
> -#define N_SLINE 68
> -#define N_SO 100
> diff --git a/include/asm-ppc64/cputable.h b/include/asm-ppc64/
> cputable.h
> --- a/include/asm-ppc64/cputable.h
> +++ b/include/asm-ppc64/cputable.h
> @@ -16,7 +16,7 @@
> #define __ASM_PPC_CPUTABLE_H
>
> #include <linux/config.h>
> -#include <asm/page.h> /* for ASM_CONST */
> +#include <asm/ppc_asm.h> /* for ASM_CONST */
>
> /* Exposed to userland CPU features - Must match ppc32 definitions */
> #define PPC_FEATURE_32 0x80000000
> diff --git a/include/asm-ppc64/mmu.h b/include/asm-ppc64/mmu.h
> --- a/include/asm-ppc64/mmu.h
> +++ b/include/asm-ppc64/mmu.h
> @@ -14,6 +14,7 @@
> #define _PPC64_MMU_H_
>
> #include <linux/config.h>
> +#include <asm/ppc_asm.h> /* for ASM_CONST */
> #include <asm/page.h>
>
> /*
> diff --git a/include/asm-ppc64/page.h b/include/asm-ppc64/page.h
> --- a/include/asm-ppc64/page.h
> +++ b/include/asm-ppc64/page.h
> @@ -11,13 +11,7 @@
> */
>
> #include <linux/config.h>
> -
> -#ifdef __ASSEMBLY__
> - #define ASM_CONST(x) x
> -#else
> - #define __ASM_CONST(x) x##UL
> - #define ASM_CONST(x) __ASM_CONST(x)
> -#endif
> +#include <asm/ppc_asm.h> /* for ASM_CONST */
>
> /* PAGE_SHIFT determines the page size */
> #define PAGE_SHIFT 12
> diff --git a/include/asm-ppc64/ppc_asm.h b/include/asm-ppc64/ppc_asm.h
> deleted file mode 100644
> --- a/include/asm-ppc64/ppc_asm.h
> +++ /dev/null
> @@ -1,242 +0,0 @@
> -/*
> - * arch/ppc64/kernel/ppc_asm.h
> - *
> - * Definitions used by various bits of low-level assembly code on
> PowerPC.
> - *
> - * Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan.
> - *
> - * This program is free software; you can redistribute it and/or
> - * modify it under the terms of the GNU General Public License
> - * as published by the Free Software Foundation; either version
> - * 2 of the License, or (at your option) any later version.
> - */
> -
> -#ifndef _PPC64_PPC_ASM_H
> -#define _PPC64_PPC_ASM_H
> -/*
> - * Macros for storing registers into and loading registers from
> - * exception frames.
> - */
> -#define SAVE_GPR(n, base) std n,GPR0+8*(n)(base)
> -#define SAVE_2GPRS(n, base) SAVE_GPR(n, base); SAVE_GPR(n+1, base)
> -#define SAVE_4GPRS(n, base) SAVE_2GPRS(n, base); SAVE_2GPRS(n+2,
> base)
> -#define SAVE_8GPRS(n, base) SAVE_4GPRS(n, base); SAVE_4GPRS(n+4,
> base)
> -#define SAVE_10GPRS(n, base) SAVE_8GPRS(n, base); SAVE_2GPRS(n+8,
> base)
> -#define REST_GPR(n, base) ld n,GPR0+8*(n)(base)
> -#define REST_2GPRS(n, base) REST_GPR(n, base); REST_GPR(n+1, base)
> -#define REST_4GPRS(n, base) REST_2GPRS(n, base); REST_2GPRS(n+2,
> base)
> -#define REST_8GPRS(n, base) REST_4GPRS(n, base); REST_4GPRS(n+4,
> base)
> -#define REST_10GPRS(n, base) REST_8GPRS(n, base); REST_2GPRS(n+8,
> base)
> -
> -#define SAVE_NVGPRS(base) SAVE_8GPRS(14, base); SAVE_10GPRS(22,
> base)
> -#define REST_NVGPRS(base) REST_8GPRS(14, base); REST_10GPRS(22,
> base)
> -
> -#define SAVE_FPR(n, base) stfd n,THREAD_FPR0+8*(n)(base)
> -#define SAVE_2FPRS(n, base) SAVE_FPR(n, base); SAVE_FPR(n+1, base)
> -#define SAVE_4FPRS(n, base) SAVE_2FPRS(n, base); SAVE_2FPRS(n+2,
> base)
> -#define SAVE_8FPRS(n, base) SAVE_4FPRS(n, base); SAVE_4FPRS(n+4,
> base)
> -#define SAVE_16FPRS(n, base) SAVE_8FPRS(n, base); SAVE_8FPRS(n+8,
> base)
> -#define SAVE_32FPRS(n, base) SAVE_16FPRS(n, base); SAVE_16FPRS(n
> +16,
> base)
> -#define REST_FPR(n, base) lfd n,THREAD_FPR0+8*(n)(base)
> -#define REST_2FPRS(n, base) REST_FPR(n, base); REST_FPR(n+1, base)
> -#define REST_4FPRS(n, base) REST_2FPRS(n, base); REST_2FPRS(n+2,
> base)
> -#define REST_8FPRS(n, base) REST_4FPRS(n, base); REST_4FPRS(n+4,
> base)
> -#define REST_16FPRS(n, base) REST_8FPRS(n, base); REST_8FPRS(n+8,
> base)
> -#define REST_32FPRS(n, base) REST_16FPRS(n, base); REST_16FPRS(n
> +16,
> base)
> -
> -#define SAVE_VR(n,b,base) li b,THREAD_VR0+(16*(n)); stvx n,b,base
> -#define SAVE_2VRS(n,b,base) SAVE_VR(n,b,base); SAVE_VR(n+1,b,base)
> -#define SAVE_4VRS(n,b,base) SAVE_2VRS(n,b,base);
> SAVE_2VRS(n+2,b,base)
> -#define SAVE_8VRS(n,b,base) SAVE_4VRS(n,b,base);
> SAVE_4VRS(n+4,b,base)
> -#define SAVE_16VRS(n,b,base) SAVE_8VRS(n,b,base);
> SAVE_8VRS(n+8,b,base)
> -#define SAVE_32VRS(n,b,base) SAVE_16VRS(n,b,base);
> SAVE_16VRS(n+16,b,base)
> -#define REST_VR(n,b,base) li b,THREAD_VR0+(16*(n)); lvx n,b,base
> -#define REST_2VRS(n,b,base) REST_VR(n,b,base); REST_VR(n+1,b,base)
> -#define REST_4VRS(n,b,base) REST_2VRS(n,b,base);
> REST_2VRS(n+2,b,base)
> -#define REST_8VRS(n,b,base) REST_4VRS(n,b,base);
> REST_4VRS(n+4,b,base)
> -#define REST_16VRS(n,b,base) REST_8VRS(n,b,base);
> REST_8VRS(n+8,b,base)
> -#define REST_32VRS(n,b,base) REST_16VRS(n,b,base);
> REST_16VRS(n+16,b,base)
> -
> -/* Macros to adjust thread priority for Iseries hardware
> multithreading
> */
> -#define HMT_LOW or 1,1,1
> -#define HMT_MEDIUM or 2,2,2
> -#define HMT_HIGH or 3,3,3
> -
> -/* Insert the high 32 bits of the MSR into what will be the new
> - MSR (via SRR1 and rfid) This preserves the MSR.SF and MSR.ISF
> - bits. */
> -
> -#define FIX_SRR1(ra, rb) \
> - mr rb,ra; \
> - mfmsr ra; \
> - rldimi ra,rb,0,32
> -
> -#define CLR_TOP32(r) rlwinm (r),(r),0,0,31 /* clear top
> 32 bits */
> -
> -/*
> - * LOADADDR( rn, name )
> - * loads the address of 'name' into 'rn'
> - *
> - * LOADBASE( rn, name )
> - * loads the address (less the low 16 bits) of 'name' into 'rn'
> - * suitable for base+disp addressing
> - */
> -#define LOADADDR(rn,name) \
> - lis rn,name##@highest; \
> - ori rn,rn,name##@higher; \
> - rldicr rn,rn,32,31; \
> - oris rn,rn,name##@h; \
> - ori rn,rn,name##@l
> -
> -#define LOADBASE(rn,name) \
> - lis rn,name@highest; \
> - ori rn,rn,name@higher; \
> - rldicr rn,rn,32,31; \
> - oris rn,rn,name@ha
> -
> -
> -#define SET_REG_TO_CONST(reg, value) \
> - lis reg,(((value)>>48)&0xFFFF); \
> - ori reg,reg,(((value)>>32)&0xFFFF); \
> - rldicr reg,reg,32,31; \
> - oris reg,reg,(((value)>>16)&0xFFFF); \
> - ori reg,reg,((value)&0xFFFF);
> -
> -#define SET_REG_TO_LABEL(reg, label) \
> - lis reg,(label)@highest; \
> - ori reg,reg,(label)@higher; \
> - rldicr reg,reg,32,31; \
> - oris reg,reg,(label)@h; \
> - ori reg,reg,(label)@l;
> -
> -
> -/* PPPBBB - DRENG If KERNELBASE is always 0xC0...,
> - * Then we can easily do this with one asm insn. -Peter
> - */
> -#define tophys(rd,rs) \
> - lis rd,((KERNELBASE>>48)&0xFFFF); \
> - rldicr rd,rd,32,31; \
> - sub rd,rs,rd
> -
> -#define tovirt(rd,rs) \
> - lis rd,((KERNELBASE>>48)&0xFFFF); \
> - rldicr rd,rd,32,31; \
> - add rd,rs,rd
> -
> -/* Condition Register Bit Fields */
> -
> -#define cr0 0
> -#define cr1 1
> -#define cr2 2
> -#define cr3 3
> -#define cr4 4
> -#define cr5 5
> -#define cr6 6
> -#define cr7 7
> -
> -
> -/* General Purpose Registers (GPRs) */
> -
> -#define r0 0
> -#define r1 1
> -#define r2 2
> -#define r3 3
> -#define r4 4
> -#define r5 5
> -#define r6 6
> -#define r7 7
> -#define r8 8
> -#define r9 9
> -#define r10 10
> -#define r11 11
> -#define r12 12
> -#define r13 13
> -#define r14 14
> -#define r15 15
> -#define r16 16
> -#define r17 17
> -#define r18 18
> -#define r19 19
> -#define r20 20
> -#define r21 21
> -#define r22 22
> -#define r23 23
> -#define r24 24
> -#define r25 25
> -#define r26 26
> -#define r27 27
> -#define r28 28
> -#define r29 29
> -#define r30 30
> -#define r31 31
> -
> -
> -/* Floating Point Registers (FPRs) */
> -
> -#define fr0 0
> -#define fr1 1
> -#define fr2 2
> -#define fr3 3
> -#define fr4 4
> -#define fr5 5
> -#define fr6 6
> -#define fr7 7
> -#define fr8 8
> -#define fr9 9
> -#define fr10 10
> -#define fr11 11
> -#define fr12 12
> -#define fr13 13
> -#define fr14 14
> -#define fr15 15
> -#define fr16 16
> -#define fr17 17
> -#define fr18 18
> -#define fr19 19
> -#define fr20 20
> -#define fr21 21
> -#define fr22 22
> -#define fr23 23
> -#define fr24 24
> -#define fr25 25
> -#define fr26 26
> -#define fr27 27
> -#define fr28 28
> -#define fr29 29
> -#define fr30 30
> -#define fr31 31
> -
> -#define vr0 0
> -#define vr1 1
> -#define vr2 2
> -#define vr3 3
> -#define vr4 4
> -#define vr5 5
> -#define vr6 6
> -#define vr7 7
> -#define vr8 8
> -#define vr9 9
> -#define vr10 10
> -#define vr11 11
> -#define vr12 12
> -#define vr13 13
> -#define vr14 14
> -#define vr15 15
> -#define vr16 16
> -#define vr17 17
> -#define vr18 18
> -#define vr19 19
> -#define vr20 20
> -#define vr21 21
> -#define vr22 22
> -#define vr23 23
> -#define vr24 24
> -#define vr25 25
> -#define vr26 26
> -#define vr27 27
> -#define vr28 28
> -#define vr29 29
> -#define vr30 30
> -#define vr31 31
> -
> -#endif /* _PPC64_PPC_ASM_H */
> _______________________________________________
> Linuxppc64-dev mailing list
> Linuxppc64-dev@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc64-dev
>
^ permalink raw reply
* Re: gdb hangs on Linux 2.6.11 on 8xx
From: Aristeu Sergio Rozanski Filho @ 2005-09-14 15:42 UTC (permalink / raw)
To: Marcelo Tosatti; +Cc: linuxppc-embedded
In-Reply-To: <20050913180440.GC14889@dmt.cnet>
Hi Marcelo,
> flash_test is trying to handle a signal, can you print some information
> about it in get_signal_to_deliver (before ptrace_stop), such as si_signo:
>
> typedef struct siginfo {
> int si_signo;
> int si_errno;
> int si_code;
>
> ptrace_stop() calls do_notify_parent_cldstop() to wakeup gdb, maybe
> there's something wrong during wakeup?
>
> The box locks up completly or its just gdb that freezes?
seems it's more simple than I thought: seems to be a problem with serial
console as I'm able to use gdb using ssh
Is serial console (using ttyCPM) supposed to work with gdb?
--
Aristeu
^ permalink raw reply
* Re: [PATCH 1/2] New PowerPC 4xx on-chip ethernet controller driver
From: Eugene Surovegin @ 2005-09-14 16:18 UTC (permalink / raw)
To: Jeff Garzik; +Cc: netdev, linuxppc-embedded
In-Reply-To: <43281B7D.5000106@pobox.com>
On Wed, Sep 14, 2005 at 08:45:49AM -0400, Jeff Garzik wrote:
> Eugene Surovegin wrote:
> >Remove old PPC4xx EMAC driver
> >
> >Signed-off-by: Eugene Surovegin <ebs@ebshome.net>
>
> Please post a diff, along with a description of the changes.
>
> One huge patch to "remove emac driver" and another huge patch to "add
> emac driver" is quite silly.
Jeff, it's not silly. I can post combined patch, but you won't be
able to read it (and combined patch is still big).
As I said, it's a _complete_ re-write. It's a _new_ driver, not just
some "changes". Description of what was done was in the first e-mail.
I've split it into two parts specifically, so _you_ will be able to
read new patch and comment on it.
--
Eugene
^ permalink raw reply
* [PATCH] New PowerPC 4xx on-chip ethernet controller driver
From: Eugene Surovegin @ 2005-09-14 17:08 UTC (permalink / raw)
To: Jeff Garzik; +Cc: netdev, linuxppc-embedded
In-Reply-To: <43281B7D.5000106@pobox.com>
On Wed, Sep 14, 2005 at 08:45:49AM -0400, Jeff Garzik wrote:
> Eugene Surovegin wrote:
> >Remove old PPC4xx EMAC driver
> >
> >Signed-off-by: Eugene Surovegin <ebs@ebshome.net>
>
> Please post a diff, along with a description of the changes.
>
> One huge patch to "remove emac driver" and another huge patch to "add
> emac driver" is quite silly.
This patch replaces current PowerPC 4xx EMAC driver with
new, re-written version.
New driver uses NAPI, it solves stability problems under heavy packet
load and low memory, corrects chip register access and fixes numerous
small bugs I don't even remember now :).
This patch has been tested on all supported in 2.6 PPC 4xx boards.
It's been used in production for almost a year now on custom
4xx hardware. PPC32 specific parts are already upstream.
Patch was acked by the current EMAC driver maintainer (Matt Porter). I
will be maintaining this new version.
Signed-off-by: Eugene Surovegin <ebs@ebshome.net>
--
Kconfig | 72
ibm_emac/Makefile | 13
ibm_emac/ibm_emac.h | 418 +++--
ibm_emac/ibm_emac_core.c | 3391 ++++++++++++++++++++++++----------------------
ibm_emac/ibm_emac_core.h | 313 ++--
ibm_emac/ibm_emac_debug.c | 377 ++---
ibm_emac/ibm_emac_debug.h | 63
ibm_emac/ibm_emac_mal.c | 671 +++++----
ibm_emac/ibm_emac_mal.h | 336 +++-
ibm_emac/ibm_emac_phy.c | 335 ++--
ibm_emac/ibm_emac_phy.h | 105 -
ibm_emac/ibm_emac_rgmii.c | 202 ++
ibm_emac/ibm_emac_rgmii.h | 68
ibm_emac/ibm_emac_tah.c | 111 +
ibm_emac/ibm_emac_tah.h | 96 -
ibm_emac/ibm_emac_zmii.c | 256 +++
ibm_emac/ibm_emac_zmii.h | 114 -
17 files changed, 4119 insertions(+), 2822 deletions(-)
Patch is quite big (~234K) because there is virtualy 0% of common code
between old and new version.
It can be found at http://kernel.ebshome.net/emac/4xx_napi_emac.diff
^ permalink raw reply
* Re: [PATCH] MPC8xx PCMCIA driver
From: Marcelo Tosatti @ 2005-09-14 18:21 UTC (permalink / raw)
To: Dominik Brodowski, Jeff Garzik, linux-ppc-embedded, linux-kernel
Cc: Magnus Damm
In-Reply-To: <20050914142746.GA14742@isilmar.linta.de>
Here is an uptodated version of the MPC8xx PCMCIA driver for v2.6,
addressing comments by Jeff and Dominik:
- use IO accessors instead of direct device memory referencing
- avoid usage of non-standard "uint/uchar" data types
- kill struct typedef's
Will submit it for inclusion once v2.6.14 is out.
Testing on 8xx platforms is more than welcome! Works like a charm
on our custom hardware (CONFIG_PRxK).
diff --git a/drivers/pcmcia/Kconfig b/drivers/pcmcia/Kconfig
--- a/drivers/pcmcia/Kconfig
+++ b/drivers/pcmcia/Kconfig
@@ -154,6 +154,16 @@ config TCIC
"Bridge" is the name used for the hardware inside your computer that
PCMCIA cards are plugged into. If unsure, say N.
+config PCMCIA_M8XX
+ tristate "MPC8xx PCMCIA support"
+ depends on PCMCIA && PPC
+ select PCCARD_NONSTATIC
+ help
+ Say Y here to include support for PowerPC 8xx series PCMCIA
+ controller.
+
+ This driver is also available as a module called m8xx_pcmcia.
+
config HD64465_PCMCIA
tristate "HD64465 host bridge support"
depends on HD64465 && PCMCIA
diff --git a/drivers/pcmcia/Makefile b/drivers/pcmcia/Makefile
--- a/drivers/pcmcia/Makefile
+++ b/drivers/pcmcia/Makefile
@@ -25,6 +25,7 @@ obj-$(CONFIG_PD6729) += pd6729.o
obj-$(CONFIG_I82365) += i82365.o
obj-$(CONFIG_I82092) += i82092.o
obj-$(CONFIG_TCIC) += tcic.o
+obj-$(CONFIG_PCMCIA_M8XX) += m8xx_pcmcia.o
obj-$(CONFIG_HD64465_PCMCIA) += hd64465_ss.o
obj-$(CONFIG_PCMCIA_SA1100) += sa11xx_core.o sa1100_cs.o
obj-$(CONFIG_PCMCIA_SA1111) += sa11xx_core.o sa1111_cs.o
diff --git a/drivers/pcmcia/m8xx_pcmcia.c b/drivers/pcmcia/m8xx_pcmcia.c
new file mode 100644
--- /dev/null
+++ b/drivers/pcmcia/m8xx_pcmcia.c
@@ -0,0 +1,1290 @@
+/*
+ * m8xx_pcmcia.c - Linux PCMCIA socket driver for the mpc8xx series.
+ *
+ * (C) 1999-2000 Magnus Damm <damm@bitsmart.com>
+ * (C) 2001-2002 Montavista Software, Inc.
+ * <mlocke@mvista.com>
+ *
+ * Support for two slots by Cyclades Corporation
+ * <oliver.kurth@cyclades.de>
+ * Further fixes, v2.6 kernel port
+ * <marcelo.tosatti@cyclades.com>
+ *
+ * "The ExCA standard specifies that socket controllers should provide
+ * two IO and five memory windows per socket, which can be independently
+ * configured and positioned in the host address space and mapped to
+ * arbitrary segments of card address space. " - David A Hinds. 1999
+ *
+ * This controller does _not_ meet the ExCA standard.
+ *
+ * m8xx pcmcia controller brief info:
+ * + 8 windows (attrib, mem, i/o)
+ * + up to two slots (SLOT_A and SLOT_B)
+ * + inputpins, outputpins, event and mask registers.
+ * - no offset register. sigh.
+ *
+ * Because of the lacking offset register we must map the whole card.
+ * We assign each memory window PCMCIA_MEM_WIN_SIZE address space.
+ * Make sure there is (PCMCIA_MEM_WIN_SIZE * PCMCIA_MEM_WIN_NO
+ * * PCMCIA_SOCKETS_NO) bytes at PCMCIA_MEM_WIN_BASE.
+ * The i/o windows are dynamically allocated at PCMCIA_IO_WIN_BASE.
+ * They are maximum 64KByte each...
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/fcntl.h>
+#include <linux/string.h>
+
+#include <asm/io.h>
+#include <asm/bitops.h>
+#include <asm/segment.h>
+#include <asm/system.h>
+
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/sched.h>
+#include <linux/slab.h>
+#include <linux/timer.h>
+#include <linux/ioport.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+
+#include <asm/mpc8xx.h>
+#include <asm/8xx_immap.h>
+#include <asm/irq.h>
+
+#include <pcmcia/version.h>
+#include <pcmcia/cs_types.h>
+#include <pcmcia/cs.h>
+#include <pcmcia/ss.h>
+
+#ifdef PCMCIA_DEBUG
+static int pc_debug = PCMCIA_DEBUG;
+module_param(pc_debug, int, 0);
+#define dprintk(args...) printk(KERN_DEBUG "m8xx_pcmcia: " args);
+#else
+#define dprintk(args...)
+#endif
+
+#define pcmcia_info(args...) printk(KERN_INFO "m8xx_pcmcia: "args)
+#define pcmcia_error(args...) printk(KERN_ERR "m8xx_pcmcia: "args)
+
+static const char *version = "Version 0.06, Aug 2005";
+MODULE_LICENSE("Dual MPL/GPL");
+
+#if !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B)
+
+/* The RPX series use SLOT_B */
+#if defined(CONFIG_RPXCLASSIC) || defined(CONFIG_RPXLITE)
+#define CONFIG_PCMCIA_SLOT_B
+#define CONFIG_BD_IS_MHZ
+#endif
+
+/* The ADS board use SLOT_A */
+#ifdef CONFIG_ADS
+#define CONFIG_PCMCIA_SLOT_A
+#define CONFIG_BD_IS_MHZ
+#endif
+
+/* The FADS series are a mess */
+#ifdef CONFIG_FADS
+#if defined(CONFIG_MPC860T) || defined(CONFIG_MPC860) || defined(CONFIG_MPC821)
+#define CONFIG_PCMCIA_SLOT_A
+#else
+#define CONFIG_PCMCIA_SLOT_B
+#endif
+#endif
+
+/* Cyclades ACS uses both slots */
+#ifdef CONFIG_PRxK
+#define CONFIG_PCMCIA_SLOT_A
+#define CONFIG_PCMCIA_SLOT_B
+#endif
+
+#endif /* !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B) */
+
+#if defined(CONFIG_PCMCIA_SLOT_A) && defined(CONFIG_PCMCIA_SLOT_B)
+
+#define PCMCIA_SOCKETS_NO 2
+/* We have only 8 windows, dualsocket support will be limited. */
+#define PCMCIA_MEM_WIN_NO 2
+#define PCMCIA_IO_WIN_NO 2
+#define PCMCIA_SLOT_MSG "SLOT_A and SLOT_B"
+
+#elif defined(CONFIG_PCMCIA_SLOT_A) || defined(CONFIG_PCMCIA_SLOT_B)
+
+#define PCMCIA_SOCKETS_NO 1
+/* full support for one slot */
+#define PCMCIA_MEM_WIN_NO 5
+#define PCMCIA_IO_WIN_NO 2
+
+/* define _slot_ to be able to optimize macros */
+
+#ifdef CONFIG_PCMCIA_SLOT_A
+#define _slot_ 0
+#define PCMCIA_SLOT_MSG "SLOT_A"
+#else
+#define _slot_ 1
+#define PCMCIA_SLOT_MSG "SLOT_B"
+#endif
+
+#else
+#error m8xx_pcmcia: Bad configuration!
+#endif
+
+/* ------------------------------------------------------------------------- */
+
+#define PCMCIA_MEM_WIN_BASE 0xe0000000 /* base address for memory window 0 */
+#define PCMCIA_MEM_WIN_SIZE 0x04000000 /* each memory window is 64 MByte */
+#define PCMCIA_IO_WIN_BASE _IO_BASE /* base address for io window 0 */
+
+#define PCMCIA_SCHLVL PCMCIA_INTERRUPT /* Status Change Interrupt Level */
+
+/* ------------------------------------------------------------------------- */
+
+/* 2.4.x and newer has this always in HZ */
+#define M8XX_BUSFREQ ((((bd_t *)&(__res))->bi_busfreq))
+
+static int pcmcia_schlvl = PCMCIA_SCHLVL;
+
+static spinlock_t events_lock = SPIN_LOCK_UNLOCKED;
+
+
+#define PCMCIA_SOCKET_KEY_5V 1
+#define PCMCIA_SOCKET_KEY_LV 2
+
+/* look up table for pgcrx registers */
+static u32 *m8xx_pgcrx[2] = {
+ &((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pgcra,
+ &((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pgcrb
+};
+
+/*
+ * This structure is used to address each window in the PCMCIA controller.
+ *
+ * Keep in mind that we assume that pcmcia_win[n+1] is mapped directly
+ * after pcmcia_win[n]...
+ */
+
+struct pcmcia_win {
+ u32 br;
+ u32 or;
+};
+
+/*
+ * For some reason the hardware guys decided to make both slots share
+ * some registers.
+ *
+ * Could someone invent object oriented hardware ?
+ *
+ * The macros are used to get the right bit from the registers.
+ * SLOT_A : slot = 0
+ * SLOT_B : slot = 1
+ */
+
+#define M8XX_PCMCIA_VS1(slot) (0x80000000 >> (slot << 4))
+#define M8XX_PCMCIA_VS2(slot) (0x40000000 >> (slot << 4))
+#define M8XX_PCMCIA_VS_MASK(slot) (0xc0000000 >> (slot << 4))
+#define M8XX_PCMCIA_VS_SHIFT(slot) (30 - (slot << 4))
+
+#define M8XX_PCMCIA_WP(slot) (0x20000000 >> (slot << 4))
+#define M8XX_PCMCIA_CD2(slot) (0x10000000 >> (slot << 4))
+#define M8XX_PCMCIA_CD1(slot) (0x08000000 >> (slot << 4))
+#define M8XX_PCMCIA_BVD2(slot) (0x04000000 >> (slot << 4))
+#define M8XX_PCMCIA_BVD1(slot) (0x02000000 >> (slot << 4))
+#define M8XX_PCMCIA_RDY(slot) (0x01000000 >> (slot << 4))
+#define M8XX_PCMCIA_RDY_L(slot) (0x00800000 >> (slot << 4))
+#define M8XX_PCMCIA_RDY_H(slot) (0x00400000 >> (slot << 4))
+#define M8XX_PCMCIA_RDY_R(slot) (0x00200000 >> (slot << 4))
+#define M8XX_PCMCIA_RDY_F(slot) (0x00100000 >> (slot << 4))
+#define M8XX_PCMCIA_MASK(slot) (0xFFFF0000 >> (slot << 4))
+
+#define M8XX_PCMCIA_POR_VALID 0x00000001
+#define M8XX_PCMCIA_POR_WRPROT 0x00000002
+#define M8XX_PCMCIA_POR_ATTRMEM 0x00000010
+#define M8XX_PCMCIA_POR_IO 0x00000018
+#define M8XX_PCMCIA_POR_16BIT 0x00000040
+
+#define M8XX_PGCRX(slot) m8xx_pgcrx[slot]
+
+#define M8XX_PGCRX_CXOE 0x00000080
+#define M8XX_PGCRX_CXRESET 0x00000040
+
+/* we keep one lookup table per socket to check flags */
+
+#define PCMCIA_EVENTS_MAX 5 /* 4 max at a time + termination */
+
+struct event_table {
+ u32 regbit;
+ u32 eventbit;
+};
+
+struct socket_info {
+ void (*handler)(void *info, u32 events);
+ void *info;
+
+ u32 slot;
+
+ socket_state_t state;
+ struct pccard_mem_map mem_win[PCMCIA_MEM_WIN_NO];
+ struct pccard_io_map io_win[PCMCIA_IO_WIN_NO];
+ struct event_table events[PCMCIA_EVENTS_MAX];
+ struct pcmcia_socket socket;
+};
+
+static struct socket_info socket[PCMCIA_SOCKETS_NO];
+
+/*
+ * Search this table to see if the windowsize is
+ * supported...
+ */
+
+#define M8XX_SIZES_NO 32
+
+static const u32 m8xx_size_to_gray[M8XX_SIZES_NO] =
+{
+ 0x00000001, 0x00000002, 0x00000008, 0x00000004,
+ 0x00000080, 0x00000040, 0x00000010, 0x00000020,
+ 0x00008000, 0x00004000, 0x00001000, 0x00002000,
+ 0x00000100, 0x00000200, 0x00000800, 0x00000400,
+
+ 0x0fffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0x01000000, 0x02000000, 0xffffffff, 0x04000000,
+ 0x00010000, 0x00020000, 0x00080000, 0x00040000,
+ 0x00800000, 0x00400000, 0x00100000, 0x00200000
+};
+
+/* ------------------------------------------------------------------------- */
+
+static irqreturn_t m8xx_interrupt(int irq, void *dev, struct pt_regs *regs);
+
+#define PCMCIA_BMT_LIMIT (15*4) /* Bus Monitor Timeout value */
+
+/* ------------------------------------------------------------------------- */
+/* board specific stuff: */
+/* voltage_set(), hardware_enable() and hardware_disable() */
+/* ------------------------------------------------------------------------- */
+/* RPX Boards from Embedded Planet */
+
+#if defined(CONFIG_RPXCLASSIC) || defined(CONFIG_RPXLITE)
+
+/* The RPX boards seems to have it's bus monitor timeout set to 6*8 clocks.
+ * SYPCR is write once only, therefore must the slowest memory be faster
+ * than the bus monitor or we will get a machine check due to the bus timeout.
+ */
+
+#define PCMCIA_BOARD_MSG "RPX CLASSIC or RPX LITE"
+
+#undef PCMCIA_BMT_LIMIT
+#define PCMCIA_BMT_LIMIT (6*8)
+
+static int voltage_set(int slot, int vcc, int vpp)
+{
+ u32 reg = 0;
+
+ switch(vcc) {
+ case 0: break;
+ case 33:
+ reg |= BCSR1_PCVCTL4;
+ break;
+ case 50:
+ reg |= BCSR1_PCVCTL5;
+ break;
+ default:
+ return 1;
+ }
+
+ switch(vpp) {
+ case 0: break;
+ case 33:
+ case 50:
+ if(vcc == vpp)
+ reg |= BCSR1_PCVCTL6;
+ else
+ return 1;
+ break;
+ case 120:
+ reg |= BCSR1_PCVCTL7;
+ default:
+ return 1;
+ }
+
+ if(!((vcc == 50) || (vcc == 0)))
+ return 1;
+
+ /* first, turn off all power */
+
+ out_be32(((u32 *)RPX_CSR_ADDR), in_be32(((u32 *)RPX_CSR_ADDR)) & ~(BCSR1_PCVCTL4 | BCSR1_PCVCTL5 | BCSR1_PCVCTL6 | BCSR1_PCVCTL7));
+
+ /* enable new powersettings */
+
+ out_be32(((u32 *)RPX_CSR_ADDR), in_be32(((u32 *)RPX_CSR_ADDR)) | reg);
+
+ return 0;
+}
+
+#define socket_get(_slot_) PCMCIA_SOCKET_KEY_5V
+#define hardware_enable(_slot_) /* No hardware to enable */
+#define hardware_disable(_slot_) /* No hardware to disable */
+
+#endif /* CONFIG_RPXCLASSIC */
+
+/* FADS Boards from Motorola */
+
+#if defined(CONFIG_FADS)
+
+#define PCMCIA_BOARD_MSG "FADS"
+
+static int voltage_set(int slot, int vcc, int vpp)
+{
+ u32 reg = 0;
+
+ switch(vcc) {
+ case 0:
+ break;
+ case 33:
+ reg |= BCSR1_PCCVCC0;
+ break;
+ case 50:
+ reg |= BCSR1_PCCVCC1;
+ break;
+ default:
+ return 1;
+ }
+
+ switch(vpp) {
+ case 0:
+ break;
+ case 33:
+ case 50:
+ if(vcc == vpp)
+ reg |= BCSR1_PCCVPP1;
+ else
+ return 1;
+ break;
+ case 120:
+ if ((vcc == 33) || (vcc == 50))
+ reg |= BCSR1_PCCVPP0;
+ else
+ return 1;
+ default:
+ return 1;
+ }
+
+ /* first, turn off all power */
+ out_be32(&((u32 *)BCSR1), in_be32(&((u32 *)BCSR1)) & ~(BCSR1_PCCVCC_MASK | BCSR1_PCCVPP_MASK));
+
+ /* enable new powersettings */
+ out_be32(&((u32 *)BCSR1), in_be32(&((u32 *)BCSR1)) | reg);
+
+ return 0;
+}
+
+#define socket_get(_slot_) PCMCIA_SOCKET_KEY_5V
+
+static void hardware_enable(int slot)
+{
+ out_be32(&((u32 *)BCSR1), in_be32(&((u32 *)BCSR1)) & ~BCSR1_PCCEN);
+}
+
+static void hardware_disable(int slot)
+{
+ out_be32(&((u32 *)BCSR1), in_be32(&((u32 *)BCSR1)) | BCSR1_PCCEN);
+}
+
+#endif
+
+/* ------------------------------------------------------------------------- */
+/* Motorola MBX860 */
+
+#if defined(CONFIG_MBX)
+
+#define PCMCIA_BOARD_MSG "MBX"
+
+static int voltage_set(int slot, int vcc, int vpp)
+{
+ u8 reg = 0;
+
+ switch(vcc) {
+ case 0:
+ break;
+ case 33:
+ reg |= CSR2_VCC_33;
+ break;
+ case 50:
+ reg |= CSR2_VCC_50;
+ break;
+ default:
+ return 1;
+ }
+
+ switch(vpp) {
+ case 0:
+ break;
+ case 33:
+ case 50:
+ if(vcc == vpp)
+ reg |= CSR2_VPP_VCC;
+ else
+ return 1;
+ break;
+ case 120:
+ if ((vcc == 33) || (vcc == 50))
+ reg |= CSR2_VPP_12;
+ else
+ return 1;
+ default:
+ return 1;
+ }
+
+ /* first, turn off all power */
+ out_8(&((u8 *)MBX_CSR2_ADDR), in_8(&((u8 *)MBX_CSR2_ADDR)) & ~(CSR2_VCC_MASK | CSR2_VPP_MASK));
+
+ /* enable new powersettings */
+ out_8(&((u8 *)MBX_CSR2_ADDR), in_8(&((u8 *)MBX_CSR2_ADDR)) | reg);
+
+ return 0;
+}
+
+#define socket_get(_slot_) PCMCIA_SOCKET_KEY_5V
+#define hardware_enable(_slot_) /* No hardware to enable */
+#define hardware_disable(_slot_) /* No hardware to disable */
+
+#endif /* CONFIG_MBX */
+
+#if defined(CONFIG_PRxK)
+#include <asm/cpld.h>
+extern volatile fpga_pc_regs *fpga_pc;
+
+#define PCMCIA_BOARD_MSG "MPC855T"
+
+static int voltage_set(int slot, int vcc, int vpp)
+{
+ u8 reg = 0;
+ u8 regread;
+ cpld_regs *ccpld = get_cpld();
+
+ switch(vcc) {
+ case 0:
+ break;
+ case 33:
+ reg |= PCMCIA_VCC_33;
+ break;
+ case 50:
+ reg |= PCMCIA_VCC_50;
+ break;
+ default:
+ return 1;
+ }
+
+ switch(vpp) {
+ case 0:
+ break;
+ case 33:
+ case 50:
+ if(vcc == vpp)
+ reg |= PCMCIA_VPP_VCC;
+ else
+ return 1;
+ break;
+ case 120:
+ if ((vcc == 33) || (vcc == 50))
+ reg |= PCMCIA_VPP_12;
+ else
+ return 1;
+ default:
+ return 1;
+ }
+
+ reg = reg >> (slot << 2);
+ regread = in_8(&ccpld->fpga_pc_ctl);
+ if (reg != (regread & ((PCMCIA_VCC_MASK | PCMCIA_VPP_MASK) >> (slot << 2)))) {
+ /* enable new powersettings */
+ regread = regread & ~((PCMCIA_VCC_MASK | PCMCIA_VPP_MASK) >> (slot << 2));
+ out_8(&ccpld->fpga_pc_ctl, reg | regread);
+ msleep(100);
+ }
+
+ return 0;
+}
+
+#define socket_get(_slot_) PCMCIA_SOCKET_KEY_LV
+#define hardware_enable(_slot_) /* No hardware to enable */
+#define hardware_disable(_slot_) /* No hardware to disable */
+
+#endif /* CONFIG_PRxK */
+
+static void m8xx_shutdown(void)
+{
+ u32 m, i;
+ struct pcmcia_win *w;
+
+ for(i = 0; i < PCMCIA_SOCKETS_NO; i++){
+ w = (void *) &((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pbr0;
+
+ out_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pscr, M8XX_PCMCIA_MASK(i));
+ out_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_per, in_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_per) & ~M8XX_PCMCIA_MASK(i));
+
+ /* turn off interrupt and disable CxOE */
+ out_be32(M8XX_PGCRX(i), M8XX_PGCRX_CXOE);
+
+ /* turn off memory windows */
+ for(m = 0; m < PCMCIA_MEM_WIN_NO; m++) {
+ out_be32(&w->or, 0); /* set to not valid */
+ w++;
+ }
+
+ /* turn off voltage */
+ voltage_set(i, 0, 0);
+
+ /* disable external hardware */
+ hardware_disable(i);
+ }
+
+ free_irq(pcmcia_schlvl, NULL);
+}
+
+/* copied from tcic.c */
+
+static int m8xx_drv_suspend(struct device *dev, pm_message_t state, u32 level)
+{
+ int ret = 0;
+ if (level == SUSPEND_SAVE_STATE)
+ ret = pcmcia_socket_dev_suspend(dev, state);
+ return ret;
+}
+
+static int m8xx_drv_resume(struct device *dev, u32 level)
+{
+ int ret = 0;
+ if (level == RESUME_RESTORE_STATE)
+ ret = pcmcia_socket_dev_resume(dev);
+ return ret;
+}
+
+static struct device_driver m8xx_driver = {
+ .name = "m8xx-pcmcia",
+ .bus = &platform_bus_type,
+ .suspend = m8xx_drv_suspend,
+ .resume = m8xx_drv_resume,
+};
+
+static struct platform_device m8xx_device = {
+ .name = "m8xx-pcmcia",
+ .id = 0,
+};
+
+static u32 pending_events[PCMCIA_SOCKETS_NO];
+static spinlock_t pending_event_lock = SPIN_LOCK_UNLOCKED;
+
+static irqreturn_t m8xx_interrupt(int irq, void *dev, struct pt_regs *regs)
+{
+ struct socket_info *s;
+ struct event_table *e;
+ unsigned int i, events, pscr, pipr, per;
+
+ dprintk("Interrupt!\n");
+ /* get interrupt sources */
+
+ pscr = in_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pscr);
+ pipr = in_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pipr);
+ per = in_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_per);
+
+ for(i = 0; i < PCMCIA_SOCKETS_NO; i++) {
+ s = &socket[i];
+ e = &s->events[0];
+ events = 0;
+
+ while(e->regbit) {
+ if(pscr & e->regbit)
+ events |= e->eventbit;
+
+ e++;
+ }
+
+ /*
+ * report only if both card detect signals are the same
+ * not too nice done,
+ * we depend on that CD2 is the bit to the left of CD1...
+ */
+ if(events & SS_DETECT)
+ if(((pipr & M8XX_PCMCIA_CD2(i)) >> 1) ^
+ (pipr & M8XX_PCMCIA_CD1(i)))
+ {
+ events &= ~SS_DETECT;
+ }
+
+#ifdef PCMCIA_GLITCHY_CD
+ /*
+ * I've experienced CD problems with my ADS board.
+ * We make an extra check to see if there was a
+ * real change of Card detection.
+ */
+
+ if((events & SS_DETECT) &&
+ ((pipr &
+ (M8XX_PCMCIA_CD2(i) | M8XX_PCMCIA_CD1(i))) == 0) &&
+ (s->state.Vcc | s->state.Vpp)) {
+ events &= ~SS_DETECT;
+ /*printk( "CD glitch workaround - CD = 0x%08x!\n",
+ (pipr & (M8XX_PCMCIA_CD2(i)
+ | M8XX_PCMCIA_CD1(i))));*/
+ }
+#endif
+
+ /* call the handler */
+
+ dprintk("slot %u: events = 0x%02x, pscr = 0x%08x, "
+ "pipr = 0x%08x\n",
+ i, events, pscr, pipr);
+
+ if(events) {
+ spin_lock(&pending_event_lock);
+ pending_events[i] |= events;
+ spin_unlock(&pending_event_lock);
+ /*
+ * Turn off RDY_L bits in the PER mask on
+ * CD interrupt receival.
+ *
+ * They can generate bad interrupts on the
+ * ACS4,8,16,32. - marcelo
+ */
+ per &= ~M8XX_PCMCIA_RDY_L(0);
+ per &= ~M8XX_PCMCIA_RDY_L(1);
+
+ out_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_per, per);
+
+ if (events)
+ pcmcia_parse_events(&socket[i].socket, events);
+ }
+ }
+
+ /* clear the interrupt sources */
+ out_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pscr, pscr);
+
+ dprintk("Interrupt done.\n");
+
+ return IRQ_HANDLED;
+}
+
+static u32 m8xx_get_graycode(u32 size)
+{
+ u32 k;
+
+ for(k = 0; k < M8XX_SIZES_NO; k++)
+ if(m8xx_size_to_gray[k] == size)
+ break;
+
+ if((k == M8XX_SIZES_NO) || (m8xx_size_to_gray[k] == -1))
+ k = -1;
+
+ return k;
+}
+
+static u32 m8xx_get_speed(u32 ns, u32 is_io)
+{
+ u32 reg, clocks, psst, psl, psht;
+
+ if(!ns) {
+
+ /*
+ * We get called with IO maps setup to 0ns
+ * if not specified by the user.
+ * They should be 255ns.
+ */
+
+ if(is_io)
+ ns = 255;
+ else
+ ns = 100; /* fast memory if 0 */
+ }
+
+ /*
+ * In PSST, PSL, PSHT fields we tell the controller
+ * timing parameters in CLKOUT clock cycles.
+ * CLKOUT is the same as GCLK2_50.
+ */
+
+/* how we want to adjust the timing - in percent */
+
+#define ADJ 180 /* 80 % longer accesstime - to be sure */
+
+ clocks = ((M8XX_BUSFREQ / 1000) * ns) / 1000;
+ clocks = (clocks * ADJ) / (100*1000);
+ if(clocks >= PCMCIA_BMT_LIMIT) {
+ printk( "Max access time limit reached\n");
+ clocks = PCMCIA_BMT_LIMIT-1;
+ }
+
+ psst = clocks / 7; /* setup time */
+ psht = clocks / 7; /* hold time */
+ psl = (clocks * 5) / 7; /* strobe length */
+
+ psst += clocks - (psst + psht + psl);
+
+ reg = psst << 12;
+ reg |= psl << 7;
+ reg |= psht << 16;
+
+ return reg;
+}
+
+static int m8xx_get_status(struct pcmcia_socket *sock, unsigned int *value)
+{
+ int lsock = container_of(sock, struct socket_info, socket)->slot;
+ struct socket_info *s = &socket[lsock];
+ unsigned int pipr, reg;
+
+ pipr = in_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pipr);
+
+ *value = ((pipr & (M8XX_PCMCIA_CD1(lsock)
+ | M8XX_PCMCIA_CD2(lsock))) == 0) ? SS_DETECT : 0;
+ *value |= (pipr & M8XX_PCMCIA_WP(lsock)) ? SS_WRPROT : 0;
+
+ if (s->state.flags & SS_IOCARD)
+ *value |= (pipr & M8XX_PCMCIA_BVD1(lsock)) ? SS_STSCHG : 0;
+ else {
+ *value |= (pipr & M8XX_PCMCIA_RDY(lsock)) ? SS_READY : 0;
+ *value |= (pipr & M8XX_PCMCIA_BVD1(lsock)) ? SS_BATDEAD : 0;
+ *value |= (pipr & M8XX_PCMCIA_BVD2(lsock)) ? SS_BATWARN : 0;
+ }
+
+ if (s->state.Vcc | s->state.Vpp)
+ *value |= SS_POWERON;
+
+ /*
+ * Voltage detection:
+ * This driver only supports 16-Bit pc-cards.
+ * Cardbus is not handled here.
+ *
+ * To determine what voltage to use we must read the VS1 and VS2 pin.
+ * Depending on what socket type is present,
+ * different combinations mean different things.
+ *
+ * Card Key Socket Key VS1 VS2 Card Vcc for CIS parse
+ *
+ * 5V 5V, LV* NC NC 5V only 5V (if available)
+ *
+ * 5V 5V, LV* GND NC 5 or 3.3V as low as possible
+ *
+ * 5V 5V, LV* GND GND 5, 3.3, x.xV as low as possible
+ *
+ * LV* 5V - - shall not fit into socket
+ *
+ * LV* LV* GND NC 3.3V only 3.3V
+ *
+ * LV* LV* NC GND x.xV x.xV (if avail.)
+ *
+ * LV* LV* GND GND 3.3 or x.xV as low as possible
+ *
+ * *LV means Low Voltage
+ *
+ *
+ * That gives us the following table:
+ *
+ * Socket VS1 VS2 Voltage
+ *
+ * 5V NC NC 5V
+ * 5V NC GND none (should not be possible)
+ * 5V GND NC >= 3.3V
+ * 5V GND GND >= x.xV
+ *
+ * LV NC NC 5V (if available)
+ * LV NC GND x.xV (if available)
+ * LV GND NC 3.3V
+ * LV GND GND >= x.xV
+ *
+ * So, how do I determine if I have a 5V or a LV
+ * socket on my board? Look at the socket!
+ *
+ *
+ * Socket with 5V key:
+ * ++--------------------------------------------+
+ * || |
+ * || ||
+ * || ||
+ * | |
+ * +---------------------------------------------+
+ *
+ * Socket with LV key:
+ * ++--------------------------------------------+
+ * || |
+ * | ||
+ * | ||
+ * | |
+ * +---------------------------------------------+
+ *
+ *
+ * With other words - LV only cards does not fit
+ * into the 5V socket!
+ */
+
+ /* read out VS1 and VS2 */
+
+ reg = (pipr & M8XX_PCMCIA_VS_MASK(lsock))
+ >> M8XX_PCMCIA_VS_SHIFT(lsock);
+
+ if(socket_get(lsock) == PCMCIA_SOCKET_KEY_LV) {
+ switch(reg) {
+ case 1:
+ *value |= SS_3VCARD;
+ break; /* GND, NC - 3.3V only */
+ case 2:
+ *value |= SS_XVCARD;
+ break; /* NC. GND - x.xV only */
+ };
+ }
+
+ dprintk("GetStatus(%d) = %#2.2x\n", lsock, *value);
+ return 0;
+}
+
+static int m8xx_get_socket(struct pcmcia_socket *sock, socket_state_t *state)
+{
+ int lsock = container_of(sock, struct socket_info, socket)->slot;
+ *state = socket[lsock].state; /* copy the whole structure */
+
+ dprintk("GetSocket(%d) = flags %#3.3x, Vcc %d, Vpp %d, "
+ "io_irq %d, csc_mask %#2.2x\n", lsock, state->flags,
+ state->Vcc, state->Vpp, state->io_irq, state->csc_mask);
+ return 0;
+}
+
+static int m8xx_set_socket(struct pcmcia_socket *sock, socket_state_t *state)
+{
+ int lsock = container_of(sock, struct socket_info, socket)->slot;
+ struct socket_info *s = &socket[lsock];
+ struct event_table *e;
+ unsigned int reg;
+ unsigned long flags;
+
+ dprintk( "SetSocket(%d, flags %#3.3x, Vcc %d, Vpp %d, "
+ "io_irq %d, csc_mask %#2.2x)\n", lsock, state->flags,
+ state->Vcc, state->Vpp, state->io_irq, state->csc_mask);
+
+ /* First, set voltage - bail out if invalid */
+ if(voltage_set(lsock, state->Vcc, state->Vpp))
+ return -EINVAL;
+
+ /* Take care of reset... */
+ if(state->flags & SS_RESET)
+ out_be32(M8XX_PGCRX(lsock), in_be32(M8XX_PGCRX(lsock)) | M8XX_PGCRX_CXRESET); /* active high */
+ else
+ out_be32(M8XX_PGCRX(lsock), in_be32(M8XX_PGCRX(lsock)) & ~M8XX_PGCRX_CXRESET);
+
+ /* ... and output enable. */
+
+ /* The CxOE signal is connected to a 74541 on the ADS.
+ I guess most other boards used the ADS as a reference.
+ I tried to control the CxOE signal with SS_OUTPUT_ENA,
+ but the reset signal seems connected via the 541.
+ If the CxOE is left high are some signals tristated and
+ no pullups are present -> the cards act wierd.
+ So right now the buffers are enabled if the power is on. */
+
+ if(state->Vcc || state->Vpp)
+ out_be32(M8XX_PGCRX(lsock), in_be32(M8XX_PGCRX(lsock)) & ~M8XX_PGCRX_CXOE); /* active low */
+ else
+ out_be32(M8XX_PGCRX(lsock), in_be32(M8XX_PGCRX(lsock)) | M8XX_PGCRX_CXOE);
+
+ /*
+ * We'd better turn off interrupts before
+ * we mess with the events-table..
+ */
+
+ spin_lock_irqsave(&events_lock, flags);
+
+ /*
+ * Play around with the interrupt mask to be able to
+ * give the events the generic pcmcia driver wants us to.
+ */
+
+ e = &s->events[0];
+ reg = 0;
+
+ if(state->csc_mask & SS_DETECT) {
+ e->eventbit = SS_DETECT;
+ reg |= e->regbit = (M8XX_PCMCIA_CD2(lsock)
+ | M8XX_PCMCIA_CD1(lsock));
+ e++;
+ }
+ if(state->flags & SS_IOCARD) {
+ /*
+ * I/O card
+ */
+ if(state->csc_mask & SS_STSCHG) {
+ e->eventbit = SS_STSCHG;
+ reg |= e->regbit = M8XX_PCMCIA_BVD1(lsock);
+ e++;
+ }
+ /*
+ * If io_irq is non-zero we should enable irq.
+ */
+ if(state->io_irq) {
+ out_be32(M8XX_PGCRX(lsock), in_be32(M8XX_PGCRX(lsock)) | mk_int_int_mask(state->io_irq) << 24);
+ /*
+ * Strange thing here:
+ * The manual does not tell us which interrupt
+ * the sources generate.
+ * Anyhow, I found out that RDY_L generates IREQLVL.
+ *
+ * We use level triggerd interrupts, and they don't
+ * have to be cleared in PSCR in the interrupt handler.
+ */
+ reg |= M8XX_PCMCIA_RDY_L(lsock);
+ }
+ else
+ out_be32(M8XX_PGCRX(lsock), in_be32(M8XX_PGCRX(lsock)) & 0x00ffffff);
+ }
+ else {
+ /*
+ * Memory card
+ */
+ if(state->csc_mask & SS_BATDEAD) {
+ e->eventbit = SS_BATDEAD;
+ reg |= e->regbit = M8XX_PCMCIA_BVD1(lsock);
+ e++;
+ }
+ if(state->csc_mask & SS_BATWARN) {
+ e->eventbit = SS_BATWARN;
+ reg |= e->regbit = M8XX_PCMCIA_BVD2(lsock);
+ e++;
+ }
+ /* What should I trigger on - low/high,raise,fall? */
+ if(state->csc_mask & SS_READY) {
+ e->eventbit = SS_READY;
+ reg |= e->regbit = 0; //??
+ e++;
+ }
+ }
+
+ e->regbit = 0; /* terminate list */
+
+ /*
+ * Clear the status changed .
+ * Port A and Port B share the same port.
+ * Writing ones will clear the bits.
+ */
+
+ out_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pscr, reg);
+
+ /*
+ * Write the mask.
+ * Port A and Port B share the same port.
+ * Need for read-modify-write.
+ * Ones will enable the interrupt.
+ */
+
+ /*
+ reg |= ((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_per
+ & M8XX_PCMCIA_MASK(lsock);
+ */
+
+ reg |= in_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_per) &
+ (M8XX_PCMCIA_MASK(0) | M8XX_PCMCIA_MASK(1));
+
+ out_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_per, reg);
+
+ spin_unlock_irqrestore(&events_lock, flags);
+
+ /* copy the struct and modify the copy */
+
+ s->state = *state;
+
+ return 0;
+}
+
+static int m8xx_set_io_map(struct pcmcia_socket *sock, struct pccard_io_map *io)
+{
+ int lsock = container_of(sock, struct socket_info, socket)->slot;
+
+ struct socket_info *s = &socket[lsock];
+ struct pcmcia_win *w;
+ unsigned int reg, winnr;
+
+#define M8XX_SIZE (io->stop - io->start + 1)
+#define M8XX_BASE (PCMCIA_IO_WIN_BASE + io->start)
+
+ dprintk( "SetIOMap(%d, %d, %#2.2x, %d ns, "
+ "%#4.4x-%#4.4x)\n", lsock, io->map, io->flags,
+ io->speed, io->start, io->stop);
+
+ if ((io->map >= PCMCIA_IO_WIN_NO) || (io->start > 0xffff)
+ || (io->stop > 0xffff) || (io->stop < io->start))
+ return -EINVAL;
+
+ if((reg = m8xx_get_graycode(M8XX_SIZE)) == -1)
+ return -EINVAL;
+
+ if(io->flags & MAP_ACTIVE) {
+
+ dprintk( "io->flags & MAP_ACTIVE\n");
+
+ winnr = (PCMCIA_MEM_WIN_NO * PCMCIA_SOCKETS_NO)
+ + (lsock * PCMCIA_IO_WIN_NO) + io->map;
+
+ /* setup registers */
+
+ w = (void *) &((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pbr0;
+ w += winnr;
+
+ out_be32(&w->or, 0); /* turn off window first */
+ out_be32(&w->br, M8XX_BASE);
+
+ reg <<= 27;
+ reg |= M8XX_PCMCIA_POR_IO |(lsock << 2);
+
+ reg |= m8xx_get_speed(io->speed, 1);
+
+ if(io->flags & MAP_WRPROT)
+ reg |= M8XX_PCMCIA_POR_WRPROT;
+
+ /*if(io->flags & (MAP_16BIT | MAP_AUTOSZ))*/
+ if(io->flags & MAP_16BIT)
+ reg |= M8XX_PCMCIA_POR_16BIT;
+
+ if(io->flags & MAP_ACTIVE)
+ reg |= M8XX_PCMCIA_POR_VALID;
+
+ out_be32(&w->or, reg);
+
+ dprintk("Socket %u: Mapped io window %u at %#8.8x, "
+ "OR = %#8.8x.\n", lsock, io->map, w->br, w->or);
+ } else {
+ /* shutdown IO window */
+ winnr = (PCMCIA_MEM_WIN_NO * PCMCIA_SOCKETS_NO)
+ + (lsock * PCMCIA_IO_WIN_NO) + io->map;
+
+ /* setup registers */
+
+ w = (void *) &((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pbr0;
+ w += winnr;
+
+ out_be32(&w->or, 0); /* turn off window */
+ out_be32(&w->br, 0); /* turn off base address */
+
+ dprintk("Socket %u: Unmapped io window %u at %#8.8x, "
+ "OR = %#8.8x.\n", lsock, io->map, w->br, w->or);
+ }
+
+ /* copy the struct and modify the copy */
+ s->io_win[io->map] = *io;
+ s->io_win[io->map].flags &= (MAP_WRPROT
+ | MAP_16BIT
+ | MAP_ACTIVE);
+ dprintk("SetIOMap exit\n");
+
+ return 0;
+}
+
+static int m8xx_set_mem_map(struct pcmcia_socket *sock, struct pccard_mem_map *mem)
+{
+ int lsock = container_of(sock, struct socket_info, socket)->slot;
+ struct socket_info *s = &socket[lsock];
+ struct pcmcia_win *w;
+ struct pccard_mem_map *old;
+ unsigned int reg, winnr;
+
+ dprintk( "SetMemMap(%d, %d, %#2.2x, %d ns, "
+ "%#5.5lx, %#5.5x)\n", lsock, mem->map, mem->flags,
+ mem->speed, mem->static_start, mem->card_start);
+
+ if ((mem->map >= PCMCIA_MEM_WIN_NO)
+// || ((mem->s) >= PCMCIA_MEM_WIN_SIZE)
+ || (mem->card_start >= 0x04000000)
+ || (mem->static_start & 0xfff) /* 4KByte resolution */
+ || (mem->card_start & 0xfff))
+ return -EINVAL;
+
+ if((reg = m8xx_get_graycode(PCMCIA_MEM_WIN_SIZE)) == -1) {
+ printk( "Cannot set size to 0x%08x.\n", PCMCIA_MEM_WIN_SIZE);
+ return -EINVAL;
+ }
+ reg <<= 27;
+
+ winnr = (lsock * PCMCIA_MEM_WIN_NO) + mem->map;
+
+ /* Setup the window in the pcmcia controller */
+
+ w = (void *) &((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pbr0;
+ w += winnr;
+
+ reg |= lsock << 2;
+
+ reg |= m8xx_get_speed(mem->speed, 0);
+
+ if(mem->flags & MAP_ATTRIB)
+ reg |= M8XX_PCMCIA_POR_ATTRMEM;
+
+ if(mem->flags & MAP_WRPROT)
+ reg |= M8XX_PCMCIA_POR_WRPROT;
+
+ if(mem->flags & MAP_16BIT)
+ reg |= M8XX_PCMCIA_POR_16BIT;
+
+ if(mem->flags & MAP_ACTIVE)
+ reg |= M8XX_PCMCIA_POR_VALID;
+
+ out_be32(&w->or, reg);
+
+ dprintk("Socket %u: Mapped memory window %u at %#8.8x, "
+ "OR = %#8.8x.\n", lsock, mem->map, w->br, w->or);
+
+ if(mem->flags & MAP_ACTIVE) {
+ /* get the new base address */
+ mem->static_start = PCMCIA_MEM_WIN_BASE +
+ (PCMCIA_MEM_WIN_SIZE * winnr)
+ + mem->card_start;
+ }
+
+ dprintk("SetMemMap(%d, %d, %#2.2x, %d ns, "
+ "%#5.5lx, %#5.5x)\n", lsock, mem->map, mem->flags,
+ mem->speed, mem->static_start, mem->card_start);
+
+ /* copy the struct and modify the copy */
+
+ old = &s->mem_win[mem->map];
+
+ *old = *mem;
+ old->flags &= (MAP_ATTRIB
+ | MAP_WRPROT
+ | MAP_16BIT
+ | MAP_ACTIVE);
+
+ return 0;
+}
+
+static int m8xx_sock_init(struct pcmcia_socket *sock)
+{
+ int i;
+ pccard_io_map io = { 0, 0, 0, 0, 1 };
+ pccard_mem_map mem = { 0, 0, 0, 0, 0, 0 };
+
+ dprintk( "sock_init(%d)\n", s);
+
+ m8xx_set_socket(sock, &dead_socket);
+ for (i = 0; i < PCMCIA_IO_WIN_NO; i++) {
+ io.map = i;
+ m8xx_set_io_map(sock, &io);
+ }
+ for (i = 0; i < PCMCIA_MEM_WIN_NO; i++) {
+ mem.map = i;
+ m8xx_set_mem_map(sock, &mem);
+ }
+
+ return 0;
+
+}
+
+static int m8xx_suspend(struct pcmcia_socket *sock)
+{
+ return m8xx_set_socket(sock, &dead_socket);
+}
+
+static struct pccard_operations m8xx_services = {
+ .init = m8xx_sock_init,
+ .suspend = m8xx_suspend,
+ .get_status = m8xx_get_status,
+ .get_socket = m8xx_get_socket,
+ .set_socket = m8xx_set_socket,
+ .set_io_map = m8xx_set_io_map,
+ .set_mem_map = m8xx_set_mem_map,
+};
+
+static int __init m8xx_init(void)
+{
+ struct pcmcia_win *w;
+ unsigned int i,m;
+
+ pcmcia_info("%s\n", version);
+
+ if (driver_register(&m8xx_driver))
+ return -1;
+
+ pcmcia_info(PCMCIA_BOARD_MSG " using " PCMCIA_SLOT_MSG
+ " with IRQ %u.\n", pcmcia_schlvl);
+
+ /* Configure Status change interrupt */
+
+ if(request_irq(pcmcia_schlvl, m8xx_interrupt, 0,
+ "m8xx_pcmcia", NULL)) {
+ pcmcia_error("Cannot allocate IRQ %u for SCHLVL!\n",
+ pcmcia_schlvl);
+ return -1;
+ }
+
+ w = (void *) &((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pbr0;
+
+ out_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pscr,
+ M8XX_PCMCIA_MASK(0)| M8XX_PCMCIA_MASK(1));
+
+ out_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_per,
+ in_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_per) &
+ ~(M8XX_PCMCIA_MASK(0)| M8XX_PCMCIA_MASK(1)));
+
+/* connect interrupt and disable CxOE */
+
+ out_be32(M8XX_PGCRX(0), M8XX_PGCRX_CXOE | (mk_int_int_mask(pcmcia_schlvl) << 16));
+ out_be32(M8XX_PGCRX(1), M8XX_PGCRX_CXOE | (mk_int_int_mask(pcmcia_schlvl) << 16));
+
+/* intialize the fixed memory windows */
+
+ for(i = 0; i < PCMCIA_SOCKETS_NO; i++){
+ for(m = 0; m < PCMCIA_MEM_WIN_NO; m++) {
+ out_be32(&w->br, PCMCIA_MEM_WIN_BASE +
+ (PCMCIA_MEM_WIN_SIZE
+ * (m + i * PCMCIA_MEM_WIN_NO)));
+
+ out_be32(&w->or, 0); /* set to not valid */
+
+ w++;
+ }
+ }
+
+/* turn off voltage */
+ voltage_set(0, 0, 0);
+ voltage_set(1, 0, 0);
+
+/* Enable external hardware */
+ hardware_enable(0);
+ hardware_enable(1);
+
+ platform_device_register(&m8xx_device);
+
+ for (i = 0 ; i < PCMCIA_SOCKETS_NO; i++) {
+ socket[i].slot = i;
+ socket[i].socket.owner = THIS_MODULE;
+ socket[i].socket.features = SS_CAP_PCCARD | SS_CAP_MEM_ALIGN | SS_CAP_STATIC_MAP;
+ socket[i].socket.irq_mask = 0x000;
+ socket[i].socket.map_size = 0x1000;
+ socket[i].socket.io_offset = 0;
+ socket[i].socket.pci_irq = i ? 7 : 9;
+ socket[i].socket.ops = &m8xx_services;
+ socket[i].socket.resource_ops = &pccard_nonstatic_ops;
+ socket[i].socket.cb_dev = NULL;
+ socket[i].socket.dev.dev = &m8xx_device.dev;
+ }
+
+ for (i = 0; i < PCMCIA_SOCKETS_NO; i++)
+ pcmcia_register_socket(&socket[i].socket);
+
+ return 0;
+}
+
+static void __exit m8xx_exit(void)
+{
+ int i;
+
+ for (i = 0; i < PCMCIA_SOCKETS_NO; i++)
+ pcmcia_unregister_socket(&socket[i].socket);
+
+ m8xx_shutdown();
+
+ platform_device_unregister(&m8xx_device);
+ driver_unregister(&m8xx_driver);
+}
+
+module_init(m8xx_init);
+module_exit(m8xx_exit);
^ permalink raw reply
* Re: [PATCH] MPC8xx PCMCIA driver
From: Jeff Garzik @ 2005-09-14 18:46 UTC (permalink / raw)
To: Marcelo Tosatti
Cc: Magnus Damm, linux-kernel, Dominik Brodowski, linux-ppc-embedded
In-Reply-To: <20050914182136.GE6783@dmt.cnet>
Marcelo Tosatti wrote:
> Here is an uptodated version of the MPC8xx PCMCIA driver for v2.6,
> addressing comments by Jeff and Dominik:
>
> - use IO accessors instead of direct device memory referencing
> - avoid usage of non-standard "uint/uchar" data types
> - kill struct typedef's
>
> Will submit it for inclusion once v2.6.14 is out.
>
> Testing on 8xx platforms is more than welcome! Works like a charm
> on our custom hardware (CONFIG_PRxK).
No complaints here...
Jeff
^ permalink raw reply
* Re: [PATCH] powerpc: merge include/asm/cputable.h
From: Kumar Gala @ 2005-09-14 19:11 UTC (permalink / raw)
To: Arnd Bergmann
Cc: linuxppc-dev, pantelis.antoniou, linuxppc64-dev,
linuxppc-embedded
In-Reply-To: <200509090623.41889.arnd@arndb.de>
Arnd,
I not sure I understand what the introduction of the enum's gets us.
- kumar
On Sep 8, 2005, at 11:23 PM, Arnd Bergmann wrote:
> This is an updated version of my old patch that creates a more
> optimized
> version of cpu_has_feature(). This version actually combines
> asm-ppc/cputable.h and asm-ppc64/cputable.h, which turned out to be
> a lot more work than only the 64 bit version.
>
> The 64 bit parts a relatively straightforward port of my earlier work
> which I tested in a number of configurations. The 32 bit parts are
> not tested at all, all I did was compiling the ppc defconfig with
> this.
>
> I think it is best if I hand the patch over to Kumar and Becky for
> further testing and cleaning up the remaining bits in the new
> file, as they appear to have invested some thought in it already.
> This version still has a number of #ifdef __powerpc64__ that should
> probably go away in the process.
>
> The patch also relies on having the ASM_CONST() macro in ppc_asm.h,
> as proposed by Kumar Gala, so it won't work on the current git
> head without that change.
>
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
>
> --
>
> clean-cg/arch/ppc/kernel/cputable.c | 401 ++++
> +----------------------
> clean-cg/arch/ppc64/Kconfig | 30 ++
> clean-cg/arch/ppc64/kernel/cputable.c | 82 +----
> clean-cg/include/asm-powerpc/cputable.h | 475 ++++++++++++++++++++
> ++++++++++++
> include/asm-ppc/cputable.h | 128 --------
> include/asm-ppc64/cputable.h | 167 -----------
>
> Index: clean-cg/include/asm-ppc64/cputable.h
> ===================================================================
> --- clean-cg.orig/include/asm-ppc64/cputable.h
> +++ /dev/null
> @@ -1,167 +0,0 @@
> -/*
> - * include/asm-ppc64/cputable.h
> - *
> - * Copyright (C) 2001 Ben. Herrenschmidt (benh@kernel.crashing.org)
> - *
> - * Modifications for ppc64:
> - * Copyright (C) 2003 Dave Engebretsen <engebret@us.ibm.com>
> - *
> - * This program is free software; you can redistribute it and/or
> - * modify it under the terms of the GNU General Public License
> - * as published by the Free Software Foundation; either version
> - * 2 of the License, or (at your option) any later version.
> - */
> -
> -#ifndef __ASM_PPC_CPUTABLE_H
> -#define __ASM_PPC_CPUTABLE_H
> -
> -#include <linux/config.h>
> -#include <asm/page.h> /* for ASM_CONST */
> -
> -/* Exposed to userland CPU features - Must match ppc32 definitions */
> -#define PPC_FEATURE_32 0x80000000
> -#define PPC_FEATURE_64 0x40000000
> -#define PPC_FEATURE_601_INSTR 0x20000000
> -#define PPC_FEATURE_HAS_ALTIVEC 0x10000000
> -#define PPC_FEATURE_HAS_FPU 0x08000000
> -#define PPC_FEATURE_HAS_MMU 0x04000000
> -#define PPC_FEATURE_HAS_4xxMAC 0x02000000
> -#define PPC_FEATURE_UNIFIED_CACHE 0x01000000
> -
> -#ifdef __KERNEL__
> -
> -#ifndef __ASSEMBLY__
> -
> -/* This structure can grow, it's real size is used by head.S code
> - * via the mkdefs mechanism.
> - */
> -struct cpu_spec;
> -struct op_ppc64_model;
> -
> -typedef void (*cpu_setup_t)(unsigned long offset, struct
> cpu_spec* spec);
> -
> -struct cpu_spec {
> - /* CPU is matched via (PVR & pvr_mask) == pvr_value */
> - unsigned int pvr_mask;
> - unsigned int pvr_value;
> -
> - char *cpu_name;
> - unsigned long cpu_features; /* Kernel features */
> - unsigned int cpu_user_features; /* Userland features */
> -
> - /* cache line sizes */
> - unsigned int icache_bsize;
> - unsigned int dcache_bsize;
> -
> - /* number of performance monitor counters */
> - unsigned int num_pmcs;
> -
> - /* this is called to initialize various CPU bits like L1 cache,
> - * BHT, SPD, etc... from head.S before branching to
> identify_machine
> - */
> - cpu_setup_t cpu_setup;
> -
> - /* Used by oprofile userspace to select the right counters */
> - char *oprofile_cpu_type;
> -
> - /* Processor specific oprofile operations */
> - struct op_ppc64_model *oprofile_model;
> -};
> -
> -extern struct cpu_spec cpu_specs[];
> -extern struct cpu_spec *cur_cpu_spec;
> -
> -static inline unsigned long cpu_has_feature(unsigned long feature)
> -{
> - return cur_cpu_spec->cpu_features & feature;
> -}
> -
> -#endif /* __ASSEMBLY__ */
> -
> -/* CPU kernel features */
> -
> -/* Retain the 32b definitions for the time being - use bottom half
> of word */
> -#define CPU_FTR_SPLIT_ID_CACHE ASM_CONST(0x0000000000000001)
> -#define CPU_FTR_L2CR ASM_CONST(0x0000000000000002)
> -#define CPU_FTR_SPEC7450 ASM_CONST(0x0000000000000004)
> -#define CPU_FTR_ALTIVEC ASM_CONST(0x0000000000000008)
> -#define CPU_FTR_TAU ASM_CONST(0x0000000000000010)
> -#define CPU_FTR_CAN_DOZE ASM_CONST(0x0000000000000020)
> -#define CPU_FTR_USE_TB ASM_CONST(0x0000000000000040)
> -#define CPU_FTR_604_PERF_MON ASM_CONST(0x0000000000000080)
> -#define CPU_FTR_601 ASM_CONST(0x0000000000000100)
> -#define CPU_FTR_HPTE_TABLE ASM_CONST(0x0000000000000200)
> -#define CPU_FTR_CAN_NAP ASM_CONST(0x0000000000000400)
> -#define CPU_FTR_L3CR ASM_CONST(0x0000000000000800)
> -#define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x0000000000001000)
> -#define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x0000000000002000)
> -#define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x0000000000004000)
> -
> -/* Add the 64b processor unique features in the top half of the
> word */
> -#define CPU_FTR_SLB ASM_CONST(0x0000000100000000)
> -#define CPU_FTR_16M_PAGE ASM_CONST(0x0000000200000000)
> -#define CPU_FTR_TLBIEL ASM_CONST(0x0000000400000000)
> -#define CPU_FTR_NOEXECUTE ASM_CONST(0x0000000800000000)
> -#define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000001000000000)
> -#define CPU_FTR_IABR ASM_CONST(0x0000002000000000)
> -#define CPU_FTR_MMCRA ASM_CONST(0x0000004000000000)
> -/* unused ASM_CONST(0x0000008000000000) */
> -#define CPU_FTR_SMT ASM_CONST(0x0000010000000000)
> -#define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x0000020000000000)
> -#define CPU_FTR_LOCKLESS_TLBIE ASM_CONST(0x0000040000000000)
> -#define CPU_FTR_MMCRA_SIHV ASM_CONST(0x0000080000000000)
> -#define CPU_FTR_CTRL ASM_CONST(0x0000100000000000)
> -
> -#ifndef __ASSEMBLY__
> -
> -#define COMMON_USER_PPC64 (PPC_FEATURE_32 | PPC_FEATURE_64 | \
> - PPC_FEATURE_HAS_FPU | PPC_FEATURE_HAS_MMU)
> -
> -#define CPU_FTR_PPCAS_ARCH_V2_BASE (CPU_FTR_SLB | \
> - CPU_FTR_TLBIEL |
> CPU_FTR_NOEXECUTE | \
> - CPU_FTR_NODSISRALIGN | CPU_FTR_CTRL)
> -
> -/* iSeries doesn't support large pages */
> -#ifdef CONFIG_PPC_ISERIES
> -#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_PPCAS_ARCH_V2_BASE)
> -#else
> -#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_PPCAS_ARCH_V2_BASE |
> CPU_FTR_16M_PAGE)
> -#endif /* CONFIG_PPC_ISERIES */
> -
> -#endif /* __ASSEMBLY */
> -
> -#ifdef __ASSEMBLY__
> -
> -#define BEGIN_FTR_SECTION 98:
> -
> -#define END_FTR_SECTION(msk, val) \
> -99: \
> - .section __ftr_fixup,"a"; \
> - .align 3; \
> - .llong msk; \
> - .llong val; \
> - .llong 98b; \
> - .llong 99b; \
> - .previous
> -
> -#else
> -
> -#define BEGIN_FTR_SECTION "98:\n"
> -#define END_FTR_SECTION(msk, val) \
> -"99:\n" \
> -" .section __ftr_fixup,\"a\";\n" \
> -" .align 3;\n" \
> -" .llong "#msk";\n" \
> -" .llong "#val";\n" \
> -" .llong 98b;\n" \
> -" .llong 99b;\n" \
> -" .previous\n"
> -
> -#endif /* __ASSEMBLY__ */
> -
> -#define END_FTR_SECTION_IFSET(msk) END_FTR_SECTION((msk), (msk))
> -#define END_FTR_SECTION_IFCLR(msk) END_FTR_SECTION((msk), 0)
> -
> -#endif /* __ASM_PPC_CPUTABLE_H */
> -#endif /* __KERNEL__ */
> -
> Index: clean-cg/arch/ppc64/Kconfig
> ===================================================================
> --- clean-cg.orig/arch/ppc64/Kconfig
> +++ clean-cg/arch/ppc64/Kconfig
> @@ -125,6 +125,36 @@ config BPA_IIC
> bool
> default y
>
> +config CPU_POWER3
> + bool
> + default y
> + depends on (PPC_ISERIES || PPC_PSERIES) && !POWER4_ONLY
> +
> +config CPU_RS64
> + bool
> + default y
> + depends on (PPC_ISERIES || PPC_PSERIES) && !POWER4_ONLY
> +
> +config CPU_POWER4
> + bool
> + default y
> + depends on PPC_ISERIES || PPC_PSERIES
> +
> +config CPU_PPC970
> + bool
> + default y
> + depends on PPC_PSERIES || PPC_PMAC || PPC_MAPLE
> +
> +config CPU_POWER5
> + bool
> + default y
> + depends on PPC_PSERIES
> +
> +config CPU_CELL
> + bool
> + default y
> + depends on PPC_BPA
> +
> # VMX is pSeries only for now until somebody writes the iSeries
> # exception vectors for it
> config ALTIVEC
> Index: clean-cg/arch/ppc64/kernel/cputable.c
> ===================================================================
> --- clean-cg.orig/arch/ppc64/kernel/cputable.c
> +++ clean-cg/arch/ppc64/kernel/cputable.c
> @@ -37,26 +37,13 @@ extern void __setup_cpu_power4(unsigned
> extern void __setup_cpu_ppc970(unsigned long offset, struct
> cpu_spec* spec);
> extern void __setup_cpu_be(unsigned long offset, struct cpu_spec*
> spec);
>
> -
> -/* We only set the altivec features if the kernel was compiled
> with altivec
> - * support
> - */
> -#ifdef CONFIG_ALTIVEC
> -#define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC
> -#define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
> -#else
> -#define CPU_FTR_ALTIVEC_COMP 0
> -#define PPC_FEATURE_HAS_ALTIVEC_COMP 0
> -#endif
> -
> struct cpu_spec cpu_specs[] = {
> { /* Power3 */
> .pvr_mask = 0xffff0000,
> .pvr_value = 0x00400000,
> .cpu_name = "POWER3 (630)",
> - .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
> - CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR,
> - .cpu_user_features = COMMON_USER_PPC64,
> + .cpu_features = CPU_FTR_POWER3,
> + .cpu_user_features = COMMON_USER_PPC64,
> .icache_bsize = 128,
> .dcache_bsize = 128,
> .num_pmcs = 8,
> @@ -70,8 +57,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffff0000,
> .pvr_value = 0x00410000,
> .cpu_name = "POWER3 (630+)",
> - .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
> - CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR,
> + .cpu_features = CPU_FTR_POWER3,
> .cpu_user_features = COMMON_USER_PPC64,
> .icache_bsize = 128,
> .dcache_bsize = 128,
> @@ -86,9 +72,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffff0000,
> .pvr_value = 0x00330000,
> .cpu_name = "RS64-II (northstar)",
> - .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
> - CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
> - CPU_FTR_MMCRA | CPU_FTR_CTRL,
> + .cpu_features = CPU_FTR_RS64,
> .cpu_user_features = COMMON_USER_PPC64,
> .icache_bsize = 128,
> .dcache_bsize = 128,
> @@ -103,9 +87,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffff0000,
> .pvr_value = 0x00340000,
> .cpu_name = "RS64-III (pulsar)",
> - .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
> - CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
> - CPU_FTR_MMCRA | CPU_FTR_CTRL,
> + .cpu_features = CPU_FTR_RS64,
> .cpu_user_features = COMMON_USER_PPC64,
> .icache_bsize = 128,
> .dcache_bsize = 128,
> @@ -120,9 +102,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffff0000,
> .pvr_value = 0x00360000,
> .cpu_name = "RS64-III (icestar)",
> - .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
> - CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
> - CPU_FTR_MMCRA | CPU_FTR_CTRL,
> + .cpu_features = CPU_FTR_RS64,
> .cpu_user_features = COMMON_USER_PPC64,
> .icache_bsize = 128,
> .dcache_bsize = 128,
> @@ -137,9 +117,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffff0000,
> .pvr_value = 0x00370000,
> .cpu_name = "RS64-IV (sstar)",
> - .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
> - CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
> - CPU_FTR_MMCRA | CPU_FTR_CTRL,
> + .cpu_features = CPU_FTR_RS64,
> .cpu_user_features = COMMON_USER_PPC64,
> .icache_bsize = 128,
> .dcache_bsize = 128,
> @@ -154,9 +132,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffff0000,
> .pvr_value = 0x00350000,
> .cpu_name = "POWER4 (gp)",
> - .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
> - CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
> - CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_MMCRA,
> + .cpu_features = CPU_FTR_POWER4,
> .cpu_user_features = COMMON_USER_PPC64,
> .icache_bsize = 128,
> .dcache_bsize = 128,
> @@ -171,9 +147,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffff0000,
> .pvr_value = 0x00380000,
> .cpu_name = "POWER4+ (gq)",
> - .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
> - CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
> - CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_MMCRA,
> + .cpu_features = CPU_FTR_POWER4,
> .cpu_user_features = COMMON_USER_PPC64,
> .icache_bsize = 128,
> .dcache_bsize = 128,
> @@ -188,10 +162,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffff0000,
> .pvr_value = 0x00390000,
> .cpu_name = "PPC970",
> - .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
> - CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
> - CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP |
> - CPU_FTR_CAN_NAP | CPU_FTR_MMCRA,
> + .cpu_features = CPU_FTR_PPC970,
> .cpu_user_features = COMMON_USER_PPC64 |
> PPC_FEATURE_HAS_ALTIVEC_COMP,
> .icache_bsize = 128,
> @@ -207,10 +178,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffff0000,
> .pvr_value = 0x003c0000,
> .cpu_name = "PPC970FX",
> - .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
> - CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
> - CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP |
> - CPU_FTR_CAN_NAP | CPU_FTR_MMCRA,
> + .cpu_features = CPU_FTR_PPC970,
> .cpu_user_features = COMMON_USER_PPC64 |
> PPC_FEATURE_HAS_ALTIVEC_COMP,
> .icache_bsize = 128,
> @@ -226,10 +194,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffff0000,
> .pvr_value = 0x00440000,
> .cpu_name = "PPC970MP",
> - .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
> - CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
> - CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP |
> - CPU_FTR_CAN_NAP | CPU_FTR_MMCRA,
> + .cpu_features = CPU_FTR_PPC970,
> .cpu_user_features = COMMON_USER_PPC64 |
> PPC_FEATURE_HAS_ALTIVEC_COMP,
> .icache_bsize = 128,
> @@ -244,11 +209,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffff0000,
> .pvr_value = 0x003a0000,
> .cpu_name = "POWER5 (gr)",
> - .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
> - CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
> - CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_MMCRA | CPU_FTR_SMT |
> - CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE |
> - CPU_FTR_MMCRA_SIHV,
> + .cpu_features = CPU_FTR_POWER5,
> .cpu_user_features = COMMON_USER_PPC64,
> .icache_bsize = 128,
> .dcache_bsize = 128,
> @@ -263,11 +224,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffff0000,
> .pvr_value = 0x003b0000,
> .cpu_name = "POWER5 (gs)",
> - .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
> - CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
> - CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_MMCRA | CPU_FTR_SMT |
> - CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE |
> - CPU_FTR_MMCRA_SIHV,
> + .cpu_features = CPU_FTR_POWER5,
> .cpu_user_features = COMMON_USER_PPC64,
> .icache_bsize = 128,
> .dcache_bsize = 128,
> @@ -281,11 +238,8 @@ struct cpu_spec cpu_specs[] = {
> { /* BE DD1.x */
> .pvr_mask = 0xffff0000,
> .pvr_value = 0x00700000,
> - .cpu_name = "Broadband Engine",
> - .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
> - CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
> - CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP |
> - CPU_FTR_SMT,
> + .cpu_name = "Cell Broadband Engine",
> + .cpu_features = CPU_FTR_CELL,
> .cpu_user_features = COMMON_USER_PPC64 |
> PPC_FEATURE_HAS_ALTIVEC_COMP,
> .icache_bsize = 128,
> @@ -296,9 +250,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0x00000000,
> .pvr_value = 0x00000000,
> .cpu_name = "POWER4 (compatible)",
> - .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
> - CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
> - CPU_FTR_PPCAS_ARCH_V2,
> + .cpu_features = CPU_FTR_COMPATIBLE,
> .cpu_user_features = COMMON_USER_PPC64,
> .icache_bsize = 128,
> .dcache_bsize = 128,
> Index: clean-cg/arch/ppc/kernel/cputable.c
> ===================================================================
> --- clean-cg.orig/arch/ppc/kernel/cputable.c
> +++ clean-cg/arch/ppc/kernel/cputable.c
> @@ -42,17 +42,6 @@ extern void __setup_cpu_generic(unsigned
> #define COMMON_PPC (PPC_FEATURE_32 | PPC_FEATURE_HAS_FPU | \
> PPC_FEATURE_HAS_MMU)
>
> -/* We only set the altivec features if the kernel was compiled
> with altivec
> - * support
> - */
> -#ifdef CONFIG_ALTIVEC
> -#define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC
> -#define PPC_FEATURE_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
> -#else
> -#define CPU_FTR_ALTIVEC_COMP 0
> -#define PPC_FEATURE_ALTIVEC_COMP 0
> -#endif
> -
> /* We only set the spe features if the kernel was compiled with
> * spe support
> */
> @@ -62,34 +51,13 @@ extern void __setup_cpu_generic(unsigned
> #define PPC_FEATURE_SPE_COMP 0
> #endif
>
> -/* We need to mark all pages as being coherent if we're SMP or we
> - * have a 74[45]x and an MPC107 host bridge.
> - */
> -#if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE)
> -#define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT
> -#else
> -#define CPU_FTR_COMMON 0
> -#endif
> -
> -/* The powersave features NAP & DOZE seems to confuse BDI when
> - debugging. So if a BDI is used, disable theses
> - */
> -#ifndef CONFIG_BDI_SWITCH
> -#define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE
> -#define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP
> -#else
> -#define CPU_FTR_MAYBE_CAN_DOZE 0
> -#define CPU_FTR_MAYBE_CAN_NAP 0
> -#endif
> -
> struct cpu_spec cpu_specs[] = {
> #if CLASSIC_PPC
> { /* 601 */
> .pvr_mask = 0xffff0000,
> .pvr_value = 0x00010000,
> .cpu_name = "601",
> - .cpu_features = CPU_FTR_COMMON | CPU_FTR_601 |
> - CPU_FTR_HPTE_TABLE,
> + .cpu_features = CPU_FTR_PPC601,
> .cpu_user_features = COMMON_PPC | PPC_FEATURE_601_INSTR |
> PPC_FEATURE_UNIFIED_CACHE,
> .icache_bsize = 32,
> @@ -100,9 +68,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffff0000,
> .pvr_value = 0x00030000,
> .cpu_name = "603",
> - .cpu_features = CPU_FTR_COMMON |
> - CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
> - CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP,
> + .cpu_features = CPU_FTR_603,
> .cpu_user_features = COMMON_PPC,
> .icache_bsize = 32,
> .dcache_bsize = 32,
> @@ -112,9 +78,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffff0000,
> .pvr_value = 0x00060000,
> .cpu_name = "603e",
> - .cpu_features = CPU_FTR_COMMON |
> - CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
> - CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP,
> + .cpu_features = CPU_FTR_603,
> .cpu_user_features = COMMON_PPC,
> .icache_bsize = 32,
> .dcache_bsize = 32,
> @@ -124,9 +88,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffff0000,
> .pvr_value = 0x00070000,
> .cpu_name = "603ev",
> - .cpu_features = CPU_FTR_COMMON |
> - CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
> - CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP,
> + .cpu_features = CPU_FTR_603,
> .cpu_user_features = COMMON_PPC,
> .icache_bsize = 32,
> .dcache_bsize = 32,
> @@ -136,9 +98,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffff0000,
> .pvr_value = 0x00040000,
> .cpu_name = "604",
> - .cpu_features = CPU_FTR_COMMON |
> - CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
> - CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE,
> + .cpu_features = CPU_FTR_604,
> .cpu_user_features = COMMON_PPC,
> .icache_bsize = 32,
> .dcache_bsize = 32,
> @@ -149,9 +109,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xfffff000,
> .pvr_value = 0x00090000,
> .cpu_name = "604e",
> - .cpu_features = CPU_FTR_COMMON |
> - CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
> - CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE,
> + .cpu_features = CPU_FTR_604,
> .cpu_user_features = COMMON_PPC,
> .icache_bsize = 32,
> .dcache_bsize = 32,
> @@ -162,9 +120,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffff0000,
> .pvr_value = 0x00090000,
> .cpu_name = "604r",
> - .cpu_features = CPU_FTR_COMMON |
> - CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
> - CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE,
> + .cpu_features = CPU_FTR_604,
> .cpu_user_features = COMMON_PPC,
> .icache_bsize = 32,
> .dcache_bsize = 32,
> @@ -175,9 +131,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffff0000,
> .pvr_value = 0x000a0000,
> .cpu_name = "604ev",
> - .cpu_features = CPU_FTR_COMMON |
> - CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
> - CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE,
> + .cpu_features = CPU_FTR_604,
> .cpu_user_features = COMMON_PPC,
> .icache_bsize = 32,
> .dcache_bsize = 32,
> @@ -188,10 +142,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffffffff,
> .pvr_value = 0x00084202,
> .cpu_name = "740/750",
> - .cpu_features = CPU_FTR_COMMON |
> - CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
> - CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_HPTE_TABLE |
> - CPU_FTR_MAYBE_CAN_NAP,
> + .cpu_features = CPU_FTR_740_NOTAU,
> .cpu_user_features = COMMON_PPC,
> .icache_bsize = 32,
> .dcache_bsize = 32,
> @@ -202,10 +153,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xfffffff0,
> .pvr_value = 0x00080100,
> .cpu_name = "750CX",
> - .cpu_features = CPU_FTR_COMMON |
> - CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
> - CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
> - CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
> + .cpu_features = CPU_FTR_750,
> .cpu_user_features = COMMON_PPC,
> .icache_bsize = 32,
> .dcache_bsize = 32,
> @@ -216,10 +164,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xfffffff0,
> .pvr_value = 0x00082200,
> .cpu_name = "750CX",
> - .cpu_features = CPU_FTR_COMMON |
> - CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
> - CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
> - CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
> + .cpu_features = CPU_FTR_750,
> .cpu_user_features = COMMON_PPC,
> .icache_bsize = 32,
> .dcache_bsize = 32,
> @@ -230,10 +175,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xfffffff0,
> .pvr_value = 0x00082210,
> .cpu_name = "750CXe",
> - .cpu_features = CPU_FTR_COMMON |
> - CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
> - CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
> - CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
> + .cpu_features = CPU_FTR_750,
> .cpu_user_features = COMMON_PPC,
> .icache_bsize = 32,
> .dcache_bsize = 32,
> @@ -244,10 +186,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffffffff,
> .pvr_value = 0x00083214,
> .cpu_name = "750CXe",
> - .cpu_features = CPU_FTR_COMMON |
> - CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
> - CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
> - CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
> + .cpu_features = CPU_FTR_750,
> .cpu_user_features = COMMON_PPC,
> .icache_bsize = 32,
> .dcache_bsize = 32,
> @@ -258,10 +197,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xfffff000,
> .pvr_value = 0x00083000,
> .cpu_name = "745/755",
> - .cpu_features = CPU_FTR_COMMON |
> - CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
> - CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
> - CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
> + .cpu_features = CPU_FTR_750,
> .cpu_user_features = COMMON_PPC,
> .icache_bsize = 32,
> .dcache_bsize = 32,
> @@ -272,11 +208,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffffff00,
> .pvr_value = 0x70000100,
> .cpu_name = "750FX",
> - .cpu_features = CPU_FTR_COMMON |
> - CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
> - CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
> - CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
> - CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM,
> + .cpu_features = CPU_FTR_750FX1,
> .cpu_user_features = COMMON_PPC,
> .icache_bsize = 32,
> .dcache_bsize = 32,
> @@ -287,11 +219,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffffffff,
> .pvr_value = 0x70000200,
> .cpu_name = "750FX",
> - .cpu_features = CPU_FTR_COMMON |
> - CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
> - CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
> - CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
> - CPU_FTR_NO_DPM,
> + .cpu_features = CPU_FTR_750FX2,
> .cpu_user_features = COMMON_PPC,
> .icache_bsize = 32,
> .dcache_bsize = 32,
> @@ -302,11 +230,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffff0000,
> .pvr_value = 0x70000000,
> .cpu_name = "750FX",
> - .cpu_features = CPU_FTR_COMMON |
> - CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
> - CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
> - CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
> - CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS,
> + .cpu_features = CPU_FTR_750FX,
> .cpu_user_features = COMMON_PPC,
> .icache_bsize = 32,
> .dcache_bsize = 32,
> @@ -317,11 +241,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffff0000,
> .pvr_value = 0x70020000,
> .cpu_name = "750GX",
> - .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
> - CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
> - CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE |
> - CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_DUAL_PLL_750FX |
> - CPU_FTR_HAS_HIGH_BATS,
> + .cpu_features = CPU_FTR_750GX,
> .cpu_user_features = COMMON_PPC,
> .icache_bsize = 32,
> .dcache_bsize = 32,
> @@ -332,10 +252,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffff0000,
> .pvr_value = 0x00080000,
> .cpu_name = "740/750",
> - .cpu_features = CPU_FTR_COMMON |
> - CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
> - CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
> - CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
> + .cpu_features = CPU_FTR_740,
> .cpu_user_features = COMMON_PPC,
> .icache_bsize = 32,
> .dcache_bsize = 32,
> @@ -346,11 +263,8 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffffffff,
> .pvr_value = 0x000c1101,
> .cpu_name = "7400 (1.1)",
> - .cpu_features = CPU_FTR_COMMON |
> - CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
> - CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
> - CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
> - .cpu_user_features = COMMON_PPC |
> PPC_FEATURE_ALTIVEC_COMP,
> + .cpu_features = CPU_FTR_7400_NOTAU,
> + .cpu_user_features = COMMON_PPC |
> PPC_FEATURE_HAS_ALTIVEC_COMP,
> .icache_bsize = 32,
> .dcache_bsize = 32,
> .num_pmcs = 4,
> @@ -360,12 +274,8 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffff0000,
> .pvr_value = 0x000c0000,
> .cpu_name = "7400",
> - .cpu_features = CPU_FTR_COMMON |
> - CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
> - CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
> - CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
> - CPU_FTR_MAYBE_CAN_NAP,
> - .cpu_user_features = COMMON_PPC |
> PPC_FEATURE_ALTIVEC_COMP,
> + .cpu_features = CPU_FTR_7400,
> + .cpu_user_features = COMMON_PPC |
> PPC_FEATURE_HAS_ALTIVEC_COMP,
> .icache_bsize = 32,
> .dcache_bsize = 32,
> .num_pmcs = 4,
> @@ -375,12 +285,8 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffff0000,
> .pvr_value = 0x800c0000,
> .cpu_name = "7410",
> - .cpu_features = CPU_FTR_COMMON |
> - CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
> - CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
> - CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
> - CPU_FTR_MAYBE_CAN_NAP,
> - .cpu_user_features = COMMON_PPC |
> PPC_FEATURE_ALTIVEC_COMP,
> + .cpu_features = CPU_FTR_7400,
> + .cpu_user_features = COMMON_PPC |
> PPC_FEATURE_HAS_ALTIVEC_COMP,
> .icache_bsize = 32,
> .dcache_bsize = 32,
> .num_pmcs = 4,
> @@ -390,12 +296,8 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffffffff,
> .pvr_value = 0x80000200,
> .cpu_name = "7450",
> - .cpu_features = CPU_FTR_COMMON |
> - CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
> - CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
> - CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
> - CPU_FTR_NEED_COHERENT,
> - .cpu_user_features = COMMON_PPC |
> PPC_FEATURE_ALTIVEC_COMP,
> + .cpu_features = CPU_FTR_7450_20,
> + .cpu_user_features = COMMON_PPC |
> PPC_FEATURE_HAS_ALTIVEC_COMP,
> .icache_bsize = 32,
> .dcache_bsize = 32,
> .num_pmcs = 6,
> @@ -405,14 +307,8 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffffffff,
> .pvr_value = 0x80000201,
> .cpu_name = "7450",
> - .cpu_features = CPU_FTR_COMMON |
> - CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
> - CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
> - CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
> - CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
> - CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP |
> - CPU_FTR_NEED_COHERENT,
> - .cpu_user_features = COMMON_PPC |
> PPC_FEATURE_ALTIVEC_COMP,
> + .cpu_features = CPU_FTR_7450_21,
> + .cpu_user_features = COMMON_PPC |
> PPC_FEATURE_HAS_ALTIVEC_COMP,
> .icache_bsize = 32,
> .dcache_bsize = 32,
> .num_pmcs = 6,
> @@ -422,13 +318,8 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffff0000,
> .pvr_value = 0x80000000,
> .cpu_name = "7450",
> - .cpu_features = CPU_FTR_COMMON |
> - CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
> - CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
> - CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
> - CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
> - CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT,
> - .cpu_user_features = COMMON_PPC |
> PPC_FEATURE_ALTIVEC_COMP,
> + .cpu_features = CPU_FTR_7450_23,
> + .cpu_user_features = COMMON_PPC |
> PPC_FEATURE_HAS_ALTIVEC_COMP,
> .icache_bsize = 32,
> .dcache_bsize = 32,
> .num_pmcs = 6,
> @@ -438,12 +329,8 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffffff00,
> .pvr_value = 0x80010100,
> .cpu_name = "7455",
> - .cpu_features = CPU_FTR_COMMON |
> - CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
> - CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
> - CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
> - CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT,
> - .cpu_user_features = COMMON_PPC |
> PPC_FEATURE_ALTIVEC_COMP,
> + .cpu_features = CPU_FTR_7455_1,
> + .cpu_user_features = COMMON_PPC |
> PPC_FEATURE_HAS_ALTIVEC_COMP,
> .icache_bsize = 32,
> .dcache_bsize = 32,
> .num_pmcs = 6,
> @@ -453,14 +340,8 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffffffff,
> .pvr_value = 0x80010200,
> .cpu_name = "7455",
> - .cpu_features = CPU_FTR_COMMON |
> - CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
> - CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
> - CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
> - CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
> - CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP |
> - CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS,
> - .cpu_user_features = COMMON_PPC |
> PPC_FEATURE_ALTIVEC_COMP,
> + .cpu_features = CPU_FTR_7455_20,
> + .cpu_user_features = COMMON_PPC |
> PPC_FEATURE_HAS_ALTIVEC_COMP,
> .icache_bsize = 32,
> .dcache_bsize = 32,
> .num_pmcs = 6,
> @@ -470,14 +351,8 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffff0000,
> .pvr_value = 0x80010000,
> .cpu_name = "7455",
> - .cpu_features = CPU_FTR_COMMON |
> - CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
> - CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
> - CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
> - CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
> - CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
> - CPU_FTR_NEED_COHERENT,
> - .cpu_user_features = COMMON_PPC |
> PPC_FEATURE_ALTIVEC_COMP,
> + .cpu_features = CPU_FTR_7455,
> + .cpu_user_features = COMMON_PPC |
> PPC_FEATURE_HAS_ALTIVEC_COMP,
> .icache_bsize = 32,
> .dcache_bsize = 32,
> .num_pmcs = 6,
> @@ -487,14 +362,8 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffffffff,
> .pvr_value = 0x80020100,
> .cpu_name = "7447/7457",
> - .cpu_features = CPU_FTR_COMMON |
> - CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
> - CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
> - CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
> - CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
> - CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
> - CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC,
> - .cpu_user_features = COMMON_PPC |
> PPC_FEATURE_ALTIVEC_COMP,
> + .cpu_features = CPU_FTR_7447_10,
> + .cpu_user_features = COMMON_PPC |
> PPC_FEATURE_HAS_ALTIVEC_COMP,
> .icache_bsize = 32,
> .dcache_bsize = 32,
> .num_pmcs = 6,
> @@ -504,14 +373,8 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffffffff,
> .pvr_value = 0x80020101,
> .cpu_name = "7447/7457",
> - .cpu_features = CPU_FTR_COMMON |
> - CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
> - CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
> - CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
> - CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
> - CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
> - CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC,
> - .cpu_user_features = COMMON_PPC |
> PPC_FEATURE_ALTIVEC_COMP,
> + .cpu_features = CPU_FTR_7447_10,
> + .cpu_user_features = COMMON_PPC |
> PPC_FEATURE_HAS_ALTIVEC_COMP,
> .icache_bsize = 32,
> .dcache_bsize = 32,
> .num_pmcs = 6,
> @@ -521,14 +384,8 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffff0000,
> .pvr_value = 0x80020000,
> .cpu_name = "7447/7457",
> - .cpu_features = CPU_FTR_COMMON |
> - CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
> - CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
> - CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
> - CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
> - CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
> - CPU_FTR_NEED_COHERENT,
> - .cpu_user_features = COMMON_PPC |
> PPC_FEATURE_ALTIVEC_COMP,
> + .cpu_features = CPU_FTR_7447,
> + .cpu_user_features = COMMON_PPC |
> PPC_FEATURE_HAS_ALTIVEC_COMP,
> .icache_bsize = 32,
> .dcache_bsize = 32,
> .num_pmcs = 6,
> @@ -538,13 +395,8 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffff0000,
> .pvr_value = 0x80030000,
> .cpu_name = "7447A",
> - .cpu_features = CPU_FTR_COMMON |
> - CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
> - CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
> - CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
> - CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
> - CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT,
> - .cpu_user_features = COMMON_PPC |
> PPC_FEATURE_ALTIVEC_COMP,
> + .cpu_features = CPU_FTR_7447A,
> + .cpu_user_features = COMMON_PPC |
> PPC_FEATURE_HAS_ALTIVEC_COMP,
> .icache_bsize = 32,
> .dcache_bsize = 32,
> .num_pmcs = 6,
> @@ -554,13 +406,8 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffff0000,
> .pvr_value = 0x80040000,
> .cpu_name = "7448",
> - .cpu_features = CPU_FTR_COMMON |
> - CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
> - CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
> - CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
> - CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
> - CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT,
> - .cpu_user_features = COMMON_PPC |
> PPC_FEATURE_ALTIVEC_COMP,
> + .cpu_features = CPU_FTR_7447A,
> + .cpu_user_features = COMMON_PPC |
> PPC_FEATURE_HAS_ALTIVEC_COMP,
> .icache_bsize = 32,
> .dcache_bsize = 32,
> .num_pmcs = 6,
> @@ -570,9 +417,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0x7fff0000,
> .pvr_value = 0x00810000,
> .cpu_name = "82xx",
> - .cpu_features = CPU_FTR_COMMON |
> - CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
> - CPU_FTR_USE_TB,
> + .cpu_features = CPU_FTR_82XX,
> .cpu_user_features = COMMON_PPC,
> .icache_bsize = 32,
> .dcache_bsize = 32,
> @@ -582,9 +427,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0x7fff0000,
> .pvr_value = 0x00820000,
> .cpu_name = "G2_LE",
> - .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
> - CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
> - CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS,
> + .cpu_features = CPU_FTR_G2_LE,
> .cpu_user_features = COMMON_PPC,
> .icache_bsize = 32,
> .dcache_bsize = 32,
> @@ -594,9 +437,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0x7fff0000,
> .pvr_value = 0x00830000,
> .cpu_name = "e300",
> - .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
> - CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
> - CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS,
> + .cpu_features = CPU_FTR_E300,
> .cpu_user_features = COMMON_PPC,
> .icache_bsize = 32,
> .dcache_bsize = 32,
> @@ -606,9 +447,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0x00000000,
> .pvr_value = 0x00000000,
> .cpu_name = "(generic PPC)",
> - .cpu_features = CPU_FTR_COMMON |
> - CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
> - CPU_FTR_HPTE_TABLE,
> + .cpu_features = CPU_FTR_CLASSIC32,
> .cpu_user_features = COMMON_PPC,
> .icache_bsize = 32,
> .dcache_bsize = 32,
> @@ -620,9 +459,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffff0000,
> .pvr_value = 0x00400000,
> .cpu_name = "Power3 (630)",
> - .cpu_features = CPU_FTR_COMMON |
> - CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
> - CPU_FTR_HPTE_TABLE,
> + .cpu_features = CPU_FTR_POWER3_32,
> .cpu_user_features = COMMON_PPC | PPC_FEATURE_64,
> .icache_bsize = 128,
> .dcache_bsize = 128,
> @@ -633,9 +470,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffff0000,
> .pvr_value = 0x00410000,
> .cpu_name = "Power3 (630+)",
> - .cpu_features = CPU_FTR_COMMON |
> - CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
> - CPU_FTR_HPTE_TABLE,
> + .cpu_features = CPU_FTR_POWER3_32,
> .cpu_user_features = COMMON_PPC | PPC_FEATURE_64,
> .icache_bsize = 128,
> .dcache_bsize = 128,
> @@ -646,9 +481,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffff0000,
> .pvr_value = 0x00360000,
> .cpu_name = "I-star",
> - .cpu_features = CPU_FTR_COMMON |
> - CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
> - CPU_FTR_HPTE_TABLE,
> + .cpu_features = CPU_FTR_POWER3_32,
> .cpu_user_features = COMMON_PPC | PPC_FEATURE_64,
> .icache_bsize = 128,
> .dcache_bsize = 128,
> @@ -659,55 +492,19 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffff0000,
> .pvr_value = 0x00370000,
> .cpu_name = "S-star",
> - .cpu_features = CPU_FTR_COMMON |
> - CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
> - CPU_FTR_HPTE_TABLE,
> + .cpu_features = CPU_FTR_POWER3_32,
> .cpu_user_features = COMMON_PPC | PPC_FEATURE_64,
> .icache_bsize = 128,
> .dcache_bsize = 128,
> .num_pmcs = 8,
> .cpu_setup = __setup_cpu_power3
> },
> -#endif /* CONFIG_PPC64BRIDGE */
> -#ifdef CONFIG_POWER4
> - { /* Power4 */
> - .pvr_mask = 0xffff0000,
> - .pvr_value = 0x00350000,
> - .cpu_name = "Power4",
> - .cpu_features = CPU_FTR_COMMON |
> - CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
> - CPU_FTR_HPTE_TABLE,
> - .cpu_user_features = COMMON_PPC | PPC_FEATURE_64,
> - .icache_bsize = 128,
> - .dcache_bsize = 128,
> - .num_pmcs = 8,
> - .cpu_setup = __setup_cpu_power4
> - },
> - { /* PPC970 */
> - .pvr_mask = 0xffff0000,
> - .pvr_value = 0x00390000,
> - .cpu_name = "PPC970",
> - .cpu_features = CPU_FTR_COMMON |
> - CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
> - CPU_FTR_HPTE_TABLE |
> - CPU_FTR_ALTIVEC_COMP | CPU_FTR_MAYBE_CAN_NAP,
> - .cpu_user_features = COMMON_PPC | PPC_FEATURE_64 |
> - PPC_FEATURE_ALTIVEC_COMP,
> - .icache_bsize = 128,
> - .dcache_bsize = 128,
> - .num_pmcs = 8,
> - .cpu_setup = __setup_cpu_ppc970
> - },
> { /* PPC970FX */
> .pvr_mask = 0xffff0000,
> .pvr_value = 0x003c0000,
> .cpu_name = "PPC970FX",
> - .cpu_features = CPU_FTR_COMMON |
> - CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
> - CPU_FTR_HPTE_TABLE |
> - CPU_FTR_ALTIVEC_COMP | CPU_FTR_MAYBE_CAN_NAP,
> - .cpu_user_features = COMMON_PPC | PPC_FEATURE_64 |
> - PPC_FEATURE_ALTIVEC_COMP,
> + .cpu_features = CPU_FTR_970_32,
> + .cpu_user_features = COMMON_PPC | PPC_FEATURE_64 |
> PPC_FEATURE_HAS_ALTIVEC_COMP,
> .icache_bsize = 128,
> .dcache_bsize = 128,
> .num_pmcs = 8,
> @@ -721,8 +518,7 @@ struct cpu_spec cpu_specs[] = {
> .cpu_name = "8xx",
> /* CPU_FTR_MAYBE_CAN_DOZE is possible,
> * if the 8xx code is there.... */
> - .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
> - CPU_FTR_USE_TB,
> + .cpu_features = CPU_FTR_8XX,
> .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
> .icache_bsize = 16,
> .dcache_bsize = 16,
> @@ -733,8 +529,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffffff00,
> .pvr_value = 0x00200200,
> .cpu_name = "403GC",
> - .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
> - CPU_FTR_USE_TB,
> + .cpu_features = CPU_FTR_40X,
> .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
> .icache_bsize = 16,
> .dcache_bsize = 16,
> @@ -743,8 +538,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffffff00,
> .pvr_value = 0x00201400,
> .cpu_name = "403GCX",
> - .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
> - CPU_FTR_USE_TB,
> + .cpu_features = CPU_FTR_40X,
> .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
> .icache_bsize = 16,
> .dcache_bsize = 16,
> @@ -753,8 +547,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffff0000,
> .pvr_value = 0x00200000,
> .cpu_name = "403G ??",
> - .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
> - CPU_FTR_USE_TB,
> + .cpu_features = CPU_FTR_40X,
> .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
> .icache_bsize = 16,
> .dcache_bsize = 16,
> @@ -763,8 +556,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffff0000,
> .pvr_value = 0x40110000,
> .cpu_name = "405GP",
> - .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
> - CPU_FTR_USE_TB,
> + .cpu_features = CPU_FTR_40X,
> .cpu_user_features = PPC_FEATURE_32 |
> PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
> .icache_bsize = 32,
> @@ -774,8 +566,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffff0000,
> .pvr_value = 0x40130000,
> .cpu_name = "STB03xxx",
> - .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
> - CPU_FTR_USE_TB,
> + .cpu_features = CPU_FTR_40X,
> .cpu_user_features = PPC_FEATURE_32 |
> PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
> .icache_bsize = 32,
> @@ -785,8 +576,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffff0000,
> .pvr_value = 0x41810000,
> .cpu_name = "STB04xxx",
> - .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
> - CPU_FTR_USE_TB,
> + .cpu_features = CPU_FTR_40X,
> .cpu_user_features = PPC_FEATURE_32 |
> PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
> .icache_bsize = 32,
> @@ -796,8 +586,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffff0000,
> .pvr_value = 0x41610000,
> .cpu_name = "NP405L",
> - .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
> - CPU_FTR_USE_TB,
> + .cpu_features = CPU_FTR_40X,
> .cpu_user_features = PPC_FEATURE_32 |
> PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
> .icache_bsize = 32,
> @@ -807,8 +596,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffff0000,
> .pvr_value = 0x40B10000,
> .cpu_name = "NP4GS3",
> - .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
> - CPU_FTR_USE_TB,
> + .cpu_features = CPU_FTR_40X,
> .cpu_user_features = PPC_FEATURE_32 |
> PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
> .icache_bsize = 32,
> @@ -818,8 +606,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffff0000,
> .pvr_value = 0x41410000,
> .cpu_name = "NP405H",
> - .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
> - CPU_FTR_USE_TB,
> + .cpu_features = CPU_FTR_40X,
> .cpu_user_features = PPC_FEATURE_32 |
> PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
> .icache_bsize = 32,
> @@ -829,8 +616,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffff0000,
> .pvr_value = 0x50910000,
> .cpu_name = "405GPr",
> - .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
> - CPU_FTR_USE_TB,
> + .cpu_features = CPU_FTR_40X,
> .cpu_user_features = PPC_FEATURE_32 |
> PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
> .icache_bsize = 32,
> @@ -840,8 +626,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffff0000,
> .pvr_value = 0x51510000,
> .cpu_name = "STBx25xx",
> - .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
> - CPU_FTR_USE_TB,
> + .cpu_features = CPU_FTR_40X,
> .cpu_user_features = PPC_FEATURE_32 |
> PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
> .icache_bsize = 32,
> @@ -851,8 +636,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffff0000,
> .pvr_value = 0x41F10000,
> .cpu_name = "405LP",
> - .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
> - CPU_FTR_USE_TB,
> + .cpu_features = CPU_FTR_40X,
> .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
> .icache_bsize = 32,
> .dcache_bsize = 32,
> @@ -861,8 +645,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffff0000,
> .pvr_value = 0x20010000,
> .cpu_name = "Virtex-II Pro",
> - .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
> - CPU_FTR_USE_TB,
> + .cpu_features = CPU_FTR_40X,
> .cpu_user_features = PPC_FEATURE_32 |
> PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
> .icache_bsize = 32,
> @@ -872,8 +655,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffff0000,
> .pvr_value = 0x51210000,
> .cpu_name = "405EP",
> - .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
> - CPU_FTR_USE_TB,
> + .cpu_features = CPU_FTR_40X,
> .cpu_user_features = PPC_FEATURE_32 |
> PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
> .icache_bsize = 32,
> @@ -886,8 +668,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xf0000fff,
> .pvr_value = 0x40000850,
> .cpu_name = "440EP Rev. A",
> - .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
> - CPU_FTR_USE_TB,
> + .cpu_features = CPU_FTR_44X,
> .cpu_user_features = COMMON_PPC, /* 440EP has an FPU */
> .icache_bsize = 32,
> .dcache_bsize = 32,
> @@ -896,8 +677,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xf0000fff,
> .pvr_value = 0x400008d3,
> .cpu_name = "440EP Rev. B",
> - .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
> - CPU_FTR_USE_TB,
> + .cpu_features = CPU_FTR_44X,
> .cpu_user_features = COMMON_PPC, /* 440EP has an FPU */
> .icache_bsize = 32,
> .dcache_bsize = 32,
> @@ -906,8 +686,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xf0000fff,
> .pvr_value = 0x40000440,
> .cpu_name = "440GP Rev. B",
> - .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
> - CPU_FTR_USE_TB,
> + .cpu_features = CPU_FTR_44X,
> .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
> .icache_bsize = 32,
> .dcache_bsize = 32,
> @@ -916,8 +695,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xf0000fff,
> .pvr_value = 0x40000481,
> .cpu_name = "440GP Rev. C",
> - .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
> - CPU_FTR_USE_TB,
> + .cpu_features = CPU_FTR_44X,
> .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
> .icache_bsize = 32,
> .dcache_bsize = 32,
> @@ -926,8 +704,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xf0000fff,
> .pvr_value = 0x50000850,
> .cpu_name = "440GX Rev. A",
> - .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
> - CPU_FTR_USE_TB,
> + .cpu_features = CPU_FTR_44X,
> .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
> .icache_bsize = 32,
> .dcache_bsize = 32,
> @@ -936,8 +713,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xf0000fff,
> .pvr_value = 0x50000851,
> .cpu_name = "440GX Rev. B",
> - .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
> - CPU_FTR_USE_TB,
> + .cpu_features = CPU_FTR_44X,
> .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
> .icache_bsize = 32,
> .dcache_bsize = 32,
> @@ -946,8 +722,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xf0000fff,
> .pvr_value = 0x50000892,
> .cpu_name = "440GX Rev. C",
> - .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
> - CPU_FTR_USE_TB,
> + .cpu_features = CPU_FTR_44X,
> .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
> .icache_bsize = 32,
> .dcache_bsize = 32,
> @@ -956,8 +731,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xf0000fff,
> .pvr_value = 0x50000894,
> .cpu_name = "440GX Rev. F",
> - .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
> - CPU_FTR_USE_TB,
> + .cpu_features = CPU_FTR_44X,
> .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
> .icache_bsize = 32,
> .dcache_bsize = 32,
> @@ -966,8 +740,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xff000fff,
> .pvr_value = 0x53000891,
> .cpu_name = "440SP Rev. A",
> - .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
> - CPU_FTR_USE_TB,
> + .cpu_features = CPU_FTR_44X,
> .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
> .icache_bsize = 32,
> .dcache_bsize = 32,
> @@ -979,7 +752,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_value = 0x81000000,
> .cpu_name = "e200z5",
> /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
> - .cpu_features = CPU_FTR_USE_TB,
> + .cpu_features = CPU_FTR_E200,
> .cpu_user_features = PPC_FEATURE_32 |
> PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_EFP_SINGLE |
> PPC_FEATURE_UNIFIED_CACHE,
> @@ -990,7 +763,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_value = 0x81100000,
> .cpu_name = "e200z6",
> /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
> - .cpu_features = CPU_FTR_USE_TB,
> + .cpu_features = CPU_FTR_E200,
> .cpu_user_features = PPC_FEATURE_32 |
> PPC_FEATURE_HAS_MMU | PPC_FEATURE_SPE_COMP |
> PPC_FEATURE_HAS_EFP_SINGLE |
> @@ -1002,8 +775,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_value = 0x80200000,
> .cpu_name = "e500",
> /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
> - .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
> - CPU_FTR_USE_TB,
> + .cpu_features = CPU_FTR_E500,
> .cpu_user_features = PPC_FEATURE_32 |
> PPC_FEATURE_HAS_MMU | PPC_FEATURE_SPE_COMP |
> PPC_FEATURE_HAS_EFP_SINGLE,
> @@ -1016,8 +788,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_value = 0x80210000,
> .cpu_name = "e500v2",
> /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
> - .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
> - CPU_FTR_USE_TB | CPU_FTR_BIG_PHYS,
> + .cpu_features = CPU_FTR_E500_2,
> .cpu_user_features = PPC_FEATURE_32 |
> PPC_FEATURE_HAS_MMU | PPC_FEATURE_SPE_COMP |
> PPC_FEATURE_HAS_EFP_SINGLE | PPC_FEATURE_HAS_EFP_DOUBLE,
> @@ -1031,7 +802,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0x00000000,
> .pvr_value = 0x00000000,
> .cpu_name = "(generic PPC)",
> - .cpu_features = CPU_FTR_COMMON,
> + .cpu_features = CPU_FTR_GENERIC_32,
> .cpu_user_features = PPC_FEATURE_32,
> .icache_bsize = 32,
> .dcache_bsize = 32,
> Index: clean-cg/include/asm-powerpc/cputable.h
> ===================================================================
> --- /dev/null
> +++ clean-cg/include/asm-powerpc/cputable.h
> @@ -0,0 +1,475 @@
> +#ifndef __ASM_POWERPC_CPUTABLE_H
> +#define __ASM_POWERPC_CPUTABLE_H
> +
> +#ifdef __KERNEL__
> +#include <linux/config.h>
> +#include <asm/ppc_asm.h> /* for ASM_CONST */
> +
> +#define PPC_FEATURE_32 0x80000000
> +#define PPC_FEATURE_64 0x40000000
> +#define PPC_FEATURE_601_INSTR 0x20000000
> +#define PPC_FEATURE_HAS_ALTIVEC 0x10000000
> +#define PPC_FEATURE_HAS_FPU 0x08000000
> +#define PPC_FEATURE_HAS_MMU 0x04000000
> +#define PPC_FEATURE_HAS_4xxMAC 0x02000000
> +#define PPC_FEATURE_UNIFIED_CACHE 0x01000000
> +#define PPC_FEATURE_HAS_SPE 0x00800000
> +#define PPC_FEATURE_HAS_EFP_SINGLE 0x00400000
> +#define PPC_FEATURE_HAS_EFP_DOUBLE 0x00200000
> +
> +#ifndef __ASSEMBLY__
> +
> +/* This structure can grow, it's real size is used by head.S code
> + * via the mkdefs mechanism.
> + */
> +struct cpu_spec;
> +struct op_ppc64_model;
> +
> +#ifndef __powerpc64__
> +typedef void (*cpu_setup_t)(unsigned long offset, int cpu_nr,
> struct cpu_spec* spec);
> +#else /* __powerpc64__ */
> +typedef void (*cpu_setup_t)(unsigned long offset, struct
> cpu_spec* spec);
> +#endif /* __powerpc64__ */
> +
> +struct cpu_spec {
> + /* CPU is matched via (PVR & pvr_mask) == pvr_value */
> + unsigned int pvr_mask;
> + unsigned int pvr_value;
> +
> + char *cpu_name;
> + unsigned long cpu_features; /* Kernel features */
> + unsigned int cpu_user_features; /* Userland features */
> +
> + /* cache line sizes */
> + unsigned int icache_bsize;
> + unsigned int dcache_bsize;
> +
> + /* number of performance monitor counters */
> + unsigned int num_pmcs;
> +
> + /* this is called to initialize various CPU bits like L1 cache,
> + * BHT, SPD, etc... from head.S before branching to
> identify_machine
> + */
> + cpu_setup_t cpu_setup;
> +#ifdef __powerpc64__
> +
> + /* Used by oprofile userspace to select the right counters */
> + char *oprofile_cpu_type;
> +
> + /* Processor specific oprofile operations */
> + struct op_ppc64_model *oprofile_model;
> +#endif /* __powerpc64__ */
> +};
> +
> +extern struct cpu_spec cpu_specs[];
> +
> +#ifndef __powerpc64__
> +extern struct cpu_spec *cur_cpu_spec[];
> +#else /* __powerpc64__ */
> +extern struct cpu_spec *cur_cpu_spec;
> +#endif /* __powerpc64__ */
> +
> +#endif /* __ASSEMBLY__ */
> +
> +/* CPU kernel features */
> +
> +/* Retain the 32b definitions all use bottom half of word */
> +#define CPU_FTR_SPLIT_ID_CACHE ASM_CONST(0x0000000000000001)
> +#define CPU_FTR_L2CR ASM_CONST(0x0000000000000002)
> +#define CPU_FTR_SPEC7450 ASM_CONST(0x0000000000000004)
> +#define CPU_FTR_ALTIVEC ASM_CONST(0x0000000000000008)
> +#define CPU_FTR_TAU ASM_CONST(0x0000000000000010)
> +#define CPU_FTR_CAN_DOZE ASM_CONST(0x0000000000000020)
> +#define CPU_FTR_USE_TB ASM_CONST(0x0000000000000040)
> +#define CPU_FTR_604_PERF_MON ASM_CONST(0x0000000000000080)
> +#define CPU_FTR_601 ASM_CONST(0x0000000000000100)
> +#define CPU_FTR_HPTE_TABLE ASM_CONST(0x0000000000000200)
> +#define CPU_FTR_CAN_NAP ASM_CONST(0x0000000000000400)
> +#define CPU_FTR_L3CR ASM_CONST(0x0000000000000800)
> +#define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x0000000000001000)
> +#define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x0000000000002000)
> +#define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x0000000000004000)
> +#define CPU_FTR_NO_DPM ASM_CONST(0x0000000000008000)
> +#define CPU_FTR_HAS_HIGH_BATS ASM_CONST(0x0000000000010000)
> +#define CPU_FTR_NEED_COHERENT ASM_CONST(0x0000000000020000)
> +#define CPU_FTR_NO_BTIC ASM_CONST(0x0000000000040000)
> +#define CPU_FTR_BIG_PHYS ASM_CONST(0x0000000000080000)
> +
> +#ifdef __powerpc64__
> +/* Add the 64b processor unique features in the top half of the
> word */
> +#define CPU_FTR_SLB ASM_CONST(0x0000000100000000)
> +#define CPU_FTR_16M_PAGE ASM_CONST(0x0000000200000000)
> +#define CPU_FTR_TLBIEL ASM_CONST(0x0000000400000000)
> +#define CPU_FTR_NOEXECUTE ASM_CONST(0x0000000800000000)
> +#define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000001000000000)
> +#define CPU_FTR_IABR ASM_CONST(0x0000002000000000)
> +#define CPU_FTR_MMCRA ASM_CONST(0x0000004000000000)
> +/* unused ASM_CONST(0x0000008000000000) */
> +#define CPU_FTR_SMT ASM_CONST(0x0000010000000000)
> +#define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x0000020000000000)
> +#define CPU_FTR_LOCKLESS_TLBIE ASM_CONST(0x0000040000000000)
> +#define CPU_FTR_MMCRA_SIHV ASM_CONST(0x0000080000000000)
> +#define CPU_FTR_CTRL ASM_CONST(0x0000100000000000)
> +#endif
> +
> +#ifndef __ASSEMBLY__
> +
> +#define COMMON_USER_PPC64 (PPC_FEATURE_32 | PPC_FEATURE_64 | \
> + PPC_FEATURE_HAS_FPU | PPC_FEATURE_HAS_MMU)
> +
> +#define CPU_FTR_PPCAS_ARCH_V2_BASE (CPU_FTR_SLB | \
> + CPU_FTR_TLBIEL | CPU_FTR_NOEXECUTE | \
> + CPU_FTR_NODSISRALIGN | CPU_FTR_CTRL)
> +
> +/* iSeries doesn't support large pages */
> +#ifdef CONFIG_PPC_ISERIES
> +#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_PPCAS_ARCH_V2_BASE)
> +#else
> +#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_PPCAS_ARCH_V2_BASE |
> CPU_FTR_16M_PAGE)
> +#endif /* CONFIG_PPC_ISERIES */
> +
> +/* We only set the altivec features if the kernel was compiled
> with altivec
> + * support
> + */
> +#ifdef CONFIG_ALTIVEC
> +#define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC
> +#define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
> +#else
> +#define CPU_FTR_ALTIVEC_COMP 0
> +#define PPC_FEATURE_HAS_ALTIVEC_COMP 0
> +#endif
> +
> +/* We need to mark all pages as being coherent if we're SMP or we
> + * have a 74[45]x and an MPC107 host bridge.
> + */
> +#if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE)
> +#define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT
> +#else
> +#define CPU_FTR_COMMON 0
> +#endif
> +
> +/* The powersave features NAP & DOZE seems to confuse BDI when
> + debugging. So if a BDI is used, disable theses
> + */
> +#ifndef CONFIG_BDI_SWITCH
> +#define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE
> +#define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP
> +#else
> +#define CPU_FTR_MAYBE_CAN_DOZE 0
> +#define CPU_FTR_MAYBE_CAN_NAP 0
> +#endif
> +
> +#define CLASSIC_PPC (!defined(CONFIG_8xx) && !defined(CONFIG_4xx)
> && \
> + !defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \
> + !defined(CONFIG_BOOKE))
> +
> +enum {
> + CPU_FTR_PPC601 = CPU_FTR_COMMON | CPU_FTR_601 |
> CPU_FTR_HPTE_TABLE,
> + CPU_FTR_603 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
> + CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
> + CPU_FTR_MAYBE_CAN_NAP,
> + CPU_FTR_604 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
> + CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE,
> + CPU_FTR_740_NOTAU = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
> + CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
> + CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
> + CPU_FTR_740 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
> + CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
> + CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
> + CPU_FTR_750 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
> + CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
> + CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
> + CPU_FTR_750FX1 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
> + CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
> + CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
> + CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM,
> + CPU_FTR_750FX2 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
> + CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
> + CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
> + CPU_FTR_NO_DPM,
> + CPU_FTR_750FX = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
> + CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
> + CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
> + CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS,
> + CPU_FTR_750GX = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
> + CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
> + CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
> + CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS,
> + CPU_FTR_7400_NOTAU = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
> + CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
> + CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
> + CPU_FTR_MAYBE_CAN_NAP,
> + CPU_FTR_7400 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
> + CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
> + CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
> + CPU_FTR_MAYBE_CAN_NAP,
> + CPU_FTR_7450_20 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
> + CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
> + CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
> + CPU_FTR_NEED_COHERENT,
> + CPU_FTR_7450_21 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
> + CPU_FTR_USE_TB |
> + CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
> + CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
> + CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP |
> + CPU_FTR_NEED_COHERENT,
> + CPU_FTR_7450_23 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
> + CPU_FTR_USE_TB |
> + CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
> + CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
> + CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT,
> + CPU_FTR_7455_1 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
> + CPU_FTR_USE_TB |
> + CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
> + CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
> CPU_FTR_HAS_HIGH_BATS |
> + CPU_FTR_NEED_COHERENT,
> + CPU_FTR_7455_20 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
> + CPU_FTR_USE_TB |
> + CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
> + CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
> + CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP |
> + CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS,
> + CPU_FTR_7455 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
> + CPU_FTR_USE_TB |
> + CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
> + CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
> + CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
> + CPU_FTR_NEED_COHERENT,
> + CPU_FTR_7447_10 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
> + CPU_FTR_USE_TB |
> + CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
> + CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
> + CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
> + CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC,
> + CPU_FTR_7447 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
> + CPU_FTR_USE_TB |
> + CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
> + CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
> + CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
> + CPU_FTR_NEED_COHERENT,
> + CPU_FTR_7447A = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
> + CPU_FTR_USE_TB |
> + CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
> + CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
> + CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
> + CPU_FTR_NEED_COHERENT,
> + CPU_FTR_82XX = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
> + CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB,
> + CPU_FTR_G2_LE = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
> + CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP |
> CPU_FTR_HAS_HIGH_BATS,
> + CPU_FTR_E300 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
> + CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP |
> CPU_FTR_HAS_HIGH_BATS,
> + CPU_FTR_CLASSIC32 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
> + CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
> + CPU_FTR_POWER3_32 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
> + CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
> + CPU_FTR_POWER4_32 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
> + CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
> + CPU_FTR_970_32 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
> + CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_ALTIVEC_COMP |
> + CPU_FTR_MAYBE_CAN_NAP,
> + CPU_FTR_8XX = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
> + CPU_FTR_40X = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
> + CPU_FTR_44X = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
> + CPU_FTR_E200 = CPU_FTR_USE_TB,
> + CPU_FTR_E500 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
> + CPU_FTR_E500_2 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
> + CPU_FTR_BIG_PHYS,
> + CPU_FTR_GENERIC_32 = CPU_FTR_COMMON,
> +#ifdef __powerpc64__
> + CPU_FTR_POWER3 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
> + CPU_FTR_HPTE_TABLE | CPU_FTR_IABR,
> + CPU_FTR_RS64 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
> + CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
> + CPU_FTR_MMCRA | CPU_FTR_CTRL,
> + CPU_FTR_POWER4 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
> + CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_MMCRA,
> + CPU_FTR_PPC970 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
> + CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 |
> + CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA,
> + CPU_FTR_POWER5 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
> + CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 |
> + CPU_FTR_MMCRA | CPU_FTR_SMT |
> + CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE |
> + CPU_FTR_MMCRA_SIHV,
> + CPU_FTR_CELL = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
> + CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 |
> + CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT,
> + CPU_FTR_COMPATIBLE = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
> + CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2,
> +#endif
> + CPU_FTR_POSSIBLE =
> +#if CLASSIC_PPC
> + CPU_FTR_601 | CPU_FTR_603 | CPU_FTR_604 | CPU_FTR_740_NOTAU |
> + CPU_FTR_740 | CPU_FTR_750 | CPU_FTR_750FX1 |
> + CPU_FTR_750FX2 | CPU_FTR_750FX | CPU_FTR_750GX |
> + CPU_FTR_7400_NOTAU | CPU_FTR_7400 | CPU_FTR_7450_20 |
> + CPU_FTR_7450_21 | CPU_FTR_7450_23 | CPU_FTR_7455_1 |
> + CPU_FTR_7455_20 | CPU_FTR_7455 | CPU_FTR_7447_10 |
> + CPU_FTR_7447 | CPU_FTR_7447A | CPU_FTR_82XX |
> + CPU_FTR_G2_LE | CPU_FTR_E300 | CPU_FTR_CLASSIC32 |
> +#else
> + CPU_FTR_GENERIC_32 |
> +#endif
> +#ifdef CONFIG_PPC64BRIDGE
> + CPU_FTR_POWER3_32 |
> +#endif
> +#ifdef CONFIG_POWER4
> + CPU_FTR_POWER4_32 | CPU_FTR_970_32 |
> +#endif
> +#ifdef CONFIG_8xx
> + CPU_FTR_8XX |
> +#endif
> +#ifdef CONFIG_40x
> + CPU_FTR_40X |
> +#endif
> +#ifdef CONFIG_44x
> + CPU_FTR_44X |
> +#endif
> +#ifdef CONFIG_FSL_BOOKE
> + CPU_FTR_E200 | CPU_FTR_E500 | CPU_FTR_E500_2 |
> +#endif
> +#ifdef CONFIG_CPU_POWER3
> + CPU_FTR_POWER3 |
> +#endif
> +#ifdef CONFIG_CPU_RS64
> + CPU_FTR_RS64 |
> +#endif
> +#ifdef CONFIG_CPU_POWER4
> + CPU_FTR_POWER4 |
> +#endif
> +#ifdef CONFIG_CPU_PPC970
> + CPU_FTR_PPC970 |
> +#endif
> +#ifdef CONFIG_CPU_POWER5
> + CPU_FTR_POWER5 |
> +#endif
> +#ifdef CONFIG_CPU_CELL
> + CPU_FTR_CELL |
> +#endif
> + 0,
> + CPU_FTR_ALWAYS =
> +#if CLASSIC_PPC
> + CPU_FTR_601 & CPU_FTR_603 & CPU_FTR_604 & CPU_FTR_740_NOTAU &
> + CPU_FTR_740 & CPU_FTR_750 & CPU_FTR_750FX1 &
> + CPU_FTR_750FX2 & CPU_FTR_750FX & CPU_FTR_750GX &
> + CPU_FTR_7400_NOTAU & CPU_FTR_7400 & CPU_FTR_7450_20 &
> + CPU_FTR_7450_21 & CPU_FTR_7450_23 & CPU_FTR_7455_1 &
> + CPU_FTR_7455_20 & CPU_FTR_7455 & CPU_FTR_7447_10 &
> + CPU_FTR_7447 & CPU_FTR_7447A & CPU_FTR_82XX &
> + CPU_FTR_G2_LE & CPU_FTR_E300 & CPU_FTR_CLASSIC32 &
> +#else
> + CPU_FTR_GENERIC_32 &
> +#endif
> +#ifdef CONFIG_PPC64BRIDGE
> + CPU_FTR_POWER3_32 &
> +#endif
> +#ifdef CONFIG_POWER4
> + CPU_FTR_POWER4_32 & CPU_FTR_970_32 &
> +#endif
> +#ifdef CONFIG_8xx
> + CPU_FTR_8XX &
> +#endif
> +#ifdef CONFIG_40x
> + CPU_FTR_40X &
> +#endif
> +#ifdef CONFIG_44x
> + CPU_FTR_44X &
> +#endif
> +#ifdef CONFIG_FSL_BOOKE
> + CPU_FTR_E200 & CPU_FTR_E500 & CPU_FTR_E500_2 &
> +#endif
> +#ifdef CONFIG_CPU_POWER3
> + CPU_FTR_POWER3 &
> +#endif
> +#ifdef CONFIG_CPU_RS64
> + CPU_FTR_RS64 &
> +#endif
> +#ifdef CONFIG_CPU_POWER4
> + CPU_FTR_POWER4 &
> +#endif
> +#ifdef CONFIG_CPU_PPC970
> + CPU_FTR_PPC970 &
> +#endif
> +#ifdef CONFIG_CPU_POWER5
> + CPU_FTR_POWER5 &
> +#endif
> +#ifdef CONFIG_CPU_CELL
> + CPU_FTR_CELL &
> +#endif
> + CPU_FTR_POSSIBLE,
> +};
> +
> +static inline int cpu_has_feature(unsigned long feature)
> +{
> + return (CPU_FTR_ALWAYS & feature) ||
> + (CPU_FTR_POSSIBLE
> +#ifndef __powerpc64__
> + & cur_cpu_spec[0]->cpu_features
> +#else
> + & cur_cpu_spec->cpu_features
> +#endif
> + & feature);
> +}
> +
> +#endif /* __ASSEMBLY */
> +
> +#ifdef __ASSEMBLY__
> +
> +#define BEGIN_FTR_SECTION 98:
> +
> +#ifndef __powerpc64__
> +#define END_FTR_SECTION(msk, val) \
> +99: \
> + .section __ftr_fixup,"a"; \
> + .align 2; \
> + .long msk; \
> + .long val; \
> + .long 98b; \
> + .long 99b; \
> + .previous
> +#else /* __powerpc64__ */
> +#define END_FTR_SECTION(msk, val) \
> +99: \
> + .section __ftr_fixup,"a"; \
> + .align 3; \
> + .llong msk; \
> + .llong val; \
> + .llong 98b; \
> + .llong 99b; \
> + .previous
> +#endif /* __powerpc64__ */
> +
> +#else
> +
> +#define BEGIN_FTR_SECTION "98:\n"
> +
> +#ifndef __powerpc64__
> +#define END_FTR_SECTION(msk, val) \
> +"99:\n" \
> +" .section __ftr_fixup,\"a\";\n" \
> +" .align 2;\n" \
> +" .long "#msk";\n" \
> +" .long "#val";\n" \
> +" .long 98b;\n" \
> +" .long 99b;\n" \
> +" .previous\n"
> +#else /* __powerpc64__ */
> +#define END_FTR_SECTION(msk, val) \
> +"99:\n" \
> +" .section __ftr_fixup,\"a\";\n" \
> +" .align 3;\n" \
> +" .llong "#msk";\n" \
> +" .llong "#val";\n" \
> +" .llong 98b;\n" \
> +" .llong 99b;\n" \
> +" .previous\n"
> +#endif /* __powerpc64__ */
> +
> +#endif /* __ASSEMBLY__ */
> +
> +#define END_FTR_SECTION_IFSET(msk) END_FTR_SECTION((msk), (msk))
> +#define END_FTR_SECTION_IFCLR(msk) END_FTR_SECTION((msk), 0)
> +
> +#endif /* __KERNEL__ */
> +#endif /* __ASM_POWERPC_CPUTABLE_H */
> Index: clean-cg/include/asm-ppc/cputable.h
> ===================================================================
> --- clean-cg.orig/include/asm-ppc/cputable.h
> +++ /dev/null
> @@ -1,128 +0,0 @@
> -/*
> - * include/asm-ppc/cputable.h
> - *
> - * Copyright (C) 2001 Ben. Herrenschmidt (benh@kernel.crashing.org)
> - *
> - * This program is free software; you can redistribute it and/or
> - * modify it under the terms of the GNU General Public License
> - * as published by the Free Software Foundation; either version
> - * 2 of the License, or (at your option) any later version.
> - */
> -
> -#ifndef __ASM_PPC_CPUTABLE_H
> -#define __ASM_PPC_CPUTABLE_H
> -
> -/* Exposed to userland CPU features */
> -#define PPC_FEATURE_32 0x80000000
> -#define PPC_FEATURE_64 0x40000000
> -#define PPC_FEATURE_601_INSTR 0x20000000
> -#define PPC_FEATURE_HAS_ALTIVEC 0x10000000
> -#define PPC_FEATURE_HAS_FPU 0x08000000
> -#define PPC_FEATURE_HAS_MMU 0x04000000
> -#define PPC_FEATURE_HAS_4xxMAC 0x02000000
> -#define PPC_FEATURE_UNIFIED_CACHE 0x01000000
> -#define PPC_FEATURE_HAS_SPE 0x00800000
> -#define PPC_FEATURE_HAS_EFP_SINGLE 0x00400000
> -#define PPC_FEATURE_HAS_EFP_DOUBLE 0x00200000
> -
> -#ifdef __KERNEL__
> -
> -#ifndef __ASSEMBLY__
> -
> -/* This structure can grow, it's real size is used by head.S code
> - * via the mkdefs mecanism.
> - */
> -struct cpu_spec;
> -
> -typedef void (*cpu_setup_t)(unsigned long offset, int cpu_nr,
> struct cpu_spec* spec);
> -
> -struct cpu_spec {
> - /* CPU is matched via (PVR & pvr_mask) == pvr_value */
> - unsigned int pvr_mask;
> - unsigned int pvr_value;
> -
> - char *cpu_name;
> - unsigned int cpu_features; /* Kernel features */
> - unsigned int cpu_user_features; /* Userland features */
> -
> - /* cache line sizes */
> - unsigned int icache_bsize;
> - unsigned int dcache_bsize;
> -
> - /* number of performance monitor counters */
> - unsigned int num_pmcs;
> -
> - /* this is called to initialize various CPU bits like L1 cache,
> - * BHT, SPD, etc... from head.S before branching to
> identify_machine
> - */
> - cpu_setup_t cpu_setup;
> -};
> -
> -extern struct cpu_spec cpu_specs[];
> -extern struct cpu_spec *cur_cpu_spec[];
> -
> -static inline unsigned int cpu_has_feature(unsigned int feature)
> -{
> - return cur_cpu_spec[0]->cpu_features & feature;
> -}
> -
> -#endif /* __ASSEMBLY__ */
> -
> -/* CPU kernel features */
> -#define CPU_FTR_SPLIT_ID_CACHE 0x00000001
> -#define CPU_FTR_L2CR 0x00000002
> -#define CPU_FTR_SPEC7450 0x00000004
> -#define CPU_FTR_ALTIVEC 0x00000008
> -#define CPU_FTR_TAU 0x00000010
> -#define CPU_FTR_CAN_DOZE 0x00000020
> -#define CPU_FTR_USE_TB 0x00000040
> -#define CPU_FTR_604_PERF_MON 0x00000080
> -#define CPU_FTR_601 0x00000100
> -#define CPU_FTR_HPTE_TABLE 0x00000200
> -#define CPU_FTR_CAN_NAP 0x00000400
> -#define CPU_FTR_L3CR 0x00000800
> -#define CPU_FTR_L3_DISABLE_NAP 0x00001000
> -#define CPU_FTR_NAP_DISABLE_L2_PR 0x00002000
> -#define CPU_FTR_DUAL_PLL_750FX 0x00004000
> -#define CPU_FTR_NO_DPM 0x00008000
> -#define CPU_FTR_HAS_HIGH_BATS 0x00010000
> -#define CPU_FTR_NEED_COHERENT 0x00020000
> -#define CPU_FTR_NO_BTIC 0x00040000
> -#define CPU_FTR_BIG_PHYS 0x00080000
> -
> -#ifdef __ASSEMBLY__
> -
> -#define BEGIN_FTR_SECTION 98:
> -
> -#define END_FTR_SECTION(msk, val) \
> -99: \
> - .section __ftr_fixup,"a"; \
> - .align 2; \
> - .long msk; \
> - .long val; \
> - .long 98b; \
> - .long 99b; \
> - .previous
> -
> -#else
> -
> -#define BEGIN_FTR_SECTION "98:\n"
> -#define END_FTR_SECTION(msk, val) \
> -"99:\n" \
> -" .section __ftr_fixup,\"a\";\n" \
> -" .align 2;\n" \
> -" .long "#msk";\n" \
> -" .long "#val";\n" \
> -" .long 98b;\n" \
> -" .long 99b;\n" \
> -" .previous\n"
> -
> -
> -#endif /* __ASSEMBLY__ */
> -
> -#define END_FTR_SECTION_IFSET(msk) END_FTR_SECTION((msk), (msk))
> -#define END_FTR_SECTION_IFCLR(msk) END_FTR_SECTION((msk), 0)
> -
> -#endif /* __ASM_PPC_CPUTABLE_H */
> -#endif /* __KERNEL__ */
> -
>
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