* Re: [PATCH] MPC8xx PCMCIA driver
From: Marcelo Tosatti @ 2005-09-14 18:21 UTC (permalink / raw)
To: Dominik Brodowski, Jeff Garzik, linux-ppc-embedded, linux-kernel
Cc: Magnus Damm
In-Reply-To: <20050914142746.GA14742@isilmar.linta.de>
Here is an uptodated version of the MPC8xx PCMCIA driver for v2.6,
addressing comments by Jeff and Dominik:
- use IO accessors instead of direct device memory referencing
- avoid usage of non-standard "uint/uchar" data types
- kill struct typedef's
Will submit it for inclusion once v2.6.14 is out.
Testing on 8xx platforms is more than welcome! Works like a charm
on our custom hardware (CONFIG_PRxK).
diff --git a/drivers/pcmcia/Kconfig b/drivers/pcmcia/Kconfig
--- a/drivers/pcmcia/Kconfig
+++ b/drivers/pcmcia/Kconfig
@@ -154,6 +154,16 @@ config TCIC
"Bridge" is the name used for the hardware inside your computer that
PCMCIA cards are plugged into. If unsure, say N.
+config PCMCIA_M8XX
+ tristate "MPC8xx PCMCIA support"
+ depends on PCMCIA && PPC
+ select PCCARD_NONSTATIC
+ help
+ Say Y here to include support for PowerPC 8xx series PCMCIA
+ controller.
+
+ This driver is also available as a module called m8xx_pcmcia.
+
config HD64465_PCMCIA
tristate "HD64465 host bridge support"
depends on HD64465 && PCMCIA
diff --git a/drivers/pcmcia/Makefile b/drivers/pcmcia/Makefile
--- a/drivers/pcmcia/Makefile
+++ b/drivers/pcmcia/Makefile
@@ -25,6 +25,7 @@ obj-$(CONFIG_PD6729) += pd6729.o
obj-$(CONFIG_I82365) += i82365.o
obj-$(CONFIG_I82092) += i82092.o
obj-$(CONFIG_TCIC) += tcic.o
+obj-$(CONFIG_PCMCIA_M8XX) += m8xx_pcmcia.o
obj-$(CONFIG_HD64465_PCMCIA) += hd64465_ss.o
obj-$(CONFIG_PCMCIA_SA1100) += sa11xx_core.o sa1100_cs.o
obj-$(CONFIG_PCMCIA_SA1111) += sa11xx_core.o sa1111_cs.o
diff --git a/drivers/pcmcia/m8xx_pcmcia.c b/drivers/pcmcia/m8xx_pcmcia.c
new file mode 100644
--- /dev/null
+++ b/drivers/pcmcia/m8xx_pcmcia.c
@@ -0,0 +1,1290 @@
+/*
+ * m8xx_pcmcia.c - Linux PCMCIA socket driver for the mpc8xx series.
+ *
+ * (C) 1999-2000 Magnus Damm <damm@bitsmart.com>
+ * (C) 2001-2002 Montavista Software, Inc.
+ * <mlocke@mvista.com>
+ *
+ * Support for two slots by Cyclades Corporation
+ * <oliver.kurth@cyclades.de>
+ * Further fixes, v2.6 kernel port
+ * <marcelo.tosatti@cyclades.com>
+ *
+ * "The ExCA standard specifies that socket controllers should provide
+ * two IO and five memory windows per socket, which can be independently
+ * configured and positioned in the host address space and mapped to
+ * arbitrary segments of card address space. " - David A Hinds. 1999
+ *
+ * This controller does _not_ meet the ExCA standard.
+ *
+ * m8xx pcmcia controller brief info:
+ * + 8 windows (attrib, mem, i/o)
+ * + up to two slots (SLOT_A and SLOT_B)
+ * + inputpins, outputpins, event and mask registers.
+ * - no offset register. sigh.
+ *
+ * Because of the lacking offset register we must map the whole card.
+ * We assign each memory window PCMCIA_MEM_WIN_SIZE address space.
+ * Make sure there is (PCMCIA_MEM_WIN_SIZE * PCMCIA_MEM_WIN_NO
+ * * PCMCIA_SOCKETS_NO) bytes at PCMCIA_MEM_WIN_BASE.
+ * The i/o windows are dynamically allocated at PCMCIA_IO_WIN_BASE.
+ * They are maximum 64KByte each...
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/fcntl.h>
+#include <linux/string.h>
+
+#include <asm/io.h>
+#include <asm/bitops.h>
+#include <asm/segment.h>
+#include <asm/system.h>
+
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/sched.h>
+#include <linux/slab.h>
+#include <linux/timer.h>
+#include <linux/ioport.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+
+#include <asm/mpc8xx.h>
+#include <asm/8xx_immap.h>
+#include <asm/irq.h>
+
+#include <pcmcia/version.h>
+#include <pcmcia/cs_types.h>
+#include <pcmcia/cs.h>
+#include <pcmcia/ss.h>
+
+#ifdef PCMCIA_DEBUG
+static int pc_debug = PCMCIA_DEBUG;
+module_param(pc_debug, int, 0);
+#define dprintk(args...) printk(KERN_DEBUG "m8xx_pcmcia: " args);
+#else
+#define dprintk(args...)
+#endif
+
+#define pcmcia_info(args...) printk(KERN_INFO "m8xx_pcmcia: "args)
+#define pcmcia_error(args...) printk(KERN_ERR "m8xx_pcmcia: "args)
+
+static const char *version = "Version 0.06, Aug 2005";
+MODULE_LICENSE("Dual MPL/GPL");
+
+#if !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B)
+
+/* The RPX series use SLOT_B */
+#if defined(CONFIG_RPXCLASSIC) || defined(CONFIG_RPXLITE)
+#define CONFIG_PCMCIA_SLOT_B
+#define CONFIG_BD_IS_MHZ
+#endif
+
+/* The ADS board use SLOT_A */
+#ifdef CONFIG_ADS
+#define CONFIG_PCMCIA_SLOT_A
+#define CONFIG_BD_IS_MHZ
+#endif
+
+/* The FADS series are a mess */
+#ifdef CONFIG_FADS
+#if defined(CONFIG_MPC860T) || defined(CONFIG_MPC860) || defined(CONFIG_MPC821)
+#define CONFIG_PCMCIA_SLOT_A
+#else
+#define CONFIG_PCMCIA_SLOT_B
+#endif
+#endif
+
+/* Cyclades ACS uses both slots */
+#ifdef CONFIG_PRxK
+#define CONFIG_PCMCIA_SLOT_A
+#define CONFIG_PCMCIA_SLOT_B
+#endif
+
+#endif /* !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B) */
+
+#if defined(CONFIG_PCMCIA_SLOT_A) && defined(CONFIG_PCMCIA_SLOT_B)
+
+#define PCMCIA_SOCKETS_NO 2
+/* We have only 8 windows, dualsocket support will be limited. */
+#define PCMCIA_MEM_WIN_NO 2
+#define PCMCIA_IO_WIN_NO 2
+#define PCMCIA_SLOT_MSG "SLOT_A and SLOT_B"
+
+#elif defined(CONFIG_PCMCIA_SLOT_A) || defined(CONFIG_PCMCIA_SLOT_B)
+
+#define PCMCIA_SOCKETS_NO 1
+/* full support for one slot */
+#define PCMCIA_MEM_WIN_NO 5
+#define PCMCIA_IO_WIN_NO 2
+
+/* define _slot_ to be able to optimize macros */
+
+#ifdef CONFIG_PCMCIA_SLOT_A
+#define _slot_ 0
+#define PCMCIA_SLOT_MSG "SLOT_A"
+#else
+#define _slot_ 1
+#define PCMCIA_SLOT_MSG "SLOT_B"
+#endif
+
+#else
+#error m8xx_pcmcia: Bad configuration!
+#endif
+
+/* ------------------------------------------------------------------------- */
+
+#define PCMCIA_MEM_WIN_BASE 0xe0000000 /* base address for memory window 0 */
+#define PCMCIA_MEM_WIN_SIZE 0x04000000 /* each memory window is 64 MByte */
+#define PCMCIA_IO_WIN_BASE _IO_BASE /* base address for io window 0 */
+
+#define PCMCIA_SCHLVL PCMCIA_INTERRUPT /* Status Change Interrupt Level */
+
+/* ------------------------------------------------------------------------- */
+
+/* 2.4.x and newer has this always in HZ */
+#define M8XX_BUSFREQ ((((bd_t *)&(__res))->bi_busfreq))
+
+static int pcmcia_schlvl = PCMCIA_SCHLVL;
+
+static spinlock_t events_lock = SPIN_LOCK_UNLOCKED;
+
+
+#define PCMCIA_SOCKET_KEY_5V 1
+#define PCMCIA_SOCKET_KEY_LV 2
+
+/* look up table for pgcrx registers */
+static u32 *m8xx_pgcrx[2] = {
+ &((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pgcra,
+ &((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pgcrb
+};
+
+/*
+ * This structure is used to address each window in the PCMCIA controller.
+ *
+ * Keep in mind that we assume that pcmcia_win[n+1] is mapped directly
+ * after pcmcia_win[n]...
+ */
+
+struct pcmcia_win {
+ u32 br;
+ u32 or;
+};
+
+/*
+ * For some reason the hardware guys decided to make both slots share
+ * some registers.
+ *
+ * Could someone invent object oriented hardware ?
+ *
+ * The macros are used to get the right bit from the registers.
+ * SLOT_A : slot = 0
+ * SLOT_B : slot = 1
+ */
+
+#define M8XX_PCMCIA_VS1(slot) (0x80000000 >> (slot << 4))
+#define M8XX_PCMCIA_VS2(slot) (0x40000000 >> (slot << 4))
+#define M8XX_PCMCIA_VS_MASK(slot) (0xc0000000 >> (slot << 4))
+#define M8XX_PCMCIA_VS_SHIFT(slot) (30 - (slot << 4))
+
+#define M8XX_PCMCIA_WP(slot) (0x20000000 >> (slot << 4))
+#define M8XX_PCMCIA_CD2(slot) (0x10000000 >> (slot << 4))
+#define M8XX_PCMCIA_CD1(slot) (0x08000000 >> (slot << 4))
+#define M8XX_PCMCIA_BVD2(slot) (0x04000000 >> (slot << 4))
+#define M8XX_PCMCIA_BVD1(slot) (0x02000000 >> (slot << 4))
+#define M8XX_PCMCIA_RDY(slot) (0x01000000 >> (slot << 4))
+#define M8XX_PCMCIA_RDY_L(slot) (0x00800000 >> (slot << 4))
+#define M8XX_PCMCIA_RDY_H(slot) (0x00400000 >> (slot << 4))
+#define M8XX_PCMCIA_RDY_R(slot) (0x00200000 >> (slot << 4))
+#define M8XX_PCMCIA_RDY_F(slot) (0x00100000 >> (slot << 4))
+#define M8XX_PCMCIA_MASK(slot) (0xFFFF0000 >> (slot << 4))
+
+#define M8XX_PCMCIA_POR_VALID 0x00000001
+#define M8XX_PCMCIA_POR_WRPROT 0x00000002
+#define M8XX_PCMCIA_POR_ATTRMEM 0x00000010
+#define M8XX_PCMCIA_POR_IO 0x00000018
+#define M8XX_PCMCIA_POR_16BIT 0x00000040
+
+#define M8XX_PGCRX(slot) m8xx_pgcrx[slot]
+
+#define M8XX_PGCRX_CXOE 0x00000080
+#define M8XX_PGCRX_CXRESET 0x00000040
+
+/* we keep one lookup table per socket to check flags */
+
+#define PCMCIA_EVENTS_MAX 5 /* 4 max at a time + termination */
+
+struct event_table {
+ u32 regbit;
+ u32 eventbit;
+};
+
+struct socket_info {
+ void (*handler)(void *info, u32 events);
+ void *info;
+
+ u32 slot;
+
+ socket_state_t state;
+ struct pccard_mem_map mem_win[PCMCIA_MEM_WIN_NO];
+ struct pccard_io_map io_win[PCMCIA_IO_WIN_NO];
+ struct event_table events[PCMCIA_EVENTS_MAX];
+ struct pcmcia_socket socket;
+};
+
+static struct socket_info socket[PCMCIA_SOCKETS_NO];
+
+/*
+ * Search this table to see if the windowsize is
+ * supported...
+ */
+
+#define M8XX_SIZES_NO 32
+
+static const u32 m8xx_size_to_gray[M8XX_SIZES_NO] =
+{
+ 0x00000001, 0x00000002, 0x00000008, 0x00000004,
+ 0x00000080, 0x00000040, 0x00000010, 0x00000020,
+ 0x00008000, 0x00004000, 0x00001000, 0x00002000,
+ 0x00000100, 0x00000200, 0x00000800, 0x00000400,
+
+ 0x0fffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0x01000000, 0x02000000, 0xffffffff, 0x04000000,
+ 0x00010000, 0x00020000, 0x00080000, 0x00040000,
+ 0x00800000, 0x00400000, 0x00100000, 0x00200000
+};
+
+/* ------------------------------------------------------------------------- */
+
+static irqreturn_t m8xx_interrupt(int irq, void *dev, struct pt_regs *regs);
+
+#define PCMCIA_BMT_LIMIT (15*4) /* Bus Monitor Timeout value */
+
+/* ------------------------------------------------------------------------- */
+/* board specific stuff: */
+/* voltage_set(), hardware_enable() and hardware_disable() */
+/* ------------------------------------------------------------------------- */
+/* RPX Boards from Embedded Planet */
+
+#if defined(CONFIG_RPXCLASSIC) || defined(CONFIG_RPXLITE)
+
+/* The RPX boards seems to have it's bus monitor timeout set to 6*8 clocks.
+ * SYPCR is write once only, therefore must the slowest memory be faster
+ * than the bus monitor or we will get a machine check due to the bus timeout.
+ */
+
+#define PCMCIA_BOARD_MSG "RPX CLASSIC or RPX LITE"
+
+#undef PCMCIA_BMT_LIMIT
+#define PCMCIA_BMT_LIMIT (6*8)
+
+static int voltage_set(int slot, int vcc, int vpp)
+{
+ u32 reg = 0;
+
+ switch(vcc) {
+ case 0: break;
+ case 33:
+ reg |= BCSR1_PCVCTL4;
+ break;
+ case 50:
+ reg |= BCSR1_PCVCTL5;
+ break;
+ default:
+ return 1;
+ }
+
+ switch(vpp) {
+ case 0: break;
+ case 33:
+ case 50:
+ if(vcc == vpp)
+ reg |= BCSR1_PCVCTL6;
+ else
+ return 1;
+ break;
+ case 120:
+ reg |= BCSR1_PCVCTL7;
+ default:
+ return 1;
+ }
+
+ if(!((vcc == 50) || (vcc == 0)))
+ return 1;
+
+ /* first, turn off all power */
+
+ out_be32(((u32 *)RPX_CSR_ADDR), in_be32(((u32 *)RPX_CSR_ADDR)) & ~(BCSR1_PCVCTL4 | BCSR1_PCVCTL5 | BCSR1_PCVCTL6 | BCSR1_PCVCTL7));
+
+ /* enable new powersettings */
+
+ out_be32(((u32 *)RPX_CSR_ADDR), in_be32(((u32 *)RPX_CSR_ADDR)) | reg);
+
+ return 0;
+}
+
+#define socket_get(_slot_) PCMCIA_SOCKET_KEY_5V
+#define hardware_enable(_slot_) /* No hardware to enable */
+#define hardware_disable(_slot_) /* No hardware to disable */
+
+#endif /* CONFIG_RPXCLASSIC */
+
+/* FADS Boards from Motorola */
+
+#if defined(CONFIG_FADS)
+
+#define PCMCIA_BOARD_MSG "FADS"
+
+static int voltage_set(int slot, int vcc, int vpp)
+{
+ u32 reg = 0;
+
+ switch(vcc) {
+ case 0:
+ break;
+ case 33:
+ reg |= BCSR1_PCCVCC0;
+ break;
+ case 50:
+ reg |= BCSR1_PCCVCC1;
+ break;
+ default:
+ return 1;
+ }
+
+ switch(vpp) {
+ case 0:
+ break;
+ case 33:
+ case 50:
+ if(vcc == vpp)
+ reg |= BCSR1_PCCVPP1;
+ else
+ return 1;
+ break;
+ case 120:
+ if ((vcc == 33) || (vcc == 50))
+ reg |= BCSR1_PCCVPP0;
+ else
+ return 1;
+ default:
+ return 1;
+ }
+
+ /* first, turn off all power */
+ out_be32(&((u32 *)BCSR1), in_be32(&((u32 *)BCSR1)) & ~(BCSR1_PCCVCC_MASK | BCSR1_PCCVPP_MASK));
+
+ /* enable new powersettings */
+ out_be32(&((u32 *)BCSR1), in_be32(&((u32 *)BCSR1)) | reg);
+
+ return 0;
+}
+
+#define socket_get(_slot_) PCMCIA_SOCKET_KEY_5V
+
+static void hardware_enable(int slot)
+{
+ out_be32(&((u32 *)BCSR1), in_be32(&((u32 *)BCSR1)) & ~BCSR1_PCCEN);
+}
+
+static void hardware_disable(int slot)
+{
+ out_be32(&((u32 *)BCSR1), in_be32(&((u32 *)BCSR1)) | BCSR1_PCCEN);
+}
+
+#endif
+
+/* ------------------------------------------------------------------------- */
+/* Motorola MBX860 */
+
+#if defined(CONFIG_MBX)
+
+#define PCMCIA_BOARD_MSG "MBX"
+
+static int voltage_set(int slot, int vcc, int vpp)
+{
+ u8 reg = 0;
+
+ switch(vcc) {
+ case 0:
+ break;
+ case 33:
+ reg |= CSR2_VCC_33;
+ break;
+ case 50:
+ reg |= CSR2_VCC_50;
+ break;
+ default:
+ return 1;
+ }
+
+ switch(vpp) {
+ case 0:
+ break;
+ case 33:
+ case 50:
+ if(vcc == vpp)
+ reg |= CSR2_VPP_VCC;
+ else
+ return 1;
+ break;
+ case 120:
+ if ((vcc == 33) || (vcc == 50))
+ reg |= CSR2_VPP_12;
+ else
+ return 1;
+ default:
+ return 1;
+ }
+
+ /* first, turn off all power */
+ out_8(&((u8 *)MBX_CSR2_ADDR), in_8(&((u8 *)MBX_CSR2_ADDR)) & ~(CSR2_VCC_MASK | CSR2_VPP_MASK));
+
+ /* enable new powersettings */
+ out_8(&((u8 *)MBX_CSR2_ADDR), in_8(&((u8 *)MBX_CSR2_ADDR)) | reg);
+
+ return 0;
+}
+
+#define socket_get(_slot_) PCMCIA_SOCKET_KEY_5V
+#define hardware_enable(_slot_) /* No hardware to enable */
+#define hardware_disable(_slot_) /* No hardware to disable */
+
+#endif /* CONFIG_MBX */
+
+#if defined(CONFIG_PRxK)
+#include <asm/cpld.h>
+extern volatile fpga_pc_regs *fpga_pc;
+
+#define PCMCIA_BOARD_MSG "MPC855T"
+
+static int voltage_set(int slot, int vcc, int vpp)
+{
+ u8 reg = 0;
+ u8 regread;
+ cpld_regs *ccpld = get_cpld();
+
+ switch(vcc) {
+ case 0:
+ break;
+ case 33:
+ reg |= PCMCIA_VCC_33;
+ break;
+ case 50:
+ reg |= PCMCIA_VCC_50;
+ break;
+ default:
+ return 1;
+ }
+
+ switch(vpp) {
+ case 0:
+ break;
+ case 33:
+ case 50:
+ if(vcc == vpp)
+ reg |= PCMCIA_VPP_VCC;
+ else
+ return 1;
+ break;
+ case 120:
+ if ((vcc == 33) || (vcc == 50))
+ reg |= PCMCIA_VPP_12;
+ else
+ return 1;
+ default:
+ return 1;
+ }
+
+ reg = reg >> (slot << 2);
+ regread = in_8(&ccpld->fpga_pc_ctl);
+ if (reg != (regread & ((PCMCIA_VCC_MASK | PCMCIA_VPP_MASK) >> (slot << 2)))) {
+ /* enable new powersettings */
+ regread = regread & ~((PCMCIA_VCC_MASK | PCMCIA_VPP_MASK) >> (slot << 2));
+ out_8(&ccpld->fpga_pc_ctl, reg | regread);
+ msleep(100);
+ }
+
+ return 0;
+}
+
+#define socket_get(_slot_) PCMCIA_SOCKET_KEY_LV
+#define hardware_enable(_slot_) /* No hardware to enable */
+#define hardware_disable(_slot_) /* No hardware to disable */
+
+#endif /* CONFIG_PRxK */
+
+static void m8xx_shutdown(void)
+{
+ u32 m, i;
+ struct pcmcia_win *w;
+
+ for(i = 0; i < PCMCIA_SOCKETS_NO; i++){
+ w = (void *) &((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pbr0;
+
+ out_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pscr, M8XX_PCMCIA_MASK(i));
+ out_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_per, in_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_per) & ~M8XX_PCMCIA_MASK(i));
+
+ /* turn off interrupt and disable CxOE */
+ out_be32(M8XX_PGCRX(i), M8XX_PGCRX_CXOE);
+
+ /* turn off memory windows */
+ for(m = 0; m < PCMCIA_MEM_WIN_NO; m++) {
+ out_be32(&w->or, 0); /* set to not valid */
+ w++;
+ }
+
+ /* turn off voltage */
+ voltage_set(i, 0, 0);
+
+ /* disable external hardware */
+ hardware_disable(i);
+ }
+
+ free_irq(pcmcia_schlvl, NULL);
+}
+
+/* copied from tcic.c */
+
+static int m8xx_drv_suspend(struct device *dev, pm_message_t state, u32 level)
+{
+ int ret = 0;
+ if (level == SUSPEND_SAVE_STATE)
+ ret = pcmcia_socket_dev_suspend(dev, state);
+ return ret;
+}
+
+static int m8xx_drv_resume(struct device *dev, u32 level)
+{
+ int ret = 0;
+ if (level == RESUME_RESTORE_STATE)
+ ret = pcmcia_socket_dev_resume(dev);
+ return ret;
+}
+
+static struct device_driver m8xx_driver = {
+ .name = "m8xx-pcmcia",
+ .bus = &platform_bus_type,
+ .suspend = m8xx_drv_suspend,
+ .resume = m8xx_drv_resume,
+};
+
+static struct platform_device m8xx_device = {
+ .name = "m8xx-pcmcia",
+ .id = 0,
+};
+
+static u32 pending_events[PCMCIA_SOCKETS_NO];
+static spinlock_t pending_event_lock = SPIN_LOCK_UNLOCKED;
+
+static irqreturn_t m8xx_interrupt(int irq, void *dev, struct pt_regs *regs)
+{
+ struct socket_info *s;
+ struct event_table *e;
+ unsigned int i, events, pscr, pipr, per;
+
+ dprintk("Interrupt!\n");
+ /* get interrupt sources */
+
+ pscr = in_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pscr);
+ pipr = in_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pipr);
+ per = in_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_per);
+
+ for(i = 0; i < PCMCIA_SOCKETS_NO; i++) {
+ s = &socket[i];
+ e = &s->events[0];
+ events = 0;
+
+ while(e->regbit) {
+ if(pscr & e->regbit)
+ events |= e->eventbit;
+
+ e++;
+ }
+
+ /*
+ * report only if both card detect signals are the same
+ * not too nice done,
+ * we depend on that CD2 is the bit to the left of CD1...
+ */
+ if(events & SS_DETECT)
+ if(((pipr & M8XX_PCMCIA_CD2(i)) >> 1) ^
+ (pipr & M8XX_PCMCIA_CD1(i)))
+ {
+ events &= ~SS_DETECT;
+ }
+
+#ifdef PCMCIA_GLITCHY_CD
+ /*
+ * I've experienced CD problems with my ADS board.
+ * We make an extra check to see if there was a
+ * real change of Card detection.
+ */
+
+ if((events & SS_DETECT) &&
+ ((pipr &
+ (M8XX_PCMCIA_CD2(i) | M8XX_PCMCIA_CD1(i))) == 0) &&
+ (s->state.Vcc | s->state.Vpp)) {
+ events &= ~SS_DETECT;
+ /*printk( "CD glitch workaround - CD = 0x%08x!\n",
+ (pipr & (M8XX_PCMCIA_CD2(i)
+ | M8XX_PCMCIA_CD1(i))));*/
+ }
+#endif
+
+ /* call the handler */
+
+ dprintk("slot %u: events = 0x%02x, pscr = 0x%08x, "
+ "pipr = 0x%08x\n",
+ i, events, pscr, pipr);
+
+ if(events) {
+ spin_lock(&pending_event_lock);
+ pending_events[i] |= events;
+ spin_unlock(&pending_event_lock);
+ /*
+ * Turn off RDY_L bits in the PER mask on
+ * CD interrupt receival.
+ *
+ * They can generate bad interrupts on the
+ * ACS4,8,16,32. - marcelo
+ */
+ per &= ~M8XX_PCMCIA_RDY_L(0);
+ per &= ~M8XX_PCMCIA_RDY_L(1);
+
+ out_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_per, per);
+
+ if (events)
+ pcmcia_parse_events(&socket[i].socket, events);
+ }
+ }
+
+ /* clear the interrupt sources */
+ out_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pscr, pscr);
+
+ dprintk("Interrupt done.\n");
+
+ return IRQ_HANDLED;
+}
+
+static u32 m8xx_get_graycode(u32 size)
+{
+ u32 k;
+
+ for(k = 0; k < M8XX_SIZES_NO; k++)
+ if(m8xx_size_to_gray[k] == size)
+ break;
+
+ if((k == M8XX_SIZES_NO) || (m8xx_size_to_gray[k] == -1))
+ k = -1;
+
+ return k;
+}
+
+static u32 m8xx_get_speed(u32 ns, u32 is_io)
+{
+ u32 reg, clocks, psst, psl, psht;
+
+ if(!ns) {
+
+ /*
+ * We get called with IO maps setup to 0ns
+ * if not specified by the user.
+ * They should be 255ns.
+ */
+
+ if(is_io)
+ ns = 255;
+ else
+ ns = 100; /* fast memory if 0 */
+ }
+
+ /*
+ * In PSST, PSL, PSHT fields we tell the controller
+ * timing parameters in CLKOUT clock cycles.
+ * CLKOUT is the same as GCLK2_50.
+ */
+
+/* how we want to adjust the timing - in percent */
+
+#define ADJ 180 /* 80 % longer accesstime - to be sure */
+
+ clocks = ((M8XX_BUSFREQ / 1000) * ns) / 1000;
+ clocks = (clocks * ADJ) / (100*1000);
+ if(clocks >= PCMCIA_BMT_LIMIT) {
+ printk( "Max access time limit reached\n");
+ clocks = PCMCIA_BMT_LIMIT-1;
+ }
+
+ psst = clocks / 7; /* setup time */
+ psht = clocks / 7; /* hold time */
+ psl = (clocks * 5) / 7; /* strobe length */
+
+ psst += clocks - (psst + psht + psl);
+
+ reg = psst << 12;
+ reg |= psl << 7;
+ reg |= psht << 16;
+
+ return reg;
+}
+
+static int m8xx_get_status(struct pcmcia_socket *sock, unsigned int *value)
+{
+ int lsock = container_of(sock, struct socket_info, socket)->slot;
+ struct socket_info *s = &socket[lsock];
+ unsigned int pipr, reg;
+
+ pipr = in_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pipr);
+
+ *value = ((pipr & (M8XX_PCMCIA_CD1(lsock)
+ | M8XX_PCMCIA_CD2(lsock))) == 0) ? SS_DETECT : 0;
+ *value |= (pipr & M8XX_PCMCIA_WP(lsock)) ? SS_WRPROT : 0;
+
+ if (s->state.flags & SS_IOCARD)
+ *value |= (pipr & M8XX_PCMCIA_BVD1(lsock)) ? SS_STSCHG : 0;
+ else {
+ *value |= (pipr & M8XX_PCMCIA_RDY(lsock)) ? SS_READY : 0;
+ *value |= (pipr & M8XX_PCMCIA_BVD1(lsock)) ? SS_BATDEAD : 0;
+ *value |= (pipr & M8XX_PCMCIA_BVD2(lsock)) ? SS_BATWARN : 0;
+ }
+
+ if (s->state.Vcc | s->state.Vpp)
+ *value |= SS_POWERON;
+
+ /*
+ * Voltage detection:
+ * This driver only supports 16-Bit pc-cards.
+ * Cardbus is not handled here.
+ *
+ * To determine what voltage to use we must read the VS1 and VS2 pin.
+ * Depending on what socket type is present,
+ * different combinations mean different things.
+ *
+ * Card Key Socket Key VS1 VS2 Card Vcc for CIS parse
+ *
+ * 5V 5V, LV* NC NC 5V only 5V (if available)
+ *
+ * 5V 5V, LV* GND NC 5 or 3.3V as low as possible
+ *
+ * 5V 5V, LV* GND GND 5, 3.3, x.xV as low as possible
+ *
+ * LV* 5V - - shall not fit into socket
+ *
+ * LV* LV* GND NC 3.3V only 3.3V
+ *
+ * LV* LV* NC GND x.xV x.xV (if avail.)
+ *
+ * LV* LV* GND GND 3.3 or x.xV as low as possible
+ *
+ * *LV means Low Voltage
+ *
+ *
+ * That gives us the following table:
+ *
+ * Socket VS1 VS2 Voltage
+ *
+ * 5V NC NC 5V
+ * 5V NC GND none (should not be possible)
+ * 5V GND NC >= 3.3V
+ * 5V GND GND >= x.xV
+ *
+ * LV NC NC 5V (if available)
+ * LV NC GND x.xV (if available)
+ * LV GND NC 3.3V
+ * LV GND GND >= x.xV
+ *
+ * So, how do I determine if I have a 5V or a LV
+ * socket on my board? Look at the socket!
+ *
+ *
+ * Socket with 5V key:
+ * ++--------------------------------------------+
+ * || |
+ * || ||
+ * || ||
+ * | |
+ * +---------------------------------------------+
+ *
+ * Socket with LV key:
+ * ++--------------------------------------------+
+ * || |
+ * | ||
+ * | ||
+ * | |
+ * +---------------------------------------------+
+ *
+ *
+ * With other words - LV only cards does not fit
+ * into the 5V socket!
+ */
+
+ /* read out VS1 and VS2 */
+
+ reg = (pipr & M8XX_PCMCIA_VS_MASK(lsock))
+ >> M8XX_PCMCIA_VS_SHIFT(lsock);
+
+ if(socket_get(lsock) == PCMCIA_SOCKET_KEY_LV) {
+ switch(reg) {
+ case 1:
+ *value |= SS_3VCARD;
+ break; /* GND, NC - 3.3V only */
+ case 2:
+ *value |= SS_XVCARD;
+ break; /* NC. GND - x.xV only */
+ };
+ }
+
+ dprintk("GetStatus(%d) = %#2.2x\n", lsock, *value);
+ return 0;
+}
+
+static int m8xx_get_socket(struct pcmcia_socket *sock, socket_state_t *state)
+{
+ int lsock = container_of(sock, struct socket_info, socket)->slot;
+ *state = socket[lsock].state; /* copy the whole structure */
+
+ dprintk("GetSocket(%d) = flags %#3.3x, Vcc %d, Vpp %d, "
+ "io_irq %d, csc_mask %#2.2x\n", lsock, state->flags,
+ state->Vcc, state->Vpp, state->io_irq, state->csc_mask);
+ return 0;
+}
+
+static int m8xx_set_socket(struct pcmcia_socket *sock, socket_state_t *state)
+{
+ int lsock = container_of(sock, struct socket_info, socket)->slot;
+ struct socket_info *s = &socket[lsock];
+ struct event_table *e;
+ unsigned int reg;
+ unsigned long flags;
+
+ dprintk( "SetSocket(%d, flags %#3.3x, Vcc %d, Vpp %d, "
+ "io_irq %d, csc_mask %#2.2x)\n", lsock, state->flags,
+ state->Vcc, state->Vpp, state->io_irq, state->csc_mask);
+
+ /* First, set voltage - bail out if invalid */
+ if(voltage_set(lsock, state->Vcc, state->Vpp))
+ return -EINVAL;
+
+ /* Take care of reset... */
+ if(state->flags & SS_RESET)
+ out_be32(M8XX_PGCRX(lsock), in_be32(M8XX_PGCRX(lsock)) | M8XX_PGCRX_CXRESET); /* active high */
+ else
+ out_be32(M8XX_PGCRX(lsock), in_be32(M8XX_PGCRX(lsock)) & ~M8XX_PGCRX_CXRESET);
+
+ /* ... and output enable. */
+
+ /* The CxOE signal is connected to a 74541 on the ADS.
+ I guess most other boards used the ADS as a reference.
+ I tried to control the CxOE signal with SS_OUTPUT_ENA,
+ but the reset signal seems connected via the 541.
+ If the CxOE is left high are some signals tristated and
+ no pullups are present -> the cards act wierd.
+ So right now the buffers are enabled if the power is on. */
+
+ if(state->Vcc || state->Vpp)
+ out_be32(M8XX_PGCRX(lsock), in_be32(M8XX_PGCRX(lsock)) & ~M8XX_PGCRX_CXOE); /* active low */
+ else
+ out_be32(M8XX_PGCRX(lsock), in_be32(M8XX_PGCRX(lsock)) | M8XX_PGCRX_CXOE);
+
+ /*
+ * We'd better turn off interrupts before
+ * we mess with the events-table..
+ */
+
+ spin_lock_irqsave(&events_lock, flags);
+
+ /*
+ * Play around with the interrupt mask to be able to
+ * give the events the generic pcmcia driver wants us to.
+ */
+
+ e = &s->events[0];
+ reg = 0;
+
+ if(state->csc_mask & SS_DETECT) {
+ e->eventbit = SS_DETECT;
+ reg |= e->regbit = (M8XX_PCMCIA_CD2(lsock)
+ | M8XX_PCMCIA_CD1(lsock));
+ e++;
+ }
+ if(state->flags & SS_IOCARD) {
+ /*
+ * I/O card
+ */
+ if(state->csc_mask & SS_STSCHG) {
+ e->eventbit = SS_STSCHG;
+ reg |= e->regbit = M8XX_PCMCIA_BVD1(lsock);
+ e++;
+ }
+ /*
+ * If io_irq is non-zero we should enable irq.
+ */
+ if(state->io_irq) {
+ out_be32(M8XX_PGCRX(lsock), in_be32(M8XX_PGCRX(lsock)) | mk_int_int_mask(state->io_irq) << 24);
+ /*
+ * Strange thing here:
+ * The manual does not tell us which interrupt
+ * the sources generate.
+ * Anyhow, I found out that RDY_L generates IREQLVL.
+ *
+ * We use level triggerd interrupts, and they don't
+ * have to be cleared in PSCR in the interrupt handler.
+ */
+ reg |= M8XX_PCMCIA_RDY_L(lsock);
+ }
+ else
+ out_be32(M8XX_PGCRX(lsock), in_be32(M8XX_PGCRX(lsock)) & 0x00ffffff);
+ }
+ else {
+ /*
+ * Memory card
+ */
+ if(state->csc_mask & SS_BATDEAD) {
+ e->eventbit = SS_BATDEAD;
+ reg |= e->regbit = M8XX_PCMCIA_BVD1(lsock);
+ e++;
+ }
+ if(state->csc_mask & SS_BATWARN) {
+ e->eventbit = SS_BATWARN;
+ reg |= e->regbit = M8XX_PCMCIA_BVD2(lsock);
+ e++;
+ }
+ /* What should I trigger on - low/high,raise,fall? */
+ if(state->csc_mask & SS_READY) {
+ e->eventbit = SS_READY;
+ reg |= e->regbit = 0; //??
+ e++;
+ }
+ }
+
+ e->regbit = 0; /* terminate list */
+
+ /*
+ * Clear the status changed .
+ * Port A and Port B share the same port.
+ * Writing ones will clear the bits.
+ */
+
+ out_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pscr, reg);
+
+ /*
+ * Write the mask.
+ * Port A and Port B share the same port.
+ * Need for read-modify-write.
+ * Ones will enable the interrupt.
+ */
+
+ /*
+ reg |= ((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_per
+ & M8XX_PCMCIA_MASK(lsock);
+ */
+
+ reg |= in_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_per) &
+ (M8XX_PCMCIA_MASK(0) | M8XX_PCMCIA_MASK(1));
+
+ out_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_per, reg);
+
+ spin_unlock_irqrestore(&events_lock, flags);
+
+ /* copy the struct and modify the copy */
+
+ s->state = *state;
+
+ return 0;
+}
+
+static int m8xx_set_io_map(struct pcmcia_socket *sock, struct pccard_io_map *io)
+{
+ int lsock = container_of(sock, struct socket_info, socket)->slot;
+
+ struct socket_info *s = &socket[lsock];
+ struct pcmcia_win *w;
+ unsigned int reg, winnr;
+
+#define M8XX_SIZE (io->stop - io->start + 1)
+#define M8XX_BASE (PCMCIA_IO_WIN_BASE + io->start)
+
+ dprintk( "SetIOMap(%d, %d, %#2.2x, %d ns, "
+ "%#4.4x-%#4.4x)\n", lsock, io->map, io->flags,
+ io->speed, io->start, io->stop);
+
+ if ((io->map >= PCMCIA_IO_WIN_NO) || (io->start > 0xffff)
+ || (io->stop > 0xffff) || (io->stop < io->start))
+ return -EINVAL;
+
+ if((reg = m8xx_get_graycode(M8XX_SIZE)) == -1)
+ return -EINVAL;
+
+ if(io->flags & MAP_ACTIVE) {
+
+ dprintk( "io->flags & MAP_ACTIVE\n");
+
+ winnr = (PCMCIA_MEM_WIN_NO * PCMCIA_SOCKETS_NO)
+ + (lsock * PCMCIA_IO_WIN_NO) + io->map;
+
+ /* setup registers */
+
+ w = (void *) &((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pbr0;
+ w += winnr;
+
+ out_be32(&w->or, 0); /* turn off window first */
+ out_be32(&w->br, M8XX_BASE);
+
+ reg <<= 27;
+ reg |= M8XX_PCMCIA_POR_IO |(lsock << 2);
+
+ reg |= m8xx_get_speed(io->speed, 1);
+
+ if(io->flags & MAP_WRPROT)
+ reg |= M8XX_PCMCIA_POR_WRPROT;
+
+ /*if(io->flags & (MAP_16BIT | MAP_AUTOSZ))*/
+ if(io->flags & MAP_16BIT)
+ reg |= M8XX_PCMCIA_POR_16BIT;
+
+ if(io->flags & MAP_ACTIVE)
+ reg |= M8XX_PCMCIA_POR_VALID;
+
+ out_be32(&w->or, reg);
+
+ dprintk("Socket %u: Mapped io window %u at %#8.8x, "
+ "OR = %#8.8x.\n", lsock, io->map, w->br, w->or);
+ } else {
+ /* shutdown IO window */
+ winnr = (PCMCIA_MEM_WIN_NO * PCMCIA_SOCKETS_NO)
+ + (lsock * PCMCIA_IO_WIN_NO) + io->map;
+
+ /* setup registers */
+
+ w = (void *) &((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pbr0;
+ w += winnr;
+
+ out_be32(&w->or, 0); /* turn off window */
+ out_be32(&w->br, 0); /* turn off base address */
+
+ dprintk("Socket %u: Unmapped io window %u at %#8.8x, "
+ "OR = %#8.8x.\n", lsock, io->map, w->br, w->or);
+ }
+
+ /* copy the struct and modify the copy */
+ s->io_win[io->map] = *io;
+ s->io_win[io->map].flags &= (MAP_WRPROT
+ | MAP_16BIT
+ | MAP_ACTIVE);
+ dprintk("SetIOMap exit\n");
+
+ return 0;
+}
+
+static int m8xx_set_mem_map(struct pcmcia_socket *sock, struct pccard_mem_map *mem)
+{
+ int lsock = container_of(sock, struct socket_info, socket)->slot;
+ struct socket_info *s = &socket[lsock];
+ struct pcmcia_win *w;
+ struct pccard_mem_map *old;
+ unsigned int reg, winnr;
+
+ dprintk( "SetMemMap(%d, %d, %#2.2x, %d ns, "
+ "%#5.5lx, %#5.5x)\n", lsock, mem->map, mem->flags,
+ mem->speed, mem->static_start, mem->card_start);
+
+ if ((mem->map >= PCMCIA_MEM_WIN_NO)
+// || ((mem->s) >= PCMCIA_MEM_WIN_SIZE)
+ || (mem->card_start >= 0x04000000)
+ || (mem->static_start & 0xfff) /* 4KByte resolution */
+ || (mem->card_start & 0xfff))
+ return -EINVAL;
+
+ if((reg = m8xx_get_graycode(PCMCIA_MEM_WIN_SIZE)) == -1) {
+ printk( "Cannot set size to 0x%08x.\n", PCMCIA_MEM_WIN_SIZE);
+ return -EINVAL;
+ }
+ reg <<= 27;
+
+ winnr = (lsock * PCMCIA_MEM_WIN_NO) + mem->map;
+
+ /* Setup the window in the pcmcia controller */
+
+ w = (void *) &((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pbr0;
+ w += winnr;
+
+ reg |= lsock << 2;
+
+ reg |= m8xx_get_speed(mem->speed, 0);
+
+ if(mem->flags & MAP_ATTRIB)
+ reg |= M8XX_PCMCIA_POR_ATTRMEM;
+
+ if(mem->flags & MAP_WRPROT)
+ reg |= M8XX_PCMCIA_POR_WRPROT;
+
+ if(mem->flags & MAP_16BIT)
+ reg |= M8XX_PCMCIA_POR_16BIT;
+
+ if(mem->flags & MAP_ACTIVE)
+ reg |= M8XX_PCMCIA_POR_VALID;
+
+ out_be32(&w->or, reg);
+
+ dprintk("Socket %u: Mapped memory window %u at %#8.8x, "
+ "OR = %#8.8x.\n", lsock, mem->map, w->br, w->or);
+
+ if(mem->flags & MAP_ACTIVE) {
+ /* get the new base address */
+ mem->static_start = PCMCIA_MEM_WIN_BASE +
+ (PCMCIA_MEM_WIN_SIZE * winnr)
+ + mem->card_start;
+ }
+
+ dprintk("SetMemMap(%d, %d, %#2.2x, %d ns, "
+ "%#5.5lx, %#5.5x)\n", lsock, mem->map, mem->flags,
+ mem->speed, mem->static_start, mem->card_start);
+
+ /* copy the struct and modify the copy */
+
+ old = &s->mem_win[mem->map];
+
+ *old = *mem;
+ old->flags &= (MAP_ATTRIB
+ | MAP_WRPROT
+ | MAP_16BIT
+ | MAP_ACTIVE);
+
+ return 0;
+}
+
+static int m8xx_sock_init(struct pcmcia_socket *sock)
+{
+ int i;
+ pccard_io_map io = { 0, 0, 0, 0, 1 };
+ pccard_mem_map mem = { 0, 0, 0, 0, 0, 0 };
+
+ dprintk( "sock_init(%d)\n", s);
+
+ m8xx_set_socket(sock, &dead_socket);
+ for (i = 0; i < PCMCIA_IO_WIN_NO; i++) {
+ io.map = i;
+ m8xx_set_io_map(sock, &io);
+ }
+ for (i = 0; i < PCMCIA_MEM_WIN_NO; i++) {
+ mem.map = i;
+ m8xx_set_mem_map(sock, &mem);
+ }
+
+ return 0;
+
+}
+
+static int m8xx_suspend(struct pcmcia_socket *sock)
+{
+ return m8xx_set_socket(sock, &dead_socket);
+}
+
+static struct pccard_operations m8xx_services = {
+ .init = m8xx_sock_init,
+ .suspend = m8xx_suspend,
+ .get_status = m8xx_get_status,
+ .get_socket = m8xx_get_socket,
+ .set_socket = m8xx_set_socket,
+ .set_io_map = m8xx_set_io_map,
+ .set_mem_map = m8xx_set_mem_map,
+};
+
+static int __init m8xx_init(void)
+{
+ struct pcmcia_win *w;
+ unsigned int i,m;
+
+ pcmcia_info("%s\n", version);
+
+ if (driver_register(&m8xx_driver))
+ return -1;
+
+ pcmcia_info(PCMCIA_BOARD_MSG " using " PCMCIA_SLOT_MSG
+ " with IRQ %u.\n", pcmcia_schlvl);
+
+ /* Configure Status change interrupt */
+
+ if(request_irq(pcmcia_schlvl, m8xx_interrupt, 0,
+ "m8xx_pcmcia", NULL)) {
+ pcmcia_error("Cannot allocate IRQ %u for SCHLVL!\n",
+ pcmcia_schlvl);
+ return -1;
+ }
+
+ w = (void *) &((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pbr0;
+
+ out_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pscr,
+ M8XX_PCMCIA_MASK(0)| M8XX_PCMCIA_MASK(1));
+
+ out_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_per,
+ in_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_per) &
+ ~(M8XX_PCMCIA_MASK(0)| M8XX_PCMCIA_MASK(1)));
+
+/* connect interrupt and disable CxOE */
+
+ out_be32(M8XX_PGCRX(0), M8XX_PGCRX_CXOE | (mk_int_int_mask(pcmcia_schlvl) << 16));
+ out_be32(M8XX_PGCRX(1), M8XX_PGCRX_CXOE | (mk_int_int_mask(pcmcia_schlvl) << 16));
+
+/* intialize the fixed memory windows */
+
+ for(i = 0; i < PCMCIA_SOCKETS_NO; i++){
+ for(m = 0; m < PCMCIA_MEM_WIN_NO; m++) {
+ out_be32(&w->br, PCMCIA_MEM_WIN_BASE +
+ (PCMCIA_MEM_WIN_SIZE
+ * (m + i * PCMCIA_MEM_WIN_NO)));
+
+ out_be32(&w->or, 0); /* set to not valid */
+
+ w++;
+ }
+ }
+
+/* turn off voltage */
+ voltage_set(0, 0, 0);
+ voltage_set(1, 0, 0);
+
+/* Enable external hardware */
+ hardware_enable(0);
+ hardware_enable(1);
+
+ platform_device_register(&m8xx_device);
+
+ for (i = 0 ; i < PCMCIA_SOCKETS_NO; i++) {
+ socket[i].slot = i;
+ socket[i].socket.owner = THIS_MODULE;
+ socket[i].socket.features = SS_CAP_PCCARD | SS_CAP_MEM_ALIGN | SS_CAP_STATIC_MAP;
+ socket[i].socket.irq_mask = 0x000;
+ socket[i].socket.map_size = 0x1000;
+ socket[i].socket.io_offset = 0;
+ socket[i].socket.pci_irq = i ? 7 : 9;
+ socket[i].socket.ops = &m8xx_services;
+ socket[i].socket.resource_ops = &pccard_nonstatic_ops;
+ socket[i].socket.cb_dev = NULL;
+ socket[i].socket.dev.dev = &m8xx_device.dev;
+ }
+
+ for (i = 0; i < PCMCIA_SOCKETS_NO; i++)
+ pcmcia_register_socket(&socket[i].socket);
+
+ return 0;
+}
+
+static void __exit m8xx_exit(void)
+{
+ int i;
+
+ for (i = 0; i < PCMCIA_SOCKETS_NO; i++)
+ pcmcia_unregister_socket(&socket[i].socket);
+
+ m8xx_shutdown();
+
+ platform_device_unregister(&m8xx_device);
+ driver_unregister(&m8xx_driver);
+}
+
+module_init(m8xx_init);
+module_exit(m8xx_exit);
^ permalink raw reply
* Re: [PATCH] MPC8xx PCMCIA driver
From: Jeff Garzik @ 2005-09-14 18:46 UTC (permalink / raw)
To: Marcelo Tosatti
Cc: Magnus Damm, linux-kernel, Dominik Brodowski, linux-ppc-embedded
In-Reply-To: <20050914182136.GE6783@dmt.cnet>
Marcelo Tosatti wrote:
> Here is an uptodated version of the MPC8xx PCMCIA driver for v2.6,
> addressing comments by Jeff and Dominik:
>
> - use IO accessors instead of direct device memory referencing
> - avoid usage of non-standard "uint/uchar" data types
> - kill struct typedef's
>
> Will submit it for inclusion once v2.6.14 is out.
>
> Testing on 8xx platforms is more than welcome! Works like a charm
> on our custom hardware (CONFIG_PRxK).
No complaints here...
Jeff
^ permalink raw reply
* Re: [PATCH] powerpc: merge include/asm/cputable.h
From: Kumar Gala @ 2005-09-14 19:11 UTC (permalink / raw)
To: Arnd Bergmann
Cc: linuxppc-dev, pantelis.antoniou, linuxppc64-dev,
linuxppc-embedded
In-Reply-To: <200509090623.41889.arnd@arndb.de>
Arnd,
I not sure I understand what the introduction of the enum's gets us.
- kumar
On Sep 8, 2005, at 11:23 PM, Arnd Bergmann wrote:
> This is an updated version of my old patch that creates a more
> optimized
> version of cpu_has_feature(). This version actually combines
> asm-ppc/cputable.h and asm-ppc64/cputable.h, which turned out to be
> a lot more work than only the 64 bit version.
>
> The 64 bit parts a relatively straightforward port of my earlier work
> which I tested in a number of configurations. The 32 bit parts are
> not tested at all, all I did was compiling the ppc defconfig with
> this.
>
> I think it is best if I hand the patch over to Kumar and Becky for
> further testing and cleaning up the remaining bits in the new
> file, as they appear to have invested some thought in it already.
> This version still has a number of #ifdef __powerpc64__ that should
> probably go away in the process.
>
> The patch also relies on having the ASM_CONST() macro in ppc_asm.h,
> as proposed by Kumar Gala, so it won't work on the current git
> head without that change.
>
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
>
> --
>
> clean-cg/arch/ppc/kernel/cputable.c | 401 ++++
> +----------------------
> clean-cg/arch/ppc64/Kconfig | 30 ++
> clean-cg/arch/ppc64/kernel/cputable.c | 82 +----
> clean-cg/include/asm-powerpc/cputable.h | 475 ++++++++++++++++++++
> ++++++++++++
> include/asm-ppc/cputable.h | 128 --------
> include/asm-ppc64/cputable.h | 167 -----------
>
> Index: clean-cg/include/asm-ppc64/cputable.h
> ===================================================================
> --- clean-cg.orig/include/asm-ppc64/cputable.h
> +++ /dev/null
> @@ -1,167 +0,0 @@
> -/*
> - * include/asm-ppc64/cputable.h
> - *
> - * Copyright (C) 2001 Ben. Herrenschmidt (benh@kernel.crashing.org)
> - *
> - * Modifications for ppc64:
> - * Copyright (C) 2003 Dave Engebretsen <engebret@us.ibm.com>
> - *
> - * This program is free software; you can redistribute it and/or
> - * modify it under the terms of the GNU General Public License
> - * as published by the Free Software Foundation; either version
> - * 2 of the License, or (at your option) any later version.
> - */
> -
> -#ifndef __ASM_PPC_CPUTABLE_H
> -#define __ASM_PPC_CPUTABLE_H
> -
> -#include <linux/config.h>
> -#include <asm/page.h> /* for ASM_CONST */
> -
> -/* Exposed to userland CPU features - Must match ppc32 definitions */
> -#define PPC_FEATURE_32 0x80000000
> -#define PPC_FEATURE_64 0x40000000
> -#define PPC_FEATURE_601_INSTR 0x20000000
> -#define PPC_FEATURE_HAS_ALTIVEC 0x10000000
> -#define PPC_FEATURE_HAS_FPU 0x08000000
> -#define PPC_FEATURE_HAS_MMU 0x04000000
> -#define PPC_FEATURE_HAS_4xxMAC 0x02000000
> -#define PPC_FEATURE_UNIFIED_CACHE 0x01000000
> -
> -#ifdef __KERNEL__
> -
> -#ifndef __ASSEMBLY__
> -
> -/* This structure can grow, it's real size is used by head.S code
> - * via the mkdefs mechanism.
> - */
> -struct cpu_spec;
> -struct op_ppc64_model;
> -
> -typedef void (*cpu_setup_t)(unsigned long offset, struct
> cpu_spec* spec);
> -
> -struct cpu_spec {
> - /* CPU is matched via (PVR & pvr_mask) == pvr_value */
> - unsigned int pvr_mask;
> - unsigned int pvr_value;
> -
> - char *cpu_name;
> - unsigned long cpu_features; /* Kernel features */
> - unsigned int cpu_user_features; /* Userland features */
> -
> - /* cache line sizes */
> - unsigned int icache_bsize;
> - unsigned int dcache_bsize;
> -
> - /* number of performance monitor counters */
> - unsigned int num_pmcs;
> -
> - /* this is called to initialize various CPU bits like L1 cache,
> - * BHT, SPD, etc... from head.S before branching to
> identify_machine
> - */
> - cpu_setup_t cpu_setup;
> -
> - /* Used by oprofile userspace to select the right counters */
> - char *oprofile_cpu_type;
> -
> - /* Processor specific oprofile operations */
> - struct op_ppc64_model *oprofile_model;
> -};
> -
> -extern struct cpu_spec cpu_specs[];
> -extern struct cpu_spec *cur_cpu_spec;
> -
> -static inline unsigned long cpu_has_feature(unsigned long feature)
> -{
> - return cur_cpu_spec->cpu_features & feature;
> -}
> -
> -#endif /* __ASSEMBLY__ */
> -
> -/* CPU kernel features */
> -
> -/* Retain the 32b definitions for the time being - use bottom half
> of word */
> -#define CPU_FTR_SPLIT_ID_CACHE ASM_CONST(0x0000000000000001)
> -#define CPU_FTR_L2CR ASM_CONST(0x0000000000000002)
> -#define CPU_FTR_SPEC7450 ASM_CONST(0x0000000000000004)
> -#define CPU_FTR_ALTIVEC ASM_CONST(0x0000000000000008)
> -#define CPU_FTR_TAU ASM_CONST(0x0000000000000010)
> -#define CPU_FTR_CAN_DOZE ASM_CONST(0x0000000000000020)
> -#define CPU_FTR_USE_TB ASM_CONST(0x0000000000000040)
> -#define CPU_FTR_604_PERF_MON ASM_CONST(0x0000000000000080)
> -#define CPU_FTR_601 ASM_CONST(0x0000000000000100)
> -#define CPU_FTR_HPTE_TABLE ASM_CONST(0x0000000000000200)
> -#define CPU_FTR_CAN_NAP ASM_CONST(0x0000000000000400)
> -#define CPU_FTR_L3CR ASM_CONST(0x0000000000000800)
> -#define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x0000000000001000)
> -#define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x0000000000002000)
> -#define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x0000000000004000)
> -
> -/* Add the 64b processor unique features in the top half of the
> word */
> -#define CPU_FTR_SLB ASM_CONST(0x0000000100000000)
> -#define CPU_FTR_16M_PAGE ASM_CONST(0x0000000200000000)
> -#define CPU_FTR_TLBIEL ASM_CONST(0x0000000400000000)
> -#define CPU_FTR_NOEXECUTE ASM_CONST(0x0000000800000000)
> -#define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000001000000000)
> -#define CPU_FTR_IABR ASM_CONST(0x0000002000000000)
> -#define CPU_FTR_MMCRA ASM_CONST(0x0000004000000000)
> -/* unused ASM_CONST(0x0000008000000000) */
> -#define CPU_FTR_SMT ASM_CONST(0x0000010000000000)
> -#define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x0000020000000000)
> -#define CPU_FTR_LOCKLESS_TLBIE ASM_CONST(0x0000040000000000)
> -#define CPU_FTR_MMCRA_SIHV ASM_CONST(0x0000080000000000)
> -#define CPU_FTR_CTRL ASM_CONST(0x0000100000000000)
> -
> -#ifndef __ASSEMBLY__
> -
> -#define COMMON_USER_PPC64 (PPC_FEATURE_32 | PPC_FEATURE_64 | \
> - PPC_FEATURE_HAS_FPU | PPC_FEATURE_HAS_MMU)
> -
> -#define CPU_FTR_PPCAS_ARCH_V2_BASE (CPU_FTR_SLB | \
> - CPU_FTR_TLBIEL |
> CPU_FTR_NOEXECUTE | \
> - CPU_FTR_NODSISRALIGN | CPU_FTR_CTRL)
> -
> -/* iSeries doesn't support large pages */
> -#ifdef CONFIG_PPC_ISERIES
> -#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_PPCAS_ARCH_V2_BASE)
> -#else
> -#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_PPCAS_ARCH_V2_BASE |
> CPU_FTR_16M_PAGE)
> -#endif /* CONFIG_PPC_ISERIES */
> -
> -#endif /* __ASSEMBLY */
> -
> -#ifdef __ASSEMBLY__
> -
> -#define BEGIN_FTR_SECTION 98:
> -
> -#define END_FTR_SECTION(msk, val) \
> -99: \
> - .section __ftr_fixup,"a"; \
> - .align 3; \
> - .llong msk; \
> - .llong val; \
> - .llong 98b; \
> - .llong 99b; \
> - .previous
> -
> -#else
> -
> -#define BEGIN_FTR_SECTION "98:\n"
> -#define END_FTR_SECTION(msk, val) \
> -"99:\n" \
> -" .section __ftr_fixup,\"a\";\n" \
> -" .align 3;\n" \
> -" .llong "#msk";\n" \
> -" .llong "#val";\n" \
> -" .llong 98b;\n" \
> -" .llong 99b;\n" \
> -" .previous\n"
> -
> -#endif /* __ASSEMBLY__ */
> -
> -#define END_FTR_SECTION_IFSET(msk) END_FTR_SECTION((msk), (msk))
> -#define END_FTR_SECTION_IFCLR(msk) END_FTR_SECTION((msk), 0)
> -
> -#endif /* __ASM_PPC_CPUTABLE_H */
> -#endif /* __KERNEL__ */
> -
> Index: clean-cg/arch/ppc64/Kconfig
> ===================================================================
> --- clean-cg.orig/arch/ppc64/Kconfig
> +++ clean-cg/arch/ppc64/Kconfig
> @@ -125,6 +125,36 @@ config BPA_IIC
> bool
> default y
>
> +config CPU_POWER3
> + bool
> + default y
> + depends on (PPC_ISERIES || PPC_PSERIES) && !POWER4_ONLY
> +
> +config CPU_RS64
> + bool
> + default y
> + depends on (PPC_ISERIES || PPC_PSERIES) && !POWER4_ONLY
> +
> +config CPU_POWER4
> + bool
> + default y
> + depends on PPC_ISERIES || PPC_PSERIES
> +
> +config CPU_PPC970
> + bool
> + default y
> + depends on PPC_PSERIES || PPC_PMAC || PPC_MAPLE
> +
> +config CPU_POWER5
> + bool
> + default y
> + depends on PPC_PSERIES
> +
> +config CPU_CELL
> + bool
> + default y
> + depends on PPC_BPA
> +
> # VMX is pSeries only for now until somebody writes the iSeries
> # exception vectors for it
> config ALTIVEC
> Index: clean-cg/arch/ppc64/kernel/cputable.c
> ===================================================================
> --- clean-cg.orig/arch/ppc64/kernel/cputable.c
> +++ clean-cg/arch/ppc64/kernel/cputable.c
> @@ -37,26 +37,13 @@ extern void __setup_cpu_power4(unsigned
> extern void __setup_cpu_ppc970(unsigned long offset, struct
> cpu_spec* spec);
> extern void __setup_cpu_be(unsigned long offset, struct cpu_spec*
> spec);
>
> -
> -/* We only set the altivec features if the kernel was compiled
> with altivec
> - * support
> - */
> -#ifdef CONFIG_ALTIVEC
> -#define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC
> -#define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
> -#else
> -#define CPU_FTR_ALTIVEC_COMP 0
> -#define PPC_FEATURE_HAS_ALTIVEC_COMP 0
> -#endif
> -
> struct cpu_spec cpu_specs[] = {
> { /* Power3 */
> .pvr_mask = 0xffff0000,
> .pvr_value = 0x00400000,
> .cpu_name = "POWER3 (630)",
> - .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
> - CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR,
> - .cpu_user_features = COMMON_USER_PPC64,
> + .cpu_features = CPU_FTR_POWER3,
> + .cpu_user_features = COMMON_USER_PPC64,
> .icache_bsize = 128,
> .dcache_bsize = 128,
> .num_pmcs = 8,
> @@ -70,8 +57,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffff0000,
> .pvr_value = 0x00410000,
> .cpu_name = "POWER3 (630+)",
> - .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
> - CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR,
> + .cpu_features = CPU_FTR_POWER3,
> .cpu_user_features = COMMON_USER_PPC64,
> .icache_bsize = 128,
> .dcache_bsize = 128,
> @@ -86,9 +72,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffff0000,
> .pvr_value = 0x00330000,
> .cpu_name = "RS64-II (northstar)",
> - .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
> - CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
> - CPU_FTR_MMCRA | CPU_FTR_CTRL,
> + .cpu_features = CPU_FTR_RS64,
> .cpu_user_features = COMMON_USER_PPC64,
> .icache_bsize = 128,
> .dcache_bsize = 128,
> @@ -103,9 +87,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffff0000,
> .pvr_value = 0x00340000,
> .cpu_name = "RS64-III (pulsar)",
> - .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
> - CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
> - CPU_FTR_MMCRA | CPU_FTR_CTRL,
> + .cpu_features = CPU_FTR_RS64,
> .cpu_user_features = COMMON_USER_PPC64,
> .icache_bsize = 128,
> .dcache_bsize = 128,
> @@ -120,9 +102,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffff0000,
> .pvr_value = 0x00360000,
> .cpu_name = "RS64-III (icestar)",
> - .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
> - CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
> - CPU_FTR_MMCRA | CPU_FTR_CTRL,
> + .cpu_features = CPU_FTR_RS64,
> .cpu_user_features = COMMON_USER_PPC64,
> .icache_bsize = 128,
> .dcache_bsize = 128,
> @@ -137,9 +117,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffff0000,
> .pvr_value = 0x00370000,
> .cpu_name = "RS64-IV (sstar)",
> - .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
> - CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
> - CPU_FTR_MMCRA | CPU_FTR_CTRL,
> + .cpu_features = CPU_FTR_RS64,
> .cpu_user_features = COMMON_USER_PPC64,
> .icache_bsize = 128,
> .dcache_bsize = 128,
> @@ -154,9 +132,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffff0000,
> .pvr_value = 0x00350000,
> .cpu_name = "POWER4 (gp)",
> - .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
> - CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
> - CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_MMCRA,
> + .cpu_features = CPU_FTR_POWER4,
> .cpu_user_features = COMMON_USER_PPC64,
> .icache_bsize = 128,
> .dcache_bsize = 128,
> @@ -171,9 +147,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffff0000,
> .pvr_value = 0x00380000,
> .cpu_name = "POWER4+ (gq)",
> - .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
> - CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
> - CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_MMCRA,
> + .cpu_features = CPU_FTR_POWER4,
> .cpu_user_features = COMMON_USER_PPC64,
> .icache_bsize = 128,
> .dcache_bsize = 128,
> @@ -188,10 +162,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffff0000,
> .pvr_value = 0x00390000,
> .cpu_name = "PPC970",
> - .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
> - CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
> - CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP |
> - CPU_FTR_CAN_NAP | CPU_FTR_MMCRA,
> + .cpu_features = CPU_FTR_PPC970,
> .cpu_user_features = COMMON_USER_PPC64 |
> PPC_FEATURE_HAS_ALTIVEC_COMP,
> .icache_bsize = 128,
> @@ -207,10 +178,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffff0000,
> .pvr_value = 0x003c0000,
> .cpu_name = "PPC970FX",
> - .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
> - CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
> - CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP |
> - CPU_FTR_CAN_NAP | CPU_FTR_MMCRA,
> + .cpu_features = CPU_FTR_PPC970,
> .cpu_user_features = COMMON_USER_PPC64 |
> PPC_FEATURE_HAS_ALTIVEC_COMP,
> .icache_bsize = 128,
> @@ -226,10 +194,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffff0000,
> .pvr_value = 0x00440000,
> .cpu_name = "PPC970MP",
> - .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
> - CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
> - CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP |
> - CPU_FTR_CAN_NAP | CPU_FTR_MMCRA,
> + .cpu_features = CPU_FTR_PPC970,
> .cpu_user_features = COMMON_USER_PPC64 |
> PPC_FEATURE_HAS_ALTIVEC_COMP,
> .icache_bsize = 128,
> @@ -244,11 +209,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffff0000,
> .pvr_value = 0x003a0000,
> .cpu_name = "POWER5 (gr)",
> - .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
> - CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
> - CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_MMCRA | CPU_FTR_SMT |
> - CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE |
> - CPU_FTR_MMCRA_SIHV,
> + .cpu_features = CPU_FTR_POWER5,
> .cpu_user_features = COMMON_USER_PPC64,
> .icache_bsize = 128,
> .dcache_bsize = 128,
> @@ -263,11 +224,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffff0000,
> .pvr_value = 0x003b0000,
> .cpu_name = "POWER5 (gs)",
> - .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
> - CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
> - CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_MMCRA | CPU_FTR_SMT |
> - CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE |
> - CPU_FTR_MMCRA_SIHV,
> + .cpu_features = CPU_FTR_POWER5,
> .cpu_user_features = COMMON_USER_PPC64,
> .icache_bsize = 128,
> .dcache_bsize = 128,
> @@ -281,11 +238,8 @@ struct cpu_spec cpu_specs[] = {
> { /* BE DD1.x */
> .pvr_mask = 0xffff0000,
> .pvr_value = 0x00700000,
> - .cpu_name = "Broadband Engine",
> - .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
> - CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
> - CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP |
> - CPU_FTR_SMT,
> + .cpu_name = "Cell Broadband Engine",
> + .cpu_features = CPU_FTR_CELL,
> .cpu_user_features = COMMON_USER_PPC64 |
> PPC_FEATURE_HAS_ALTIVEC_COMP,
> .icache_bsize = 128,
> @@ -296,9 +250,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0x00000000,
> .pvr_value = 0x00000000,
> .cpu_name = "POWER4 (compatible)",
> - .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
> - CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
> - CPU_FTR_PPCAS_ARCH_V2,
> + .cpu_features = CPU_FTR_COMPATIBLE,
> .cpu_user_features = COMMON_USER_PPC64,
> .icache_bsize = 128,
> .dcache_bsize = 128,
> Index: clean-cg/arch/ppc/kernel/cputable.c
> ===================================================================
> --- clean-cg.orig/arch/ppc/kernel/cputable.c
> +++ clean-cg/arch/ppc/kernel/cputable.c
> @@ -42,17 +42,6 @@ extern void __setup_cpu_generic(unsigned
> #define COMMON_PPC (PPC_FEATURE_32 | PPC_FEATURE_HAS_FPU | \
> PPC_FEATURE_HAS_MMU)
>
> -/* We only set the altivec features if the kernel was compiled
> with altivec
> - * support
> - */
> -#ifdef CONFIG_ALTIVEC
> -#define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC
> -#define PPC_FEATURE_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
> -#else
> -#define CPU_FTR_ALTIVEC_COMP 0
> -#define PPC_FEATURE_ALTIVEC_COMP 0
> -#endif
> -
> /* We only set the spe features if the kernel was compiled with
> * spe support
> */
> @@ -62,34 +51,13 @@ extern void __setup_cpu_generic(unsigned
> #define PPC_FEATURE_SPE_COMP 0
> #endif
>
> -/* We need to mark all pages as being coherent if we're SMP or we
> - * have a 74[45]x and an MPC107 host bridge.
> - */
> -#if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE)
> -#define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT
> -#else
> -#define CPU_FTR_COMMON 0
> -#endif
> -
> -/* The powersave features NAP & DOZE seems to confuse BDI when
> - debugging. So if a BDI is used, disable theses
> - */
> -#ifndef CONFIG_BDI_SWITCH
> -#define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE
> -#define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP
> -#else
> -#define CPU_FTR_MAYBE_CAN_DOZE 0
> -#define CPU_FTR_MAYBE_CAN_NAP 0
> -#endif
> -
> struct cpu_spec cpu_specs[] = {
> #if CLASSIC_PPC
> { /* 601 */
> .pvr_mask = 0xffff0000,
> .pvr_value = 0x00010000,
> .cpu_name = "601",
> - .cpu_features = CPU_FTR_COMMON | CPU_FTR_601 |
> - CPU_FTR_HPTE_TABLE,
> + .cpu_features = CPU_FTR_PPC601,
> .cpu_user_features = COMMON_PPC | PPC_FEATURE_601_INSTR |
> PPC_FEATURE_UNIFIED_CACHE,
> .icache_bsize = 32,
> @@ -100,9 +68,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffff0000,
> .pvr_value = 0x00030000,
> .cpu_name = "603",
> - .cpu_features = CPU_FTR_COMMON |
> - CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
> - CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP,
> + .cpu_features = CPU_FTR_603,
> .cpu_user_features = COMMON_PPC,
> .icache_bsize = 32,
> .dcache_bsize = 32,
> @@ -112,9 +78,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffff0000,
> .pvr_value = 0x00060000,
> .cpu_name = "603e",
> - .cpu_features = CPU_FTR_COMMON |
> - CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
> - CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP,
> + .cpu_features = CPU_FTR_603,
> .cpu_user_features = COMMON_PPC,
> .icache_bsize = 32,
> .dcache_bsize = 32,
> @@ -124,9 +88,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffff0000,
> .pvr_value = 0x00070000,
> .cpu_name = "603ev",
> - .cpu_features = CPU_FTR_COMMON |
> - CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
> - CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP,
> + .cpu_features = CPU_FTR_603,
> .cpu_user_features = COMMON_PPC,
> .icache_bsize = 32,
> .dcache_bsize = 32,
> @@ -136,9 +98,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffff0000,
> .pvr_value = 0x00040000,
> .cpu_name = "604",
> - .cpu_features = CPU_FTR_COMMON |
> - CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
> - CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE,
> + .cpu_features = CPU_FTR_604,
> .cpu_user_features = COMMON_PPC,
> .icache_bsize = 32,
> .dcache_bsize = 32,
> @@ -149,9 +109,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xfffff000,
> .pvr_value = 0x00090000,
> .cpu_name = "604e",
> - .cpu_features = CPU_FTR_COMMON |
> - CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
> - CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE,
> + .cpu_features = CPU_FTR_604,
> .cpu_user_features = COMMON_PPC,
> .icache_bsize = 32,
> .dcache_bsize = 32,
> @@ -162,9 +120,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffff0000,
> .pvr_value = 0x00090000,
> .cpu_name = "604r",
> - .cpu_features = CPU_FTR_COMMON |
> - CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
> - CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE,
> + .cpu_features = CPU_FTR_604,
> .cpu_user_features = COMMON_PPC,
> .icache_bsize = 32,
> .dcache_bsize = 32,
> @@ -175,9 +131,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffff0000,
> .pvr_value = 0x000a0000,
> .cpu_name = "604ev",
> - .cpu_features = CPU_FTR_COMMON |
> - CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
> - CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE,
> + .cpu_features = CPU_FTR_604,
> .cpu_user_features = COMMON_PPC,
> .icache_bsize = 32,
> .dcache_bsize = 32,
> @@ -188,10 +142,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffffffff,
> .pvr_value = 0x00084202,
> .cpu_name = "740/750",
> - .cpu_features = CPU_FTR_COMMON |
> - CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
> - CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_HPTE_TABLE |
> - CPU_FTR_MAYBE_CAN_NAP,
> + .cpu_features = CPU_FTR_740_NOTAU,
> .cpu_user_features = COMMON_PPC,
> .icache_bsize = 32,
> .dcache_bsize = 32,
> @@ -202,10 +153,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xfffffff0,
> .pvr_value = 0x00080100,
> .cpu_name = "750CX",
> - .cpu_features = CPU_FTR_COMMON |
> - CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
> - CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
> - CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
> + .cpu_features = CPU_FTR_750,
> .cpu_user_features = COMMON_PPC,
> .icache_bsize = 32,
> .dcache_bsize = 32,
> @@ -216,10 +164,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xfffffff0,
> .pvr_value = 0x00082200,
> .cpu_name = "750CX",
> - .cpu_features = CPU_FTR_COMMON |
> - CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
> - CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
> - CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
> + .cpu_features = CPU_FTR_750,
> .cpu_user_features = COMMON_PPC,
> .icache_bsize = 32,
> .dcache_bsize = 32,
> @@ -230,10 +175,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xfffffff0,
> .pvr_value = 0x00082210,
> .cpu_name = "750CXe",
> - .cpu_features = CPU_FTR_COMMON |
> - CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
> - CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
> - CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
> + .cpu_features = CPU_FTR_750,
> .cpu_user_features = COMMON_PPC,
> .icache_bsize = 32,
> .dcache_bsize = 32,
> @@ -244,10 +186,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffffffff,
> .pvr_value = 0x00083214,
> .cpu_name = "750CXe",
> - .cpu_features = CPU_FTR_COMMON |
> - CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
> - CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
> - CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
> + .cpu_features = CPU_FTR_750,
> .cpu_user_features = COMMON_PPC,
> .icache_bsize = 32,
> .dcache_bsize = 32,
> @@ -258,10 +197,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xfffff000,
> .pvr_value = 0x00083000,
> .cpu_name = "745/755",
> - .cpu_features = CPU_FTR_COMMON |
> - CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
> - CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
> - CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
> + .cpu_features = CPU_FTR_750,
> .cpu_user_features = COMMON_PPC,
> .icache_bsize = 32,
> .dcache_bsize = 32,
> @@ -272,11 +208,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffffff00,
> .pvr_value = 0x70000100,
> .cpu_name = "750FX",
> - .cpu_features = CPU_FTR_COMMON |
> - CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
> - CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
> - CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
> - CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM,
> + .cpu_features = CPU_FTR_750FX1,
> .cpu_user_features = COMMON_PPC,
> .icache_bsize = 32,
> .dcache_bsize = 32,
> @@ -287,11 +219,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffffffff,
> .pvr_value = 0x70000200,
> .cpu_name = "750FX",
> - .cpu_features = CPU_FTR_COMMON |
> - CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
> - CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
> - CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
> - CPU_FTR_NO_DPM,
> + .cpu_features = CPU_FTR_750FX2,
> .cpu_user_features = COMMON_PPC,
> .icache_bsize = 32,
> .dcache_bsize = 32,
> @@ -302,11 +230,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffff0000,
> .pvr_value = 0x70000000,
> .cpu_name = "750FX",
> - .cpu_features = CPU_FTR_COMMON |
> - CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
> - CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
> - CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
> - CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS,
> + .cpu_features = CPU_FTR_750FX,
> .cpu_user_features = COMMON_PPC,
> .icache_bsize = 32,
> .dcache_bsize = 32,
> @@ -317,11 +241,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffff0000,
> .pvr_value = 0x70020000,
> .cpu_name = "750GX",
> - .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
> - CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
> - CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE |
> - CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_DUAL_PLL_750FX |
> - CPU_FTR_HAS_HIGH_BATS,
> + .cpu_features = CPU_FTR_750GX,
> .cpu_user_features = COMMON_PPC,
> .icache_bsize = 32,
> .dcache_bsize = 32,
> @@ -332,10 +252,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffff0000,
> .pvr_value = 0x00080000,
> .cpu_name = "740/750",
> - .cpu_features = CPU_FTR_COMMON |
> - CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
> - CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
> - CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
> + .cpu_features = CPU_FTR_740,
> .cpu_user_features = COMMON_PPC,
> .icache_bsize = 32,
> .dcache_bsize = 32,
> @@ -346,11 +263,8 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffffffff,
> .pvr_value = 0x000c1101,
> .cpu_name = "7400 (1.1)",
> - .cpu_features = CPU_FTR_COMMON |
> - CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
> - CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
> - CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
> - .cpu_user_features = COMMON_PPC |
> PPC_FEATURE_ALTIVEC_COMP,
> + .cpu_features = CPU_FTR_7400_NOTAU,
> + .cpu_user_features = COMMON_PPC |
> PPC_FEATURE_HAS_ALTIVEC_COMP,
> .icache_bsize = 32,
> .dcache_bsize = 32,
> .num_pmcs = 4,
> @@ -360,12 +274,8 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffff0000,
> .pvr_value = 0x000c0000,
> .cpu_name = "7400",
> - .cpu_features = CPU_FTR_COMMON |
> - CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
> - CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
> - CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
> - CPU_FTR_MAYBE_CAN_NAP,
> - .cpu_user_features = COMMON_PPC |
> PPC_FEATURE_ALTIVEC_COMP,
> + .cpu_features = CPU_FTR_7400,
> + .cpu_user_features = COMMON_PPC |
> PPC_FEATURE_HAS_ALTIVEC_COMP,
> .icache_bsize = 32,
> .dcache_bsize = 32,
> .num_pmcs = 4,
> @@ -375,12 +285,8 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffff0000,
> .pvr_value = 0x800c0000,
> .cpu_name = "7410",
> - .cpu_features = CPU_FTR_COMMON |
> - CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
> - CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
> - CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
> - CPU_FTR_MAYBE_CAN_NAP,
> - .cpu_user_features = COMMON_PPC |
> PPC_FEATURE_ALTIVEC_COMP,
> + .cpu_features = CPU_FTR_7400,
> + .cpu_user_features = COMMON_PPC |
> PPC_FEATURE_HAS_ALTIVEC_COMP,
> .icache_bsize = 32,
> .dcache_bsize = 32,
> .num_pmcs = 4,
> @@ -390,12 +296,8 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffffffff,
> .pvr_value = 0x80000200,
> .cpu_name = "7450",
> - .cpu_features = CPU_FTR_COMMON |
> - CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
> - CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
> - CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
> - CPU_FTR_NEED_COHERENT,
> - .cpu_user_features = COMMON_PPC |
> PPC_FEATURE_ALTIVEC_COMP,
> + .cpu_features = CPU_FTR_7450_20,
> + .cpu_user_features = COMMON_PPC |
> PPC_FEATURE_HAS_ALTIVEC_COMP,
> .icache_bsize = 32,
> .dcache_bsize = 32,
> .num_pmcs = 6,
> @@ -405,14 +307,8 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffffffff,
> .pvr_value = 0x80000201,
> .cpu_name = "7450",
> - .cpu_features = CPU_FTR_COMMON |
> - CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
> - CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
> - CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
> - CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
> - CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP |
> - CPU_FTR_NEED_COHERENT,
> - .cpu_user_features = COMMON_PPC |
> PPC_FEATURE_ALTIVEC_COMP,
> + .cpu_features = CPU_FTR_7450_21,
> + .cpu_user_features = COMMON_PPC |
> PPC_FEATURE_HAS_ALTIVEC_COMP,
> .icache_bsize = 32,
> .dcache_bsize = 32,
> .num_pmcs = 6,
> @@ -422,13 +318,8 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffff0000,
> .pvr_value = 0x80000000,
> .cpu_name = "7450",
> - .cpu_features = CPU_FTR_COMMON |
> - CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
> - CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
> - CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
> - CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
> - CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT,
> - .cpu_user_features = COMMON_PPC |
> PPC_FEATURE_ALTIVEC_COMP,
> + .cpu_features = CPU_FTR_7450_23,
> + .cpu_user_features = COMMON_PPC |
> PPC_FEATURE_HAS_ALTIVEC_COMP,
> .icache_bsize = 32,
> .dcache_bsize = 32,
> .num_pmcs = 6,
> @@ -438,12 +329,8 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffffff00,
> .pvr_value = 0x80010100,
> .cpu_name = "7455",
> - .cpu_features = CPU_FTR_COMMON |
> - CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
> - CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
> - CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
> - CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT,
> - .cpu_user_features = COMMON_PPC |
> PPC_FEATURE_ALTIVEC_COMP,
> + .cpu_features = CPU_FTR_7455_1,
> + .cpu_user_features = COMMON_PPC |
> PPC_FEATURE_HAS_ALTIVEC_COMP,
> .icache_bsize = 32,
> .dcache_bsize = 32,
> .num_pmcs = 6,
> @@ -453,14 +340,8 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffffffff,
> .pvr_value = 0x80010200,
> .cpu_name = "7455",
> - .cpu_features = CPU_FTR_COMMON |
> - CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
> - CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
> - CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
> - CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
> - CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP |
> - CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS,
> - .cpu_user_features = COMMON_PPC |
> PPC_FEATURE_ALTIVEC_COMP,
> + .cpu_features = CPU_FTR_7455_20,
> + .cpu_user_features = COMMON_PPC |
> PPC_FEATURE_HAS_ALTIVEC_COMP,
> .icache_bsize = 32,
> .dcache_bsize = 32,
> .num_pmcs = 6,
> @@ -470,14 +351,8 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffff0000,
> .pvr_value = 0x80010000,
> .cpu_name = "7455",
> - .cpu_features = CPU_FTR_COMMON |
> - CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
> - CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
> - CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
> - CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
> - CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
> - CPU_FTR_NEED_COHERENT,
> - .cpu_user_features = COMMON_PPC |
> PPC_FEATURE_ALTIVEC_COMP,
> + .cpu_features = CPU_FTR_7455,
> + .cpu_user_features = COMMON_PPC |
> PPC_FEATURE_HAS_ALTIVEC_COMP,
> .icache_bsize = 32,
> .dcache_bsize = 32,
> .num_pmcs = 6,
> @@ -487,14 +362,8 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffffffff,
> .pvr_value = 0x80020100,
> .cpu_name = "7447/7457",
> - .cpu_features = CPU_FTR_COMMON |
> - CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
> - CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
> - CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
> - CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
> - CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
> - CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC,
> - .cpu_user_features = COMMON_PPC |
> PPC_FEATURE_ALTIVEC_COMP,
> + .cpu_features = CPU_FTR_7447_10,
> + .cpu_user_features = COMMON_PPC |
> PPC_FEATURE_HAS_ALTIVEC_COMP,
> .icache_bsize = 32,
> .dcache_bsize = 32,
> .num_pmcs = 6,
> @@ -504,14 +373,8 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffffffff,
> .pvr_value = 0x80020101,
> .cpu_name = "7447/7457",
> - .cpu_features = CPU_FTR_COMMON |
> - CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
> - CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
> - CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
> - CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
> - CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
> - CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC,
> - .cpu_user_features = COMMON_PPC |
> PPC_FEATURE_ALTIVEC_COMP,
> + .cpu_features = CPU_FTR_7447_10,
> + .cpu_user_features = COMMON_PPC |
> PPC_FEATURE_HAS_ALTIVEC_COMP,
> .icache_bsize = 32,
> .dcache_bsize = 32,
> .num_pmcs = 6,
> @@ -521,14 +384,8 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffff0000,
> .pvr_value = 0x80020000,
> .cpu_name = "7447/7457",
> - .cpu_features = CPU_FTR_COMMON |
> - CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
> - CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
> - CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
> - CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
> - CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
> - CPU_FTR_NEED_COHERENT,
> - .cpu_user_features = COMMON_PPC |
> PPC_FEATURE_ALTIVEC_COMP,
> + .cpu_features = CPU_FTR_7447,
> + .cpu_user_features = COMMON_PPC |
> PPC_FEATURE_HAS_ALTIVEC_COMP,
> .icache_bsize = 32,
> .dcache_bsize = 32,
> .num_pmcs = 6,
> @@ -538,13 +395,8 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffff0000,
> .pvr_value = 0x80030000,
> .cpu_name = "7447A",
> - .cpu_features = CPU_FTR_COMMON |
> - CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
> - CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
> - CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
> - CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
> - CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT,
> - .cpu_user_features = COMMON_PPC |
> PPC_FEATURE_ALTIVEC_COMP,
> + .cpu_features = CPU_FTR_7447A,
> + .cpu_user_features = COMMON_PPC |
> PPC_FEATURE_HAS_ALTIVEC_COMP,
> .icache_bsize = 32,
> .dcache_bsize = 32,
> .num_pmcs = 6,
> @@ -554,13 +406,8 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffff0000,
> .pvr_value = 0x80040000,
> .cpu_name = "7448",
> - .cpu_features = CPU_FTR_COMMON |
> - CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
> - CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
> - CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
> - CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
> - CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT,
> - .cpu_user_features = COMMON_PPC |
> PPC_FEATURE_ALTIVEC_COMP,
> + .cpu_features = CPU_FTR_7447A,
> + .cpu_user_features = COMMON_PPC |
> PPC_FEATURE_HAS_ALTIVEC_COMP,
> .icache_bsize = 32,
> .dcache_bsize = 32,
> .num_pmcs = 6,
> @@ -570,9 +417,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0x7fff0000,
> .pvr_value = 0x00810000,
> .cpu_name = "82xx",
> - .cpu_features = CPU_FTR_COMMON |
> - CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
> - CPU_FTR_USE_TB,
> + .cpu_features = CPU_FTR_82XX,
> .cpu_user_features = COMMON_PPC,
> .icache_bsize = 32,
> .dcache_bsize = 32,
> @@ -582,9 +427,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0x7fff0000,
> .pvr_value = 0x00820000,
> .cpu_name = "G2_LE",
> - .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
> - CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
> - CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS,
> + .cpu_features = CPU_FTR_G2_LE,
> .cpu_user_features = COMMON_PPC,
> .icache_bsize = 32,
> .dcache_bsize = 32,
> @@ -594,9 +437,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0x7fff0000,
> .pvr_value = 0x00830000,
> .cpu_name = "e300",
> - .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
> - CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
> - CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS,
> + .cpu_features = CPU_FTR_E300,
> .cpu_user_features = COMMON_PPC,
> .icache_bsize = 32,
> .dcache_bsize = 32,
> @@ -606,9 +447,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0x00000000,
> .pvr_value = 0x00000000,
> .cpu_name = "(generic PPC)",
> - .cpu_features = CPU_FTR_COMMON |
> - CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
> - CPU_FTR_HPTE_TABLE,
> + .cpu_features = CPU_FTR_CLASSIC32,
> .cpu_user_features = COMMON_PPC,
> .icache_bsize = 32,
> .dcache_bsize = 32,
> @@ -620,9 +459,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffff0000,
> .pvr_value = 0x00400000,
> .cpu_name = "Power3 (630)",
> - .cpu_features = CPU_FTR_COMMON |
> - CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
> - CPU_FTR_HPTE_TABLE,
> + .cpu_features = CPU_FTR_POWER3_32,
> .cpu_user_features = COMMON_PPC | PPC_FEATURE_64,
> .icache_bsize = 128,
> .dcache_bsize = 128,
> @@ -633,9 +470,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffff0000,
> .pvr_value = 0x00410000,
> .cpu_name = "Power3 (630+)",
> - .cpu_features = CPU_FTR_COMMON |
> - CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
> - CPU_FTR_HPTE_TABLE,
> + .cpu_features = CPU_FTR_POWER3_32,
> .cpu_user_features = COMMON_PPC | PPC_FEATURE_64,
> .icache_bsize = 128,
> .dcache_bsize = 128,
> @@ -646,9 +481,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffff0000,
> .pvr_value = 0x00360000,
> .cpu_name = "I-star",
> - .cpu_features = CPU_FTR_COMMON |
> - CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
> - CPU_FTR_HPTE_TABLE,
> + .cpu_features = CPU_FTR_POWER3_32,
> .cpu_user_features = COMMON_PPC | PPC_FEATURE_64,
> .icache_bsize = 128,
> .dcache_bsize = 128,
> @@ -659,55 +492,19 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffff0000,
> .pvr_value = 0x00370000,
> .cpu_name = "S-star",
> - .cpu_features = CPU_FTR_COMMON |
> - CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
> - CPU_FTR_HPTE_TABLE,
> + .cpu_features = CPU_FTR_POWER3_32,
> .cpu_user_features = COMMON_PPC | PPC_FEATURE_64,
> .icache_bsize = 128,
> .dcache_bsize = 128,
> .num_pmcs = 8,
> .cpu_setup = __setup_cpu_power3
> },
> -#endif /* CONFIG_PPC64BRIDGE */
> -#ifdef CONFIG_POWER4
> - { /* Power4 */
> - .pvr_mask = 0xffff0000,
> - .pvr_value = 0x00350000,
> - .cpu_name = "Power4",
> - .cpu_features = CPU_FTR_COMMON |
> - CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
> - CPU_FTR_HPTE_TABLE,
> - .cpu_user_features = COMMON_PPC | PPC_FEATURE_64,
> - .icache_bsize = 128,
> - .dcache_bsize = 128,
> - .num_pmcs = 8,
> - .cpu_setup = __setup_cpu_power4
> - },
> - { /* PPC970 */
> - .pvr_mask = 0xffff0000,
> - .pvr_value = 0x00390000,
> - .cpu_name = "PPC970",
> - .cpu_features = CPU_FTR_COMMON |
> - CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
> - CPU_FTR_HPTE_TABLE |
> - CPU_FTR_ALTIVEC_COMP | CPU_FTR_MAYBE_CAN_NAP,
> - .cpu_user_features = COMMON_PPC | PPC_FEATURE_64 |
> - PPC_FEATURE_ALTIVEC_COMP,
> - .icache_bsize = 128,
> - .dcache_bsize = 128,
> - .num_pmcs = 8,
> - .cpu_setup = __setup_cpu_ppc970
> - },
> { /* PPC970FX */
> .pvr_mask = 0xffff0000,
> .pvr_value = 0x003c0000,
> .cpu_name = "PPC970FX",
> - .cpu_features = CPU_FTR_COMMON |
> - CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
> - CPU_FTR_HPTE_TABLE |
> - CPU_FTR_ALTIVEC_COMP | CPU_FTR_MAYBE_CAN_NAP,
> - .cpu_user_features = COMMON_PPC | PPC_FEATURE_64 |
> - PPC_FEATURE_ALTIVEC_COMP,
> + .cpu_features = CPU_FTR_970_32,
> + .cpu_user_features = COMMON_PPC | PPC_FEATURE_64 |
> PPC_FEATURE_HAS_ALTIVEC_COMP,
> .icache_bsize = 128,
> .dcache_bsize = 128,
> .num_pmcs = 8,
> @@ -721,8 +518,7 @@ struct cpu_spec cpu_specs[] = {
> .cpu_name = "8xx",
> /* CPU_FTR_MAYBE_CAN_DOZE is possible,
> * if the 8xx code is there.... */
> - .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
> - CPU_FTR_USE_TB,
> + .cpu_features = CPU_FTR_8XX,
> .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
> .icache_bsize = 16,
> .dcache_bsize = 16,
> @@ -733,8 +529,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffffff00,
> .pvr_value = 0x00200200,
> .cpu_name = "403GC",
> - .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
> - CPU_FTR_USE_TB,
> + .cpu_features = CPU_FTR_40X,
> .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
> .icache_bsize = 16,
> .dcache_bsize = 16,
> @@ -743,8 +538,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffffff00,
> .pvr_value = 0x00201400,
> .cpu_name = "403GCX",
> - .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
> - CPU_FTR_USE_TB,
> + .cpu_features = CPU_FTR_40X,
> .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
> .icache_bsize = 16,
> .dcache_bsize = 16,
> @@ -753,8 +547,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffff0000,
> .pvr_value = 0x00200000,
> .cpu_name = "403G ??",
> - .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
> - CPU_FTR_USE_TB,
> + .cpu_features = CPU_FTR_40X,
> .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
> .icache_bsize = 16,
> .dcache_bsize = 16,
> @@ -763,8 +556,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffff0000,
> .pvr_value = 0x40110000,
> .cpu_name = "405GP",
> - .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
> - CPU_FTR_USE_TB,
> + .cpu_features = CPU_FTR_40X,
> .cpu_user_features = PPC_FEATURE_32 |
> PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
> .icache_bsize = 32,
> @@ -774,8 +566,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffff0000,
> .pvr_value = 0x40130000,
> .cpu_name = "STB03xxx",
> - .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
> - CPU_FTR_USE_TB,
> + .cpu_features = CPU_FTR_40X,
> .cpu_user_features = PPC_FEATURE_32 |
> PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
> .icache_bsize = 32,
> @@ -785,8 +576,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffff0000,
> .pvr_value = 0x41810000,
> .cpu_name = "STB04xxx",
> - .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
> - CPU_FTR_USE_TB,
> + .cpu_features = CPU_FTR_40X,
> .cpu_user_features = PPC_FEATURE_32 |
> PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
> .icache_bsize = 32,
> @@ -796,8 +586,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffff0000,
> .pvr_value = 0x41610000,
> .cpu_name = "NP405L",
> - .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
> - CPU_FTR_USE_TB,
> + .cpu_features = CPU_FTR_40X,
> .cpu_user_features = PPC_FEATURE_32 |
> PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
> .icache_bsize = 32,
> @@ -807,8 +596,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffff0000,
> .pvr_value = 0x40B10000,
> .cpu_name = "NP4GS3",
> - .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
> - CPU_FTR_USE_TB,
> + .cpu_features = CPU_FTR_40X,
> .cpu_user_features = PPC_FEATURE_32 |
> PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
> .icache_bsize = 32,
> @@ -818,8 +606,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffff0000,
> .pvr_value = 0x41410000,
> .cpu_name = "NP405H",
> - .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
> - CPU_FTR_USE_TB,
> + .cpu_features = CPU_FTR_40X,
> .cpu_user_features = PPC_FEATURE_32 |
> PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
> .icache_bsize = 32,
> @@ -829,8 +616,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffff0000,
> .pvr_value = 0x50910000,
> .cpu_name = "405GPr",
> - .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
> - CPU_FTR_USE_TB,
> + .cpu_features = CPU_FTR_40X,
> .cpu_user_features = PPC_FEATURE_32 |
> PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
> .icache_bsize = 32,
> @@ -840,8 +626,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffff0000,
> .pvr_value = 0x51510000,
> .cpu_name = "STBx25xx",
> - .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
> - CPU_FTR_USE_TB,
> + .cpu_features = CPU_FTR_40X,
> .cpu_user_features = PPC_FEATURE_32 |
> PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
> .icache_bsize = 32,
> @@ -851,8 +636,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffff0000,
> .pvr_value = 0x41F10000,
> .cpu_name = "405LP",
> - .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
> - CPU_FTR_USE_TB,
> + .cpu_features = CPU_FTR_40X,
> .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
> .icache_bsize = 32,
> .dcache_bsize = 32,
> @@ -861,8 +645,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffff0000,
> .pvr_value = 0x20010000,
> .cpu_name = "Virtex-II Pro",
> - .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
> - CPU_FTR_USE_TB,
> + .cpu_features = CPU_FTR_40X,
> .cpu_user_features = PPC_FEATURE_32 |
> PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
> .icache_bsize = 32,
> @@ -872,8 +655,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xffff0000,
> .pvr_value = 0x51210000,
> .cpu_name = "405EP",
> - .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
> - CPU_FTR_USE_TB,
> + .cpu_features = CPU_FTR_40X,
> .cpu_user_features = PPC_FEATURE_32 |
> PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
> .icache_bsize = 32,
> @@ -886,8 +668,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xf0000fff,
> .pvr_value = 0x40000850,
> .cpu_name = "440EP Rev. A",
> - .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
> - CPU_FTR_USE_TB,
> + .cpu_features = CPU_FTR_44X,
> .cpu_user_features = COMMON_PPC, /* 440EP has an FPU */
> .icache_bsize = 32,
> .dcache_bsize = 32,
> @@ -896,8 +677,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xf0000fff,
> .pvr_value = 0x400008d3,
> .cpu_name = "440EP Rev. B",
> - .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
> - CPU_FTR_USE_TB,
> + .cpu_features = CPU_FTR_44X,
> .cpu_user_features = COMMON_PPC, /* 440EP has an FPU */
> .icache_bsize = 32,
> .dcache_bsize = 32,
> @@ -906,8 +686,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xf0000fff,
> .pvr_value = 0x40000440,
> .cpu_name = "440GP Rev. B",
> - .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
> - CPU_FTR_USE_TB,
> + .cpu_features = CPU_FTR_44X,
> .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
> .icache_bsize = 32,
> .dcache_bsize = 32,
> @@ -916,8 +695,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xf0000fff,
> .pvr_value = 0x40000481,
> .cpu_name = "440GP Rev. C",
> - .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
> - CPU_FTR_USE_TB,
> + .cpu_features = CPU_FTR_44X,
> .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
> .icache_bsize = 32,
> .dcache_bsize = 32,
> @@ -926,8 +704,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xf0000fff,
> .pvr_value = 0x50000850,
> .cpu_name = "440GX Rev. A",
> - .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
> - CPU_FTR_USE_TB,
> + .cpu_features = CPU_FTR_44X,
> .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
> .icache_bsize = 32,
> .dcache_bsize = 32,
> @@ -936,8 +713,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xf0000fff,
> .pvr_value = 0x50000851,
> .cpu_name = "440GX Rev. B",
> - .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
> - CPU_FTR_USE_TB,
> + .cpu_features = CPU_FTR_44X,
> .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
> .icache_bsize = 32,
> .dcache_bsize = 32,
> @@ -946,8 +722,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xf0000fff,
> .pvr_value = 0x50000892,
> .cpu_name = "440GX Rev. C",
> - .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
> - CPU_FTR_USE_TB,
> + .cpu_features = CPU_FTR_44X,
> .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
> .icache_bsize = 32,
> .dcache_bsize = 32,
> @@ -956,8 +731,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xf0000fff,
> .pvr_value = 0x50000894,
> .cpu_name = "440GX Rev. F",
> - .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
> - CPU_FTR_USE_TB,
> + .cpu_features = CPU_FTR_44X,
> .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
> .icache_bsize = 32,
> .dcache_bsize = 32,
> @@ -966,8 +740,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0xff000fff,
> .pvr_value = 0x53000891,
> .cpu_name = "440SP Rev. A",
> - .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
> - CPU_FTR_USE_TB,
> + .cpu_features = CPU_FTR_44X,
> .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
> .icache_bsize = 32,
> .dcache_bsize = 32,
> @@ -979,7 +752,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_value = 0x81000000,
> .cpu_name = "e200z5",
> /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
> - .cpu_features = CPU_FTR_USE_TB,
> + .cpu_features = CPU_FTR_E200,
> .cpu_user_features = PPC_FEATURE_32 |
> PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_EFP_SINGLE |
> PPC_FEATURE_UNIFIED_CACHE,
> @@ -990,7 +763,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_value = 0x81100000,
> .cpu_name = "e200z6",
> /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
> - .cpu_features = CPU_FTR_USE_TB,
> + .cpu_features = CPU_FTR_E200,
> .cpu_user_features = PPC_FEATURE_32 |
> PPC_FEATURE_HAS_MMU | PPC_FEATURE_SPE_COMP |
> PPC_FEATURE_HAS_EFP_SINGLE |
> @@ -1002,8 +775,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_value = 0x80200000,
> .cpu_name = "e500",
> /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
> - .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
> - CPU_FTR_USE_TB,
> + .cpu_features = CPU_FTR_E500,
> .cpu_user_features = PPC_FEATURE_32 |
> PPC_FEATURE_HAS_MMU | PPC_FEATURE_SPE_COMP |
> PPC_FEATURE_HAS_EFP_SINGLE,
> @@ -1016,8 +788,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_value = 0x80210000,
> .cpu_name = "e500v2",
> /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
> - .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
> - CPU_FTR_USE_TB | CPU_FTR_BIG_PHYS,
> + .cpu_features = CPU_FTR_E500_2,
> .cpu_user_features = PPC_FEATURE_32 |
> PPC_FEATURE_HAS_MMU | PPC_FEATURE_SPE_COMP |
> PPC_FEATURE_HAS_EFP_SINGLE | PPC_FEATURE_HAS_EFP_DOUBLE,
> @@ -1031,7 +802,7 @@ struct cpu_spec cpu_specs[] = {
> .pvr_mask = 0x00000000,
> .pvr_value = 0x00000000,
> .cpu_name = "(generic PPC)",
> - .cpu_features = CPU_FTR_COMMON,
> + .cpu_features = CPU_FTR_GENERIC_32,
> .cpu_user_features = PPC_FEATURE_32,
> .icache_bsize = 32,
> .dcache_bsize = 32,
> Index: clean-cg/include/asm-powerpc/cputable.h
> ===================================================================
> --- /dev/null
> +++ clean-cg/include/asm-powerpc/cputable.h
> @@ -0,0 +1,475 @@
> +#ifndef __ASM_POWERPC_CPUTABLE_H
> +#define __ASM_POWERPC_CPUTABLE_H
> +
> +#ifdef __KERNEL__
> +#include <linux/config.h>
> +#include <asm/ppc_asm.h> /* for ASM_CONST */
> +
> +#define PPC_FEATURE_32 0x80000000
> +#define PPC_FEATURE_64 0x40000000
> +#define PPC_FEATURE_601_INSTR 0x20000000
> +#define PPC_FEATURE_HAS_ALTIVEC 0x10000000
> +#define PPC_FEATURE_HAS_FPU 0x08000000
> +#define PPC_FEATURE_HAS_MMU 0x04000000
> +#define PPC_FEATURE_HAS_4xxMAC 0x02000000
> +#define PPC_FEATURE_UNIFIED_CACHE 0x01000000
> +#define PPC_FEATURE_HAS_SPE 0x00800000
> +#define PPC_FEATURE_HAS_EFP_SINGLE 0x00400000
> +#define PPC_FEATURE_HAS_EFP_DOUBLE 0x00200000
> +
> +#ifndef __ASSEMBLY__
> +
> +/* This structure can grow, it's real size is used by head.S code
> + * via the mkdefs mechanism.
> + */
> +struct cpu_spec;
> +struct op_ppc64_model;
> +
> +#ifndef __powerpc64__
> +typedef void (*cpu_setup_t)(unsigned long offset, int cpu_nr,
> struct cpu_spec* spec);
> +#else /* __powerpc64__ */
> +typedef void (*cpu_setup_t)(unsigned long offset, struct
> cpu_spec* spec);
> +#endif /* __powerpc64__ */
> +
> +struct cpu_spec {
> + /* CPU is matched via (PVR & pvr_mask) == pvr_value */
> + unsigned int pvr_mask;
> + unsigned int pvr_value;
> +
> + char *cpu_name;
> + unsigned long cpu_features; /* Kernel features */
> + unsigned int cpu_user_features; /* Userland features */
> +
> + /* cache line sizes */
> + unsigned int icache_bsize;
> + unsigned int dcache_bsize;
> +
> + /* number of performance monitor counters */
> + unsigned int num_pmcs;
> +
> + /* this is called to initialize various CPU bits like L1 cache,
> + * BHT, SPD, etc... from head.S before branching to
> identify_machine
> + */
> + cpu_setup_t cpu_setup;
> +#ifdef __powerpc64__
> +
> + /* Used by oprofile userspace to select the right counters */
> + char *oprofile_cpu_type;
> +
> + /* Processor specific oprofile operations */
> + struct op_ppc64_model *oprofile_model;
> +#endif /* __powerpc64__ */
> +};
> +
> +extern struct cpu_spec cpu_specs[];
> +
> +#ifndef __powerpc64__
> +extern struct cpu_spec *cur_cpu_spec[];
> +#else /* __powerpc64__ */
> +extern struct cpu_spec *cur_cpu_spec;
> +#endif /* __powerpc64__ */
> +
> +#endif /* __ASSEMBLY__ */
> +
> +/* CPU kernel features */
> +
> +/* Retain the 32b definitions all use bottom half of word */
> +#define CPU_FTR_SPLIT_ID_CACHE ASM_CONST(0x0000000000000001)
> +#define CPU_FTR_L2CR ASM_CONST(0x0000000000000002)
> +#define CPU_FTR_SPEC7450 ASM_CONST(0x0000000000000004)
> +#define CPU_FTR_ALTIVEC ASM_CONST(0x0000000000000008)
> +#define CPU_FTR_TAU ASM_CONST(0x0000000000000010)
> +#define CPU_FTR_CAN_DOZE ASM_CONST(0x0000000000000020)
> +#define CPU_FTR_USE_TB ASM_CONST(0x0000000000000040)
> +#define CPU_FTR_604_PERF_MON ASM_CONST(0x0000000000000080)
> +#define CPU_FTR_601 ASM_CONST(0x0000000000000100)
> +#define CPU_FTR_HPTE_TABLE ASM_CONST(0x0000000000000200)
> +#define CPU_FTR_CAN_NAP ASM_CONST(0x0000000000000400)
> +#define CPU_FTR_L3CR ASM_CONST(0x0000000000000800)
> +#define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x0000000000001000)
> +#define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x0000000000002000)
> +#define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x0000000000004000)
> +#define CPU_FTR_NO_DPM ASM_CONST(0x0000000000008000)
> +#define CPU_FTR_HAS_HIGH_BATS ASM_CONST(0x0000000000010000)
> +#define CPU_FTR_NEED_COHERENT ASM_CONST(0x0000000000020000)
> +#define CPU_FTR_NO_BTIC ASM_CONST(0x0000000000040000)
> +#define CPU_FTR_BIG_PHYS ASM_CONST(0x0000000000080000)
> +
> +#ifdef __powerpc64__
> +/* Add the 64b processor unique features in the top half of the
> word */
> +#define CPU_FTR_SLB ASM_CONST(0x0000000100000000)
> +#define CPU_FTR_16M_PAGE ASM_CONST(0x0000000200000000)
> +#define CPU_FTR_TLBIEL ASM_CONST(0x0000000400000000)
> +#define CPU_FTR_NOEXECUTE ASM_CONST(0x0000000800000000)
> +#define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000001000000000)
> +#define CPU_FTR_IABR ASM_CONST(0x0000002000000000)
> +#define CPU_FTR_MMCRA ASM_CONST(0x0000004000000000)
> +/* unused ASM_CONST(0x0000008000000000) */
> +#define CPU_FTR_SMT ASM_CONST(0x0000010000000000)
> +#define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x0000020000000000)
> +#define CPU_FTR_LOCKLESS_TLBIE ASM_CONST(0x0000040000000000)
> +#define CPU_FTR_MMCRA_SIHV ASM_CONST(0x0000080000000000)
> +#define CPU_FTR_CTRL ASM_CONST(0x0000100000000000)
> +#endif
> +
> +#ifndef __ASSEMBLY__
> +
> +#define COMMON_USER_PPC64 (PPC_FEATURE_32 | PPC_FEATURE_64 | \
> + PPC_FEATURE_HAS_FPU | PPC_FEATURE_HAS_MMU)
> +
> +#define CPU_FTR_PPCAS_ARCH_V2_BASE (CPU_FTR_SLB | \
> + CPU_FTR_TLBIEL | CPU_FTR_NOEXECUTE | \
> + CPU_FTR_NODSISRALIGN | CPU_FTR_CTRL)
> +
> +/* iSeries doesn't support large pages */
> +#ifdef CONFIG_PPC_ISERIES
> +#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_PPCAS_ARCH_V2_BASE)
> +#else
> +#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_PPCAS_ARCH_V2_BASE |
> CPU_FTR_16M_PAGE)
> +#endif /* CONFIG_PPC_ISERIES */
> +
> +/* We only set the altivec features if the kernel was compiled
> with altivec
> + * support
> + */
> +#ifdef CONFIG_ALTIVEC
> +#define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC
> +#define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
> +#else
> +#define CPU_FTR_ALTIVEC_COMP 0
> +#define PPC_FEATURE_HAS_ALTIVEC_COMP 0
> +#endif
> +
> +/* We need to mark all pages as being coherent if we're SMP or we
> + * have a 74[45]x and an MPC107 host bridge.
> + */
> +#if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE)
> +#define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT
> +#else
> +#define CPU_FTR_COMMON 0
> +#endif
> +
> +/* The powersave features NAP & DOZE seems to confuse BDI when
> + debugging. So if a BDI is used, disable theses
> + */
> +#ifndef CONFIG_BDI_SWITCH
> +#define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE
> +#define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP
> +#else
> +#define CPU_FTR_MAYBE_CAN_DOZE 0
> +#define CPU_FTR_MAYBE_CAN_NAP 0
> +#endif
> +
> +#define CLASSIC_PPC (!defined(CONFIG_8xx) && !defined(CONFIG_4xx)
> && \
> + !defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \
> + !defined(CONFIG_BOOKE))
> +
> +enum {
> + CPU_FTR_PPC601 = CPU_FTR_COMMON | CPU_FTR_601 |
> CPU_FTR_HPTE_TABLE,
> + CPU_FTR_603 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
> + CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
> + CPU_FTR_MAYBE_CAN_NAP,
> + CPU_FTR_604 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
> + CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE,
> + CPU_FTR_740_NOTAU = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
> + CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
> + CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
> + CPU_FTR_740 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
> + CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
> + CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
> + CPU_FTR_750 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
> + CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
> + CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
> + CPU_FTR_750FX1 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
> + CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
> + CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
> + CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM,
> + CPU_FTR_750FX2 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
> + CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
> + CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
> + CPU_FTR_NO_DPM,
> + CPU_FTR_750FX = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
> + CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
> + CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
> + CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS,
> + CPU_FTR_750GX = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
> + CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
> + CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
> + CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS,
> + CPU_FTR_7400_NOTAU = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
> + CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
> + CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
> + CPU_FTR_MAYBE_CAN_NAP,
> + CPU_FTR_7400 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
> + CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
> + CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
> + CPU_FTR_MAYBE_CAN_NAP,
> + CPU_FTR_7450_20 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
> + CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
> + CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
> + CPU_FTR_NEED_COHERENT,
> + CPU_FTR_7450_21 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
> + CPU_FTR_USE_TB |
> + CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
> + CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
> + CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP |
> + CPU_FTR_NEED_COHERENT,
> + CPU_FTR_7450_23 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
> + CPU_FTR_USE_TB |
> + CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
> + CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
> + CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT,
> + CPU_FTR_7455_1 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
> + CPU_FTR_USE_TB |
> + CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
> + CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
> CPU_FTR_HAS_HIGH_BATS |
> + CPU_FTR_NEED_COHERENT,
> + CPU_FTR_7455_20 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
> + CPU_FTR_USE_TB |
> + CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
> + CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
> + CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP |
> + CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS,
> + CPU_FTR_7455 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
> + CPU_FTR_USE_TB |
> + CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
> + CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
> + CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
> + CPU_FTR_NEED_COHERENT,
> + CPU_FTR_7447_10 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
> + CPU_FTR_USE_TB |
> + CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
> + CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
> + CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
> + CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC,
> + CPU_FTR_7447 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
> + CPU_FTR_USE_TB |
> + CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
> + CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
> + CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
> + CPU_FTR_NEED_COHERENT,
> + CPU_FTR_7447A = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
> + CPU_FTR_USE_TB |
> + CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
> + CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
> + CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
> + CPU_FTR_NEED_COHERENT,
> + CPU_FTR_82XX = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
> + CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB,
> + CPU_FTR_G2_LE = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
> + CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP |
> CPU_FTR_HAS_HIGH_BATS,
> + CPU_FTR_E300 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
> + CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP |
> CPU_FTR_HAS_HIGH_BATS,
> + CPU_FTR_CLASSIC32 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
> + CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
> + CPU_FTR_POWER3_32 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
> + CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
> + CPU_FTR_POWER4_32 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
> + CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
> + CPU_FTR_970_32 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
> + CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_ALTIVEC_COMP |
> + CPU_FTR_MAYBE_CAN_NAP,
> + CPU_FTR_8XX = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
> + CPU_FTR_40X = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
> + CPU_FTR_44X = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
> + CPU_FTR_E200 = CPU_FTR_USE_TB,
> + CPU_FTR_E500 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
> + CPU_FTR_E500_2 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
> + CPU_FTR_BIG_PHYS,
> + CPU_FTR_GENERIC_32 = CPU_FTR_COMMON,
> +#ifdef __powerpc64__
> + CPU_FTR_POWER3 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
> + CPU_FTR_HPTE_TABLE | CPU_FTR_IABR,
> + CPU_FTR_RS64 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
> + CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
> + CPU_FTR_MMCRA | CPU_FTR_CTRL,
> + CPU_FTR_POWER4 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
> + CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_MMCRA,
> + CPU_FTR_PPC970 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
> + CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 |
> + CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA,
> + CPU_FTR_POWER5 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
> + CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 |
> + CPU_FTR_MMCRA | CPU_FTR_SMT |
> + CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE |
> + CPU_FTR_MMCRA_SIHV,
> + CPU_FTR_CELL = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
> + CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 |
> + CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT,
> + CPU_FTR_COMPATIBLE = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
> + CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2,
> +#endif
> + CPU_FTR_POSSIBLE =
> +#if CLASSIC_PPC
> + CPU_FTR_601 | CPU_FTR_603 | CPU_FTR_604 | CPU_FTR_740_NOTAU |
> + CPU_FTR_740 | CPU_FTR_750 | CPU_FTR_750FX1 |
> + CPU_FTR_750FX2 | CPU_FTR_750FX | CPU_FTR_750GX |
> + CPU_FTR_7400_NOTAU | CPU_FTR_7400 | CPU_FTR_7450_20 |
> + CPU_FTR_7450_21 | CPU_FTR_7450_23 | CPU_FTR_7455_1 |
> + CPU_FTR_7455_20 | CPU_FTR_7455 | CPU_FTR_7447_10 |
> + CPU_FTR_7447 | CPU_FTR_7447A | CPU_FTR_82XX |
> + CPU_FTR_G2_LE | CPU_FTR_E300 | CPU_FTR_CLASSIC32 |
> +#else
> + CPU_FTR_GENERIC_32 |
> +#endif
> +#ifdef CONFIG_PPC64BRIDGE
> + CPU_FTR_POWER3_32 |
> +#endif
> +#ifdef CONFIG_POWER4
> + CPU_FTR_POWER4_32 | CPU_FTR_970_32 |
> +#endif
> +#ifdef CONFIG_8xx
> + CPU_FTR_8XX |
> +#endif
> +#ifdef CONFIG_40x
> + CPU_FTR_40X |
> +#endif
> +#ifdef CONFIG_44x
> + CPU_FTR_44X |
> +#endif
> +#ifdef CONFIG_FSL_BOOKE
> + CPU_FTR_E200 | CPU_FTR_E500 | CPU_FTR_E500_2 |
> +#endif
> +#ifdef CONFIG_CPU_POWER3
> + CPU_FTR_POWER3 |
> +#endif
> +#ifdef CONFIG_CPU_RS64
> + CPU_FTR_RS64 |
> +#endif
> +#ifdef CONFIG_CPU_POWER4
> + CPU_FTR_POWER4 |
> +#endif
> +#ifdef CONFIG_CPU_PPC970
> + CPU_FTR_PPC970 |
> +#endif
> +#ifdef CONFIG_CPU_POWER5
> + CPU_FTR_POWER5 |
> +#endif
> +#ifdef CONFIG_CPU_CELL
> + CPU_FTR_CELL |
> +#endif
> + 0,
> + CPU_FTR_ALWAYS =
> +#if CLASSIC_PPC
> + CPU_FTR_601 & CPU_FTR_603 & CPU_FTR_604 & CPU_FTR_740_NOTAU &
> + CPU_FTR_740 & CPU_FTR_750 & CPU_FTR_750FX1 &
> + CPU_FTR_750FX2 & CPU_FTR_750FX & CPU_FTR_750GX &
> + CPU_FTR_7400_NOTAU & CPU_FTR_7400 & CPU_FTR_7450_20 &
> + CPU_FTR_7450_21 & CPU_FTR_7450_23 & CPU_FTR_7455_1 &
> + CPU_FTR_7455_20 & CPU_FTR_7455 & CPU_FTR_7447_10 &
> + CPU_FTR_7447 & CPU_FTR_7447A & CPU_FTR_82XX &
> + CPU_FTR_G2_LE & CPU_FTR_E300 & CPU_FTR_CLASSIC32 &
> +#else
> + CPU_FTR_GENERIC_32 &
> +#endif
> +#ifdef CONFIG_PPC64BRIDGE
> + CPU_FTR_POWER3_32 &
> +#endif
> +#ifdef CONFIG_POWER4
> + CPU_FTR_POWER4_32 & CPU_FTR_970_32 &
> +#endif
> +#ifdef CONFIG_8xx
> + CPU_FTR_8XX &
> +#endif
> +#ifdef CONFIG_40x
> + CPU_FTR_40X &
> +#endif
> +#ifdef CONFIG_44x
> + CPU_FTR_44X &
> +#endif
> +#ifdef CONFIG_FSL_BOOKE
> + CPU_FTR_E200 & CPU_FTR_E500 & CPU_FTR_E500_2 &
> +#endif
> +#ifdef CONFIG_CPU_POWER3
> + CPU_FTR_POWER3 &
> +#endif
> +#ifdef CONFIG_CPU_RS64
> + CPU_FTR_RS64 &
> +#endif
> +#ifdef CONFIG_CPU_POWER4
> + CPU_FTR_POWER4 &
> +#endif
> +#ifdef CONFIG_CPU_PPC970
> + CPU_FTR_PPC970 &
> +#endif
> +#ifdef CONFIG_CPU_POWER5
> + CPU_FTR_POWER5 &
> +#endif
> +#ifdef CONFIG_CPU_CELL
> + CPU_FTR_CELL &
> +#endif
> + CPU_FTR_POSSIBLE,
> +};
> +
> +static inline int cpu_has_feature(unsigned long feature)
> +{
> + return (CPU_FTR_ALWAYS & feature) ||
> + (CPU_FTR_POSSIBLE
> +#ifndef __powerpc64__
> + & cur_cpu_spec[0]->cpu_features
> +#else
> + & cur_cpu_spec->cpu_features
> +#endif
> + & feature);
> +}
> +
> +#endif /* __ASSEMBLY */
> +
> +#ifdef __ASSEMBLY__
> +
> +#define BEGIN_FTR_SECTION 98:
> +
> +#ifndef __powerpc64__
> +#define END_FTR_SECTION(msk, val) \
> +99: \
> + .section __ftr_fixup,"a"; \
> + .align 2; \
> + .long msk; \
> + .long val; \
> + .long 98b; \
> + .long 99b; \
> + .previous
> +#else /* __powerpc64__ */
> +#define END_FTR_SECTION(msk, val) \
> +99: \
> + .section __ftr_fixup,"a"; \
> + .align 3; \
> + .llong msk; \
> + .llong val; \
> + .llong 98b; \
> + .llong 99b; \
> + .previous
> +#endif /* __powerpc64__ */
> +
> +#else
> +
> +#define BEGIN_FTR_SECTION "98:\n"
> +
> +#ifndef __powerpc64__
> +#define END_FTR_SECTION(msk, val) \
> +"99:\n" \
> +" .section __ftr_fixup,\"a\";\n" \
> +" .align 2;\n" \
> +" .long "#msk";\n" \
> +" .long "#val";\n" \
> +" .long 98b;\n" \
> +" .long 99b;\n" \
> +" .previous\n"
> +#else /* __powerpc64__ */
> +#define END_FTR_SECTION(msk, val) \
> +"99:\n" \
> +" .section __ftr_fixup,\"a\";\n" \
> +" .align 3;\n" \
> +" .llong "#msk";\n" \
> +" .llong "#val";\n" \
> +" .llong 98b;\n" \
> +" .llong 99b;\n" \
> +" .previous\n"
> +#endif /* __powerpc64__ */
> +
> +#endif /* __ASSEMBLY__ */
> +
> +#define END_FTR_SECTION_IFSET(msk) END_FTR_SECTION((msk), (msk))
> +#define END_FTR_SECTION_IFCLR(msk) END_FTR_SECTION((msk), 0)
> +
> +#endif /* __KERNEL__ */
> +#endif /* __ASM_POWERPC_CPUTABLE_H */
> Index: clean-cg/include/asm-ppc/cputable.h
> ===================================================================
> --- clean-cg.orig/include/asm-ppc/cputable.h
> +++ /dev/null
> @@ -1,128 +0,0 @@
> -/*
> - * include/asm-ppc/cputable.h
> - *
> - * Copyright (C) 2001 Ben. Herrenschmidt (benh@kernel.crashing.org)
> - *
> - * This program is free software; you can redistribute it and/or
> - * modify it under the terms of the GNU General Public License
> - * as published by the Free Software Foundation; either version
> - * 2 of the License, or (at your option) any later version.
> - */
> -
> -#ifndef __ASM_PPC_CPUTABLE_H
> -#define __ASM_PPC_CPUTABLE_H
> -
> -/* Exposed to userland CPU features */
> -#define PPC_FEATURE_32 0x80000000
> -#define PPC_FEATURE_64 0x40000000
> -#define PPC_FEATURE_601_INSTR 0x20000000
> -#define PPC_FEATURE_HAS_ALTIVEC 0x10000000
> -#define PPC_FEATURE_HAS_FPU 0x08000000
> -#define PPC_FEATURE_HAS_MMU 0x04000000
> -#define PPC_FEATURE_HAS_4xxMAC 0x02000000
> -#define PPC_FEATURE_UNIFIED_CACHE 0x01000000
> -#define PPC_FEATURE_HAS_SPE 0x00800000
> -#define PPC_FEATURE_HAS_EFP_SINGLE 0x00400000
> -#define PPC_FEATURE_HAS_EFP_DOUBLE 0x00200000
> -
> -#ifdef __KERNEL__
> -
> -#ifndef __ASSEMBLY__
> -
> -/* This structure can grow, it's real size is used by head.S code
> - * via the mkdefs mecanism.
> - */
> -struct cpu_spec;
> -
> -typedef void (*cpu_setup_t)(unsigned long offset, int cpu_nr,
> struct cpu_spec* spec);
> -
> -struct cpu_spec {
> - /* CPU is matched via (PVR & pvr_mask) == pvr_value */
> - unsigned int pvr_mask;
> - unsigned int pvr_value;
> -
> - char *cpu_name;
> - unsigned int cpu_features; /* Kernel features */
> - unsigned int cpu_user_features; /* Userland features */
> -
> - /* cache line sizes */
> - unsigned int icache_bsize;
> - unsigned int dcache_bsize;
> -
> - /* number of performance monitor counters */
> - unsigned int num_pmcs;
> -
> - /* this is called to initialize various CPU bits like L1 cache,
> - * BHT, SPD, etc... from head.S before branching to
> identify_machine
> - */
> - cpu_setup_t cpu_setup;
> -};
> -
> -extern struct cpu_spec cpu_specs[];
> -extern struct cpu_spec *cur_cpu_spec[];
> -
> -static inline unsigned int cpu_has_feature(unsigned int feature)
> -{
> - return cur_cpu_spec[0]->cpu_features & feature;
> -}
> -
> -#endif /* __ASSEMBLY__ */
> -
> -/* CPU kernel features */
> -#define CPU_FTR_SPLIT_ID_CACHE 0x00000001
> -#define CPU_FTR_L2CR 0x00000002
> -#define CPU_FTR_SPEC7450 0x00000004
> -#define CPU_FTR_ALTIVEC 0x00000008
> -#define CPU_FTR_TAU 0x00000010
> -#define CPU_FTR_CAN_DOZE 0x00000020
> -#define CPU_FTR_USE_TB 0x00000040
> -#define CPU_FTR_604_PERF_MON 0x00000080
> -#define CPU_FTR_601 0x00000100
> -#define CPU_FTR_HPTE_TABLE 0x00000200
> -#define CPU_FTR_CAN_NAP 0x00000400
> -#define CPU_FTR_L3CR 0x00000800
> -#define CPU_FTR_L3_DISABLE_NAP 0x00001000
> -#define CPU_FTR_NAP_DISABLE_L2_PR 0x00002000
> -#define CPU_FTR_DUAL_PLL_750FX 0x00004000
> -#define CPU_FTR_NO_DPM 0x00008000
> -#define CPU_FTR_HAS_HIGH_BATS 0x00010000
> -#define CPU_FTR_NEED_COHERENT 0x00020000
> -#define CPU_FTR_NO_BTIC 0x00040000
> -#define CPU_FTR_BIG_PHYS 0x00080000
> -
> -#ifdef __ASSEMBLY__
> -
> -#define BEGIN_FTR_SECTION 98:
> -
> -#define END_FTR_SECTION(msk, val) \
> -99: \
> - .section __ftr_fixup,"a"; \
> - .align 2; \
> - .long msk; \
> - .long val; \
> - .long 98b; \
> - .long 99b; \
> - .previous
> -
> -#else
> -
> -#define BEGIN_FTR_SECTION "98:\n"
> -#define END_FTR_SECTION(msk, val) \
> -"99:\n" \
> -" .section __ftr_fixup,\"a\";\n" \
> -" .align 2;\n" \
> -" .long "#msk";\n" \
> -" .long "#val";\n" \
> -" .long 98b;\n" \
> -" .long 99b;\n" \
> -" .previous\n"
> -
> -
> -#endif /* __ASSEMBLY__ */
> -
> -#define END_FTR_SECTION_IFSET(msk) END_FTR_SECTION((msk), (msk))
> -#define END_FTR_SECTION_IFCLR(msk) END_FTR_SECTION((msk), 0)
> -
> -#endif /* __ASM_PPC_CPUTABLE_H */
> -#endif /* __KERNEL__ */
> -
>
^ permalink raw reply
* [PATCH] Remove arch/ppc/syslib/ppc4xx_pm.c
From: Alexey Dobriyan @ 2005-09-14 20:10 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev, Armin Kuster, Domen Puncer
From: Domen Puncer <domen@coderock.org>
Remove nowhere referenced file (grep ppc4xx_pm -r . didn't find anything)
Signed-off-by: Domen Puncer <domen@coderock.org>
Signed-off-by: Alexey Dobriyan <adobriyan@gmail.com>
---
arch/ppc/syslib/ppc4xx_pm.c | 47 --------------------------------------------
1 files changed, 47 deletions(-)
--- a/arch/ppc/syslib/ppc4xx_pm.c 2005-09-14 19:05:25.000000000 +0400
+++ /dev/null 1970-01-01 00:00:00.000000000 +0000
@@ -1,47 +0,0 @@
-/*
- * Author: Armin Kuster <akuster@mvista.com>
- *
- * 2002 (c) MontaVista, Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- *
- * This an attempt to get Power Management going for the IBM 4xx processor.
- * This was derived from the ppc4xx._setup.c file
- */
-
-#include <linux/config.h>
-#include <linux/init.h>
-
-#include <asm/ibm4xx.h>
-
-void __init
-ppc4xx_pm_init(void)
-{
-
- unsigned int value = 0;
-
- /* turn off unused hardware to save power */
-#ifdef CONFIG_405GP
- value |= CPM_DCP; /* CodePack */
-#endif
-
-#if !defined(CONFIG_IBM_OCP_GPIO)
- value |= CPM_GPIO0;
-#endif
-
-#if !defined(CONFIG_PPC405_I2C_ADAP)
- value |= CPM_IIC0;
-#ifdef CONFIG_STB03xxx
- value |= CPM_IIC1;
-#endif
-#endif
-
-
-#if !defined(CONFIG_405_DMA)
- value |= CPM_DMA;
-#endif
-
- mtdcr(DCRN_CPMFR, value);
-
-}
^ permalink raw reply
* Re: gdb hangs on Linux 2.6.11 on 8xx
From: Marcelo Tosatti @ 2005-09-14 20:55 UTC (permalink / raw)
To: Aristeu Sergio Rozanski Filho; +Cc: linuxppc-embedded
In-Reply-To: <20050914154218.GA4335@oops.ghostprotocols.net>
On Wed, Sep 14, 2005 at 12:42:18PM -0300, Aristeu Sergio Rozanski Filho wrote:
> Hi Marcelo,
>
> > flash_test is trying to handle a signal, can you print some information
> > about it in get_signal_to_deliver (before ptrace_stop), such as si_signo:
> >
> > typedef struct siginfo {
> > int si_signo;
> > int si_errno;
> > int si_code;
> >
> > ptrace_stop() calls do_notify_parent_cldstop() to wakeup gdb, maybe
> > there's something wrong during wakeup?
> >
> > The box locks up completly or its just gdb that freezes?
> seems it's more simple than I thought: seems to be a problem with serial
> console as I'm able to use gdb using ssh
> Is serial console (using ttyCPM) supposed to work with gdb?
Using a different device than the one used by the serial console? Yes,
think so..
^ permalink raw reply
* Re: gdb hangs on Linux 2.6.11 on 8xx
From: Aristeu Sergio Rozanski Filho @ 2005-09-14 21:30 UTC (permalink / raw)
To: Marcelo Tosatti; +Cc: linuxppc-embedded
In-Reply-To: <20050914205521.GA9808@dmt.cnet>
> Using a different device than the one used by the serial console? Yes,
> think so..
no, I'm not trying to use gdb over serial... :)
--
Aristeu
^ permalink raw reply
* Re: [PATCH] powerpc: merge include/asm/cputable.h
From: Arnd Bergmann @ 2005-09-14 23:58 UTC (permalink / raw)
To: Kumar Gala
Cc: linuxppc-dev, pantelis.antoniou, linuxppc64-dev,
linuxppc-embedded
In-Reply-To: <06F93AF6-7AF8-4320-B9E3-CBF9EA333403@freescale.com>
On Middeweken 14 September 2005 21:11, Kumar Gala wrote:
> I not sure I understand what the introduction of the enum's gets us.
>
It doesn't have to be an enum, it could just as well be a #define,
if we find that to be better in some way (maybe compile-time).
The general idea is to convert run-time checks into compile-time
checks in order to improve the running kernel. If you have
// start code
enum {
FEATURE_1 = 1,
FEATURE_2 = 2,
PLATFORM_1 = FEATURE_1,
PLATFORM_2 = FEATURE_2,
PLATFORM_3 = FEATURE_1 | FEATURE_2,
FEATURE_POSSIBLE =
#ifdef CONFIG_PLATFORM_1
PLATFORM_1 |
#endif
#ifdef CONFIG_FEATURE_2
PLATFORM_2 |
#endif
#ifdef CONFIG_FEATURE_3
PLATFORM_3 |
#endif
0,
FEATURE_ALWAYS =
#ifdef CONFIG_PLATFORM_1
PLATFORM_1 &
#endif
#ifdef CONFIG_PLATFORM_2
PLATFORM_2 &
#endif
#ifdef CONFIG_PLATFORM_3
PLATFORM_3 &
#endif
FEATURE_POSSIBLE,
};
static inline int have_feature(unsigned long feature)
{
return (FEATURE_ALWAYS & feature) ||
(FEATURE_POSSIBLE & runtime_feature & feature);
}
int foo();
int bar();
int main(void)
{
if (have_feature(FEATURE_1))
return foo();
if (have_feature(FEATURE_2))
return bar();
return 0;
}
// end code
Then gcc will produce optimal object code for any combination
of CONFIG_PLATFORM_{1,2,3}. Of course I have to admit that the
header file is not exactly elegant ;-).
Arnd <><
^ permalink raw reply
* A question about the /dev/ide
From: FCG WANG Baohua @ 2005-09-15 1:57 UTC (permalink / raw)
To: wd; +Cc: linuxppc-embedded
Dear all:
I had use the UPM of MPC8270 to create the device driver of my pcmcia =
CF card.=20
How to create the "/dev/hda" device nodes? I had only "/dev/ide" =
device nodes, I want to use command like "mkswap /dev/hda4".
When I use "mkswap /dev/ide/host0/bus0/target0/lun0/part1p4", it shows =
the "No such file or directory" message. How can I create=20
the right device nodes? thanks!
When it booted, it showed the following message:
Uniform Multi-Platform E-IDE driver Revision: 7.00beta4-2.4
ide: Assuming 66MHz system bus speed for PIO modes
ide0: MPC82xx IDE interface
Probing IDE interface ide0...
hda: STI Flash 7.2.0, CFA DISK drive
ide0 at 0xc900d800-0xc900d807,0xc900d80e on irq 24
hda: attached ide-disk driver.
hda: 250880 sectors (128 MB), CHS=3D980/8/32
Partition check:
Partition check:
When using "fdisk -l" it shows the following message:
Disk /dev/ide/host0/bus0/target0/lun0/disc: 128 MB, 128450560 =
bytes
8 heads, 32 sectors/track, 980 cylinders
Units =3D cylinders of 256 * 512 =3D 131072 bytes
Device Boot Start End =
Blocks Id System
/dev/ide/host0/bus0/target0/lun0/part1 * 1 972 =
124400 6 FAT16
When use "p" option of "fdisk", it shows the following message:
Disk /dev/ide/host0/bus0/target0/lun0/part1: 127 MB, 127385600 =
bytes
8 heads, 32 sectors/track, 971 cylinders
Units =3D cylinders of 256 * 512 =3D 131072 bytes
Device Boot =
Start End Blocks Id System
/dev/ide/host0/bus0/target0/lun0/part1p1 1 16 =
2032 83 Linux
/dev/ide/host0/bus0/target0/lun0/part1p2 17 32 =
2048 83 Linux=20
/dev/ide/host0/bus0/target0/lun0/part1p3 33 788 =
96768 83 Linux=20
/dev/ide/host0/bus0/target0/lun0/part1p4 789 971 =
23424 83 Linux
=20
^ permalink raw reply
* [PATCH] powerpc: don't execute a temporary comment
From: Stephen Rothwell @ 2005-09-15 6:04 UTC (permalink / raw)
To: paulus; +Cc: ppc-dev, ppc64-dev
Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
---
arch/ppc/Makefile | 2 +-
arch/ppc64/Makefile | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
--
Cheers,
Stephen Rothwell sfr@canb.auug.org.au
http://www.canb.auug.org.au/~sfr/
86f7688825b1f1e6fa4c43bce001b2a232f7d1bc
diff --git a/arch/ppc/Makefile b/arch/ppc/Makefile
--- a/arch/ppc/Makefile
+++ b/arch/ppc/Makefile
@@ -102,9 +102,9 @@ define archhelp
@echo ' *_defconfig - Select default config from arch/$(ARCH)/ppc/configs'
endef
+# arch/$(ARCH)/include is a temporary hack until we have migrated to asm-powerpc
archclean:
$(Q)$(MAKE) $(clean)=arch/ppc/boot
- # Temporary hack until we have migrated to asm-powerpc
$(Q)rm -rf arch/$(ARCH)/include
archprepare: checkbin
diff --git a/arch/ppc64/Makefile b/arch/ppc64/Makefile
--- a/arch/ppc64/Makefile
+++ b/arch/ppc64/Makefile
@@ -113,9 +113,9 @@ defaultimage-$(CONFIG_PPC_ISERIES) := vm
KBUILD_IMAGE := $(defaultimage-y)
all: $(KBUILD_IMAGE)
+# arch/$(ARCH)/include is a temporary hack until we have migrated to asm-powerpc
archclean:
$(Q)$(MAKE) $(clean)=$(boot)
- # Temporary hack until we have migrated to asm-powerpc
$(Q)rm -rf arch/$(ARCH)/include
^ permalink raw reply
* How to use kerberos in ELDK
From: JohnsonCheng @ 2005-09-15 6:28 UTC (permalink / raw)
To: linux-ppc-embedded
[-- Attachment #1: Type: text/plain, Size: 184 bytes --]
Dear All,
I have loadload ELDK-3.1.1 (ppc-2005-03-07 & ppc-2005-03-07-src), but
whatever I try it, it doesn't work.
Do anybody know how to use it?
Thanks,
Johnson Cheng
[-- Attachment #2: Type: text/html, Size: 3109 bytes --]
^ permalink raw reply
* MPC5200 BestComm
From: zhonglei @ 2005-09-15 7:10 UTC (permalink / raw)
To: linuxppc-dev
hi:
My BestComm driver encounter the TEA.Please give
me a help!
The register values are as follows:
/**********************************************/
Setting BestComm Interface to the Local Plus
Bus......Set GR=001
starts DMA when 0x000001f3 bytes!
[ OK ]
MPC5xxx_MBAR+0x3C04 is 0x00000140
MPC5xxx_MBAR+0x3C08 is 0x03010002
MPC5xxx_MBAR+0x3C0C is 0x00000101
MPC5xxx_MBAR+0x3C48 is 0x01000000
MPC5xxx_MBAR+0x3C4C is 0x000001F3
MPC5xxx_MBAR+0x3C00 is 0x00000010
Starting BestComm setting......
TaskSetup......[ OK ]
LPRDTaskId=0x00000004
BestComm request_irq
succeed!MPC5xxx_SDMA_IRQ_BASE+LPRDTaskId=0x00000019
TaskStart running ......[ OK ]
htm_open: LPRDTaskId task 4 started
Kick off FIFO!
irq is entered!
TaskIntStatus=0xFFFFFFFF
End of irq!
MPC5xxx_MBAR+0x1F64 is 0x00000007
MPC5xxx_MBAR+0x1F68 is 0x00007121 // this is
the priority setting
MPC5xxx_MBAR+0x0500 is 0x0AFFFD00
MPC5xxx_MBAR+0x0504 is 0x00000000
MPC5xxx_MBAR+0x0508 is 0x00000000
MPC5xxx_MBAR+0x050C is 0x00000000
MPC5xxx_MBAR+0x0510 is 0x00D01001
MPC5xxx_MBAR+0x0514 is 0x00010FFF
MPC5xxx_MBAR+0x0518 is 0x00000000
MPC5xxx_MBAR+0x051C is 0x00000000
MPC5xxx_MBAR+0x0524 is 0x00000001
MPC5xxx_MBAR+0x0528 is 0x00000000
MPC5xxx_MBAR+0x052C is 0x00002000
MPC5xxx_MBAR+0x0530 is 0x00800000
MPC5xxx_MBAR+0x0538 is 0x00000000
MPC5xxx_MBAR+0x3C44 is 0x00020000
MPC5xxx_MBAR+0x3C48 is 0x01000000
MPC5xxx_MBAR+0x3C4C is 0x000001F3
MPC5xxx_MBAR+0x3C50 is 0x00000008 // readptr is
correct (I set bestcomm transfer 8 bytes from fifo
LPTaskParam.Size.NumBytes = 8;)
MPC5xxx_MBAR+0x3C54 is 0x00000010 // writeptr is
correct
MPC5xxx_MBAR+0x3C14 is 0x01000010 // bytedone is
correct
MPC5xxx_MBAR+0x1218 is 0xFFFFFFE3
MPC5xxx_MBAR+0x1214 is 0x14000000 // a TEA on
task 4 happens!!!
MPC5xxx_MBAR+0x1210 is 0x0F0F0001
MPC5xxx_MBAR+0x121C is 0x03002000
MPC5xxx_MBAR+0x1220 is 0x20C2C3C3
MPC5xxx_MBAR+0x1224 is 0x204400C5
MPC5xxx_MBAR+0x1228 is 0x00000000
MPC5xxx_MBAR+0x122C is 0x00000000
MPC5xxx_MBAR+0x1230 is 0x00000000
MPC5xxx_MBAR+0x1234 is 0x00000000
MPC5xxx_MBAR+0x1238 is 0x00000000
MPC5xxx_MBAR+0x123C is 0x07000006
MPC5xxx_MBAR+0x1240 is 0x05000000
MPC5xxx_MBAR+0x1244 is 0x00000000
MPC5xxx_MBAR+0x1248 is 0x00000000
MPC5xxx_MBAR+0x124C is 0x07000000
MPC5xxx_MBAR+0x1250 is 0x00000000
MPC5xxx_MBAR+0x1254 is 0x00000000
MPC5xxx_MBAR+0x1258 is 0x00000000
MPC5xxx_MBAR+0x1F48 is 0x00000103 // data tenure
time-out and address tenure time-out
MPC5xxx_MBAR+0x1F58 is 0x0FFFFFFF
MPC5xxx_MBAR+0x1F5C is 0x0FFFFFFF
MPC5xxx_MBAR+0x1F50 is 0xC1C24CC0 // captured
address
MPC5xxx_MBAR+0x1F54 is 0x00000062 // captured
signal
/**********************************************/
Please give me a help!!!!
Thanks a lot!
BestRegards
zhonglei
^ permalink raw reply
* Re: How to use kerberos in ELDK
From: Wolfgang Denk @ 2005-09-15 7:08 UTC (permalink / raw)
To: JohnsonCheng; +Cc: linux-ppc-embedded
In-Reply-To: <20050915062857.B598968263@ozlabs.org>
In message <20050915062857.B598968263@ozlabs.org> you wrote:
>
> I have loadload ELDK-3.1.1 (ppc-2005-03-07 & ppc-2005-03-07-src), but
> whatever I try it, it doesn't work.
Can you please provide a specific example command you tried (and make
sure that it's working in a standard Linux environment), and post it
with a complete list of all output and error messages it produces?
Best regards,
Wolfgang Denk
--
Software Engineering: Embedded and Realtime Systems, Embedded Linux
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de
Calm down, it's *__only* ones and zeroes.
^ permalink raw reply
* Re: Help on 8260 board
From: Tore Martin Hagen @ 2005-09-15 8:24 UTC (permalink / raw)
To: prabha.j; +Cc: linuxppc-embedded
In-Reply-To: <OF29F8842B.21C92BA3-ON6525707B.0016F392-6525707B.0017A365@tcs.com>
Hi,
To change u-boot for your needs you will need to do approximately the
following:
copy include/configs/MPC8260ADS.h to include/configs/YOURBOARD8260.h
Print out the the file and sit down with the 8260 ref. manual. Adjust
the YOURBOARD8260.h to fit your needs. (If you are not a HW designer
this will definitely take you some time)
Added a new directory
board/yourboard8260
copied the following files from board/mpc8266ads to board/fox8275:
config.mk
flash.c
Makefile
mpc8260ads.c -> yourboard8260.c
u-boot.lds
Changed the files to fit the your board.
Changed the main Makefile to support a new target
> YOURBOARD8260_config: unconfig
> @./mkconfig $(@:_config=) ppc mpc8260 yourboard8260
good luck
^ permalink raw reply
* Re: __switch_to test-and-branch ALTIVEC specific?
From: Segher Boessenkool @ 2005-09-15 8:21 UTC (permalink / raw)
To: Marcelo Tosatti; +Cc: linuxppc-dev, cort, linux-ppc-embedded
In-Reply-To: <20050913203555.GB18639@dmt.cnet>
>> This probably has to due with what happens on a G4 system with a
>> kernel not build with Altivec.. However, I dont remember exactly what
>> behavior is desired.
A kernel not build with AltiVec support will just
SIGILL any user process that tries to use it (and
MSR[VEC] = 0).
The code here can safely be #ifdef'ed out (but note
I only looked at the code, I didn't test it ;-) )
Segher
^ permalink raw reply
* Re: A question about the /dev/ide
From: Clemens Koller @ 2005-09-15 10:41 UTC (permalink / raw)
To: FCG WANG Baohua; +Cc: linuxppc-embedded
In-Reply-To: <A9DE2BAF233E444FA9C5E77A5825A01E86506C@ydmail.sbell.com.cn>
Hello, Wang Baohua!
FCG WANG Baohua wrote:
> Dear all:
> I had use the UPM of MPC8270 to create the device driver of my pcmcia CF card.
Just an idea: There are IDE-to-CF adapters and PCI-IDE adapters with working drivers.
(for evaluation)
> How to create the "/dev/hda" device nodes? I had only "/dev/ide" device nodes,
> I want to use command like "mkswap /dev/hda4".
> When I use "mkswap /dev/ide/host0/bus0/target0/lun0/part1p4",
> it shows the "No such file or directory" message. How can I create
> the right device nodes? thanks!
man mknod?
But maybe you want to read some more things about devfs, udev, ... /etc/devfsd.conf
before you know what you are doing there?
Well... all that depends on your kernel/system config a bit...
Best greets,
--
Clemens Koller
_______________________________
R&D Imaging Devices
Anagramm GmbH
Rupert-Mayer-Str. 45/1
81379 Muenchen
Germany
http://www.anagramm.de
Phone: +49-89-741518-50
Fax: +49-89-741518-19
^ permalink raw reply
* Re: [PATCH] powerpc: Merged ppc_asm.h
From: Paul Mackerras @ 2005-09-15 10:54 UTC (permalink / raw)
To: Kumar Gala; +Cc: linuxppc-dev list, linuxppc64-dev
In-Reply-To: <F0F2A9CC-F204-407C-A9FA-A60818D09DAB@freescale.com>
Kumar Gala writes:
> What's the status of applying this to your tree?
>
> http://patchwork.ozlabs.org/linuxppc/patch?id=2330
I'm going to start up a ppc-merge.git tree on kernel.org soon. I
don't intend to send any more 32/64 merge patches to Linus until after
2.6.14 is out.
Regards,
Paul.
^ permalink raw reply
* Re: PATCH powerpc: Merge asm-ppc*/sections.h
From: Paul Mackerras @ 2005-09-15 11:09 UTC (permalink / raw)
To: Jon Loeliger; +Cc: linuxppc64-dev, Arnd Bergmann, linuxppc-dev@ozlabs.org
In-Reply-To: <1126705588.14036.10.camel@cashmere.sps.mot.com>
Jon Loeliger writes:
> In the Grand Scheme of Things, removing things and making them
> simpler seems a lofty goal. :-) Anyone know of any pitfalls that
> await me if I try to remove these sections, a la pmac and friends?
You'll probably get most objection from the PReP users, for whom
getting back a few hundred kB is a big deal. (Maybe we should just
buy both of them a G5 or something. 8-)
> And I assume that the obvious mappings can take place (ie, that
> "pmac.text" can just be placed in regular .text, etc), right?
Yes.
Paul.
^ permalink raw reply
* Re: __switch_to test-and-branch ALTIVEC specific?
From: Paul Mackerras @ 2005-09-15 11:18 UTC (permalink / raw)
To: Marcelo Tosatti; +Cc: linuxppc-dev, linux-ppc-embedded
In-Reply-To: <20050913175028.GB14889@dmt.cnet>
Marcelo Tosatti writes:
> This test&branch looks AltiVec specific, any reason for not #ifdef'ing it
> out?
No, your patch looks fine. (/me wishes patchwork had a "Queued"
state.)
Paul.
^ permalink raw reply
* Re: [PATCH] powerpc: don't execute a temporary comment
From: John W. Linville @ 2005-09-15 14:07 UTC (permalink / raw)
To: Stephen Rothwell; +Cc: ppc-dev, ppc64-dev
In-Reply-To: <20050915160430.550d02ed.sfr@canb.auug.org.au>
On Thu, Sep 15, 2005 at 04:04:30PM +1000, Stephen Rothwell wrote:
> --- a/arch/ppc/Makefile
> +++ b/arch/ppc/Makefile
> @@ -102,9 +102,9 @@ define archhelp
> @echo ' *_defconfig - Select default config from arch/$(ARCH)/ppc/configs'
> endef
>
> +# arch/$(ARCH)/include is a temporary hack until we have migrated to asm-powerpc
> archclean:
> $(Q)$(MAKE) $(clean)=arch/ppc/boot
> - # Temporary hack until we have migrated to asm-powerpc
> $(Q)rm -rf arch/$(ARCH)/include
>
> archprepare: checkbin
Why is this helpful? Better in general to keep the commment near the code, no?
John
--
John W. Linville
linville@tuxdriver.com
^ permalink raw reply
* non-inlined versions of local_irq*
From: Kumar Gala @ 2005-09-15 15:12 UTC (permalink / raw)
To: linuxppc-dev list; +Cc: linuxppc64-dev
Anyone know why on ppc32 we have non-inlined versions of:
extern void local_irq_enable(void);
extern void local_irq_disable(void);
extern void local_irq_restore(unsigned long);
extern void local_save_flags_ptr(unsigned long *);
From looking at the code they are never used. Just wondering if
this was for debug or some other reason.
- kumar
^ permalink raw reply
* PPC4xx cleanup
From: Stefan Roese @ 2005-09-15 16:03 UTC (permalink / raw)
To: linuxppc-embedded
In-Reply-To: <20050830083859.B5925@cox.net>
Hi,
I am right now testing and cleaning up some of the AMCC 4xx eval board ports
to better support U-Boot as firmware. One question before I begin to send a
few patches:
All of the 44x boards I looked at (e.g. Ocotea) have to be extended in the
platform file (e.g. platforms/4xx/ocotea.c) to not only copy the bd_info
struct from r3, but also check r4 and r6 for initrd and kernel command line
passing from the bootloader. Instead of adding this code to all different
platform files, I would like to move this code to the common function
"ibm44x_platform_init" (syslib/ibm44x_common.c) like it is done in the 40x
ports "ppc4xx_init" (syslib/ppc4xx_setup.c).
Any objections/remarks?
Best regards,
Stefan
^ permalink raw reply
* Re: PPC4xx cleanup
From: Matt Porter @ 2005-09-15 16:25 UTC (permalink / raw)
To: Stefan Roese; +Cc: linuxppc-embedded
In-Reply-To: <200509151803.15301.sr@denx.de>
On Thu, Sep 15, 2005 at 06:03:14PM +0200, Stefan Roese wrote:
> Hi,
>
> I am right now testing and cleaning up some of the AMCC 4xx eval board ports
> to better support U-Boot as firmware. One question before I begin to send a
> few patches:
>
> All of the 44x boards I looked at (e.g. Ocotea) have to be extended in the
> platform file (e.g. platforms/4xx/ocotea.c) to not only copy the bd_info
> struct from r3, but also check r4 and r6 for initrd and kernel command line
> passing from the bootloader. Instead of adding this code to all different
> platform files, I would like to move this code to the common function
> "ibm44x_platform_init" (syslib/ibm44x_common.c) like it is done in the 40x
> ports "ppc4xx_init" (syslib/ppc4xx_setup.c).
>
> Any objections/remarks?
Sounds great to me. This will have to wait to go in mainline until
after 2.6.14 is out though.
-Matt
^ permalink raw reply
* Re: PATCH powerpc: Merge asm-ppc*/sections.h
From: Jon Loeliger @ 2005-09-15 17:07 UTC (permalink / raw)
To: linuxppc64-dev, linuxppc-dev@ozlabs.org
In-Reply-To: <17193.22140.962651.122114@cargo.ozlabs.ibm.com>
On Thu, 2005-09-15 at 06:09, Paul Mackerras wrote:
> Jon Loeliger writes:
>
> > In the Grand Scheme of Things, removing things and making them
> > simpler seems a lofty goal. :-) Anyone know of any pitfalls that
> > await me if I try to remove these sections, a la pmac and friends?
>
> You'll probably get most objection from the PReP users, for whom
> getting back a few hundred kB is a big deal. (Maybe we should just
> buy both of them a G5 or something. 8-)
OK. I dug up some data.
Compiled ppc32 *_defconfig across the page.
Section down the left. All numbers are 4K pages.
OF is the so-called "__openfirmware" section.
pmac ibmchrp stx_gp3 mpc8555_cds
--------------------------------------
pmac 10 7 0 0
prep 2 2 0 0
chrp 1 1 0 0
OF 2 1 0 0
init 47 46 23 32
Over in arch/ppc/mm/init.c this gets done:
printk ("Freeing unused kernel memory:");
FREESEC(init);
if (_machine != _MACH_Pmac)
FREESEC(pmac);
if (_machine != _MACH_chrp)
FREESEC(chrp);
if (_machine != _MACH_prep)
FREESEC(prep);
if (!have_of)
FREESEC(openfirmware);
Toss sections that don't match your _machine.
Everyone tosses init section.
Embedded boards will take no hit.
Ppc64 currently does not have these special sections
and hence will see no impact here.
That is the cost of removing these section identifiers.
So, is everyone prepared to live with these few pages
of occasional increased image size and remove the
special sections?
Thanks,
jdl
^ permalink raw reply
* Re: PATCH powerpc: Merge asm-ppc*/sections.h
From: Kumar Gala @ 2005-09-15 17:28 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc64-dev, Arnd Bergmann, linuxppc-dev
In-Reply-To: <17193.22140.962651.122114@cargo.ozlabs.ibm.com>
On Sep 15, 2005, at 6:09 AM, Paul Mackerras wrote:
> Jon Loeliger writes:
>
>
>> In the Grand Scheme of Things, removing things and making them
>> simpler seems a lofty goal. :-) Anyone know of any pitfalls that
>> await me if I try to remove these sections, a la pmac and friends?
>>
>
> You'll probably get most objection from the PReP users, for whom
> getting back a few hundred kB is a big deal. (Maybe we should just
> buy both of them a G5 or something. 8-)
If they care that much they should submit a patch to build a PReP
specific kernel that doesn't include this stuff. And while you are
buying G5's for people send one my way :)
I vote that we just get ride of this sections stuff for prep, pmac,
of, chrp and if we want to reduce the code size make it a compile
choice to build specific kernel's that dont include the crap that the
others need. (especially based on the numbers that Jon has posted
for size).
- kumar
^ permalink raw reply
* Re: [PATCH] powerpc: merge include/asm/cputable.h
From: Kumar Gala @ 2005-09-15 17:44 UTC (permalink / raw)
To: Arnd Bergmann
Cc: linuxppc-dev, pantelis.antoniou, linuxppc64-dev,
linuxppc-embedded
In-Reply-To: <200509150158.10511.arnd@arndb.de>
I get the idea now, how about we make CPU_FTR_ALWAYS &
CPU_FTR_POSSIBLE just #defines and leave it to various sub-archs to
define CPU_FTR_POSSIBLE if they want to.
I see the classes of for FTR_POSSIBLE: CLASSIC_PPC, 8xx, 4xx, FSL-
BOOKE, PPC64 (maybe more subclasses here).
The hugh enum while useful, is just really ugly and I can't believe
it's worth it for the ~60 cases we are using cpu_has_feature() in.
- kumar
On Sep 14, 2005, at 6:58 PM, Arnd Bergmann wrote:
> On Middeweken 14 September 2005 21:11, Kumar Gala wrote:
>
>> I not sure I understand what the introduction of the enum's gets us.
>>
>>
> It doesn't have to be an enum, it could just as well be a #define,
> if we find that to be better in some way (maybe compile-time).
>
> The general idea is to convert run-time checks into compile-time
> checks in order to improve the running kernel. If you have
>
> // start code
> enum {
> FEATURE_1 = 1,
> FEATURE_2 = 2,
> PLATFORM_1 = FEATURE_1,
> PLATFORM_2 = FEATURE_2,
> PLATFORM_3 = FEATURE_1 | FEATURE_2,
> FEATURE_POSSIBLE =
> #ifdef CONFIG_PLATFORM_1
> PLATFORM_1 |
> #endif
> #ifdef CONFIG_FEATURE_2
> PLATFORM_2 |
> #endif
> #ifdef CONFIG_FEATURE_3
> PLATFORM_3 |
> #endif
> 0,
> FEATURE_ALWAYS =
> #ifdef CONFIG_PLATFORM_1
> PLATFORM_1 &
> #endif
> #ifdef CONFIG_PLATFORM_2
> PLATFORM_2 &
> #endif
> #ifdef CONFIG_PLATFORM_3
> PLATFORM_3 &
> #endif
> FEATURE_POSSIBLE,
> };
>
> static inline int have_feature(unsigned long feature)
> {
> return (FEATURE_ALWAYS & feature) ||
> (FEATURE_POSSIBLE & runtime_feature & feature);
> }
>
> int foo();
> int bar();
> int main(void)
> {
> if (have_feature(FEATURE_1))
> return foo();
> if (have_feature(FEATURE_2))
> return bar();
> return 0;
> }
> // end code
>
> Then gcc will produce optimal object code for any combination
> of CONFIG_PLATFORM_{1,2,3}. Of course I have to admit that the
> header file is not exactly elegant ;-).
>
> Arnd <><
>
^ permalink raw reply
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