* Re: Which way to store log in flash on mpc8xx?
From: Jörn Engel @ 2005-09-19 19:07 UTC (permalink / raw)
To: Shawn Jin; +Cc: linux-mtd, David Jander, linuxppc-embedded
In-Reply-To: <c3d0340b050919114040d0a0fe@mail.gmail.com>
On Mon, 19 September 2005 11:40:05 -0700, Shawn Jin wrote:
>
> > > This must be a very common task (to store logfiles in flash), but I just can't
> > > seem to find the right way to do it.
> >
> > Note that log files may cause a lot of trouble when using a JFFS2
> > file system. Youmay want to addd a buffering layer, like pramfs in a
> > dedicated RAM area (SRAM ideally).
>
> What's the trouble caused by log files when using a JFFS2? I'm not
> aware of that. Any pointers to where I should look into are much
> appreciated.
I guess this should become a FAQ item.
JFFS2 creates one or more nodes whenever sys_write is called.
Unbuffered log entries are usually quite small, so a single node is
written. Let's assume the worst case, just for fun, writes of a
single by.
Now, each node is prepended by a struct jffs2_raw_inode of 64 bytes.
So you're causing the first problem:
1. Up to 65x the raw file data is written to flash.
Which means you waste bus bandwidth, was flash space and waste flash
lifetime. After GC, most of those nodes should get combined to 4k
nodes (plus 64 bytes for the header). Now, JFFS2 also requires an
in-memory structure per node, the struct jffs2_raw_node_ref, weighing
in at 16 or 24 bytes, if you have a 32bit or 64bit arch. Those will
cost you precious memory:
2. Up to 24x the raw file data is required in DRAM.
Next problem is with GC accounting. JFFS2 only differentiates between
valid and obsolete data. After writing a huge logfile, all of its
nodes are still valid. Therefore GC will never try to GC such nodes,
unless they happen to sit in an erase block with a lot of obsolete
data. And even then, they could get copied as-is, with no combining.
3. JFFS2 GC is too stupid to detect miniature nodes and combine them.
So, your problem 1 and 2 will not go away if you wait long enough.
Renaming the log file also won't help. The only cure would be to
*copy* it to the new location and delete the original file afterwards.
Or - alternatively - to fix JFFS2 GC and send a patch.
Or - as already proposed - by writing in larger chunks in the first
place.
If you decide to fix JFFS2 GC, I'd be happy to review the patches and
merge them if deemed worthy.
Jörn
--
My second remark is that our intellectual powers are rather geared to
master static relations and that our powers to visualize processes
evolving in time are relatively poorly developed.
-- Edsger W. Dijkstra
^ permalink raw reply
* Re: Which way to store log in flash on mpc8xx?
From: Wolfgang Denk @ 2005-09-19 19:29 UTC (permalink / raw)
To: shawnxjin; +Cc: linuxppc-embedded
In-Reply-To: <c3d0340b050919114040d0a0fe@mail.gmail.com>
In message <c3d0340b050919114040d0a0fe@mail.gmail.com> you wrote:
>
> What's the trouble caused by log files when using a JFFS2? I'm not
> aware of that. Any pointers to where I should look into are much
> appreciated.
Please see the linux-mtd web site and/or MTD mailing list archives
for details. JFFS2 works excellent with files that are written once
(or with only a few write() calls. Logfiles typically grow forever,
by many, many small chunks of data appended in many write()
operations - this is kind of killer application for JFFS2.
Best regards,
Wolfgang Denk
--
Software Engineering: Embedded and Realtime Systems, Embedded Linux
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de
"I find this a nice feature but it is not according to the documen-
tation. Or is it a BUG?" "Let's call it an accidental feature. :-)"
- Larry Wall in <6909@jpl-devvax.JPL.NASA.GOV>
^ permalink raw reply
* PATCH powerpc Merge atomic.h
From: Jon Loeliger @ 2005-09-19 20:29 UTC (permalink / raw)
To: linuxppc-dev, linuxppc64-dev
Paul,
There is also Arnd's patch called "[PATCH 0/3] Start the merge"
from 08/29 that is really the merger of asm-ppc*/atomic.h.
I repost it here for Arnd, who can NAK it or not.
It is a pre-requisite patch for doing the rwsem.h merge
as discussed recently.
jdl
This is another patch to merge the atomic.h file. It is not completely
trivial and changes the semantics for 32 bit SMP systems, which previously
did not do EIEIO_ON_SMP within the atomic operations. AFAICT, that was
a bug in the 32 bit version, which is now fixed as a side-effect of
the merge.
The combined version of this file also prevents building user space
applications using atomic.h on ppc64. That was already impossible
on 32 bit ppc, but probably also created broken output on ppc64.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
--
include/asm-ppc/atomic.h | 214 ------------------------------
include/asm-ppc64/atomic.h | 197 ---------------------------
include/asm-ppc64/memory.h | 59 --------
linux-2.6.12/include/asm-powerpc/atomic.h | 209 +++++++++++++++++++++++++++++
linux-2.6.12/include/asm-powerpc/memory.h | 59 ++++++++
linux-2.6.12/include/asm-ppc/io.h | 11 -
6 files changed, 269 insertions(+), 480 deletions(-)
Index: linux-2.6.12/include/asm-ppc/atomic.h
===================================================================
--- linux-2.6.12.orig/include/asm-ppc/atomic.h 2005-08-29 08:04:06.000000000 +0200
+++ /dev/null 1970-01-01 00:00:00.000000000 +0000
@@ -1,214 +0,0 @@
-/*
- * PowerPC atomic operations
- */
-
-#ifndef _ASM_PPC_ATOMIC_H_
-#define _ASM_PPC_ATOMIC_H_
-
-typedef struct { volatile int counter; } atomic_t;
-
-#ifdef __KERNEL__
-
-#define ATOMIC_INIT(i) { (i) }
-
-#define atomic_read(v) ((v)->counter)
-#define atomic_set(v,i) (((v)->counter) = (i))
-
-extern void atomic_clear_mask(unsigned long mask, unsigned long *addr);
-
-#ifdef CONFIG_SMP
-#define SMP_SYNC "sync"
-#define SMP_ISYNC "\n\tisync"
-#else
-#define SMP_SYNC ""
-#define SMP_ISYNC
-#endif
-
-/* Erratum #77 on the 405 means we need a sync or dcbt before every stwcx.
- * The old ATOMIC_SYNC_FIX covered some but not all of this.
- */
-#ifdef CONFIG_IBM405_ERR77
-#define PPC405_ERR77(ra,rb) "dcbt " #ra "," #rb ";"
-#else
-#define PPC405_ERR77(ra,rb)
-#endif
-
-static __inline__ void atomic_add(int a, atomic_t *v)
-{
- int t;
-
- __asm__ __volatile__(
-"1: lwarx %0,0,%3 # atomic_add\n\
- add %0,%2,%0\n"
- PPC405_ERR77(0,%3)
-" stwcx. %0,0,%3 \n\
- bne- 1b"
- : "=&r" (t), "=m" (v->counter)
- : "r" (a), "r" (&v->counter), "m" (v->counter)
- : "cc");
-}
-
-static __inline__ int atomic_add_return(int a, atomic_t *v)
-{
- int t;
-
- __asm__ __volatile__(
-"1: lwarx %0,0,%2 # atomic_add_return\n\
- add %0,%1,%0\n"
- PPC405_ERR77(0,%2)
-" stwcx. %0,0,%2 \n\
- bne- 1b"
- SMP_ISYNC
- : "=&r" (t)
- : "r" (a), "r" (&v->counter)
- : "cc", "memory");
-
- return t;
-}
-
-#define atomic_add_negative(a, v) (atomic_add_return((a), (v)) < 0)
-
-static __inline__ void atomic_sub(int a, atomic_t *v)
-{
- int t;
-
- __asm__ __volatile__(
-"1: lwarx %0,0,%3 # atomic_sub\n\
- subf %0,%2,%0\n"
- PPC405_ERR77(0,%3)
-" stwcx. %0,0,%3 \n\
- bne- 1b"
- : "=&r" (t), "=m" (v->counter)
- : "r" (a), "r" (&v->counter), "m" (v->counter)
- : "cc");
-}
-
-static __inline__ int atomic_sub_return(int a, atomic_t *v)
-{
- int t;
-
- __asm__ __volatile__(
-"1: lwarx %0,0,%2 # atomic_sub_return\n\
- subf %0,%1,%0\n"
- PPC405_ERR77(0,%2)
-" stwcx. %0,0,%2 \n\
- bne- 1b"
- SMP_ISYNC
- : "=&r" (t)
- : "r" (a), "r" (&v->counter)
- : "cc", "memory");
-
- return t;
-}
-
-static __inline__ void atomic_inc(atomic_t *v)
-{
- int t;
-
- __asm__ __volatile__(
-"1: lwarx %0,0,%2 # atomic_inc\n\
- addic %0,%0,1\n"
- PPC405_ERR77(0,%2)
-" stwcx. %0,0,%2 \n\
- bne- 1b"
- : "=&r" (t), "=m" (v->counter)
- : "r" (&v->counter), "m" (v->counter)
- : "cc");
-}
-
-static __inline__ int atomic_inc_return(atomic_t *v)
-{
- int t;
-
- __asm__ __volatile__(
-"1: lwarx %0,0,%1 # atomic_inc_return\n\
- addic %0,%0,1\n"
- PPC405_ERR77(0,%1)
-" stwcx. %0,0,%1 \n\
- bne- 1b"
- SMP_ISYNC
- : "=&r" (t)
- : "r" (&v->counter)
- : "cc", "memory");
-
- return t;
-}
-
-/*
- * atomic_inc_and_test - increment and test
- * @v: pointer of type atomic_t
- *
- * Atomically increments @v by 1
- * and returns true if the result is zero, or false for all
- * other cases.
- */
-#define atomic_inc_and_test(v) (atomic_inc_return(v) == 0)
-
-static __inline__ void atomic_dec(atomic_t *v)
-{
- int t;
-
- __asm__ __volatile__(
-"1: lwarx %0,0,%2 # atomic_dec\n\
- addic %0,%0,-1\n"
- PPC405_ERR77(0,%2)\
-" stwcx. %0,0,%2\n\
- bne- 1b"
- : "=&r" (t), "=m" (v->counter)
- : "r" (&v->counter), "m" (v->counter)
- : "cc");
-}
-
-static __inline__ int atomic_dec_return(atomic_t *v)
-{
- int t;
-
- __asm__ __volatile__(
-"1: lwarx %0,0,%1 # atomic_dec_return\n\
- addic %0,%0,-1\n"
- PPC405_ERR77(0,%1)
-" stwcx. %0,0,%1\n\
- bne- 1b"
- SMP_ISYNC
- : "=&r" (t)
- : "r" (&v->counter)
- : "cc", "memory");
-
- return t;
-}
-
-#define atomic_sub_and_test(a, v) (atomic_sub_return((a), (v)) == 0)
-#define atomic_dec_and_test(v) (atomic_dec_return((v)) == 0)
-
-/*
- * Atomically test *v and decrement if it is greater than 0.
- * The function returns the old value of *v minus 1.
- */
-static __inline__ int atomic_dec_if_positive(atomic_t *v)
-{
- int t;
-
- __asm__ __volatile__(
-"1: lwarx %0,0,%1 # atomic_dec_if_positive\n\
- addic. %0,%0,-1\n\
- blt- 2f\n"
- PPC405_ERR77(0,%1)
-" stwcx. %0,0,%1\n\
- bne- 1b"
- SMP_ISYNC
- "\n\
-2:" : "=&r" (t)
- : "r" (&v->counter)
- : "cc", "memory");
-
- return t;
-}
-
-#define __MB __asm__ __volatile__ (SMP_SYNC : : : "memory")
-#define smp_mb__before_atomic_dec() __MB
-#define smp_mb__after_atomic_dec() __MB
-#define smp_mb__before_atomic_inc() __MB
-#define smp_mb__after_atomic_inc() __MB
-
-#endif /* __KERNEL__ */
-#endif /* _ASM_PPC_ATOMIC_H_ */
Index: linux-2.6.12/include/asm-ppc64/memory.h
===================================================================
--- linux-2.6.12.orig/include/asm-ppc64/memory.h 2005-08-29 08:04:06.000000000 +0200
+++ /dev/null 1970-01-01 00:00:00.000000000 +0000
@@ -1,59 +0,0 @@
-#ifndef _ASM_POWERPC_MEMORY_H_
-#define _ASM_POWERPC_MEMORY_H_
-
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <linux/config.h>
-
-/*
- * Arguably the bitops and *xchg operations don't imply any memory barrier
- * or SMP ordering, but in fact a lot of drivers expect them to imply
- * both, since they do on x86 cpus.
- */
-#ifdef CONFIG_SMP
-#define EIEIO_ON_SMP "eieio\n"
-#define ISYNC_ON_SMP "\n\tisync"
-#else
-#define EIEIO_ON_SMP
-#define ISYNC_ON_SMP
-#endif
-
-static inline void eieio(void)
-{
- __asm__ __volatile__ ("eieio" : : : "memory");
-}
-
-static inline void isync(void)
-{
- __asm__ __volatile__ ("isync" : : : "memory");
-}
-
-#ifdef CONFIG_SMP
-#define eieio_on_smp() eieio()
-#define isync_on_smp() isync()
-#else
-#define eieio_on_smp() __asm__ __volatile__("": : :"memory")
-#define isync_on_smp() __asm__ __volatile__("": : :"memory")
-#endif
-
-/* Macros for adjusting thread priority (hardware multi-threading) */
-#define HMT_very_low() asm volatile("or 31,31,31 # very low priority")
-#define HMT_low() asm volatile("or 1,1,1 # low priority")
-#define HMT_medium_low() asm volatile("or 6,6,6 # medium low priority")
-#define HMT_medium() asm volatile("or 2,2,2 # medium priority")
-#define HMT_medium_high() asm volatile("or 5,5,5 # medium high priority")
-#define HMT_high() asm volatile("or 3,3,3 # high priority")
-
-#define HMT_VERY_LOW "\tor 31,31,31 # very low priority\n"
-#define HMT_LOW "\tor 1,1,1 # low priority\n"
-#define HMT_MEDIUM_LOW "\tor 6,6,6 # medium low priority\n"
-#define HMT_MEDIUM "\tor 2,2,2 # medium priority\n"
-#define HMT_MEDIUM_HIGH "\tor 5,5,5 # medium high priority\n"
-#define HMT_HIGH "\tor 3,3,3 # high priority\n"
-
-#endif
Index: linux-2.6.12/include/asm-ppc/io.h
===================================================================
--- linux-2.6.12.orig/include/asm-ppc/io.h 2005-08-29 08:04:06.000000000 +0200
+++ linux-2.6.12/include/asm-ppc/io.h 2005-08-29 08:04:26.000000000 +0200
@@ -8,6 +8,7 @@
#include <asm/page.h>
#include <asm/byteorder.h>
+#include <asm/memory.h>
#include <asm/mmu.h>
#define SIO_CONFIG_RA 0x398
@@ -440,16 +441,6 @@
#define page_to_phys(page) (page_to_pfn(page) << PAGE_SHIFT)
#define page_to_bus(page) (page_to_phys(page) + PCI_DRAM_OFFSET)
-/*
- * Enforce In-order Execution of I/O:
- * Acts as a barrier to ensure all previous I/O accesses have
- * completed before any further ones are issued.
- */
-extern inline void eieio(void)
-{
- __asm__ __volatile__ ("eieio" : : : "memory");
-}
-
/* Enforce in-order execution of data I/O.
* No distinction between read/write on PPC; use eieio for all three.
*/
Index: linux-2.6.12/include/asm-ppc64/atomic.h
===================================================================
--- linux-2.6.12.orig/include/asm-ppc64/atomic.h 2005-08-29 08:04:06.000000000 +0200
+++ /dev/null 1970-01-01 00:00:00.000000000 +0000
@@ -1,197 +0,0 @@
-/*
- * PowerPC64 atomic operations
- *
- * Copyright (C) 2001 Paul Mackerras <paulus@au.ibm.com>, IBM
- * Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _ASM_PPC64_ATOMIC_H_
-#define _ASM_PPC64_ATOMIC_H_
-
-#include <asm/memory.h>
-
-typedef struct { volatile int counter; } atomic_t;
-
-#define ATOMIC_INIT(i) { (i) }
-
-#define atomic_read(v) ((v)->counter)
-#define atomic_set(v,i) (((v)->counter) = (i))
-
-static __inline__ void atomic_add(int a, atomic_t *v)
-{
- int t;
-
- __asm__ __volatile__(
-"1: lwarx %0,0,%3 # atomic_add\n\
- add %0,%2,%0\n\
- stwcx. %0,0,%3\n\
- bne- 1b"
- : "=&r" (t), "=m" (v->counter)
- : "r" (a), "r" (&v->counter), "m" (v->counter)
- : "cc");
-}
-
-static __inline__ int atomic_add_return(int a, atomic_t *v)
-{
- int t;
-
- __asm__ __volatile__(
- EIEIO_ON_SMP
-"1: lwarx %0,0,%2 # atomic_add_return\n\
- add %0,%1,%0\n\
- stwcx. %0,0,%2\n\
- bne- 1b"
- ISYNC_ON_SMP
- : "=&r" (t)
- : "r" (a), "r" (&v->counter)
- : "cc", "memory");
-
- return t;
-}
-
-#define atomic_add_negative(a, v) (atomic_add_return((a), (v)) < 0)
-
-static __inline__ void atomic_sub(int a, atomic_t *v)
-{
- int t;
-
- __asm__ __volatile__(
-"1: lwarx %0,0,%3 # atomic_sub\n\
- subf %0,%2,%0\n\
- stwcx. %0,0,%3\n\
- bne- 1b"
- : "=&r" (t), "=m" (v->counter)
- : "r" (a), "r" (&v->counter), "m" (v->counter)
- : "cc");
-}
-
-static __inline__ int atomic_sub_return(int a, atomic_t *v)
-{
- int t;
-
- __asm__ __volatile__(
- EIEIO_ON_SMP
-"1: lwarx %0,0,%2 # atomic_sub_return\n\
- subf %0,%1,%0\n\
- stwcx. %0,0,%2\n\
- bne- 1b"
- ISYNC_ON_SMP
- : "=&r" (t)
- : "r" (a), "r" (&v->counter)
- : "cc", "memory");
-
- return t;
-}
-
-static __inline__ void atomic_inc(atomic_t *v)
-{
- int t;
-
- __asm__ __volatile__(
-"1: lwarx %0,0,%2 # atomic_inc\n\
- addic %0,%0,1\n\
- stwcx. %0,0,%2\n\
- bne- 1b"
- : "=&r" (t), "=m" (v->counter)
- : "r" (&v->counter), "m" (v->counter)
- : "cc");
-}
-
-static __inline__ int atomic_inc_return(atomic_t *v)
-{
- int t;
-
- __asm__ __volatile__(
- EIEIO_ON_SMP
-"1: lwarx %0,0,%1 # atomic_inc_return\n\
- addic %0,%0,1\n\
- stwcx. %0,0,%1\n\
- bne- 1b"
- ISYNC_ON_SMP
- : "=&r" (t)
- : "r" (&v->counter)
- : "cc", "memory");
-
- return t;
-}
-
-/*
- * atomic_inc_and_test - increment and test
- * @v: pointer of type atomic_t
- *
- * Atomically increments @v by 1
- * and returns true if the result is zero, or false for all
- * other cases.
- */
-#define atomic_inc_and_test(v) (atomic_inc_return(v) == 0)
-
-static __inline__ void atomic_dec(atomic_t *v)
-{
- int t;
-
- __asm__ __volatile__(
-"1: lwarx %0,0,%2 # atomic_dec\n\
- addic %0,%0,-1\n\
- stwcx. %0,0,%2\n\
- bne- 1b"
- : "=&r" (t), "=m" (v->counter)
- : "r" (&v->counter), "m" (v->counter)
- : "cc");
-}
-
-static __inline__ int atomic_dec_return(atomic_t *v)
-{
- int t;
-
- __asm__ __volatile__(
- EIEIO_ON_SMP
-"1: lwarx %0,0,%1 # atomic_dec_return\n\
- addic %0,%0,-1\n\
- stwcx. %0,0,%1\n\
- bne- 1b"
- ISYNC_ON_SMP
- : "=&r" (t)
- : "r" (&v->counter)
- : "cc", "memory");
-
- return t;
-}
-
-#define atomic_sub_and_test(a, v) (atomic_sub_return((a), (v)) == 0)
-#define atomic_dec_and_test(v) (atomic_dec_return((v)) == 0)
-
-/*
- * Atomically test *v and decrement if it is greater than 0.
- * The function returns the old value of *v minus 1.
- */
-static __inline__ int atomic_dec_if_positive(atomic_t *v)
-{
- int t;
-
- __asm__ __volatile__(
- EIEIO_ON_SMP
-"1: lwarx %0,0,%1 # atomic_dec_if_positive\n\
- addic. %0,%0,-1\n\
- blt- 2f\n\
- stwcx. %0,0,%1\n\
- bne- 1b"
- ISYNC_ON_SMP
- "\n\
-2:" : "=&r" (t)
- : "r" (&v->counter)
- : "cc", "memory");
-
- return t;
-}
-
-#define smp_mb__before_atomic_dec() smp_mb()
-#define smp_mb__after_atomic_dec() smp_mb()
-#define smp_mb__before_atomic_inc() smp_mb()
-#define smp_mb__after_atomic_inc() smp_mb()
-
-#endif /* _ASM_PPC64_ATOMIC_H_ */
Index: linux-2.6.12/include/asm-powerpc/memory.h
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ linux-2.6.12/include/asm-powerpc/memory.h 2005-08-29 08:04:26.000000000 +0200
@@ -0,0 +1,59 @@
+#ifndef _ASM_PPC64_MEMORY_H_
+#define _ASM_PPC64_MEMORY_H_
+
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include <linux/config.h>
+
+/*
+ * Arguably the bitops and *xchg operations don't imply any memory barrier
+ * or SMP ordering, but in fact a lot of drivers expect them to imply
+ * both, since they do on x86 cpus.
+ */
+#ifdef CONFIG_SMP
+#define EIEIO_ON_SMP "eieio\n"
+#define ISYNC_ON_SMP "\n\tisync"
+#else
+#define EIEIO_ON_SMP
+#define ISYNC_ON_SMP
+#endif
+
+static inline void eieio(void)
+{
+ __asm__ __volatile__ ("eieio" : : : "memory");
+}
+
+static inline void isync(void)
+{
+ __asm__ __volatile__ ("isync" : : : "memory");
+}
+
+#ifdef CONFIG_SMP
+#define eieio_on_smp() eieio()
+#define isync_on_smp() isync()
+#else
+#define eieio_on_smp() __asm__ __volatile__("": : :"memory")
+#define isync_on_smp() __asm__ __volatile__("": : :"memory")
+#endif
+
+/* Macros for adjusting thread priority (hardware multi-threading) */
+#define HMT_very_low() asm volatile("or 31,31,31 # very low priority")
+#define HMT_low() asm volatile("or 1,1,1 # low priority")
+#define HMT_medium_low() asm volatile("or 6,6,6 # medium low priority")
+#define HMT_medium() asm volatile("or 2,2,2 # medium priority")
+#define HMT_medium_high() asm volatile("or 5,5,5 # medium high priority")
+#define HMT_high() asm volatile("or 3,3,3 # high priority")
+
+#define HMT_VERY_LOW "\tor 31,31,31 # very low priority\n"
+#define HMT_LOW "\tor 1,1,1 # low priority\n"
+#define HMT_MEDIUM_LOW "\tor 6,6,6 # medium low priority\n"
+#define HMT_MEDIUM "\tor 2,2,2 # medium priority\n"
+#define HMT_MEDIUM_HIGH "\tor 5,5,5 # medium high priority\n"
+#define HMT_HIGH "\tor 3,3,3 # high priority\n"
+
+#endif
Index: linux-2.6.12/include/asm-powerpc/atomic.h
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ linux-2.6.12/include/asm-powerpc/atomic.h 2005-08-29 08:04:26.000000000 +0200
@@ -0,0 +1,209 @@
+/*
+ * PowerPC atomic operations
+ */
+
+#ifndef _ASM_POWERPC_ATOMIC_H_
+#define _ASM_POWERPC_ATOMIC_H_
+
+typedef struct { volatile int counter; } atomic_t;
+
+#ifdef __KERNEL__
+#include <asm/memory.h>
+
+#define ATOMIC_INIT(i) { (i) }
+
+#define atomic_read(v) ((v)->counter)
+#define atomic_set(v,i) (((v)->counter) = (i))
+
+/* Erratum #77 on the 405 means we need a sync or dcbt before every stwcx.
+ * The old ATOMIC_SYNC_FIX covered some but not all of this.
+ */
+#ifdef CONFIG_IBM405_ERR77
+#define PPC405_ERR77(ra,rb) "dcbt " #ra "," #rb ";"
+#else
+#define PPC405_ERR77(ra,rb)
+#endif
+
+static __inline__ void atomic_add(int a, atomic_t *v)
+{
+ int t;
+
+ __asm__ __volatile__(
+"1: lwarx %0,0,%3 # atomic_add\n\
+ add %0,%2,%0\n"
+ PPC405_ERR77(0,%3)
+" stwcx. %0,0,%3 \n\
+ bne- 1b"
+ : "=&r" (t), "=m" (v->counter)
+ : "r" (a), "r" (&v->counter), "m" (v->counter)
+ : "cc");
+}
+
+static __inline__ int atomic_add_return(int a, atomic_t *v)
+{
+ int t;
+
+ __asm__ __volatile__(
+ EIEIO_ON_SMP
+"1: lwarx %0,0,%2 # atomic_add_return\n\
+ add %0,%1,%0\n"
+ PPC405_ERR77(0,%2)
+" stwcx. %0,0,%2 \n\
+ bne- 1b"
+ ISYNC_ON_SMP
+ : "=&r" (t)
+ : "r" (a), "r" (&v->counter)
+ : "cc", "memory");
+
+ return t;
+}
+
+#define atomic_add_negative(a, v) (atomic_add_return((a), (v)) < 0)
+
+static __inline__ void atomic_sub(int a, atomic_t *v)
+{
+ int t;
+
+ __asm__ __volatile__(
+"1: lwarx %0,0,%3 # atomic_sub\n\
+ subf %0,%2,%0\n"
+ PPC405_ERR77(0,%3)
+" stwcx. %0,0,%3 \n\
+ bne- 1b"
+ : "=&r" (t), "=m" (v->counter)
+ : "r" (a), "r" (&v->counter), "m" (v->counter)
+ : "cc");
+}
+
+static __inline__ int atomic_sub_return(int a, atomic_t *v)
+{
+ int t;
+
+ __asm__ __volatile__(
+ EIEIO_ON_SMP
+"1: lwarx %0,0,%2 # atomic_sub_return\n\
+ subf %0,%1,%0\n"
+ PPC405_ERR77(0,%2)
+" stwcx. %0,0,%2 \n\
+ bne- 1b"
+ ISYNC_ON_SMP
+ : "=&r" (t)
+ : "r" (a), "r" (&v->counter)
+ : "cc", "memory");
+
+ return t;
+}
+
+static __inline__ void atomic_inc(atomic_t *v)
+{
+ int t;
+
+ __asm__ __volatile__(
+"1: lwarx %0,0,%2 # atomic_inc\n\
+ addic %0,%0,1\n"
+ PPC405_ERR77(0,%2)
+" stwcx. %0,0,%2 \n\
+ bne- 1b"
+ : "=&r" (t), "=m" (v->counter)
+ : "r" (&v->counter), "m" (v->counter)
+ : "cc");
+}
+
+static __inline__ int atomic_inc_return(atomic_t *v)
+{
+ int t;
+
+ __asm__ __volatile__(
+ EIEIO_ON_SMP
+"1: lwarx %0,0,%1 # atomic_inc_return\n\
+ addic %0,%0,1\n"
+ PPC405_ERR77(0,%1)
+" stwcx. %0,0,%1 \n\
+ bne- 1b"
+ ISYNC_ON_SMP
+ : "=&r" (t)
+ : "r" (&v->counter)
+ : "cc", "memory");
+
+ return t;
+}
+
+/*
+ * atomic_inc_and_test - increment and test
+ * @v: pointer of type atomic_t
+ *
+ * Atomically increments @v by 1
+ * and returns true if the result is zero, or false for all
+ * other cases.
+ */
+#define atomic_inc_and_test(v) (atomic_inc_return(v) == 0)
+
+static __inline__ void atomic_dec(atomic_t *v)
+{
+ int t;
+
+ __asm__ __volatile__(
+"1: lwarx %0,0,%2 # atomic_dec\n\
+ addic %0,%0,-1\n"
+ PPC405_ERR77(0,%2)\
+" stwcx. %0,0,%2\n\
+ bne- 1b"
+ : "=&r" (t), "=m" (v->counter)
+ : "r" (&v->counter), "m" (v->counter)
+ : "cc");
+}
+
+static __inline__ int atomic_dec_return(atomic_t *v)
+{
+ int t;
+
+ __asm__ __volatile__(
+ EIEIO_ON_SMP
+"1: lwarx %0,0,%1 # atomic_dec_return\n\
+ addic %0,%0,-1\n"
+ PPC405_ERR77(0,%1)
+" stwcx. %0,0,%1\n\
+ bne- 1b"
+ ISYNC_ON_SMP
+ : "=&r" (t)
+ : "r" (&v->counter)
+ : "cc", "memory");
+
+ return t;
+}
+
+#define atomic_sub_and_test(a, v) (atomic_sub_return((a), (v)) == 0)
+#define atomic_dec_and_test(v) (atomic_dec_return((v)) == 0)
+
+/*
+ * Atomically test *v and decrement if it is greater than 0.
+ * The function returns the old value of *v minus 1.
+ */
+static __inline__ int atomic_dec_if_positive(atomic_t *v)
+{
+ int t;
+
+ __asm__ __volatile__(
+ EIEIO_ON_SMP
+"1: lwarx %0,0,%1 # atomic_dec_if_positive\n\
+ addic. %0,%0,-1\n\
+ blt- 2f\n"
+ PPC405_ERR77(0,%1)
+" stwcx. %0,0,%1\n\
+ bne- 1b"
+ ISYNC_ON_SMP
+ "\n\
+2:" : "=&r" (t)
+ : "r" (&v->counter)
+ : "cc", "memory");
+
+ return t;
+}
+
+#define smp_mb__before_atomic_dec() smp_mb()
+#define smp_mb__after_atomic_dec() smp_mb()
+#define smp_mb__before_atomic_inc() smp_mb()
+#define smp_mb__after_atomic_inc() smp_mb()
+
+#endif /* __KERNEL__ */
+#endif /* _ASM_POWERPC_ATOMIC_H_ */
^ permalink raw reply
* Re: PATCH powerpc Merge atomic.h
From: Jon Loeliger @ 2005-09-19 20:52 UTC (permalink / raw)
Cc: linuxppc-dev, linuxppc64-dev
In-Reply-To: <E1EHSGk-0005RA-Dh@jdl.com>
So, like, the other day Jon Loeliger mumbled:
> Paul,
>
> There is also Arnd's patch called "[PATCH 0/3] Start the merge"
> from 08/29 that is really the merger of asm-ppc*/atomic.h.
>
> I repost it here for Arnd, who can NAK it or not.
<talk-like-a-pirate-day>
Arrrg! Scurvey dogs! Ye cannt even squeek by repostin' old
patches today. Run it out the gang-plank and flush the rotten thing!
Someone needs a floggin' til this applies properly. Memory.h be damned.
You'll be needin' two-patches iffin you don't watcherself.
</talk-like-a-pirate-day>
jdl
^ permalink raw reply
* [PATCH] powerpc Merge bug.h
From: Becky Bruce @ 2005-09-19 22:01 UTC (permalink / raw)
To: linuxppc64-dev, linuxppc-dev
Resending per Paul's request.....
ppc32/ppc64: Merge bug.h into include/asm-powerpc
This patch merges bug.h into include/asm-powerpc. Changed the data
structure for bug_entry such that line is always an int on both 32 and
64-bit platforms; removed casts to int from the 64-bit trap code to
reflect this.
Signed-off-by: Kumar Gala <kumar.gala@freescale.com>
Signed-off-by: Becky Bruce <Becky.Bruce@freescale.com>
---
commit fcaf8560dc918048b43867d79efa5b26bd6a9a81
tree 079802fdb229c0e3721b893235e2ef912e30d7cd
parent dfe2ac4994952cadc891f095668f9e582d4402b3
author Becky Bruce <becky.bruce@freescale.com> Fri, 09 Sep 2005 11:15:22 -0500
committer Becky Bruce <becky.bruce@freescale.com> Fri, 09 Sep 2005 11:15:22 -0500
arch/ppc/kernel/traps.c | 2 +
arch/ppc64/kernel/traps.c | 4 +-
include/asm-powerpc/bug.h | 81 +++++++++++++++++++++++++++++++++++++++++++++
include/asm-ppc/bug.h | 58 --------------------------------
include/asm-ppc64/bug.h | 69 --------------------------------------
5 files changed, 84 insertions(+), 130 deletions(-)
diff --git a/arch/ppc/kernel/traps.c b/arch/ppc/kernel/traps.c
--- a/arch/ppc/kernel/traps.c
+++ b/arch/ppc/kernel/traps.c
@@ -553,7 +553,7 @@ extern struct bug_entry __start___bug_ta
#define module_find_bug(x) NULL
#endif
-static struct bug_entry *find_bug(unsigned long bugaddr)
+struct bug_entry *find_bug(unsigned long bugaddr)
{
struct bug_entry *bug;
diff --git a/arch/ppc64/kernel/traps.c b/arch/ppc64/kernel/traps.c
--- a/arch/ppc64/kernel/traps.c
+++ b/arch/ppc64/kernel/traps.c
@@ -389,12 +389,12 @@ check_bug_trap(struct pt_regs *regs)
/* this is a WARN_ON rather than BUG/BUG_ON */
printk(KERN_ERR "Badness in %s at %s:%d\n",
bug->function, bug->file,
- (unsigned int)bug->line & ~BUG_WARNING_TRAP);
+ bug->line & ~BUG_WARNING_TRAP);
show_stack(current, (void *)regs->gpr[1]);
return 1;
}
printk(KERN_CRIT "kernel BUG in %s at %s:%d!\n",
- bug->function, bug->file, (unsigned int)bug->line);
+ bug->function, bug->file, bug->line);
return 0;
}
diff --git a/include/asm-powerpc/bug.h b/include/asm-powerpc/bug.h
new file mode 100644
--- /dev/null
+++ b/include/asm-powerpc/bug.h
@@ -0,0 +1,81 @@
+#ifndef _ASM_POWERPC_BUG_H
+#define _ASM_POWERPC_BUG_H
+
+/*
+ * Define an illegal instr to trap on the bug.
+ * We don't use 0 because that marks the end of a function
+ * in the ELF ABI. That's "Boo Boo" in case you wonder...
+ */
+#define BUG_OPCODE .long 0x00b00b00 /* For asm */
+#define BUG_ILLEGAL_INSTR "0x00b00b00" /* For BUG macro */
+
+#ifndef __ASSEMBLY__
+
+#ifdef __powerpc64__
+#define BUG_TABLE_ENTRY(label, line, file, func) \
+ ".llong " #label "\n .long " #line "\n .llong " #file ", " #func "\n"
+#define TRAP_OP(ra, rb) "1: tdnei " #ra ", " #rb "\n"
+#define DATA_TYPE long long
+#else
+#define BUG_TABLE_ENTRY(label, line, file, func) \
+ ".long " #label ", " #line ", " #file ", " #func "\n"
+#define TRAP_OP(ra, rb) "1: twnei " #ra ", " #rb "\n"
+#define DATA_TYPE int
+#endif /* __powerpc64__ */
+
+struct bug_entry {
+ unsigned long bug_addr;
+ int line;
+ const char *file;
+ const char *function;
+};
+
+struct bug_entry *find_bug(unsigned long bugaddr);
+
+/*
+ * If this bit is set in the line number it means that the trap
+ * is for WARN_ON rather than BUG or BUG_ON.
+ */
+#define BUG_WARNING_TRAP 0x1000000
+
+#ifdef CONFIG_BUG
+
+#define BUG() do { \
+ __asm__ __volatile__( \
+ "1: twi 31,0,0\n" \
+ ".section __bug_table,\"a\"\n\t" \
+ BUG_TABLE_ENTRY(1b,%0,%1,%2) \
+ ".previous" \
+ : : "i" (__LINE__), "i" (__FILE__), "i" (__FUNCTION__)); \
+} while (0)
+
+#define BUG_ON(x) do { \
+ __asm__ __volatile__( \
+ TRAP_OP(%0,0) \
+ ".section __bug_table,\"a\"\n\t" \
+ BUG_TABLE_ENTRY(1b,%1,%2,%3) \
+ ".previous" \
+ : : "r" ((DATA_TYPE)(x)), "i" (__LINE__), \
+ "i" (__FILE__), "i" (__FUNCTION__)); \
+} while (0)
+
+#define WARN_ON(x) do { \
+ __asm__ __volatile__( \
+ TRAP_OP(%0,0) \
+ ".section __bug_table,\"a\"\n\t" \
+ BUG_TABLE_ENTRY(1b,%1,%2,%3) \
+ ".previous" \
+ : : "r" ((DATA_TYPE)(x)), \
+ "i" (__LINE__ + BUG_WARNING_TRAP), \
+ "i" (__FILE__), "i" (__FUNCTION__)); \
+} while (0)
+
+#define HAVE_ARCH_BUG
+#define HAVE_ARCH_BUG_ON
+#define HAVE_ARCH_WARN_ON
+#endif /* CONFIG_BUG */
+#endif /* __ASSEMBLY __ */
+
+#include <asm-generic/bug.h>
+
+#endif /* _ASM_POWERPC_BUG_H */
diff --git a/include/asm-ppc/bug.h b/include/asm-ppc/bug.h
deleted file mode 100644
--- a/include/asm-ppc/bug.h
+++ /dev/null
@@ -1,58 +0,0 @@
-#ifndef _PPC_BUG_H
-#define _PPC_BUG_H
-
-struct bug_entry {
- unsigned long bug_addr;
- int line;
- const char *file;
- const char *function;
-};
-
-/*
- * If this bit is set in the line number it means that the trap
- * is for WARN_ON rather than BUG or BUG_ON.
- */
-#define BUG_WARNING_TRAP 0x1000000
-
-#ifdef CONFIG_BUG
-#define BUG() do { \
- __asm__ __volatile__( \
- "1: twi 31,0,0\n" \
- ".section __bug_table,\"a\"\n\t" \
- " .long 1b,%0,%1,%2\n" \
- ".previous" \
- : : "i" (__LINE__), "i" (__FILE__), "i" (__FUNCTION__)); \
-} while (0)
-
-#define BUG_ON(x) do { \
- if (!__builtin_constant_p(x) || (x)) { \
- __asm__ __volatile__( \
- "1: twnei %0,0\n" \
- ".section __bug_table,\"a\"\n\t" \
- " .long 1b,%1,%2,%3\n" \
- ".previous" \
- : : "r" (x), "i" (__LINE__), "i" (__FILE__), \
- "i" (__FUNCTION__)); \
- } \
-} while (0)
-
-#define WARN_ON(x) do { \
- if (!__builtin_constant_p(x) || (x)) { \
- __asm__ __volatile__( \
- "1: twnei %0,0\n" \
- ".section __bug_table,\"a\"\n\t" \
- " .long 1b,%1,%2,%3\n" \
- ".previous" \
- : : "r" (x), "i" (__LINE__ + BUG_WARNING_TRAP), \
- "i" (__FILE__), "i" (__FUNCTION__)); \
- } \
-} while (0)
-
-#define HAVE_ARCH_BUG
-#define HAVE_ARCH_BUG_ON
-#define HAVE_ARCH_WARN_ON
-#endif
-
-#include <asm-generic/bug.h>
-
-#endif
diff --git a/include/asm-ppc64/bug.h b/include/asm-ppc64/bug.h
deleted file mode 100644
--- a/include/asm-ppc64/bug.h
+++ /dev/null
@@ -1,69 +0,0 @@
-#ifndef _PPC64_BUG_H
-#define _PPC64_BUG_H
-
-/*
- * Define an illegal instr to trap on the bug.
- * We don't use 0 because that marks the end of a function
- * in the ELF ABI. That's "Boo Boo" in case you wonder...
- */
-#define BUG_OPCODE .long 0x00b00b00 /* For asm */
-#define BUG_ILLEGAL_INSTR "0x00b00b00" /* For BUG macro */
-
-#ifndef __ASSEMBLY__
-
-struct bug_entry {
- unsigned long bug_addr;
- long line;
- const char *file;
- const char *function;
-};
-
-struct bug_entry *find_bug(unsigned long bugaddr);
-
-/*
- * If this bit is set in the line number it means that the trap
- * is for WARN_ON rather than BUG or BUG_ON.
- */
-#define BUG_WARNING_TRAP 0x1000000
-
-#ifdef CONFIG_BUG
-
-#define BUG() do { \
- __asm__ __volatile__( \
- "1: twi 31,0,0\n" \
- ".section __bug_table,\"a\"\n\t" \
- " .llong 1b,%0,%1,%2\n" \
- ".previous" \
- : : "i" (__LINE__), "i" (__FILE__), "i" (__FUNCTION__)); \
-} while (0)
-
-#define BUG_ON(x) do { \
- __asm__ __volatile__( \
- "1: tdnei %0,0\n" \
- ".section __bug_table,\"a\"\n\t" \
- " .llong 1b,%1,%2,%3\n" \
- ".previous" \
- : : "r" ((long long)(x)), "i" (__LINE__), \
- "i" (__FILE__), "i" (__FUNCTION__)); \
-} while (0)
-
-#define WARN_ON(x) do { \
- __asm__ __volatile__( \
- "1: tdnei %0,0\n" \
- ".section __bug_table,\"a\"\n\t" \
- " .llong 1b,%1,%2,%3\n" \
- ".previous" \
- : : "r" ((long long)(x)), \
- "i" (__LINE__ + BUG_WARNING_TRAP), \
- "i" (__FILE__), "i" (__FUNCTION__)); \
-} while (0)
-
-#define HAVE_ARCH_BUG
-#define HAVE_ARCH_BUG_ON
-#define HAVE_ARCH_WARN_ON
-#endif
-#endif
-
-#include <asm-generic/bug.h>
-
-#endif
^ permalink raw reply
* Add Pantelis' OF Flat Dev Tree bits?
From: Jon Loeliger @ 2005-09-19 22:31 UTC (permalink / raw)
To: linuxppc-dev, linuxppc64-dev
Avast, Cap'n Paul!
Did ye wan ta add Pantelis Antoniou's patch ta
support OF Flat Dev Tree to the powerpc-merge tree?
His patch be dated Sep-03, but I don't think I'll
be directly repostin' that booty here.
jdl
^ permalink raw reply
* [PATCH] powerpc: Merge elf.h
From: Becky Bruce @ 2005-09-20 0:17 UTC (permalink / raw)
To: linuxppc64-dev, linuxppc-dev
ppc/ppc64: Merge elf.h into include/asm-powerpc
Merge elf.h into a single include file for 32 and 64-bit ppc platforms. This
patch has been tested on 32-bit and built on 64-bit platforms.
Signed-off-by: Kumar Gala <kumar.gala@freescale.com>
Signed-off-by: Becky Bruce <Becky.Bruce@freescale.com>
---
commit 4377f15fe916f0ef45e5204537be7efa2c6d1872
tree 144f0009ea0246044f1a36693512cc358fc01058
parent a374ad4968cd7b4b45443328b608b459add77a2e
author Becky Bruce <becky.bruce@freescale.com> Mon, 19 Sep 2005 19:13:34 -0500
committer Becky Bruce <becky.bruce@freescale.com> Mon, 19 Sep 2005 19:13:34 -0500
include/asm-powerpc/elf.h | 414 +++++++++++++++++++++++++++++++++++++++++++++
include/asm-ppc/elf.h | 151 ----------------
include/asm-ppc64/elf.h | 387 ------------------------------------------
3 files changed, 414 insertions(+), 538 deletions(-)
diff --git a/include/asm-powerpc/elf.h b/include/asm-powerpc/elf.h
new file mode 100644
--- /dev/null
+++ b/include/asm-powerpc/elf.h
@@ -0,0 +1,414 @@
+#ifndef _ASM_POWERPC_ELF_H
+#define _ASM_POWERPC_ELF_H
+
+#include <asm/types.h>
+#include <asm/ptrace.h>
+#include <asm/cputable.h>
+#include <asm/auxvec.h>
+
+/* PowerPC relocations defined by the ABIs */
+#define R_PPC_NONE 0
+#define R_PPC_ADDR32 1 /* 32bit absolute address */
+#define R_PPC_ADDR24 2 /* 26bit address, 2 bits ignored. */
+#define R_PPC_ADDR16 3 /* 16bit absolute address */
+#define R_PPC_ADDR16_LO 4 /* lower 16bit of absolute address */
+#define R_PPC_ADDR16_HI 5 /* high 16bit of absolute address */
+#define R_PPC_ADDR16_HA 6 /* adjusted high 16bit */
+#define R_PPC_ADDR14 7 /* 16bit address, 2 bits ignored */
+#define R_PPC_ADDR14_BRTAKEN 8
+#define R_PPC_ADDR14_BRNTAKEN 9
+#define R_PPC_REL24 10 /* PC relative 26 bit */
+#define R_PPC_REL14 11 /* PC relative 16 bit */
+#define R_PPC_REL14_BRTAKEN 12
+#define R_PPC_REL14_BRNTAKEN 13
+#define R_PPC_GOT16 14
+#define R_PPC_GOT16_LO 15
+#define R_PPC_GOT16_HI 16
+#define R_PPC_GOT16_HA 17
+#define R_PPC_PLTREL24 18
+#define R_PPC_COPY 19
+#define R_PPC_GLOB_DAT 20
+#define R_PPC_JMP_SLOT 21
+#define R_PPC_RELATIVE 22
+#define R_PPC_LOCAL24PC 23
+#define R_PPC_UADDR32 24
+#define R_PPC_UADDR16 25
+#define R_PPC_REL32 26
+#define R_PPC_PLT32 27
+#define R_PPC_PLTREL32 28
+#define R_PPC_PLT16_LO 29
+#define R_PPC_PLT16_HI 30
+#define R_PPC_PLT16_HA 31
+#define R_PPC_SDAREL16 32
+#define R_PPC_SECTOFF 33
+#define R_PPC_SECTOFF_LO 34
+#define R_PPC_SECTOFF_HI 35
+#define R_PPC_SECTOFF_HA 36
+
+/* PowerPC relocations defined for the TLS access ABI. */
+#define R_PPC_TLS 67 /* none (sym+add)@tls */
+#define R_PPC_DTPMOD32 68 /* word32 (sym+add)@dtpmod */
+#define R_PPC_TPREL16 69 /* half16* (sym+add)@tprel */
+#define R_PPC_TPREL16_LO 70 /* half16 (sym+add)@tprel@l */
+#define R_PPC_TPREL16_HI 71 /* half16 (sym+add)@tprel@h */
+#define R_PPC_TPREL16_HA 72 /* half16 (sym+add)@tprel@ha */
+#define R_PPC_TPREL32 73 /* word32 (sym+add)@tprel */
+#define R_PPC_DTPREL16 74 /* half16* (sym+add)@dtprel */
+#define R_PPC_DTPREL16_LO 75 /* half16 (sym+add)@dtprel@l */
+#define R_PPC_DTPREL16_HI 76 /* half16 (sym+add)@dtprel@h */
+#define R_PPC_DTPREL16_HA 77 /* half16 (sym+add)@dtprel@ha */
+#define R_PPC_DTPREL32 78 /* word32 (sym+add)@dtprel */
+#define R_PPC_GOT_TLSGD16 79 /* half16* (sym+add)@got@tlsgd */
+#define R_PPC_GOT_TLSGD16_LO 80 /* half16 (sym+add)@got@tlsgd@l */
+#define R_PPC_GOT_TLSGD16_HI 81 /* half16 (sym+add)@got@tlsgd@h */
+#define R_PPC_GOT_TLSGD16_HA 82 /* half16 (sym+add)@got@tlsgd@ha */
+#define R_PPC_GOT_TLSLD16 83 /* half16* (sym+add)@got@tlsld */
+#define R_PPC_GOT_TLSLD16_LO 84 /* half16 (sym+add)@got@tlsld@l */
+#define R_PPC_GOT_TLSLD16_HI 85 /* half16 (sym+add)@got@tlsld@h */
+#define R_PPC_GOT_TLSLD16_HA 86 /* half16 (sym+add)@got@tlsld@ha */
+#define R_PPC_GOT_TPREL16 87 /* half16* (sym+add)@got@tprel */
+#define R_PPC_GOT_TPREL16_LO 88 /* half16 (sym+add)@got@tprel@l */
+#define R_PPC_GOT_TPREL16_HI 89 /* half16 (sym+add)@got@tprel@h */
+#define R_PPC_GOT_TPREL16_HA 90 /* half16 (sym+add)@got@tprel@ha */
+#define R_PPC_GOT_DTPREL16 91 /* half16* (sym+add)@got@dtprel */
+#define R_PPC_GOT_DTPREL16_LO 92 /* half16* (sym+add)@got@dtprel@l */
+#define R_PPC_GOT_DTPREL16_HI 93 /* half16* (sym+add)@got@dtprel@h */
+#define R_PPC_GOT_DTPREL16_HA 94 /* half16* (sym+add)@got@dtprel@ha */
+
+/* keep this the last entry. */
+#define R_PPC_NUM 95
+
+/*
+ * ELF register definitions..
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#include <asm/ptrace.h>
+
+#define ELF_NGREG 48 /* includes nip, msr, lr, etc. */
+#define ELF_NFPREG 33 /* includes fpscr */
+
+typedef unsigned long elf_greg_t64;
+typedef elf_greg_t64 elf_gregset_t64[ELF_NGREG];
+
+typedef unsigned int elf_greg_t32;
+typedef elf_greg_t32 elf_gregset_t32[ELF_NGREG];
+
+/*
+ * ELF_ARCH, CLASS, and DATA are used to set parameters in the core dumps.
+ */
+#ifdef __powerpc64__
+# define ELF_NVRREG32 33 /* includes vscr & vrsave stuffed together */
+# define ELF_NVRREG 34 /* includes vscr & vrsave in split vectors */
+# define ELF_GREG_TYPE elf_greg_t64
+#else
+# define ELF_NEVRREG 34 /* includes acc (as 2) */
+# define ELF_NVRREG 33 /* includes vscr */
+# define ELF_GREG_TYPE elf_greg_t32
+# define ELF_ARCH EM_PPC
+# define ELF_CLASS ELFCLASS32
+# define ELF_DATA ELFDATA2MSB
+#endif /* __powerpc64__ */
+
+#ifndef ELF_ARCH
+# define ELF_ARCH EM_PPC64
+# define ELF_CLASS ELFCLASS64
+# define ELF_DATA ELFDATA2MSB
+ typedef elf_greg_t64 elf_greg_t;
+ typedef elf_gregset_t64 elf_gregset_t;
+# define elf_addr_t unsigned long
+#else
+ /* Assumption: ELF_ARCH == EM_PPC and ELF_CLASS == ELFCLASS32 */
+ typedef elf_greg_t32 elf_greg_t;
+ typedef elf_gregset_t32 elf_gregset_t;
+# define elf_addr_t u32
+#endif /* ELF_ARCH */
+
+/* Floating point registers */
+typedef double elf_fpreg_t;
+typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
+
+/* Altivec registers */
+/*
+ * The entries with indexes 0-31 contain the corresponding vector registers.
+ * The entry with index 32 contains the vscr as the last word (offset 12)
+ * within the quadword. This allows the vscr to be stored as either a
+ * quadword (since it must be copied via a vector register to/from storage)
+ * or as a word.
+ *
+ * 64-bit kernel notes: The entry at index 33 contains the vrsave as the first
+ * word (offset 0) within the quadword.
+ *
+ * This definition of the VMX state is compatible with the current PPC32
+ * ptrace interface. This allows signal handling and ptrace to use the same
+ * structures. This also simplifies the implementation of a bi-arch
+ * (combined (32- and 64-bit) gdb.
+ *
+ * Note that it's _not_ compatible with 32 bits ucontext which stuffs the
+ * vrsave along with vscr and so only uses 33 vectors for the register set
+ */
+typedef __vector128 elf_vrreg_t;
+typedef elf_vrreg_t elf_vrregset_t[ELF_NVRREG];
+#ifdef __powerpc64__
+typedef elf_vrreg_t elf_vrregset_t32[ELF_NVRREG32];
+#endif
+
+/*
+ * This is used to ensure we don't load something for the wrong architecture.
+ */
+#define elf_check_arch(x) ((x)->e_machine == ELF_ARCH)
+
+#define USE_ELF_CORE_DUMP
+#define ELF_EXEC_PAGESIZE 4096
+
+/* This is the location that an ET_DYN program is loaded if exec'ed. Typical
+ use of this is to invoke "./ld.so someprog" to test out a new version of
+ the loader. We need to make sure that it is out of the way of the program
+ that it will "exec", and that there is sufficient room for the brk. */
+
+#define ELF_ET_DYN_BASE (0x08000000)
+
+#ifdef __KERNEL__
+
+/* Common routine for both 32-bit and 64-bit processes */
+static inline void ppc_elf_core_copy_regs(elf_gregset_t elf_regs,
+ struct pt_regs *regs)
+{
+ int i;
+ int gprs = sizeof(struct pt_regs)/sizeof(ELF_GREG_TYPE);
+
+ if (gprs > ELF_NGREG)
+ gprs = ELF_NGREG;
+
+ for (i=0; i < gprs; i++)
+ elf_regs[i] = (elf_greg_t)((ELF_GREG_TYPE *)regs)[i];
+
+ memset((char *)(elf_regs) + sizeof(struct pt_regs), 0, \
+ sizeof(elf_gregset_t) - sizeof(struct pt_regs));
+
+}
+#define ELF_CORE_COPY_REGS(gregs, regs) ppc_elf_core_copy_regs(gregs, regs);
+
+static inline int dump_task_regs(struct task_struct *tsk,
+ elf_gregset_t *elf_regs)
+{
+ struct pt_regs *regs = tsk->thread.regs;
+ if (regs)
+ ppc_elf_core_copy_regs(*elf_regs, regs);
+
+ return 1;
+}
+#define ELF_CORE_COPY_TASK_REGS(tsk, elf_regs) dump_task_regs(tsk, elf_regs)
+
+extern int dump_task_fpu(struct task_struct *, elf_fpregset_t *);
+#define ELF_CORE_COPY_FPREGS(tsk, elf_fpregs) dump_task_fpu(tsk, elf_fpregs)
+
+#endif /* __KERNEL__ */
+
+/* ELF_HWCAP yields a mask that user programs can use to figure out what
+ instruction set this cpu supports. This could be done in userspace,
+ but it's not easy, and we've already done it here. */
+#ifdef __powerpc64__
+# define ELF_HWCAP (cur_cpu_spec->cpu_user_features)
+# define ELF_PLAT_INIT(_r, load_addr) do { \
+ memset(_r->gpr, 0, sizeof(_r->gpr)); \
+ _r->ctr = _r->link = _r->xer = _r->ccr = 0; \
+ _r->gpr[2] = load_addr; \
+} while (0)
+#else
+# define ELF_HWCAP (cur_cpu_spec[0]->cpu_user_features)
+#endif /* __powerpc64__ */
+
+/* This yields a string that ld.so will use to load implementation
+ specific libraries for optimization. This is more specific in
+ intent than poking at uname or /proc/cpuinfo.
+
+ For the moment, we have only optimizations for the Intel generations,
+ but that could change... */
+
+#define ELF_PLATFORM (NULL)
+
+#ifdef __KERNEL__
+
+#ifdef __powerpc64__
+# define SET_PERSONALITY(ex, ibcs2) \
+do { \
+ unsigned long new_flags = 0; \
+ if ((ex).e_ident[EI_CLASS] == ELFCLASS32) \
+ new_flags = _TIF_32BIT; \
+ if ((current_thread_info()->flags & _TIF_32BIT) \
+ != new_flags) \
+ set_thread_flag(TIF_ABI_PENDING); \
+ else \
+ clear_thread_flag(TIF_ABI_PENDING); \
+ if (personality(current->personality) != PER_LINUX32) \
+ set_personality(PER_LINUX); \
+} while (0)
+/*
+ * An executable for which elf_read_implies_exec() returns TRUE will
+ * have the READ_IMPLIES_EXEC personality flag set automatically. This
+ * is only required to work around bugs in old 32bit toolchains. Since
+ * the 64bit ABI has never had these issues dont enable the workaround
+ * even if we have an executable stack.
+ */
+# define elf_read_implies_exec(ex, exec_stk) (test_thread_flag(TIF_32BIT) ? \
+ (exec_stk != EXSTACK_DISABLE_X) : 0)
+#else
+# define SET_PERSONALITY(ex, ibcs2) set_personality((ibcs2)?PER_SVR4:PER_LINUX)
+#endif /* __powerpc64__ */
+
+#endif /* __KERNEL__ */
+
+extern int dcache_bsize;
+extern int icache_bsize;
+extern int ucache_bsize;
+
+#ifdef __powerpc64__
+struct linux_binprm;
+#define ARCH_HAS_SETUP_ADDITIONAL_PAGES /* vDSO has arch_setup_additional_pages */
+extern int arch_setup_additional_pages(struct linux_binprm *bprm, int executable_stack);
+#define VDSO_AUX_ENT(a,b) NEW_AUX_ENT(a,b);
+#else
+#define VDSO_AUX_ENT(a,b)
+#endif /* __powerpc64__ */
+
+/*
+ * The requirements here are:
+ * - keep the final alignment of sp (sp & 0xf)
+ * - make sure the 32-bit value at the first 16 byte aligned position of
+ * AUXV is greater than 16 for glibc compatibility.
+ * AT_IGNOREPPC is used for that.
+ * - for compatibility with glibc ARCH_DLINFO must always be defined on PPC,
+ * even if DLINFO_ARCH_ITEMS goes to zero or is undefined.
+ */
+#define ARCH_DLINFO \
+do { \
+ /* Handle glibc compatibility. */ \
+ NEW_AUX_ENT(AT_IGNOREPPC, AT_IGNOREPPC); \
+ NEW_AUX_ENT(AT_IGNOREPPC, AT_IGNOREPPC); \
+ /* Cache size items */ \
+ NEW_AUX_ENT(AT_DCACHEBSIZE, dcache_bsize); \
+ NEW_AUX_ENT(AT_ICACHEBSIZE, icache_bsize); \
+ NEW_AUX_ENT(AT_UCACHEBSIZE, ucache_bsize); \
+ VDSO_AUX_ENT(AT_SYSINFO_EHDR, current->thread.vdso_base) \
+} while (0)
+
+/* PowerPC64 relocations defined by the ABIs */
+#define R_PPC64_NONE R_PPC_NONE
+#define R_PPC64_ADDR32 R_PPC_ADDR32 /* 32bit absolute address. */
+#define R_PPC64_ADDR24 R_PPC_ADDR24 /* 26bit address, word aligned. */
+#define R_PPC64_ADDR16 R_PPC_ADDR16 /* 16bit absolute address. */
+#define R_PPC64_ADDR16_LO R_PPC_ADDR16_LO /* lower 16bits of abs. address. */
+#define R_PPC64_ADDR16_HI R_PPC_ADDR16_HI /* high 16bits of abs. address. */
+#define R_PPC64_ADDR16_HA R_PPC_ADDR16_HA /* adjusted high 16bits. */
+#define R_PPC64_ADDR14 R_PPC_ADDR14 /* 16bit address, word aligned. */
+#define R_PPC64_ADDR14_BRTAKEN R_PPC_ADDR14_BRTAKEN
+#define R_PPC64_ADDR14_BRNTAKEN R_PPC_ADDR14_BRNTAKEN
+#define R_PPC64_REL24 R_PPC_REL24 /* PC relative 26 bit, word aligned. */
+#define R_PPC64_REL14 R_PPC_REL14 /* PC relative 16 bit. */
+#define R_PPC64_REL14_BRTAKEN R_PPC_REL14_BRTAKEN
+#define R_PPC64_REL14_BRNTAKEN R_PPC_REL14_BRNTAKEN
+#define R_PPC64_GOT16 R_PPC_GOT16
+#define R_PPC64_GOT16_LO R_PPC_GOT16_LO
+#define R_PPC64_GOT16_HI R_PPC_GOT16_HI
+#define R_PPC64_GOT16_HA R_PPC_GOT16_HA
+
+#define R_PPC64_COPY R_PPC_COPY
+#define R_PPC64_GLOB_DAT R_PPC_GLOB_DAT
+#define R_PPC64_JMP_SLOT R_PPC_JMP_SLOT
+#define R_PPC64_RELATIVE R_PPC_RELATIVE
+
+#define R_PPC64_UADDR32 R_PPC_UADDR32
+#define R_PPC64_UADDR16 R_PPC_UADDR16
+#define R_PPC64_REL32 R_PPC_REL32
+#define R_PPC64_PLT32 R_PPC_PLT32
+#define R_PPC64_PLTREL32 R_PPC_PLTREL32
+#define R_PPC64_PLT16_LO R_PPC_PLT16_LO
+#define R_PPC64_PLT16_HI R_PPC_PLT16_HI
+#define R_PPC64_PLT16_HA R_PPC_PLT16_HA
+
+#define R_PPC64_SECTOFF R_PPC_SECTOFF
+#define R_PPC64_SECTOFF_LO R_PPC_SECTOFF_LO
+#define R_PPC64_SECTOFF_HI R_PPC_SECTOFF_HI
+#define R_PPC64_SECTOFF_HA R_PPC_SECTOFF_HA
+#define R_PPC64_ADDR30 37 /* word30 (S + A - P) >> 2. */
+#define R_PPC64_ADDR64 38 /* doubleword64 S + A. */
+#define R_PPC64_ADDR16_HIGHER 39 /* half16 #higher(S + A). */
+#define R_PPC64_ADDR16_HIGHERA 40 /* half16 #highera(S + A). */
+#define R_PPC64_ADDR16_HIGHEST 41 /* half16 #highest(S + A). */
+#define R_PPC64_ADDR16_HIGHESTA 42 /* half16 #highesta(S + A). */
+#define R_PPC64_UADDR64 43 /* doubleword64 S + A. */
+#define R_PPC64_REL64 44 /* doubleword64 S + A - P. */
+#define R_PPC64_PLT64 45 /* doubleword64 L + A. */
+#define R_PPC64_PLTREL64 46 /* doubleword64 L + A - P. */
+#define R_PPC64_TOC16 47 /* half16* S + A - .TOC. */
+#define R_PPC64_TOC16_LO 48 /* half16 #lo(S + A - .TOC.). */
+#define R_PPC64_TOC16_HI 49 /* half16 #hi(S + A - .TOC.). */
+#define R_PPC64_TOC16_HA 50 /* half16 #ha(S + A - .TOC.). */
+#define R_PPC64_TOC 51 /* doubleword64 .TOC. */
+#define R_PPC64_PLTGOT16 52 /* half16* M + A. */
+#define R_PPC64_PLTGOT16_LO 53 /* half16 #lo(M + A). */
+#define R_PPC64_PLTGOT16_HI 54 /* half16 #hi(M + A). */
+#define R_PPC64_PLTGOT16_HA 55 /* half16 #ha(M + A). */
+
+#define R_PPC64_ADDR16_DS 56 /* half16ds* (S + A) >> 2. */
+#define R_PPC64_ADDR16_LO_DS 57 /* half16ds #lo(S + A) >> 2. */
+#define R_PPC64_GOT16_DS 58 /* half16ds* (G + A) >> 2. */
+#define R_PPC64_GOT16_LO_DS 59 /* half16ds #lo(G + A) >> 2. */
+#define R_PPC64_PLT16_LO_DS 60 /* half16ds #lo(L + A) >> 2. */
+#define R_PPC64_SECTOFF_DS 61 /* half16ds* (R + A) >> 2. */
+#define R_PPC64_SECTOFF_LO_DS 62 /* half16ds #lo(R + A) >> 2. */
+#define R_PPC64_TOC16_DS 63 /* half16ds* (S + A - .TOC.) >> 2. */
+#define R_PPC64_TOC16_LO_DS 64 /* half16ds #lo(S + A - .TOC.) >> 2. */
+#define R_PPC64_PLTGOT16_DS 65 /* half16ds* (M + A) >> 2. */
+#define R_PPC64_PLTGOT16_LO_DS 66 /* half16ds #lo(M + A) >> 2. */
+
+/* PowerPC64 relocations defined for the TLS access ABI. */
+#define R_PPC64_TLS 67 /* none (sym+add)@tls */
+#define R_PPC64_DTPMOD64 68 /* doubleword64 (sym+add)@dtpmod */
+#define R_PPC64_TPREL16 69 /* half16* (sym+add)@tprel */
+#define R_PPC64_TPREL16_LO 70 /* half16 (sym+add)@tprel@l */
+#define R_PPC64_TPREL16_HI 71 /* half16 (sym+add)@tprel@h */
+#define R_PPC64_TPREL16_HA 72 /* half16 (sym+add)@tprel@ha */
+#define R_PPC64_TPREL64 73 /* doubleword64 (sym+add)@tprel */
+#define R_PPC64_DTPREL16 74 /* half16* (sym+add)@dtprel */
+#define R_PPC64_DTPREL16_LO 75 /* half16 (sym+add)@dtprel@l */
+#define R_PPC64_DTPREL16_HI 76 /* half16 (sym+add)@dtprel@h */
+#define R_PPC64_DTPREL16_HA 77 /* half16 (sym+add)@dtprel@ha */
+#define R_PPC64_DTPREL64 78 /* doubleword64 (sym+add)@dtprel */
+#define R_PPC64_GOT_TLSGD16 79 /* half16* (sym+add)@got@tlsgd */
+#define R_PPC64_GOT_TLSGD16_LO 80 /* half16 (sym+add)@got@tlsgd@l */
+#define R_PPC64_GOT_TLSGD16_HI 81 /* half16 (sym+add)@got@tlsgd@h */
+#define R_PPC64_GOT_TLSGD16_HA 82 /* half16 (sym+add)@got@tlsgd@ha */
+#define R_PPC64_GOT_TLSLD16 83 /* half16* (sym+add)@got@tlsld */
+#define R_PPC64_GOT_TLSLD16_LO 84 /* half16 (sym+add)@got@tlsld@l */
+#define R_PPC64_GOT_TLSLD16_HI 85 /* half16 (sym+add)@got@tlsld@h */
+#define R_PPC64_GOT_TLSLD16_HA 86 /* half16 (sym+add)@got@tlsld@ha */
+#define R_PPC64_GOT_TPREL16_DS 87 /* half16ds* (sym+add)@got@tprel */
+#define R_PPC64_GOT_TPREL16_LO_DS 88 /* half16ds (sym+add)@got@tprel@l */
+#define R_PPC64_GOT_TPREL16_HI 89 /* half16 (sym+add)@got@tprel@h */
+#define R_PPC64_GOT_TPREL16_HA 90 /* half16 (sym+add)@got@tprel@ha */
+#define R_PPC64_GOT_DTPREL16_DS 91 /* half16ds* (sym+add)@got@dtprel */
+#define R_PPC64_GOT_DTPREL16_LO_DS 92 /* half16ds (sym+add)@got@dtprel@l */
+#define R_PPC64_GOT_DTPREL16_HI 93 /* half16 (sym+add)@got@dtprel@h */
+#define R_PPC64_GOT_DTPREL16_HA 94 /* half16 (sym+add)@got@dtprel@ha */
+#define R_PPC64_TPREL16_DS 95 /* half16ds* (sym+add)@tprel */
+#define R_PPC64_TPREL16_LO_DS 96 /* half16ds (sym+add)@tprel@l */
+#define R_PPC64_TPREL16_HIGHER 97 /* half16 (sym+add)@tprel@higher */
+#define R_PPC64_TPREL16_HIGHERA 98 /* half16 (sym+add)@tprel@highera */
+#define R_PPC64_TPREL16_HIGHEST 99 /* half16 (sym+add)@tprel@highest */
+#define R_PPC64_TPREL16_HIGHESTA 100 /* half16 (sym+add)@tprel@highesta */
+#define R_PPC64_DTPREL16_DS 101 /* half16ds* (sym+add)@dtprel */
+#define R_PPC64_DTPREL16_LO_DS 102 /* half16ds (sym+add)@dtprel@l */
+#define R_PPC64_DTPREL16_HIGHER 103 /* half16 (sym+add)@dtprel@higher */
+#define R_PPC64_DTPREL16_HIGHERA 104 /* half16 (sym+add)@dtprel@highera */
+#define R_PPC64_DTPREL16_HIGHEST 105 /* half16 (sym+add)@dtprel@highest */
+#define R_PPC64_DTPREL16_HIGHESTA 106 /* half16 (sym+add)@dtprel@highesta */
+
+/* Keep this the last entry. */
+#define R_PPC64_NUM 107
+
+#endif /* _ASM_POWERPC_ELF_H */
diff --git a/include/asm-ppc/elf.h b/include/asm-ppc/elf.h
deleted file mode 100644
--- a/include/asm-ppc/elf.h
+++ /dev/null
@@ -1,151 +0,0 @@
-#ifndef __PPC_ELF_H
-#define __PPC_ELF_H
-
-/*
- * ELF register definitions..
- */
-#include <asm/types.h>
-#include <asm/ptrace.h>
-#include <asm/cputable.h>
-#include <asm/auxvec.h>
-
-/* PowerPC relocations defined by the ABIs */
-#define R_PPC_NONE 0
-#define R_PPC_ADDR32 1 /* 32bit absolute address */
-#define R_PPC_ADDR24 2 /* 26bit address, 2 bits ignored. */
-#define R_PPC_ADDR16 3 /* 16bit absolute address */
-#define R_PPC_ADDR16_LO 4 /* lower 16bit of absolute address */
-#define R_PPC_ADDR16_HI 5 /* high 16bit of absolute address */
-#define R_PPC_ADDR16_HA 6 /* adjusted high 16bit */
-#define R_PPC_ADDR14 7 /* 16bit address, 2 bits ignored */
-#define R_PPC_ADDR14_BRTAKEN 8
-#define R_PPC_ADDR14_BRNTAKEN 9
-#define R_PPC_REL24 10 /* PC relative 26 bit */
-#define R_PPC_REL14 11 /* PC relative 16 bit */
-#define R_PPC_REL14_BRTAKEN 12
-#define R_PPC_REL14_BRNTAKEN 13
-#define R_PPC_GOT16 14
-#define R_PPC_GOT16_LO 15
-#define R_PPC_GOT16_HI 16
-#define R_PPC_GOT16_HA 17
-#define R_PPC_PLTREL24 18
-#define R_PPC_COPY 19
-#define R_PPC_GLOB_DAT 20
-#define R_PPC_JMP_SLOT 21
-#define R_PPC_RELATIVE 22
-#define R_PPC_LOCAL24PC 23
-#define R_PPC_UADDR32 24
-#define R_PPC_UADDR16 25
-#define R_PPC_REL32 26
-#define R_PPC_PLT32 27
-#define R_PPC_PLTREL32 28
-#define R_PPC_PLT16_LO 29
-#define R_PPC_PLT16_HI 30
-#define R_PPC_PLT16_HA 31
-#define R_PPC_SDAREL16 32
-#define R_PPC_SECTOFF 33
-#define R_PPC_SECTOFF_LO 34
-#define R_PPC_SECTOFF_HI 35
-#define R_PPC_SECTOFF_HA 36
-/* Keep this the last entry. */
-#define R_PPC_NUM 37
-
-#define ELF_NGREG 48 /* includes nip, msr, lr, etc. */
-#define ELF_NFPREG 33 /* includes fpscr */
-#define ELF_NVRREG 33 /* includes vscr */
-#define ELF_NEVRREG 34 /* includes acc (as 2) */
-
-/*
- * These are used to set parameters in the core dumps.
- */
-#define ELF_ARCH EM_PPC
-#define ELF_CLASS ELFCLASS32
-#define ELF_DATA ELFDATA2MSB
-
-/* General registers */
-typedef unsigned long elf_greg_t;
-typedef elf_greg_t elf_gregset_t[ELF_NGREG];
-
-/* Floating point registers */
-typedef double elf_fpreg_t;
-typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
-
-/* Altivec registers */
-typedef __vector128 elf_vrreg_t;
-typedef elf_vrreg_t elf_vrregset_t[ELF_NVRREG];
-
-#ifdef __KERNEL__
-
-struct task_struct;
-
-/*
- * This is used to ensure we don't load something for the wrong architecture.
- */
-
-#define elf_check_arch(x) ((x)->e_machine == EM_PPC)
-
-/* This is the location that an ET_DYN program is loaded if exec'ed. Typical
- use of this is to invoke "./ld.so someprog" to test out a new version of
- the loader. We need to make sure that it is out of the way of the program
- that it will "exec", and that there is sufficient room for the brk. */
-
-#define ELF_ET_DYN_BASE (0x08000000)
-
-#define USE_ELF_CORE_DUMP
-#define ELF_EXEC_PAGESIZE 4096
-
-#define ELF_CORE_COPY_REGS(gregs, regs) \
- memcpy((gregs), (regs), sizeof(struct pt_regs)); \
- memset((char *)(gregs) + sizeof(struct pt_regs), 0, \
- sizeof(elf_gregset_t) - sizeof(struct pt_regs));
-
-#define ELF_CORE_COPY_TASK_REGS(t, elfregs) \
- ((t)->thread.regs? \
- ({ ELF_CORE_COPY_REGS((elfregs), (t)->thread.regs); 1; }): 0)
-
-extern int dump_task_fpu(struct task_struct *t, elf_fpregset_t *fpu);
-#define ELF_CORE_COPY_FPREGS(t, fpu) dump_task_fpu((t), (fpu))
-
-/* This yields a mask that user programs can use to figure out what
- instruction set this cpu supports. This could be done in userspace,
- but it's not easy, and we've already done it here. */
-
-#define ELF_HWCAP (cur_cpu_spec[0]->cpu_user_features)
-
-/* This yields a string that ld.so will use to load implementation
- specific libraries for optimization. This is more specific in
- intent than poking at uname or /proc/cpuinfo.
-
- For the moment, we have only optimizations for the Intel generations,
- but that could change... */
-
-#define ELF_PLATFORM (NULL)
-
-#define SET_PERSONALITY(ex, ibcs2) set_personality((ibcs2)?PER_SVR4:PER_LINUX)
-
-extern int dcache_bsize;
-extern int icache_bsize;
-extern int ucache_bsize;
-
-/*
- * The requirements here are:
- * - keep the final alignment of sp (sp & 0xf)
- * - make sure the 32-bit value at the first 16 byte aligned position of
- * AUXV is greater than 16 for glibc compatibility.
- * AT_IGNOREPPC is used for that.
- * - for compatibility with glibc ARCH_DLINFO must always be defined on PPC,
- * even if DLINFO_ARCH_ITEMS goes to zero or is undefined.
- */
-#define ARCH_DLINFO \
-do { \
- /* Handle glibc compatibility. */ \
- NEW_AUX_ENT(AT_IGNOREPPC, AT_IGNOREPPC); \
- NEW_AUX_ENT(AT_IGNOREPPC, AT_IGNOREPPC); \
- /* Cache size items */ \
- NEW_AUX_ENT(AT_DCACHEBSIZE, dcache_bsize); \
- NEW_AUX_ENT(AT_ICACHEBSIZE, icache_bsize); \
- NEW_AUX_ENT(AT_UCACHEBSIZE, ucache_bsize); \
- } while (0)
-
-#endif /* __KERNEL__ */
-#endif
diff --git a/include/asm-ppc64/elf.h b/include/asm-ppc64/elf.h
deleted file mode 100644
--- a/include/asm-ppc64/elf.h
+++ /dev/null
@@ -1,387 +0,0 @@
-#ifndef __PPC64_ELF_H
-#define __PPC64_ELF_H
-
-#include <asm/types.h>
-#include <asm/ptrace.h>
-#include <asm/cputable.h>
-#include <asm/auxvec.h>
-
-/* PowerPC relocations defined by the ABIs */
-#define R_PPC_NONE 0
-#define R_PPC_ADDR32 1 /* 32bit absolute address */
-#define R_PPC_ADDR24 2 /* 26bit address, 2 bits ignored. */
-#define R_PPC_ADDR16 3 /* 16bit absolute address */
-#define R_PPC_ADDR16_LO 4 /* lower 16bit of absolute address */
-#define R_PPC_ADDR16_HI 5 /* high 16bit of absolute address */
-#define R_PPC_ADDR16_HA 6 /* adjusted high 16bit */
-#define R_PPC_ADDR14 7 /* 16bit address, 2 bits ignored */
-#define R_PPC_ADDR14_BRTAKEN 8
-#define R_PPC_ADDR14_BRNTAKEN 9
-#define R_PPC_REL24 10 /* PC relative 26 bit */
-#define R_PPC_REL14 11 /* PC relative 16 bit */
-#define R_PPC_REL14_BRTAKEN 12
-#define R_PPC_REL14_BRNTAKEN 13
-#define R_PPC_GOT16 14
-#define R_PPC_GOT16_LO 15
-#define R_PPC_GOT16_HI 16
-#define R_PPC_GOT16_HA 17
-#define R_PPC_PLTREL24 18
-#define R_PPC_COPY 19
-#define R_PPC_GLOB_DAT 20
-#define R_PPC_JMP_SLOT 21
-#define R_PPC_RELATIVE 22
-#define R_PPC_LOCAL24PC 23
-#define R_PPC_UADDR32 24
-#define R_PPC_UADDR16 25
-#define R_PPC_REL32 26
-#define R_PPC_PLT32 27
-#define R_PPC_PLTREL32 28
-#define R_PPC_PLT16_LO 29
-#define R_PPC_PLT16_HI 30
-#define R_PPC_PLT16_HA 31
-#define R_PPC_SDAREL16 32
-#define R_PPC_SECTOFF 33
-#define R_PPC_SECTOFF_LO 34
-#define R_PPC_SECTOFF_HI 35
-#define R_PPC_SECTOFF_HA 36
-
-/* PowerPC relocations defined for the TLS access ABI. */
-#define R_PPC_TLS 67 /* none (sym+add)@tls */
-#define R_PPC_DTPMOD32 68 /* word32 (sym+add)@dtpmod */
-#define R_PPC_TPREL16 69 /* half16* (sym+add)@tprel */
-#define R_PPC_TPREL16_LO 70 /* half16 (sym+add)@tprel@l */
-#define R_PPC_TPREL16_HI 71 /* half16 (sym+add)@tprel@h */
-#define R_PPC_TPREL16_HA 72 /* half16 (sym+add)@tprel@ha */
-#define R_PPC_TPREL32 73 /* word32 (sym+add)@tprel */
-#define R_PPC_DTPREL16 74 /* half16* (sym+add)@dtprel */
-#define R_PPC_DTPREL16_LO 75 /* half16 (sym+add)@dtprel@l */
-#define R_PPC_DTPREL16_HI 76 /* half16 (sym+add)@dtprel@h */
-#define R_PPC_DTPREL16_HA 77 /* half16 (sym+add)@dtprel@ha */
-#define R_PPC_DTPREL32 78 /* word32 (sym+add)@dtprel */
-#define R_PPC_GOT_TLSGD16 79 /* half16* (sym+add)@got@tlsgd */
-#define R_PPC_GOT_TLSGD16_LO 80 /* half16 (sym+add)@got@tlsgd@l */
-#define R_PPC_GOT_TLSGD16_HI 81 /* half16 (sym+add)@got@tlsgd@h */
-#define R_PPC_GOT_TLSGD16_HA 82 /* half16 (sym+add)@got@tlsgd@ha */
-#define R_PPC_GOT_TLSLD16 83 /* half16* (sym+add)@got@tlsld */
-#define R_PPC_GOT_TLSLD16_LO 84 /* half16 (sym+add)@got@tlsld@l */
-#define R_PPC_GOT_TLSLD16_HI 85 /* half16 (sym+add)@got@tlsld@h */
-#define R_PPC_GOT_TLSLD16_HA 86 /* half16 (sym+add)@got@tlsld@ha */
-#define R_PPC_GOT_TPREL16 87 /* half16* (sym+add)@got@tprel */
-#define R_PPC_GOT_TPREL16_LO 88 /* half16 (sym+add)@got@tprel@l */
-#define R_PPC_GOT_TPREL16_HI 89 /* half16 (sym+add)@got@tprel@h */
-#define R_PPC_GOT_TPREL16_HA 90 /* half16 (sym+add)@got@tprel@ha */
-#define R_PPC_GOT_DTPREL16 91 /* half16* (sym+add)@got@dtprel */
-#define R_PPC_GOT_DTPREL16_LO 92 /* half16* (sym+add)@got@dtprel@l */
-#define R_PPC_GOT_DTPREL16_HI 93 /* half16* (sym+add)@got@dtprel@h */
-#define R_PPC_GOT_DTPREL16_HA 94 /* half16* (sym+add)@got@dtprel@ha */
-
-/* Keep this the last entry. */
-#define R_PPC_NUM 95
-
-/*
- * ELF register definitions..
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-#include <asm/ptrace.h>
-
-#define ELF_NGREG 48 /* includes nip, msr, lr, etc. */
-#define ELF_NFPREG 33 /* includes fpscr */
-#define ELF_NVRREG32 33 /* includes vscr & vrsave stuffed together */
-#define ELF_NVRREG 34 /* includes vscr & vrsave in split vectors */
-
-typedef unsigned long elf_greg_t64;
-typedef elf_greg_t64 elf_gregset_t64[ELF_NGREG];
-
-typedef unsigned int elf_greg_t32;
-typedef elf_greg_t32 elf_gregset_t32[ELF_NGREG];
-
-/*
- * These are used to set parameters in the core dumps.
- */
-#ifndef ELF_ARCH
-# define ELF_ARCH EM_PPC64
-# define ELF_CLASS ELFCLASS64
-# define ELF_DATA ELFDATA2MSB
- typedef elf_greg_t64 elf_greg_t;
- typedef elf_gregset_t64 elf_gregset_t;
-# define elf_addr_t unsigned long
-#else
- /* Assumption: ELF_ARCH == EM_PPC and ELF_CLASS == ELFCLASS32 */
- typedef elf_greg_t32 elf_greg_t;
- typedef elf_gregset_t32 elf_gregset_t;
-# define elf_addr_t u32
-#endif
-
-typedef double elf_fpreg_t;
-typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
-
-/* Altivec registers */
-/*
- * The entries with indexes 0-31 contain the corresponding vector registers.
- * The entry with index 32 contains the vscr as the last word (offset 12)
- * within the quadword. This allows the vscr to be stored as either a
- * quadword (since it must be copied via a vector register to/from storage)
- * or as a word. The entry with index 33 contains the vrsave as the first
- * word (offset 0) within the quadword.
- *
- * This definition of the VMX state is compatible with the current PPC32
- * ptrace interface. This allows signal handling and ptrace to use the same
- * structures. This also simplifies the implementation of a bi-arch
- * (combined (32- and 64-bit) gdb.
- *
- * Note that it's _not_ compatible with 32 bits ucontext which stuffs the
- * vrsave along with vscr and so only uses 33 vectors for the register set
- */
-typedef __vector128 elf_vrreg_t;
-typedef elf_vrreg_t elf_vrregset_t[ELF_NVRREG];
-typedef elf_vrreg_t elf_vrregset_t32[ELF_NVRREG32];
-
-/*
- * This is used to ensure we don't load something for the wrong architecture.
- */
-#define elf_check_arch(x) ((x)->e_machine == ELF_ARCH)
-
-#define USE_ELF_CORE_DUMP
-#define ELF_EXEC_PAGESIZE 4096
-
-/* This is the location that an ET_DYN program is loaded if exec'ed. Typical
- use of this is to invoke "./ld.so someprog" to test out a new version of
- the loader. We need to make sure that it is out of the way of the program
- that it will "exec", and that there is sufficient room for the brk. */
-
-#define ELF_ET_DYN_BASE (0x08000000)
-
-#ifdef __KERNEL__
-
-/* Common routine for both 32-bit and 64-bit processes */
-static inline void ppc64_elf_core_copy_regs(elf_gregset_t elf_regs,
- struct pt_regs *regs)
-{
- int i;
- int gprs = sizeof(struct pt_regs)/sizeof(elf_greg_t64);
-
- if (gprs > ELF_NGREG)
- gprs = ELF_NGREG;
-
- for (i=0; i < gprs; i++)
- elf_regs[i] = (elf_greg_t)((elf_greg_t64 *)regs)[i];
-}
-#define ELF_CORE_COPY_REGS(gregs, regs) ppc64_elf_core_copy_regs(gregs, regs);
-
-static inline int dump_task_regs(struct task_struct *tsk,
- elf_gregset_t *elf_regs)
-{
- struct pt_regs *regs = tsk->thread.regs;
- if (regs)
- ppc64_elf_core_copy_regs(*elf_regs, regs);
-
- return 1;
-}
-#define ELF_CORE_COPY_TASK_REGS(tsk, elf_regs) dump_task_regs(tsk, elf_regs)
-
-extern int dump_task_fpu(struct task_struct *, elf_fpregset_t *);
-#define ELF_CORE_COPY_FPREGS(tsk, elf_fpregs) dump_task_fpu(tsk, elf_fpregs)
-
-/* XXX Should we define the XFPREGS using altivec ??? */
-
-#endif
-
-/* This yields a mask that user programs can use to figure out what
- instruction set this cpu supports. This could be done in userspace,
- but it's not easy, and we've already done it here. */
-
-#define ELF_HWCAP (cur_cpu_spec->cpu_user_features)
-
-/* This yields a string that ld.so will use to load implementation
- specific libraries for optimization. This is more specific in
- intent than poking at uname or /proc/cpuinfo.
-
- For the moment, we have only optimizations for the Intel generations,
- but that could change... */
-
-#define ELF_PLATFORM (NULL)
-
-#define ELF_PLAT_INIT(_r, load_addr) do { \
- memset(_r->gpr, 0, sizeof(_r->gpr)); \
- _r->ctr = _r->link = _r->xer = _r->ccr = 0; \
- _r->gpr[2] = load_addr; \
-} while (0)
-
-#ifdef __KERNEL__
-#define SET_PERSONALITY(ex, ibcs2) \
-do { \
- unsigned long new_flags = 0; \
- if ((ex).e_ident[EI_CLASS] == ELFCLASS32) \
- new_flags = _TIF_32BIT; \
- if ((current_thread_info()->flags & _TIF_32BIT) \
- != new_flags) \
- set_thread_flag(TIF_ABI_PENDING); \
- else \
- clear_thread_flag(TIF_ABI_PENDING); \
- if (personality(current->personality) != PER_LINUX32) \
- set_personality(PER_LINUX); \
-} while (0)
-
-/*
- * An executable for which elf_read_implies_exec() returns TRUE will
- * have the READ_IMPLIES_EXEC personality flag set automatically. This
- * is only required to work around bugs in old 32bit toolchains. Since
- * the 64bit ABI has never had these issues dont enable the workaround
- * even if we have an executable stack.
- */
-#define elf_read_implies_exec(ex, exec_stk) (test_thread_flag(TIF_32BIT) ? \
- (exec_stk != EXSTACK_DISABLE_X) : 0)
-
-#endif
-
-extern int dcache_bsize;
-extern int icache_bsize;
-extern int ucache_bsize;
-
-/* We do have an arch_setup_additional_pages for vDSO matters */
-#define ARCH_HAS_SETUP_ADDITIONAL_PAGES
-struct linux_binprm;
-extern int arch_setup_additional_pages(struct linux_binprm *bprm, int executable_stack);
-
-/*
- * The requirements here are:
- * - keep the final alignment of sp (sp & 0xf)
- * - make sure the 32-bit value at the first 16 byte aligned position of
- * AUXV is greater than 16 for glibc compatibility.
- * AT_IGNOREPPC is used for that.
- * - for compatibility with glibc ARCH_DLINFO must always be defined on PPC,
- * even if DLINFO_ARCH_ITEMS goes to zero or is undefined.
- */
-#define ARCH_DLINFO \
-do { \
- /* Handle glibc compatibility. */ \
- NEW_AUX_ENT(AT_IGNOREPPC, AT_IGNOREPPC); \
- NEW_AUX_ENT(AT_IGNOREPPC, AT_IGNOREPPC); \
- /* Cache size items */ \
- NEW_AUX_ENT(AT_DCACHEBSIZE, dcache_bsize); \
- NEW_AUX_ENT(AT_ICACHEBSIZE, icache_bsize); \
- NEW_AUX_ENT(AT_UCACHEBSIZE, ucache_bsize); \
- /* vDSO base */ \
- NEW_AUX_ENT(AT_SYSINFO_EHDR, current->thread.vdso_base); \
- } while (0)
-
-/* PowerPC64 relocations defined by the ABIs */
-#define R_PPC64_NONE R_PPC_NONE
-#define R_PPC64_ADDR32 R_PPC_ADDR32 /* 32bit absolute address. */
-#define R_PPC64_ADDR24 R_PPC_ADDR24 /* 26bit address, word aligned. */
-#define R_PPC64_ADDR16 R_PPC_ADDR16 /* 16bit absolute address. */
-#define R_PPC64_ADDR16_LO R_PPC_ADDR16_LO /* lower 16bits of abs. address. */
-#define R_PPC64_ADDR16_HI R_PPC_ADDR16_HI /* high 16bits of abs. address. */
-#define R_PPC64_ADDR16_HA R_PPC_ADDR16_HA /* adjusted high 16bits. */
-#define R_PPC64_ADDR14 R_PPC_ADDR14 /* 16bit address, word aligned. */
-#define R_PPC64_ADDR14_BRTAKEN R_PPC_ADDR14_BRTAKEN
-#define R_PPC64_ADDR14_BRNTAKEN R_PPC_ADDR14_BRNTAKEN
-#define R_PPC64_REL24 R_PPC_REL24 /* PC relative 26 bit, word aligned. */
-#define R_PPC64_REL14 R_PPC_REL14 /* PC relative 16 bit. */
-#define R_PPC64_REL14_BRTAKEN R_PPC_REL14_BRTAKEN
-#define R_PPC64_REL14_BRNTAKEN R_PPC_REL14_BRNTAKEN
-#define R_PPC64_GOT16 R_PPC_GOT16
-#define R_PPC64_GOT16_LO R_PPC_GOT16_LO
-#define R_PPC64_GOT16_HI R_PPC_GOT16_HI
-#define R_PPC64_GOT16_HA R_PPC_GOT16_HA
-
-#define R_PPC64_COPY R_PPC_COPY
-#define R_PPC64_GLOB_DAT R_PPC_GLOB_DAT
-#define R_PPC64_JMP_SLOT R_PPC_JMP_SLOT
-#define R_PPC64_RELATIVE R_PPC_RELATIVE
-
-#define R_PPC64_UADDR32 R_PPC_UADDR32
-#define R_PPC64_UADDR16 R_PPC_UADDR16
-#define R_PPC64_REL32 R_PPC_REL32
-#define R_PPC64_PLT32 R_PPC_PLT32
-#define R_PPC64_PLTREL32 R_PPC_PLTREL32
-#define R_PPC64_PLT16_LO R_PPC_PLT16_LO
-#define R_PPC64_PLT16_HI R_PPC_PLT16_HI
-#define R_PPC64_PLT16_HA R_PPC_PLT16_HA
-
-#define R_PPC64_SECTOFF R_PPC_SECTOFF
-#define R_PPC64_SECTOFF_LO R_PPC_SECTOFF_LO
-#define R_PPC64_SECTOFF_HI R_PPC_SECTOFF_HI
-#define R_PPC64_SECTOFF_HA R_PPC_SECTOFF_HA
-#define R_PPC64_ADDR30 37 /* word30 (S + A - P) >> 2. */
-#define R_PPC64_ADDR64 38 /* doubleword64 S + A. */
-#define R_PPC64_ADDR16_HIGHER 39 /* half16 #higher(S + A). */
-#define R_PPC64_ADDR16_HIGHERA 40 /* half16 #highera(S + A). */
-#define R_PPC64_ADDR16_HIGHEST 41 /* half16 #highest(S + A). */
-#define R_PPC64_ADDR16_HIGHESTA 42 /* half16 #highesta(S + A). */
-#define R_PPC64_UADDR64 43 /* doubleword64 S + A. */
-#define R_PPC64_REL64 44 /* doubleword64 S + A - P. */
-#define R_PPC64_PLT64 45 /* doubleword64 L + A. */
-#define R_PPC64_PLTREL64 46 /* doubleword64 L + A - P. */
-#define R_PPC64_TOC16 47 /* half16* S + A - .TOC. */
-#define R_PPC64_TOC16_LO 48 /* half16 #lo(S + A - .TOC.). */
-#define R_PPC64_TOC16_HI 49 /* half16 #hi(S + A - .TOC.). */
-#define R_PPC64_TOC16_HA 50 /* half16 #ha(S + A - .TOC.). */
-#define R_PPC64_TOC 51 /* doubleword64 .TOC. */
-#define R_PPC64_PLTGOT16 52 /* half16* M + A. */
-#define R_PPC64_PLTGOT16_LO 53 /* half16 #lo(M + A). */
-#define R_PPC64_PLTGOT16_HI 54 /* half16 #hi(M + A). */
-#define R_PPC64_PLTGOT16_HA 55 /* half16 #ha(M + A). */
-
-#define R_PPC64_ADDR16_DS 56 /* half16ds* (S + A) >> 2. */
-#define R_PPC64_ADDR16_LO_DS 57 /* half16ds #lo(S + A) >> 2. */
-#define R_PPC64_GOT16_DS 58 /* half16ds* (G + A) >> 2. */
-#define R_PPC64_GOT16_LO_DS 59 /* half16ds #lo(G + A) >> 2. */
-#define R_PPC64_PLT16_LO_DS 60 /* half16ds #lo(L + A) >> 2. */
-#define R_PPC64_SECTOFF_DS 61 /* half16ds* (R + A) >> 2. */
-#define R_PPC64_SECTOFF_LO_DS 62 /* half16ds #lo(R + A) >> 2. */
-#define R_PPC64_TOC16_DS 63 /* half16ds* (S + A - .TOC.) >> 2. */
-#define R_PPC64_TOC16_LO_DS 64 /* half16ds #lo(S + A - .TOC.) >> 2. */
-#define R_PPC64_PLTGOT16_DS 65 /* half16ds* (M + A) >> 2. */
-#define R_PPC64_PLTGOT16_LO_DS 66 /* half16ds #lo(M + A) >> 2. */
-
-/* PowerPC64 relocations defined for the TLS access ABI. */
-#define R_PPC64_TLS 67 /* none (sym+add)@tls */
-#define R_PPC64_DTPMOD64 68 /* doubleword64 (sym+add)@dtpmod */
-#define R_PPC64_TPREL16 69 /* half16* (sym+add)@tprel */
-#define R_PPC64_TPREL16_LO 70 /* half16 (sym+add)@tprel@l */
-#define R_PPC64_TPREL16_HI 71 /* half16 (sym+add)@tprel@h */
-#define R_PPC64_TPREL16_HA 72 /* half16 (sym+add)@tprel@ha */
-#define R_PPC64_TPREL64 73 /* doubleword64 (sym+add)@tprel */
-#define R_PPC64_DTPREL16 74 /* half16* (sym+add)@dtprel */
-#define R_PPC64_DTPREL16_LO 75 /* half16 (sym+add)@dtprel@l */
-#define R_PPC64_DTPREL16_HI 76 /* half16 (sym+add)@dtprel@h */
-#define R_PPC64_DTPREL16_HA 77 /* half16 (sym+add)@dtprel@ha */
-#define R_PPC64_DTPREL64 78 /* doubleword64 (sym+add)@dtprel */
-#define R_PPC64_GOT_TLSGD16 79 /* half16* (sym+add)@got@tlsgd */
-#define R_PPC64_GOT_TLSGD16_LO 80 /* half16 (sym+add)@got@tlsgd@l */
-#define R_PPC64_GOT_TLSGD16_HI 81 /* half16 (sym+add)@got@tlsgd@h */
-#define R_PPC64_GOT_TLSGD16_HA 82 /* half16 (sym+add)@got@tlsgd@ha */
-#define R_PPC64_GOT_TLSLD16 83 /* half16* (sym+add)@got@tlsld */
-#define R_PPC64_GOT_TLSLD16_LO 84 /* half16 (sym+add)@got@tlsld@l */
-#define R_PPC64_GOT_TLSLD16_HI 85 /* half16 (sym+add)@got@tlsld@h */
-#define R_PPC64_GOT_TLSLD16_HA 86 /* half16 (sym+add)@got@tlsld@ha */
-#define R_PPC64_GOT_TPREL16_DS 87 /* half16ds* (sym+add)@got@tprel */
-#define R_PPC64_GOT_TPREL16_LO_DS 88 /* half16ds (sym+add)@got@tprel@l */
-#define R_PPC64_GOT_TPREL16_HI 89 /* half16 (sym+add)@got@tprel@h */
-#define R_PPC64_GOT_TPREL16_HA 90 /* half16 (sym+add)@got@tprel@ha */
-#define R_PPC64_GOT_DTPREL16_DS 91 /* half16ds* (sym+add)@got@dtprel */
-#define R_PPC64_GOT_DTPREL16_LO_DS 92 /* half16ds (sym+add)@got@dtprel@l */
-#define R_PPC64_GOT_DTPREL16_HI 93 /* half16 (sym+add)@got@dtprel@h */
-#define R_PPC64_GOT_DTPREL16_HA 94 /* half16 (sym+add)@got@dtprel@ha */
-#define R_PPC64_TPREL16_DS 95 /* half16ds* (sym+add)@tprel */
-#define R_PPC64_TPREL16_LO_DS 96 /* half16ds (sym+add)@tprel@l */
-#define R_PPC64_TPREL16_HIGHER 97 /* half16 (sym+add)@tprel@higher */
-#define R_PPC64_TPREL16_HIGHERA 98 /* half16 (sym+add)@tprel@highera */
-#define R_PPC64_TPREL16_HIGHEST 99 /* half16 (sym+add)@tprel@highest */
-#define R_PPC64_TPREL16_HIGHESTA 100 /* half16 (sym+add)@tprel@highesta */
-#define R_PPC64_DTPREL16_DS 101 /* half16ds* (sym+add)@dtprel */
-#define R_PPC64_DTPREL16_LO_DS 102 /* half16ds (sym+add)@dtprel@l */
-#define R_PPC64_DTPREL16_HIGHER 103 /* half16 (sym+add)@dtprel@higher */
-#define R_PPC64_DTPREL16_HIGHERA 104 /* half16 (sym+add)@dtprel@highera */
-#define R_PPC64_DTPREL16_HIGHEST 105 /* half16 (sym+add)@dtprel@highest */
-#define R_PPC64_DTPREL16_HIGHESTA 106 /* half16 (sym+add)@dtprel@highesta */
-
-/* Keep this the last entry. */
-#define R_PPC64_NUM 107
-
-#endif /* __PPC64_ELF_H */
^ permalink raw reply
* [PATCH] Add support for USB to 440EP platform files
From: Wade Farnsworth @ 2005-09-19 23:55 UTC (permalink / raw)
To: Matt Porter; +Cc: linuxppc-embedded
[-- Attachment #1: Type: text/plain, Size: 223 bytes --]
This adds support for the USB host and device interfaces on the 440EP to
the appropriate platform-specific files.
Signed off by: John Otken <jotken@softadvances.com>
Signed off by: Wade Farnsworth <wfarnsworth@mvista.com>
[-- Attachment #2: 440ep-ppc-usb.patch --]
[-- Type: text/x-patch, Size: 2374 bytes --]
diff -uprN linux-2.6/include/asm-ppc/ibm44x.h linux-2.6-dev/include/asm-ppc/ibm44x.h
--- linux-2.6/include/asm-ppc/ibm44x.h 2005-09-12 11:18:19.000000000 -0700
+++ linux-2.6-dev/include/asm-ppc/ibm44x.h 2005-09-13 13:51:23.000000000 -0700
@@ -169,6 +169,7 @@
#ifdef CONFIG_440EP
#define DCRN_SDR_UART2 0x0122
#define DCRN_SDR_UART3 0x0123
+#define DCRN_SDR_USB0 0x0320
#define DCRN_SDR_CUST0 0x4000
#endif
Binary files linux-2.6/arch/ppc/boot/images/ramdisk.gz and linux-2.6-dev/arch/ppc/boot/images/ramdisk.gz differ
Binary files linux-2.6/arch/ppc/boot/images/ramdisk.image.gz and linux-2.6-dev/arch/ppc/boot/images/ramdisk.image.gz differ
diff -uprN linux-2.6/arch/ppc/platforms/4xx/ibm440ep.c linux-2.6-dev/arch/ppc/platforms/4xx/ibm440ep.c
--- linux-2.6/arch/ppc/platforms/4xx/ibm440ep.c 2005-09-12 11:17:54.000000000 -0700
+++ linux-2.6-dev/arch/ppc/platforms/4xx/ibm440ep.c 2005-09-13 14:00:10.000000000 -0700
@@ -182,23 +182,48 @@ struct ppc4xx_uic_settings ppc4xx_core_u
},
};
-static struct resource usb_gadget_resources[] = {
+static struct resource ohci_usb_resources[] = {
[0] = {
- .start = 0x050000100ULL,
- .end = 0x05000017FULL,
+ .start = 0x0EF601000ULL,
+ .end = 0x0EF60107FULL,
.flags = IORESOURCE_MEM,
},
[1] = {
- .start = 55,
- .end = 55,
+ .start = 40,
+ .end = 40,
.flags = IORESOURCE_IRQ,
},
};
+static struct resource usb_gadget_resources[] = {
+ [0] = {
+ .start = 0x050000100ULL,
+ .end = 0x05000017FULL,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = 55,
+ .end = 55,
+ .flags = IORESOURCE_IRQ,
+ .name = "usb_device_irq",
+ },
+};
+
static u64 dma_mask = 0xffffffffULL;
+static struct platform_device ohci_usb_device = {
+ .name = "ppc-soc-ohci",
+ .id = 1,
+ .num_resources = ARRAY_SIZE(ohci_usb_resources),
+ .resource = ohci_usb_resources,
+ .dev = {
+ .dma_mask = &dma_mask,
+ .coherent_dma_mask = 0xffffffffULL,
+ }
+};
+
static struct platform_device usb_gadget_device = {
- .name = "musbhsfc",
+ .name = "musbhsfc_udc",
.id = 0,
.num_resources = ARRAY_SIZE(usb_gadget_resources),
.resource = usb_gadget_resources,
@@ -210,6 +235,7 @@ static struct platform_device usb_gadget
static struct platform_device *ibm440ep_devs[] __initdata = {
&usb_gadget_device,
+ &ohci_usb_device,
};
static int __init
^ permalink raw reply
* Esse Cartao foi feito para voce
From: cartoes @ 2005-09-20 3:08 UTC (permalink / raw)
To: linuxppc-embedded
[-- Attachment #1: Type: text/html, Size: 3656 bytes --]
^ permalink raw reply
* Re: [PATCH 1/2] Move Virtex-II Pro / ML300 port over to the platform bus.
From: Peter Korsgaard @ 2005-09-20 6:26 UTC (permalink / raw)
To: glikely; +Cc: linuxppc-embedded
In-Reply-To: <528646bc050910003630c25dca@mail.gmail.com>
>>>>> " " == Grant Likely <glikely@gmail.com> writes:
Hi,
> This is a large patch that moves the ML300 to the platform bus.
> It also isolates most of the linux tree from changes to the
> xparameters.h file. Ultimately, the goal is to move everything
> over to the flattened device tree for telling the kernel about
> devices. That way xparameters.h can go away entirely for the
> kernel proper. (Isolated to the bootloader)
Great!
> Comments are appreciated.
Here you go..
> diff --git a/arch/ppc/platforms/4xx/xilinx_ml300_devices.c
...
> +struct plat_serial8250_port serial_platform_data[] = {
> +#ifdef XPAR_OPB_UART16550_0_BASEADDR
> + {
> + .mapbase = XPAR_OPB_UART16550_0_BASEADDR + 3,
> + .irq = XPAR_DCR_INTC_0_OPB_UART16550_0_IP2INTC_IRPT_INTR,
> + .iotype = UPIO_MEM,
> + .uartclk = XPAR_XUARTNS550_CLOCK_HZ,
> + .flags = UPF_BOOT_AUTOCONF,
> + .regshift = 2,
> + },
> +#endif
> +#ifdef XPAR_OPB_UART16550_1_BASEADDR
> + {
> + .mapbase = XPAR_OPB_UART16550_1_BASEADDR + 3,
You forgot the offset of 0x1000 (did you mean
XPAR_UARTNS550_0_BASEADDR) ?
> diff --git a/arch/ppc/platforms/4xx/xparameters/xparameters.h
...
> + /* zImage serial port definitions */
> + #define SERIAL_PORT_DFNS { \
> + .baud_base = XPAR_XUARTNS550_CLOCK_HZ/16, \
> + .irq = XPAR_DCR_INTC_0_OPB_UART16550_0_IP2INTC_IRPT_INTR, \
> + .flags = ASYNC_BOOT_AUTOCONF, \
> + .iomem_base = (u8 *)XPAR_OPB_UART16550_0_BASEADDR + 3, \
And again.
Otherwise it looks good.
--
Bye, Peter Korsgaard
^ permalink raw reply
* Re: Which way to store log in flash on mpc8xx?
From: David Jander @ 2005-09-20 9:17 UTC (permalink / raw)
To: linuxppc-embedded
In-Reply-To: <20050919192101.C6267353BF3@atlas.denx.de>
Hi again,
On Monday 19 September 2005 21:21, Wolfgang Denk wrote:
>[...]
> Are you 100% sure your system is stable and wihout any memory errors?
> Never seen any other erros or crashes?
It has been running for several weeks without reboot processing data, and we
have never had any other strange things, nor data corruption, crashes, or
whatever.
> > My big question: Is it at all possible that gc.c comes to that BUG() in
> > line 139 because of anything other than a bug in jffs2-code?
>
> Yes, for example when your SDRAM initialization is broken and/or
> other memory corruption happens.
Then you would expect to have other symptoms too, don't you? Well, we don't
have any other symptoms of SDRAM errors. Although, I have seen PC's with
faulty SDRAM that behave as if the HD was broken, but the fine tool
"memtest86" finally revealed the truth ;-)
Is there something like memtest86 for linux-ppc (i.e. written in portable C)?
>[...]
> I don't think it's a flash error. If there is data corruption, then
> it's more likely the SDRAM.
Hmm, but.... there is no data corruption. I have not seen one file on flash
that had other data than intended, and that inspite of the GC freaking out.
> > The logs of almost all files in fs/jffs2/ which I have say that the
> > actual version corresponds to the CVS-snapshot of March 13, 2005, and
> > that the previous version of April 2004 is broken.
> > Which files were modified _after_ March 13, 2005?
> > (A hint to what command options or tools to use to browse cvs-logs more
> > easily at this point is appreciated... I am using cervisia).
>
> cvsps is really helpful, see http://www.cobite.com/cvsps/cvsps-2.1.tar.gz
>
> Also there are web interfaces to our kernel tree;
> for CVS see
> http://81.169.171.120/cgi-bin/cvsweb/
> for git see
> http://81.169.171.120/cgi-bin/gitweb.cgi
Thanks for the tips. The gitweb interface looked quite impressive!
> Make sure to use at least the version tagged as LABEL_2005_05_09_1245
> or later.
We have that version. I have been trying to figure out what changed up until
that label, but the only thing I found that looked relevant was:
"Re-implement PatchSets 260, 263 and 303"
That commit only changed 3 files, non of them directly related to jffs2 code,
and only seemed to add support for FUJITSU flash chips. What am I missing?
MTD developers say that cvs from march-2005 _is_ broken, so there must be some
evident bug-fixes in your tree since then.... otherwise it is still broken
(whatever it was).
Of course, maybe I'm just blind ;-)
> > I know about the problems jffs2 has with logfiles and alikes. I am still
> > thinking about what would be the most robust way of coping with this, and
> > until now, oversized partitions with log-rotation on size seems to do the
> > trick. I don't want to loose log-data on power-loss so I don't feel so
> > comfortable with buffering much of it in RAM.
>
> The problem with your approach is the number of erase cycles which
> will cause the flash to die sooner than you may want.
That's true, but under normal use, you'll have maybe 5..10 lines a day added
to a given logfile, maybe even less, and since the partition is relatively
huge, wear-levelling in the jffs2 driver should do the obvious I believe.
It's not optimal, but it should work reliably AFAICT.
Regards,
--
David Jander
Protonic Holland.
^ permalink raw reply
* Re: 8250 serial driver on MPC8272ADS board
From: Vitaly Bordug @ 2005-09-20 9:56 UTC (permalink / raw)
To: Landau, Bracha; +Cc: linuxppc-embedded list
In-Reply-To: <B621B955FA9FBB4C83F9724972F4DD1901CB5421@ILEX2.IL.NDS.COM>
Landau, Bracha wrote:
> I am running linux kernel 2.6.13 on a MPC8272ADS board. When I compile the kernel with the 8250 serial driver, the kernel crashes when loading it. It crashes also if compiled as a module and insmod'ed later.
> Has anyone had experience with this?
That's because this board does not have 8250 serial, you should use
CPM_UART(SCC1 and SCC4) instead (take a look at the
arch/ppc/configs/ads8272_defconfig)
--
Sincerely,
Vitaly
^ permalink raw reply
* ELDK included in which AMCC440EP Kit?
From: KylongMu @ 2005-09-20 15:17 UTC (permalink / raw)
To: Wolfgang Denk; +Cc: Linuxppc-embedded
[-- Attachment #1: Type: text/plain, Size: 244 bytes --]
Hi , Denk:
I'm going to buy the AMCC440EP Evaluation Kit , there are two
types : one is Bamboo , another is Yosemite .
Witch of them supported by ELDK , or both of them . There are
not clear message from web.
Thanks a lot!
KylongMu
[-- Attachment #2: Type: text/html, Size: 967 bytes --]
^ permalink raw reply
* MPC8250 MCC operating on 2-bit channels
From: Stevan Ignjatovic @ 2005-09-20 15:16 UTC (permalink / raw)
To: linuxppc-embedded
Hello,
My problem is concerned with the multi channel controller MCC2 on
MPC8250. Its task is to relay messages from D channels between Local
Exchange and ISDN BRA subscribers. All active D channels (up to 128) are
aggregated into single stream tied directly to the TDMc2, ie. both
TDMc2_Rx and TDMc2_Tx are divided into 2-bit channels. 2.048MHz clock
and 8KHz frame pulse are generated externaly and are connected to
corresponding processor pins (common pins for receive and transmit
sections).
When tested with internal loopback (SI2MR[SDM2]=0b10) everything works
fine, ie. for example the message we send through channel 0 is received
correctly on channel 0. However, it doesn't work in real application.
The debugging process led me to this simple test. I connected TDMc2_Rx
and TDMc2_Tx to FPGA in which I implemented the delay of N frames (N x
125us, since the frame pulse is 8KHz), such that for N=0 I have simple
external loopback, for N=1 delay of one entire frame, and so on. I was
sending messages through channel 0 (it is the only channel I actually
started). The results I obtained were very strange. For N=0, N=4, N=8
the received message was correct, but for N=1,2,3 it was not (I was
usually reported CRC erro,r or non octet alignment error, or abort).When
I tried with 4-bit channels, the result was correct for N=0,2,4,....
Only with 8-bit channels I obtained correct result for all frame delays.
The fact that everything works fine with 8-bit channels makes me believe
that all MCC and SIRAM settings are ok. I tried many combinations of
SIRAM programming (For example, I tried to program only channel 0 as
2-bit and all others as 8-bit, or as null entries), but it didn't work
out. It is also worth to mention that I have never received GUN or GOV
errors.
Has anybody dealt with 2-bit channels on MCC? What can cause such
problems (remember that everything works fine with 8-bit channels). I
would also appreciate if somebody has the possibility to implement
similar test.
Regards,
Stevan
^ permalink raw reply
* GT64260_eth (Ethernet) Driver
From: Earl Olsen @ 2005-09-20 16:02 UTC (permalink / raw)
To: linuxppc-embedded
[-- Attachment #1: Type: text/plain, Size: 2746 bytes --]
Does anybody know if this issue was solved?
I'm running into the exact same problem with 2.6.10.
Thanks
Dieu Morales wrote:
>Greetings, I am working with the latest 2.6.7 kernel
>source on a ppc radstone PPC7A board and was curious
>if anyone was in the process or planned on porting the
>gt64260_eth driver to support the 2.6.x kernel.
>
>Not being familiar with the gt64260 Ethernet device or
>code, I plan to take it line by line. I have attempted
>to use the driver from the ppc.bkbits.net 2.4
>development tree and currently have only changed the
>dev = init_etherdev(dev, sizeof (gt_eth_priv));
>to
>dev = alloc_etherdev(sizeof (gt_eth_priv_struct ));
>Shortly after, when attempting to allocate the Tx and
>Rx page buffers, I get an exception in the
>uncachedPages function. I have traced the problem to
>the pmd_presentò(*pmd) function in va_to_pte(addr)
>returning 0. I dumped the values of pmd, init_mm, and
>pmd in the va_to_pte() and the values seemed O.K., so
>I commented out the pmd_presentò(*pmd) check but was
>once again stopped by the pte_present(*pte) check. I
>have seen the driver operate under 2.4.26 dev tree
>from ppc.bkbits.net where this problem does not occur.
>One difference I have noticed is that during
>initialization of the 2.6.7 kernel, I do not get the
>following output.
>Buffer-cache hash table entries:
>Page-cache hash table entries:
>The filemap.c, where the "Page-cache " printk resides
>in 2.4, looks heavily reworked, so I don't suspect
>this is an issue?
>
>
Dieu,
You should sync up with Brian Waite (look at CC: list) who has been
looking at writing a new enet driver for the 2.6 kernel using the latest
bridge support code. You can get a look at the latest support code by
cloning bk://source.mvista.com/linux-2.5-marvell. Note the the mpsc
driver that's there still isn't working correctly.
Mark
--
Earl Olsen
Senior Software Engineer
Dilithium Networks, Inc.
TEL:+1 707-792-3925
earl.olsen@dilithiumnetworks.com
www.dilithiumnetworks.com
Communications for a Borderless World
This electronic message from Dilithium Networks contains information which may be privileged or confidential. It is intended to be for the use of the recipient(s) named above. If you are not the intended recipient please return the message to the sender by replying to it and then delete the message from your computer. Dilithium Networks shall not be held liable to any person resulting from the use of any information contained in this e-mail and shall not be liable to any person who acts or omits to do anything in reliance upon it. Dilithium Networks does not accept responsibility for changes made to this message after it was sent.
[-- Attachment #2: Type: text/html, Size: 4432 bytes --]
^ permalink raw reply
* Re: GT64260_eth (Ethernet) Driver
From: Brian Waite @ 2005-09-20 17:13 UTC (permalink / raw)
To: linuxppc-embedded
In-Reply-To: <B8561865DB141248943E2376D0E85215014202FE@DHOST001-17.DEX001.intermedia.net>
On Tuesday 20 September 2005 12:02 pm, Earl Olsen wrote:
> Does anybody know if this issue was solved?
> I'm running into the exact same problem with 2.6.10.
>
> Thanks
>
> Dieu Morales wrote:
> >Greetings, I am working with the latest 2.6.7 kernel
> >source on a ppc radstone PPC7A board and was curious
> >if anyone was in the process or planned on porting the
> >gt64260_eth driver to support the 2.6.x kernel.
2.6.7 is a really early version. I don't know of any working Marvel 64260 o=
r=20
64360 code in this time frame. I do know that the 64360 was patched to=20
mainline at ~2.6.13. Since then all real Marvel work should have been done =
on=20
mainline. I'd reccommend moving forward.
> >
> >Not being familiar with the gt64260 Ethernet device or
> >code, I plan to take it line by line.=20
That is probably a mistake for a number of reasons. First, you will not be=
=20
able to get this into the mainline because it does not use the=20
platform_device structures like the Marvell 64360 ethernet device. Secondly=
,=20
most of the developers doing Marvell work, are using the 64360 chipset. I'd=
=20
reccommend using a newer kernel and backporting the 64360 ethernet code to=
=20
64260. I just looked at my baseline tree (2.6.12-rc1) and see the only=20
platform using the 64260 chip, besides the eval board, was the cpci690.c. I=
=20
would look and see ifthis is still a working platform and base your platfor=
m=20
code off of that.
> >I have attempted=20
> >to use the driver from the ppc.bkbits.net 2.4
> >development tree and currently have only changed the
> >dev =3D init_etherdev(dev, sizeof (gt_eth_priv));
> >to
> >dev =3D alloc_etherdev(sizeof (gt_eth_priv_struct ));
> >Shortly after, when attempting to allocate the Tx and
> >Rx page buffers, I get an exception in the
> >uncachedPages function. I have traced the problem to
> >the pmd_present=C3=B2(*pmd) function in va_to_pte(addr)
> >returning 0. I dumped td the values seemed O.K., so
> >I commented out the pmd_present=C3=B2(*pmd) check but was
> >once again stopped by the pte_present(*pte) check. I
> >have seen the driver operate under 2.4.26 dev tree
> >from ppc.bkbits.net where this problem does not occur.
> >One difference I have noticed is that during
> >initialization of the 2.6.7 kernel, I do not get the
> >following output.
> >Buffer-cache hash table entries:
> >Page-cache hash table entries:
> >The filemap.c, where the "Page-cache " printk resides
> >in 2.4, looks heavily reworked, so I don't suspect
> >this is an issue?
>
> Dieu,
>
> You should sync up with Brian Waite (look at CC: list) who has been
> looking at writing a new enet driver for the 2.6 kernel using the latest
> bridge support code. You can get a look at the latest support code by
> cloning bk://source.mvista.com/linux-2.5-marvell. =20
No. Only use mainline kernel.org for latest support. Nothing else is workin=
g=20
100%. In the kernel.org tree the MPSC driver is working along with the 360=
=20
ethernet device.=20
> Note the the mpsc=20
> driver that's there still isn't working correctly.
I haven't loked at the 64260 for well over a year since we went to the 6436=
0.=20
The 260 was just too bad in too many respects. I was willing to test the 26=
0=20
code with my old hardware if there was a merged driver and even develop the=
=20
merged driver, but it became obvious the merged driver was going to be ugly
Thanks
Brian
^ permalink raw reply
* RE: MPC8250 MCC operating on 2-bit channels
From: Rune Torgersen @ 2005-09-20 17:42 UTC (permalink / raw)
To: Stevan Ignjatovic, linuxppc-embedded
> -----Original Message-----
> From: linuxppc-embedded-bounces@ozlabs.org Stevan Ignjatovic
> Sent: Tuesday, September 20, 2005 10:17
> Subject: MPC8250 MCC operating on 2-bit channels
> Has anybody dealt with 2-bit channels on MCC? What can cause such
> problems (remember that everything works fine with 8-bit channels). I
> would also appreciate if somebody has the possibility to implement
> similar test.
I am using 7 bit channels without any problems (tx and rx) on MCC 1 and
2.
(on an MPC8266)
Can you send me a dump of your SIRAM settings, and I'll take a look at
them?
Be aware of one thing (at least for 826x with 2 MCC's), first channel on
MCC2 is numbered 128, not 0
Rune Torgersen
^ permalink raw reply
* wait_event and interrupts
From: Rune Torgersen @ 2005-09-20 17:56 UTC (permalink / raw)
To: linuxppc-embedded
Hi
I have a driver that roughly does something like:
int driver_read(int cs, int addr, void *buf, int len)
{
hw_done =3D 0;
/* init_hw */
if (!hw_done)
{
ret =3D wait_event_interruptible_timeout(inq, hw_done, TIMEOUT);
if (ret =3D=3D 0)
{
if (hw_done)
goto hw_finished;
=09
return -EIO;
}
}
hw_finished:
return len;
}
static irqreturn_t myinterrupt(int irq, void * dev_id, struct pt_regs *
regs)
{
hw_done =3D 1;
schedule_work(&tqueue);
return IRQ_HANDLED;
}
static void do_softint(void *private_)
{
wake_up_interruptible(&inq);
}
I have a problem however with this, because in about 10% of my cases,
the interrupt triggers very fast, and ends up being served between the
check for hw_done and the wait_event call. This cause the wait to
timeout instead of getting waked up.
Is there a better way of doing this?
I do not want to do a busy wait, because the hardware can take up to
several 100's of ms to return, but most often returns within 20us.
^ permalink raw reply
* Re: Which way to store log in flash on mpc8xx?
From: Wolfgang Denk @ 2005-09-20 18:07 UTC (permalink / raw)
To: David Jander; +Cc: linuxppc-embedded
In-Reply-To: <200509201117.40454.david.jander@protonic.nl>
In message <200509201117.40454.david.jander@protonic.nl> you wrote:
>
> Is there something like memtest86 for linux-ppc (i.e. written in portable C)?
Yes, there is. Run the system with root file system mounted over NFS,
and then put some load on the system, like by compiling the linux
kernel on the target. Anything else which adds DMA load does not
hurt, either. In such a situation, with a lots of context switches,
stress on the memory management system and having a lots of DMA
traffic going on you may see some memory problems. Unfortunately none
of the standard memory tests will catch thse, as the tests usually
provide only plain read / write accesses, while the problems show up
only in burst mode, i. e. when filling the caches and/or doing DMA.
There is an attempt of a burst mode memory test in the U-Boot code,
but I have to admit that I didn't work to show the exact problem on
the system it was written for.
> Hmm, but.... there is no data corruption. I have not seen one file on flash
> that had other data than intended, and that inspite of the GC freaking out.
Maybe there is no corruption of the data in flash. But are you sure
that correct data are loaded to and read from RAM? We had a similar
problem on a board where data got corrupted only when doing a lot of
transfers flash->RAM.
> That commit only changed 3 files, non of them directly related to jffs2 code,
This is correct.
> and only seemed to add support for FUJITSU flash chips. What am I missing?
> MTD developers say that cvs from march-2005 _is_ broken, so there must be some
Yes, of course it's broken. Like all computer code. There are a
couple of known issues (especially with NAND flash), but I don't
think they could explain the type of problems you are seeing.
Best regards,
Wolfgang Denk
--
Software Engineering: Embedded and Realtime Systems, Embedded Linux
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de
Einstein argued that there must be simplified explanations of nature,
because God is not capricious or arbitrary. No such faith comforts
the software engineer. - Fred Brooks, Jr.
^ permalink raw reply
* Re: ELDK included in which AMCC440EP Kit?
From: Wolfgang Denk @ 2005-09-20 18:10 UTC (permalink / raw)
To: KylongMu; +Cc: Linuxppc-embedded
In-Reply-To: <20050920151811.C0246E55@smtp.263.net>
In message <20050920151811.C0246E55@smtp.263.net> you wrote:
>
> I'm going to buy the AMCC440EP Evaluation Kit , there are two
> types : one is Bamboo , another is Yosemite .
> Witch of them supported by ELDK , or both of them . There are
> not clear message from web.
The ELDK is a tool chain. It is hardware independent, so any 4xx/44x
board is "supported" by the ELDK.
Both the U-Boot and the Linux source code as available on the ELDK
CDROM image is too old for the Yosemite, but you can access the
current versions from our git/CVS/FTP servers, and then both Bamboo
and Yosemite are supported.
Best regards,
Wolfgang Denk
--
Software Engineering: Embedded and Realtime Systems, Embedded Linux
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de
"The more data I punch in this card, the lighter it becomes, and the
lower the mailing cost."
- Stan Kelly-Bootle, "The Devil's DP Dictionary"
^ permalink raw reply
* Re: GT64260_eth (Ethernet) Driver
From: Mark A. Greer @ 2005-09-20 18:32 UTC (permalink / raw)
To: Brian Waite; +Cc: linuxppc-embedded
In-Reply-To: <200509201313.48945.bwaite@irobot.com>
On Tue, Sep 20, 2005 at 01:13:48PM -0400, Brian Waite wrote:
> On Tuesday 20 September 2005 12:02 pm, Earl Olsen wrote:
> platform using the 64260 chip, besides the eval board, was the cpci690.c. I
> would look and see ifthis is still a working platform and base your platform
> code off of that.
The cpci690 is a working platform but it does not use the embedded enet
ctlr because there is no driver.
> > Dieu,
> >
> > You should sync up with Brian Waite (look at CC: list) who has been
> > looking at writing a new enet driver for the 2.6 kernel using the latest
> > bridge support code. You can get a look at the latest support code by
> > cloning bk://source.mvista.com/linux-2.5-marvell.
> No. Only use mainline kernel.org for latest support. Nothing else is working
> 100%. In the kernel.org tree the MPSC driver is working along with the 360
> ethernet device.
This is from a very, very old email that is no longer accurate. It
should be ignored. This is no tree except the mainline/mm tree and there
is not gt64260 enet driver in the mainline/mm tree (that I know of).
> > Note the the mpsc
> > driver that's there still isn't working correctly.
> I haven't loked at the 64260 for well over a year since we went to the 64360.
> The 260 was just too bad in too many respects. I was willing to test the 260
> code with my old hardware if there was a merged driver and even develop the
> merged driver, but it became obvious the merged driver was going to be ugly
Ditto.
Mark
^ permalink raw reply
* Re: wait_event and interrupts
From: Jeff Angielski @ 2005-09-20 18:40 UTC (permalink / raw)
To: Rune Torgersen; +Cc: linuxppc-embedded
In-Reply-To: <DCEAAC0833DD314AB0B58112AD99B93B859463@ismail.innsys.innovsys.com>
On Tue, 2005-09-20 at 12:56 -0500, Rune Torgersen wrote:
> Is there a better way of doing this?
If you *must* share the variable between interrupt and non-interrupt
context, you must mutex it in an interrupt safe way. The use of
spin_lock_irqsave() comes to mind for you read function.
But you are going to have other problems with this approach anyways
since you "appear" to be assuming a one-to-one relationship between your
interrupt handler and the read function. Is that really true?
Jeff Angielski
The PTR Group
^ permalink raw reply
* RE: wait_event and interrupts
From: Rune Torgersen @ 2005-09-20 19:14 UTC (permalink / raw)
To: jeff; +Cc: linuxppc-embedded
> -----Original Message-----
> From: Jeff Angielski [mailto:jeff@theptrgroup.com]=20
> Sent: Tuesday, September 20, 2005 13:40
> On Tue, 2005-09-20 at 12:56 -0500, Rune Torgersen wrote:
>=20
> > Is there a better way of doing this?
>=20
> If you *must* share the variable between interrupt and non-interrupt
> context, you must mutex it in an interrupt safe way. The use of
> spin_lock_irqsave() comes to mind for you read function.
The shared variable is an int, which should be atomic to access anyways.
Someone else told me to try to set the shared variable to volatile.
> But you are going to have other problems with this approach anyways
> since you "appear" to be assuming a one-to-one relationship=20
> between your
> interrupt handler and the read function. Is that really true?
Yes. The read function starts the hardware, and the hardware responds
with an interrupt when it's done.
^ permalink raw reply
* RE: Which way to store log in flash on mpc8xx?
From: Eli Brin @ 2005-09-20 20:25 UTC (permalink / raw)
To: David Jander; +Cc: linuxppc-embedded
Hello David,
Wolfgang wrote:
>Yes, there is. Run the system with root file system mounted over NFS,
>and then put some load on the system, like by compiling the linux
>kernel on the target.
If you want to have some fun, and stress the platform, compile and run (via
NFS) Crafty, an open source Linux chess porgram.
We did so on our 8xx target and it plays very well...
Best regards,
Eli Brin
^ permalink raw reply
* PATCH powerpc Merge asm-ppc*/vga.h
From: linuxppc @ 2005-09-20 19:32 UTC (permalink / raw)
To: linuxppc-dev, linuxppc64-dev
Merge asm-ppc*/vga.h
Signed-off-by: Jon Loeliger <jdl@freescale.com>
Signed-off-by: Kumar Gala <kumar.gala@freescale.com>
---
include/asm-powerpc/vga.h | 54 +++++++++++++++++++++++++++++++++++++++++++++
include/asm-ppc/vga.h | 46 --------------------------------------
include/asm-ppc64/vga.h | 50 ------------------------------------------
3 files changed, 54 insertions(+), 96 deletions(-)
diff --git a/include/asm-powerpc/vga.h b/include/asm-powerpc/vga.h
new file mode 100644
--- /dev/null
+++ b/include/asm-powerpc/vga.h
@@ -0,0 +1,54 @@
+#ifndef _ASM_POWERPC_VGA_H_
+#define _ASM_POWERPC_VGA_H_
+
+#ifdef __KERNEL__
+
+/*
+ * Access to VGA videoram
+ *
+ * (c) 1998 Martin Mares <mj@ucw.cz>
+ */
+
+
+#include <asm/io.h>
+
+#include <linux/config.h>
+
+#if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_MDA_CONSOLE)
+
+#define VT_BUF_HAVE_RW
+/*
+ * These are only needed for supporting VGA or MDA text mode, which use little
+ * endian byte ordering.
+ * In other cases, we can optimize by using native byte ordering and
+ * <linux/vt_buffer.h> has already done the right job for us.
+ */
+
+static inline void scr_writew(u16 val, volatile u16 *addr)
+{
+ st_le16(addr, val);
+}
+
+static inline u16 scr_readw(volatile const u16 *addr)
+{
+ return ld_le16(addr);
+}
+
+#define VT_BUF_HAVE_MEMCPYW
+#define scr_memcpyw memcpy
+
+#endif /* !CONFIG_VGA_CONSOLE && !CONFIG_MDA_CONSOLE */
+
+extern unsigned long vgacon_remap_base;
+
+#ifdef __powerpc64__
+#define VGA_MAP_MEM(x) ((unsigned long) ioremap((x), 0))
+#else
+#define VGA_MAP_MEM(x) (x + vgacon_remap_base)
+#endif
+
+#define vga_readb(x) (*(x))
+#define vga_writeb(x,y) (*(y) = (x))
+
+#endif /* __KERNEL__ */
+#endif /* _ASM_POWERPC_VGA_H_ */
diff --git a/include/asm-ppc/vga.h b/include/asm-ppc/vga.h
deleted file mode 100644
--- a/include/asm-ppc/vga.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * Access to VGA videoram
- *
- * (c) 1998 Martin Mares <mj@ucw.cz>
- */
-
-#ifdef __KERNEL__
-#ifndef _LINUX_ASM_VGA_H_
-#define _LINUX_ASM_VGA_H_
-
-#include <asm/io.h>
-
-#include <linux/config.h>
-
-#if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_MDA_CONSOLE)
-
-#define VT_BUF_HAVE_RW
-/*
- * These are only needed for supporting VGA or MDA text mode, which use little
- * endian byte ordering.
- * In other cases, we can optimize by using native byte ordering and
- * <linux/vt_buffer.h> has already done the right job for us.
- */
-
-extern inline void scr_writew(u16 val, volatile u16 *addr)
-{
- st_le16(addr, val);
-}
-
-extern inline u16 scr_readw(volatile const u16 *addr)
-{
- return ld_le16(addr);
-}
-
-#define VT_BUF_HAVE_MEMCPYW
-#define scr_memcpyw memcpy
-
-#endif /* !CONFIG_VGA_CONSOLE && !CONFIG_MDA_CONSOLE */
-
-extern unsigned long vgacon_remap_base;
-#define VGA_MAP_MEM(x) (x + vgacon_remap_base)
-#define vga_readb(x) (*(x))
-#define vga_writeb(x,y) (*(y) = (x))
-
-#endif
-#endif /* __KERNEL__ */
diff --git a/include/asm-ppc64/vga.h b/include/asm-ppc64/vga.h
deleted file mode 100644
--- a/include/asm-ppc64/vga.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * Access to VGA videoram
- *
- * (c) 1998 Martin Mares <mj@ucw.cz>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _LINUX_ASM_VGA_H_
-#define _LINUX_ASM_VGA_H_
-
-#include <asm/io.h>
-
-#include <linux/config.h>
-
-#if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_MDA_CONSOLE)
-
-#define VT_BUF_HAVE_RW
-/*
- * These are only needed for supporting VGA or MDA text mode, which use little
- * endian byte ordering.
- * In other cases, we can optimize by using native byte ordering and
- * <linux/vt_buffer.h> has already done the right job for us.
- */
-
-static inline void scr_writew(u16 val, volatile u16 *addr)
-{
- st_le16(addr, val);
-}
-
-static inline u16 scr_readw(volatile const u16 *addr)
-{
- return ld_le16(addr);
-}
-
-#define VT_BUF_HAVE_MEMCPYW
-#define scr_memcpyw memcpy
-
-#endif /* !CONFIG_VGA_CONSOLE && !CONFIG_MDA_CONSOLE */
-
-extern unsigned long vgacon_remap_base;
-#define VGA_MAP_MEM(x) ((unsigned long) ioremap((x), 0))
-
-#define vga_readb(x) (*(x))
-#define vga_writeb(x,y) (*(y) = (x))
-
-#endif
^ permalink raw reply
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox