* Re: [PATCH] powerpc: merged asm/cputable.h
From: Benjamin Herrenschmidt @ 2005-09-26 23:38 UTC (permalink / raw)
To: Kumar Gala; +Cc: michael, linuxppc-dev, Stephen Rothwell, linuxppc64-dev
In-Reply-To: <65BBD07F-B465-45E0-9422-9015D1FBF93A@freescale.com>
> At the end of the day we should have the same init path for
> everything. We have to deal with the fact that some processors are
> not going to have "real mode" to run in. Anything Book-E 32 or 64-
> bit is going to fall into this case.
I know, and real mode isn't necessarily useable on others, my point was,
there is this "pre-mmu-init" phase when we run into a kind of reduced
mmu environment but no need to use RELOC's or -mrelocatable. That is:
- on ppc64, real mode
- on CONFIG_6xx, memory mapped by BATs over first 16M or so
- on others, typically, bolted TLB entries during early asm
This "pre-init" phase has common characteristics, that is
- we can run code without reloc's as explained above
- we can't access much memory above kernel text/data. on ppc64, it
ranges from all memory (lucky) to the limit of the RMO on lpar which
tend to get smaller. In fact, pSeries might even lose real mode sooner
or later and get into a similar "bolted initial mapping" case.
This is when early_setup() is run on ppc64. This is when machine_init()
and MMU_init() are called on ppc32. Those do fundamentally the same
thing. Some pre-init, typically based on device-tree bits & pieces, and
choosing the "right" ppc_md. They could be merged to look like the ppc64
version. The main issue is that ppc32 does a bit too much there (like
finish_device_tree which should be done later like ppc64). There is bits
& pieces there that should be moved around a bit, including in platform
code (ppc_md.probe() should replace {pmac,chrp,...}_init() for example).
Ben.
^ permalink raw reply
* Re: [PATCH] powerpc: merged asm/cputable.h
From: Benjamin Herrenschmidt @ 2005-09-26 23:31 UTC (permalink / raw)
To: michael; +Cc: linuxppc64-dev, Stephen Rothwell, linuxppc-dev
In-Reply-To: <200509270905.29545.michael@ellerman.id.au>
> > There is a small issue here: You turn identify_cpu into C code. However,
> > on ppc32, this is called with the kernel not yet relocated (before
> > prom_init even !). Same with the feature fixup. On ppc32, in order to
> > run C code that early, it needs to be in -mrelocatable bits of code
> > (like prom_init) or use RELOC macros (ugh !).
>
> We could keep the bulk of the patch (turn cur_cpu_spec into a struct) but
> still do identify_cpu() in asm, although it would seem like a step backward.
We can do it in C in ppc32 if we use proper RELOC() macros, or do it in
an -mrelocatable piece of code like prom_init (but I'd like to avoid
that).
> Do people think it's "better" to have one unified asm implementation, or one
> in asm for ppc32 and one in C for ppc64?
We should only need one implementation for both I suppose.
Ben
^ permalink raw reply
* Re: [PATCH] powerpc: merged asm/cputable.h
From: Kumar Gala @ 2005-09-26 23:22 UTC (permalink / raw)
To: Benjamin Herrenschmidt
Cc: michael, linuxppc-dev, Stephen Rothwell, linuxppc64-dev
In-Reply-To: <1127774755.15882.104.camel@gaston>
On Sep 26, 2005, at 5:45 PM, Benjamin Herrenschmidt wrote:
> On Mon, 2005-09-26 at 11:57 +1000, Michael Ellerman wrote:
>
>
>> Here's a version of my patch updated to apply on top of the merge
>>
> tree.
>
>> It'll be a lot cleaner when ppc32 has a single cur_cpu_spec, as we'll
>> be able to remove a lot of the #ifdefs.
>>
>
> There is a small issue here: You turn identify_cpu into C code.
> However,
> on ppc32, this is called with the kernel not yet relocated (before
> prom_init even !). Same with the feature fixup. On ppc32, in order to
> run C code that early, it needs to be in -mrelocatable bits of code
> (like prom_init) or use RELOC macros (ugh !).
What's the pain in building cputable.c as -mrelocatable on ppc32 for
now?
> This puts some light on the fact that we do things quite differently
> here between ppc32 and ppc64. On ppc64, the call to identify CPU is
> done
> after kernel is relocated (after prom_init), and before early_setup,
> though the call to fixup the feature sections is done later, after the
> initial parsing of the flat device-tree, where we can "adjust" some
> features based on firmware properties.
>
> We might want to sync a bit what ppc32 and ppc64 do here, however,
> that
> will/would require some changes in the way we manipulate some MMU
> bits.
>
> On ppc32, we first create a temporary initial mapping, using BATs on
> 6xx, using other mecanisms on other CPUs, that covers kernel text &
> data
> (not much more). This could be "equivalent" of the ppc64 bit that runs
> in real mode. (Though we have to be careful there if we do something
> like unpacking the device-tree, that has to be done -after- final
> translation is turned on with full access to the linear mapping).
>
> Also, the ppc64 bits calls indentify_cpu from asm on the primary
> CPU at
> least. I don't think that is strictly necessary, at least not any
> more.
> It could be done instead at the beginning of early_setup.
At the end of the day we should have the same init path for
everything. We have to deal with the fact that some processors are
not going to have "real mode" to run in. Anything Book-E 32 or 64-
bit is going to fall into this case.
- kumar
^ permalink raw reply
* Re: [PATCH] powerpc: merged asm/cputable.h
From: Michael Ellerman @ 2005-09-26 23:05 UTC (permalink / raw)
To: linuxppc64-dev; +Cc: Stephen Rothwell, linuxppc-dev
In-Reply-To: <1127774755.15882.104.camel@gaston>
[-- Attachment #1: Type: text/plain, Size: 1226 bytes --]
On Tue, 27 Sep 2005 08:45, Benjamin Herrenschmidt wrote:
> On Mon, 2005-09-26 at 11:57 +1000, Michael Ellerman wrote:
> > Here's a version of my patch updated to apply on top of the merge tree.
> > It'll be a lot cleaner when ppc32 has a single cur_cpu_spec, as we'll
> > be able to remove a lot of the #ifdefs.
>
> There is a small issue here: You turn identify_cpu into C code. However,
> on ppc32, this is called with the kernel not yet relocated (before
> prom_init even !). Same with the feature fixup. On ppc32, in order to
> run C code that early, it needs to be in -mrelocatable bits of code
> (like prom_init) or use RELOC macros (ugh !).
We could keep the bulk of the patch (turn cur_cpu_spec into a struct) but
still do identify_cpu() in asm, although it would seem like a step backward.
Do people think it's "better" to have one unified asm implementation, or one
in asm for ppc32 and one in C for ppc64?
cheers
--
Michael Ellerman
IBM OzLabs
email: michael:ellerman.id.au
inmsg: mpe:jabber.org
wwweb: http://michael.ellerman.id.au
phone: +61 2 6212 1183 (tie line 70 21183)
We do not inherit the earth from our ancestors,
we borrow it from our children. - S.M.A.R.T Person
[-- Attachment #2: Type: application/pgp-signature, Size: 189 bytes --]
^ permalink raw reply
* [PATCH] Change #if CONFIG_6xx -> #if defined(CONFIG_6xx) in perfmon.c
From: Roland Dreier @ 2005-09-26 22:56 UTC (permalink / raw)
To: paulus, linuxppc-dev
This trivial change fixes the warning
arch/ppc/kernel/perfmon.c:48:7: warning: "CONFIG_6xx" is not defined
Signed-off-by: Roland Dreier <rolandd@cisco.com>
diff --git a/arch/ppc/kernel/perfmon.c b/arch/ppc/kernel/perfmon.c
--- a/arch/ppc/kernel/perfmon.c
+++ b/arch/ppc/kernel/perfmon.c
@@ -45,7 +45,7 @@ static void dummy_perf(struct pt_regs *r
mtpmr(PMRN_PMGC0, pmgc0);
}
-#elif CONFIG_6xx
+#elif defined (CONFIG_6xx)
/* Ensure exceptions are disabled */
static void dummy_perf(struct pt_regs *regs)
^ permalink raw reply
* [PATCH] Make phys_mem_access_prot() work with pfns instead of addresses
From: Roland Dreier @ 2005-09-26 22:45 UTC (permalink / raw)
To: akpm, benh; +Cc: linuxppc-dev, linux-kernel
Here's a patch that makes mmap64() work better on /dev/mem. On ppc,
we currently call phys_mem_access_prot() on the address being mmap'ed;
unfortunately calculating the address to pass in can overflow on
32-bit architectures. Fortunately, mmap_mem() already has the pfn, so
it's simple to get rid of the conversion and work directly with the pfn.
My interest comes from being able to access memory-mapped peripherals
on PowerPC 44x chips (which are 32-bit). The registers are typically
located at addresses above 4G, and it's nice to be able to just use
mmap64() from userspace to peek and poke at things.
I tested the patch on a PowerPC 440SPe system by successfully using
mmap64() on an address above 4G.
I only compile tested for ppc64. Also, I don't have access to a
system where Ben's original change helped performance. The changes
seem pretty safe to me but someone should check my work.
Thanks,
Roland
--
Change the phys_mem_access_prot() function to take a pfn instead of an
address. This allows mmap64() to work on /dev/mem for addresses above
4G on 32-bit architectures. We start with a pfn in mmap_mem(), so
there's no need to convert to an address; in fact, it's actively bad,
since the conversion can overflow when the address is above 4G.
Similarly fix the ppc32 page_is_ram() function to avoid a conversion
to an address by directly comparing to max_pfn. Working with max_pfn
instead of high_memory fixes page_is_ram() to give the right answer
for highmem pages.
Signed-off-by: Roland Dreier <rolandd@cisco.com>
diff --git a/arch/ppc/kernel/pci.c b/arch/ppc/kernel/pci.c
--- a/arch/ppc/kernel/pci.c
+++ b/arch/ppc/kernel/pci.c
@@ -1586,16 +1586,17 @@ static pgprot_t __pci_mmap_set_pgprot(st
* above routine
*/
pgprot_t pci_phys_mem_access_prot(struct file *file,
- unsigned long offset,
+ unsigned long pfn,
unsigned long size,
pgprot_t protection)
{
struct pci_dev *pdev = NULL;
struct resource *found = NULL;
unsigned long prot = pgprot_val(protection);
+ unsigned long offset = pfn << PAGE_SHIFT;
int i;
- if (page_is_ram(offset >> PAGE_SHIFT))
+ if (page_is_ram(pfn))
return prot;
prot |= _PAGE_NO_CACHE | _PAGE_GUARDED;
diff --git a/arch/ppc/mm/init.c b/arch/ppc/mm/init.c
--- a/arch/ppc/mm/init.c
+++ b/arch/ppc/mm/init.c
@@ -648,18 +648,16 @@ void update_mmu_cache(struct vm_area_str
*/
int page_is_ram(unsigned long pfn)
{
- unsigned long paddr = (pfn << PAGE_SHIFT);
-
- return paddr < __pa(high_memory);
+ return pfn < max_pfn;
}
-pgprot_t phys_mem_access_prot(struct file *file, unsigned long addr,
+pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
unsigned long size, pgprot_t vma_prot)
{
if (ppc_md.phys_mem_access_prot)
- return ppc_md.phys_mem_access_prot(file, addr, size, vma_prot);
+ return ppc_md.phys_mem_access_prot(file, pfn, size, vma_prot);
- if (!page_is_ram(addr >> PAGE_SHIFT))
+ if (!page_is_ram(pfn))
vma_prot = __pgprot(pgprot_val(vma_prot)
| _PAGE_GUARDED | _PAGE_NO_CACHE);
return vma_prot;
diff --git a/arch/ppc64/kernel/pci.c b/arch/ppc64/kernel/pci.c
--- a/arch/ppc64/kernel/pci.c
+++ b/arch/ppc64/kernel/pci.c
@@ -727,16 +727,17 @@ static pgprot_t __pci_mmap_set_pgprot(st
* above routine
*/
pgprot_t pci_phys_mem_access_prot(struct file *file,
- unsigned long offset,
+ unsigned long pfn,
unsigned long size,
pgprot_t protection)
{
struct pci_dev *pdev = NULL;
struct resource *found = NULL;
unsigned long prot = pgprot_val(protection);
+ unsigned long offset = pfn << PAGE_SHIFT;
int i;
- if (page_is_ram(offset >> PAGE_SHIFT))
+ if (page_is_ram(pfn))
return __pgprot(prot);
prot |= _PAGE_NO_CACHE | _PAGE_GUARDED;
diff --git a/arch/ppc64/mm/init.c b/arch/ppc64/mm/init.c
--- a/arch/ppc64/mm/init.c
+++ b/arch/ppc64/mm/init.c
@@ -856,13 +856,13 @@ void pgtable_cache_init(void)
}
}
-pgprot_t phys_mem_access_prot(struct file *file, unsigned long addr,
+pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
unsigned long size, pgprot_t vma_prot)
{
if (ppc_md.phys_mem_access_prot)
- return ppc_md.phys_mem_access_prot(file, addr, size, vma_prot);
+ return ppc_md.phys_mem_access_prot(file, pfn, size, vma_prot);
- if (!page_is_ram(addr >> PAGE_SHIFT))
+ if (!page_is_ram(pfn))
vma_prot = __pgprot(pgprot_val(vma_prot)
| _PAGE_GUARDED | _PAGE_NO_CACHE);
return vma_prot;
diff --git a/drivers/char/mem.c b/drivers/char/mem.c
--- a/drivers/char/mem.c
+++ b/drivers/char/mem.c
@@ -231,9 +231,7 @@ static ssize_t write_mem(struct file * f
static int mmap_mem(struct file * file, struct vm_area_struct * vma)
{
#if defined(__HAVE_PHYS_MEM_ACCESS_PROT)
- unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
-
- vma->vm_page_prot = phys_mem_access_prot(file, offset,
+ vma->vm_page_prot = phys_mem_access_prot(file, vma->vm_pgoff,
vma->vm_end - vma->vm_start,
vma->vm_page_prot);
#elif defined(pgprot_noncached)
diff --git a/drivers/video/fbmem.c b/drivers/video/fbmem.c
--- a/drivers/video/fbmem.c
+++ b/drivers/video/fbmem.c
@@ -918,7 +918,7 @@ fb_mmap(struct file *file, struct vm_are
}
#endif
#elif defined(__powerpc__)
- vma->vm_page_prot = phys_mem_access_prot(file, off,
+ vma->vm_page_prot = phys_mem_access_prot(file, off >> PAGE_SHIFT,
vma->vm_end - vma->vm_start,
vma->vm_page_prot);
#elif defined(__alpha__)
diff --git a/include/asm-ppc/machdep.h b/include/asm-ppc/machdep.h
--- a/include/asm-ppc/machdep.h
+++ b/include/asm-ppc/machdep.h
@@ -98,7 +98,7 @@ struct machdep_calls {
/* Get access protection for /dev/mem */
pgprot_t (*phys_mem_access_prot)(struct file *file,
- unsigned long offset,
+ unsigned long pfn,
unsigned long size,
pgprot_t vma_prot);
diff --git a/include/asm-ppc/pci.h b/include/asm-ppc/pci.h
--- a/include/asm-ppc/pci.h
+++ b/include/asm-ppc/pci.h
@@ -126,7 +126,7 @@ extern void pcibios_add_platform_entries
struct file;
extern pgprot_t pci_phys_mem_access_prot(struct file *file,
- unsigned long offset,
+ unsigned long pfn,
unsigned long size,
pgprot_t prot);
diff --git a/include/asm-ppc/pgtable.h b/include/asm-ppc/pgtable.h
--- a/include/asm-ppc/pgtable.h
+++ b/include/asm-ppc/pgtable.h
@@ -705,7 +705,7 @@ static inline void __ptep_set_access_fla
#define pgprot_noncached(prot) (__pgprot(pgprot_val(prot) | _PAGE_NO_CACHE | _PAGE_GUARDED))
struct file;
-extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long addr,
+extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
unsigned long size, pgprot_t vma_prot);
#define __HAVE_PHYS_MEM_ACCESS_PROT
diff --git a/include/asm-ppc64/machdep.h b/include/asm-ppc64/machdep.h
--- a/include/asm-ppc64/machdep.h
+++ b/include/asm-ppc64/machdep.h
@@ -130,7 +130,7 @@ struct machdep_calls {
/* Get access protection for /dev/mem */
pgprot_t (*phys_mem_access_prot)(struct file *file,
- unsigned long offset,
+ unsigned long pfn,
unsigned long size,
pgprot_t vma_prot);
diff --git a/include/asm-ppc64/pci.h b/include/asm-ppc64/pci.h
--- a/include/asm-ppc64/pci.h
+++ b/include/asm-ppc64/pci.h
@@ -168,7 +168,7 @@ extern void pcibios_add_platform_entries
struct file;
extern pgprot_t pci_phys_mem_access_prot(struct file *file,
- unsigned long offset,
+ unsigned long pfn,
unsigned long size,
pgprot_t prot);
diff --git a/include/asm-ppc64/pgtable.h b/include/asm-ppc64/pgtable.h
--- a/include/asm-ppc64/pgtable.h
+++ b/include/asm-ppc64/pgtable.h
@@ -471,7 +471,7 @@ static inline void __ptep_set_access_fla
#define pgprot_noncached(prot) (__pgprot(pgprot_val(prot) | _PAGE_NO_CACHE | _PAGE_GUARDED))
struct file;
-extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long addr,
+extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
unsigned long size, pgprot_t vma_prot);
#define __HAVE_PHYS_MEM_ACCESS_PROT
^ permalink raw reply
* Re: [PATCH] powerpc: merged asm/cputable.h
From: Benjamin Herrenschmidt @ 2005-09-26 22:45 UTC (permalink / raw)
To: michael; +Cc: linuxppc-dev, linuxppc64-dev, Stephen Rothwell
In-Reply-To: <200509261157.37514.michael@ellerman.id.au>
On Mon, 2005-09-26 at 11:57 +1000, Michael Ellerman wrote:
> Here's a version of my patch updated to apply on top of the merge tree.
> It'll be a lot cleaner when ppc32 has a single cur_cpu_spec, as we'll
> be able to remove a lot of the #ifdefs.
There is a small issue here: You turn identify_cpu into C code. However,
on ppc32, this is called with the kernel not yet relocated (before
prom_init even !). Same with the feature fixup. On ppc32, in order to
run C code that early, it needs to be in -mrelocatable bits of code
(like prom_init) or use RELOC macros (ugh !).
This puts some light on the fact that we do things quite differently
here between ppc32 and ppc64. On ppc64, the call to identify CPU is done
after kernel is relocated (after prom_init), and before early_setup,
though the call to fixup the feature sections is done later, after the
initial parsing of the flat device-tree, where we can "adjust" some
features based on firmware properties.
We might want to sync a bit what ppc32 and ppc64 do here, however, that
will/would require some changes in the way we manipulate some MMU bits.
On ppc32, we first create a temporary initial mapping, using BATs on
6xx, using other mecanisms on other CPUs, that covers kernel text & data
(not much more). This could be "equivalent" of the ppc64 bit that runs
in real mode. (Though we have to be careful there if we do something
like unpacking the device-tree, that has to be done -after- final
translation is turned on with full access to the linear mapping).
Also, the ppc64 bits calls indentify_cpu from asm on the primary CPU at
least. I don't think that is strictly necessary, at least not any more.
It could be done instead at the beginning of early_setup.
Ben.
^ permalink raw reply
* Hello-new comer ask a start question.
From: Jerry Zhou @ 2005-09-26 21:41 UTC (permalink / raw)
To: linuxppc-embedded
[-- Attachment #1: Type: text/plain, Size: 204 bytes --]
Dear all,
I am a new comer.
I have bring up a MPC850 board by vxWorks BSP, and I want to bring it up by
linux, would you please tell me how to start?
Appreciate for your help
Jerry Zhou
[-- Attachment #2: Type: text/html, Size: 2475 bytes --]
^ permalink raw reply
* [PATCH] Add support for XMON on AMCC 440GX
From: Tom Rini @ 2005-09-26 21:37 UTC (permalink / raw)
To: Matt Porter, Paul Mackerras; +Cc: linuxppc-embedded
Note: The hex address rather than define matches style in the rest of
the code.
Add support for XMON on the AMCC 440GX boards.
Signed-off-by: Cal Erickson <cerickson@mvista.com>
Signed-off-by: Tom Rini <trini@kernel.crashing.org>
--- a/arch/ppc/xmon/start.c 2003-12-30 17:41:00.000000000 -0800
+++ b/arch/ppc/xmon/new_start.c 2005-09-23 09:20:24.000000000 -0700
@@ -213,6 +213,12 @@
TXRDY = 0x20;
RXRDY = 1;
DLAB = 0x80;
+#elif defined(CONFIG_440GX)
+ sccd = (volatile unsigned char *)ioremap64(0x0000000140000200, 8);
+ sccc = (volatile unsigned char *)( sccd + 5 );
+ TXRDY = 0x20;
+ RXRDY = 1;
+ DLAB = 0x80;
#endif /* platform */
__sysrq_put_key_op('x', &sysrq_xmon_op);
--
Tom Rini
http://gate.crashing.org/~trini/
^ permalink raw reply
* Re: sys_shmat
From: Brad Boyer @ 2005-09-26 17:44 UTC (permalink / raw)
To: zhonglei; +Cc: linuxppc-dev
In-Reply-To: <200509261548.AA26280018@RCS-9000.COM>
On Mon, Sep 26, 2005 at 03:48:03PM +0800, zhonglei wrote:
> I get a pointer shramptr from sys_shmat(shid,0,SHM_R|SHM_W,&shramptr) to use share RAM in my driver.
> But when I assign a value into this pointer in my interrupt routine,
> the system shows: oops: kernel access of bad area!
> what's the problem?
The problem is that sys_shmat is the implementation of the shmat() system
call and is therefore only intended to attach shared memory to a normal
user-space process. The memory is attached to whatever process is listed
as current at the time of the call. This is obviously not what you wanted,
since you apparently want something that is useful from kernel-space.
Perhaps you should tell the list what you are trying to do from a more
conceptual view? No matter what you are trying to do, I think you are
misunderstanding the services that are available to a driver in the kernel.
The key question you need to answer is where you need to be able to
access this memory. In particular, do you need it in a user-space program?
Brad Boyer
flar@allandria.com
^ permalink raw reply
* Re: porting Linux on ppc7a
From: Mark A. Greer @ 2005-09-26 17:15 UTC (permalink / raw)
To: smiling_23; +Cc: linuxppc-embedded
In-Reply-To: <432FFE87.6020100@nerdshack.com>
On Tue, Sep 20, 2005 at 05:50:23PM +0530, smiling_23 wrote:
> Hi all,
> I am tryin to port Linux on ppc7a radstone board. I have seen
> two threads on porting linux on ppc7a, There
> he mentioned ppc7a board is similar to EV64260 board. I tried to get
> the data sheets of EV64620, i failed to found this
> board data sheets. If any one has this board data sheets , web link or
> any information please send the information to me.
> Thanks and regards,
> Venkata jagadish.p.
Before you go too far, did you look to see what already in the community
source? There is a port to the radstone ppc7d. I don't know but I
wouldn't be surprised if its pretty close to your ppc7a.
If you want docs on Marvell products like the ev64260, you need to sign an NDA
(last time I checked).
Mark
^ permalink raw reply
* [PATCH] powerpc: merge ipcbuf.h
From: Becky Bruce @ 2005-09-26 16:21 UTC (permalink / raw)
To: linuxppc64-dev, linuxppc-dev
powerpc: Merge ipcbuf.h
Merged ipcbuf.h into include/asm-powerpc. The type of a couple of
__unused fields in the ipc64_perm struct has been changed to long long
so we get a 64-bit quantity on both 32/64 ppcs. The pad field is now
called __pad1 on both platforms. The "seq" structure member is now an int,
so we get 32-bits on both platforms as well (previously, it was a long
on ppc32). The size of the structure on both platforms is the same as
it always was. Also, updated include/asm-ppc64/compat.h to match the
new structure definition.
Builds cleanly on several different 32/64-bit platforms with no new
warnings.
Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
Signed-off-by: Kumar Gala <kumar.gala@freescale.com>
---
commit 62cba170a9d2629791c9e9ceebb9c679f81fb3fb
tree 848d43a4a62930af1ed7181088d2b428d4b40b2d
parent 76b1ba19ac14976b8cd288180bb939f429a70820
author Becky Bruce <becky.bruce@freescale.com> Mon, 26 Sep 2005 11:17:55 -0500
committer Becky Bruce <becky.bruce@freescale.com> Mon, 26 Sep 2005 11:17:55 -0500
include/asm-powerpc/ipcbuf.h | 28 ++++++++++++++++++++++++++++
include/asm-ppc/ipcbuf.h | 29 -----------------------------
include/asm-ppc64/compat.h | 6 +++---
include/asm-ppc64/ipcbuf.h | 28 ----------------------------
4 files changed, 31 insertions(+), 60 deletions(-)
diff --git a/include/asm-powerpc/ipcbuf.h b/include/asm-powerpc/ipcbuf.h
new file mode 100644
--- /dev/null
+++ b/include/asm-powerpc/ipcbuf.h
@@ -0,0 +1,28 @@
+#ifndef _ASM_POWERPC_IPCBUF_H
+#define _ASM_POWERPC_IPCBUF_H
+
+/*
+ * The ipc64_perm structure for the PPC is identical to kern_ipc_perm
+ * as we have always had 32-bit UIDs and GIDs in the kernel.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+struct ipc64_perm
+{
+ __kernel_key_t key;
+ __kernel_uid_t uid;
+ __kernel_gid_t gid;
+ __kernel_uid_t cuid;
+ __kernel_gid_t cgid;
+ __kernel_mode_t mode;
+ unsigned int seq;
+ unsigned int __pad1;
+ unsigned long long __unused1;
+ unsigned long long __unused2;
+};
+
+#endif /* _ASM_POWERPC_IPCBUF_H */
diff --git a/include/asm-ppc/ipcbuf.h b/include/asm-ppc/ipcbuf.h
deleted file mode 100644
--- a/include/asm-ppc/ipcbuf.h
+++ /dev/null
@@ -1,29 +0,0 @@
-#ifndef __PPC_IPCBUF_H__
-#define __PPC_IPCBUF_H__
-
-/*
- * The ipc64_perm structure for PPC architecture.
- * Note extra padding because this structure is passed back and forth
- * between kernel and user space.
- *
- * Pad space is left for:
- * - 1 32-bit value to fill up for 8-byte alignment
- * - 2 miscellaneous 64-bit values (so that this structure matches
- * PPC64 ipc64_perm)
- */
-
-struct ipc64_perm
-{
- __kernel_key_t key;
- __kernel_uid_t uid;
- __kernel_gid_t gid;
- __kernel_uid_t cuid;
- __kernel_gid_t cgid;
- __kernel_mode_t mode;
- unsigned long seq;
- unsigned int __pad2;
- unsigned long long __unused1;
- unsigned long long __unused2;
-};
-
-#endif /* __PPC_IPCBUF_H__ */
diff --git a/include/asm-ppc64/compat.h b/include/asm-ppc64/compat.h
--- a/include/asm-ppc64/compat.h
+++ b/include/asm-ppc64/compat.h
@@ -152,9 +152,9 @@ struct compat_ipc64_perm {
__compat_gid_t cgid;
compat_mode_t mode;
unsigned int seq;
- unsigned int __pad2;
- unsigned long __unused1; /* yes they really are 64bit pads */
- unsigned long __unused2;
+ unsigned int __pad1;
+ unsigned long long __unused1; /* yes they really are 64bit pads */
+ unsigned long long __unused2;
};
struct compat_semid64_ds {
diff --git a/include/asm-ppc64/ipcbuf.h b/include/asm-ppc64/ipcbuf.h
deleted file mode 100644
--- a/include/asm-ppc64/ipcbuf.h
+++ /dev/null
@@ -1,28 +0,0 @@
-#ifndef __PPC64_IPCBUF_H__
-#define __PPC64_IPCBUF_H__
-
-/*
- * The ipc64_perm structure for the PPC is identical to kern_ipc_perm
- * as we have always had 32-bit UIDs and GIDs in the kernel.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-struct ipc64_perm
-{
- __kernel_key_t key;
- __kernel_uid_t uid;
- __kernel_gid_t gid;
- __kernel_uid_t cuid;
- __kernel_gid_t cgid;
- __kernel_mode_t mode;
- unsigned int seq;
- unsigned int __pad1;
- unsigned long __unused1;
- unsigned long __unused2;
-};
-
-#endif /* __PPC64_IPCBUF_H__ */
^ permalink raw reply
* Re: [PATCH] ppc32: make sure we have an L3 before touch its control register
From: Kumar Gala @ 2005-09-26 16:04 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev
In-Reply-To: <1127599811.27674.47.camel@gaston>
On Sep 24, 2005, at 5:10 PM, Benjamin Herrenschmidt wrote:
> On Thu, 2005-09-22 at 14:51 -0500, Kumar Gala wrote:
>
>> Ben,
>>
>> Can you take a look at this. I think its pretty straight forward and
>>
> if
>
>> your ok with it please forward on to linus.
>>
>
> We usually haven't dong the fixup of cpu features yet at the point
> setup() is run, thus your change will have no effect. You need to
> actually go look at the CPU feature bits. (You can look a bit below in
> that same code how it does for CPU_FTR_L3_DISABLE_NAP and
> CCPU_FTR_CAN_NAP.
Dope, you're right. I notice that we apparent do this for BTIC and
DPM in this function though?
> Also, it's 745x, those CPUs so far always existed in their 744x
> version
> without L3 and no way to recongnize them via PVR afaik (until before
> 7447A). I would expect L3CR to just return 0. Is this not the case on
> 7447/7448 ? If yes, then there is no need to change the code...
Need to check. I was lead to believe on 7448 they may have gotten
ride of L3CR and thus my patch. I do some digging internally to see
what's happening with L3CR on 7448.
>
> Ben.
>
>
>> - kumar
>>
>> --
>>
>> Some variants of 745x may not actually have the L3CR register. Since
>> we mark which variants of 745x have L3CRs in the cputable we can
>> use that information to ensure that the mfspr L3CR will not cause
>> an exception in the processors that don't have the register.
>>
>> Signed-off-by: Kumar K. Gala <kumar.gala@freescale.com>
>>
>> ---
>> commit f706b6046f1fee29bdf3081dd783f7e482012165
>> tree 6d42ee61458ec94ac7d4567e3f0383dd1e47a537
>> parent d8ac10639b6a1ed900efbee38c18baaca31e64dc
>> author Kumar K. Gala <kumar.gala@freescale.com> Thu, 22 Sep 2005
>>
> 14:47:52 -0500
>
>> committer Kumar K. Gala <kumar.gala@freescale.com> Thu, 22 Sep 2005
>>
> 14:47:52 -0500
>
>>
>> arch/ppc/kernel/cpu_setup_6xx.S | 2 ++
>> 1 files changed, 2 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/ppc/kernel/cpu_setup_6xx.S
>>
> b/arch/ppc/kernel/cpu_setup_6xx.S
>
>> --- a/arch/ppc/kernel/cpu_setup_6xx.S
>> +++ b/arch/ppc/kernel/cpu_setup_6xx.S
>> @@ -212,9 +212,11 @@ setup_745x_specifics:
>> * the firmware. If any, we disable NAP capability as
>> * it's known to be bogus on rev 2.1 and earlier
>> */
>> +BEGIN_FTR_SECTION
>> mfspr r11,SPRN_L3CR
>> andis. r11,r11,L3CR_L3E@h
>> beq 1f
>> +END_FTR_SECTION_IFSET(CPU_FTR_L3CR)
>> lwz r6,CPU_SPEC_FEATURES(r5)
>> andi. r0,r6,CPU_FTR_L3_DISABLE_NAP
>> beq 1f
>
^ permalink raw reply
* Re: Slow read performance of NAND flash on PPC 405EP
From: Conn Clark @ 2005-09-26 15:23 UTC (permalink / raw)
To: Andy Hawkins; +Cc: linuxppc-embedded
In-Reply-To: <006101c5c27a$ca9c3280$153335bf@cabletime.com>
Andy Hawkins wrote:
> Hi,
>
> Thanks for the reply.
>
>
>>It would be nice if you would break out the fields in the
>>PB2AP control
>>word. This is what I came up with.
>>
>>BME = 1, burst mode enabled
>>FWT = 2, 3 wait states
>>BWT = 4, 5 wait states
>>CSN = 0, 0 clock cycles before CS asserted
>>OEN = 1, 1 clock cycle before the PerOE is asserted
>>WBN = 1, 1 clock cycle delay until the first PerW line
>>assertion after CS
>>WBF = 1, 1 clock cycle delay
>>TH = 2, 2 clock cycles in between each burst
>>RE = 0, PerREADY line disabled
>>SOR = 1, no effect
>>BME = 0
>
>
> That matches how we decoded it, yes.
>
>
>>So you are reading things in burst mode. I have no experience doing
>>things in burst mode so I'm not going to be much help. I
>>would look at
>>your timing diagrams again. Try changing the TH to 1 or 0 and
>>see what
>>happens.
>
>
> We did try switching away from burst mode. However, as the flash is a serial
> read device with only one address, then each 'burst' transaction is only for
> a single ready anyway. We did try configuring without burst mode enabled,
> and it made little difference.
>
> Are the figures we're seeing particularly slow, or are our expectations
> unrealistic?
>
> Any other ideas?
>
> Thanks again
>
> Andy
>
Without looking at the data sheet for your flash device I find it a
little strange that the first wait state is 3 and the subsequent read
wait states are 5 (i.e. 3,5,5,5,5... ) . Usually burst sequential
devices have a long first wait state period followed by shorter ones
(i.e. 5,3,3,3,3..... ). Are you sure you have this correct?
Unfortunately I don't have time to calculate your actual data rate.
Other than reducing the Transfer Hold setting down from 2 to 1 or 0 I
don't have any other ideas. In the end you get what you can get and
thats it. If you have everything correct thats about all your going to
get unless you start pushing timing beyond what they are rated for. I'm
sure you don't want to do that.
Good Luck
-- Conn
*****************************************************************
Blessed be the heretic, for he causes some to think and unites
the rest against him.
*****************************************************************
Conn Clark
Engineering Assistant clark@esteem.com
Electronic Systems Technology Inc. www.esteem.com
Stock Ticker Symbol ELST
^ permalink raw reply
* [PATCH] update xmon help text for ppc
From: Olaf Hering @ 2005-09-26 13:05 UTC (permalink / raw)
To: Andrew Morton, Paul Mackeras, linuxppc-dev
mention a few more commands in xmon.
System.map processing was replaced with kallsyms.
Signed-off-by: Olaf Hering <olh@suse.de>
arch/ppc/xmon/xmon.c | 9 +++++++--
1 files changed, 7 insertions(+), 2 deletions(-)
Index: linux-2.6.13.orig/arch/ppc/xmon/xmon.c
===================================================================
--- linux-2.6.13.orig.orig/arch/ppc/xmon/xmon.c
+++ linux-2.6.13.orig/arch/ppc/xmon/xmon.c
@@ -148,9 +148,14 @@ Commands:\n\
r print registers\n\
S print special registers\n\
t print backtrace\n\
- la lookup address in system.map\n\
- ls lookup symbol in system.map\n\
+ la lookup address\n\
+ ls lookup symbol\n\
+ C checksum\n\
+ P call function with arguments\n\
+ T print time\n\
x exit monitor\n\
+ zr reboot\n\
+ zh halt\n\
";
static int xmon_trace[NR_CPUS];
--
short story of a lazy sysadmin:
alias appserv=wotan
^ permalink raw reply
* Re: PATCH powerpc Merge asm-ppc*/rwsem.h
From: David Howells @ 2005-09-26 11:38 UTC (permalink / raw)
To: Paul Mackerras; +Cc: David Howells, linuxppc-dev, linuxppc64-dev
In-Reply-To: <17204.41449.162199.476757@cargo.ozlabs.ibm.com>
Paul Mackerras <paulus@samba.org> wrote:
>
> > rwsems on ppc64 should really be using a 64-bit counter, not a 32-bit
> > counter, otherwise you limit the maximum number of processes to 32K-ish.
> >
> > The counter should be "signed long" really.
>
> It has long annoyed me that we waste half the bits in the rwsem
> counter, just because you assume a lowest-common-denominator set of
> atomic ops. IIRC your implementation replaced the earlier ppc
> implementation which had a 32-bit counter and didn't have the 32k
> process limit.
And also didn't work, at least not on i386.
> I'd have to study it in more detail, but I strongly suspect that with
> an atomic operation that did something like
>
> *p = max(*p, limit) + inc
There is no requirement for an arch to use the XADD-based algorithm for doing
this - that's optimised for use with the i386/x86_64 XADD instruction. That
can be emulated by cmpxchg or load-locked/store-conditional type constructs
like MIPS, Alpha and ppc have.
> atomically (or alternatively a min), we could increase the limit to at
> least 1G processes with a 32-bit counter, without needing to change
> your common slow-path implementation.
I think you'd probably need a different slow-path for what you want. My XADD
optimised slow patch assumes that certain values represent certain states, and
if you're using different values, then it won't necessarily work. This is why
the thing is contingent on CONFIG_RWSEM_XCHGADD_ALGORITHM.
> Such an atomic op is easy to implement with load-and-reserve /
> store-conditional instructions. Look at __sem_update_count in
> arch/ppc64/kernel/semaphore.c for an example.
So that does (I think):
do {
int old_count = load_reserve(&sem->count);
int tmp = old_count >> 31; // not sure about this: 31 or 1?
tmp = old_count & ~tmp;
tmp = tmp + incr;
} while (!conditionally_assign(&sem->count, tmp));
PPC asm makes my head hurt; in particular the description of the SRAWI
instruction I've got is a delight to behold, and is inconsistent with the
description of the SRAW instruction:-/
I'm guessing it does a shift by 31 to leave tmp filled with copies of bit 0
(the sign bit) of old_count. The manual suggests the shift is 32-N (or 1 in
this case) which would seem odd.
I see how it works, then. What's "limit" in this formula:
> *p = max(*p, limit) + inc
Is it the maximum number of processes that may hold readlocks? Or maybe the
negated quantity thereof.
It's hard to see immediately how this will work. The counter has to represent
several things:
(1) The number of active readers (max N) or the number of active writers (max
1).
(2) Whether or not there is potential contention.
I do this with my XADD algorithm by splitting the word into two halves:
MSH = #active_writers + #failed_writers + #sleepers
LSH = #active_readers + #active_writers + #failed_contenders
Basically, the counter is a lock additional to the spinlock.
Perhaps you could do something like this:
COUNT MEANING
======================= ==========================================
0 Not in use
0x00000001 - 0x7fffffff N readers
0x80000000 last active reader or writer done, contention
0x80000001 - 0xffffffff N active readers or writers, contention
So up_read() and up_write() would decrement the count. If the result reaches
0x80000000 then you have to perform contention resolution.
down_read() would increment the count if >= 0, or attempt to sleep otherwise.
down_write() would just set the sign bit of the count and sleep if != 0, or set
the count to 0x80000001 and return.
We could also divide the space in two, and use the second most significant bit
(0x40000000) to record the fact that there are sleeping contenders or to record
which type of lock is actually active.
However, I think there's a problem with doing that, and that is:
COUNT PROCESS 0 PROCESS 1
======== ====================== ================================
00000000
down_read()
00000001
-->down_write()
lwarx
stwcx [set sign bit]
80000001
-->down_write_slow()
-->up_read()
lwarx
stwcx [dec]
80000000
-->up_read_slow()
-->lock sem->wait_lock
<--lock sem->wait_lock
-->lock sem->wait_lock
count indicated contention
but nothing on sem->wait_list
- do we leave the count unaltered?
- do we clear the count?
- do we set the count to 0x80000001?
If we leave the count set to 0x80000000, then the down_write_slow() when it
runs won't be able to tell whether it got sem->wait_lock before or after
down_read_slow() did. In one case it should go to sleep and in the other it
should claim the lock.
If we set the count to 0x80000001, then the case where _two_ CPUs are
contending with the releaser may _both_ think they have the lock, and in any
case can't tell the difference between that and a sleeping process just having
been woken up and given a writelock.
If we clear the count, then other processes may be able to queue jump (which
isn't necessarily a problem since spinlocks aren't fair anyway, though they
could be made so). down_write_slow() would have to attempt to take the lock
again, though this time it would already have the spinlock. But what might
happen is that:
COUNT PROCESS 0 PROCESS 1 PROCESS 2
======== ====================== =============== ===============
80000000
-->lock sem->wait_lock
count indicated contention
but nothing on sem->wait_list
- do we clear the count?
00000000
down_write()
80000001
unlock sem->wait_lock
<--up_read_slow()
<--up_read()
<--lock sem->wait_lock
lwarx
stwcx [set sign bit]
80000001
-->up_write()
lwarx
stwcx [dec]
80000000
-->up_write_slow()
-->lock sem->wait_lock
list_add_tail()
unlock sem->wait_lock
sleep
<--lock sem->wait_lock
dequeue process 1
set count
80000001
unlock sem->wait_lock
<--up_write_slow()
<--up_write()
wake
<--up_write_slow()
<--up_write()
Ummm... that does seem to work. I think their may be a multi-process race in
there somewhere, but I can't work it out if there is; just as long as
up_write() always does contention resolution.
The down side of this is that you always have to get the spinlock in up_write,
unlike in the XADD implementation where the counter includes a contention
counter.
I think downgrade_write() should simply be a matter of: whilst holding the
spinlock, set the counter to the number of outstanding reads, and only set the
sign bit if there's a sleeping writer left at the front of the queue.
Should interruptible rwsems arrive, then I think just dequeuing the aborted
down op should be enough. Leave the contention counter with the sign bit set as
it'll sort itself out later.
David
^ permalink raw reply
* Init ATI M6-C16h with BIOS for PPC 440GX
From: Roberto Pavon Sierra @ 2005-09-26 11:12 UTC (permalink / raw)
To: linuxppc-embedded
Hi,
can someone help me?
I try to initialize a ATI (M6-C16h) video card with BIOS for a PPC 440GX.
The BIOS is in a ST(M25P10-A) serial flash memory. After the reset i get few
Initiation data. I work with U-boot and linux kernel 2.6.12.
How can i initialize this video card? or read the data from BIOS correct?
Best regards,
Roberto Pavón
^ permalink raw reply
* sys_shmat
From: zhonglei @ 2005-09-26 7:48 UTC (permalink / raw)
To: linuxppc-dev
hi:
I get a pointer shramptr from sys_shmat(shid,0,SHM_R|SHM_W,&shramptr) to use share RAM in my driver.
But when I assign a value into this pointer in my interrupt routine,
the system shows: oops: kernel access of bad area!
what's the problem?
thanks
zhonglei
^ permalink raw reply
* [PATCH] ppc: fix stupid thinko in oprofile fix
From: Benjamin Herrenschmidt @ 2005-09-26 3:42 UTC (permalink / raw)
To: Andrew Morton; +Cc: linuxppc-dev list
I did something stupid in my oprofile fix, here's the obvious fix:
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Index: linux-work/arch/ppc/kernel/perfmon.c
===================================================================
--- linux-work.orig/arch/ppc/kernel/perfmon.c 2005-09-26 09:53:19.000000000 +1000
+++ linux-work/arch/ppc/kernel/perfmon.c 2005-09-26 13:40:16.000000000 +1000
@@ -45,9 +45,8 @@
mtpmr(PMRN_PMGC0, pmgc0);
}
-#elif CONFIG_6xx
+#elif defined(CONFIG_6xx)
/* Ensure exceptions are disabled */
-
static void dummy_perf(struct pt_regs *regs)
{
unsigned int mmcr0 = mfspr(SPRN_MMCR0);
^ permalink raw reply
* Re: [PATCH] powerpc: merged asm/cputable.h
From: Michael Ellerman @ 2005-09-26 1:57 UTC (permalink / raw)
To: linuxppc64-dev; +Cc: Stephen Rothwell, linuxppc-dev
In-Reply-To: <BCC97EBE-6171-4FF9-A696-B98B11046391@freescale.com>
On Sun, 25 Sep 2005 01:35, Kumar Gala wrote:
> On Sep 23, 2005, at 7:48 PM, Stephen Rothwell wrote:
> > On Sat, 24 Sep 2005 10:04:12 +1000 Paul Mackerras
> >
> > <paulus@samba.org> wrote:
> >> Kumar Gala writes:
> >>> +#ifdef __powerpc64__
> >>> +extern struct cpu_spec *cur_cpu_spec;
> >>> +#else /* __powerpc64__ */
> >>> +extern struct cpu_spec *cur_cpu_spec[];
> >>> +#endif /* __powerpc64__ */
> >>
> >> I would like to see this unified - it makes no sense for them to be
> >> different. We are unlikely to support asymmetric multiprocessing any
> >> time soon, so let's go with the single cur_cpu_spec pointer (a la
> >> ppc64).
> >
> > Michael Ellerman also has a patch that makes this a struct (i.e. not a
> > pointer) which allows us to mark the array of cpuspec's that we test
> > against at boot time as __init. Maybe he could do the ppc32 single
> > cpu_spec as part of that.
>
> I'm all for unifying this as well. If Michael can post his patch
> I'll look at fixing up this issue. Let's merge the current patch and
> follow it up with an update that includes this fix and Michael's work.
Here's a version of my patch updated to apply on top of the merge tree.
It'll be a lot cleaner when ppc32 has a single cur_cpu_spec, as we'll
be able to remove a lot of the #ifdefs.
cheers
Signed-off-by: Michael Ellerman <michael@ellerman.id.au>
---
arch/powerpc/oprofile/common.c | 8 +++----
arch/powerpc/oprofile/op_model_power4.c | 6 ++---
arch/ppc64/kernel/asm-offsets.c | 4 ---
arch/ppc64/kernel/cputable.c | 33 ++++++++++++++++++++++++++------
arch/ppc64/kernel/head.S | 11 ----------
arch/ppc64/kernel/idle_power4.S | 5 +---
arch/ppc64/kernel/misc.S | 32 -------------------------------
arch/ppc64/kernel/prom.c | 12 +++++------
arch/ppc64/kernel/setup.c | 8 +++----
arch/ppc64/kernel/sysfs.c | 32 +++++++++++++++----------------
include/asm-powerpc/cputable.h | 24 +++++++++++++++++------
include/asm-powerpc/elf.h | 2 -
Index: kexec/include/asm-powerpc/cputable.h
===================================================================
--- kexec.orig/include/asm-powerpc/cputable.h
+++ kexec/include/asm-powerpc/cputable.h
@@ -26,7 +26,7 @@ struct cpu_spec;
struct op_powerpc_model;
#ifdef __powerpc64__
-typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec);
+typedef void (*cpu_setup_t)(struct cpu_spec* spec);
#else /* __powerpc64__ */
typedef void (*cpu_setup_t)(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
#endif /* __powerpc64__ */
@@ -61,10 +61,10 @@ struct cpu_spec {
#endif /* __powerpc64__ */
};
-extern struct cpu_spec cpu_specs[];
+extern void identify_cpu(void);
#ifdef __powerpc64__
-extern struct cpu_spec *cur_cpu_spec;
+extern struct cpu_spec cur_cpu_spec;
#else /* __powerpc64__ */
extern struct cpu_spec *cur_cpu_spec[];
#endif /* __powerpc64__ */
@@ -398,14 +398,26 @@ static inline int cpu_has_feature(unsign
{
return (CPU_FTRS_ALWAYS & feature) ||
(CPU_FTRS_POSSIBLE
-#ifndef __powerpc64__
- & cur_cpu_spec[0]->cpu_features
+#ifdef __powerpc64__
+ & cur_cpu_spec.cpu_features
#else
- & cur_cpu_spec->cpu_features
+ & cur_cpu_spec[0].cpu_features
#endif
& feature);
}
+#ifdef __powerpc64__
+static inline void cpu_set_feature(unsigned long feature)
+{
+ cur_cpu_spec.cpu_features |= feature;
+}
+
+static inline void cpu_unset_feature(unsigned long feature)
+{
+ cur_cpu_spec.cpu_features &= ~feature;
+}
+#endif
+
#endif /* !__ASSEMBLY__ */
#ifdef __ASSEMBLY__
Index: kexec/arch/ppc64/kernel/cputable.c
===================================================================
--- kexec.orig/arch/ppc64/kernel/cputable.c
+++ kexec/arch/ppc64/kernel/cputable.c
@@ -22,7 +22,7 @@
#include <asm/oprofile_impl.h>
#include <asm/cputable.h>
-struct cpu_spec* cur_cpu_spec = NULL;
+struct cpu_spec cur_cpu_spec;
EXPORT_SYMBOL(cur_cpu_spec);
/* NOTE:
@@ -32,12 +32,12 @@ EXPORT_SYMBOL(cur_cpu_spec);
* part of the cputable though. That has to be fixed for both ppc32
* and ppc64
*/
-extern void __setup_cpu_power3(unsigned long offset, struct cpu_spec* spec);
-extern void __setup_cpu_power4(unsigned long offset, struct cpu_spec* spec);
-extern void __setup_cpu_ppc970(unsigned long offset, struct cpu_spec* spec);
-extern void __setup_cpu_be(unsigned long offset, struct cpu_spec* spec);
+extern void __setup_cpu_power3(struct cpu_spec* spec);
+extern void __setup_cpu_power4(struct cpu_spec* spec);
+extern void __setup_cpu_ppc970(struct cpu_spec* spec);
+extern void __setup_cpu_be(struct cpu_spec* spec);
-struct cpu_spec cpu_specs[] = {
+static __initdata struct cpu_spec cpu_specs[] = {
{ /* Power3 */
.pvr_mask = 0xffff0000,
.pvr_value = 0x00400000,
@@ -258,3 +258,24 @@ struct cpu_spec cpu_specs[] = {
.cpu_setup = __setup_cpu_power4,
}
};
+
+void __init identify_cpu(void)
+{
+ unsigned int pvr, mask, value;
+ int i;
+
+ pvr = mfspr(SPRN_PVR);
+
+ /* We rely on the default match at the end of the cpu_spec array */
+ for (i = 0; ; i++) {
+ mask = cpu_specs[i].pvr_mask;
+ value = cpu_specs[i].pvr_value;
+
+ if ((pvr & mask) == value)
+ break;
+ }
+
+ cur_cpu_spec = cpu_specs[i];
+
+ cur_cpu_spec.cpu_setup(&cur_cpu_spec);
+}
Index: kexec/arch/ppc64/kernel/asm-offsets.c
===================================================================
--- kexec.orig/arch/ppc64/kernel/asm-offsets.c
+++ kexec/arch/ppc64/kernel/asm-offsets.c
@@ -165,11 +165,7 @@ int main(void)
DEFINE(CLONE_UNTRACED, CLONE_UNTRACED);
/* About the CPU features table */
- DEFINE(CPU_SPEC_ENTRY_SIZE, sizeof(struct cpu_spec));
- DEFINE(CPU_SPEC_PVR_MASK, offsetof(struct cpu_spec, pvr_mask));
- DEFINE(CPU_SPEC_PVR_VALUE, offsetof(struct cpu_spec, pvr_value));
DEFINE(CPU_SPEC_FEATURES, offsetof(struct cpu_spec, cpu_features));
- DEFINE(CPU_SPEC_SETUP, offsetof(struct cpu_spec, cpu_setup));
/* systemcfg offsets for use by vdso */
DEFINE(CFG_TB_ORIG_STAMP, offsetof(struct systemcfg, tb_orig_stamp));
Index: kexec/arch/ppc64/kernel/head.S
===================================================================
--- kexec.orig/arch/ppc64/kernel/head.S
+++ kexec/arch/ppc64/kernel/head.S
@@ -1354,15 +1354,11 @@ _STATIC(__start_initialization_iSeries)
li r0,0
stdu r0,-STACK_FRAME_OVERHEAD(r1)
- LOADADDR(r3,cpu_specs)
- LOADADDR(r4,cur_cpu_spec)
- li r5,0
- bl .identify_cpu
-
LOADADDR(r2,__toc_start)
addi r2,r2,0x4000
addi r2,r2,0x4000
+ bl .identify_cpu
bl .iSeries_early_setup
/* relocation is on at this point */
@@ -1771,11 +1767,6 @@ _STATIC(start_here_multiplatform)
addi r2,r2,0x4000
sub r2,r2,r26
- LOADADDR(r3,cpu_specs)
- sub r3,r3,r26
- LOADADDR(r4,cur_cpu_spec)
- sub r4,r4,r26
- mr r5,r26
bl .identify_cpu
/* Save some low level config HIDs of CPU0 to be copied to
Index: kexec/arch/ppc64/kernel/misc.S
===================================================================
--- kexec.orig/arch/ppc64/kernel/misc.S
+++ kexec/arch/ppc64/kernel/misc.S
@@ -508,35 +508,6 @@ _GLOBAL(cvt_df)
blr
/*
- * identify_cpu and calls setup_cpu
- * In: r3 = base of the cpu_specs array
- * r4 = address of cur_cpu_spec
- * r5 = relocation offset
- */
-_GLOBAL(identify_cpu)
- mfpvr r7
-1:
- lwz r8,CPU_SPEC_PVR_MASK(r3)
- and r8,r8,r7
- lwz r9,CPU_SPEC_PVR_VALUE(r3)
- cmplw 0,r9,r8
- beq 1f
- addi r3,r3,CPU_SPEC_ENTRY_SIZE
- b 1b
-1:
- add r0,r3,r5
- std r0,0(r4)
- ld r4,CPU_SPEC_SETUP(r3)
- sub r4,r4,r5
- ld r4,0(r4)
- sub r4,r4,r5
- mtctr r4
- /* Calling convention for cpu setup is r3=offset, r4=cur_cpu_spec */
- mr r4,r3
- mr r3,r5
- bctr
-
-/*
* do_cpu_ftr_fixups - goes through the list of CPU feature fixups
* and writes nop's over sections of code that don't apply for this cpu.
* r3 = data offset (not changed)
@@ -545,9 +516,8 @@ _GLOBAL(do_cpu_ftr_fixups)
/* Get CPU 0 features */
LOADADDR(r6,cur_cpu_spec)
sub r6,r6,r3
- ld r4,0(r6)
+ ld r4,CPU_SPEC_FEATURES(r6)
sub r4,r4,r3
- ld r4,CPU_SPEC_FEATURES(r4)
/* Get the fixup table */
LOADADDR(r6,__start___ftr_fixup)
sub r6,r6,r3
Index: kexec/arch/ppc64/kernel/idle_power4.S
===================================================================
--- kexec.orig/arch/ppc64/kernel/idle_power4.S
+++ kexec/arch/ppc64/kernel/idle_power4.S
@@ -38,9 +38,8 @@ END_FTR_SECTION_IFCLR(CPU_FTR_CAN_NAP)
/* We must dynamically check for the NAP feature as it
* can be cleared by CPU init after the fixups are done
*/
- LOADBASE(r3,cur_cpu_spec)
- ld r4,cur_cpu_spec@l(r3)
- ld r4,CPU_SPEC_FEATURES(r4)
+ LOADADDR(r3,cur_cpu_spec)
+ ld r4,CPU_SPEC_FEATURES(r3)
andi. r0,r4,CPU_FTR_CAN_NAP
beqlr
/* Now check if user or arch enabled NAP mode */
Index: kexec/arch/ppc64/kernel/prom.c
===================================================================
--- kexec.orig/arch/ppc64/kernel/prom.c
+++ kexec/arch/ppc64/kernel/prom.c
@@ -1032,15 +1032,15 @@ static int __init early_init_dt_scan_cpu
/* Check if we have a VMX and eventually update CPU features */
prop = (u32 *)get_flat_dt_prop(node, "ibm,vmx", NULL);
if (prop && (*prop) > 0) {
- cur_cpu_spec->cpu_features |= CPU_FTR_ALTIVEC;
- cur_cpu_spec->cpu_user_features |= PPC_FEATURE_HAS_ALTIVEC;
+ cpu_set_feature(CPU_FTR_ALTIVEC);
+ cpu_set_feature(PPC_FEATURE_HAS_ALTIVEC);
}
/* Same goes for Apple's "altivec" property */
prop = (u32 *)get_flat_dt_prop(node, "altivec", NULL);
if (prop) {
- cur_cpu_spec->cpu_features |= CPU_FTR_ALTIVEC;
- cur_cpu_spec->cpu_user_features |= PPC_FEATURE_HAS_ALTIVEC;
+ cpu_set_feature(CPU_FTR_ALTIVEC);
+ cpu_set_feature(PPC_FEATURE_HAS_ALTIVEC);
}
#endif /* CONFIG_ALTIVEC */
@@ -1051,9 +1051,9 @@ static int __init early_init_dt_scan_cpu
*/
prop = (u32 *)get_flat_dt_prop(node, "ibm,ppc-interrupt-server#s",
&size);
- cur_cpu_spec->cpu_features &= ~CPU_FTR_SMT;
+ cpu_unset_feature(CPU_FTR_SMT);
if (prop && ((size / sizeof(u32)) > 1))
- cur_cpu_spec->cpu_features |= CPU_FTR_SMT;
+ cpu_set_feature(CPU_FTR_SMT);
return 0;
}
Index: kexec/arch/ppc64/kernel/setup.c
===================================================================
--- kexec.orig/arch/ppc64/kernel/setup.c
+++ kexec/arch/ppc64/kernel/setup.c
@@ -448,7 +448,7 @@ static void __init initialize_cache_info
}
size = 0;
- lsize = cur_cpu_spec->dcache_bsize;
+ lsize = cur_cpu_spec.dcache_bsize;
sizep = (u32 *)get_property(np, "d-cache-size", NULL);
if (sizep != NULL)
size = *sizep;
@@ -466,7 +466,7 @@ static void __init initialize_cache_info
ppc64_caches.dlines_per_page = PAGE_SIZE / lsize;
size = 0;
- lsize = cur_cpu_spec->icache_bsize;
+ lsize = cur_cpu_spec.icache_bsize;
sizep = (u32 *)get_property(np, "i-cache-size", NULL);
if (sizep != NULL)
size = *sizep;
@@ -736,8 +736,8 @@ static int show_cpuinfo(struct seq_file
seq_printf(m, "processor\t: %lu\n", cpu_id);
seq_printf(m, "cpu\t\t: ");
- if (cur_cpu_spec->pvr_mask)
- seq_printf(m, "%s", cur_cpu_spec->cpu_name);
+ if (cur_cpu_spec.pvr_mask)
+ seq_printf(m, "%s", cur_cpu_spec.cpu_name);
else
seq_printf(m, "unknown (%08x)", pvr);
Index: kexec/arch/ppc64/kernel/sysfs.c
===================================================================
--- kexec.orig/arch/ppc64/kernel/sysfs.c
+++ kexec/arch/ppc64/kernel/sysfs.c
@@ -215,21 +215,21 @@ static void register_cpu_online(unsigned
if (cpu_has_feature(CPU_FTR_MMCRA))
sysdev_create_file(s, &attr_mmcra);
- if (cur_cpu_spec->num_pmcs >= 1)
+ if (cur_cpu_spec.num_pmcs >= 1)
sysdev_create_file(s, &attr_pmc1);
- if (cur_cpu_spec->num_pmcs >= 2)
+ if (cur_cpu_spec.num_pmcs >= 2)
sysdev_create_file(s, &attr_pmc2);
- if (cur_cpu_spec->num_pmcs >= 3)
+ if (cur_cpu_spec.num_pmcs >= 3)
sysdev_create_file(s, &attr_pmc3);
- if (cur_cpu_spec->num_pmcs >= 4)
+ if (cur_cpu_spec.num_pmcs >= 4)
sysdev_create_file(s, &attr_pmc4);
- if (cur_cpu_spec->num_pmcs >= 5)
+ if (cur_cpu_spec.num_pmcs >= 5)
sysdev_create_file(s, &attr_pmc5);
- if (cur_cpu_spec->num_pmcs >= 6)
+ if (cur_cpu_spec.num_pmcs >= 6)
sysdev_create_file(s, &attr_pmc6);
- if (cur_cpu_spec->num_pmcs >= 7)
+ if (cur_cpu_spec.num_pmcs >= 7)
sysdev_create_file(s, &attr_pmc7);
- if (cur_cpu_spec->num_pmcs >= 8)
+ if (cur_cpu_spec.num_pmcs >= 8)
sysdev_create_file(s, &attr_pmc8);
if (cpu_has_feature(CPU_FTR_SMT))
@@ -257,21 +257,21 @@ static void unregister_cpu_online(unsign
if (cpu_has_feature(CPU_FTR_MMCRA))
sysdev_remove_file(s, &attr_mmcra);
- if (cur_cpu_spec->num_pmcs >= 1)
+ if (cur_cpu_spec.num_pmcs >= 1)
sysdev_remove_file(s, &attr_pmc1);
- if (cur_cpu_spec->num_pmcs >= 2)
+ if (cur_cpu_spec.num_pmcs >= 2)
sysdev_remove_file(s, &attr_pmc2);
- if (cur_cpu_spec->num_pmcs >= 3)
+ if (cur_cpu_spec.num_pmcs >= 3)
sysdev_remove_file(s, &attr_pmc3);
- if (cur_cpu_spec->num_pmcs >= 4)
+ if (cur_cpu_spec.num_pmcs >= 4)
sysdev_remove_file(s, &attr_pmc4);
- if (cur_cpu_spec->num_pmcs >= 5)
+ if (cur_cpu_spec.num_pmcs >= 5)
sysdev_remove_file(s, &attr_pmc5);
- if (cur_cpu_spec->num_pmcs >= 6)
+ if (cur_cpu_spec.num_pmcs >= 6)
sysdev_remove_file(s, &attr_pmc6);
- if (cur_cpu_spec->num_pmcs >= 7)
+ if (cur_cpu_spec.num_pmcs >= 7)
sysdev_remove_file(s, &attr_pmc7);
- if (cur_cpu_spec->num_pmcs >= 8)
+ if (cur_cpu_spec.num_pmcs >= 8)
sysdev_remove_file(s, &attr_pmc8);
if (cpu_has_feature(CPU_FTR_SMT))
Index: kexec/arch/powerpc/oprofile/common.c
===================================================================
--- kexec.orig/arch/powerpc/oprofile/common.c
+++ kexec/arch/powerpc/oprofile/common.c
@@ -173,12 +173,12 @@ int __init oprofile_arch_init(struct opr
ops->cpu_type = cpu_type;
#else /* __powerpc64__ */
- if (!cur_cpu_spec->oprofile_model || !cur_cpu_spec->oprofile_cpu_type)
+ if (!cur_cpu_spec.oprofile_model || !cur_cpu_spec.oprofile_cpu_type)
return -ENODEV;
- model = cur_cpu_spec->oprofile_model;
- model->num_counters = cur_cpu_spec->num_pmcs;
+ model = cur_cpu_spec.oprofile_model;
+ model->num_counters = cur_cpu_spec.num_pmcs;
- ops->cpu_type = cur_cpu_spec->oprofile_cpu_type;
+ ops->cpu_type = cur_cpu_spec.oprofile_cpu_type;
#endif /* __powerpc64__ */
ops->create_files = op_powerpc_create_files;
ops->setup = op_powerpc_setup;
Index: kexec/arch/powerpc/oprofile/op_model_power4.c
===================================================================
--- kexec.orig/arch/powerpc/oprofile/op_model_power4.c
+++ kexec/arch/powerpc/oprofile/op_model_power4.c
@@ -64,7 +64,7 @@ static void power4_reg_setup(struct op_c
backtrace_spinlocks = sys->backtrace_spinlocks;
- for (i = 0; i < cur_cpu_spec->num_pmcs; ++i)
+ for (i = 0; i < cur_cpu_spec.num_pmcs; ++i)
reset_value[i] = 0x80000000UL - ctr[i].count;
/* setup user and kernel profiling */
@@ -117,7 +117,7 @@ static void power4_start(struct op_count
/* set the PMM bit (see comment below) */
mtmsrd(mfmsr() | MSR_PMM);
- for (i = 0; i < cur_cpu_spec->num_pmcs; ++i) {
+ for (i = 0; i < cur_cpu_spec.num_pmcs; ++i) {
if (ctr[i].enabled) {
ctr_write(i, reset_value[i]);
} else {
@@ -268,7 +268,7 @@ static void power4_handle_interrupt(stru
/* set the PMM bit (see comment below) */
mtmsrd(mfmsr() | MSR_PMM);
- for (i = 0; i < cur_cpu_spec->num_pmcs; ++i) {
+ for (i = 0; i < cur_cpu_spec.num_pmcs; ++i) {
val = ctr_read(i);
if (val < 0) {
if (oprofile_running && ctr[i].enabled) {
Index: kexec/include/asm-powerpc/elf.h
===================================================================
--- kexec.orig/include/asm-powerpc/elf.h
+++ kexec/include/asm-powerpc/elf.h
@@ -213,7 +213,7 @@ extern int dump_task_fpu(struct task_str
instruction set this cpu supports. This could be done in userspace,
but it's not easy, and we've already done it here. */
#ifdef __powerpc64__
-# define ELF_HWCAP (cur_cpu_spec->cpu_user_features)
+# define ELF_HWCAP (cur_cpu_spec.cpu_user_features)
# define ELF_PLAT_INIT(_r, load_addr) do { \
memset(_r->gpr, 0, sizeof(_r->gpr)); \
_r->ctr = _r->link = _r->xer = _r->ccr = 0; \
^ permalink raw reply
* Re: [PATCH 0/8] apus update
From: Roman Zippel @ 2005-09-24 23:13 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <Pine.LNX.4.61.0509250032560.19121@scrub.home>
Hi,
On Sun, 25 Sep 2005, Roman Zippel wrote:
> Here are eight patches to get APUS closer to working.
All of them should of course include this line:
Signed-off-by: Roman Zippel <zippel@linux-m68k.org>
Sorry about that.
bye, Roman
^ permalink raw reply
* [PATCH 8/8] apus: update zorro bus access functions
From: Roman Zippel @ 2005-09-24 22:44 UTC (permalink / raw)
To: linuxppc-dev
APUS only needs an eieio() to synchronize IO access, also a simple C
construct to access memory mapped IO is sufficient.
---
include/asm-ppc/zorro.h | 52 ++++++++++++++++++++++++++++++++++++++++--------
1 file changed, 44 insertions(+), 8 deletions(-)
Index: linux/include/asm-ppc/zorro.h
===================================================================
--- linux.orig/include/asm-ppc/zorro.h 2005-09-23 15:52:38.000000000 +0200
+++ linux/include/asm-ppc/zorro.h 2005-09-23 16:45:08.000000000 +0200
@@ -3,13 +3,50 @@
#include <asm/io.h>
-#define z_readb in_8
-#define z_readw in_be16
-#define z_readl in_be32
-
-#define z_writeb(val, port) out_8((port), (val))
-#define z_writew(val, port) out_be16((port), (val))
-#define z_writel(val, port) out_be32((port), (val))
+static inline unsigned int z_readb(unsigned long addr)
+{
+ unsigned int ret;
+
+ ret = *(volatile u8 *)addr;
+ eieio();
+ return ret;
+}
+
+static inline unsigned int z_readw(unsigned long addr)
+{
+ unsigned int ret;
+
+ ret = *(volatile u16 *)addr;
+ eieio();
+ return ret;
+}
+
+static inline unsigned int z_readl(unsigned long addr)
+{
+ unsigned int ret;
+
+ ret = *(volatile u32 *)addr;
+ eieio();
+ return ret;
+}
+
+static inline void z_writeb(unsigned int val, unsigned long addr)
+{
+ *(volatile u8 *)addr = val;
+ eieio();
+}
+
+static inline void z_writew(unsigned int val, unsigned long addr)
+{
+ *(volatile u16 *)addr = val;
+ eieio();
+}
+
+static inline void z_writel(unsigned int val,unsigned long addr)
+{
+ *(volatile u32 *)addr = val;
+ eieio();
+}
#define z_memset_io(a,b,c) memset((void *)(a),(b),(c))
#define z_memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c))
@@ -19,7 +56,6 @@ extern void *__ioremap(unsigned long add
unsigned long flags);
extern void *ioremap(unsigned long address, unsigned long size);
-extern void iounmap(void *addr);
extern void *__ioremap(unsigned long address, unsigned long size,
unsigned long flags);
^ permalink raw reply
* [PATCH 7/8] apus: use pfn_to_page() for pmd_page()
From: Roman Zippel @ 2005-09-24 22:44 UTC (permalink / raw)
To: linuxppc-dev
pfn_to_page() does the same, but also takes care of the memory start if
necessary.
---
include/asm-ppc/pgtable.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Index: linux/include/asm-ppc/pgtable.h
===================================================================
--- linux.orig/include/asm-ppc/pgtable.h 2005-09-23 16:19:20.000000000 +0200
+++ linux/include/asm-ppc/pgtable.h 2005-09-23 16:20:31.000000000 +0200
@@ -723,7 +723,7 @@ extern pgprot_t phys_mem_access_prot(str
#define pmd_page_kernel(pmd) \
((unsigned long) __va(pmd_val(pmd) & PAGE_MASK))
#define pmd_page(pmd) \
- (mem_map + (pmd_val(pmd) >> PAGE_SHIFT))
+ pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT)
#else
#define pmd_page_kernel(pmd) \
((unsigned long) (pmd_val(pmd) & PAGE_MASK))
^ permalink raw reply
* [PATCH 6/8] apus: remove apus special case in address conversion
From: Roman Zippel @ 2005-09-24 22:44 UTC (permalink / raw)
To: linuxppc-dev
Use __pa()/__va() instead of direct calculation for the various address
conversions. This also removes the now unused mm_ptov().
---
arch/ppc/kernel/ppc_ksyms.c | 3 ---
arch/ppc/mm/pgtable.c | 39 ---------------------------------------
include/asm-ppc/io.h | 24 ++++--------------------
3 files changed, 4 insertions(+), 62 deletions(-)
Index: linux/include/asm-ppc/io.h
===================================================================
--- linux.orig/include/asm-ppc/io.h 2005-09-23 16:44:25.000000000 +0200
+++ linux/include/asm-ppc/io.h 2005-09-23 16:44:25.000000000 +0200
@@ -392,24 +392,16 @@ extern void io_block_mapping(unsigned lo
*/
extern inline unsigned long virt_to_bus(volatile void * address)
{
-#ifndef CONFIG_APUS
if (address == (void *)0)
return 0;
- return (unsigned long)address - KERNELBASE + PCI_DRAM_OFFSET;
-#else
- return iopa ((unsigned long) address);
-#endif
+ return __pa(address) + PCI_DRAM_OFFSET;
}
extern inline void * bus_to_virt(unsigned long address)
{
-#ifndef CONFIG_APUS
if (address == 0)
return NULL;
- return (void *)(address - PCI_DRAM_OFFSET + KERNELBASE);
-#else
- return (void*) mm_ptov (address);
-#endif
+ return __va(address) - PCI_DRAM_OFFSET;
}
/*
@@ -418,20 +410,12 @@ extern inline void * bus_to_virt(unsigne
*/
extern inline unsigned long virt_to_phys(volatile void * address)
{
-#ifndef CONFIG_APUS
- return (unsigned long) address - KERNELBASE;
-#else
- return iopa ((unsigned long) address);
-#endif
+ return __pa(address);
}
extern inline void * phys_to_virt(unsigned long address)
{
-#ifndef CONFIG_APUS
- return (void *) (address + KERNELBASE);
-#else
- return (void*) mm_ptov (address);
-#endif
+ return __va(address);
}
/*
Index: linux/arch/ppc/kernel/ppc_ksyms.c
===================================================================
--- linux.orig/arch/ppc/kernel/ppc_ksyms.c 2005-09-23 15:52:38.000000000 +0200
+++ linux/arch/ppc/kernel/ppc_ksyms.c 2005-09-23 16:48:47.000000000 +0200
@@ -68,8 +68,6 @@ long long __ashrdi3(long long, int);
long long __ashldi3(long long, int);
long long __lshrdi3(long long, int);
-extern unsigned long mm_ptov (unsigned long paddr);
-
EXPORT_SYMBOL(clear_pages);
EXPORT_SYMBOL(clear_user_page);
EXPORT_SYMBOL(do_signal);
@@ -145,7 +143,6 @@ EXPORT_SYMBOL(_outsw_ns);
EXPORT_SYMBOL(_insl_ns);
EXPORT_SYMBOL(_outsl_ns);
EXPORT_SYMBOL(iopa);
-EXPORT_SYMBOL(mm_ptov);
EXPORT_SYMBOL(ioremap);
#ifdef CONFIG_44x
EXPORT_SYMBOL(ioremap64);
Index: linux/arch/ppc/mm/pgtable.c
===================================================================
--- linux.orig/arch/ppc/mm/pgtable.c 2005-09-23 15:52:38.000000000 +0200
+++ linux/arch/ppc/mm/pgtable.c 2005-09-23 16:49:45.000000000 +0200
@@ -429,42 +429,3 @@ unsigned long iopa(unsigned long addr)
return(pa);
}
-
-/* This is will find the virtual address for a physical one....
- * Swiped from APUS, could be dangerous :-).
- * This is only a placeholder until I really find a way to make this
- * work. -- Dan
- */
-unsigned long
-mm_ptov (unsigned long paddr)
-{
- unsigned long ret;
-#if 0
- if (paddr < 16*1024*1024)
- ret = ZTWO_VADDR(paddr);
- else {
- int i;
-
- for (i = 0; i < kmap_chunk_count;){
- unsigned long phys = kmap_chunks[i++];
- unsigned long size = kmap_chunks[i++];
- unsigned long virt = kmap_chunks[i++];
- if (paddr >= phys
- && paddr < (phys + size)){
- ret = virt + paddr - phys;
- goto exit;
- }
- }
-
- ret = (unsigned long) __va(paddr);
- }
-exit:
-#ifdef DEBUGPV
- printk ("PTOV(%lx)=%lx\n", paddr, ret);
-#endif
-#else
- ret = (unsigned long)paddr + KERNELBASE;
-#endif
- return ret;
-}
-
^ permalink raw reply
* [PATCH 5/8] ppc: use correct asm ops
From: Roman Zippel @ 2005-09-24 22:43 UTC (permalink / raw)
To: linuxppc-dev
Use the correct assembler instructions, which match
__do_in_asm/__do_out_asm.
---
include/asm-ppc/io.h | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
Index: linux/include/asm-ppc/io.h
===================================================================
--- linux.orig/include/asm-ppc/io.h 2005-09-23 16:20:24.000000000 +0200
+++ linux/include/asm-ppc/io.h 2005-09-23 16:20:26.000000000 +0200
@@ -294,10 +294,10 @@ extern __inline__ void name(unsigned int
__do_out_asm(outb, "stbx")
#ifdef CONFIG_APUS
__do_in_asm(inb, "lbzx")
-__do_in_asm(inw, "lhz%U1%X1")
-__do_in_asm(inl, "lwz%U1%X1")
-__do_out_asm(outl,"stw%U0%X0")
-__do_out_asm(outw, "sth%U0%X0")
+__do_in_asm(inw, "lhzx")
+__do_in_asm(inl, "lwzx")
+__do_out_asm(outl,"stwx")
+__do_out_asm(outw, "sthx")
#elif defined (CONFIG_8260_PCI9)
/* in asm cannot be defined if PCI9 workaround is used */
#define inb(port) in_8((port)+___IO_BASE)
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