* Regarding PPC 64 kernel source.
From: vinay hegde @ 2005-10-12 5:09 UTC (permalink / raw)
To: linuxppc-embedded
Hi,
Can somebody point me the link from where I can
download PPC64 kernel source please??
Thanks!
vinay
__________________________________________________________
Yahoo! India Matrimony: Find your partner now. Go to http://yahoo.shaadi.com
^ permalink raw reply
* Re: Which PHY connection to use on MPC8541...
From: Gerhard Jaeger @ 2005-10-12 6:43 UTC (permalink / raw)
To: linuxppc-embedded; +Cc: Stefan Nickl
In-Reply-To: <4BD1885F-AD59-4FFF-8694-AB66BE80DF96@freescale.com>
On Tuesday 11 October 2005 20:05, Andy Fleming wrote:
> On Oct 11, 2005, at 05:57, Stefan Nickl wrote:
> > Hi,
> >
> > about a year ago we resorted to using port pin MDIO in this situation
> > for the FCCs because the fcc_enet driver and the gianfar driver live
> > in separate worlds, so to speak.
> >
> > But in the meantime, Andy Fleming was very active regarding the PHY
> > abstraction layer. I still haven't seen patches that migrate fcc_enet
> > to using this layer, but the gianfar driver seems to use this code
> > now.
> >
> The work to migrate the new fs_enet driver to use the TSEC MDIO is in
> progress. I have a few other things I'm working on right now, and
> I've been having some hardware issues, but I've already done most of
> the work to get the FCC to use the TSEC's MDIO bus.
> >
> > So I'd say quick solution: use TSEC1 MDIO for TSECs and cpm port pins
> > for FCC, clean solution: change fcc_enet to use the PHY abstraction
> > layer.
> >
> I'd say it depends on how long until your hardware is ready. You
> might want to wire up the cpm IO pins, just in case. I have yet to
> actually get the fs_enet driver to send packets on the 8560, so
> there's no telling how long it will be before that driver works on 8541.
>
> Andy
>
Thank you guys for the quick answers. We already thought of additionally
wireing up the cpm IO pins to have some kind of backup ;) We expect the
hardware to be available in february/march next year so I guess there's
pretty much time.
Gerhard
^ permalink raw reply
* Re: MPC8555 USB host support
From: Stefan Roese @ 2005-10-12 6:59 UTC (permalink / raw)
To: linuxppc-embedded; +Cc: Kylo Ginsberg
In-Reply-To: <61cc712d0510111329i45138617lc8eeea1edad4ae0f@mail.gmail.com>
On Tuesday 11 October 2005 22:29, Kylo Ginsberg wrote:
> I asked a similar question a few months back and found the comments
> instructive. Google for a thread started with this subject: "MPC885 -
> USB HCI drivers".
Thanks for the hint. This brings me back to the "MPC885 - USB HCI drivers"
thread.
Pantelis, you mentioned an existing (and working ;-)) linux 2.4 USB HCI driver
for 8xx and 82xx. Did you find the time to clean the driver up? Perhaps, I
could be your "vict^H^H^Holunteer", to port it to 2.6.
Best regards,
Stefan
^ permalink raw reply
* Re: MPC8555 USB host support
From: Stefan Roese @ 2005-10-12 7:27 UTC (permalink / raw)
To: Mike Rapoport; +Cc: linuxppc-embedded
In-Reply-To: <434CB71E.5000603@compulab.co.il>
Mike,
On Wednesday 12 October 2005 09:11, Mike Rapoport wrote:
> I don't know if Pantelis found a volo^H^H^Hictim, but I've made some
> porting of the USB HCI driver for
> 82xx (I afraid 8xx support was broken during the port). But the code is
> *very* ugly and still buggy.
I am currently collecting information about the porting effort, and your "ugly
and buggy" driver would be very helpful. So, please send me your version as
well. Thanks.
Best regards,
Stefan
^ permalink raw reply
* Re: MPC8555 USB host support
From: Pantelis Antoniou @ 2005-10-12 7:01 UTC (permalink / raw)
To: Stefan Roese; +Cc: Kylo Ginsberg, linuxppc-embedded
In-Reply-To: <200510120859.12362.sr@denx.de>
Stefan Roese wrote:
> On Tuesday 11 October 2005 22:29, Kylo Ginsberg wrote:
>
>>I asked a similar question a few months back and found the comments
>>instructive. Google for a thread started with this subject: "MPC885 -
>>USB HCI drivers".
>
>
> Thanks for the hint. This brings me back to the "MPC885 - USB HCI drivers"
> thread.
>
> Pantelis, you mentioned an existing (and working ;-)) linux 2.4 USB HCI driver
> for 8xx and 82xx. Did you find the time to clean the driver up? Perhaps, I
> could be your "vict^H^H^Holunteer", to port it to 2.6.
>
> Best regards,
> Stefan
>
>
Sure, I can always use a "vict^Wvolunteer" :)
Regards
Pantelis
^ permalink raw reply
* Re: MPC8555 USB host support
From: Mike Rapoport @ 2005-10-12 7:11 UTC (permalink / raw)
To: Stefan Roese; +Cc: linuxppc-embedded
In-Reply-To: <200510120859.12362.sr@denx.de>
Stefan Roese wrote:
>Pantelis, you mentioned an existing (and working ;-)) linux 2.4 USB HCI driver
>for 8xx and 82xx. Did you find the time to clean the driver up? Perhaps, I
>could be your "vict^H^H^Holunteer", to port it to 2.6.
>
Stefan,
I don't know if Pantelis found a volo^H^H^Hictim, but I've made some
porting of the USB HCI driver for
82xx (I afraid 8xx support was broken during the port). But the code is
*very* ugly and still buggy.
--
Sincerely yours,
Mike Rapoport
^ permalink raw reply
* init process not running
From: Nathael PAJANI @ 2005-10-12 10:03 UTC (permalink / raw)
To: linuxppc-embedded
Hi,
I'm porting the kernel (tried a 2.6.9 and 2.6.13) to an ACTIS Computer
board (MPC8560, e500 core), and I have a strange problem.
Everything seems all right, but the init process does not start.
I have an echo from the tty (cpm2 SCC1), so the kernel is not crashed.
I even got the ticker.
I first thought I had a problem with the console but if I use another
init process (using another process from the ramdisk, mke2fs), nothing
happens either.
I tried to replace the init process by another process which simply
returns (eventually after a printf("Hello world") ), so the kernel would
panic, but still nothing.
Tried to create a syscall which reboots the board, and call it from the
hello_world, nothing.
Tried to use an "init=/unexisting/process", and this skips to the next
possibility (/sbin/init), so the ramfs seem good, tried another ramfs,
which is running correctly on annother ppc board, but still the same
problem.
anyhow the "do_execve" is successfull.
The scheduler seems to be scheduling pid 3 and 8, it tries to wake up
pid 1, but its "old_state" is 0.
changing the state to 1 in "start_thread" does not fix this.
when a task is created, usualy "wake_up_new_task" is called, but not
here (but this is the first task using execve).
Does anyone have a clue about what I did wrong, or where and what to
look at?
Thanks a lot for your help.
Following two traces of the boot process, one with the 2.6.9, one with
the 2.6.13.2
Here is a trace of the boot process with the 2.6.9 kernel
(# represent the second):
Loading ELF headers...done
Loading segment #0 at
0x00800000....................................................................................e
Loading extra data at 0x00a33000....done
Lowest address: 0x00800000
Entry address: 0x00800000
Highest address: 0x00a3474e
Bytes loaded: 2312014
loaded at: 00800000 00A353CC
board data at: 00A3312C 00A3334C
relocated to: 00805090 008052B0
zimage at: 00805A21 00892EB8
initrd at: 00893000 00A32F88
avail ram: 00A36000 20000000
Linux/PPC load: rw console=ttyS0 root=/dev/ram0 init=/sbin/nath
Uncompressing Linux...done
Memory CAM mapping: CAM0=256Mb, CAM1=256Mb, CAM2=0Mb residual: 0Mb
Linux version 2.6.9-3 #174 Thu Oct 6 11:34:23 CEST 2005
cpm2_immr address (0xfff80000) remapped to 0xfdfc0000
Built 1 zonelists
Kernel command line: rw console=ttyS0 root=/dev/ram0 init=/sbin/nath
OpenPIC Version 1.2 (1 CPUs and 44 IRQ sources) at fdb7d000
PID hash table entries: 4096 (order: 12, 65536 bytes)
###Dentry cache hash table entries: 131072 (order: 7, 524288 bytes)
#Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
#Memory: 516096k available (888k kernel code, 340k data, 68k init, 0k
highmem)
Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
NATH: rest_init: going to kernel_thread
checking if image is initramfs...##########it isn't (no cpio magic);
looks like an initrd
Freeing initrd memory: 1663k freed
Linux NoNET1.0 for Linux 2.6
#<6>PCI: Probing PCI hardware
Serial: CPM driver $Revision: 0.01b $
ttyS0 at MMIO 0xfdfd1a00 (irq = 40) is a CPM UART
#RAMDISK driver initialized: 16 RAM disks of 8192K size 1024 blocksize
loop: loaded (max 8 devices)
Using anticipatory io scheduler
###########VFS: NATH: fs_names = ext2, name = /dev/root
VFS: Mounted root /dev/root (ext2 filesystem).
NATH: init: run_init_process, /sbin/nath
NATH: init: run_init_process, /sbin/init
#####################################################################
Here is a trace of the boot process with the 2.6.13 kernel:
Loading ELF headers...done
Loading segment #0 at
0x00800000...........................................................................e
Loading extra data at 0x00a41000........................done
Lowest address: 0x00800000
Entry address: 0x00800000
Highest address: 0x00a6ad8e
Bytes loaded: 2534798
loaded at: 00800000 00A433CC
board data at: 00A4112C 00A4134C
relocated to: 00805090 008052B0
zimage at: 00805A71 008A020B
initrd at: 008A1000 00A40F88
avail ram: 00A44000 20000000
Linux/PPC load: rw console=ttyS0 root=/dev/ram
Uncompressing Linux...done.
Now booting the kernel
Memory CAM mapping: CAM0=256Mb, CAM1=256Mb, CAM2=0Mb residual: 0Mb
Linux version 2.6.13-3 (nathael@linux-bbe) (gcc version 3.3.3) #62 Wed
Oct 12 10:43:49 CEST 2005
cpm2_immr address (0xfff80000) remapped to 0xfdfc0000
Built 1 zonelistchecking if image is initramfs...it isn't (no cpio
magic); looks like an initrd
Freeing initrd memory: 1663k freed
s
Kernel command line: rw console=ttyS0 root=/dev/ram
OpenPIC Version 1.2 (1 CPUs and 44 IRQ sources) at fdb7d000
PID hash table entries: 4096 (order: 12, 65536 bytes)
Dentry cache hash table entries: 131072 (order: 7, 524288 bytes)
Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
Memory: 515968k available (952k kernel code, 484k data, 88k init, 0k
highmem)
Mount-cache hash table entries: 512
checking if image is initramfs...it isn't (no cpio magic); looks like an
initrd
Freeing initrd memory: 1663k freed
Linux NoNET1.0 for Linux 2.6
PCI: Probing PCI hardware
Macintosh non-volatile memory driver v1.1
Serial: CPM driver $Revision: 0.01b $
ttyS0 at MMIO 0xfdfd1a00 (irq = 40) is a CPM UART
io scheduler noop registered
io scheduler anticipatory registered
io scheduler deadline registered
io scheduler cfq registered
RAMDISK driver initialized: 16 RAM disks of 8192K size 1024 blocksize
loop: loaded (max 8 devices)
VFS: Mounted root (ext2 filesystem).
Freeing unused kernel memory: 88k init
NATH: init: run_init_process, /sbin/init
NATH: sys_execve called.
NATH: do_execve: prepare_binprm done
NIP: 10000100 LR: 00000000 SP: 7F9ECF10 REGS: c089ff00 TRAP: 0c01 Not
tainted
MSR: 0002d002 EE: 1 PR: 1 FP: 0 ME: 1 IR/DR: 00
TASK = c0a4eb70[1] 'init' THREAD: c089e000
State: 0
Last syscall: 11
GPR00: 00000000 7F9ECF10 00000000 00000000 00000000 00000000 00000000
00000000
GPR08: 00000000 00000000 00000000 00000000 00000000
NIP [10000100] 0x10000100
LR [00000000] 0x0
NATH: load_elf_binary: OK
NATH: do_execve: success.
NATH: sys_execve: end.
NATH: try_to_wake_up, pid: 1, old_state: 0, state_mask: 1
NATH: try_to_wake_up, pid: 1, old_state: 0, state_mask: 1
NATH: try_to_wake_up, pid: 1, old_state: 0, state_mask: 1
NATH: try_to_wake_up, pid: 1, old_state: 0, state_mask: 1
NATH: try_to_wake_up, pid: 1, old_state: 0, state_mask: 1
NATH: try_to_wake_up, pid: 8, old_state: 1, state_mask: 15
NATH: activate_task, pid: 8, state: 1
NATH: try_to_wake_up, pid: 3, old_state: 1, state_mask: 3
NATH: activate_task, pid: 3, state: 1
.......
Nathaël PAJANI
CPE Lyon
^ permalink raw reply
* Re: MPC8555 USB host support
From: Alex Zeffertt @ 2005-10-12 12:34 UTC (permalink / raw)
To: Stefan Roese; +Cc: linuxppc-embedded
In-Reply-To: <200510120927.56692.sr@denx.de>
On Wed, 12 Oct 2005 09:27:56 +0200
Stefan Roese <sr@denx.de> wrote:
> Mike,
>
> On Wednesday 12 October 2005 09:11, Mike Rapoport wrote:
> > I don't know if Pantelis found a volo^H^H^Hictim, but I've made
> > some porting of the USB HCI driver for
> > 82xx (I afraid 8xx support was broken during the port). But the
> > code is*very* ugly and still buggy.
>
> I am currently collecting information about the porting effort, and
> your "ugly and buggy" driver would be very helpful. So, please send
> me your version as well. Thanks.
>
Yes me too please. Also Russell McGuire was asking earlier about
this. Maybe the best thing to do would be to create a sourceforge
project and post the latest patches there. I have an 8272ads board
and I'd be happy to test it out and provide feedback.
Regards,
Alex
^ permalink raw reply
* [PATCH 2/2] MTD: Add initial support for DAVE "PPChameleon" board.
From: Wolfgang Denk @ 2005-10-12 15:44 UTC (permalink / raw)
To: linuxppc-embedded; +Cc: llandre
Hello,
the following patch (against current kernel.org tree) adds MTD
support for the NOR and NAND flashes on the "PPChameleon" modules /
eval boards manufactured by DAVE s.r.l.
[PATCH] MTD: Add support for DAVE "PPChameleon" board.
Included support for the NOR and NAND flashes on the module, and for
the NAND flash on the eval board.
Note: on my system, all sectors of the NAND flash on the eval board
get flagged as bad, while there are actually only 5 bad sectors on
this device. This needs more investigation,
Signed-off-by: Wolfgang Denk <wd@denx.de>
---
commit 1fe4ae42778972c8065e5aaa1e807571798c57e8
tree 80ae5bb762dd29bb82d39f7bdd69ed7951aee629
parent c9759e3e50c6e0f7c935a0f84f6c811e0bc3bc84
author Wolfgang Denk <wd@pollux.denx.de> Wed, 12 Oct 2005 17:42:18 +0200
committer Wolfgang Denk <wd@pollux.denx.de> Wed, 12 Oct 2005 17:42:18 +0200
drivers/mtd/maps/Kconfig | 8 +++
drivers/mtd/maps/Makefile | 1
drivers/mtd/maps/ppchameleon.c | 109 +++++++++++++++++++++++++++++++++++++
drivers/mtd/nand/Kconfig | 6 +-
drivers/mtd/nand/ppchameleonevb.c | 55 +++++++++----------
5 files changed, 147 insertions(+), 32 deletions(-)
diff --git a/drivers/mtd/maps/Kconfig b/drivers/mtd/maps/Kconfig
--- a/drivers/mtd/maps/Kconfig
+++ b/drivers/mtd/maps/Kconfig
@@ -356,6 +356,14 @@ config MTD_REDWOOD
Redwood board. If you have one of these boards and would like to
use the flash chips on it, say 'Y'.
+config MTD_PPCHAMELEON
+ tristate "Flash device mapped on DAVE PPChamelonEVB Boards"
+ depends on MTD_CFI && PPC32 && 40x && PPChameleonEVB
+ help
+ This enables access routines for the flash chips on the
+ DAVE PPChamelonEVB board. If you have one of these boardsr
+ and would like to use the flash chips on it, say 'Y'.
+
config MTD_UBOOT_PARTITIONS
bool "Use U-Boot partition setup"
depends on MTD_WALNUT || MTD_EBONY || MTD_OCOTEA || MTD_BAMBOO
diff --git a/drivers/mtd/maps/Makefile b/drivers/mtd/maps/Makefile
--- a/drivers/mtd/maps/Makefile
+++ b/drivers/mtd/maps/Makefile
@@ -72,3 +72,4 @@ obj-$(CONFIG_MTD_DMV182) += dmv182.o
obj-$(CONFIG_MTD_SHARP_SL) += sharpsl-flash.o
obj-$(CONFIG_MTD_PLATRAM) += plat-ram.o
obj-$(CONFIG_MTD_OMAP_NOR) += omap_nor.o
+obj-$(CONFIG_MTD_PPCHAMELEON) += ppchameleon.o
diff --git a/drivers/mtd/maps/ppchameleon.c b/drivers/mtd/maps/ppchameleon.c
new file mode 100644
--- /dev/null
+++ b/drivers/mtd/maps/ppchameleon.c
@@ -0,0 +1,109 @@
+/*
+ * drivers/mtd/maps/ppchameleon.c
+ *
+ * Mapping for DAVE PPChamelonEVB flash
+ *
+ * Maintained by Wolfgang Denk, <wd@denx.de>
+ *
+ * Copyright (c) 2005 DENX Software Engineering
+ * Wolfgang Denk <wd@denx.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/map.h>
+#include <linux/mtd/partitions.h>
+#include <linux/config.h>
+#include <linux/version.h>
+#include <asm/io.h>
+#include <asm/ibm4xx.h>
+#include <asm/ppcboot.h>
+
+extern bd_t __res;
+
+static struct mtd_info *flash;
+
+static struct map_info ppchameleon_map = {
+ .name = "PPChameleon",
+ .bankwidth = 2,
+};
+
+static struct mtd_partition ppchameleon_partitions[] = {
+ {
+ name: "linux", /* Linux kernel image */
+ offset: 0x00000000,
+ size: 0x00180000,
+/* mask_flags: MTD_WRITEABLE, / * force read-only */
+ },
+ {
+ name: "user", /* unassigned */
+ offset: 0x00180000,
+ size: 0x00240000,
+ },
+ {
+ name: "u-boot", /* U-Boot Firmware */
+ offset: 0x003C0000,
+ size: 0x00040000, /* 256 KB */
+/* mask_flags: MTD_WRITEABLE, / * force read-only */
+ },
+};
+
+int __init init_ppchameleon(void)
+{
+ unsigned long flash_base, flash_size;
+
+ flash_base = __res.bi_flashstart;
+ flash_size = __res.bi_flashsize;
+
+ ppchameleon_map.size = flash_size;
+ ppchameleon_map.phys = flash_base;
+ ppchameleon_map.virt =
+ (void __iomem *)ioremap(flash_base, ppchameleon_map.size);
+
+ if (!ppchameleon_map.virt) {
+ printk("Failed to ioremap flash.\n");
+ return -EIO;
+ }
+
+ simple_map_init(&ppchameleon_map);
+
+ flash = do_map_probe("cfi_probe", &ppchameleon_map);
+ if (flash) {
+ flash->owner = THIS_MODULE;
+ add_mtd_partitions(flash, ppchameleon_partitions,
+ ARRAY_SIZE(ppchameleon_partitions));
+ } else {
+ printk("map probe failed for flash\n");
+ return -ENXIO;
+ }
+
+ return 0;
+}
+
+static void __exit cleanup_ppchameleon(void)
+{
+ if (flash) {
+ del_mtd_partitions(flash);
+ map_destroy(flash);
+ }
+
+ if (ppchameleon_map.virt) {
+ iounmap((void *)ppchameleon_map.virt);
+ ppchameleon_map.virt = 0;
+ }
+}
+
+module_init(init_ppchameleon);
+module_exit(cleanup_ppchameleon);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Wolfgang Denk <wd@denx.de>");
+MODULE_DESCRIPTION("MTD map and partitions for DAVE PPChameleonEVB boards");
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -75,10 +75,10 @@ config MTD_NAND_RTC_FROM4
flash interface board (FROM_BOARD4)
config MTD_NAND_PPCHAMELEONEVB
- tristate "NAND Flash device on PPChameleonEVB board"
- depends on PPCHAMELEONEVB && MTD_NAND
+ tristate "NAND Flash device on DAVE PPChameleonEVB board"
+ depends on PPChameleonEVB && MTD_NAND
help
- This enables the NAND flash driver on the PPChameleon EVB Board.
+ This enables the NAND flash driver on the DAVE PPChameleonEVB Board.
config MTD_NAND_S3C2410
tristate "NAND Flash support for S3C2410/S3C2440 SoC"
diff --git a/drivers/mtd/nand/ppchameleonevb.c b/drivers/mtd/nand/ppchameleonevb.c
--- a/drivers/mtd/nand/ppchameleonevb.c
+++ b/drivers/mtd/nand/ppchameleonevb.c
@@ -1,6 +1,7 @@
/*
* drivers/mtd/nand/ppchameleonevb.c
*
+ * Copyright (C) 2005 Wolfgang Denk <wd@denx.de>
* Copyright (C) 2003 DAVE Srl (info@wawnet.biz)
*
* Derived from drivers/mtd/nand/edb7312.c
@@ -30,7 +31,7 @@
#include <linux/mtd/nand.h>
#include <linux/mtd/partitions.h>
#include <asm/io.h>
-#include <platforms/PPChameleonEVB.h>
+#include <platforms/4xx/ppchameleon.h>
#undef USE_READY_BUSY_PIN
#define USE_READY_BUSY_PIN
@@ -41,8 +42,9 @@
/* handy sizes */
#define SZ_4M 0x00400000
#define NAND_SMALL_SIZE 0x02000000
-#define NAND_MTD_NAME "ppchameleon-nand"
-#define NAND_EVB_MTD_NAME "ppchameleonevb-nand"
+
+#define NAND_MTD_NAME "ppchameleon-nand"
+#define NAND_EVB_MTD_NAME "ppchameleonevb-nand"
/* GPIO pins used to drive NAND chip mounted on processor module */
#define NAND_nCE_GPIO_PIN (0x80000000 >> 1)
@@ -50,51 +52,46 @@
#define NAND_ALE_GPIO_PIN (0x80000000 >> 3)
#define NAND_RB_GPIO_PIN (0x80000000 >> 4)
/* GPIO pins used to drive NAND chip mounted on EVB */
-#define NAND_EVB_nCE_GPIO_PIN (0x80000000 >> 14)
-#define NAND_EVB_CLE_GPIO_PIN (0x80000000 >> 15)
-#define NAND_EVB_ALE_GPIO_PIN (0x80000000 >> 16)
-#define NAND_EVB_RB_GPIO_PIN (0x80000000 >> 31)
+#define NAND_EVB_nCE_GPIO_PIN (0x80000000 >> 14)
+#define NAND_EVB_CLE_GPIO_PIN (0x80000000 >> 15)
+#define NAND_EVB_ALE_GPIO_PIN (0x80000000 >> 16)
+#define NAND_EVB_RB_GPIO_PIN (0x80000000 >> 31)
/*
* MTD structure for PPChameleonEVB board
*/
-static struct mtd_info *ppchameleon_mtd = NULL;
+static struct mtd_info *ppchameleon_mtd = NULL;
static struct mtd_info *ppchameleonevb_mtd = NULL;
/*
* Module stuff
*/
-static unsigned long ppchameleon_fio_pbase = CFG_NAND0_PADDR;
+static unsigned long ppchameleon_fio_pbase = CFG_NAND0_PADDR;
static unsigned long ppchameleonevb_fio_pbase = CFG_NAND1_PADDR;
-#ifdef MODULE
-module_param(ppchameleon_fio_pbase, ulong, 0);
-module_param(ppchameleonevb_fio_pbase, ulong, 0);
-#else
-__setup("ppchameleon_fio_pbase=",ppchameleon_fio_pbase);
-__setup("ppchameleonevb_fio_pbase=",ppchameleonevb_fio_pbase);
-#endif
-
#ifdef CONFIG_MTD_PARTITIONS
/*
* Define static partitions for flash devices
*/
static struct mtd_partition partition_info_hi[] = {
- { name: "PPChameleon HI Nand Flash",
- offset: 0,
- size: 128*1024*1024 }
+ { name: "PPChameleon HI Nand Flash",
+ offset: 0,
+ size: 128*1024*1024
+ },
};
static struct mtd_partition partition_info_me[] = {
- { name: "PPChameleon ME Nand Flash",
- offset: 0,
- size: 32*1024*1024 }
+ { name: "PPChameleon ME Nand Flash",
+ offset: 0,
+ size: 32*1024*1024
+ },
};
static struct mtd_partition partition_info_evb[] = {
- { name: "PPChameleonEVB Nand Flash",
- offset: 0,
- size: 32*1024*1024 }
+ { name: "PPChameleonEVB Nand Flash",
+ offset: 0,
+ size: 32*1024*1024
+ },
};
#define NUM_PARTITIONS 1
@@ -405,9 +402,9 @@ static void __exit ppchameleonevb_cleanu
/* Release iomaps */
this = (struct nand_chip *) &ppchameleon_mtd[1];
- iounmap((void *) this->IO_ADDR_R;
+ iounmap((void *) this->IO_ADDR_R);
this = (struct nand_chip *) &ppchameleonevb_mtd[1];
- iounmap((void *) this->IO_ADDR_R;
+ iounmap((void *) this->IO_ADDR_R);
/* Free the MTD device structure */
kfree (ppchameleon_mtd);
@@ -417,4 +414,4 @@ module_exit(ppchameleonevb_cleanup);
MODULE_LICENSE("GPL");
MODULE_AUTHOR("DAVE Srl <support-ppchameleon@dave-tech.it>");
-MODULE_DESCRIPTION("MTD map driver for DAVE Srl PPChameleonEVB board");
+MODULE_DESCRIPTION("MTD NAND flash driver for DAVE Srl PPChameleonEVB board");
^ permalink raw reply
* [PATCH 1/2] ppc32: Add initial support for DAVE "PPChameleon" board.
From: Wolfgang Denk @ 2005-10-12 15:38 UTC (permalink / raw)
To: linuxppc-embedded; +Cc: llandre
Hello,
the following patch (against current kernel.org tree) adds suport for
the "PPChameleon" modules / eval boards manufactured by DAVE s.r.l.
[PATCH] ppc32: Add initial support for DAVE "PPChameleon" board.
Not included yet: support for MTD, I2C, RTC.
Signed-off-by: Wolfgang Denk <wd@denx.de>
---
commit c9759e3e50c6e0f7c935a0f84f6c811e0bc3bc84
tree ae801a82c095e78a09fca6d4b77c9ee5d677304a
parent 2f70d4fec3a12a03db9a6accbff3271c85b91a2b
author Wolfgang Denk <wd@pollux.denx.de> Wed, 12 Oct 2005 17:29:22 +0200
committer Wolfgang Denk <wd@pollux.denx.de> Wed, 12 Oct 2005 17:29:22 +0200
arch/ppc/configs/PPChameleon_defconfig | 881 ++++++++++++++++++++++++++++++++
arch/ppc/platforms/4xx/Kconfig | 9
arch/ppc/platforms/4xx/Makefile | 1
arch/ppc/platforms/4xx/ibm405ep.h | 49 +-
arch/ppc/platforms/4xx/ppchameleon.c | 257 +++++++++
arch/ppc/platforms/4xx/ppchameleon.h | 145 +++++
include/asm-ppc/ibm4xx.h | 4
7 files changed, 1328 insertions(+), 18 deletions(-)
diff --git a/arch/ppc/configs/PPChameleon_defconfig b/arch/ppc/configs/PPChameleon_defconfig
new file mode 100644
--- /dev/null
+++ b/arch/ppc/configs/PPChameleon_defconfig
@@ -0,0 +1,881 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.14-rc3
+# Mon Oct 10 14:06:58 2005
+#
+CONFIG_MMU=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_RWSEM_XCHGADD_ALGORITHM=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_PPC=y
+CONFIG_PPC32=y
+CONFIG_GENERIC_NVRAM=y
+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+CONFIG_ARCH_MAY_HAVE_PC_FDC=y
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_CLEAN_COMPILE=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+
+#
+# General setup
+#
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_SYSCTL=y
+# CONFIG_AUDIT is not set
+# CONFIG_HOTPLUG is not set
+CONFIG_KOBJECT_UEVENT=y
+# CONFIG_IKCONFIG is not set
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_EMBEDDED=y
+# CONFIG_KALLSYMS is not set
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+# CONFIG_EPOLL is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SHMEM=y
+CONFIG_CC_ALIGN_FUNCTIONS=0
+CONFIG_CC_ALIGN_LABELS=0
+CONFIG_CC_ALIGN_LOOPS=0
+CONFIG_CC_ALIGN_JUMPS=0
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+
+#
+# Loadable module support
+#
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_OBSOLETE_MODPARM=y
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
+
+#
+# Processor
+#
+# CONFIG_6xx is not set
+CONFIG_40x=y
+# CONFIG_44x is not set
+# CONFIG_POWER3 is not set
+# CONFIG_POWER4 is not set
+# CONFIG_8xx is not set
+# CONFIG_E200 is not set
+# CONFIG_E500 is not set
+# CONFIG_MATH_EMULATION is not set
+# CONFIG_KEXEC is not set
+# CONFIG_CPU_FREQ is not set
+CONFIG_4xx=y
+# CONFIG_WANT_EARLY_SERIAL is not set
+
+#
+# IBM 4xx options
+#
+# CONFIG_BUBINGA is not set
+# CONFIG_CPCI405 is not set
+# CONFIG_EP405 is not set
+CONFIG_PPChameleonEVB=y
+# CONFIG_REDWOOD_5 is not set
+# CONFIG_REDWOOD_6 is not set
+# CONFIG_SYCAMORE is not set
+# CONFIG_WALNUT is not set
+# CONFIG_XILINX_ML300 is not set
+CONFIG_IBM_OCP=y
+CONFIG_405EP=y
+# CONFIG_PPC4xx_DMA is not set
+CONFIG_PPC_GEN550=y
+CONFIG_UART0_TTYS0=y
+# CONFIG_UART0_TTYS1 is not set
+CONFIG_NOT_COHERENT_CACHE=y
+
+#
+# Platform options
+#
+# CONFIG_PC_KEYBOARD is not set
+# CONFIG_HIGHMEM is not set
+CONFIG_HZ_100=y
+# CONFIG_HZ_250 is not set
+# CONFIG_HZ_1000 is not set
+CONFIG_HZ=100
+CONFIG_PREEMPT_NONE=y
+# CONFIG_PREEMPT_VOLUNTARY is not set
+# CONFIG_PREEMPT is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_CMDLINE_BOOL is not set
+# CONFIG_PM is not set
+# CONFIG_SOFTWARE_SUSPEND is not set
+CONFIG_SECCOMP=y
+CONFIG_ISA_DMA_API=y
+
+#
+# Bus options
+#
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_LEGACY_PROC=y
+
+#
+# PCCARD (PCMCIA/CardBus) support
+#
+# CONFIG_PCCARD is not set
+
+#
+# Advanced setup
+#
+# CONFIG_ADVANCED_OPTIONS is not set
+
+#
+# Default settings for advanced configuration options are used
+#
+CONFIG_HIGHMEM_START=0xfe000000
+CONFIG_LOWMEM_SIZE=0x30000000
+CONFIG_KERNEL_START=0xc0000000
+CONFIG_TASK_SIZE=0x80000000
+CONFIG_CONSISTENT_START=0xff100000
+CONFIG_CONSISTENT_SIZE=0x00200000
+CONFIG_BOOT_LOAD=0x00400000
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+CONFIG_SYN_COOKIES=y
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_BIC=y
+# CONFIG_IPV6 is not set
+# CONFIG_NETFILTER is not set
+
+#
+# DCCP Configuration (EXPERIMENTAL)
+#
+# CONFIG_IP_DCCP is not set
+
+#
+# SCTP Configuration (EXPERIMENTAL)
+#
+# CONFIG_IP_SCTP is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_NET_CLS_ROUTE is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_IEEE80211 is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+# CONFIG_STANDALONE is not set
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_FW_LOADER is not set
+
+#
+# Connector - unified userspace <-> kernelspace linker
+#
+# CONFIG_CONNECTOR is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_AMDSTD_RETRY=3
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+CONFIG_MTD_COMPLEX_MAPPINGS=y
+# CONFIG_MTD_PHYSMAP is not set
+CONFIG_MTD_PPCHAMELEON=y
+# CONFIG_MTD_PCI is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLKMTD is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+
+#
+# NAND Flash Device Drivers
+#
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_VERIFY_WRITE=y
+CONFIG_MTD_NAND_IDS=y
+CONFIG_MTD_NAND_PPCHAMELEONEVB=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Plug and Play support
+#
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_SX8 is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=4
+CONFIG_BLK_DEV_RAM_SIZE=4096
+CONFIG_BLK_DEV_INITRD=y
+# CONFIG_LBD is not set
+# CONFIG_CDROM_PKTCDVD is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_ATA_OVER_ETH is not set
+
+#
+# ATA/ATAPI/MFM/RLL support
+#
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+
+#
+# Fusion MPT device support
+#
+# CONFIG_FUSION is not set
+
+#
+# IEEE 1394 (FireWire) support
+#
+# CONFIG_IEEE1394 is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+
+#
+# Macintosh device drivers
+#
+
+#
+# Network device support
+#
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+
+#
+# ARCnet devices
+#
+# CONFIG_ARCNET is not set
+
+#
+# PHY device support
+#
+# CONFIG_PHYLIB is not set
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_CASSINI is not set
+# CONFIG_NET_VENDOR_3COM is not set
+
+#
+# Tulip family network device support
+#
+# CONFIG_NET_TULIP is not set
+# CONFIG_HP100 is not set
+CONFIG_IBM_EMAC=y
+CONFIG_IBM_EMAC_RXB=64
+CONFIG_IBM_EMAC_TXB=32
+CONFIG_IBM_EMAC_POLL_WEIGHT=32
+CONFIG_IBM_EMAC_RX_COPY_THRESHOLD=256
+CONFIG_IBM_EMAC_RX_SKB_HEADROOM=0
+# CONFIG_IBM_EMAC_PHY_RX_CLK_FIX is not set
+# CONFIG_IBM_EMAC_DEBUG is not set
+# CONFIG_NET_PCI is not set
+
+#
+# Ethernet (1000 Mbit)
+#
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_E1000 is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_R8169 is not set
+# CONFIG_SIS190 is not set
+# CONFIG_SKGE is not set
+# CONFIG_SK98LIN is not set
+# CONFIG_TIGON3 is not set
+# CONFIG_BNX2 is not set
+
+#
+# Ethernet (10000 Mbit)
+#
+# CONFIG_CHELSIO_T1 is not set
+# CONFIG_IXGB is not set
+# CONFIG_S2IO is not set
+
+#
+# Token Ring devices
+#
+# CONFIG_TR is not set
+
+#
+# Wireless LAN (non-hamradio)
+#
+# CONFIG_NET_RADIO is not set
+
+#
+# Wan interfaces
+#
+# CONFIG_WAN is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_SHAPER is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# Telephony Support
+#
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_TSDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+# CONFIG_SERIO_I8042 is not set
+# CONFIG_SERIO_SERPORT is not set
+# CONFIG_SERIO_PCIPS2 is not set
+# CONFIG_SERIO_LIBPS2 is not set
+# CONFIG_SERIO_RAW is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=2
+# CONFIG_SERIAL_8250_EXTENDED is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_JSM is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+
+#
+# IPMI
+#
+# CONFIG_IPMI_HANDLER is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_NVRAM is not set
+CONFIG_GEN_RTC=y
+# CONFIG_GEN_RTC_X is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_RAW_DRIVER is not set
+
+#
+# TPM devices
+#
+# CONFIG_TCG_TPM is not set
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# Dallas's 1-wire bus
+#
+# CONFIG_W1 is not set
+
+#
+# Hardware Monitoring support
+#
+CONFIG_HWMON=y
+# CONFIG_HWMON_VID is not set
+# CONFIG_HWMON_DEBUG_CHIP is not set
+
+#
+# Misc devices
+#
+
+#
+# Multimedia Capabilities Port drivers
+#
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# Digital Video Broadcasting Devices
+#
+# CONFIG_DVB is not set
+
+#
+# Graphics support
+#
+# CONFIG_FB is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+# CONFIG_USB is not set
+
+#
+# USB Gadget Support
+#
+# CONFIG_USB_GADGET is not set
+
+#
+# MMC/SD Card support
+#
+# CONFIG_MMC is not set
+
+#
+# InfiniBand support
+#
+# CONFIG_INFINIBAND is not set
+
+#
+# SN Devices
+#
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+# CONFIG_EXT2_FS_SECURITY is not set
+CONFIG_EXT2_FS_XIP=y
+CONFIG_FS_XIP=y
+# CONFIG_EXT3_FS is not set
+# CONFIG_JBD is not set
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+# CONFIG_XFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_INOTIFY=y
+# CONFIG_QUOTA is not set
+CONFIG_DNOTIFY=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_RAMFS=y
+# CONFIG_RELAYFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
+CONFIG_JFFS2_ZLIB=y
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+# CONFIG_JFFS2_CMODE_NONE is not set
+CONFIG_JFFS2_CMODE_PRIORITY=y
+# CONFIG_JFFS2_CMODE_SIZE is not set
+CONFIG_CRAMFS=y
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+
+#
+# Network File Systems
+#
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_NFS_V3_ACL=y
+CONFIG_NFS_V4=y
+# CONFIG_NFS_DIRECTIO is not set
+# CONFIG_NFSD is not set
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_ACL_SUPPORT=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+CONFIG_SUNRPC_GSS=y
+CONFIG_RPCSEC_GSS_KRB5=y
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+# CONFIG_9P_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+# CONFIG_MSDOS_PARTITION is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+
+#
+# Native Language Support
+#
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+# CONFIG_NLS_CODEPAGE_437 is not set
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+CONFIG_NLS_ASCII=y
+# CONFIG_NLS_ISO8859_1 is not set
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+
+#
+# IBM 40x options
+#
+
+#
+# Library routines
+#
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+CONFIG_CRC32=y
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+
+#
+# Profiling support
+#
+# CONFIG_PROFILING is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+# CONFIG_DEBUG_KERNEL is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_SERIAL_TEXT_DEBUG is not set
+CONFIG_PPC_OCP=y
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+
+#
+# Cryptographic options
+#
+CONFIG_CRYPTO=y
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_MD4 is not set
+CONFIG_CRYPTO_MD5=y
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_WP512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Hardware crypto devices
+#
diff --git a/arch/ppc/platforms/4xx/Kconfig b/arch/ppc/platforms/4xx/Kconfig
--- a/arch/ppc/platforms/4xx/Kconfig
+++ b/arch/ppc/platforms/4xx/Kconfig
@@ -32,6 +32,11 @@ config EP405
help
This option enables support for the EP405/EP405PC boards.
+config PPChameleonEVB
+ bool "PPChameleonEVB"
+ help
+ This option enables support for the DAVE 405EP evaluation board.
+
config REDWOOD_5
bool "Redwood-5"
help
@@ -175,7 +180,7 @@ config BOOKE
config IBM_OCP
bool
- depends on ASH || BAMBOO || BUBINGA || CPCI405 || EBONY || EP405 || LUAN || OCOTEA || REDWOOD_5 || REDWOOD_6 || SYCAMORE || WALNUT || YELLOWSTONE || YOSEMITE
+ depends on ASH || BAMBOO || BUBINGA || CPCI405 || EBONY || EP405 || LUAN || OCOTEA || PPChameleonEVB || REDWOOD_5 || REDWOOD_6 || SYCAMORE || WALNUT || YELLOWSTONE || YOSEMITE
default y
config XILINX_OCP
@@ -201,7 +206,7 @@ config 403GCX
config 405EP
bool
- depends on BUBINGA
+ depends on BUBINGA || PPChameleonEVB
default y
config 405GP
diff --git a/arch/ppc/platforms/4xx/Makefile b/arch/ppc/platforms/4xx/Makefile
--- a/arch/ppc/platforms/4xx/Makefile
+++ b/arch/ppc/platforms/4xx/Makefile
@@ -8,6 +8,7 @@ obj-$(CONFIG_EP405) += ep405.o
obj-$(CONFIG_BUBINGA) += bubinga.o
obj-$(CONFIG_LUAN) += luan.o
obj-$(CONFIG_OCOTEA) += ocotea.o
+obj-$(CONFIG_PPChameleonEVB) += ppchameleon.o
obj-$(CONFIG_REDWOOD_5) += redwood5.o
obj-$(CONFIG_REDWOOD_6) += redwood6.o
obj-$(CONFIG_SYCAMORE) += sycamore.o
diff --git a/arch/ppc/platforms/4xx/ibm405ep.h b/arch/ppc/platforms/4xx/ibm405ep.h
--- a/arch/ppc/platforms/4xx/ibm405ep.h
+++ b/arch/ppc/platforms/4xx/ibm405ep.h
@@ -54,6 +54,23 @@
#define PPC4xx_ONB_IO_VADDR PPC4xx_ONB_IO_PADDR
#define PPC4xx_ONB_IO_SIZE ((uint)4*1024)
+/* GPIO macro register defines */
+#define GPIO_BASE ((uint)0xEF600700)
+#define GPIO0_OR (GPIO_BASE+0x0)
+#define GPIO0_TCR (GPIO_BASE+0x4)
+#define GPIO0_OSRH (GPIO_BASE+0x8)
+#define GPIO0_OSRL (GPIO_BASE+0xC)
+#define GPIO0_TSRH (GPIO_BASE+0x10)
+#define GPIO0_TSRL (GPIO_BASE+0x14)
+#define GPIO0_ODR (GPIO_BASE+0x18)
+#define GPIO0_IR (GPIO_BASE+0x1C)
+#define GPIO0_RR1 (GPIO_BASE+0x20)
+#define GPIO0_RR2 (GPIO_BASE+0x24)
+#define GPIO0_ISR1H (GPIO_BASE+0x30)
+#define GPIO0_ISR1L (GPIO_BASE+0x34)
+#define GPIO0_ISR2H (GPIO_BASE+0x38)
+#define GPIO0_ISR2L (GPIO_BASE+0x3C)
+
/* serial port defines */
#define RS_TABLE_SIZE 2
@@ -91,8 +108,8 @@
STD_UART_OP(1)
/* DCR defines */
-#define DCRN_CPMSR_BASE 0x0BA
-#define DCRN_CPMFR_BASE 0x0B9
+#define DCRN_CPMSR_BASE 0x0BA
+#define DCRN_CPMFR_BASE 0x0B9
#define DCRN_CPC0_PLLMR0_BASE 0x0F0
#define DCRN_CPC0_BOOT_BASE 0x0F1
@@ -107,20 +124,20 @@
#define DCRN_CPC0_PCI_BASE 0x0F9
-#define IBM_CPM_GPT 0x80000000 /* GPT interface */
-#define IBM_CPM_PCI 0x40000000 /* PCI bridge */
-#define IBM_CPM_UIC 0x00010000 /* Universal Int Controller */
-#define IBM_CPM_CPU 0x00008000 /* processor core */
-#define IBM_CPM_EBC 0x00002000 /* EBC controller */
-#define IBM_CPM_SDRAM0 0x00004000 /* SDRAM memory controller */
-#define IBM_CPM_GPIO0 0x00001000 /* General Purpose IO */
-#define IBM_CPM_TMRCLK 0x00000400 /* CPU timers */
-#define IBM_CPM_PLB 0x00000100 /* PLB bus arbiter */
-#define IBM_CPM_OPB 0x00000080 /* PLB to OPB bridge */
-#define IBM_CPM_DMA 0x00000040 /* DMA controller */
-#define IBM_CPM_IIC0 0x00000010 /* IIC interface */
-#define IBM_CPM_UART1 0x00000002 /* serial port 0 */
-#define IBM_CPM_UART0 0x00000001 /* serial port 1 */
+#define IBM_CPM_GPT 0x80000000 /* GPT interface */
+#define IBM_CPM_PCI 0x40000000 /* PCI bridge */
+#define IBM_CPM_UIC 0x00010000 /* Universal Int Controller */
+#define IBM_CPM_CPU 0x00008000 /* processor core */
+#define IBM_CPM_EBC 0x00002000 /* EBC controller */
+#define IBM_CPM_SDRAM0 0x00004000 /* SDRAM memory controller */
+#define IBM_CPM_GPIO0 0x00001000 /* General Purpose IO */
+#define IBM_CPM_TMRCLK 0x00000400 /* CPU timers */
+#define IBM_CPM_PLB 0x00000100 /* PLB bus arbiter */
+#define IBM_CPM_OPB 0x00000080 /* PLB to OPB bridge */
+#define IBM_CPM_DMA 0x00000040 /* DMA controller */
+#define IBM_CPM_IIC0 0x00000010 /* IIC interface */
+#define IBM_CPM_UART1 0x00000002 /* serial port 0 */
+#define IBM_CPM_UART0 0x00000001 /* serial port 1 */
#define DFLT_IBM4xx_PM ~(IBM_CPM_PCI | IBM_CPM_CPU | IBM_CPM_DMA \
| IBM_CPM_OPB | IBM_CPM_EBC \
| IBM_CPM_SDRAM0 | IBM_CPM_PLB \
diff --git a/arch/ppc/platforms/4xx/ppchameleon.c b/arch/ppc/platforms/4xx/ppchameleon.c
new file mode 100644
--- /dev/null
+++ b/arch/ppc/platforms/4xx/ppchameleon.c
@@ -0,0 +1,257 @@
+/*
+ * Support for DAVE PPC 405EP evaluation board (PPChameleon).
+ *
+ * Author: Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
+ * derived from "Octobus hppc405" board by haag.cc
+ * (see http://www.haag.cc/downloads/files/octobus-hppc405-2.6.12.2-V0.1)
+ * which in turn was obviously based on evb405ep.
+ * Maintained by Wolfgang Denk, <wd@denx.de>
+ *
+ * 2005 (c) Wolfgang Denk, DENX Software Engineering. This file is
+ * licensed under the terms of the GNU General Public License version 2.
+ * This program is licensed "as is" without any warranty of any kind,
+ * whether express or implied.
+ */
+
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/pci.h>
+#include <linux/serial_core.h>
+#include <linux/serial.h>
+
+#include <asm/system.h>
+#include <asm/pci-bridge.h>
+#include <asm/machdep.h>
+#include <asm/page.h>
+#include <asm/time.h>
+#include <asm/io.h>
+#include <asm/ocp.h>
+#include <platforms/4xx/ibm405ep.h>
+
+#ifdef CONFIG_PPC_RTC
+#include <asm/todc.h>
+#endif
+
+#include <asm/kgdb.h>
+
+#undef DEBUG
+
+#ifdef DEBUG
+#define DBG(x...) printk(x)
+#else
+#define DBG(x...)
+#endif
+
+
+void *ppchameleon_rtc_base;
+
+extern void gen550_init(int, struct uart_port *);
+extern int early_serial_setup(struct uart_port *port);
+
+/* Some IRQs unique to the board
+ * Used by the generic 405 PCI setup functions in ppc4xx_pci.c
+ */
+int __init
+ppc405_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
+{
+ static char pci_irq_table[][4] =
+ /*
+ * PCI IDSEL/INTPIN->INTLINE
+ * A B C D
+ */
+ {
+ {28, 28, 28, 28}, /* IDSEL 1 - PCI slot 1 */
+ {29, 29, 29, 29}, /* IDSEL 2 - PCI slot 2 */
+ {30, 30, 30, 30}, /* IDSEL 3 - PCI slot 3 */
+ {31, 31, 31, 31}, /* IDSEL 4 - PCI slot 4 */
+ };
+
+ const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
+ return PCI_IRQ_TABLE_LOOKUP;
+};
+
+
+/* The serial clock for the chip is an internal clock determined by
+ * different clock speeds/dividers.
+ * Calculate the proper input baud rate and setup the serial driver.
+ */
+
+static void __init
+ppchameleon_early_serial_map (void)
+{
+ u32 uart_div;
+ struct uart_port port;
+ int serial_baud_405ep;
+
+ int size = sizeof (port);
+ bd_t tmp = (bd_t) __res;
+
+ /* bd_t *bip = &tmp; */
+ uart_div = (mfdcr (DCRN_CPC0_UCR_BASE) & DCRN_CPC0_UCR_U0DIV);
+
+ serial_baud_405ep = tmp.bi_intfreq / uart_div;
+ /* serial_baud_405ep=__res.bi_baudrate * uart_div; */
+
+ /* Setup ioremapped serial port access */
+ memset (&port, 0, size);
+ port.membase = (void *) ACTING_UART0_IO_BASE;
+ port.irq = UART0_INT;
+ port.uartclk = serial_baud_405ep;
+ port.regshift = 0;
+ port.iotype = SERIAL_IO_MEM;
+ port.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST;
+ port.line = 0;
+
+ if (early_serial_setup (&port) != 0) {
+ printk ("Early serial init of port 0 failed\n");
+ }
+}
+
+
+void __init board_setup_arch (void)
+{
+
+ ppc4xx_setup_arch ();
+
+ ibm_ocp_set_emac(0, 1);
+
+ ppchameleon_early_serial_map ();
+
+ printk ("DAVE PPchameleonEVB Board (Wolfgang Denk wd@denx.de)\n");
+}
+
+#if defined(CONFIG_BIOS_FIXUP)
+void __init bios_fixup (struct pci_controller *hose, struct pcil0_regs *pcip)
+{
+
+ unsigned int bar_response, bar;
+
+ /*
+ * Expected PCI mapping:
+ *
+ * PLB addr PCI memory addr
+ * --------------------- ---------------------
+ * 0000'0000 - 7fff'ffff <--- 0000'0000 - 7fff'ffff
+ * 8000'0000 - Bfff'ffff ---> 8000'0000 - Bfff'ffff
+ *
+ * PLB addr PCI io addr
+ * --------------------- ---------------------
+ * e800'0000 - e800'ffff ---> 0000'0000 - 0001'0000
+ *
+ * The following code is simplified by assuming that the bootrom
+ * has been well behaved in following this mapping.
+ */
+
+#ifdef DEBUG
+ int i;
+
+ printk ("ioremap PCLIO_BASE = 0x%x\n", pcip);
+ printk ("PCI bridge regs before fixup \n");
+ for (i = 0; i <= 3; i++) {
+ printk (" pmm%dma\t0x%x\n", i, in_le32 (&(pcip->pmm[i].ma)));
+ printk (" pmm%dma\t0x%x\n", i, in_le32 (&(pcip->pmm[i].la)));
+ printk (" pmm%dma\t0x%x\n", i,
+ in_le32 (&(pcip->pmm[i].pcila)));
+ printk (" pmm%dma\t0x%x\n", i,
+ in_le32 (&(pcip->pmm[i].pciha)));
+ }
+ printk (" ptm1ms\t0x%x\n", in_le32 (&(pcip->ptm1ms)));
+ printk (" ptm1la\t0x%x\n", in_le32 (&(pcip->ptm1la)));
+ printk (" ptm2ms\t0x%x\n", in_le32 (&(pcip->ptm2ms)));
+ printk (" ptm2la\t0x%x\n", in_le32 (&(pcip->ptm2la)));
+
+#endif
+
+ /* added for IBM boot rom version 1.15 bios bar changes -AK */
+
+ /* Disable region first */
+ out_le32 ((void *) &(pcip->pmm[0].ma), 0x00000000);
+ /* PLB starting addr, PCI: 0x80000000 */
+ out_le32 ((void *) &(pcip->pmm[0].la), 0x80000000);
+ /* PCI start addr, 0x80000000 */
+ out_le32 ((void *) &(pcip->pmm[0].pcila), PPC405_PCI_MEM_BASE);
+ /* 512MB range of PLB to PCI */
+ out_le32 ((void *) &(pcip->pmm[0].pciha), 0x00000000);
+ /* Enable no pre-fetch, enable region */
+ out_le32 ((void *) &(pcip->pmm[0].ma), ((0xffffffff -
+ (PPC405_PCI_UPPER_MEM -
+ PPC405_PCI_MEM_BASE)) |
+ 0x01));
+
+ /* Disable region one */
+ out_le32 ((void *) &(pcip->pmm[1].ma), 0x00000000);
+ out_le32 ((void *) &(pcip->pmm[1].la), 0x00000000);
+ out_le32 ((void *) &(pcip->pmm[1].pcila), 0x00000000);
+ out_le32 ((void *) &(pcip->pmm[1].pciha), 0x00000000);
+ out_le32 ((void *) &(pcip->pmm[1].ma), 0x00000000);
+ out_le32 ((void *) &(pcip->ptm1ms), 0x00000001);
+
+ /* Disable region two */
+ out_le32 ((void *) &(pcip->pmm[2].ma), 0x00000000);
+ out_le32 ((void *) &(pcip->pmm[2].la), 0x00000000);
+ out_le32 ((void *) &(pcip->pmm[2].pcila), 0x00000000);
+ out_le32 ((void *) &(pcip->pmm[2].pciha), 0x00000000);
+ out_le32 ((void *) &(pcip->pmm[2].ma), 0x00000000);
+ out_le32 ((void *) &(pcip->ptm2ms), 0x00000000);
+ out_le32 ((void *) &(pcip->ptm2la), 0x00000000);
+
+ /* Zero config bars */
+ for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) {
+ early_write_config_dword (hose, hose->first_busno,
+ PCI_FUNC (hose->first_busno), bar,
+ 0x00000000);
+ early_read_config_dword (hose, hose->first_busno,
+ PCI_FUNC (hose->first_busno), bar,
+ &bar_response);
+ DBG ("BUS %d, device %d, Function %d bar 0x%8.8x is 0x%8.8x\n", hose->first_busno, PCI_SLOT (hose->first_busno), PCI_FUNC (hose->first_busno), bar, bar_response);
+ }
+ /* end work arround */
+#ifdef DEBUG
+
+ printk ("PCI bridge regs after fixup \n");
+ for (i = 0; i <= 3; i++) {
+ printk (" pmm%dma\t0x%x\n", i, in_le32 (&(pcip->pmm[i].ma)));
+ printk (" pmm%dma\t0x%x\n", i, in_le32 (&(pcip->pmm[i].la)));
+ printk (" pmm%dma\t0x%x\n", i,
+ in_le32 (&(pcip->pmm[i].pcila)));
+ printk (" pmm%dma\t0x%x\n", i,
+ in_le32 (&(pcip->pmm[i].pciha)));
+ }
+ printk (" ptm1ms\t0x%x\n", in_le32 (&(pcip->ptm1ms)));
+ printk (" ptm1la\t0x%x\n", in_le32 (&(pcip->ptm1la)));
+ printk (" ptm2ms\t0x%x\n", in_le32 (&(pcip->ptm2ms)));
+ printk (" ptm2la\t0x%x\n", in_le32 (&(pcip->ptm2la)));
+
+#endif
+}
+#endif
+
+void __init board_io_mapping (void)
+{
+ ppc4xx_map_io ();
+}
+
+void __init board_setup_irq (void)
+{
+}
+
+void __init
+platform_init (unsigned long r3, unsigned long r4, unsigned long r5,
+ unsigned long r6, unsigned long r7)
+{
+ ppc4xx_init (r3, r4, r5, r6, r7);
+
+ ppc_md.setup_arch = board_setup_arch;
+ ppc_md.setup_io_mappings = board_io_mapping;
+
+#ifdef CONFIG_PPC_RTC
+ ppc_md.time_init = todc_time_init;
+ ppc_md.set_rtc_time = todc_set_rtc_time;
+ ppc_md.get_rtc_time = todc_get_rtc_time;
+ ppc_md.nvram_read_val = todc_direct_read_val;
+ ppc_md.nvram_write_val = todc_direct_write_val;
+#endif
+#ifdef CONFIG_KGDB
+ ppc_md.early_serial_map = ppchameleon_early_serial_map;
+#endif
+}
diff --git a/arch/ppc/platforms/4xx/ppchameleon.h b/arch/ppc/platforms/4xx/ppchameleon.h
new file mode 100644
--- /dev/null
+++ b/arch/ppc/platforms/4xx/ppchameleon.h
@@ -0,0 +1,145 @@
+/*
+ * Support for DAVE PPC 405EP evaluation board (PPChameleon).
+ *
+ * Author: Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
+ * derived from "Octobus hppc405" board by haag.cc
+ * (see http://www.haag.cc/downloads/files/octobus-hppc405-2.6.12.2-V0.1)
+ * which in turn was obviously based on evb405ep.
+ * Maintained by Wolfgang Denk, <wd@denx.de>
+ *
+ * 2005 (c) Wolfgang Denk, DENX Software Engineering. This file is
+ * licensed under the terms of the GNU General Public License version 2.
+ * This program is licensed "as is" without any warranty of any kind,
+ * whether express or implied.
+ */
+
+#ifdef __KERNEL__
+#ifndef __ASM_PPCHAMELEONEVB_H__
+#define __ASM_PPCHAMELEONEVB_H__
+
+/* 405EP */
+#include <platforms/4xx/ibm405ep.h>
+/*#include <asm/io.h>*/
+
+#include <asm/ppcboot.h>
+
+#ifndef __ASSEMBLY__
+
+/* Some 4xx parts use a different timebase frequency from the internal clock.
+*/
+#define bi_tbfreq bi_intfreq
+
+/* The UART clock is based off an internal clock -
+ * define BASE_BAUD based on the internal clock and divider(s).
+ * Since BASE_BAUD must be a constant, we will initialize it
+ * using clock/divider values which OpenBIOS initializes
+ * for typical configurations at various CPU speeds.
+ * The base baud is calculated as (FWDA / EXT UART DIV / 16)
+ */
+#define BASE_BAUD 0
+
+#define PPC4xx_MACHINE_NAME "DAVE PPChameleonEVB"
+
+/******************************************************************************
+ * Some internal regs are not defined elsewhere so we put 'em here *
+ ******************************************************************************/
+
+/**************/
+/* NAND stuff */
+/**************/
+/* Internal NAND */
+#define CFG_NAND0_PADDR ((uint)0xFF400000)
+#define CFG_NAND0_VADDR CFG_NAND0_PADDR
+#define CFG_NAND0_CE (0x80000000 >> 1) /* our CE is GPIO1 */
+#define CFG_NAND0_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
+#define CFG_NAND0_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
+#define CFG_NAND0_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
+/* External NAND */
+#define CFG_NAND1_PADDR 0xFF000000
+#define CFG_NAND1_VADDR CFG_NAND1_PADDR
+#define CFG_NAND1_CE (0x80000000 >> 14) /* our CE is GPIO14 */
+#define CFG_NAND1_CLE (0x80000000 >> 15) /* our CLE is GPIO15 */
+#define CFG_NAND1_ALE (0x80000000 >> 16) /* our ALE is GPIO16 */
+#define CFG_NAND1_RDY (0x80000000 >> 31) /* our RDY is GPIO31 */
+/* Macros to perform I/O operations */
+#define MACRO_NAND_DISABLE_CE(nandptr) do { \
+ switch((unsigned long)nandptr) { \
+ case CFG_NAND0_PADDR: \
+ out_be32((volatile unsigned*)GPIO0_OR, in_be32((volatile unsigned*)GPIO0_OR) | CFG_NAND0_CE); \
+ break; \
+ case CFG_NAND1_PADDR: \
+ out_be32((volatile unsigned*)GPIO0_OR, in_be32((volatile unsigned*)GPIO0_OR) | CFG_NAND1_CE); \
+ break; \
+ } \
+} while(0)
+
+#define MACRO_NAND_ENABLE_CE(nandptr) do { \
+ switch((unsigned long)nandptr) { \
+ case CFG_NAND0_PADDR: \
+ out_be32((volatile unsigned*)GPIO0_OR, in_be32((volatile unsigned*)GPIO0_OR) & ~CFG_NAND0_CE); \
+ break; \
+ case CFG_NAND1_PADDR: \
+ out_be32((volatile unsigned*)GPIO0_OR, in_be32((volatile unsigned*)GPIO0_OR) & ~CFG_NAND1_CE); \
+ break; \
+ } \
+} while(0)
+
+
+#define MACRO_NAND_CTL_CLRALE(nandptr) do { \
+ switch((unsigned long)nandptr) { \
+ case CFG_NAND0_PADDR: \
+ out_be32((volatile unsigned*)GPIO0_OR, in_be32((volatile unsigned*)GPIO0_OR) & ~CFG_NAND0_ALE); \
+ break; \
+ case CFG_NAND1_PADDR: \
+ out_be32((volatile unsigned*)GPIO0_OR, in_be32((volatile unsigned*)GPIO0_OR) & ~CFG_NAND1_ALE); \
+ break; \
+ } \
+} while(0)
+
+#define MACRO_NAND_CTL_SETALE(nandptr) do { \
+ switch((unsigned long)nandptr) { \
+ case CFG_NAND0_PADDR: \
+ out_be32((volatile unsigned*)GPIO0_OR, in_be32((volatile unsigned*)GPIO0_OR) | CFG_NAND0_ALE); \
+ break; \
+ case CFG_NAND1_PADDR: \
+ out_be32((volatile unsigned*)GPIO0_OR, in_be32((volatile unsigned*)GPIO0_OR) | CFG_NAND1_ALE); \
+ break; \
+ } \
+} while(0)
+
+#define MACRO_NAND_CTL_CLRCLE(nandptr) do { \
+ switch((unsigned long)nandptr) { \
+ case CFG_NAND0_PADDR: \
+ out_be32((volatile unsigned*)GPIO0_OR, in_be32((volatile unsigned*)GPIO0_OR) & ~CFG_NAND0_CLE); \
+ break; \
+ case CFG_NAND1_PADDR: \
+ out_be32((volatile unsigned*)GPIO0_OR, in_be32((volatile unsigned*)GPIO0_OR) & ~CFG_NAND1_CLE); \
+ break; \
+ } \
+} while(0)
+
+#define MACRO_NAND_CTL_SETCLE(nandptr) do { \
+ switch((unsigned long)nandptr) { \
+ case CFG_NAND0_PADDR: \
+ out_be32((volatile unsigned*)GPIO0_OR, in_be32((volatile unsigned*)GPIO0_OR) | CFG_NAND0_CLE); \
+ break; \
+ case CFG_NAND1_PADDR: \
+ out_be32((volatile unsigned*)GPIO0_OR, in_be32((volatile unsigned*)GPIO0_OR) | CFG_NAND1_CLE); \
+ break; \
+ } \
+} while(0)
+
+#define MACRO_NAND_WAIT_READY(nand) while { \
+ switch((unsigned long)(((struct nand_chip *)nand)->IO_ADDR)) { \
+ case CFG_NAND0_PADDR: \
+ !(in_be32((volatile unsigned*)GPIO0_IR) & CFG_NAND0_RDY); \
+ break; \
+ case CFG_NAND1_PADDR: \
+ !(in_be32((volatile unsigned*)GPIO0_IR) & CFG_NAND1_RDY); \
+ break; \
+ } \
+}
+
+#endif /* !__ASSEMBLY__ */
+#endif /* __ASM_PPCHAMELEONEVB_H__ */
+#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/ibm4xx.h b/include/asm-ppc/ibm4xx.h
--- a/include/asm-ppc/ibm4xx.h
+++ b/include/asm-ppc/ibm4xx.h
@@ -31,6 +31,10 @@
#include <platforms/4xx/ep405.h>
#endif
+#if defined(CONFIG_PPChameleonEVB)
+#include <platforms/4xx/ppchameleon.h>
+#endif
+
#if defined(CONFIG_REDWOOD_5)
#include <platforms/4xx/redwood5.h>
#endif
^ permalink raw reply
* SPI driver for AMCC 440EP
From: Rolf Offermanns @ 2005-10-12 15:47 UTC (permalink / raw)
To: linuxppc-embedded
Hi!
Does anyone have an SPI driver for the PPC440EP?
If not I am going to write one. In that case, what API would you suggest to
use.
I checked the archives (both LKML and linuxppc-embedded) for SPI API
discussions, but I am still not sure which way to go since all discussions
ended at some point without an agreement. I would like to see the driver
going into mainline someday, so please give me a hint about which way to
choose.
Thanks,
Rolf
--
Rolf Offermanns <roffermanns@sysgo.com>
SYSGO AG Tel.: +49-6136-9948-0
Am Pfaffenstein 14 Fax: +49-6136-9948-10
55270 Klein-Winternheim http://www.sysgo.com
^ permalink raw reply
* "PPC 405 MAL0 eth: receive descriptor error"
From: extabe @ 2005-10-12 17:00 UTC (permalink / raw)
To: linuxppc-embedded
Hi!
We have built a board based on AMCC 440ep and used bamboo as reference board. We are running montavista 2.4.20 kernel and have problems with the network.
After a while when using the network linux outputs this:
"PPC 405 MAL0 eth: receive descriptor error"
Searching the kernelsource shows that this output comes from
static void ppc405_eth_rxde(int irq, void *dev_instance, struct pt_regs *regs)
in drivers/net/ibm_ocp/ibm_ocp_enet.c
and the comment for this function is:
"This interrupt should be very rare at best. This occurs when
the hardware has a problem with the receive descriptors. The manual
states that it occurs when the hardware cannot the receive descriptor
empty bit is not set. The recovery mechanism will be to traverse through the descriptors, handle any that are marked to be
handled and reinitialize each along the way. At that point the driver
will be restarted."
Can anybody help me with this problem? After it occurs the system freezes for about 2 minutes.
We are using u-boot configured for bamboo with small modifications and the same goes for the kernel.
//Andre
^ permalink raw reply
* Re: "PPC 405 MAL0 eth: receive descriptor error"
From: Eugene Surovegin @ 2005-10-12 17:24 UTC (permalink / raw)
To: extabe; +Cc: linuxppc-embedded
In-Reply-To: <20051012170048.QRLV3110.mxfep03.bredband.com@mxfep03>
On Wed, Oct 12, 2005 at 07:00:48PM +0200, extabe@bredband.net wrote:
> We have built a board based on AMCC 440ep and used bamboo as reference board. We are running montavista 2.4.20 kernel and have problems with the network.
> After a while when using the network linux outputs this:
>
> "PPC 405 MAL0 eth: receive descriptor error"
>
> Searching the kernelsource shows that this output comes from
>
> static void ppc405_eth_rxde(int irq, void *dev_instance, struct pt_regs *regs)
>
> in drivers/net/ibm_ocp/ibm_ocp_enet.c
>
> and the comment for this function is:
>
> "This interrupt should be very rare at best. This occurs when
> the hardware has a problem with the receive descriptors. The manual
> states that it occurs when the hardware cannot the receive descriptor
> empty bit is not set. The recovery mechanism will be to traverse through the descriptors, handle any that are marked to be
> handled and reinitialize each along the way. At that point the driver
> will be restarted."
>
> Can anybody help me with this problem? After it occurs the system freezes for about 2 minutes.
>
Current EMAC driver (in both 2.4 and 2.6) is buggy. That comment is
actually misleading, because this IRQ can happen during normal
operation, e.g. under heavy packet load.
There is re-write available for both 2.4 and 2.6. You can find more
information at http://kernel.ebshome.net/.
2.4 patch is against 2.4.31, so you'll have to back port all required
stuff to 2.4.21.
--
Eugene
^ permalink raw reply
* Re: SRAM support for the Pegasos II platform
From: Dale Farnsworth @ 2005-10-12 18:22 UTC (permalink / raw)
To: Andrew Morton; +Cc: linuxppc-dev, sl, dholm, det.nicolas
In-Reply-To: <20051011135022.60ddfbbc.akpm@osdl.org>
On Tue, Oct 11, 2005 at 08:50:22PM +0000, Andrew Morton wrote:
> Nicolas DET <det.nicolas@free.fr> wrote:
> >
> > You can find enclosed or at the URL a patch for the 2.6.14-rc1.
> > http://arrakin.homedns.org/~nicolas/mv643xx_eth_chrp_pegasos_eth.c.2.6.14-rc1.diff
> >
> > It allows (with drivers/net/mv643xx_eth.*) to take advantage of the SRAM of
> > the Marvell Discovery II for the network driver.
>
> I've kind of lost the plot with what happened with this patch. Who is the
> maintainer of this driver, and has [s]he commented on this patch?
I'm the maintainer of the 2.6 mv643xx_eth driver. The only comment I had
(in http://ozlabs.org/pipermail/linuxppc-dev/2005-September/019764.html)
was that the define for PEGASOS2_SRAM_SIZE looks wrong. When that and
the whitespace/style issues are fixed, I'm OK with the change.
-Dale
^ permalink raw reply
* Re: ads8272 SEC problem on 2.4.18
From: Kim Phillips @ 2005-10-12 20:06 UTC (permalink / raw)
To: Vikas Aggarwal; +Cc: linuxppc-embedded
In-Reply-To: <1084.24.92.61.26.1126086971.squirrel@webmail.albany.edu>
okay, the devtech team has ported the 2.4 SEC driver to 2.6 (and finally fixed this issue). It is a direct port from the 2.4 driver - so whatever limitations exist in the 2.4 version will exist in this. It's available on the Codewarrior BSP site:
http://www.metrowerks.com/MW/Develop/Embedded/Linux/DownloadBSP.htm
Use the MPC8272ADS 2.6 Kernel link.
Kim
On Wed, 7 Sep 2005 05:56:11 -0400 (EDT)
"Vikas Aggarwal" <va824363@albany.edu> wrote:
> I had the similar error with SEC1 for 8248. My RNG DPD could not generate
> desired result. After DPD address written my ISR was invoked but all i had
> is TEA error, or bus error etc when i checked the Status Registers.
>
> regards
> -vikas
>
> > HiHo!
> >
> > I am trying to get the SEC engine running on a ads8272
> > but i am completely stuck now. (It feels like the problem
> > we saw on this list last month, but there is still no solution
> > to that issue yet.
> >
> > Quick Problem description:
> > initialize seems, ok, yet when i feed a single
> > dpd (for DES EU) into channel 0, the engine
> > seems to stuck during fetch. Nothing happens.
> >
> > Questions:
> > - Can someone help me out? (Not sure if this is the right list for this?)
> > - Do (open) sources for the SEC1 (motorola/freescale) engine exist for
> > vanilla linux?
> > (I know of Arabella, but they are neither open nor for vanilla linux)
> >
> > ciao
> > Markus
> >
> > P.S. some more details below
> > --------------------------------------------
> > more info:
> > - i hopefully initialized it correctly
> > - prepared a dpd
> > - wrote it into fetch register
> > - see that something happens: CurrentDescriptorPR changes
> > - boing, that's it... no more
> >
> > some dumps:
> > Before writing the fetch register:
> > CryptoChannelConfigRegister (f0042008), 0x00000000 0x0000071c
> > CryptoChannelPointerStatusRegister (f0042010), 0x00000000 0x00000007
> > CryptoChannelCurrentDescriptorPointerRegister (f0042040), 0x00000000
> > 0x00000000
> > CryptoChannelFetchDescriptorRegister (f0042048), 0x00000000 0x00000000
> > CryptoChannelDescriptorBufferRegister 0 (f0042080), 0x00000000
> >
> > after writing to fetch register
> > CryptoChannelConfigRegister (f0042008), 0x00000000 0x0000071c
> > CryptoChannelPointerStatusRegister (f0042010), 0x00000002 0x00000007
> > CryptoChannelCurrentDescriptorPointerRegister (f0042040), 0x00000000
> > 0x002e9a98
> > CryptoChannelFetchDescriptorRegister (f0042048), 0x00000000 0x00000000
> > CryptoChannelDescriptorBufferRegister 0 (f0042080), 0x00000000
> >
> > CCPSR changes to 2 (error), but i don't know why?
> > Nothing else (at least nothing i can see) happens.
> > ------------------------------------------------------
> > markus schaefer --- software engineer
> > epygi labs de gmbh
> > herrenstrasse 23
> > d-76133 karlsruhe, germany
> > tel: +49 (721) 205 96 30 -- fax: +49 (721) 205 96 59
> > sip: 20444@sip.epygi.com
> > *email removed, but it is easy to guess*
> > http://www.epygi.de
> >
> > _______________________________________________
> > Linuxppc-embedded mailing list
> > Linuxppc-embedded@ozlabs.org
> > https://ozlabs.org/mailman/listinfo/linuxppc-embedded
> >
>
>
> _______________________________________________
> Linuxppc-embedded mailing list
> Linuxppc-embedded@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-embedded
--
^ permalink raw reply
* Re: init process not running
From: Shawn Jin @ 2005-10-12 20:40 UTC (permalink / raw)
To: Nathael PAJANI; +Cc: linuxppc-embedded
In-Reply-To: <434CDF76.3080705@cpe.fr>
What about your UART driver and interrupt controller? I had such
experience before and it turned out to be a problem in interrupt
controller driver. The serial driver uses interrupt mode to operate
UART once init gets called.
Just my 2 cents.
-Shawn.
^ permalink raw reply
* [PATCH] Oprofile backtrace support for e500
From: Andy Fleming @ 2005-10-12 22:37 UTC (permalink / raw)
To: Oprofile List; +Cc: linuxppc-embedded
Signed-off-by Andy Fleming <afleming@freescale.com>
* Added support for callgraphs (ie backtracing)
---
commit f3bcff9f931bdd36e8cd527408418ed5f3f7a85b
tree d08362251f25801221ff2c71e0371757b1fc49d0
parent 3294b2b37eb56ee4ad287776998293485a7c122e
author Andrew Fleming <afleming@freescale.com> Wed, 12 Oct 2005 16:09:23 -0500
committer Andrew Fleming <afleming@freescale.com> Wed, 12 Oct 2005 16:09:23 -0500
arch/ppc/oprofile/Makefile | 2 -
arch/ppc/oprofile/backtrace.c | 126 ++++++++++++++++++++++++++++++++
arch/ppc/oprofile/common.c | 6 +-
arch/ppc/oprofile/op_model_fsl_booke.c | 7 --
4 files changed, 133 insertions(+), 8 deletions(-)
diff --git a/arch/ppc/oprofile/Makefile b/arch/ppc/oprofile/Makefile
--- a/arch/ppc/oprofile/Makefile
+++ b/arch/ppc/oprofile/Makefile
@@ -6,7 +6,7 @@ DRIVER_OBJS := $(addprefix ../../../driv
oprofilefs.o oprofile_stats.o \
timer_int.o )
-oprofile-y := $(DRIVER_OBJS) common.o
+oprofile-y := $(DRIVER_OBJS) common.o backtrace.o
ifeq ($(CONFIG_FSL_BOOKE),y)
oprofile-y += op_model_fsl_booke.o
diff --git a/arch/ppc/oprofile/backtrace.c b/arch/ppc/oprofile/backtrace.c
new file mode 100644
--- /dev/null
+++ b/arch/ppc/oprofile/backtrace.c
@@ -0,0 +1,126 @@
+/*
+ * PPC 32 oprofile support
+ * Based on PPC64 oprofile backtrace support
+ * Copyright (C) 2005 Brian Rogan <bcr6@cornell.edu>, IBM
+ *
+ * Copyright (C) Freescale Semiconductor, Inc 2005
+ *
+ * Author: Andy Fleming
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include <linux/oprofile.h>
+#include <linux/sched.h>
+#include <asm/processor.h>
+#include <asm/uaccess.h>
+
+static unsigned int user_putsp32(unsigned int sp, int *is_first) {
+ unsigned int stack_frame[2], rv;
+ unsigned long t = sp;
+
+ /* If the page isn't accessible, then we've done all that we can do,
+ * a partial stack trace is better than none.
+ */
+ rv = __copy_from_user_inatomic(stack_frame, (void *) t, sizeof(stack_frame));
+ if(rv != 0) {
+ /* The most likely reason for this is that we returned -EFAULT,
+ * which means that we've done all that we can do from interrupt
+ * context. All other errors though are equally valid reasons to
+ * abort our backtrace. */
+ return 0;
+ }
+
+
+ /* SVR4 compliant executables have the Link Register offset by 4 bytes
+ * from the beginning of the stack page */
+ //printk("Link was: %p\n", stack_frame[1]);
+ if(! *is_first) {
+ oprofile_add_trace(stack_frame[1]);
+ } else {
+ *is_first = 0;
+ }
+
+ /* Sanity check to make sure that the previous stack frame is actually above
+ * us in memory, like we would expect it to be from the PPC spec.
+ *
+ * The last stack pointer is always at offset 0 from the beginning of the
+ * stack frame.
+ */
+ rv = stack_frame[0];
+ if(rv > sp) {
+ return rv;
+ } else {
+ return 0;
+ }
+}
+
+static int validate_sp(unsigned long sp)
+{
+ unsigned long prev_sp;
+ unsigned long stack_top;
+
+ prev_sp = (unsigned long) (current->thread_info + 1);
+ stack_top = (unsigned long) current->thread_info + THREAD_SIZE;
+
+ if (sp > prev_sp && sp < stack_top && (sp & 3) == 0)
+ return 1;
+
+ return 0;
+}
+
+static unsigned long kernel_putsp32(unsigned long sp, int *is_first) {
+ unsigned long * stack_frame = (unsigned long *) sp;
+ unsigned long rv;
+
+ if(!validate_sp(sp)) {
+ return 0;
+ }
+
+ //printk("Link was: %p\n", stack_frame[1]);
+ if(! *is_first) {
+ /* Same as before LR is offset 4 bytes from the beginning */
+ oprofile_add_trace(stack_frame[1]);
+ } else {
+ *is_first = 0;
+ }
+
+ rv = stack_frame[0];
+ if(rv > sp) {
+ return rv;
+ } else {
+ return 0;
+ }
+}
+
+
+void
+op_ppc32_backtrace(struct pt_regs * const regs, unsigned int depth)
+{
+ unsigned long cursp = regs->gpr[1];
+ int first_frame = 1;
+
+ //printk("backtracing\n");
+ if (!user_mode(regs)) {
+ unsigned long sp = cursp;
+ while (depth--)
+ {
+ sp = kernel_putsp32(sp, &first_frame);
+ if(!sp) {
+ break;
+ }
+ }
+ return;
+ } else {
+ unsigned long sp = cursp;
+ while(depth--) {
+ sp = user_putsp32(sp, &first_frame);
+ if(!sp) {
+ break;
+ }
+ }
+ }
+}
diff --git a/arch/ppc/oprofile/common.c b/arch/ppc/oprofile/common.c
--- a/arch/ppc/oprofile/common.c
+++ b/arch/ppc/oprofile/common.c
@@ -84,6 +84,9 @@ static void op_ppc32_stop(void)
on_each_cpu(op_ppc32_cpu_stop, NULL, 0, 1);
}
+extern void
+op_ppc32_backtrace(struct pt_regs * const regs, unsigned int depth);
+
static int op_ppc32_create_files(struct super_block *sb, struct dentry *root)
{
int i;
@@ -121,7 +124,8 @@ static struct oprofile_operations oprof_
.shutdown = op_ppc32_shutdown,
.start = op_ppc32_start,
.stop = op_ppc32_stop,
- .cpu_type = NULL /* To be filled in below. */
+ .cpu_type = NULL, /* To be filled in below. */
+ .backtrace = op_ppc32_backtrace,
};
int __init oprofile_arch_init(struct oprofile_operations *ops)
diff --git a/arch/ppc/oprofile/op_model_fsl_booke.c b/arch/ppc/oprofile/op_model_fsl_booke.c
--- a/arch/ppc/oprofile/op_model_fsl_booke.c
+++ b/arch/ppc/oprofile/op_model_fsl_booke.c
@@ -146,22 +146,17 @@ static void fsl_booke_stop(void)
static void fsl_booke_handle_interrupt(struct pt_regs *regs,
struct op_counter_config *ctr)
{
- unsigned long pc;
- int is_kernel;
int val;
int i;
/* set the PMM bit (see comment below) */
mtmsr(mfmsr() | MSR_PMM);
- pc = regs->nip;
- is_kernel = (pc >= KERNELBASE);
-
for (i = 0; i < num_counters; ++i) {
val = ctr_read(i);
if (val < 0) {
if (oprofile_running && ctr[i].enabled) {
- oprofile_add_pc(pc, is_kernel, i);
+ oprofile_add_sample(regs, i);
ctr_write(i, reset_value[i]);
} else {
ctr_write(i, 0);
* Removed commented code
---
commit 7f50cb2cd6153dda4d999b13418dd8e3609def5c
tree 47ddd0af393ee7cb8dfa911fe5c3d383865fc217
parent f3bcff9f931bdd36e8cd527408418ed5f3f7a85b
author Andrew Fleming <afleming@freescale.com> Wed, 12 Oct 2005 16:12:05 -0500
committer Andrew Fleming <afleming@freescale.com> Wed, 12 Oct 2005 16:12:05 -0500
arch/ppc/oprofile/backtrace.c | 3 ---
1 files changed, 0 insertions(+), 3 deletions(-)
diff --git a/arch/ppc/oprofile/backtrace.c b/arch/ppc/oprofile/backtrace.c
--- a/arch/ppc/oprofile/backtrace.c
+++ b/arch/ppc/oprofile/backtrace.c
@@ -37,7 +37,6 @@ static unsigned int user_putsp32(unsigne
/* SVR4 compliant executables have the Link Register offset by 4 bytes
* from the beginning of the stack page */
- //printk("Link was: %p\n", stack_frame[1]);
if(! *is_first) {
oprofile_add_trace(stack_frame[1]);
} else {
@@ -80,7 +79,6 @@ static unsigned long kernel_putsp32(unsi
return 0;
}
- //printk("Link was: %p\n", stack_frame[1]);
if(! *is_first) {
/* Same as before LR is offset 4 bytes from the beginning */
oprofile_add_trace(stack_frame[1]);
@@ -103,7 +101,6 @@ op_ppc32_backtrace(struct pt_regs * cons
unsigned long cursp = regs->gpr[1];
int first_frame = 1;
- //printk("backtracing\n");
if (!user_mode(regs)) {
unsigned long sp = cursp;
while (depth--)
^ permalink raw reply
* MPC7447A based board with MV64462 Marvell Discovery III controller
From: Ashish Bijlani @ 2005-10-13 7:42 UTC (permalink / raw)
To: linuxppc-embedded
[-- Attachment #1: Type: text/plain, Size: 465 bytes --]
Hi,
I'm trying to bring MPC7447A based board with MV64462 Marvell Discovery III
controller up. Can you guide me to Linux-2.6 sources with support for
MV64462 Marvell Discovery III controller and MPC7447A PowerPC processor.
Support for I2c, dual 10/100/1000 ethernet ports, and relevant platform
should be there. I cannot access the bit keeper repositories so please guide
me to the linux-2.6 kernel source tree if you can.
Thanks in advance.
-Ashish
[-- Attachment #2: Type: text/html, Size: 529 bytes --]
^ permalink raw reply
* NPTL support on PPC
From: David Ho @ 2005-10-13 14:20 UTC (permalink / raw)
To: linuxppc-embedded
[-- Attachment #1: Type: text/plain, Size: 293 bytes --]
Hi all,
Just out of curiosity, is NPTL support already available on PPC?
I believe there are 2 parts to it. Kernel support which is probably already
there in 2.6. And the other is glibc, is there a generally available
toolchain (i.e. ELDK) that already support NPTL?
Thanks, David
[-- Attachment #2: Type: text/html, Size: 333 bytes --]
^ permalink raw reply
* Re: NPTL support on PPC
From: David Ho @ 2005-10-13 14:25 UTC (permalink / raw)
To: linuxppc-embedded
In-Reply-To: <4dd15d180510130720m45089eafk10cd9936457ced8b@mail.gmail.com>
[-- Attachment #1: Type: text/plain, Size: 1250 bytes --]
glibc used on ELDK 3.0 is still using linuxthreads.
David
bash-2.05# ./libc.so.6
GNU C Library stable release version 2.3.1, by Roland McGrath et al.
Copyright (C) 2003 Free Software Foundation, Inc.
This is free software; see the source for copying conditions.
There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A
PARTICULAR PURPOSE.
Compiled by GNU CC version 3.2.2 20030217 (Yellow Dog Linux 3.0 3.2.2-2a_1).
Compiled on a Linux 2.4.24-pre2 system on 2004-02-17.
Available extensions:
GNU libio by Per Bothner
crypt add-on version 2.1 by Michael Glad and others
linuxthreads-0.10 by Xavier Leroy
BIND-8.2.3-T5B
libthread_db work sponsored by Alpha Processor Inc
NIS(YP)/NIS+ NSS modules 0.19 by Thorsten Kukuk
software FPU emulation by Richard Henderson, Jakub Jelinek and others
Report bugs using the `glibcbug' script to <bugs@gnu.org>.
On 10/13/05, David Ho <davidkwho@gmail.com> wrote:
>
> Hi all,
>
> Just out of curiosity, is NPTL support already available on PPC?
>
> I believe there are 2 parts to it. Kernel support which is probably
> already there in 2.6. And the other is glibc, is there a generally
> available toolchain (i.e. ELDK) that already support NPTL?
>
> Thanks, David
>
[-- Attachment #2: Type: text/html, Size: 1971 bytes --]
^ permalink raw reply
* Re: NPTL support on PPC
From: Gerhard Jaeger @ 2005-10-13 14:52 UTC (permalink / raw)
To: linuxppc-embedded; +Cc: David Ho
In-Reply-To: <4dd15d180510130725o3c23326i6f9703015401a381@mail.gmail.com>
On Thursday 13 October 2005 16:25, David Ho wrote:
> glibc used on ELDK 3.0 is still using linuxthreads.
>
> David
>
> bash-2.05# ./libc.so.6
> GNU C Library stable release version 2.3.1, by Roland McGrath et al.
> Copyright (C) 2003 Free Software Foundation, Inc.
> This is free software; see the source for copying conditions.
> There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A
> PARTICULAR PURPOSE.
> Compiled by GNU CC version 3.2.2 20030217 (Yellow Dog Linux 3.0 3.2.2-2a_1).
> Compiled on a Linux 2.4.24-pre2 system on 2004-02-17.
> Available extensions:
> GNU libio by Per Bothner
> crypt add-on version 2.1 by Michael Glad and others
> linuxthreads-0.10 by Xavier Leroy
> BIND-8.2.3-T5B
> libthread_db work sponsored by Alpha Processor Inc
> NIS(YP)/NIS+ NSS modules 0.19 by Thorsten Kukuk
> software FPU emulation by Richard Henderson, Jakub Jelinek and others
> Report bugs using the `glibcbug' script to <bugs@gnu.org>.
>
>
> On 10/13/05, David Ho <davidkwho@gmail.com> wrote:
> >
> > Hi all,
> >
> > Just out of curiosity, is NPTL support already available on PPC?
> >
> > I believe there are 2 parts to it. Kernel support which is probably
> > already there in 2.6. And the other is glibc, is there a generally
> > available toolchain (i.e. ELDK) that already support NPTL?
> >
> > Thanks, David
Yes it's available! you might want to checkout the work done around
the crosstool project (http://www.kegel.com/crosstool) or check my
sig ;)
-/bin/sh-3.00# /lib/tls/libc.so.6
GNU C Library stable release version 2.3.4, by Roland McGrath et al.
Copyright (C) 2004 Free Software Foundation, Inc.
This is free software; see the source for copying conditions.
There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A
PARTICULAR PURPOSE.
Compiled by GNU CC version 3.4.4.
Compiled on a Linux 2.6.12.6-elinos-214 system on 2005-09-28.
Available extensions:
GNU libio by Per Bothner
crypt add-on version 2.1 by Michael Glad and others
Native POSIX Threads Library by Ulrich Drepper et al
BIND-8.2.3-T5B
NIS(YP)/NIS+ NSS modules 0.19 by Thorsten Kukuk
software FPU emulation by Richard Henderson, Jakub Jelinek and others
Thread-local storage support included.
Ciao,
Gerhard
--
Gerhard Jaeger <gjaeger@sysgo.com>
SYSGO AG Embedded and Real-Time Software
www.sysgo.com | www.elinos.com | www.pikeos.com | www.osek.de
^ permalink raw reply
* network driver over shared memory
From: gaashpub-lnx @ 2005-10-13 17:09 UTC (permalink / raw)
To: linuxppc-embedded; +Cc: gaashpub-lnx
Experts,
Hope this is not a too dumb question.
I have an embedded system with a few PPCs, one master
and a few slaves. All PPCs are interconnected with
shared memory over PCI.
I would like to create and IP or "Ethernet like"
network between all the PPCs to enable files transfer
over FTP or NFS between the master and the slaves.
Is there a network driver for this in 2.6 kernel. If
not any idea where to look for or with what to begin
with.
PS: Please put my email in the reply as I'm not member
of this list (yet)
Thanks
Gaash
^ permalink raw reply
* Re: MPC7447A based board with MV64462 Marvell Discovery III controller
From: Mark A. Greer @ 2005-10-13 18:26 UTC (permalink / raw)
To: Ashish Bijlani; +Cc: linuxppc-embedded
In-Reply-To: <ec55b17e0510130042m6c6c0c43ndf09f40a03f9cf97@mail.gmail.com>
On Thu, Oct 13, 2005 at 01:12:19PM +0530, Ashish Bijlani wrote:
> Hi,
>
> I'm trying to bring MPC7447A based board with MV64462 Marvell Discovery III
> controller up. Can you guide me to Linux-2.6 sources with support for
> MV64462 Marvell Discovery III controller and MPC7447A PowerPC processor.
> Support for I2c, dual 10/100/1000 ethernet ports, and relevant platform
> should be there. I cannot access the bit keeper repositories so please guide
> me to the linux-2.6 kernel source tree if you can.
Ashish,
Support for both the 7447A and mv64x6x is in the latest 2.6 mainline
kernel source at kernel.org.
If your board is a chrp/openfirmware board, then you probably want to use
the Pegasos code as an example. If your board has U-boot or some other
non-OF firmware, then use the katana or chestnut as an example (katana
is more up-to-date than the chestnut). The ev64360 code may help too.
There are i2c and enet drivers (and mpsc and wdt) in that source as well.
Note that I've never had a 64462 to test with. Since the '2' means it
has less functionality than the '0', you may run into some problems.
If you do, please let me know what they are.
Mark
^ permalink raw reply
* What is OCP_FUNC_OPB ??
From: Roland Dreier @ 2005-10-13 20:05 UTC (permalink / raw)
To: linuxppc-embedded, mporter
While merging Ruslan Sushko's fix for GPIO and IIC addresses into my
440SPe tree, I noticed that ocp_core[] has an entry for a function
OCP_FUNC_OPB. I'd like to get this correct for the 440SPe port, but I
don't see any users in the tree.
Is this field just used to create an entry in sysfs -- if so what does
userspace use it for?? Or is it just completely obsolete? What is
the .paddr member supposed to represent? Is it just the base address
of the whole OPB region?
Is it worth applying the patch below (according to the 440SP manual,
the OPB region starts at 0x1 f000 0000), or should we just get rid of
these entries entirely?
Thanks,
Roland
[PPC32] Correct OPB base address for PowerPC 440SP
Signed-off-by: Roland Dreier <rolandd@cisco.com>
---
diff --git a/arch/ppc/platforms/4xx/ibm440sp.c b/arch/ppc/platforms/4xx/ibm440sp.c
index feb17e4..0b7e462 100644
--- a/arch/ppc/platforms/4xx/ibm440sp.c
+++ b/arch/ppc/platforms/4xx/ibm440sp.c
@@ -60,7 +60,7 @@ struct ocp_def core_ocp[] = {
{ .vendor = OCP_VENDOR_IBM,
.function = OCP_FUNC_OPB,
.index = 0,
- .paddr = 0x0000000140000000ULL,
+ .paddr = 0x00000001f0000000ULL,
.irq = OCP_IRQ_NA,
.pm = OCP_CPM_NA,
},
^ permalink raw reply related
* [PATCH 2.6.14-rc3 1/1] chrp_pegasos_eth: Added Marvell Discovery II SRAM support
From: Nicolas DET @ 2005-10-13 20:00 UTC (permalink / raw)
To: Sven Luther, Andrew Morton, linuxppc-dev
[-- Attachment #1: Type: text/plain, Size: 183 bytes --]
Added proper entry to support the Marvell MV64361 (Marvell Discovery II)
SRAM.
This feature may be used by the mv643xx_eth driver.
Signed-off-by: Nicolas DET <det.nicolas@free.fr)
[-- Attachment #2: chrp_pegasos_eth.2.6.14-rc4.patch --]
[-- Type: text/x-patch, Size: 5110 bytes --]
diff -ur a/arch/ppc/platforms/chrp_pegasos_eth.c b/arch/ppc/platforms/chrp_pegasos_eth.c
--- a/arch/ppc/platforms/chrp_pegasos_eth.c 2005-10-13 21:19:46.590643250 +0200
+++ b/arch/ppc/platforms/chrp_pegasos_eth.c 2005-10-13 21:29:54.976665000 +0200
@@ -17,6 +17,21 @@
#include <linux/mv643xx.h>
#include <linux/pci.h>
+// Pegasos II location and size for the SRAM stuff
+// Only used for the ethernet driver ATM
+#define PEGASOS2_MARVELL_REGBASE (0xf1000000)
+#define PEGASOS2_MARVELL_REGSIZE (0x00004000)
+#define PEGASOS2_SRAM_BASE (0xf2000000)
+#define PEGASOS2_SRAM_SIZE (0x00040000)
+
+#define PEGASOS2_SRAM_BASE_ETH0 (PEGASOS2_SRAM_BASE)
+#define PEGASOS2_SRAM_BASE_ETH1 (PEGASOS2_SRAM_BASE_ETH0 + (PEGASOS2_SRAM_SIZE / 2) )
+
+#define PEGASOS2_SRAM_RXRING_SIZE (PEGASOS2_SRAM_SIZE/4)
+#define PEGASOS2_SRAM_TXRING_SIZE (PEGASOS2_SRAM_SIZE/4)
+
+#undef BE_VERBOSE
+
/* Pegasos 2 specific Marvell MV 64361 gigabit ethernet port setup */
static struct resource mv643xx_eth_shared_resources[] = {
[0] = {
@@ -44,7 +59,15 @@
},
};
-static struct mv643xx_eth_platform_data eth0_pd;
+static struct mv643xx_eth_platform_data eth0_pd = {
+ .tx_sram_addr = PEGASOS2_SRAM_BASE_ETH0,
+ .tx_sram_size = PEGASOS2_SRAM_TXRING_SIZE,
+ .tx_queue_size = PEGASOS2_SRAM_TXRING_SIZE/16,
+
+ .rx_sram_addr = PEGASOS2_SRAM_BASE + PEGASOS2_SRAM_TXRING_SIZE,
+ .rx_sram_size = PEGASOS2_SRAM_RXRING_SIZE,
+ .rx_queue_size = PEGASOS2_SRAM_RXRING_SIZE/16,
+};
static struct platform_device eth0_device = {
.name = MV643XX_ETH_NAME,
@@ -65,7 +88,15 @@
},
};
-static struct mv643xx_eth_platform_data eth1_pd;
+static struct mv643xx_eth_platform_data eth1_pd = {
+ .tx_sram_addr = PEGASOS2_SRAM_BASE_ETH1,
+ .tx_sram_size = PEGASOS2_SRAM_TXRING_SIZE,
+ .tx_queue_size = PEGASOS2_SRAM_TXRING_SIZE/16,
+
+ .rx_sram_addr = PEGASOS2_SRAM_BASE_ETH1 + PEGASOS2_SRAM_TXRING_SIZE,
+ .rx_sram_size = PEGASOS2_SRAM_RXRING_SIZE,
+ .rx_queue_size = PEGASOS2_SRAM_RXRING_SIZE/16,
+};
static struct platform_device eth1_device = {
.name = MV643XX_ETH_NAME,
@@ -83,19 +114,111 @@
ð1_device,
};
+/***********/
+/***********/
+#define MV_READ(offset,val) { val = readl(mv643xx_reg_base + offset); }
+#define MV_WRITE(offset,data) writel(data, mv643xx_reg_base + offset)
+
+static void __iomem *mv643xx_reg_base = NULL;
-int
-mv643xx_eth_add_pds(void)
+
+static int Enable_SRAM(void)
+{
+ u32 ALong;
+
+ // Let's io remap the mv register to touch the SRAM config
+ if (mv643xx_reg_base == NULL)
+ mv643xx_reg_base = ioremap(PEGASOS2_MARVELL_REGBASE, PEGASOS2_MARVELL_REGSIZE);
+
+ if (mv643xx_reg_base == NULL)
+ return -ENOMEM;
+
+#ifdef BE_VERBOSE
+ printk("Pegasos II/Marvell MV64361: register remapped from %p to %p\n", (void *)PEGASOS2_MARVELL_REGBASE, (void *)mv643xx_reg_base);
+#endif
+
+ // First the SRAM config register
+ // We set it to 0 ATM -> No cache coherency, no parity check
+ MV_WRITE(MV64340_SRAM_CONFIG, 0);
+
+ // set the SRAM address on the CPU side
+ MV_WRITE(MV64340_INTEGRATED_SRAM_BASE_ADDR, PEGASOS2_SRAM_BASE >> 16);
+
+ // Now enable it (CPU side)
+ MV_READ(MV64340_BASE_ADDR_ENABLE, ALong);
+ ALong &= ~(1 << 19);
+ MV_WRITE(MV64340_BASE_ADDR_ENABLE, ALong);
+
+ // And now to the GB side on WB 4 (0->3) can be use for DRAM stuff
+ ALong = 0x02; // Integrated SRAM value
+ ALong |= PEGASOS2_SRAM_BASE & 0xffff0000; // Finally set the SRAM adress in the uppter par of the register
+ MV_WRITE(MV643XX_ETH_BAR_4, ALong);
+
+ // and the size ...
+ MV_WRITE(MV643XX_ETH_SIZE_REG_4, PEGASOS2_SRAM_SIZE & 0xffff0000);
+
+ // Finaly enable the window
+ MV_READ(MV643XX_ETH_BASE_ADDR_ENABLE_REG, ALong);
+ ALong &= ~(1 << 4);
+ MV_WRITE(MV643XX_ETH_BASE_ADDR_ENABLE_REG, ALong);
+
+#ifdef BE_VERBOSE
+ printk("Pegasos II/Marvell MV64361: register unmapped\n");
+ printk("Pegasos II/Marvell MV64361: SRAM at %p, size=%x\n", (void*) PEGASOS2_SRAM_BASE, PEGASOS2_SRAM_SIZE);
+#endif
+
+ iounmap(mv643xx_reg_base);
+ mv643xx_reg_base = NULL;
+
+ return 1;
+}
+
+
+/***********/
+/***********/
+int mv643xx_eth_add_pds(void)
{
int ret = 0;
- static struct pci_device_id pci_marvell_mv64360[] = {
+ static struct pci_device_id pci_marvell_mv64360[] =
+ {
{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_MV64360) },
{ }
};
- if (pci_dev_present(pci_marvell_mv64360)) {
+#ifdef BE_VERBOSE
+ printk("Pegasos II/Marvell MV64361: init\n");
+#endif
+
+ if (pci_dev_present(pci_marvell_mv64360))
+ {
ret = platform_add_devices(mv643xx_eth_pd_devs, ARRAY_SIZE(mv643xx_eth_pd_devs));
+
+ if ( Enable_SRAM() < 0)
+ {
+ // Humm, disable SRAM stuff
+ eth0_pd.tx_sram_addr = 0;
+ eth0_pd.tx_sram_size = 0;
+ eth0_pd.rx_sram_addr = 0;
+ eth0_pd.rx_sram_size = 0;
+
+ eth1_pd.tx_sram_addr = 0;
+ eth1_pd.tx_sram_size = 0;
+ eth1_pd.rx_sram_addr = 0;
+ eth1_pd.rx_sram_size = 0;
+
+#ifdef BE_VERBOSE
+ printk("Pegasos II/Marvell MV64361: Can't enable the SRAM\n");
+#endif
+ }
}
+
+#ifdef BE_VERBOSE
+
+ printk("Pegasos II/Marvell MV64361: init is over\n");
+#endif
+
return ret;
}
+
device_initcall(mv643xx_eth_add_pds);
+
^ permalink raw reply
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox