* [patch 11/43] Add modalias for pmac network drivers
From: akpm @ 2005-10-29 0:46 UTC (permalink / raw)
To: paulus; +Cc: akpm, linuxppc-dev, olh, linuxppc64-dev
From: Olaf Hering <olh@suse.de>
mesh, mac53c94 and airport already have an entry. Add the network drivers
for pmac.
Signed-off-by: Olaf Hering <olh@suse.de>
Cc: Paul Mackerras <paulus@samba.org>
Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
---
drivers/net/bmac.c | 1 +
drivers/net/mace.c | 1 +
2 files changed, 2 insertions(+)
diff -puN drivers/net/bmac.c~add-modalias-for-pmac-network-drivers drivers/net/bmac.c
--- devel/drivers/net/bmac.c~add-modalias-for-pmac-network-drivers 2005-10-28 17:44:03.000000000 -0700
+++ devel-akpm/drivers/net/bmac.c 2005-10-28 17:44:03.000000000 -0700
@@ -1658,6 +1658,7 @@ static struct of_device_id bmac_match[]
},
{},
};
+MODULE_DEVICE_TABLE (of, bmac_match);
static struct macio_driver bmac_driver =
{
diff -puN drivers/net/mace.c~add-modalias-for-pmac-network-drivers drivers/net/mace.c
--- devel/drivers/net/mace.c~add-modalias-for-pmac-network-drivers 2005-10-28 17:44:03.000000000 -0700
+++ devel-akpm/drivers/net/mace.c 2005-10-28 17:44:03.000000000 -0700
@@ -1016,6 +1016,7 @@ static struct of_device_id mace_match[]
},
{},
};
+MODULE_DEVICE_TABLE (of, mace_match);
static struct macio_driver mace_driver =
{
_
^ permalink raw reply
* [patch 10/43] Add modalias to macio sysfs attributes
From: akpm @ 2005-10-29 0:46 UTC (permalink / raw)
To: paulus; +Cc: akpm, scwhab, linuxppc-dev, olh, linuxppc64-dev
From: <scwhab@suse.de>
Provide a "compatible" entry in /sys/bus/macio/devices/*/ This can be used
to load drivers via the modules.alias file.
Signed-off-by: Olaf Hering <olh@suse.de>
Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Paul Mackerras <paulus@samba.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
---
drivers/macintosh/macio_sysfs.c | 26 ++++++++++++++++++++++++++
1 files changed, 26 insertions(+)
diff -puN drivers/macintosh/macio_sysfs.c~add-modalias-to-macio-sysfs-attributes drivers/macintosh/macio_sysfs.c
--- devel/drivers/macintosh/macio_sysfs.c~add-modalias-to-macio-sysfs-attributes 2005-10-28 17:44:03.000000000 -0700
+++ devel-akpm/drivers/macintosh/macio_sysfs.c 2005-10-28 17:44:03.000000000 -0700
@@ -39,6 +39,31 @@ compatible_show (struct device *dev, str
return length;
}
+static ssize_t modalias_show (struct device *dev, struct device_attribute *attr,
+ char *buf)
+{
+ struct of_device *of;
+ char *compat;
+ int cplen;
+ int length;
+
+ of = &to_macio_device (dev)->ofdev;
+ compat = (char *) get_property (of->node, "compatible", &cplen);
+ if (!compat) compat = "", cplen = 1;
+ length = sprintf (buf, "of:N%sT%s", of->node->name, of->node->type);
+ buf += length;
+ while (cplen > 0) {
+ int l;
+ length += sprintf (buf, "C%s", compat);
+ buf += length;
+ l = strlen (compat) + 1;
+ compat += l;
+ cplen -= l;
+ }
+
+ return length;
+}
+
macio_config_of_attr (name, "%s\n");
macio_config_of_attr (type, "%s\n");
@@ -46,5 +71,6 @@ struct device_attribute macio_dev_attrs[
__ATTR_RO(name),
__ATTR_RO(type),
__ATTR_RO(compatible),
+ __ATTR_RO(modalias),
__ATTR_NULL
};
_
^ permalink raw reply
* [patch 09/43] ppc32: nvram driver for chrp
From: akpm @ 2005-10-29 0:46 UTC (permalink / raw)
To: paulus; +Cc: akpm, linuxppc-dev, olh, linuxppc64-dev
From: Olaf Hering <olh@suse.de>
This implements a nvram acccess method, similar to
arch/ppc64/kernel/pSeries_nvram.c tested on CHRP B50.
Signed-off-by: Olaf Hering <olh@suse.de>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Paul Mackerras <paulus@samba.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
---
arch/ppc/platforms/Makefile | 3 +
arch/ppc/platforms/chrp_nvram.c | 83 ++++++++++++++++++++++++++++++++++++++++
arch/ppc/platforms/chrp_setup.c | 3 -
include/asm-ppc/system.h | 1
4 files changed, 88 insertions(+), 2 deletions(-)
diff -puN /dev/null arch/ppc/platforms/chrp_nvram.c
--- /dev/null 2003-09-15 06:40:47.000000000 -0700
+++ devel-akpm/arch/ppc/platforms/chrp_nvram.c 2005-10-28 17:44:02.000000000 -0700
@@ -0,0 +1,83 @@
+/*
+ * c 2001 PPC 64 Team, IBM Corp
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ *
+ * /dev/nvram driver for PPC
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+#include <asm/uaccess.h>
+#include <asm/prom.h>
+#include <asm/machdep.h>
+
+static unsigned int nvram_size;
+static unsigned char nvram_buf[4];
+static DEFINE_SPINLOCK(nvram_lock);
+
+static unsigned char chrp_nvram_read(int addr)
+{
+ unsigned long done, flags;
+ unsigned char ret;
+
+ if (addr >= nvram_size) {
+ printk(KERN_DEBUG "%s: read addr %d > nvram_size %u\n",
+ current->comm, addr, nvram_size);
+ return 0xff;
+ }
+ spin_lock_irqsave(&nvram_lock, flags);
+ if ((call_rtas("nvram-fetch", 3, 2, &done, addr, __pa(nvram_buf), 1) != 0) || 1 != done)
+ ret = 0xff;
+ else
+ ret = nvram_buf[0];
+ spin_unlock_irqrestore(&nvram_lock, flags);
+
+ return ret;
+}
+
+static void chrp_nvram_write(int addr, unsigned char val)
+{
+ unsigned long done, flags;
+
+ if (addr >= nvram_size) {
+ printk(KERN_DEBUG "%s: write addr %d > nvram_size %u\n",
+ current->comm, addr, nvram_size);
+ return;
+ }
+ spin_lock_irqsave(&nvram_lock, flags);
+ nvram_buf[0] = val;
+ if ((call_rtas("nvram-store", 3, 2, &done, addr, __pa(nvram_buf), 1) != 0) || 1 != done)
+ printk(KERN_DEBUG "rtas IO error storing 0x%02x at %d", val, addr);
+ spin_unlock_irqrestore(&nvram_lock, flags);
+}
+
+void __init chrp_nvram_init(void)
+{
+ struct device_node *nvram;
+ unsigned int *nbytes_p, proplen;
+
+ nvram = of_find_node_by_type(NULL, "nvram");
+ if (nvram == NULL)
+ return;
+
+ nbytes_p = (unsigned int *)get_property(nvram, "#bytes", &proplen);
+ if (nbytes_p == NULL || proplen != sizeof(unsigned int))
+ return;
+
+ nvram_size = *nbytes_p;
+
+ printk(KERN_INFO "CHRP nvram contains %u bytes\n", nvram_size);
+ of_node_put(nvram);
+
+ ppc_md.nvram_read_val = chrp_nvram_read;
+ ppc_md.nvram_write_val = chrp_nvram_write;
+
+ return;
+}
diff -puN arch/ppc/platforms/chrp_setup.c~ppc32-nvram-driver-for-chrp arch/ppc/platforms/chrp_setup.c
--- devel/arch/ppc/platforms/chrp_setup.c~ppc32-nvram-driver-for-chrp 2005-10-28 17:44:02.000000000 -0700
+++ devel-akpm/arch/ppc/platforms/chrp_setup.c 2005-10-28 17:44:02.000000000 -0700
@@ -464,8 +464,7 @@ void __init
chrp_init2(void)
{
#ifdef CONFIG_NVRAM
-// XX replace this in a more saner way
-// pmac_nvram_init();
+ chrp_nvram_init();
#endif
request_region(0x20,0x20,"pic1");
diff -puN arch/ppc/platforms/Makefile~ppc32-nvram-driver-for-chrp arch/ppc/platforms/Makefile
--- devel/arch/ppc/platforms/Makefile~ppc32-nvram-driver-for-chrp 2005-10-28 17:44:02.000000000 -0700
+++ devel-akpm/arch/ppc/platforms/Makefile 2005-10-28 17:45:21.000000000 -0700
@@ -14,6 +14,9 @@ obj-$(CONFIG_PPC_PMAC) += pmac_pic.o pm
pmac_low_i2c.o pmac_cache.o
obj-$(CONFIG_PPC_CHRP) += chrp_setup.o chrp_time.o chrp_pci.o \
chrp_pegasos_eth.o
+ifeq ($(CONFIG_PPC_CHRP),y)
+obj-$(CONFIG_NVRAM) += chrp_nvram.o
+endif
obj-$(CONFIG_PPC_PREP) += prep_pci.o prep_setup.o
ifeq ($(CONFIG_PPC_PMAC),y)
obj-$(CONFIG_NVRAM) += pmac_nvram.o
diff -puN include/asm-ppc/system.h~ppc32-nvram-driver-for-chrp include/asm-ppc/system.h
--- devel/include/asm-ppc/system.h~ppc32-nvram-driver-for-chrp 2005-10-28 17:44:02.000000000 -0700
+++ devel-akpm/include/asm-ppc/system.h 2005-10-28 17:44:02.000000000 -0700
@@ -70,6 +70,7 @@ extern void _set_L3CR(unsigned long);
#endif
extern void via_cuda_init(void);
extern void pmac_nvram_init(void);
+extern void chrp_nvram_init(void);
extern void read_rtc_time(void);
extern void pmac_find_display(void);
extern void giveup_fpu(struct task_struct *);
_
^ permalink raw reply
* [patch 08/43] ppc: make phys_mem_access_prot() work with pfns instead of addresses
From: akpm @ 2005-10-29 0:46 UTC (permalink / raw)
To: paulus; +Cc: akpm, linuxppc-dev, linuxppc64-dev, rolandd
From: Roland Dreier <rolandd@cisco.com>
Change the phys_mem_access_prot() function to take a pfn instead of an
address. This allows mmap64() to work on /dev/mem for addresses above 4G
on 32-bit architectures. We start with a pfn in mmap_mem(), so there's no
need to convert to an address; in fact, it's actively bad, since the
conversion can overflow when the address is above 4G.
Similarly fix the ppc32 page_is_ram() function to avoid a conversion to an
address by directly comparing to max_pfn. Working with max_pfn instead of
high_memory fixes page_is_ram() to give the right answer for highmem pages.
Signed-off-by: Roland Dreier <rolandd@cisco.com>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Anton Blanchard <anton@samba.org>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
---
arch/ppc/kernel/pci.c | 5 +++--
arch/ppc/mm/init.c | 10 ++++------
arch/ppc64/kernel/pci.c | 5 +++--
arch/ppc64/mm/init.c | 6 +++---
drivers/char/mem.c | 4 +---
drivers/video/fbmem.c | 2 +-
include/asm-ppc/machdep.h | 2 +-
include/asm-ppc/pci.h | 2 +-
include/asm-ppc/pgtable.h | 2 +-
include/asm-ppc64/machdep.h | 2 +-
include/asm-ppc64/pci.h | 2 +-
include/asm-ppc64/pgtable.h | 2 +-
12 files changed, 21 insertions(+), 23 deletions(-)
diff -puN arch/ppc64/kernel/pci.c~ppc-make-phys_mem_access_prot-work-with-pfns-instead-of arch/ppc64/kernel/pci.c
--- devel/arch/ppc64/kernel/pci.c~ppc-make-phys_mem_access_prot-work-with-pfns-instead-of 2005-10-28 17:44:02.000000000 -0700
+++ devel-akpm/arch/ppc64/kernel/pci.c 2005-10-28 17:44:02.000000000 -0700
@@ -727,16 +727,17 @@ static pgprot_t __pci_mmap_set_pgprot(st
* above routine
*/
pgprot_t pci_phys_mem_access_prot(struct file *file,
- unsigned long offset,
+ unsigned long pfn,
unsigned long size,
pgprot_t protection)
{
struct pci_dev *pdev = NULL;
struct resource *found = NULL;
unsigned long prot = pgprot_val(protection);
+ unsigned long offset = pfn << PAGE_SHIFT;
int i;
- if (page_is_ram(offset >> PAGE_SHIFT))
+ if (page_is_ram(pfn))
return __pgprot(prot);
prot |= _PAGE_NO_CACHE | _PAGE_GUARDED;
diff -puN arch/ppc64/mm/init.c~ppc-make-phys_mem_access_prot-work-with-pfns-instead-of arch/ppc64/mm/init.c
--- devel/arch/ppc64/mm/init.c~ppc-make-phys_mem_access_prot-work-with-pfns-instead-of 2005-10-28 17:44:02.000000000 -0700
+++ devel-akpm/arch/ppc64/mm/init.c 2005-10-28 17:44:02.000000000 -0700
@@ -855,13 +855,13 @@ void pgtable_cache_init(void)
}
}
-pgprot_t phys_mem_access_prot(struct file *file, unsigned long addr,
+pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
unsigned long size, pgprot_t vma_prot)
{
if (ppc_md.phys_mem_access_prot)
- return ppc_md.phys_mem_access_prot(file, addr, size, vma_prot);
+ return ppc_md.phys_mem_access_prot(file, pfn, size, vma_prot);
- if (!page_is_ram(addr >> PAGE_SHIFT))
+ if (!page_is_ram(pfn))
vma_prot = __pgprot(pgprot_val(vma_prot)
| _PAGE_GUARDED | _PAGE_NO_CACHE);
return vma_prot;
diff -puN arch/ppc/kernel/pci.c~ppc-make-phys_mem_access_prot-work-with-pfns-instead-of arch/ppc/kernel/pci.c
--- devel/arch/ppc/kernel/pci.c~ppc-make-phys_mem_access_prot-work-with-pfns-instead-of 2005-10-28 17:44:02.000000000 -0700
+++ devel-akpm/arch/ppc/kernel/pci.c 2005-10-28 17:44:02.000000000 -0700
@@ -1586,16 +1586,17 @@ static pgprot_t __pci_mmap_set_pgprot(st
* above routine
*/
pgprot_t pci_phys_mem_access_prot(struct file *file,
- unsigned long offset,
+ unsigned long pfn,
unsigned long size,
pgprot_t protection)
{
struct pci_dev *pdev = NULL;
struct resource *found = NULL;
unsigned long prot = pgprot_val(protection);
+ unsigned long offset = pfn << PAGE_SHIFT;
int i;
- if (page_is_ram(offset >> PAGE_SHIFT))
+ if (page_is_ram(pfn))
return prot;
prot |= _PAGE_NO_CACHE | _PAGE_GUARDED;
diff -puN arch/ppc/mm/init.c~ppc-make-phys_mem_access_prot-work-with-pfns-instead-of arch/ppc/mm/init.c
--- devel/arch/ppc/mm/init.c~ppc-make-phys_mem_access_prot-work-with-pfns-instead-of 2005-10-28 17:44:02.000000000 -0700
+++ devel-akpm/arch/ppc/mm/init.c 2005-10-28 17:44:02.000000000 -0700
@@ -648,18 +648,16 @@ void update_mmu_cache(struct vm_area_str
*/
int page_is_ram(unsigned long pfn)
{
- unsigned long paddr = (pfn << PAGE_SHIFT);
-
- return paddr < __pa(high_memory);
+ return pfn < max_pfn;
}
-pgprot_t phys_mem_access_prot(struct file *file, unsigned long addr,
+pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
unsigned long size, pgprot_t vma_prot)
{
if (ppc_md.phys_mem_access_prot)
- return ppc_md.phys_mem_access_prot(file, addr, size, vma_prot);
+ return ppc_md.phys_mem_access_prot(file, pfn, size, vma_prot);
- if (!page_is_ram(addr >> PAGE_SHIFT))
+ if (!page_is_ram(pfn))
vma_prot = __pgprot(pgprot_val(vma_prot)
| _PAGE_GUARDED | _PAGE_NO_CACHE);
return vma_prot;
diff -puN drivers/char/mem.c~ppc-make-phys_mem_access_prot-work-with-pfns-instead-of drivers/char/mem.c
--- devel/drivers/char/mem.c~ppc-make-phys_mem_access_prot-work-with-pfns-instead-of 2005-10-28 17:44:02.000000000 -0700
+++ devel-akpm/drivers/char/mem.c 2005-10-28 17:44:02.000000000 -0700
@@ -231,9 +231,7 @@ static ssize_t write_mem(struct file * f
static int mmap_mem(struct file * file, struct vm_area_struct * vma)
{
#if defined(__HAVE_PHYS_MEM_ACCESS_PROT)
- unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
-
- vma->vm_page_prot = phys_mem_access_prot(file, offset,
+ vma->vm_page_prot = phys_mem_access_prot(file, vma->vm_pgoff,
vma->vm_end - vma->vm_start,
vma->vm_page_prot);
#elif defined(pgprot_noncached)
diff -puN drivers/video/fbmem.c~ppc-make-phys_mem_access_prot-work-with-pfns-instead-of drivers/video/fbmem.c
--- devel/drivers/video/fbmem.c~ppc-make-phys_mem_access_prot-work-with-pfns-instead-of 2005-10-28 17:44:02.000000000 -0700
+++ devel-akpm/drivers/video/fbmem.c 2005-10-28 17:44:02.000000000 -0700
@@ -918,7 +918,7 @@ fb_mmap(struct file *file, struct vm_are
}
#endif
#elif defined(__powerpc__)
- vma->vm_page_prot = phys_mem_access_prot(file, off,
+ vma->vm_page_prot = phys_mem_access_prot(file, off >> PAGE_SHIFT,
vma->vm_end - vma->vm_start,
vma->vm_page_prot);
#elif defined(__alpha__)
diff -puN include/asm-ppc64/machdep.h~ppc-make-phys_mem_access_prot-work-with-pfns-instead-of include/asm-ppc64/machdep.h
--- devel/include/asm-ppc64/machdep.h~ppc-make-phys_mem_access_prot-work-with-pfns-instead-of 2005-10-28 17:44:02.000000000 -0700
+++ devel-akpm/include/asm-ppc64/machdep.h 2005-10-28 17:44:02.000000000 -0700
@@ -130,7 +130,7 @@ struct machdep_calls {
/* Get access protection for /dev/mem */
pgprot_t (*phys_mem_access_prot)(struct file *file,
- unsigned long offset,
+ unsigned long pfn,
unsigned long size,
pgprot_t vma_prot);
diff -puN include/asm-ppc64/pci.h~ppc-make-phys_mem_access_prot-work-with-pfns-instead-of include/asm-ppc64/pci.h
--- devel/include/asm-ppc64/pci.h~ppc-make-phys_mem_access_prot-work-with-pfns-instead-of 2005-10-28 17:44:02.000000000 -0700
+++ devel-akpm/include/asm-ppc64/pci.h 2005-10-28 17:44:02.000000000 -0700
@@ -168,7 +168,7 @@ extern void pcibios_add_platform_entries
struct file;
extern pgprot_t pci_phys_mem_access_prot(struct file *file,
- unsigned long offset,
+ unsigned long pfn,
unsigned long size,
pgprot_t prot);
diff -puN include/asm-ppc64/pgtable.h~ppc-make-phys_mem_access_prot-work-with-pfns-instead-of include/asm-ppc64/pgtable.h
--- devel/include/asm-ppc64/pgtable.h~ppc-make-phys_mem_access_prot-work-with-pfns-instead-of 2005-10-28 17:44:02.000000000 -0700
+++ devel-akpm/include/asm-ppc64/pgtable.h 2005-10-28 17:44:02.000000000 -0700
@@ -471,7 +471,7 @@ static inline void __ptep_set_access_fla
#define pgprot_noncached(prot) (__pgprot(pgprot_val(prot) | _PAGE_NO_CACHE | _PAGE_GUARDED))
struct file;
-extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long addr,
+extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
unsigned long size, pgprot_t vma_prot);
#define __HAVE_PHYS_MEM_ACCESS_PROT
diff -puN include/asm-ppc/machdep.h~ppc-make-phys_mem_access_prot-work-with-pfns-instead-of include/asm-ppc/machdep.h
--- devel/include/asm-ppc/machdep.h~ppc-make-phys_mem_access_prot-work-with-pfns-instead-of 2005-10-28 17:44:02.000000000 -0700
+++ devel-akpm/include/asm-ppc/machdep.h 2005-10-28 17:44:02.000000000 -0700
@@ -98,7 +98,7 @@ struct machdep_calls {
/* Get access protection for /dev/mem */
pgprot_t (*phys_mem_access_prot)(struct file *file,
- unsigned long offset,
+ unsigned long pfn,
unsigned long size,
pgprot_t vma_prot);
diff -puN include/asm-ppc/pci.h~ppc-make-phys_mem_access_prot-work-with-pfns-instead-of include/asm-ppc/pci.h
--- devel/include/asm-ppc/pci.h~ppc-make-phys_mem_access_prot-work-with-pfns-instead-of 2005-10-28 17:44:02.000000000 -0700
+++ devel-akpm/include/asm-ppc/pci.h 2005-10-28 17:44:02.000000000 -0700
@@ -126,7 +126,7 @@ extern void pcibios_add_platform_entries
struct file;
extern pgprot_t pci_phys_mem_access_prot(struct file *file,
- unsigned long offset,
+ unsigned long pfn,
unsigned long size,
pgprot_t prot);
diff -puN include/asm-ppc/pgtable.h~ppc-make-phys_mem_access_prot-work-with-pfns-instead-of include/asm-ppc/pgtable.h
--- devel/include/asm-ppc/pgtable.h~ppc-make-phys_mem_access_prot-work-with-pfns-instead-of 2005-10-28 17:44:02.000000000 -0700
+++ devel-akpm/include/asm-ppc/pgtable.h 2005-10-28 17:44:02.000000000 -0700
@@ -705,7 +705,7 @@ static inline void __ptep_set_access_fla
#define pgprot_noncached(prot) (__pgprot(pgprot_val(prot) | _PAGE_NO_CACHE | _PAGE_GUARDED))
struct file;
-extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long addr,
+extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
unsigned long size, pgprot_t vma_prot);
#define __HAVE_PHYS_MEM_ACCESS_PROT
_
^ permalink raw reply
* [patch 07/43] ppc32: update xmon help text
From: akpm @ 2005-10-29 0:46 UTC (permalink / raw)
To: paulus; +Cc: akpm, linuxppc-dev, olh, linuxppc64-dev
From: Olaf Hering <olh@suse.de>
Mention a few more commands in xmon. System.map processing was replaced
with kallsyms.
Signed-off-by: Olaf Hering <olh@suse.de>
Signed-off-by: Andrew Morton <akpm@osdl.org>
---
arch/ppc/xmon/xmon.c | 9 +++++++--
1 files changed, 7 insertions(+), 2 deletions(-)
diff -puN arch/ppc/xmon/xmon.c~ppc32-update-xmon-help-text arch/ppc/xmon/xmon.c
--- devel/arch/ppc/xmon/xmon.c~ppc32-update-xmon-help-text 2005-10-28 17:44:02.000000000 -0700
+++ devel-akpm/arch/ppc/xmon/xmon.c 2005-10-28 17:44:02.000000000 -0700
@@ -148,9 +148,14 @@ Commands:\n\
r print registers\n\
S print special registers\n\
t print backtrace\n\
- la lookup address in system.map\n\
- ls lookup symbol in system.map\n\
+ la lookup address\n\
+ ls lookup symbol\n\
+ C checksum\n\
+ P call function with arguments\n\
+ T print time\n\
x exit monitor\n\
+ zr reboot\n\
+ zh halt\n\
";
static int xmon_trace[NR_CPUS];
_
^ permalink raw reply
* [patch 06/43] ppc32: handle access to non-present IO ports on 8xx
From: akpm @ 2005-10-29 0:46 UTC (permalink / raw)
To: paulus; +Cc: akpm, linuxppc-dev, linuxppc64-dev
From: Marcelo Tosatti <marcelo.tosatti@cyclades.com>
Accessing non present "IO ports" on 8xx generates MCE's. The exception is
easily triggered during insertion/removal/suspension of PCMCIA cards.
The following adds exception table entries for I/O instructions on 8xx
(copied from the original Paul's PowerMac code), and changes
MachineCheckException() slightly to cover 8xx specific's (on 8xx the MCE
can be generated while executing the IO access instruction itself, which is
not the case on PowerMac's, as the comment on traps.c details).
Signed-off-by: Marcelo Tosatti <marcelo.tosatti@cyclades.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
---
arch/ppc/kernel/misc.S | 160 ++++++++++++++++++++++++++++++++++++++++++------
arch/ppc/kernel/traps.c | 8 +-
include/asm-ppc/io.h | 24 ++++++-
3 files changed, 168 insertions(+), 24 deletions(-)
diff -puN arch/ppc/kernel/misc.S~ppc32-handle-access-to-non-present-io-ports-on-8xx arch/ppc/kernel/misc.S
--- devel/arch/ppc/kernel/misc.S~ppc32-handle-access-to-non-present-io-ports-on-8xx 2005-10-28 17:44:02.000000000 -0700
+++ devel-akpm/arch/ppc/kernel/misc.S 2005-10-28 17:44:02.000000000 -0700
@@ -930,8 +930,20 @@ _GLOBAL(_insb)
subi r4,r4,1
blelr-
00: lbz r5,0(r3)
- eieio
- stbu r5,1(r4)
+01: eieio
+02: stbu r5,1(r4)
+#ifdef CONFIG_8xx
+ isync
+ .section .fixup,"ax"
+03: blr
+ .text
+ .section __ex_table, "a"
+ .align 2
+ .long 00b, 03b
+ .long 01b, 03b
+ .long 02b, 03b
+ .text
+#endif
bdnz 00b
blr
@@ -941,8 +953,20 @@ _GLOBAL(_outsb)
subi r4,r4,1
blelr-
00: lbzu r5,1(r4)
- stb r5,0(r3)
- eieio
+01: stb r5,0(r3)
+02: eieio
+#ifdef CONFIG_8xx
+ isync
+ .section .fixup,"ax"
+03: blr
+ .text
+ .section __ex_table, "a"
+ .align 2
+ .long 00b, 03b
+ .long 01b, 03b
+ .long 02b, 03b
+ .text
+#endif
bdnz 00b
blr
@@ -952,8 +976,20 @@ _GLOBAL(_insw)
subi r4,r4,2
blelr-
00: lhbrx r5,0,r3
- eieio
- sthu r5,2(r4)
+01: eieio
+02: sthu r5,2(r4)
+#ifdef CONFIG_8xx
+ isync
+ .section .fixup,"ax"
+03: blr
+ .text
+ .section __ex_table, "a"
+ .align 2
+ .long 00b, 03b
+ .long 01b, 03b
+ .long 02b, 03b
+ .text
+#endif
bdnz 00b
blr
@@ -963,8 +999,20 @@ _GLOBAL(_outsw)
subi r4,r4,2
blelr-
00: lhzu r5,2(r4)
- eieio
- sthbrx r5,0,r3
+01: eieio
+02: sthbrx r5,0,r3
+#ifdef CONFIG_8xx
+ isync
+ .section .fixup,"ax"
+03: blr
+ .text
+ .section __ex_table, "a"
+ .align 2
+ .long 00b, 03b
+ .long 01b, 03b
+ .long 02b, 03b
+ .text
+#endif
bdnz 00b
blr
@@ -974,8 +1022,20 @@ _GLOBAL(_insl)
subi r4,r4,4
blelr-
00: lwbrx r5,0,r3
- eieio
- stwu r5,4(r4)
+01: eieio
+02: stwu r5,4(r4)
+#ifdef CONFIG_8xx
+ isync
+ .section .fixup,"ax"
+03: blr
+ .text
+ .section __ex_table, "a"
+ .align 2
+ .long 00b, 03b
+ .long 01b, 03b
+ .long 02b, 03b
+ .text
+#endif
bdnz 00b
blr
@@ -985,8 +1045,20 @@ _GLOBAL(_outsl)
subi r4,r4,4
blelr-
00: lwzu r5,4(r4)
- stwbrx r5,0,r3
- eieio
+01: stwbrx r5,0,r3
+02: eieio
+#ifdef CONFIG_8xx
+ isync
+ .section .fixup,"ax"
+03: blr
+ .text
+ .section __ex_table, "a"
+ .align 2
+ .long 00b, 03b
+ .long 01b, 03b
+ .long 02b, 03b
+ .text
+#endif
bdnz 00b
blr
@@ -997,8 +1069,20 @@ _GLOBAL(_insw_ns)
subi r4,r4,2
blelr-
00: lhz r5,0(r3)
- eieio
- sthu r5,2(r4)
+01: eieio
+02: sthu r5,2(r4)
+#ifdef CONFIG_8xx
+ isync
+ .section .fixup,"ax"
+03: blr
+ .text
+ .section __ex_table, "a"
+ .align 2
+ .long 00b, 03b
+ .long 01b, 03b
+ .long 02b, 03b
+ .text
+#endif
bdnz 00b
blr
@@ -1009,8 +1093,20 @@ _GLOBAL(_outsw_ns)
subi r4,r4,2
blelr-
00: lhzu r5,2(r4)
- sth r5,0(r3)
- eieio
+01: sth r5,0(r3)
+02: eieio
+#ifdef CONFIG_8xx
+ isync
+ .section .fixup,"ax"
+03: blr
+ .text
+ .section __ex_table, "a"
+ .align 2
+ .long 00b, 03b
+ .long 01b, 03b
+ .long 02b, 03b
+ .text
+#endif
bdnz 00b
blr
@@ -1021,8 +1117,20 @@ _GLOBAL(_insl_ns)
subi r4,r4,4
blelr-
00: lwz r5,0(r3)
- eieio
- stwu r5,4(r4)
+01: eieio
+02: stwu r5,4(r4)
+#ifdef CONFIG_8xx
+ isync
+ .section .fixup,"ax"
+03: blr
+ .text
+ .section __ex_table, "a"
+ .align 2
+ .long 00b, 03b
+ .long 01b, 03b
+ .long 02b, 03b
+ .text
+#endif
bdnz 00b
blr
@@ -1033,8 +1141,20 @@ _GLOBAL(_outsl_ns)
subi r4,r4,4
blelr-
00: lwzu r5,4(r4)
- stw r5,0(r3)
- eieio
+01: stw r5,0(r3)
+02: eieio
+#ifdef CONFIG_8xx
+ isync
+ .section .fixup,"ax"
+03: blr
+ .text
+ .section __ex_table, "a"
+ .align 2
+ .long 00b, 03b
+ .long 01b, 03b
+ .long 02b, 03b
+ .text
+#endif
bdnz 00b
blr
diff -puN arch/ppc/kernel/traps.c~ppc32-handle-access-to-non-present-io-ports-on-8xx arch/ppc/kernel/traps.c
--- devel/arch/ppc/kernel/traps.c~ppc32-handle-access-to-non-present-io-ports-on-8xx 2005-10-28 17:44:02.000000000 -0700
+++ devel-akpm/arch/ppc/kernel/traps.c 2005-10-28 17:44:02.000000000 -0700
@@ -154,7 +154,7 @@ void _exception(int signr, struct pt_reg
*/
static inline int check_io_access(struct pt_regs *regs)
{
-#ifdef CONFIG_PPC_PMAC
+#if defined CONFIG_PPC_PMAC || defined CONFIG_8xx
unsigned long msr = regs->msr;
const struct exception_table_entry *entry;
unsigned int *nip = (unsigned int *)regs->nip;
@@ -173,7 +173,11 @@ static inline int check_io_access(struct
nip -= 2;
else if (*nip == 0x4c00012c) /* isync */
--nip;
- if (*nip == 0x7c0004ac || (*nip >> 26) == 3) {
+ /* eieio from I/O string functions */
+ else if ((*nip) == 0x7c0006ac || *(nip+1) == 0x7c0006ac)
+ nip += 2;
+ if (*nip == 0x7c0004ac || (*nip >> 26) == 3 ||
+ (*(nip+1) >> 26) == 3) {
/* sync or twi */
unsigned int rb;
diff -puN include/asm-ppc/io.h~ppc32-handle-access-to-non-present-io-ports-on-8xx include/asm-ppc/io.h
--- devel/include/asm-ppc/io.h~ppc32-handle-access-to-non-present-io-ports-on-8xx 2005-10-28 17:44:02.000000000 -0700
+++ devel-akpm/include/asm-ppc/io.h 2005-10-28 17:44:02.000000000 -0700
@@ -257,7 +257,7 @@ extern __inline__ unsigned int name(unsi
{ \
unsigned int x; \
__asm__ __volatile__( \
- op " %0,0,%1\n" \
+ "0:" op " %0,0,%1\n" \
"1: twi 0,%0,0\n" \
"2: isync\n" \
"3: nop\n" \
@@ -268,6 +268,7 @@ extern __inline__ unsigned int name(unsi
".previous\n" \
".section __ex_table,\"a\"\n" \
" .align 2\n" \
+ " .long 0b,5b\n" \
" .long 1b,5b\n" \
" .long 2b,5b\n" \
" .long 3b,5b\n" \
@@ -276,7 +277,25 @@ extern __inline__ unsigned int name(unsi
: "r" (port + ___IO_BASE)); \
return x; \
}
-
+#ifdef CONFIG_8xx
+#define __do_out_asm(name, op) \
+extern __inline__ void name(unsigned int val, unsigned int port) \
+{ \
+ __asm__ __volatile__( \
+ "0:" op " %0,0,%1\n" \
+ "1: sync\n" \
+ "2:\n" \
+ ".section .fixup,\"ax\"\n" \
+ "3: b 2b\n" \
+ ".previous\n" \
+ ".section __ex_table,\"a\"\n" \
+ " .align 2\n" \
+ " .long 0b,2b\n" \
+ " .long 1b,2b\n" \
+ ".previous" \
+ : : "r" (val), "r" (port + ___IO_BASE)); \
+}
+#else
#define __do_out_asm(name, op) \
extern __inline__ void name(unsigned int val, unsigned int port) \
{ \
@@ -290,6 +309,7 @@ extern __inline__ void name(unsigned int
".previous" \
: : "r" (val), "r" (port + ___IO_BASE)); \
}
+#endif
__do_out_asm(outb, "stbx")
#ifdef CONFIG_APUS
_
^ permalink raw reply
* [patch 05/43] ppc32: #ifdef out ALTIVEC specific code in __switch_to
From: akpm @ 2005-10-29 0:46 UTC (permalink / raw)
To: paulus; +Cc: akpm, linuxppc-dev, linuxppc64-dev
From: Marcelo Tosatti <marcelo.tosatti@cyclades.com>
#ifdef out an ALTIVEC specific tweak in __switch_to()
Signed-off-by: Marcelo Tosatti <marcelo.tosatti@cyclades.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
---
arch/ppc/kernel/process.c | 2 ++
1 files changed, 2 insertions(+)
diff -puN arch/ppc/kernel/process.c~ppc32-ifdef-out-altivec-specific-code-in-__switch_to arch/ppc/kernel/process.c
--- devel/arch/ppc/kernel/process.c~ppc32-ifdef-out-altivec-specific-code-in-__switch_to 2005-10-28 17:44:02.000000000 -0700
+++ devel-akpm/arch/ppc/kernel/process.c 2005-10-28 17:44:02.000000000 -0700
@@ -287,11 +287,13 @@ struct task_struct *__switch_to(struct t
#endif /* CONFIG_SPE */
#endif /* CONFIG_SMP */
+#ifdef CONFIG_ALTIVEC
/* Avoid the trap. On smp this this never happens since
* we don't set last_task_used_altivec -- Cort
*/
if (new->thread.regs && last_task_used_altivec == new)
new->thread.regs->msr |= MSR_VEC;
+#endif
#ifdef CONFIG_SPE
/* Avoid the trap. On smp this this never happens since
* we don't set last_task_used_spe
_
^ permalink raw reply
* [patch 04/43] ppc32: Cleanup AMCC PPC44x eval board U-Boot support
From: akpm @ 2005-10-29 0:46 UTC (permalink / raw)
To: paulus; +Cc: akpm, linuxppc-dev, sr, linuxppc64-dev
From: Matt Porter <mporter@kernel.crashing.org>
Cleanup PPC440 eval boards (bamboo, ebony, luan and ocotea) to better
support U-Boot as bootloader.
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Matt Porter <mporter@kernel.crashing.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
---
arch/ppc/platforms/4xx/bamboo.c | 14 ++------------
arch/ppc/platforms/4xx/ebony.c | 13 ++-----------
arch/ppc/platforms/4xx/luan.c | 13 ++-----------
arch/ppc/platforms/4xx/ocotea.c | 31 +++++++++++--------------------
arch/ppc/syslib/ibm44x_common.c | 35 ++++++++++++++++++++++++++++++++++-
arch/ppc/syslib/ibm44x_common.h | 3 ++-
6 files changed, 53 insertions(+), 56 deletions(-)
diff -puN arch/ppc/platforms/4xx/bamboo.c~ppc32-cleanup-amcc-ppc44x-eval-board-u-boot-support arch/ppc/platforms/4xx/bamboo.c
--- devel/arch/ppc/platforms/4xx/bamboo.c~ppc32-cleanup-amcc-ppc44x-eval-board-u-boot-support 2005-10-28 17:44:02.000000000 -0700
+++ devel-akpm/arch/ppc/platforms/4xx/bamboo.c 2005-10-28 17:44:02.000000000 -0700
@@ -51,7 +51,7 @@
#include <syslib/gen550.h>
#include <syslib/ibm440gx_common.h>
-bd_t __res;
+extern bd_t __res;
static struct ibm44x_clocks clocks __initdata;
@@ -425,17 +425,7 @@ bamboo_setup_arch(void)
void __init platform_init(unsigned long r3, unsigned long r4,
unsigned long r5, unsigned long r6, unsigned long r7)
{
- parse_bootinfo(find_bootinfo());
-
- /*
- * If we were passed in a board information, copy it into the
- * residual data area.
- */
- if (r3)
- __res = *(bd_t *)(r3 + KERNELBASE);
-
-
- ibm44x_platform_init();
+ ibm44x_platform_init(r3, r4, r5, r6, r7);
ppc_md.setup_arch = bamboo_setup_arch;
ppc_md.show_cpuinfo = bamboo_show_cpuinfo;
diff -puN arch/ppc/platforms/4xx/ebony.c~ppc32-cleanup-amcc-ppc44x-eval-board-u-boot-support arch/ppc/platforms/4xx/ebony.c
--- devel/arch/ppc/platforms/4xx/ebony.c~ppc32-cleanup-amcc-ppc44x-eval-board-u-boot-support 2005-10-28 17:44:02.000000000 -0700
+++ devel-akpm/arch/ppc/platforms/4xx/ebony.c 2005-10-28 17:44:02.000000000 -0700
@@ -54,7 +54,7 @@
#include <syslib/gen550.h>
#include <syslib/ibm440gp_common.h>
-bd_t __res;
+extern bd_t __res;
static struct ibm44x_clocks clocks __initdata;
@@ -317,16 +317,7 @@ ebony_setup_arch(void)
void __init platform_init(unsigned long r3, unsigned long r4,
unsigned long r5, unsigned long r6, unsigned long r7)
{
- parse_bootinfo(find_bootinfo());
-
- /*
- * If we were passed in a board information, copy it into the
- * residual data area.
- */
- if (r3)
- __res = *(bd_t *)(r3 + KERNELBASE);
-
- ibm44x_platform_init();
+ ibm44x_platform_init(r3, r4, r5, r6, r7);
ppc_md.setup_arch = ebony_setup_arch;
ppc_md.show_cpuinfo = ebony_show_cpuinfo;
diff -puN arch/ppc/platforms/4xx/luan.c~ppc32-cleanup-amcc-ppc44x-eval-board-u-boot-support arch/ppc/platforms/4xx/luan.c
--- devel/arch/ppc/platforms/4xx/luan.c~ppc32-cleanup-amcc-ppc44x-eval-board-u-boot-support 2005-10-28 17:44:02.000000000 -0700
+++ devel-akpm/arch/ppc/platforms/4xx/luan.c 2005-10-28 17:44:02.000000000 -0700
@@ -52,7 +52,7 @@
#include <syslib/ibm440gx_common.h>
#include <syslib/ibm440sp_common.h>
-bd_t __res;
+extern bd_t __res;
static struct ibm44x_clocks clocks __initdata;
@@ -355,16 +355,7 @@ luan_setup_arch(void)
void __init platform_init(unsigned long r3, unsigned long r4,
unsigned long r5, unsigned long r6, unsigned long r7)
{
- parse_bootinfo(find_bootinfo());
-
- /*
- * If we were passed in a board information, copy it into the
- * residual data area.
- */
- if (r3)
- __res = *(bd_t *)(r3 + KERNELBASE);
-
- ibm44x_platform_init();
+ ibm44x_platform_init(r3, r4, r5, r6, r7);
ppc_md.setup_arch = luan_setup_arch;
ppc_md.show_cpuinfo = luan_show_cpuinfo;
diff -puN arch/ppc/platforms/4xx/ocotea.c~ppc32-cleanup-amcc-ppc44x-eval-board-u-boot-support arch/ppc/platforms/4xx/ocotea.c
--- devel/arch/ppc/platforms/4xx/ocotea.c~ppc32-cleanup-amcc-ppc44x-eval-board-u-boot-support 2005-10-28 17:44:02.000000000 -0700
+++ devel-akpm/arch/ppc/platforms/4xx/ocotea.c 2005-10-28 17:44:02.000000000 -0700
@@ -52,7 +52,7 @@
#include <syslib/gen550.h>
#include <syslib/ibm440gx_common.h>
-bd_t __res;
+extern bd_t __res;
static struct ibm44x_clocks clocks __initdata;
@@ -286,6 +286,15 @@ ocotea_setup_arch(void)
ibm440gx_tah_enable();
+ /*
+ * Determine various clocks.
+ * To be completely correct we should get SysClk
+ * from FPGA, because it can be changed by on-board switches
+ * --ebs
+ */
+ ibm440gx_get_clocks(&clocks, 33333333, 6 * 1843200);
+ ocp_sys_info.opb_bus_freq = clocks.opb;
+
/* Setup TODC access */
TODC_INIT(TODC_TYPE_DS1743,
0,
@@ -324,25 +333,7 @@ static void __init ocotea_init(void)
void __init platform_init(unsigned long r3, unsigned long r4,
unsigned long r5, unsigned long r6, unsigned long r7)
{
- parse_bootinfo(find_bootinfo());
-
- /*
- * If we were passed in a board information, copy it into the
- * residual data area.
- */
- if (r3)
- __res = *(bd_t *)(r3 + KERNELBASE);
-
- /*
- * Determine various clocks.
- * To be completely correct we should get SysClk
- * from FPGA, because it can be changed by on-board switches
- * --ebs
- */
- ibm440gx_get_clocks(&clocks, 33333333, 6 * 1843200);
- ocp_sys_info.opb_bus_freq = clocks.opb;
-
- ibm44x_platform_init();
+ ibm44x_platform_init(r3, r4, r5, r6, r7);
ppc_md.setup_arch = ocotea_setup_arch;
ppc_md.show_cpuinfo = ocotea_show_cpuinfo;
diff -puN arch/ppc/syslib/ibm44x_common.c~ppc32-cleanup-amcc-ppc44x-eval-board-u-boot-support arch/ppc/syslib/ibm44x_common.c
--- devel/arch/ppc/syslib/ibm44x_common.c~ppc32-cleanup-amcc-ppc44x-eval-board-u-boot-support 2005-10-28 17:44:02.000000000 -0700
+++ devel-akpm/arch/ppc/syslib/ibm44x_common.c 2005-10-28 17:44:02.000000000 -0700
@@ -27,9 +27,14 @@
#include <asm/time.h>
#include <asm/ppc4xx_pic.h>
#include <asm/param.h>
+#include <asm/bootinfo.h>
+#include <asm/ppcboot.h>
#include <syslib/gen550.h>
+/* Global Variables */
+bd_t __res;
+
phys_addr_t fixup_bigphys_addr(phys_addr_t addr, phys_addr_t size)
{
phys_addr_t page_4gb = 0;
@@ -150,8 +155,36 @@ static unsigned long __init ibm44x_find_
return mem_size;
}
-void __init ibm44x_platform_init(void)
+void __init ibm44x_platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
+ unsigned long r6, unsigned long r7)
{
+ parse_bootinfo(find_bootinfo());
+
+ /*
+ * If we were passed in a board information, copy it into the
+ * residual data area.
+ */
+ if (r3)
+ __res = *(bd_t *)(r3 + KERNELBASE);
+
+#if defined(CONFIG_BLK_DEV_INITRD)
+ /*
+ * If the init RAM disk has been configured in, and there's a valid
+ * starting address for it, set it up.
+ */
+ if (r4) {
+ initrd_start = r4 + KERNELBASE;
+ initrd_end = r5 + KERNELBASE;
+ }
+#endif /* CONFIG_BLK_DEV_INITRD */
+
+ /* Copy the kernel command line arguments to a safe place. */
+
+ if (r6) {
+ *(char *) (r7 + KERNELBASE) = 0;
+ strcpy(cmd_line, (char *) (r6 + KERNELBASE));
+ }
+
ppc_md.init_IRQ = ppc4xx_pic_init;
ppc_md.find_end_of_memory = ibm44x_find_end_of_memory;
ppc_md.restart = ibm44x_restart;
diff -puN arch/ppc/syslib/ibm44x_common.h~ppc32-cleanup-amcc-ppc44x-eval-board-u-boot-support arch/ppc/syslib/ibm44x_common.h
--- devel/arch/ppc/syslib/ibm44x_common.h~ppc32-cleanup-amcc-ppc44x-eval-board-u-boot-support 2005-10-28 17:44:02.000000000 -0700
+++ devel-akpm/arch/ppc/syslib/ibm44x_common.h 2005-10-28 17:44:02.000000000 -0700
@@ -36,7 +36,8 @@ struct ibm44x_clocks {
};
/* common 44x platform init */
-void ibm44x_platform_init(void) __init;
+void ibm44x_platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
+ unsigned long r6, unsigned long r7) __init;
/* initialize decrementer and tick-related variables */
void ibm44x_calibrate_decr(unsigned int freq) __init;
_
^ permalink raw reply
* [patch 03/43] MPC8xx PCMCIA driver
From: akpm @ 2005-10-29 0:46 UTC (permalink / raw)
To: paulus; +Cc: akpm, linuxppc-dev, linux, linuxppc64-dev
From: Marcelo Tosatti <marcelo.tosatti@cyclades.com>
Here is an uptodated version of the MPC8xx PCMCIA driver for v2.6,
addressing comments by Jeff and Dominik:
- use IO accessors instead of direct device memory referencing
- avoid usage of non-standard "uint/uchar" data types
- kill struct typedef's
Will submit it for inclusion once v2.6.14 is out.
Testing on 8xx platforms is more than welcome! Works like a charm
on our custom hardware (CONFIG_PRxK).
Cc: Dominik Brodowski <linux@dominikbrodowski.net>
Signed-off-by: Andrew Morton <akpm@osdl.org>
---
drivers/pcmcia/Kconfig | 10
drivers/pcmcia/Makefile | 1
drivers/pcmcia/m8xx_pcmcia.c | 1290 +++++++++++++++++++++++++++++++++++++++++++
3 files changed, 1301 insertions(+)
diff -puN drivers/pcmcia/Kconfig~mpc8xx-pcmcia-driver drivers/pcmcia/Kconfig
--- devel/drivers/pcmcia/Kconfig~mpc8xx-pcmcia-driver 2005-10-28 17:44:02.000000000 -0700
+++ devel-akpm/drivers/pcmcia/Kconfig 2005-10-28 17:44:02.000000000 -0700
@@ -154,6 +154,16 @@ config TCIC
"Bridge" is the name used for the hardware inside your computer that
PCMCIA cards are plugged into. If unsure, say N.
+config PCMCIA_M8XX
+ tristate "MPC8xx PCMCIA support"
+ depends on PCMCIA && PPC
+ select PCCARD_NONSTATIC
+ help
+ Say Y here to include support for PowerPC 8xx series PCMCIA
+ controller.
+
+ This driver is also available as a module called m8xx_pcmcia.
+
config HD64465_PCMCIA
tristate "HD64465 host bridge support"
depends on HD64465 && PCMCIA
diff -puN /dev/null drivers/pcmcia/m8xx_pcmcia.c
--- /dev/null 2003-09-15 06:40:47.000000000 -0700
+++ devel-akpm/drivers/pcmcia/m8xx_pcmcia.c 2005-10-28 17:44:02.000000000 -0700
@@ -0,0 +1,1290 @@
+/*
+ * m8xx_pcmcia.c - Linux PCMCIA socket driver for the mpc8xx series.
+ *
+ * (C) 1999-2000 Magnus Damm <damm@bitsmart.com>
+ * (C) 2001-2002 Montavista Software, Inc.
+ * <mlocke@mvista.com>
+ *
+ * Support for two slots by Cyclades Corporation
+ * <oliver.kurth@cyclades.de>
+ * Further fixes, v2.6 kernel port
+ * <marcelo.tosatti@cyclades.com>
+ *
+ * "The ExCA standard specifies that socket controllers should provide
+ * two IO and five memory windows per socket, which can be independently
+ * configured and positioned in the host address space and mapped to
+ * arbitrary segments of card address space. " - David A Hinds. 1999
+ *
+ * This controller does _not_ meet the ExCA standard.
+ *
+ * m8xx pcmcia controller brief info:
+ * + 8 windows (attrib, mem, i/o)
+ * + up to two slots (SLOT_A and SLOT_B)
+ * + inputpins, outputpins, event and mask registers.
+ * - no offset register. sigh.
+ *
+ * Because of the lacking offset register we must map the whole card.
+ * We assign each memory window PCMCIA_MEM_WIN_SIZE address space.
+ * Make sure there is (PCMCIA_MEM_WIN_SIZE * PCMCIA_MEM_WIN_NO
+ * * PCMCIA_SOCKETS_NO) bytes at PCMCIA_MEM_WIN_BASE.
+ * The i/o windows are dynamically allocated at PCMCIA_IO_WIN_BASE.
+ * They are maximum 64KByte each...
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/fcntl.h>
+#include <linux/string.h>
+
+#include <asm/io.h>
+#include <asm/bitops.h>
+#include <asm/segment.h>
+#include <asm/system.h>
+
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/sched.h>
+#include <linux/slab.h>
+#include <linux/timer.h>
+#include <linux/ioport.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+
+#include <asm/mpc8xx.h>
+#include <asm/8xx_immap.h>
+#include <asm/irq.h>
+
+#include <pcmcia/version.h>
+#include <pcmcia/cs_types.h>
+#include <pcmcia/cs.h>
+#include <pcmcia/ss.h>
+
+#ifdef PCMCIA_DEBUG
+static int pc_debug = PCMCIA_DEBUG;
+module_param(pc_debug, int, 0);
+#define dprintk(args...) printk(KERN_DEBUG "m8xx_pcmcia: " args);
+#else
+#define dprintk(args...)
+#endif
+
+#define pcmcia_info(args...) printk(KERN_INFO "m8xx_pcmcia: "args)
+#define pcmcia_error(args...) printk(KERN_ERR "m8xx_pcmcia: "args)
+
+static const char *version = "Version 0.06, Aug 2005";
+MODULE_LICENSE("Dual MPL/GPL");
+
+#if !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B)
+
+/* The RPX series use SLOT_B */
+#if defined(CONFIG_RPXCLASSIC) || defined(CONFIG_RPXLITE)
+#define CONFIG_PCMCIA_SLOT_B
+#define CONFIG_BD_IS_MHZ
+#endif
+
+/* The ADS board use SLOT_A */
+#ifdef CONFIG_ADS
+#define CONFIG_PCMCIA_SLOT_A
+#define CONFIG_BD_IS_MHZ
+#endif
+
+/* The FADS series are a mess */
+#ifdef CONFIG_FADS
+#if defined(CONFIG_MPC860T) || defined(CONFIG_MPC860) || defined(CONFIG_MPC821)
+#define CONFIG_PCMCIA_SLOT_A
+#else
+#define CONFIG_PCMCIA_SLOT_B
+#endif
+#endif
+
+/* Cyclades ACS uses both slots */
+#ifdef CONFIG_PRxK
+#define CONFIG_PCMCIA_SLOT_A
+#define CONFIG_PCMCIA_SLOT_B
+#endif
+
+#endif /* !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B) */
+
+#if defined(CONFIG_PCMCIA_SLOT_A) && defined(CONFIG_PCMCIA_SLOT_B)
+
+#define PCMCIA_SOCKETS_NO 2
+/* We have only 8 windows, dualsocket support will be limited. */
+#define PCMCIA_MEM_WIN_NO 2
+#define PCMCIA_IO_WIN_NO 2
+#define PCMCIA_SLOT_MSG "SLOT_A and SLOT_B"
+
+#elif defined(CONFIG_PCMCIA_SLOT_A) || defined(CONFIG_PCMCIA_SLOT_B)
+
+#define PCMCIA_SOCKETS_NO 1
+/* full support for one slot */
+#define PCMCIA_MEM_WIN_NO 5
+#define PCMCIA_IO_WIN_NO 2
+
+/* define _slot_ to be able to optimize macros */
+
+#ifdef CONFIG_PCMCIA_SLOT_A
+#define _slot_ 0
+#define PCMCIA_SLOT_MSG "SLOT_A"
+#else
+#define _slot_ 1
+#define PCMCIA_SLOT_MSG "SLOT_B"
+#endif
+
+#else
+#error m8xx_pcmcia: Bad configuration!
+#endif
+
+/* ------------------------------------------------------------------------- */
+
+#define PCMCIA_MEM_WIN_BASE 0xe0000000 /* base address for memory window 0 */
+#define PCMCIA_MEM_WIN_SIZE 0x04000000 /* each memory window is 64 MByte */
+#define PCMCIA_IO_WIN_BASE _IO_BASE /* base address for io window 0 */
+
+#define PCMCIA_SCHLVL PCMCIA_INTERRUPT /* Status Change Interrupt Level */
+
+/* ------------------------------------------------------------------------- */
+
+/* 2.4.x and newer has this always in HZ */
+#define M8XX_BUSFREQ ((((bd_t *)&(__res))->bi_busfreq))
+
+static int pcmcia_schlvl = PCMCIA_SCHLVL;
+
+static spinlock_t events_lock = SPIN_LOCK_UNLOCKED;
+
+
+#define PCMCIA_SOCKET_KEY_5V 1
+#define PCMCIA_SOCKET_KEY_LV 2
+
+/* look up table for pgcrx registers */
+static u32 *m8xx_pgcrx[2] = {
+ &((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pgcra,
+ &((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pgcrb
+};
+
+/*
+ * This structure is used to address each window in the PCMCIA controller.
+ *
+ * Keep in mind that we assume that pcmcia_win[n+1] is mapped directly
+ * after pcmcia_win[n]...
+ */
+
+struct pcmcia_win {
+ u32 br;
+ u32 or;
+};
+
+/*
+ * For some reason the hardware guys decided to make both slots share
+ * some registers.
+ *
+ * Could someone invent object oriented hardware ?
+ *
+ * The macros are used to get the right bit from the registers.
+ * SLOT_A : slot = 0
+ * SLOT_B : slot = 1
+ */
+
+#define M8XX_PCMCIA_VS1(slot) (0x80000000 >> (slot << 4))
+#define M8XX_PCMCIA_VS2(slot) (0x40000000 >> (slot << 4))
+#define M8XX_PCMCIA_VS_MASK(slot) (0xc0000000 >> (slot << 4))
+#define M8XX_PCMCIA_VS_SHIFT(slot) (30 - (slot << 4))
+
+#define M8XX_PCMCIA_WP(slot) (0x20000000 >> (slot << 4))
+#define M8XX_PCMCIA_CD2(slot) (0x10000000 >> (slot << 4))
+#define M8XX_PCMCIA_CD1(slot) (0x08000000 >> (slot << 4))
+#define M8XX_PCMCIA_BVD2(slot) (0x04000000 >> (slot << 4))
+#define M8XX_PCMCIA_BVD1(slot) (0x02000000 >> (slot << 4))
+#define M8XX_PCMCIA_RDY(slot) (0x01000000 >> (slot << 4))
+#define M8XX_PCMCIA_RDY_L(slot) (0x00800000 >> (slot << 4))
+#define M8XX_PCMCIA_RDY_H(slot) (0x00400000 >> (slot << 4))
+#define M8XX_PCMCIA_RDY_R(slot) (0x00200000 >> (slot << 4))
+#define M8XX_PCMCIA_RDY_F(slot) (0x00100000 >> (slot << 4))
+#define M8XX_PCMCIA_MASK(slot) (0xFFFF0000 >> (slot << 4))
+
+#define M8XX_PCMCIA_POR_VALID 0x00000001
+#define M8XX_PCMCIA_POR_WRPROT 0x00000002
+#define M8XX_PCMCIA_POR_ATTRMEM 0x00000010
+#define M8XX_PCMCIA_POR_IO 0x00000018
+#define M8XX_PCMCIA_POR_16BIT 0x00000040
+
+#define M8XX_PGCRX(slot) m8xx_pgcrx[slot]
+
+#define M8XX_PGCRX_CXOE 0x00000080
+#define M8XX_PGCRX_CXRESET 0x00000040
+
+/* we keep one lookup table per socket to check flags */
+
+#define PCMCIA_EVENTS_MAX 5 /* 4 max at a time + termination */
+
+struct event_table {
+ u32 regbit;
+ u32 eventbit;
+};
+
+struct socket_info {
+ void (*handler)(void *info, u32 events);
+ void *info;
+
+ u32 slot;
+
+ socket_state_t state;
+ struct pccard_mem_map mem_win[PCMCIA_MEM_WIN_NO];
+ struct pccard_io_map io_win[PCMCIA_IO_WIN_NO];
+ struct event_table events[PCMCIA_EVENTS_MAX];
+ struct pcmcia_socket socket;
+};
+
+static struct socket_info socket[PCMCIA_SOCKETS_NO];
+
+/*
+ * Search this table to see if the windowsize is
+ * supported...
+ */
+
+#define M8XX_SIZES_NO 32
+
+static const u32 m8xx_size_to_gray[M8XX_SIZES_NO] =
+{
+ 0x00000001, 0x00000002, 0x00000008, 0x00000004,
+ 0x00000080, 0x00000040, 0x00000010, 0x00000020,
+ 0x00008000, 0x00004000, 0x00001000, 0x00002000,
+ 0x00000100, 0x00000200, 0x00000800, 0x00000400,
+
+ 0x0fffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0x01000000, 0x02000000, 0xffffffff, 0x04000000,
+ 0x00010000, 0x00020000, 0x00080000, 0x00040000,
+ 0x00800000, 0x00400000, 0x00100000, 0x00200000
+};
+
+/* ------------------------------------------------------------------------- */
+
+static irqreturn_t m8xx_interrupt(int irq, void *dev, struct pt_regs *regs);
+
+#define PCMCIA_BMT_LIMIT (15*4) /* Bus Monitor Timeout value */
+
+/* ------------------------------------------------------------------------- */
+/* board specific stuff: */
+/* voltage_set(), hardware_enable() and hardware_disable() */
+/* ------------------------------------------------------------------------- */
+/* RPX Boards from Embedded Planet */
+
+#if defined(CONFIG_RPXCLASSIC) || defined(CONFIG_RPXLITE)
+
+/* The RPX boards seems to have it's bus monitor timeout set to 6*8 clocks.
+ * SYPCR is write once only, therefore must the slowest memory be faster
+ * than the bus monitor or we will get a machine check due to the bus timeout.
+ */
+
+#define PCMCIA_BOARD_MSG "RPX CLASSIC or RPX LITE"
+
+#undef PCMCIA_BMT_LIMIT
+#define PCMCIA_BMT_LIMIT (6*8)
+
+static int voltage_set(int slot, int vcc, int vpp)
+{
+ u32 reg = 0;
+
+ switch(vcc) {
+ case 0: break;
+ case 33:
+ reg |= BCSR1_PCVCTL4;
+ break;
+ case 50:
+ reg |= BCSR1_PCVCTL5;
+ break;
+ default:
+ return 1;
+ }
+
+ switch(vpp) {
+ case 0: break;
+ case 33:
+ case 50:
+ if(vcc == vpp)
+ reg |= BCSR1_PCVCTL6;
+ else
+ return 1;
+ break;
+ case 120:
+ reg |= BCSR1_PCVCTL7;
+ default:
+ return 1;
+ }
+
+ if(!((vcc == 50) || (vcc == 0)))
+ return 1;
+
+ /* first, turn off all power */
+
+ out_be32(((u32 *)RPX_CSR_ADDR), in_be32(((u32 *)RPX_CSR_ADDR)) & ~(BCSR1_PCVCTL4 | BCSR1_PCVCTL5 | BCSR1_PCVCTL6 | BCSR1_PCVCTL7));
+
+ /* enable new powersettings */
+
+ out_be32(((u32 *)RPX_CSR_ADDR), in_be32(((u32 *)RPX_CSR_ADDR)) | reg);
+
+ return 0;
+}
+
+#define socket_get(_slot_) PCMCIA_SOCKET_KEY_5V
+#define hardware_enable(_slot_) /* No hardware to enable */
+#define hardware_disable(_slot_) /* No hardware to disable */
+
+#endif /* CONFIG_RPXCLASSIC */
+
+/* FADS Boards from Motorola */
+
+#if defined(CONFIG_FADS)
+
+#define PCMCIA_BOARD_MSG "FADS"
+
+static int voltage_set(int slot, int vcc, int vpp)
+{
+ u32 reg = 0;
+
+ switch(vcc) {
+ case 0:
+ break;
+ case 33:
+ reg |= BCSR1_PCCVCC0;
+ break;
+ case 50:
+ reg |= BCSR1_PCCVCC1;
+ break;
+ default:
+ return 1;
+ }
+
+ switch(vpp) {
+ case 0:
+ break;
+ case 33:
+ case 50:
+ if(vcc == vpp)
+ reg |= BCSR1_PCCVPP1;
+ else
+ return 1;
+ break;
+ case 120:
+ if ((vcc == 33) || (vcc == 50))
+ reg |= BCSR1_PCCVPP0;
+ else
+ return 1;
+ default:
+ return 1;
+ }
+
+ /* first, turn off all power */
+ out_be32(&((u32 *)BCSR1), in_be32(&((u32 *)BCSR1)) & ~(BCSR1_PCCVCC_MASK | BCSR1_PCCVPP_MASK));
+
+ /* enable new powersettings */
+ out_be32(&((u32 *)BCSR1), in_be32(&((u32 *)BCSR1)) | reg);
+
+ return 0;
+}
+
+#define socket_get(_slot_) PCMCIA_SOCKET_KEY_5V
+
+static void hardware_enable(int slot)
+{
+ out_be32(&((u32 *)BCSR1), in_be32(&((u32 *)BCSR1)) & ~BCSR1_PCCEN);
+}
+
+static void hardware_disable(int slot)
+{
+ out_be32(&((u32 *)BCSR1), in_be32(&((u32 *)BCSR1)) | BCSR1_PCCEN);
+}
+
+#endif
+
+/* ------------------------------------------------------------------------- */
+/* Motorola MBX860 */
+
+#if defined(CONFIG_MBX)
+
+#define PCMCIA_BOARD_MSG "MBX"
+
+static int voltage_set(int slot, int vcc, int vpp)
+{
+ u8 reg = 0;
+
+ switch(vcc) {
+ case 0:
+ break;
+ case 33:
+ reg |= CSR2_VCC_33;
+ break;
+ case 50:
+ reg |= CSR2_VCC_50;
+ break;
+ default:
+ return 1;
+ }
+
+ switch(vpp) {
+ case 0:
+ break;
+ case 33:
+ case 50:
+ if(vcc == vpp)
+ reg |= CSR2_VPP_VCC;
+ else
+ return 1;
+ break;
+ case 120:
+ if ((vcc == 33) || (vcc == 50))
+ reg |= CSR2_VPP_12;
+ else
+ return 1;
+ default:
+ return 1;
+ }
+
+ /* first, turn off all power */
+ out_8(&((u8 *)MBX_CSR2_ADDR), in_8(&((u8 *)MBX_CSR2_ADDR)) & ~(CSR2_VCC_MASK | CSR2_VPP_MASK));
+
+ /* enable new powersettings */
+ out_8(&((u8 *)MBX_CSR2_ADDR), in_8(&((u8 *)MBX_CSR2_ADDR)) | reg);
+
+ return 0;
+}
+
+#define socket_get(_slot_) PCMCIA_SOCKET_KEY_5V
+#define hardware_enable(_slot_) /* No hardware to enable */
+#define hardware_disable(_slot_) /* No hardware to disable */
+
+#endif /* CONFIG_MBX */
+
+#if defined(CONFIG_PRxK)
+#include <asm/cpld.h>
+extern volatile fpga_pc_regs *fpga_pc;
+
+#define PCMCIA_BOARD_MSG "MPC855T"
+
+static int voltage_set(int slot, int vcc, int vpp)
+{
+ u8 reg = 0;
+ u8 regread;
+ cpld_regs *ccpld = get_cpld();
+
+ switch(vcc) {
+ case 0:
+ break;
+ case 33:
+ reg |= PCMCIA_VCC_33;
+ break;
+ case 50:
+ reg |= PCMCIA_VCC_50;
+ break;
+ default:
+ return 1;
+ }
+
+ switch(vpp) {
+ case 0:
+ break;
+ case 33:
+ case 50:
+ if(vcc == vpp)
+ reg |= PCMCIA_VPP_VCC;
+ else
+ return 1;
+ break;
+ case 120:
+ if ((vcc == 33) || (vcc == 50))
+ reg |= PCMCIA_VPP_12;
+ else
+ return 1;
+ default:
+ return 1;
+ }
+
+ reg = reg >> (slot << 2);
+ regread = in_8(&ccpld->fpga_pc_ctl);
+ if (reg != (regread & ((PCMCIA_VCC_MASK | PCMCIA_VPP_MASK) >> (slot << 2)))) {
+ /* enable new powersettings */
+ regread = regread & ~((PCMCIA_VCC_MASK | PCMCIA_VPP_MASK) >> (slot << 2));
+ out_8(&ccpld->fpga_pc_ctl, reg | regread);
+ msleep(100);
+ }
+
+ return 0;
+}
+
+#define socket_get(_slot_) PCMCIA_SOCKET_KEY_LV
+#define hardware_enable(_slot_) /* No hardware to enable */
+#define hardware_disable(_slot_) /* No hardware to disable */
+
+#endif /* CONFIG_PRxK */
+
+static void m8xx_shutdown(void)
+{
+ u32 m, i;
+ struct pcmcia_win *w;
+
+ for(i = 0; i < PCMCIA_SOCKETS_NO; i++){
+ w = (void *) &((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pbr0;
+
+ out_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pscr, M8XX_PCMCIA_MASK(i));
+ out_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_per, in_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_per) & ~M8XX_PCMCIA_MASK(i));
+
+ /* turn off interrupt and disable CxOE */
+ out_be32(M8XX_PGCRX(i), M8XX_PGCRX_CXOE);
+
+ /* turn off memory windows */
+ for(m = 0; m < PCMCIA_MEM_WIN_NO; m++) {
+ out_be32(&w->or, 0); /* set to not valid */
+ w++;
+ }
+
+ /* turn off voltage */
+ voltage_set(i, 0, 0);
+
+ /* disable external hardware */
+ hardware_disable(i);
+ }
+
+ free_irq(pcmcia_schlvl, NULL);
+}
+
+/* copied from tcic.c */
+
+static int m8xx_drv_suspend(struct device *dev, pm_message_t state, u32 level)
+{
+ int ret = 0;
+ if (level == SUSPEND_SAVE_STATE)
+ ret = pcmcia_socket_dev_suspend(dev, state);
+ return ret;
+}
+
+static int m8xx_drv_resume(struct device *dev, u32 level)
+{
+ int ret = 0;
+ if (level == RESUME_RESTORE_STATE)
+ ret = pcmcia_socket_dev_resume(dev);
+ return ret;
+}
+
+static struct device_driver m8xx_driver = {
+ .name = "m8xx-pcmcia",
+ .bus = &platform_bus_type,
+ .suspend = m8xx_drv_suspend,
+ .resume = m8xx_drv_resume,
+};
+
+static struct platform_device m8xx_device = {
+ .name = "m8xx-pcmcia",
+ .id = 0,
+};
+
+static u32 pending_events[PCMCIA_SOCKETS_NO];
+static spinlock_t pending_event_lock = SPIN_LOCK_UNLOCKED;
+
+static irqreturn_t m8xx_interrupt(int irq, void *dev, struct pt_regs *regs)
+{
+ struct socket_info *s;
+ struct event_table *e;
+ unsigned int i, events, pscr, pipr, per;
+
+ dprintk("Interrupt!\n");
+ /* get interrupt sources */
+
+ pscr = in_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pscr);
+ pipr = in_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pipr);
+ per = in_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_per);
+
+ for(i = 0; i < PCMCIA_SOCKETS_NO; i++) {
+ s = &socket[i];
+ e = &s->events[0];
+ events = 0;
+
+ while(e->regbit) {
+ if(pscr & e->regbit)
+ events |= e->eventbit;
+
+ e++;
+ }
+
+ /*
+ * report only if both card detect signals are the same
+ * not too nice done,
+ * we depend on that CD2 is the bit to the left of CD1...
+ */
+ if(events & SS_DETECT)
+ if(((pipr & M8XX_PCMCIA_CD2(i)) >> 1) ^
+ (pipr & M8XX_PCMCIA_CD1(i)))
+ {
+ events &= ~SS_DETECT;
+ }
+
+#ifdef PCMCIA_GLITCHY_CD
+ /*
+ * I've experienced CD problems with my ADS board.
+ * We make an extra check to see if there was a
+ * real change of Card detection.
+ */
+
+ if((events & SS_DETECT) &&
+ ((pipr &
+ (M8XX_PCMCIA_CD2(i) | M8XX_PCMCIA_CD1(i))) == 0) &&
+ (s->state.Vcc | s->state.Vpp)) {
+ events &= ~SS_DETECT;
+ /*printk( "CD glitch workaround - CD = 0x%08x!\n",
+ (pipr & (M8XX_PCMCIA_CD2(i)
+ | M8XX_PCMCIA_CD1(i))));*/
+ }
+#endif
+
+ /* call the handler */
+
+ dprintk("slot %u: events = 0x%02x, pscr = 0x%08x, "
+ "pipr = 0x%08x\n",
+ i, events, pscr, pipr);
+
+ if(events) {
+ spin_lock(&pending_event_lock);
+ pending_events[i] |= events;
+ spin_unlock(&pending_event_lock);
+ /*
+ * Turn off RDY_L bits in the PER mask on
+ * CD interrupt receival.
+ *
+ * They can generate bad interrupts on the
+ * ACS4,8,16,32. - marcelo
+ */
+ per &= ~M8XX_PCMCIA_RDY_L(0);
+ per &= ~M8XX_PCMCIA_RDY_L(1);
+
+ out_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_per, per);
+
+ if (events)
+ pcmcia_parse_events(&socket[i].socket, events);
+ }
+ }
+
+ /* clear the interrupt sources */
+ out_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pscr, pscr);
+
+ dprintk("Interrupt done.\n");
+
+ return IRQ_HANDLED;
+}
+
+static u32 m8xx_get_graycode(u32 size)
+{
+ u32 k;
+
+ for(k = 0; k < M8XX_SIZES_NO; k++)
+ if(m8xx_size_to_gray[k] == size)
+ break;
+
+ if((k == M8XX_SIZES_NO) || (m8xx_size_to_gray[k] == -1))
+ k = -1;
+
+ return k;
+}
+
+static u32 m8xx_get_speed(u32 ns, u32 is_io)
+{
+ u32 reg, clocks, psst, psl, psht;
+
+ if(!ns) {
+
+ /*
+ * We get called with IO maps setup to 0ns
+ * if not specified by the user.
+ * They should be 255ns.
+ */
+
+ if(is_io)
+ ns = 255;
+ else
+ ns = 100; /* fast memory if 0 */
+ }
+
+ /*
+ * In PSST, PSL, PSHT fields we tell the controller
+ * timing parameters in CLKOUT clock cycles.
+ * CLKOUT is the same as GCLK2_50.
+ */
+
+/* how we want to adjust the timing - in percent */
+
+#define ADJ 180 /* 80 % longer accesstime - to be sure */
+
+ clocks = ((M8XX_BUSFREQ / 1000) * ns) / 1000;
+ clocks = (clocks * ADJ) / (100*1000);
+ if(clocks >= PCMCIA_BMT_LIMIT) {
+ printk( "Max access time limit reached\n");
+ clocks = PCMCIA_BMT_LIMIT-1;
+ }
+
+ psst = clocks / 7; /* setup time */
+ psht = clocks / 7; /* hold time */
+ psl = (clocks * 5) / 7; /* strobe length */
+
+ psst += clocks - (psst + psht + psl);
+
+ reg = psst << 12;
+ reg |= psl << 7;
+ reg |= psht << 16;
+
+ return reg;
+}
+
+static int m8xx_get_status(struct pcmcia_socket *sock, unsigned int *value)
+{
+ int lsock = container_of(sock, struct socket_info, socket)->slot;
+ struct socket_info *s = &socket[lsock];
+ unsigned int pipr, reg;
+
+ pipr = in_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pipr);
+
+ *value = ((pipr & (M8XX_PCMCIA_CD1(lsock)
+ | M8XX_PCMCIA_CD2(lsock))) == 0) ? SS_DETECT : 0;
+ *value |= (pipr & M8XX_PCMCIA_WP(lsock)) ? SS_WRPROT : 0;
+
+ if (s->state.flags & SS_IOCARD)
+ *value |= (pipr & M8XX_PCMCIA_BVD1(lsock)) ? SS_STSCHG : 0;
+ else {
+ *value |= (pipr & M8XX_PCMCIA_RDY(lsock)) ? SS_READY : 0;
+ *value |= (pipr & M8XX_PCMCIA_BVD1(lsock)) ? SS_BATDEAD : 0;
+ *value |= (pipr & M8XX_PCMCIA_BVD2(lsock)) ? SS_BATWARN : 0;
+ }
+
+ if (s->state.Vcc | s->state.Vpp)
+ *value |= SS_POWERON;
+
+ /*
+ * Voltage detection:
+ * This driver only supports 16-Bit pc-cards.
+ * Cardbus is not handled here.
+ *
+ * To determine what voltage to use we must read the VS1 and VS2 pin.
+ * Depending on what socket type is present,
+ * different combinations mean different things.
+ *
+ * Card Key Socket Key VS1 VS2 Card Vcc for CIS parse
+ *
+ * 5V 5V, LV* NC NC 5V only 5V (if available)
+ *
+ * 5V 5V, LV* GND NC 5 or 3.3V as low as possible
+ *
+ * 5V 5V, LV* GND GND 5, 3.3, x.xV as low as possible
+ *
+ * LV* 5V - - shall not fit into socket
+ *
+ * LV* LV* GND NC 3.3V only 3.3V
+ *
+ * LV* LV* NC GND x.xV x.xV (if avail.)
+ *
+ * LV* LV* GND GND 3.3 or x.xV as low as possible
+ *
+ * *LV means Low Voltage
+ *
+ *
+ * That gives us the following table:
+ *
+ * Socket VS1 VS2 Voltage
+ *
+ * 5V NC NC 5V
+ * 5V NC GND none (should not be possible)
+ * 5V GND NC >= 3.3V
+ * 5V GND GND >= x.xV
+ *
+ * LV NC NC 5V (if available)
+ * LV NC GND x.xV (if available)
+ * LV GND NC 3.3V
+ * LV GND GND >= x.xV
+ *
+ * So, how do I determine if I have a 5V or a LV
+ * socket on my board? Look at the socket!
+ *
+ *
+ * Socket with 5V key:
+ * ++--------------------------------------------+
+ * || |
+ * || ||
+ * || ||
+ * | |
+ * +---------------------------------------------+
+ *
+ * Socket with LV key:
+ * ++--------------------------------------------+
+ * || |
+ * | ||
+ * | ||
+ * | |
+ * +---------------------------------------------+
+ *
+ *
+ * With other words - LV only cards does not fit
+ * into the 5V socket!
+ */
+
+ /* read out VS1 and VS2 */
+
+ reg = (pipr & M8XX_PCMCIA_VS_MASK(lsock))
+ >> M8XX_PCMCIA_VS_SHIFT(lsock);
+
+ if(socket_get(lsock) == PCMCIA_SOCKET_KEY_LV) {
+ switch(reg) {
+ case 1:
+ *value |= SS_3VCARD;
+ break; /* GND, NC - 3.3V only */
+ case 2:
+ *value |= SS_XVCARD;
+ break; /* NC. GND - x.xV only */
+ };
+ }
+
+ dprintk("GetStatus(%d) = %#2.2x\n", lsock, *value);
+ return 0;
+}
+
+static int m8xx_get_socket(struct pcmcia_socket *sock, socket_state_t *state)
+{
+ int lsock = container_of(sock, struct socket_info, socket)->slot;
+ *state = socket[lsock].state; /* copy the whole structure */
+
+ dprintk("GetSocket(%d) = flags %#3.3x, Vcc %d, Vpp %d, "
+ "io_irq %d, csc_mask %#2.2x\n", lsock, state->flags,
+ state->Vcc, state->Vpp, state->io_irq, state->csc_mask);
+ return 0;
+}
+
+static int m8xx_set_socket(struct pcmcia_socket *sock, socket_state_t *state)
+{
+ int lsock = container_of(sock, struct socket_info, socket)->slot;
+ struct socket_info *s = &socket[lsock];
+ struct event_table *e;
+ unsigned int reg;
+ unsigned long flags;
+
+ dprintk( "SetSocket(%d, flags %#3.3x, Vcc %d, Vpp %d, "
+ "io_irq %d, csc_mask %#2.2x)\n", lsock, state->flags,
+ state->Vcc, state->Vpp, state->io_irq, state->csc_mask);
+
+ /* First, set voltage - bail out if invalid */
+ if(voltage_set(lsock, state->Vcc, state->Vpp))
+ return -EINVAL;
+
+ /* Take care of reset... */
+ if(state->flags & SS_RESET)
+ out_be32(M8XX_PGCRX(lsock), in_be32(M8XX_PGCRX(lsock)) | M8XX_PGCRX_CXRESET); /* active high */
+ else
+ out_be32(M8XX_PGCRX(lsock), in_be32(M8XX_PGCRX(lsock)) & ~M8XX_PGCRX_CXRESET);
+
+ /* ... and output enable. */
+
+ /* The CxOE signal is connected to a 74541 on the ADS.
+ I guess most other boards used the ADS as a reference.
+ I tried to control the CxOE signal with SS_OUTPUT_ENA,
+ but the reset signal seems connected via the 541.
+ If the CxOE is left high are some signals tristated and
+ no pullups are present -> the cards act wierd.
+ So right now the buffers are enabled if the power is on. */
+
+ if(state->Vcc || state->Vpp)
+ out_be32(M8XX_PGCRX(lsock), in_be32(M8XX_PGCRX(lsock)) & ~M8XX_PGCRX_CXOE); /* active low */
+ else
+ out_be32(M8XX_PGCRX(lsock), in_be32(M8XX_PGCRX(lsock)) | M8XX_PGCRX_CXOE);
+
+ /*
+ * We'd better turn off interrupts before
+ * we mess with the events-table..
+ */
+
+ spin_lock_irqsave(&events_lock, flags);
+
+ /*
+ * Play around with the interrupt mask to be able to
+ * give the events the generic pcmcia driver wants us to.
+ */
+
+ e = &s->events[0];
+ reg = 0;
+
+ if(state->csc_mask & SS_DETECT) {
+ e->eventbit = SS_DETECT;
+ reg |= e->regbit = (M8XX_PCMCIA_CD2(lsock)
+ | M8XX_PCMCIA_CD1(lsock));
+ e++;
+ }
+ if(state->flags & SS_IOCARD) {
+ /*
+ * I/O card
+ */
+ if(state->csc_mask & SS_STSCHG) {
+ e->eventbit = SS_STSCHG;
+ reg |= e->regbit = M8XX_PCMCIA_BVD1(lsock);
+ e++;
+ }
+ /*
+ * If io_irq is non-zero we should enable irq.
+ */
+ if(state->io_irq) {
+ out_be32(M8XX_PGCRX(lsock), in_be32(M8XX_PGCRX(lsock)) | mk_int_int_mask(state->io_irq) << 24);
+ /*
+ * Strange thing here:
+ * The manual does not tell us which interrupt
+ * the sources generate.
+ * Anyhow, I found out that RDY_L generates IREQLVL.
+ *
+ * We use level triggerd interrupts, and they don't
+ * have to be cleared in PSCR in the interrupt handler.
+ */
+ reg |= M8XX_PCMCIA_RDY_L(lsock);
+ }
+ else
+ out_be32(M8XX_PGCRX(lsock), in_be32(M8XX_PGCRX(lsock)) & 0x00ffffff);
+ }
+ else {
+ /*
+ * Memory card
+ */
+ if(state->csc_mask & SS_BATDEAD) {
+ e->eventbit = SS_BATDEAD;
+ reg |= e->regbit = M8XX_PCMCIA_BVD1(lsock);
+ e++;
+ }
+ if(state->csc_mask & SS_BATWARN) {
+ e->eventbit = SS_BATWARN;
+ reg |= e->regbit = M8XX_PCMCIA_BVD2(lsock);
+ e++;
+ }
+ /* What should I trigger on - low/high,raise,fall? */
+ if(state->csc_mask & SS_READY) {
+ e->eventbit = SS_READY;
+ reg |= e->regbit = 0; //??
+ e++;
+ }
+ }
+
+ e->regbit = 0; /* terminate list */
+
+ /*
+ * Clear the status changed .
+ * Port A and Port B share the same port.
+ * Writing ones will clear the bits.
+ */
+
+ out_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pscr, reg);
+
+ /*
+ * Write the mask.
+ * Port A and Port B share the same port.
+ * Need for read-modify-write.
+ * Ones will enable the interrupt.
+ */
+
+ /*
+ reg |= ((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_per
+ & M8XX_PCMCIA_MASK(lsock);
+ */
+
+ reg |= in_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_per) &
+ (M8XX_PCMCIA_MASK(0) | M8XX_PCMCIA_MASK(1));
+
+ out_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_per, reg);
+
+ spin_unlock_irqrestore(&events_lock, flags);
+
+ /* copy the struct and modify the copy */
+
+ s->state = *state;
+
+ return 0;
+}
+
+static int m8xx_set_io_map(struct pcmcia_socket *sock, struct pccard_io_map *io)
+{
+ int lsock = container_of(sock, struct socket_info, socket)->slot;
+
+ struct socket_info *s = &socket[lsock];
+ struct pcmcia_win *w;
+ unsigned int reg, winnr;
+
+#define M8XX_SIZE (io->stop - io->start + 1)
+#define M8XX_BASE (PCMCIA_IO_WIN_BASE + io->start)
+
+ dprintk( "SetIOMap(%d, %d, %#2.2x, %d ns, "
+ "%#4.4x-%#4.4x)\n", lsock, io->map, io->flags,
+ io->speed, io->start, io->stop);
+
+ if ((io->map >= PCMCIA_IO_WIN_NO) || (io->start > 0xffff)
+ || (io->stop > 0xffff) || (io->stop < io->start))
+ return -EINVAL;
+
+ if((reg = m8xx_get_graycode(M8XX_SIZE)) == -1)
+ return -EINVAL;
+
+ if(io->flags & MAP_ACTIVE) {
+
+ dprintk( "io->flags & MAP_ACTIVE\n");
+
+ winnr = (PCMCIA_MEM_WIN_NO * PCMCIA_SOCKETS_NO)
+ + (lsock * PCMCIA_IO_WIN_NO) + io->map;
+
+ /* setup registers */
+
+ w = (void *) &((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pbr0;
+ w += winnr;
+
+ out_be32(&w->or, 0); /* turn off window first */
+ out_be32(&w->br, M8XX_BASE);
+
+ reg <<= 27;
+ reg |= M8XX_PCMCIA_POR_IO |(lsock << 2);
+
+ reg |= m8xx_get_speed(io->speed, 1);
+
+ if(io->flags & MAP_WRPROT)
+ reg |= M8XX_PCMCIA_POR_WRPROT;
+
+ /*if(io->flags & (MAP_16BIT | MAP_AUTOSZ))*/
+ if(io->flags & MAP_16BIT)
+ reg |= M8XX_PCMCIA_POR_16BIT;
+
+ if(io->flags & MAP_ACTIVE)
+ reg |= M8XX_PCMCIA_POR_VALID;
+
+ out_be32(&w->or, reg);
+
+ dprintk("Socket %u: Mapped io window %u at %#8.8x, "
+ "OR = %#8.8x.\n", lsock, io->map, w->br, w->or);
+ } else {
+ /* shutdown IO window */
+ winnr = (PCMCIA_MEM_WIN_NO * PCMCIA_SOCKETS_NO)
+ + (lsock * PCMCIA_IO_WIN_NO) + io->map;
+
+ /* setup registers */
+
+ w = (void *) &((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pbr0;
+ w += winnr;
+
+ out_be32(&w->or, 0); /* turn off window */
+ out_be32(&w->br, 0); /* turn off base address */
+
+ dprintk("Socket %u: Unmapped io window %u at %#8.8x, "
+ "OR = %#8.8x.\n", lsock, io->map, w->br, w->or);
+ }
+
+ /* copy the struct and modify the copy */
+ s->io_win[io->map] = *io;
+ s->io_win[io->map].flags &= (MAP_WRPROT
+ | MAP_16BIT
+ | MAP_ACTIVE);
+ dprintk("SetIOMap exit\n");
+
+ return 0;
+}
+
+static int m8xx_set_mem_map(struct pcmcia_socket *sock, struct pccard_mem_map *mem)
+{
+ int lsock = container_of(sock, struct socket_info, socket)->slot;
+ struct socket_info *s = &socket[lsock];
+ struct pcmcia_win *w;
+ struct pccard_mem_map *old;
+ unsigned int reg, winnr;
+
+ dprintk( "SetMemMap(%d, %d, %#2.2x, %d ns, "
+ "%#5.5lx, %#5.5x)\n", lsock, mem->map, mem->flags,
+ mem->speed, mem->static_start, mem->card_start);
+
+ if ((mem->map >= PCMCIA_MEM_WIN_NO)
+// || ((mem->s) >= PCMCIA_MEM_WIN_SIZE)
+ || (mem->card_start >= 0x04000000)
+ || (mem->static_start & 0xfff) /* 4KByte resolution */
+ || (mem->card_start & 0xfff))
+ return -EINVAL;
+
+ if((reg = m8xx_get_graycode(PCMCIA_MEM_WIN_SIZE)) == -1) {
+ printk( "Cannot set size to 0x%08x.\n", PCMCIA_MEM_WIN_SIZE);
+ return -EINVAL;
+ }
+ reg <<= 27;
+
+ winnr = (lsock * PCMCIA_MEM_WIN_NO) + mem->map;
+
+ /* Setup the window in the pcmcia controller */
+
+ w = (void *) &((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pbr0;
+ w += winnr;
+
+ reg |= lsock << 2;
+
+ reg |= m8xx_get_speed(mem->speed, 0);
+
+ if(mem->flags & MAP_ATTRIB)
+ reg |= M8XX_PCMCIA_POR_ATTRMEM;
+
+ if(mem->flags & MAP_WRPROT)
+ reg |= M8XX_PCMCIA_POR_WRPROT;
+
+ if(mem->flags & MAP_16BIT)
+ reg |= M8XX_PCMCIA_POR_16BIT;
+
+ if(mem->flags & MAP_ACTIVE)
+ reg |= M8XX_PCMCIA_POR_VALID;
+
+ out_be32(&w->or, reg);
+
+ dprintk("Socket %u: Mapped memory window %u at %#8.8x, "
+ "OR = %#8.8x.\n", lsock, mem->map, w->br, w->or);
+
+ if(mem->flags & MAP_ACTIVE) {
+ /* get the new base address */
+ mem->static_start = PCMCIA_MEM_WIN_BASE +
+ (PCMCIA_MEM_WIN_SIZE * winnr)
+ + mem->card_start;
+ }
+
+ dprintk("SetMemMap(%d, %d, %#2.2x, %d ns, "
+ "%#5.5lx, %#5.5x)\n", lsock, mem->map, mem->flags,
+ mem->speed, mem->static_start, mem->card_start);
+
+ /* copy the struct and modify the copy */
+
+ old = &s->mem_win[mem->map];
+
+ *old = *mem;
+ old->flags &= (MAP_ATTRIB
+ | MAP_WRPROT
+ | MAP_16BIT
+ | MAP_ACTIVE);
+
+ return 0;
+}
+
+static int m8xx_sock_init(struct pcmcia_socket *sock)
+{
+ int i;
+ pccard_io_map io = { 0, 0, 0, 0, 1 };
+ pccard_mem_map mem = { 0, 0, 0, 0, 0, 0 };
+
+ dprintk( "sock_init(%d)\n", s);
+
+ m8xx_set_socket(sock, &dead_socket);
+ for (i = 0; i < PCMCIA_IO_WIN_NO; i++) {
+ io.map = i;
+ m8xx_set_io_map(sock, &io);
+ }
+ for (i = 0; i < PCMCIA_MEM_WIN_NO; i++) {
+ mem.map = i;
+ m8xx_set_mem_map(sock, &mem);
+ }
+
+ return 0;
+
+}
+
+static int m8xx_suspend(struct pcmcia_socket *sock)
+{
+ return m8xx_set_socket(sock, &dead_socket);
+}
+
+static struct pccard_operations m8xx_services = {
+ .init = m8xx_sock_init,
+ .suspend = m8xx_suspend,
+ .get_status = m8xx_get_status,
+ .get_socket = m8xx_get_socket,
+ .set_socket = m8xx_set_socket,
+ .set_io_map = m8xx_set_io_map,
+ .set_mem_map = m8xx_set_mem_map,
+};
+
+static int __init m8xx_init(void)
+{
+ struct pcmcia_win *w;
+ unsigned int i,m;
+
+ pcmcia_info("%s\n", version);
+
+ if (driver_register(&m8xx_driver))
+ return -1;
+
+ pcmcia_info(PCMCIA_BOARD_MSG " using " PCMCIA_SLOT_MSG
+ " with IRQ %u.\n", pcmcia_schlvl);
+
+ /* Configure Status change interrupt */
+
+ if(request_irq(pcmcia_schlvl, m8xx_interrupt, 0,
+ "m8xx_pcmcia", NULL)) {
+ pcmcia_error("Cannot allocate IRQ %u for SCHLVL!\n",
+ pcmcia_schlvl);
+ return -1;
+ }
+
+ w = (void *) &((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pbr0;
+
+ out_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pscr,
+ M8XX_PCMCIA_MASK(0)| M8XX_PCMCIA_MASK(1));
+
+ out_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_per,
+ in_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_per) &
+ ~(M8XX_PCMCIA_MASK(0)| M8XX_PCMCIA_MASK(1)));
+
+/* connect interrupt and disable CxOE */
+
+ out_be32(M8XX_PGCRX(0), M8XX_PGCRX_CXOE | (mk_int_int_mask(pcmcia_schlvl) << 16));
+ out_be32(M8XX_PGCRX(1), M8XX_PGCRX_CXOE | (mk_int_int_mask(pcmcia_schlvl) << 16));
+
+/* intialize the fixed memory windows */
+
+ for(i = 0; i < PCMCIA_SOCKETS_NO; i++){
+ for(m = 0; m < PCMCIA_MEM_WIN_NO; m++) {
+ out_be32(&w->br, PCMCIA_MEM_WIN_BASE +
+ (PCMCIA_MEM_WIN_SIZE
+ * (m + i * PCMCIA_MEM_WIN_NO)));
+
+ out_be32(&w->or, 0); /* set to not valid */
+
+ w++;
+ }
+ }
+
+/* turn off voltage */
+ voltage_set(0, 0, 0);
+ voltage_set(1, 0, 0);
+
+/* Enable external hardware */
+ hardware_enable(0);
+ hardware_enable(1);
+
+ platform_device_register(&m8xx_device);
+
+ for (i = 0 ; i < PCMCIA_SOCKETS_NO; i++) {
+ socket[i].slot = i;
+ socket[i].socket.owner = THIS_MODULE;
+ socket[i].socket.features = SS_CAP_PCCARD | SS_CAP_MEM_ALIGN | SS_CAP_STATIC_MAP;
+ socket[i].socket.irq_mask = 0x000;
+ socket[i].socket.map_size = 0x1000;
+ socket[i].socket.io_offset = 0;
+ socket[i].socket.pci_irq = i ? 7 : 9;
+ socket[i].socket.ops = &m8xx_services;
+ socket[i].socket.resource_ops = &pccard_nonstatic_ops;
+ socket[i].socket.cb_dev = NULL;
+ socket[i].socket.dev.dev = &m8xx_device.dev;
+ }
+
+ for (i = 0; i < PCMCIA_SOCKETS_NO; i++)
+ pcmcia_register_socket(&socket[i].socket);
+
+ return 0;
+}
+
+static void __exit m8xx_exit(void)
+{
+ int i;
+
+ for (i = 0; i < PCMCIA_SOCKETS_NO; i++)
+ pcmcia_unregister_socket(&socket[i].socket);
+
+ m8xx_shutdown();
+
+ platform_device_unregister(&m8xx_device);
+ driver_unregister(&m8xx_driver);
+}
+
+module_init(m8xx_init);
+module_exit(m8xx_exit);
diff -puN drivers/pcmcia/Makefile~mpc8xx-pcmcia-driver drivers/pcmcia/Makefile
--- devel/drivers/pcmcia/Makefile~mpc8xx-pcmcia-driver 2005-10-28 17:44:02.000000000 -0700
+++ devel-akpm/drivers/pcmcia/Makefile 2005-10-28 17:44:02.000000000 -0700
@@ -25,6 +25,7 @@ obj-$(CONFIG_PD6729) += pd6729.o
obj-$(CONFIG_I82365) += i82365.o
obj-$(CONFIG_I82092) += i82092.o
obj-$(CONFIG_TCIC) += tcic.o
+obj-$(CONFIG_PCMCIA_M8XX) += m8xx_pcmcia.o
obj-$(CONFIG_HD64465_PCMCIA) += hd64465_ss.o
obj-$(CONFIG_PCMCIA_SA1100) += sa11xx_core.o sa1100_cs.o
obj-$(CONFIG_PCMCIA_SA1111) += sa11xx_core.o sa1111_cs.o
_
^ permalink raw reply
* [patch 02/43] ppc32 8xx: use io accessor macros instead of direct memory reference
From: akpm @ 2005-10-29 0:46 UTC (permalink / raw)
To: paulus; +Cc: akpm, linuxppc-dev, linuxppc64-dev
From: Marcelo Tosatti <marcelo.tosatti@cyclades.com>
Convert core 8xx drivers to use in_xxxbe/in_xxx macros instead of direct
memory references.
Other than making IO accesses explicit (which is a plus for readability), a
common set of macros provides a unified place for the volatile flag to
constraint compiler code reordering.
There are several unlucky places at the moment which lack the volatile
flag.
Signed-off-by: Marcelo Tosatti <marcelo.tosatti@cyclades.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
---
arch/ppc/8xx_io/commproc.c | 20 +++++++++----------
arch/ppc/syslib/m8xx_setup.c | 45 +++++++++++++++++++------------------------
arch/ppc/syslib/m8xx_wdt.c | 14 ++++++-------
arch/ppc/syslib/ppc8xx_pic.c | 17 ++++++----------
4 files changed, 44 insertions(+), 52 deletions(-)
diff -puN arch/ppc/8xx_io/commproc.c~ppc32-8xx-use-io-accessor-macros-instead-of-direct-memory-reference arch/ppc/8xx_io/commproc.c
--- devel/arch/ppc/8xx_io/commproc.c~ppc32-8xx-use-io-accessor-macros-instead-of-direct-memory-reference 2005-10-28 17:44:02.000000000 -0700
+++ devel-akpm/arch/ppc/8xx_io/commproc.c 2005-10-28 17:44:02.000000000 -0700
@@ -73,7 +73,7 @@ cpm_mask_irq(unsigned int irq)
{
int cpm_vec = irq - CPM_IRQ_OFFSET;
- ((immap_t *)IMAP_ADDR)->im_cpic.cpic_cimr &= ~(1 << cpm_vec);
+ out_be32(&((immap_t *)IMAP_ADDR)->im_cpic.cpic_cimr, in_be32(&((immap_t *)IMAP_ADDR)->im_cpic.cpic_cimr) & ~(1 << cpm_vec));
}
static void
@@ -81,7 +81,7 @@ cpm_unmask_irq(unsigned int irq)
{
int cpm_vec = irq - CPM_IRQ_OFFSET;
- ((immap_t *)IMAP_ADDR)->im_cpic.cpic_cimr |= (1 << cpm_vec);
+ out_be32(&((immap_t *)IMAP_ADDR)->im_cpic.cpic_cimr, in_be32(&((immap_t *)IMAP_ADDR)->im_cpic.cpic_cimr) | (1 << cpm_vec));
}
static void
@@ -95,7 +95,7 @@ cpm_eoi(unsigned int irq)
{
int cpm_vec = irq - CPM_IRQ_OFFSET;
- ((immap_t *)IMAP_ADDR)->im_cpic.cpic_cisr = (1 << cpm_vec);
+ out_be32(&((immap_t *)IMAP_ADDR)->im_cpic.cpic_cisr, (1 << cpm_vec));
}
struct hw_interrupt_type cpm_pic = {
@@ -133,7 +133,7 @@ m8xx_cpm_reset(void)
* manual recommends it.
* Bit 25, FAM can also be set to use FEC aggressive mode (860T).
*/
- imp->im_siu_conf.sc_sdcr = 1;
+ out_be32(&imp->im_siu_conf.sc_sdcr, 1),
/* Reclaim the DP memory for our use. */
m8xx_cpm_dpinit();
@@ -178,10 +178,10 @@ cpm_interrupt_init(void)
/* Initialize the CPM interrupt controller.
*/
- ((immap_t *)IMAP_ADDR)->im_cpic.cpic_cicr =
+ out_be32(&((immap_t *)IMAP_ADDR)->im_cpic.cpic_cicr,
(CICR_SCD_SCC4 | CICR_SCC_SCC3 | CICR_SCB_SCC2 | CICR_SCA_SCC1) |
- ((CPM_INTERRUPT/2) << 13) | CICR_HP_MASK;
- ((immap_t *)IMAP_ADDR)->im_cpic.cpic_cimr = 0;
+ ((CPM_INTERRUPT/2) << 13) | CICR_HP_MASK);
+ out_be32(&((immap_t *)IMAP_ADDR)->im_cpic.cpic_cimr, 0);
/* install the CPM interrupt controller routines for the CPM
* interrupt vectors
@@ -198,7 +198,7 @@ cpm_interrupt_init(void)
if (setup_irq(CPM_IRQ_OFFSET + CPMVEC_ERROR, &cpm_error_irqaction))
panic("Could not allocate CPM error IRQ!");
- ((immap_t *)IMAP_ADDR)->im_cpic.cpic_cicr |= CICR_IEN;
+ out_be32(&((immap_t *)IMAP_ADDR)->im_cpic.cpic_cicr, in_be32(&((immap_t *)IMAP_ADDR)->im_cpic.cpic_cicr) | CICR_IEN);
}
/*
@@ -212,8 +212,8 @@ cpm_get_irq(struct pt_regs *regs)
/* Get the vector by setting the ACK bit and then reading
* the register.
*/
- ((volatile immap_t *)IMAP_ADDR)->im_cpic.cpic_civr = 1;
- cpm_vec = ((volatile immap_t *)IMAP_ADDR)->im_cpic.cpic_civr;
+ out_be16(&((volatile immap_t *)IMAP_ADDR)->im_cpic.cpic_civr, 1);
+ cpm_vec = in_be16(&((volatile immap_t *)IMAP_ADDR)->im_cpic.cpic_civr);
cpm_vec >>= 11;
return cpm_vec;
diff -puN arch/ppc/syslib/m8xx_setup.c~ppc32-8xx-use-io-accessor-macros-instead-of-direct-memory-reference arch/ppc/syslib/m8xx_setup.c
--- devel/arch/ppc/syslib/m8xx_setup.c~ppc32-8xx-use-io-accessor-macros-instead-of-direct-memory-reference 2005-10-28 17:44:02.000000000 -0700
+++ devel-akpm/arch/ppc/syslib/m8xx_setup.c 2005-10-28 17:45:23.000000000 -0700
@@ -144,12 +144,12 @@ void __init m8xx_calibrate_decr(void)
int freq, fp, divisor;
/* Unlock the SCCR. */
- ((volatile immap_t *)IMAP_ADDR)->im_clkrstk.cark_sccrk = ~KAPWR_KEY;
- ((volatile immap_t *)IMAP_ADDR)->im_clkrstk.cark_sccrk = KAPWR_KEY;
+ out_be32(&((immap_t *)IMAP_ADDR)->im_clkrstk.cark_sccrk, ~KAPWR_KEY);
+ out_be32(&((immap_t *)IMAP_ADDR)->im_clkrstk.cark_sccrk, KAPWR_KEY);
/* Force all 8xx processors to use divide by 16 processor clock. */
- ((volatile immap_t *)IMAP_ADDR)->im_clkrst.car_sccr |= 0x02000000;
-
+ out_be32(&((immap_t *)IMAP_ADDR)->im_clkrst.car_sccr,
+ in_be32(&((immap_t *)IMAP_ADDR)->im_clkrst.car_sccr)|0x02000000);
/* Processor frequency is MHz.
* The value 'fp' is the number of decrementer ticks per second.
*/
@@ -175,28 +175,24 @@ void __init m8xx_calibrate_decr(void)
* we guarantee the registers are locked, then we unlock them
* for our use.
*/
- ((volatile immap_t *)IMAP_ADDR)->im_sitk.sitk_tbscrk = ~KAPWR_KEY;
- ((volatile immap_t *)IMAP_ADDR)->im_sitk.sitk_rtcsck = ~KAPWR_KEY;
- ((volatile immap_t *)IMAP_ADDR)->im_sitk.sitk_tbk = ~KAPWR_KEY;
- ((volatile immap_t *)IMAP_ADDR)->im_sitk.sitk_tbscrk = KAPWR_KEY;
- ((volatile immap_t *)IMAP_ADDR)->im_sitk.sitk_rtcsck = KAPWR_KEY;
- ((volatile immap_t *)IMAP_ADDR)->im_sitk.sitk_tbk = KAPWR_KEY;
+ out_be32(&((immap_t *)IMAP_ADDR)->im_sitk.sitk_tbscrk, ~KAPWR_KEY);
+ out_be32(&((immap_t *)IMAP_ADDR)->im_sitk.sitk_rtcsck, ~KAPWR_KEY);
+ out_be32(&((immap_t *)IMAP_ADDR)->im_sitk.sitk_tbk, ~KAPWR_KEY);
+ out_be32(&((immap_t *)IMAP_ADDR)->im_sitk.sitk_tbscrk, KAPWR_KEY);
+ out_be32(&((immap_t *)IMAP_ADDR)->im_sitk.sitk_rtcsck, KAPWR_KEY);
+ out_be32(&((immap_t *)IMAP_ADDR)->im_sitk.sitk_tbk, KAPWR_KEY);
/* Disable the RTC one second and alarm interrupts. */
- ((volatile immap_t *)IMAP_ADDR)->im_sit.sit_rtcsc &=
- ~(RTCSC_SIE | RTCSC_ALE);
+ out_be16(&((immap_t *)IMAP_ADDR)->im_sit.sit_rtcsc, in_be16(&((immap_t *)IMAP_ADDR)->im_sit.sit_rtcsc) & ~(RTCSC_SIE | RTCSC_ALE));
/* Enable the RTC */
- ((volatile immap_t *)IMAP_ADDR)->im_sit.sit_rtcsc |=
- (RTCSC_RTF | RTCSC_RTE);
+ out_be16(&((immap_t *)IMAP_ADDR)->im_sit.sit_rtcsc, in_be16(&((immap_t *)IMAP_ADDR)->im_sit.sit_rtcsc) | (RTCSC_RTF | RTCSC_RTE));
/* Enabling the decrementer also enables the timebase interrupts
* (or from the other point of view, to get decrementer interrupts
* we have to enable the timebase). The decrementer interrupt
* is wired into the vector table, nothing to do here for that.
*/
- ((volatile immap_t *)IMAP_ADDR)->im_sit.sit_tbscr =
- ((mk_int_int_mask(DEC_INTERRUPT) << 8) |
- (TBSCR_TBF | TBSCR_TBE));
+ out_be16(&((immap_t *)IMAP_ADDR)->im_sit.sit_tbscr, (mk_int_int_mask(DEC_INTERRUPT) << 8) | (TBSCR_TBF | TBSCR_TBE));
if (setup_irq(DEC_INTERRUPT, &tbint_irqaction))
panic("Could not allocate timer IRQ!");
@@ -216,9 +212,9 @@ void __init m8xx_calibrate_decr(void)
static int
m8xx_set_rtc_time(unsigned long time)
{
- ((volatile immap_t *)IMAP_ADDR)->im_sitk.sitk_rtck = KAPWR_KEY;
- ((volatile immap_t *)IMAP_ADDR)->im_sit.sit_rtc = time;
- ((volatile immap_t *)IMAP_ADDR)->im_sitk.sitk_rtck = ~KAPWR_KEY;
+ out_be32(&((immap_t *)IMAP_ADDR)->im_sitk.sitk_rtck, KAPWR_KEY);
+ out_be32(&((immap_t *)IMAP_ADDR)->im_sit.sit_rtc, time);
+ out_be32(&((immap_t *)IMAP_ADDR)->im_sitk.sitk_rtck, ~KAPWR_KEY);
return(0);
}
@@ -226,7 +222,7 @@ static unsigned long
m8xx_get_rtc_time(void)
{
/* Get time from the RTC. */
- return((unsigned long)(((immap_t *)IMAP_ADDR)->im_sit.sit_rtc));
+ return (unsigned long) in_be32(&((immap_t *)IMAP_ADDR)->im_sit.sit_rtc);
}
static void
@@ -235,13 +231,13 @@ m8xx_restart(char *cmd)
__volatile__ unsigned char dummy;
local_irq_disable();
- ((immap_t *)IMAP_ADDR)->im_clkrst.car_plprcr |= 0x00000080;
+ out_be32(&((immap_t *)IMAP_ADDR)->im_clkrst.car_plprcr, in_be32(&((immap_t *)IMAP_ADDR)->im_clkrst.car_plprcr) | 0x00000080);
/* Clear the ME bit in MSR to cause checkstop on machine check
*/
mtmsr(mfmsr() & ~0x1000);
- dummy = ((immap_t *)IMAP_ADDR)->im_clkrst.res[0];
+ dummy = in_8(&((immap_t *)IMAP_ADDR)->im_clkrst.res[0]);
printk("Restart failed\n");
while(1);
}
@@ -306,8 +302,7 @@ m8xx_init_IRQ(void)
i8259_init(0);
/* The i8259 cascade interrupt must be level sensitive. */
- ((immap_t *)IMAP_ADDR)->im_siu_conf.sc_siel &=
- ~(0x80000000 >> ISA_BRIDGE_INT);
+ out_be32(&((immap_t *)IMAP_ADDR)->im_siu_conf.sc_siel, in_be32(&((immap_t *)IMAP_ADDR)->im_siu_conf.sc_siel & ~(0x80000000 >> ISA_BRIDGE_INT)));
if (setup_irq(ISA_BRIDGE_INT, &mbx_i8259_irqaction))
enable_irq(ISA_BRIDGE_INT);
diff -puN arch/ppc/syslib/m8xx_wdt.c~ppc32-8xx-use-io-accessor-macros-instead-of-direct-memory-reference arch/ppc/syslib/m8xx_wdt.c
--- devel/arch/ppc/syslib/m8xx_wdt.c~ppc32-8xx-use-io-accessor-macros-instead-of-direct-memory-reference 2005-10-28 17:44:02.000000000 -0700
+++ devel-akpm/arch/ppc/syslib/m8xx_wdt.c 2005-10-28 17:44:02.000000000 -0700
@@ -29,8 +29,8 @@ void m8xx_wdt_reset(void)
{
volatile immap_t *imap = (volatile immap_t *)IMAP_ADDR;
- imap->im_siu_conf.sc_swsr = 0x556c; /* write magic1 */
- imap->im_siu_conf.sc_swsr = 0xaa39; /* write magic2 */
+ out_be16(imap->im_siu_conf.sc_swsr, 0x556c); /* write magic1 */
+ out_be16(imap->im_siu_conf.sc_swsr, 0xaa39); /* write magic2 */
}
static irqreturn_t m8xx_wdt_interrupt(int irq, void *dev, struct pt_regs *regs)
@@ -39,7 +39,7 @@ static irqreturn_t m8xx_wdt_interrupt(in
m8xx_wdt_reset();
- imap->im_sit.sit_piscr |= PISCR_PS; /* clear irq */
+ out_be16(imap->im_sit.sit_piscr, in_be16(imap->im_sit.sit_piscr | PISCR_PS)); /* clear irq */
return IRQ_HANDLED;
}
@@ -51,7 +51,7 @@ void __init m8xx_wdt_handler_install(bd_
u32 sypcr;
u32 pitrtclk;
- sypcr = imap->im_siu_conf.sc_sypcr;
+ sypcr = in_be32(imap->im_siu_conf.sc_sypcr);
if (!(sypcr & 0x04)) {
printk(KERN_NOTICE "m8xx_wdt: wdt disabled (SYPCR: 0x%08X)\n",
@@ -87,9 +87,9 @@ void __init m8xx_wdt_handler_install(bd_
else
pitc = pitrtclk * wdt_timeout / binfo->bi_intfreq / 2;
- imap->im_sit.sit_pitc = pitc << 16;
- imap->im_sit.sit_piscr =
- (mk_int_int_mask(PIT_INTERRUPT) << 8) | PISCR_PIE | PISCR_PTE;
+ out_be32(imap->im_sit.sit_pitc, pitc << 16);
+
+ out_be16(imap->im_sit.sit_piscr, (mk_int_int_mask(PIT_INTERRUPT) << 8) | PISCR_PIE | PISCR_PTE);
if (setup_irq(PIT_INTERRUPT, &m8xx_wdt_irqaction))
panic("m8xx_wdt: error setting up the watchdog irq!");
diff -puN arch/ppc/syslib/ppc8xx_pic.c~ppc32-8xx-use-io-accessor-macros-instead-of-direct-memory-reference arch/ppc/syslib/ppc8xx_pic.c
--- devel/arch/ppc/syslib/ppc8xx_pic.c~ppc32-8xx-use-io-accessor-macros-instead-of-direct-memory-reference 2005-10-28 17:44:02.000000000 -0700
+++ devel-akpm/arch/ppc/syslib/ppc8xx_pic.c 2005-10-28 17:44:02.000000000 -0700
@@ -6,6 +6,7 @@
#include <linux/signal.h>
#include <linux/interrupt.h>
#include <asm/irq.h>
+#include <asm/io.h>
#include <asm/8xx_immap.h>
#include <asm/mpc8xx.h>
#include "ppc8xx_pic.h"
@@ -29,8 +30,7 @@ static void m8xx_mask_irq(unsigned int i
word = irq_nr >> 5;
ppc_cached_irq_mask[word] &= ~(1 << (31-bit));
- ((immap_t *)IMAP_ADDR)->im_siu_conf.sc_simask =
- ppc_cached_irq_mask[word];
+ out_be32(&((immap_t *)IMAP_ADDR)->im_siu_conf.sc_simask, ppc_cached_irq_mask[word]);
}
static void m8xx_unmask_irq(unsigned int irq_nr)
@@ -41,8 +41,7 @@ static void m8xx_unmask_irq(unsigned int
word = irq_nr >> 5;
ppc_cached_irq_mask[word] |= (1 << (31-bit));
- ((immap_t *)IMAP_ADDR)->im_siu_conf.sc_simask =
- ppc_cached_irq_mask[word];
+ out_be32(&((immap_t *)IMAP_ADDR)->im_siu_conf.sc_simask, ppc_cached_irq_mask[word]);
}
static void m8xx_end_irq(unsigned int irq_nr)
@@ -55,8 +54,7 @@ static void m8xx_end_irq(unsigned int ir
word = irq_nr >> 5;
ppc_cached_irq_mask[word] |= (1 << (31-bit));
- ((immap_t *)IMAP_ADDR)->im_siu_conf.sc_simask =
- ppc_cached_irq_mask[word];
+ out_be32(&((immap_t *)IMAP_ADDR)->im_siu_conf.sc_simask, ppc_cached_irq_mask[word]);
}
}
@@ -69,9 +67,8 @@ static void m8xx_mask_and_ack(unsigned i
word = irq_nr >> 5;
ppc_cached_irq_mask[word] &= ~(1 << (31-bit));
- ((immap_t *)IMAP_ADDR)->im_siu_conf.sc_simask =
- ppc_cached_irq_mask[word];
- ((immap_t *)IMAP_ADDR)->im_siu_conf.sc_sipend = 1 << (31-bit);
+ out_be32(&((immap_t *)IMAP_ADDR)->im_siu_conf.sc_simask, ppc_cached_irq_mask[word]);
+ out_be32(&((immap_t *)IMAP_ADDR)->im_siu_conf.sc_sipend, 1 << (31-bit));
}
struct hw_interrupt_type ppc8xx_pic = {
@@ -93,7 +90,7 @@ m8xx_get_irq(struct pt_regs *regs)
/* For MPC8xx, read the SIVEC register and shift the bits down
* to get the irq number.
*/
- irq = ((immap_t *)IMAP_ADDR)->im_siu_conf.sc_sivec >> 26;
+ irq = in_be32(&((immap_t *)IMAP_ADDR)->im_siu_conf.sc_sivec) >> 26;
/*
* When we read the sivec without an interrupt to process, we will
_
^ permalink raw reply
* [patch 01/43] ppc: prevent GCC 4 from generating AltiVec instructions in kernel
From: akpm @ 2005-10-29 0:46 UTC (permalink / raw)
To: paulus; +Cc: akpm, linuxppc-dev, allinux, linuxppc64-dev
From: Lee Nicks <allinux@gmail.com>
Depending on how GCC is built, GCC 4 may generate altivec instructions without
user explicitly requesting vector operations in the code. Although this is a
performance booster for user applications, it is a problem for kernel.
This patch explicitly instruct GCC to NOT generate altivec instructions while
building the kernel.
Here are some test cases I ran.
(1) build gcc 4.0.1 with '--with-cpu=7450 --enable-altivec
--enable-cxx-flags=-mcpu=7450', and use this gcc to build kernel WITHOUT
this kernel patch. Kernel fail to boot up on a 7450 board because of
altivec instructions in kernel.
(2) build gcc 4.0.1 with "--with-cpu=7450 --enable-altivec
--enable-cxx-flags=-mcpu=7450", and use this gcc to build kernel WITH this
kernel patch. Kernel boot up on a 7450 board without any problem.
(3) build gcc 4.0.1 with "--with-cpu=750 --enable-cxx-flags=-mcpu=750",
and use this gcc to build kernel with or without this kernel patch.
Kernel boot up on a 7450 board without any problem.
This patch should also work with GCC 3 or even earlier GCC 2.95.3.
Signed-off-by: Lee Nicks <allinux@gmail.com>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
---
arch/ppc/Makefile | 4 ++++
arch/ppc64/Makefile | 3 +++
2 files changed, 7 insertions(+)
diff -puN arch/ppc64/Makefile~ppc-prevent-gcc-4-from-generating-altivec-instructions-in-kernel arch/ppc64/Makefile
--- devel/arch/ppc64/Makefile~ppc-prevent-gcc-4-from-generating-altivec-instructions-in-kernel 2005-10-28 17:44:02.000000000 -0700
+++ devel-akpm/arch/ppc64/Makefile 2005-10-28 17:45:21.000000000 -0700
@@ -75,6 +75,9 @@ else
CFLAGS += $(call cc-option,-mtune=power4)
endif
+# No AltiVec instruction when building kernel
+CFLAGS += $(call cc-option, -mno-altivec)
+
# Enable unit-at-a-time mode when possible. It shrinks the
# kernel considerably.
CFLAGS += $(call cc-option,-funit-at-a-time)
diff -puN arch/ppc/Makefile~ppc-prevent-gcc-4-from-generating-altivec-instructions-in-kernel arch/ppc/Makefile
--- devel/arch/ppc/Makefile~ppc-prevent-gcc-4-from-generating-altivec-instructions-in-kernel 2005-10-28 17:44:02.000000000 -0700
+++ devel-akpm/arch/ppc/Makefile 2005-10-28 17:44:02.000000000 -0700
@@ -26,6 +26,10 @@ CPPFLAGS += -Iarch/$(ARCH) -Iarch/$(ARCH
AFLAGS += -Iarch/$(ARCH)
CFLAGS += -Iarch/$(ARCH) -msoft-float -pipe \
-ffixed-r2 -mmultiple
+
+# No AltiVec instruction when building kernel
+CFLAGS += $(call cc-option, -mno-altivec)
+
CPP = $(CC) -E $(CFLAGS)
# Temporary hack until we have migrated to asm-powerpc
LINUXINCLUDE += -Iarch/$(ARCH)/include
_
^ permalink raw reply
* Re: Patches for 2.6.15
From: Andrew Morton @ 2005-10-29 0:40 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev, kumar.gala, linuxppc64-dev
In-Reply-To: <17250.49231.248045.41302@cargo.ozlabs.ibm.com>
Paul Mackerras <paulus@samba.org> wrote:
>
> Andrew, will I just grab the ones you listed from the latest -mm, or
> will you send them to me?
I'll mail them all over.
^ permalink raw reply
* Re: Patches for 2.6.15
From: Paul Mackerras @ 2005-10-29 0:20 UTC (permalink / raw)
To: Andrew Morton; +Cc: linuxppc-dev, Kumar Gala, linuxppc64-dev
In-Reply-To: <20051028130246.459f1e9a.akpm@osdl.org>
Andrew Morton writes:
> Kumar Gala <kumar.gala@freescale.com> wrote:
> >
> > Can we ask Andrew to flush any ppc patches in -mm to linus before we
> > have Linus pull the merge tree.
>
> Well I'd prefer that ;)
My concern is that if we do that we may end up losing some of the
changes from Andrew's patches when the merge goes in and/or creating a
nasty, difficult merge.
Probably the best thing is if I take the patches and apply them on top
of the merge tree (hacking them as necessary) and then get Linus to
pull.
Andrew, will I just grab the ones you listed from the latest -mm, or
will you send them to me?
Paul.
^ permalink raw reply
* Re: Patches for 2.6.15
From: Paul Mackerras @ 2005-10-29 0:10 UTC (permalink / raw)
To: Christopher Friesen; +Cc: linuxppc-dev, linuxppc64-dev
In-Reply-To: <43624B30.20600@nortel.com>
Christopher Friesen writes:
> Under the unified architecture, what is the machine type in the "uname"
> outout?
"ppc" on 32-bit machines, "ppc64" on 64-bit machines, same as before.
The intention is that the merge doesn't change the user/kernel ABI in
any way. :)
Paul.
^ permalink raw reply
* Re: PPC32 - No IDE/ATA devices on new PowerBook
From: Benjamin Herrenschmidt @ 2005-10-29 0:02 UTC (permalink / raw)
To: Parag Warudkar; +Cc: linuxppc-dev list, linux-kernel
In-Reply-To: <05700451-DD42-4BBE-9DB2-8705B88548BF@comcast.net>
On Fri, 2005-10-28 at 19:24 -0400, Parag Warudkar wrote:
> Thanks. I tried 2.4 kernel and to my surprise it detected the IDE/ATA
> controller! (Although it balked out with errors - read past the end
> of the device or something...).
2.4 used the device-tree exclusively for probing IDE on pmac, while 2.6
uses PCI probing when it's a PCI device. The device-tree method tend to
work even when we don't have the PCI ID, but it's dangerous: the driver
doesn't know the details of the timings for this chip revision etc...
and thus may well do crap. I wouldn't try too much with 2.4.
Can you try this patch ? If you don't have a way to build a patched
kernel, you may find somebody on linuxppc-dev list who can do it for
you.
Index: linux-work/drivers/ide/ppc/pmac.c
===================================================================
--- linux-work.orig/drivers/ide/ppc/pmac.c 2005-09-22 14:06:32.000000000 +1000
+++ linux-work/drivers/ide/ppc/pmac.c 2005-10-29 10:00:03.000000000 +1000
@@ -1664,11 +1664,16 @@
};
static struct pci_device_id pmac_ide_pci_match[] = {
- { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_ATA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
- { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_IPID_ATA100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
- { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_K2_ATA100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
+ { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_ATA,
+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
+ { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_IPID_ATA100,
+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
+ { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_K2_ATA100,
+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
{ PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_SH_ATA,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
+ { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_IPIDD2_ATA,
+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
};
static struct pci_driver pmac_ide_pci_driver = {
Index: linux-work/include/linux/pci_ids.h
===================================================================
--- linux-work.orig/include/linux/pci_ids.h 2005-10-06 09:59:14.000000000 +1000
+++ linux-work/include/linux/pci_ids.h 2005-10-29 09:59:06.000000000 +1000
@@ -912,6 +912,7 @@
#define PCI_DEVICE_ID_APPLE_SH_FW 0x0052
#define PCI_DEVICE_ID_APPLE_U3L_AGP 0x0058
#define PCI_DEVICE_ID_APPLE_U3H_AGP 0x0059
+#define PCI_DEVICE_ID_APPLE_IPIDD2_ATA 0x0069
#define PCI_DEVICE_ID_APPLE_TIGON3 0x1645
#define PCI_VENDOR_ID_YAMAHA 0x1073
^ permalink raw reply
* Re: Patches for 2.6.15
From: Andrew Morton @ 2005-10-28 23:21 UTC (permalink / raw)
To: Arnd Bergmann; +Cc: linuxppc64-dev, linuxppc-dev
In-Reply-To: <200510290111.13867.arnd@arndb.de>
Arnd Bergmann <arnd@arndb.de> wrote:
>
> Andrew, are you ok with including spufs in -mm when the merge
> tree is upstream?
Probably. I haven't paid much attention to them thus far, sorry.
^ permalink raw reply
* [PATCH] reserve syscall numbers for Cell
From: Arnd Bergmann @ 2005-10-28 23:16 UTC (permalink / raw)
To: linuxppc64-dev; +Cc: linuxppc-dev
In-Reply-To: <200510290111.13867.arnd@arndb.de>
This creates two powerpc specific dummy system calls that will
later be used on the Cell platform to manage SPUs.
Reserve the system call numbers now so we don't accidentally
use the same numbers for different system calls.
Signed-off-by: Arnd Bergmann <arndb@de.ibm.com>
---
Please apply to merge tree
--- a/kernel/sys_ni.c 2005-10-29 00:46:21.000000000 +0200
+++ b/kernel/sys_ni.c 2005-10-29 00:47:37.000000000 +0200
@@ -90,3 +90,5 @@
cond_syscall(sys32_ipc);
cond_syscall(sys32_sysctl);
cond_syscall(ppc_rtas);
+cond_syscall(sys_spu_run);
+cond_syscall(sys_spu_create);
--- a/arch/powerpc/kernel/systbl.S 2005-10-29 00:39:49.000000000 +0200
+++ b/arch/powerpc/kernel/systbl.S 2005-10-29 00:44:48.000000000 +0200
@@ -319,3 +319,5 @@
SYSCALL(inotify_init)
SYSCALL(inotify_add_watch)
SYSCALL(inotify_rm_watch)
+SYSCALL(spu_run)
+SYSCALL(spu_create)
--- a/include/asm-powerpc/unistd.h 2005-10-29 00:34:40.000000000 +0200
+++ b/include/asm-powerpc/unistd.h 2005-10-29 00:35:52.000000000 +0200
@@ -297,7 +297,9 @@
#define __NR_inotify_add_watch 276
#define __NR_inotify_rm_watch 277
-#define __NR_syscalls 278
+#define __NR_spu_run 278
+#define __NR_spu_create 279
+#define __NR_syscalls 280
#ifdef __KERNEL__
#define __NR__exit __NR_exit
^ permalink raw reply
* Re: Patches for 2.6.15
From: Arnd Bergmann @ 2005-10-28 23:11 UTC (permalink / raw)
To: linuxppc64-dev; +Cc: akpm, linuxppc-dev
In-Reply-To: <17250.8725.358204.62510@cargo.ozlabs.ibm.com>
On Freedag 28 Oktober 2005 15:05, Paul Mackerras wrote:
> If anyone has patches for arch/ppc{,64} and include/asm-ppc{,64} that
> they would like to see go upstream now that 2.6.14 is out, other than
> patches that are already in the powerpc-merge tree, please let me
> know. =A0I am planning to ask Linus to pull the powerpc-merge tree
> shortly, and that will probably break your patches.
Out of my spufs patches, I'd like to have at least the reservation
for my two system call numbers in there so we don't get any conflicts
on that front. The patch follows in another mail.
=46rom my point of view, the spufs itself could go in at this point,
but I have the feeling that the real concerns from other people
will come up at the moment that I post them for inclusion.=20
Andrew, are you ok with including spufs in -mm when the merge
tree is upstream?
> If possible, I'd like to get to the point where we can remove
> arch/ppc64 entirely by the end of the 2-week merge window for 2.6.15.
Ok, I'll do a new patch to move over the BPA files then to get
my stuff out of the way ASAP.
Arnd <><
^ permalink raw reply
* Re: How the linux use BAT
From: Benjamin Herrenschmidt @ 2005-10-28 22:39 UTC (permalink / raw)
To: Noah yan; +Cc: linuxppc-dev
In-Reply-To: <59521b110510280856y9c39f4by54cadd01830ded07@mail.gmail.com>
On Fri, 2005-10-28 at 10:56 -0500, Noah yan wrote:
>
> I am sorry that I did make it clear. It is a little confusing for me
> between the hardware segment and the term "segment" or "section" used
> in a process's address space (AS). One of my understanding is that a
> section in a process's AS is mapped to a hardware segment, which sound
> straightforward but maybe wrong because a process binary may have lots
> of segments that are not the same size.
No, there is no relationship. The kernel just sets up enough segments to
map the entire process address space, this is irrelevant to the actual
program sections.
> Pure segment VM is also hard to maintain memory efficiency. Or,
> several sections, such as different data section are in segments. I
> remember in Linux x86 (posibbly 2.4), segment is not fully used in
> term of VM. The segmentation of the kernel and userland are defined
> upon booting and never changed later on.
The segmentation mecanism on PowerPC is slightly different. We change
segments when context switching as they contain the "vsid" which acts as
a kind of context ID, thus we can keep entry for more than one
context/process in the hash table, we don't have to flush it on context
switches.
> Thanks very much!
> Noah
>
>
>
>
>
> The way linux uses BATs is for the kernel linear mapping.
> Linux uses by
> default (though that can be configued differently) a 3G/1G
> split, that
> is the low 3G of address space are used by userland (and
> covered by the
> user page tables) and the high 1G are used by the kernel. That
> kernel
> space itself is split into a bottom part up to 768Mb (by
> default, that
> can also be configured differently) which is the linear
> mapping, that is
> a single linear mapping of all RAM from 0xc0000000. The rest
> of the
> kernel space is mapped with page tables and known as the
> kernel virtual
> space, used for vmalloc and ioremap.
>
> The BATs are used for the linear mapping. They "override" the
> page
> tables over it if any (though we usually don't bother setting
> up PTEs
> over the space that is BAT mapped). They basically improve
> performances
> by not requiring to go through the hash trasnslation for most
> kernel
> accesses to memory and not using space in the TLB/ERAT.
>
> Ben.
>
>
>
^ permalink raw reply
* memcpy for unaligned memory regions
From: Olaf Hering @ 2005-10-28 21:42 UTC (permalink / raw)
To: linuxppc-dev
The vmlinux.coff is constantly crashing for me, depending on the size
and location of the vmlinux.gz and the ramdisk. The 601 can not handle
unaligned memory access that cross a page boundary (or whatever).
So I tweaked the memcpy.S from arch/ppc64/boot to deal with this.
Does this look ok?
.globl memmove
memmove:
cmpwi 0,r5,0
beqlr
cmplw 0,r3,r4
bgt backwards_memcpy
/* fall through */
.globl memcpy
memcpy:
cmpwi 0,r5,0
beqlr
andi. r0,r4,3 /* get src word aligned */
beq 20f
10: subfic r0,r0,4
cmpd r0,r5
blt 11f
mr r0,r5
11: mtctr r0
12: lbz r7,0(r4)
stb r7,0(r3)
addi r4,r4,1
addi r3,r3,1
bdnz 12b
subf. r5,r0,r5
beqlr
20: andi. r0,r3,3 /* get dest word aligned */
beq 30f
subfic r0,r0,4
cmpd r0,r5
blt 21f
mr r0,r5
21: mtctr r0
22: lbz r7,0(r4)
stb r7,0(r3)
addi r4,r4,1
addi r3,r3,1
bdnz 22b
subf. r5,r0,r5
beqlr
andi. r0,r4,3 /* get src word aligned */
bne 10b
30:
rlwinm. r7,r5,32-3,3,31 /* r7 = r5 >> 3 */
addi r6,r3,-4
addi r4,r4,-4
beq 32f /* if less than 8 bytes to do */
mtctr r7
31: lwz r7,4(r4)
lwzu r8,8(r4)
stw r7,4(r6)
stwu r8,8(r6)
bdnz 31b
andi. r5,r5,7
32: cmplwi 0,r5,4
blt 33f
lwzu r0,4(r4)
addi r5,r5,-4
stwu r0,4(r6)
33: cmpwi 0,r5,0
beqlr
mtctr r5
addi r4,r4,3
addi r6,r6,3
34: lbzu r0,1(r4)
stbu r0,1(r6)
bdnz 34b
blr
.globl backwards_memcpy
backwards_memcpy:
add r6,r3,r5
add r4,r4,r5
andi. r0,r4,3 /* get src word aligned */
beq 20f
10: cmpd r0,r5
blt 11f
mr r0,r5
11: mtctr r0
12: lbzu r7,-1(r4)
stbu r7,-1(r6)
bdnz 12b
subf. r5,r0,r5
beqlr
20: andi. r0,r6,3 /* get dest word aligned */
beq 30f
cmpd r0,r5
blt 21f
mr r0,r5
21: mtctr r0
22: lbzu r7,-1(r4)
stbu r7,-1(r6)
bdnz 22b
subf. r5,r0,r5
beqlr
andi. r0,r4,3 /* get src word aligned */
bne 10b
30:
rlwinm. r7,r5,32-3,3,31 /* r7 = r5 >> 3 */
beq 32f
mtctr r7
31: lwz r7,-4(r4)
lwzu r8,-8(r4)
stw r7,-4(r6)
stwu r8,-8(r6)
bdnz 31b
andi. r5,r5,7
32: cmplwi 0,r5,4
blt 33f
lwzu r0,-4(r4)
subi r5,r5,4
stwu r0,-4(r6)
33: cmpwi 0,r5,0
beqlr
mtctr r5
34: lbzu r0,-1(r4)
stbu r0,-1(r6)
bdnz 34b
blr
--
short story of a lazy sysadmin:
alias appserv=wotan
^ permalink raw reply
* Re: Howto Cross Compile GCC to run on PPC Platform
From: Wolfgang Denk @ 2005-10-28 20:51 UTC (permalink / raw)
To: Jeff Stevens; +Cc: linuxppc-embedded
In-Reply-To: <20051028155510.17662.qmail@web33413.mail.mud.yahoo.com>
In message <20051028155510.17662.qmail@web33413.mail.mud.yahoo.com> you wrote:
> I am trying to compile GCC on an x86 platform to
> run natively on an embedded PPC platform. I am able
> to compile gcc as a cross compiler (to run on x86),
> but can't seem to get it to cross compile gcc (to run
> on ppc). Does anyone know of a good HowTo to do this?
> I'm currently downloading the source distro of ELDK,
> so if it's already in there I'll find it, but if there
It is.
> is one elsewhere online please let me know.
Note that released versions of the ELDK (up to and including ELDK
3.1.1) require a RedHat-7.3 build host. Don't waste your time on
trying later Linux distros ;-)
Current top-of-tree in CVS should build under Fedora Core 4; but this
code has not been released yet - it is beta quality only.
Best regards,
Wolfgang Denk
--
Software Engineering: Embedded and Realtime Systems, Embedded Linux
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de
"Any excuse will serve a tyrant." - Aesop
^ permalink raw reply
* Re: MPC8xx support in 2.6 and [PATCH] USB host controller selection...
From: Greg KH @ 2005-10-28 20:43 UTC (permalink / raw)
To: Marcelo Tosatti; +Cc: David Jander, linux-ppc-embedded
In-Reply-To: <20051028152109.GB18915@logos.cnet>
On Fri, Oct 28, 2005 at 01:21:09PM -0200, Marcelo Tosatti wrote:
> Greg, please refer to the end of the message.
> > - USB Kconfig file for 2.6 kernel is broken. It is not correct to assume that
> > you either have a PCI interface or a processor with internal HCI. Proof: We
> > have a board based on MPC852T (no internal UHCI) which can plug into an
> > (optional) daughter board with a ISP1160 on it. See attached patch.
Then please send the proper patch to the linux-usb-devel mailing list.
> Is it driven by the UHCI driver?
It shouldn't be :)
> >From http://www.semiconductors.philips.com/cgi-bin/pldb/pip/isp1160.html
>
> The ISP1160 is an embedded Universal Serial Bus (USB) Host Controller
> (HC) that complies with Universal Serial Bus Specification Rev. 2.0,
> supporting data transfer at full-speed (12 Mbit/s) and low-speed (1.5
> Mbit/s).
We already have a driver for this device in the kernel tree, right?
> > Maybe the patch should be sent elsewere since it has not much to do with PPC,
> > so can someone please tell me where?
>
> I guess that you should have something like
>
> config USB_ARCH_HAS_HCD
> default y if USB_ARCH_HAS_OHCI
> default y if USB_ARCH_HAS_UHCI
>
> config USB_ARCH_UHCI
> default y if 8xx
>
> Greg?
I don't understand what you are trying to fix up here. What is wrong
with the current checks? If your arch/board has support for the 1160
and we have the Kconfig set wrong for that, we can easily change it.
thanks,
greg k-h
^ permalink raw reply
* Re: Howto Cross Compile GCC to run on PPC Platform
From: Bryan O'Donoghue @ 2005-10-28 20:48 UTC (permalink / raw)
To: Peter Hanson; +Cc: Steven Blakeslee, linuxppc-embedded
In-Reply-To: <50e923300510281227i15609c9dt7778ecbe20920dfa@mail.google.com>
Peter Hanson wrote:
> On 10/28/05, Steven Blakeslee <BlakesleeS@embeddedplanet.com> wrote:
>
>>>get it to cross compile gcc (to run on ppc). Does anyone
>>>know of a good HowTo to do this?
>>
>>Karim Yaghmour's "Building Embedded Linux Systems"
>>
>>
>>
>>> I'm currently downloading the source distro of ELDK, so if
>>>it's already in there I'll find it, but if there is one
>>>elsewhere online please let me know.
>>
>>Very good, full of features.
>
>
> My favorite cross tool chain site:
>
> Building and Testing gcc/glibc cross toolchains
> http://kegel.com/crosstool/
>
> Look into Canadian crosses. At the very least you should find the
> discussion helpful.
I'd use the ELDK if I were you as an x86 hosted cross compiler, if only
because it makes sense in terms of compiling bootloader & kernel with
the same toolchain. Also, if memory serves the ELDK comes with a powerpc
gcc in the supplied ppc root file system.
Alternatively : you can use the uClibc toolchain, to generate a similar
setup.
Here's a script I've thrown together since I sometimes need to generate
gcc toolchains easily for various targets. I've tested it with arm and
powerpc and because, it might be useful to switch between c libraries. ymmv.
http://netsoc.dit.ie/~deckard/software/build_compiler.sh. This script is
based on some excellent documents that Red Hat produced.
http://sources.redhat.com/ml/crossgcc/2005-08/msg00114/l-cross-ltr.pdf
--
"Caveat Emptor" -- James T. Kirk, in no such episode
^ permalink raw reply
* Re: Kernel 2.6 on MPC8xx performance trouble...
From: Marcelo Tosatti @ 2005-10-28 15:30 UTC (permalink / raw)
To: David Jander; +Cc: linux-ppc-embedded
In-Reply-To: <200510280857.44625.david.jander@protonic.nl>
On Fri, Oct 28, 2005 at 08:57:44AM +0200, David Jander wrote:
>
> Hi all,
>
> Many people have said it before: 2.6 has a performance penalty specially for
> embdedded systems.
> But now that I have 2.6 running on our 100MHz MPC852T based board, I was
> shocked to see the result:
> The most simple task doing nothing but a closed loop of integer math runs at
> _half_ the speed compared to kernel 2.4.25!!!!!
David,
Do you have CONFIG_PIN_TLB enabled?
If you do, please patch this in:
http://www.kernel.org/git/?p=linux/kernel/git/marcelo/8xx-fixes;a=commitdiff;h=a41ba028534c45280170c05c23609ea84f34b38a
And select DEBUG_PIN_TLBIE.
^ permalink raw reply
* Re: Kernel 2.6 on MPC8xx performance trouble...
From: Wolfgang Denk @ 2005-10-28 20:37 UTC (permalink / raw)
To: David Jander; +Cc: linuxppc-embedded
In-Reply-To: <200510281257.22650.david.jander@protonic.nl>
In message <200510281257.22650.david.jander@protonic.nl> you wrote:
>
> > What is 'a' and 'b'? The only other explanation I can see is that your
> > "Do something" is more memory heavy than you think - array calculations?
> > (Cache problems should probably give a worse result, but you could check
> > that those config registers are the same).
>
> They are just integers with fixed start values. These are in the loop, so it's
> not an empty loop and hopefully the compiler won't out-optimize it so easily
> (that is of course without specifying any optimization flags). Please don't
> tell me it's a lousy benchmark, because I already know that! Be it as lousy
> as it is, I shouldn't get _those_ results IMHO.
Indeed, you should not get such results. If you compare with the
lmbench results of our 2.4/2.6 comparison, you will notice that we
did NOT see such behaviour. There was a perfromnce degradation for
pure integer tests, due to increased system overhead, but far from a
factor of 2.
See http://www.denx.de/wiki/pub/Know/Linux24vs26/lmbench_results
Best regards,
Wolfgang Denk
--
Software Engineering: Embedded and Realtime Systems, Embedded Linux
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de
A fanatic is a person who can't change his mind and won't change the
subject. - Winston Churchill
^ permalink raw reply
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