* Denx vs kernel.org
From: Matt Jerdonek @ 2005-12-06 16:42 UTC (permalink / raw)
To: linuxppc-embedded
I'm looking at embedding linux into a PowerPC-based
system. I found the DENX website to be very helpful,
but I'm struggling to understand a few items:
1) The source from kernel.org appears to have support
for the powerpc (arch/powerpc/8xx_io). But when using
'make xconfig' I cannot select PowerPC from the list
of processors. Is this just a limitation on the the
configuration utility?
2) What is the difference between the sources on DENX
and kernel.org? Are there other places where PPC
linux kernel source is stored? I'm not opposed to
using the DENX source, I'm just trying to understand
it.
3) I've used eCos before and I'm familiar with
RedBoot. Is there a compelling reason to use U-Boot
over RedBoot? For example, I think U-boot contains an
NFS client while RedBoot does not. Is this important?
Thanks in advance,
-- Matt
__________________________________________
Yahoo! DSL – Something to write home about.
Just $16.99/mo. or less.
dsl.yahoo.com
^ permalink raw reply
* Re: [PATCH] Support 8xx based Silicon Turnkey XTc
From: Wolfgang Denk @ 2005-12-06 16:01 UTC (permalink / raw)
To: pantelis.antoniou; +Cc: Robert Applebaum, linuxppc-embedded
In-Reply-To: <200512052115.45858.pantelis.antoniou@gmail.com>
Dear Pantelis,
in message <200512052115.45858.pantelis.antoniou@gmail.com> you wrote:
> Support of Silicon Turnkey's XTc.
Ummm .. a few questions...
> arch/ppc/platforms/stxxtc.h | 285 +++++++++++++
Here you include a lot of inlined code, but I have problems finding
out what it is good for. For example, there is a full-blown
bit-banging SPI driver included which is nowhere referenced.
Am I missing something, or should this be cleaned up a bit?
> drivers/mtd/maps/stxxtc_nor.c | 326 +++++++++++++++
I think it is not a good idea to embed spaces in the flash map names,
as this will make it impossible to select such devices from the
kernel command line which you seem to intend (at least you have
CONFIG_MTD_CMDLINE_PARTS enabled in your default configuration) ?
And a design question: Why are you using the concatenating (NOR)
flash driver? Why don't you simply map the flashes (in U-Boot) such
that you have one contiguous region? That would make flash use in
U-Boot much more convenient, too.
Best regards,
Wolfgang Denk
--
Software Engineering: Embedded and Realtime Systems, Embedded Linux
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de
Where would we be without rhetorical questions?
^ permalink raw reply
* Re: [PATCH] Support 8xx based Silicon Turnkey XTc
From: Marcelo Tosatti @ 2005-12-06 15:36 UTC (permalink / raw)
To: Pantelis Antoniou; +Cc: Robert Applebaum, linuxppc-embedded
In-Reply-To: <200512052115.45858.pantelis.antoniou@gmail.com>
Hi Panto!
On Mon, Dec 05, 2005 at 09:15:43PM +0200, Pantelis Antoniou wrote:
> Support of Silicon Turnkey's XTc.
>
> ---
> commit fac9bbd80d8f8ab3c6af5a417f804dbf8537c700
> tree 7863f94249651a26ca3eb29aed4c65c214968dda
> parent e4f5c82a92c2a546a16af1614114eec19120e40a
> author Pantelis Antoniou <pantelis.antoniou@gmail.com> Mon, 05 Dec 2005 21:13:56 +0200
> committer Pantelis Antoniou <pantelis.antoniou@gmail.com> Mon, 05 Dec 2005 21:13:56 +0200
>
> arch/ppc/Kconfig | 5
> arch/ppc/configs/stxxtc_defconfig | 804 +++++++++++++++++++++++++++++++++++++
> arch/ppc/platforms/Makefile | 1
> arch/ppc/platforms/stxxtc.h | 285 +++++++++++++
> arch/ppc/platforms/stxxtc_setup.c | 193 +++++++++
> arch/ppc/syslib/m8xx_setup.c | 14 +
> drivers/mtd/maps/Kconfig | 6
> drivers/mtd/maps/Makefile | 1
> drivers/mtd/maps/stxxtc_nor.c | 326 +++++++++++++++
> drivers/mtd/nand/Kconfig | 8
> drivers/mtd/nand/Makefile | 1
> drivers/mtd/nand/stxxtc_nand.c | 277 +++++++++++++
> include/asm-ppc/mpc8xx.h | 4
> 13 files changed, 1922 insertions(+), 3 deletions(-)
>
> +# CONFIG_PIN_TLB is not set
Might want to enable by default?
> diff --git a/arch/ppc/platforms/stxxtc.h b/arch/ppc/platforms/stxxtc.h
> new file mode 100644
> --- /dev/null
> +++ b/arch/ppc/platforms/stxxtc.h
> @@ -0,0 +1,285 @@
> +/*
> + * A collection of structures, addresses, and values associated with
> + * the STXXTC systems.
> + *
> + * Copyright (c) 2005 Pantelis Antoniou <pantelis.antoniou@gmail.com>
> + * Dan Malek <dan@embeddedalley.com>
> + *
> + */
> +#ifndef __MACH_STXXTC_DEFS
> +#define __MACH_STXXTC_DEFS
> +
> +#include <linux/config.h>
> +
> +#ifndef __ASSEMBLY__
> +
> +#include <asm/ppcboot.h>
> +
> +#include <asm/8xx_immap.h>
> +#include <asm/commproc.h>
> +#include <asm/mpc8xx.h>
> +#include <asm/delay.h>
> +
> +#endif
> +
> +#define IMAP_ADDR 0xFF000000 /* physical base address of IMMR area */
Extra TAB (or missing tab below, whatever you prefer ;)
> +#define IMAP_SIZE (64 * 1024) /* mapped size of IMMR area */
> +
> +/* We don't use the 8259.
> +*/
> +#define NR_8259_INTS 0
> +
> +#define NAND_SIZE 0x00010000
> +#define NAND_BASE 0xF1000000
> +
> +/*-----------------------------------------------------------------------
> + * PCMCIA stuff
> + *-----------------------------------------------------------------------
> + *
> + */
> +#define PCMCIA_MEM_SIZE ( 64 << 20 )
> +
> +#define MAX_HWIFS 1 /* overwrite default in include/asm-ppc/ide.h */
> +
> +/*
> + * Definitions for IDE0 Interface
> + */
> +#define IDE0_BASE_OFFSET 0
> +#define IDE0_DATA_REG_OFFSET (PCMCIA_MEM_SIZE + 0x320)
> +#define IDE0_ERROR_REG_OFFSET (2 * PCMCIA_MEM_SIZE + 0x320 + 1)
> +#define IDE0_NSECTOR_REG_OFFSET (2 * PCMCIA_MEM_SIZE + 0x320 + 2)
> +#define IDE0_SECTOR_REG_OFFSET (2 * PCMCIA_MEM_SIZE + 0x320 + 3)
> +#define IDE0_LCYL_REG_OFFSET (2 * PCMCIA_MEM_SIZE + 0x320 + 4)
> +#define IDE0_HCYL_REG_OFFSET (2 * PCMCIA_MEM_SIZE + 0x320 + 5)
> +#define IDE0_SELECT_REG_OFFSET (2 * PCMCIA_MEM_SIZE + 0x320 + 6)
> +#define IDE0_STATUS_REG_OFFSET (2 * PCMCIA_MEM_SIZE + 0x320 + 7)
> +#define IDE0_CONTROL_REG_OFFSET 0x0106
> +#define IDE0_IRQ_REG_OFFSET 0x000A /* not used */
> +
> +#define IDE0_INTERRUPT 13
> +
> +/* XXX FUCK!, for IDE disk set to 0, for normal PCMCIA set to 1 */
> +/* XXX don't ask me why.. */
Can you make the comment a bit nicer? :)
> +#if 1
> +/* define IO_BASE for PCMCIA */
> +#define _IO_BASE 0x80000000
> +#define _IO_BASE_SIZE (64<<10)
> +#endif
> +
> +/***********************************************************************/
> +
> +/* shorthand for the ports data registers */
> +#define PORTA (((volatile immap_t *)IMAP_ADDR)->im_ioport.iop_padat)
> +#define PORTB (((volatile immap_t *)IMAP_ADDR)->im_cpm.cp_pbdat)
> +#define PORTC (((volatile immap_t *)IMAP_ADDR)->im_ioport.iop_pcdat)
> +#define PORTD (((volatile immap_t *)IMAP_ADDR)->im_ioport.iop_pddat)
> +#define PORTE (((volatile immap_t *)IMAP_ADDR)->im_cpm.cp_pedat)
> +
> +/********************************************************************************/
> +
> +#define PIN_PORT_EQ(p, x) ((void *) & x ## _PORT == (void *) & p)
> +#define PIN_PORT_NE(p, x) ((void *) & x ## _PORT != (void *) & p)
> +
> +#define PIN_PORT_RW(x) (PIN_PORT_NE(PORTXWO, x) && PIN_PORT_NE(PORTXRO, x))
> +#define PIN_PORT_RO(x) PIN_PORT_EQ(PORTXRO, x)
> +#define PIN_PORT_WO(x) PIN_PORT_EQ(PORTXWO, x)
> +
> +/********************************************************************************/
> +
> +#define PIN_SFT(x) ((sizeof(x ## _PORT) * 8 - 1) - x ## _BIT)
> +#define PIN_MSK(x) (1U << PIN_SFT(x))
> +
> +/********************************************************************************/
> +
> +/* normal m8xx pins */
> +#define _PIN_HI(x) \
> + do { \
> + x ## _PORT |= PIN_MSK(x); \
> + } while(0)
> +
> +#define _PIN_LO(x) \
> + do { \
> + x ## _PORT &= ~PIN_MSK(x); \
> + } while(0)
> +
> +#define _PIN_TGL(x) \
> + do { \
> + x ## _PORT ^= PIN_MSK(x); \
> + } while(0)
> +
> +#define _PIN_GET(x) \
> + (!!(x ## _PORT & PIN_MSK(x)))
> +
> +#define _PIN_SET(x, v) \
> + do { \
> + if (__builtin_constant_p(v)) { \
> + if ((v) != 0) \
> + _PIN_HI(x); \
> + else \
> + _PIN_LO(x); \
> + } else \
> + x ## _PORT = ( x ## _PORT & ~PIN_MSK(x)) | (!!(v) << PIN_SFT(x)); \
> + } while(0)
> +
> +#define _PIN_CFG_IN(x) \
> + do { \
> + if (PIN_PORT_EQ(PORTA, x)) \
> + PORTA_config(PIN_MSK(x), 0, 0); \
> + if (PIN_PORT_EQ(PORTB, x)) \
> + PORTB_config(PIN_MSK(x), 0, 0); \
> + if (PIN_PORT_EQ(PORTC, x)) \
> + PORTC_config(PIN_MSK(x), 0, 0); \
> + if (PIN_PORT_EQ(PORTD, x)) \
> + PORTD_config(PIN_MSK(x), 0, 0); \
> + if (PIN_PORT_EQ(PORTE, x)) \
> + PORTE_config(PIN_MSK(x), 0, 0); \
> + } while(0)
> +
> +#define _PIN_CFG_INT_ANY(x) \
> + do { \
> + if (PIN_PORT_EQ(PORTC, x)) \
> + PORTC_config(PIN_MSK(x), 0, 0); \
> + } while(0)
> +
> +#define _PIN_CFG_INT_FALL(x) \
> + do { \
> + if (PIN_PORT_EQ(PORTC, x)) \
> + PORTC_config(PIN_MSK(x), 0, 0); \
> + } while(0)
> +
> +#define _PIN_CFG_OUT(x, v) \
> + do { \
> + _PIN_SET(x, v); \
> + if (PIN_PORT_EQ(PORTA, x)) \
> + PORTA_config(0, PIN_MSK(x), 0); \
> + if (PIN_PORT_EQ(PORTB, x)) \
> + PORTB_config(0, PIN_MSK(x), 0); \
> + if (PIN_PORT_EQ(PORTC, x)) \
> + PORTC_config(0, PIN_MSK(x), 0); \
> + if (PIN_PORT_EQ(PORTD, x)) \
> + PORTD_config(0, PIN_MSK(x), 0); \
> + if (PIN_PORT_EQ(PORTE, x)) \
> + PORTE_config(0, PIN_MSK(x), 0); \
> + } while(0)
> +
> +#define _PIN_CFG_OUT_HI(x) _PIN_CFG_OUT(x, 1)
> +#define _PIN_CFG_OUT_LO(x) _PIN_CFG_OUT(x, 0)
> +
> +#ifndef __ASSEMBLY__
> +
> +static inline void PORTA_config(uint inmsk, uint outmsk, uint dummy)
> +{
> + volatile immap_t *imap = (volatile immap_t *)IMAP_ADDR;
> + ushort msk = (ushort)inmsk | (ushort)outmsk;
> +
> + imap->im_ioport.iop_padir = (imap->im_ioport.iop_padir & ~(ushort)inmsk) | (ushort)outmsk;
> + imap->im_ioport.iop_paodr &= ~msk;
> + imap->im_ioport.iop_papar &= ~msk;
> +}
> +
> +static inline void PORTB_config(uint inmsk, uint outmsk, uint dummy)
> +{
> + volatile immap_t *imap = (volatile immap_t *)IMAP_ADDR;
> + uint msk = inmsk | outmsk;
> +
> + imap->im_cpm.cp_pbdir = (imap->im_cpm.cp_pbdir & ~inmsk) | outmsk;
> + imap->im_cpm.cp_pbodr &= ~msk;
> + imap->im_cpm.cp_pbpar &= ~msk;
> +}
> +
> +static inline void PORTC_config(uint inmsk, uint outmsk, uint fallmsk)
> +{
> + volatile immap_t *imap = (volatile immap_t *)IMAP_ADDR;
> + ushort msk = (ushort)inmsk | (ushort)outmsk;
> +
> + imap->im_ioport.iop_pcdir = (imap->im_ioport.iop_pcdir & ~(ushort)inmsk) | (ushort)outmsk;
> + imap->im_ioport.iop_pcso &= ~msk;
> + imap->im_ioport.iop_pcint = (imap->im_ioport.iop_pcint & ~(ushort)inmsk) | ((ushort)fallmsk & (ushort)inmsk);
> + imap->im_ioport.iop_pcpar &= ~msk;
> +}
> +
> +static inline void PORTD_config(uint inmsk, uint outmsk, uint dummy)
> +{
> + volatile immap_t *imap = (volatile immap_t *)IMAP_ADDR;
> + ushort msk = (ushort)inmsk | (ushort)outmsk;
> +
> + imap->im_ioport.iop_pddir = (imap->im_ioport.iop_pddir & ~(ushort)inmsk) | (ushort)outmsk;
> + imap->im_ioport.iop_pdpar &= ~msk;
> +}
> +
> +static inline void PORTE_config(uint inmsk, uint outmsk, uint dummy)
> +{
> + volatile immap_t *imap = (volatile immap_t *)IMAP_ADDR;
> + uint msk = inmsk | outmsk;
> +
> + imap->im_cpm.cp_pedir = (imap->im_cpm.cp_pedir & ~inmsk) | outmsk;
> + imap->im_cpm.cp_peodr &= ~msk;
> + imap->im_cpm.cp_pepar &= ~msk;
> +}
I don't like this macros being board specific - can't you simplify/beautify
this all?
> +
> +/**********************************************/
> +
> +unsigned long pin_lock(void);
> +void pin_unlock(unsigned long flags);
> +
> +#endif /* __ASSEMBLY */
> +
> +/******************************************************************************/
> +
> +/* NAND flash pins */
> +
> +#define F_ALE_PORT PORTC
> +#define F_ALE_BIT 15
> +
> +#define F_CLE_PORT PORTB
> +#define F_CLE_BIT 23
> +
> +#define F_CE_PORT PORTA
> +#define F_CE_BIT 7
> +
> +#define F_RY_BY_PORT PORTA
> +#define F_RY_BY_BIT 6
> +
> +/***********************************************************************/
> +
> +/* SPI pin definitions */
> +
> +#define SPI_RXD_PORT PORTB
> +#define SPI_RXD_BIT 28
> +
> +#define SPI_TXD_PORT PORTB
> +#define SPI_TXD_BIT 29
> +
> +#define SPI_CLK_PORT PORTB
> +#define SPI_CLK_BIT 30
> +
> +#define SPI_DELAY() udelay(1)
> +
> +#ifndef __ASSEMBLY__
> +
> +static inline unsigned int spi_transfer(unsigned int tx)
> +{
> + unsigned int rx;
> + int i;
> +
> + rx = 0;
> + for (i = 0; i < 8; i++) {
> + _PIN_SET(SPI_TXD, tx & 0x80);
> + tx <<= 1;
> + _PIN_TGL(SPI_CLK);
> + SPI_DELAY();
> + rx <<= 1;
> + rx |= _PIN_GET(SPI_RXD);
> + _PIN_TGL(SPI_CLK);
> + SPI_DELAY();
> + }
> +
> + return rx;
> +}
> +
> +#endif
> +
> +#define BOARD_CHIP_NAME "MPC870"
> +
> +#endif /* __MACH_STXXTC_DEFS */
> +
> diff --git a/arch/ppc/platforms/stxxtc_setup.c b/arch/ppc/platforms/stxxtc_setup.c
> new file mode 100644
> --- /dev/null
> +++ b/arch/ppc/platforms/stxxtc_setup.c
> @@ -0,0 +1,193 @@
> +/*
> + * arch/ppc/platforms/stxxtc.c
> + *
> + * Platform setup for the Silicon Turnkey eXpress XTc
> + */
> +
> +#include <linux/config.h>
> +#include <linux/init.h>
> +#include <linux/module.h>
> +#include <linux/param.h>
> +#include <linux/string.h>
> +#include <linux/ioport.h>
> +#include <linux/device.h>
> +
> +#include <asm/delay.h>
> +#include <asm/io.h>
> +#include <asm/machdep.h>
> +#include <asm/page.h>
> +#include <asm/processor.h>
> +#include <asm/system.h>
> +#include <asm/time.h>
> +#include <asm/ppcboot.h>
> +#include <asm/ppc_sys.h>
> +
> +#include <linux/stddef.h>
> +
> +#include <linux/fs_enet_pd.h>
> +
> +#include <platforms/stxxtc.h>
> +
> +/***********************************************************************/
> +
> +#ifdef CONFIG_FW_ENV
> +#include <syslib/fw_env.h>
> +
> +static const char *ro_vars[] = {
> + "ethaddr", "eth1addr", "adsladdr", "serial#", "usbaddr", "usb1addr", "ver", "board",
> + NULL
> +};
> +#endif
> +
> +/***********************************************************************/
> +
> +static spinlock_t port_spinlock;
> +
> +unsigned long pin_lock(void)
> +{
> + unsigned long flags;
> +
> + spin_lock_irqsave(&port_spinlock, flags);
> + return flags;
> +}
> +EXPORT_SYMBOL(pin_lock);
> +
> +void pin_unlock(unsigned long flags)
> +{
> + spin_unlock_irqrestore(&port_spinlock, flags);
> +}
> +EXPORT_SYMBOL(pin_unlock);
Unused? Why do you need this?
> +
> +/***********************************************************************/
> +
> +static struct fs_mii_bus_info fec_mii_bus_info = {
> + .method = fsmii_fec,
> + .id = 0,
> +};
> +
> +static struct fs_platform_info mpc8xx_fec_pdata[2] = {
> + [0] = {
> + .phy_addr = 0x01,
> + .phy_irq = -1,
> + .fs_no = fsid_fec1,
> + .rx_ring = 128,
> + .tx_ring = 16,
> + .napi_weight = 17,
> + .bus_info = &fec_mii_bus_info,
> + .rx_copybreak = 240,
> + .use_napi = 1,
> + .use_rmii = 0,
> + },
> + [1] = {
> + .phy_addr = 0x03,
> + .phy_irq = -1,
> + .fs_no = fsid_fec2,
> + .rx_ring = 128,
> + .tx_ring = 16,
> + .napi_weight = 17,
> + .bus_info = &fec_mii_bus_info,
> + .rx_copybreak = 240,
> + .use_napi = 1,
> + .use_rmii = 0,
> + }
> +};
> +
> +/***********************************************************************/
> +
> +static void stxxtc_fixup_fs_pdata(struct platform_device *pd, int fs_no)
> +{
> + struct fs_platform_info *fpi;
> + bd_t *bd;
> + int idx;
> +
> + idx = fs_get_fec_index(fs_no);
> + if (idx == -1) {
> + printk(KERN_ERR "stxxtc_setup: Only FEC ethernets supported by STXXTC.\n");
> + return;
> + }
> +
> + fpi = &mpc8xx_fec_pdata[idx];
> +
> + bd = (bd_t *)__res;
> +
> + memcpy(fpi->macaddr, bd->bi_enetaddr, 6);
> + fpi->macaddr[5] += idx; /* different per interface */
> +
> + pd->dev.platform_data = fpi;
> +
> + /* we don't setup *any* pins, we trust the bootloader */
> +}
> +
> +static void stxxtc_fixup_fec_pdata(struct platform_device *pd, int idx)
> +{
> + int fs_no = fsid_fec1 + pd->id - 1;
> +
> + stxxtc_fixup_fs_pdata(pd, fs_no);
> +}
> +
> +static int stxxtc_platform_notify(struct device *dev)
> +{
> + static struct {
> + const char *bus_id;
> + void (*rtn)(struct platform_device * pdev, int idx);
> + } dev_map[] = {
> + { "fsl-cpm-fec", stxxtc_fixup_fec_pdata },
> + };
> + struct platform_device *pdev;
> + int i, j, idx;
> + const char *s;
> +
> + if (dev && dev->bus_id)
> + for (i = 0; i < ARRAY_SIZE(dev_map); i++) {
> + idx = -1;
> + if ((s = strrchr(dev->bus_id, '.')) != NULL)
> + idx = (int)simple_strtol(s + 1, NULL, 10);
> + else
> + s = dev->bus_id + strlen(s);
> +
> + j = s - dev->bus_id;
> +
> + if (!strncmp(dev->bus_id, dev_map[i].bus_id, j)) {
> + pdev = container_of(dev, struct platform_device, dev);
> + dev_map[i].rtn(pdev, idx);
> + }
> + }
> +
> + return 0;
> +}
Isnt a lot of this common code between all boards? (other than the dev_map array
definition).
> +
> +int __init
> +stxxtc_init(void)
> +{
> + immap_t *imap = (immap_t *)IMAP_ADDR;
> +
> + spin_lock_init(&port_spinlock);
> +
> + imap->im_siu_conf.sc_sypcr |= 0x0000FF00;
> +
> + /* configure SPI pins */
> + _PIN_CFG_OUT_HI(SPI_TXD);
> + _PIN_CFG_OUT_HI(SPI_CLK);
> + _PIN_CFG_IN(SPI_RXD);
> +
> + /* configure NAND pins */
> + _PIN_CFG_OUT_LO(F_ALE);
> + _PIN_CFG_OUT_LO(F_CLE);
> + _PIN_CFG_OUT_HI(F_CE);
> + _PIN_CFG_IN(F_RY_BY);
> +
> + platform_notify = stxxtc_platform_notify;
> +
> + identify_ppc_sys_by_name("MPC885");
> +
> + /* remove these devices */
> + ppc_sys_device_remove(MPC8xx_CPM_SCC1);
> + ppc_sys_device_remove(MPC8xx_CPM_SCC2);
> + ppc_sys_device_remove(MPC8xx_CPM_SCC3);
> + ppc_sys_device_remove(MPC8xx_CPM_SCC4);
> +
> + return 0;
> +}
> +
> +arch_initcall(stxxtc_init);
> +
> diff --git a/arch/ppc/syslib/m8xx_setup.c b/arch/ppc/syslib/m8xx_setup.c
> --- a/arch/ppc/syslib/m8xx_setup.c
> +++ b/arch/ppc/syslib/m8xx_setup.c
> @@ -370,16 +370,26 @@ m8xx_map_io(void)
> #if defined(CONFIG_NETTA)
> io_block_mapping(_IO_BASE,_IO_BASE,_IO_BASE_SIZE, _PAGE_IO);
> #endif
> +#if defined(CONFIG_STXXTC)
> + io_block_mapping(_IO_BASE,_IO_BASE,64 << 10, _PAGE_IO);
64<<10 = IO_BASE_SIZE?
> +#endif
> }
>
> void __init
> platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
> unsigned long r6, unsigned long r7)
> {
> + bd_t *bd;
> +
> parse_bootinfo(find_bootinfo());
>
> - if ( r3 )
> - memcpy( (void *)__res,(void *)(r3+KERNELBASE), sizeof(bd_t) );
> + if ( r3 ) {
> + bd = (bd_t *)(r3+KERNELBASE);
> + /* skip OF tree if present */
> + if (*(u32 *)bd == 0xd00dfeed)
> + bd = (bd_t *)((char *)bd + ((u32 *)bd)[1]);
> + memcpy(__res, bd, sizeof(bd_t));
> + }
Separate patch?
>
> #ifdef CONFIG_PCI
> m8xx_setup_pci_ptrs();
> diff --git a/drivers/mtd/maps/Kconfig b/drivers/mtd/maps/Kconfig
> --- a/drivers/mtd/maps/Kconfig
> +++ b/drivers/mtd/maps/Kconfig
> @@ -639,5 +639,11 @@ config MTD_PLATRAM
>
> This selection automatically selects the map_ram driver.
>
> +config MTD_STXXTC_NOR
> + tristate "NOR Map driver for STXXTC NOR flash"
> + depends on STXXTC && MTD_CONCAT && MTD_PARTITIONS && MTD_CFI_INTELEXT
> + help
> + Map driver for Silicon Turnkey eXpress XTc NOR flash.
> +
> endmenu
Would be easier if the flash driver was a separate patch.
^ permalink raw reply
* Re: Does this Bug fixed ?
From: Hollis Blanchard @ 2005-12-06 15:31 UTC (permalink / raw)
To: sairam k; +Cc: linuxppc-dev
In-Reply-To: <c6be647f0512052129s2afd4c1vf4442192ea6d5c28@mail.gmail.com>
On Dec 5, 2005, at 11:29 PM, sairam k wrote:
>
> 1) I used linuxppc_2_4_devel PowerPC development tree source(from
> ppc.bkbits.net) to build kernel for PowerPC
> IBM405EP(evb405ep_defconfig) and montavista's gcc cross compiler for
> ppc_405-
...
> Does anyone fixed this bug........if so why it is not reflected in
> bkbits
I don't know if this has been fixed, but bkbits has not been used for
over six months. Instead you should get your source from kernel.org .
Also, there are many embedded developers on the linuxppc-embedded list;
you might try asking there instead of here.
Finally, please do not send HTML email to these lists.
Good luck.
-Hollis
^ permalink raw reply
* Re: 回复:Re: Fw: Anyone using CodeWarrior USB TAP?
From: York Sun @ 2005-12-06 15:22 UTC (permalink / raw)
To: zengshuai; +Cc: ppc
In-Reply-To: <31839904.1133852113796.JavaMail.postfix@mx3.mail.sohu.com>
No. It doesn't support GDB protocol.
York
On Tue, 2005-12-06 at 14:55 +0800, zengshuai@sogou.com wrote:
> I have a question too.
> Can we use CodeWarrior USB TAP in GDB?
> The CodeWarrior IDE is really expensive.
>=20
> ----- =E5=8E=9F=E6=96=87 -----
> From: York Sun=20
> To: Kim Phillips=20
> Cc: linuxppc-embedded@ozlabs.org=20
> Subject: Re: Fw: Anyone using CodeWarrior USB TAP?
> Sent: Tue Dec 06 03:37:22 CST 2005
>=20
> > Addison,
> >=20
> > I don't know if you can receive this reply since I am not in the mailin=
g
> > list.
> >=20
> > The answer is that the USB TAP can work under Linux. You will need
> > CodeWarrior Linux version. The current version is 2.6. Please contact
> > the sales of channels where you got your board.
> >=20
> > No specific driver is required for Linux. Just kindly remind you to
> > check the writing privilege of /proc/bus/usb/001/* if you not the root
> > user.
> >=20
> > York
> >=20
> >=20
> > On Mon, 2005-12-05 at 13:22 -0600, Kim Phillips wrote:
> > > York, know anything about this? If you're subscribed, could you answ=
er directly to the list?
> > >=20
> > > Kim
> > >=20
> > > Begin forwarded message:
> > >=20
> > > Date: Mon, 5 Dec 2005 17:05:39 +0000
> > > From: Addison Baldwin <addison.baldwin@gmail.com>
> > > To: linuxppc-embedded@ozlabs.org
> > > Subject: Anyone using CodeWarrior USB TAP?
> > >=20
> > >=20
> > > Hi
> > >=20
> > > I received a MPC8272ADS board from Freescale, and I'm trying to use a
> > > CodeWarrior USB TAB that has been provided with the board. It seems t=
hat
> > > such a device only works under Windows, as I didn't find a driver to =
make it
> > > works under Linux.
> > >=20
> > > I would like to know if anyone have got the CodeWarrior USB working u=
nder
> > > Linux.
> > >=20
> > > Thanks,
> > > Addison
> > >=20
> > >=20
> > >=20
> > --=20
> > York Sun
> > =20
> > This email, and any associated attachments have been classified as:
> > [x] Freescale Semiconductor General Business
> > [ ] Freescale Semiconductor Internal Use Only
> > [ ] Freescale Semiconductor Confidential Proprietary
> >=20
> > _______________________________________________
> > Linuxppc-embedded mailing list
> > Linuxppc-embedded@ozlabs.org
> > https://ozlabs.org/mailman/listinfo/linuxppc-embedded
>=20
>=20
> ------------------------------
> =E6=88=91=E7=8E=B0=E5=9C=A8=E4=BD=BF=E7=94=A8Sogou.com=E7=9A=842G=E9=82=
=AE=E7=AE=B1=E4=BA=86=EF=BC=8C=E4=BD=A0=E4=B9=9F=E6=9D=A5=E8=AF=95=E8=AF=95=
=E5=90=A7!=20
> http://mail.sogou.com/recommend/sogoumail_invite_reg1.jsp?from=3Dsogouinv=
itation&s_EMAIL=3Dzengshuai%40sogou.com&username=3D&FullName=3D&Email=3D&ve=
rify=3De197bd6dbd1fc7f8d6a035729df08d63
>=20
--=20
York Sun
=20
This email, and any associated attachments have been classified as:
[x] Freescale Semiconductor General Business
[ ] Freescale Semiconductor Internal Use Only
[ ] Freescale Semiconductor Confidential Proprietary
^ permalink raw reply
* Re: 回复:Re: Fw: Anyone using CodeWarrior USB TAP?
From: York Sun @ 2005-12-06 15:18 UTC (permalink / raw)
To: zengshuai; +Cc: ppc
In-Reply-To: <31839904.1133852113796.JavaMail.postfix@mx3.mail.sohu.com>
No, you can't. It doesn't support GDB protocol so far.
York
On Tue, 2005-12-06 at 14:55 +0800, zengshuai@sogou.com wrote:
> I have a question too.
> Can we use CodeWarrior USB TAP in GDB?
> The CodeWarrior IDE is really expensive.
>=20
> ----- =E5=8E=9F=E6=96=87 -----
> From: York Sun=20
> To: Kim Phillips=20
> Cc: linuxppc-embedded@ozlabs.org=20
> Subject: Re: Fw: Anyone using CodeWarrior USB TAP?
> Sent: Tue Dec 06 03:37:22 CST 2005
>=20
> > Addison,
> >=20
> > I don't know if you can receive this reply since I am not in the mailin=
g
> > list.
> >=20
> > The answer is that the USB TAP can work under Linux. You will need
> > CodeWarrior Linux version. The current version is 2.6. Please contact
> > the sales of channels where you got your board.
> >=20
> > No specific driver is required for Linux. Just kindly remind you to
> > check the writing privilege of /proc/bus/usb/001/* if you not the root
> > user.
> >=20
> > York
> >=20
> >=20
> > On Mon, 2005-12-05 at 13:22 -0600, Kim Phillips wrote:
> > > York, know anything about this? If you're subscribed, could you answ=
er directly to the list?
> > >=20
> > > Kim
> > >=20
> > > Begin forwarded message:
> > >=20
> > > Date: Mon, 5 Dec 2005 17:05:39 +0000
> > > From: Addison Baldwin <addison.baldwin@gmail.com>
> > > To: linuxppc-embedded@ozlabs.org
> > > Subject: Anyone using CodeWarrior USB TAP?
> > >=20
> > >=20
> > > Hi
> > >=20
> > > I received a MPC8272ADS board from Freescale, and I'm trying to use a
> > > CodeWarrior USB TAB that has been provided with the board. It seems t=
hat
> > > such a device only works under Windows, as I didn't find a driver to =
make it
> > > works under Linux.
> > >=20
> > > I would like to know if anyone have got the CodeWarrior USB working u=
nder
> > > Linux.
> > >=20
> > > Thanks,
> > > Addison
> > >=20
> > >=20
> > >=20
> > --=20
> > York Sun
> > =20
> > This email, and any associated attachments have been classified as:
> > [x] Freescale Semiconductor General Business
> > [ ] Freescale Semiconductor Internal Use Only
> > [ ] Freescale Semiconductor Confidential Proprietary
> >=20
> > _______________________________________________
> > Linuxppc-embedded mailing list
> > Linuxppc-embedded@ozlabs.org
> > https://ozlabs.org/mailman/listinfo/linuxppc-embedded
>=20
>=20
> ------------------------------
> =E6=88=91=E7=8E=B0=E5=9C=A8=E4=BD=BF=E7=94=A8Sogou.com=E7=9A=842G=E9=82=
=AE=E7=AE=B1=E4=BA=86=EF=BC=8C=E4=BD=A0=E4=B9=9F=E6=9D=A5=E8=AF=95=E8=AF=95=
=E5=90=A7!=20
> http://mail.sogou.com/recommend/sogoumail_invite_reg1.jsp?from=3Dsogouinv=
itation&s_EMAIL=3Dzengshuai%40sogou.com&username=3D&FullName=3D&Email=3D&ve=
rify=3De197bd6dbd1fc7f8d6a035729df08d63
>=20
--=20
York Sun
=20
This email, and any associated attachments have been classified as:
[x] Freescale Semiconductor General Business
[ ] Freescale Semiconductor Internal Use Only
[ ] Freescale Semiconductor Confidential Proprietary
^ permalink raw reply
* no IRQ from USB on MPC8248
From: Nathael PAJANI @ 2005-12-06 15:12 UTC (permalink / raw)
To: linuxppc-embedded
In-Reply-To: <20051206125102.1FC7F68888@ozlabs.org>
Hi all!
As I said previously I started a backport of the hcd driver from
sourceforge (http://cpm2usb.sourceforge.net/) to linux 2.6.9 for an
actis board (VSBC6848) based on a MPC8248 (MPC8272 family)
I have a running 2.6.9 kernel for this board, and no other, that's why
I'm doing a backport of the driver. (for those who might wonder)
I managed to have the core up:
---> insmod usbcore.ko
Using usbcore.ko
usbcore: registered new driver usbfs
usbcore: registered new driver hub
---> mount /proc/bus/usb
---> insmod m82xx-hcd.ko
Using m82xx-hcd.ko
=> driver mpc82xx-hcd, 0.02
mpc82xx-hcd mpc82xx-hcd3: PQ2 intergrated USB controller v0.1
mpc82xx-hcd mpc82xx-hcd3: new USB bus registered, assigned bus number 1
hub 1-0:1.0: USB hub found
hub 1-0:1.0: 1 port detected
PQ2USB: debug file creation
---> Done
~ #
so this is OK
then, when plugging a device, I got this:
usb 1-1: new full speed USB device using address 2
usb 1-1: control timeout on ep0out
mpc82xx-hcd mpc82xx-hcd3: Unlink after no-IRQ? Different ACPI or APIC
settings may help.
usb 1-1: control timeout on ep0out
usb 1-1: device not accepting address 2, error -110
usb 1-1: new full speed USB device using address 3
usb 1-1: control timeout on ep0out
usb 1-1: control timeout on ep0out
usb 1-1: device not accepting address 3, error -110
which means the hub detects a device, and tries to configure it.
On the device (MP3player) I have an LCD display, and the text switches
to "USB-C" and comes back, which means something has been received.
Let's consider the device is working fine, I have then two possibilities:
first: the device receives incoherent stuff, and does not dare
responding, but I got no way to check on the device. (I consider the
usbcore tries to send cohenrent stuff!)
second: the device is happy to see a request and replies correctly....
but there's no interrupt fired, whether using SUI_INT_USB (==11) or the
SCC3 interrupt (==42)
I've been looking for many things allready, but did not find a clue of
what might happen... If you have some, I'll be pleased to hear about them.
I also had a look at the debug file:
~ # cat /proc/driver/m8xxhci_privateh
===> Misc stats:
sof = 0 isrs = 0 cpm_irqs = 0 overrun = 0
rxb = 0 txb = 0 bsy = 0 sof = 0
txe[0] = 0 txe[1] = 0 txe[2] = 0 txe[3] = 0
nak[0] = 0 nak[1] = 0 nak[2] = 0 nak[3] = 0
to[0] = 0 to[1] = 0 to[2] = 0 to[3] = 0
stall[0] = 0 stall[1] = 0 stall[2] = 0 stall[3] = 0
tx_err = 0 tx_nak = 0 tx_stal = 0 tx_to = 0 tx_un = 0
enqs[ISO] = 0 enqs[INTR] = 0 enqs[CTRL] = 4 enqs[BULK] = 0
cpls[ISO] = 0 cpls[INTR] = 0 cpls[CTRL] = 4 cpls[BULK] = 0
===> Periodic schedule:
~ #
but as I do not know what might be expected, I do not know what to think
about it.
The sof, isrs, and cpm_irqs counters confirm that there have been no
irqs ...
please, help me if you can.
and anyway, have fun :) :)
^ permalink raw reply
* [PATCH 5/5] ppc32: Add PCI-X support for Yucca board
From: Ruslan V. Sushko @ 2005-12-06 12:50 UTC (permalink / raw)
To: rollandd; +Cc: linuxppc-embedded
[-- Attachment #1: Type: text/plain, Size: 177 bytes --]
This patch is cleaned (all whitespace fixes of original code has been
removed) version old PCI-X patch for Yucca board.
Signed-off-by: Ruslan V. Sushko <rsushko@ru.mvista.com>
[-- Attachment #2: yucca_pcix.patch --]
[-- Type: text/x-patch, Size: 8454 bytes --]
This patch is cleaned (all whitespace fixes of original code has been removed) version old PCIX patch for yucca board.
---
commit c9e322aa17237167d6355fb2e55028d51271f1df
tree ef967150a7445cc54f234e18fe7a83ca06142a46
parent 9bc85a59a27ae0559a59a852f3ce58a49368d3dd
author Ruslan V. Sushko <rsushko@ru.mvista.com> Tue, 06 Dec 2005 13:30:13 +0300
committer Ruslan V. Sushko <rsushko@ru.mvista.com> Tue, 06 Dec 2005 13:30:13 +0300
arch/ppc/platforms/4xx/yucca.c | 168 ++++++++++++++++++++++++++++++++--------
include/asm-ppc/ibm44x.h | 9 ++
2 files changed, 142 insertions(+), 35 deletions(-)
diff --git a/arch/ppc/platforms/4xx/yucca.c b/arch/ppc/platforms/4xx/yucca.c
--- a/arch/ppc/platforms/4xx/yucca.c
+++ b/arch/ppc/platforms/4xx/yucca.c
@@ -58,6 +58,25 @@ extern bd_t __res;
static struct ibm44x_clocks clocks __initdata;
+unsigned char ppc4xx_uic_ext_irq_cfg[] __initdata = {
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ15: EXT */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ14: EXT */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ13: EXT */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ12: PCI-X slot */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ11: EXT */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ10: EXT */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ9: EXT */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ8: EXT */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ7: EXT */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ6: EXT */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ5: EXT */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ4: EXT */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ3: EXT */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ2: EXT */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ1: EXT */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ0: EXT */
+};
+
static void __init
yucca_calibrate_decr(void)
{
@@ -80,13 +99,83 @@ yucca_show_cpuinfo(struct seq_file *m)
return 0;
}
-static enum {
- HOSE_UNKNOWN,
+static void __init yucca_set_emacdata(void)
+{
+ struct ocp_def *def;
+ struct ocp_func_emac_data *emacdata;
+
+ /* Set phy_map, phy_mode, and mac_addr for the EMAC */
+ def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 0);
+ emacdata = def->additions;
+ emacdata->phy_map = 0x00000001; /* Skip 0x00 */
+ emacdata->phy_mode = PHY_MODE_GMII;
+ memcpy(emacdata->mac_addr, __res.bi_enetaddr, 6);
+}
+
+enum yucca_hoses {
HOSE_PCIX,
HOSE_PCIE0,
HOSE_PCIE1,
- HOSE_PCIE2
-} hose_type[4];
+ HOSE_PCIE2,
+ HOSE_MAX
+};
+
+static enum yucca_hoses hose_type[4];
+
+#define is_pcix_hose(_hs_) ((_hs_) == HOSE_PCIX)
+#define is_pcie_hose(_hs_) (((_hs_) >= HOSE_PCIE0) && ((_hs_) <= HOSE_PCIE2))
+#define pcie_hose_num(_hs_) ((_hs_) - HOSE_PCIE0)
+
+#define PCIX_READW(offset) \
+ (readw((void *)((u32)pcix_reg_base+offset)))
+
+#define PCIX_WRITEW(value, offset) \
+ (writew(value, (void *)((u32)pcix_reg_base+offset)))
+
+#define PCIX_WRITEL(value, offset) \
+ (writel(value, (void *)((u32)pcix_reg_base+offset)))
+
+static void __init
+ppc440spe_setup_pcix(struct pci_controller *hose)
+{
+ void *pcix_reg_base;
+
+ pcix_reg_base = ioremap64(PCIX0_REG_BASE, PCIX_REG_SIZE);
+
+ /* Disable all windows */
+ PCIX_WRITEL(0, PCIX0_POM0SA);
+ PCIX_WRITEL(0, PCIX0_POM1SA);
+ PCIX_WRITEL(0, PCIX0_POM2SA);
+ PCIX_WRITEL(0, PCIX0_PIM0SA);
+ PCIX_WRITEL(0, PCIX0_PIM0SAH);
+ PCIX_WRITEL(0, PCIX0_PIM1SA);
+ PCIX_WRITEL(0, PCIX0_PIM2SA);
+ PCIX_WRITEL(0, PCIX0_PIM2SAH);
+
+ /*
+ * Setup 512MB PLB->PCI outbound mem window
+ * (a_n000_0000->0_n000_0000)
+ * */
+ PCIX_WRITEL(0x0000000d, PCIX0_POM0LAH);
+ PCIX_WRITEL(hose->mem_space.start, PCIX0_POM0LAL);
+ PCIX_WRITEL(0x00000000, PCIX0_POM0PCIAH);
+ PCIX_WRITEL(hose->mem_space.start, PCIX0_POM0PCIAL);
+ PCIX_WRITEL(~(hose->mem_space.end - hose->mem_space.start) | 1 ,
+ PCIX0_POM0SA);
+
+ /* Setup 1GB PCI->PLB inbound memory window at 0, enable MSIs */
+ PCIX_WRITEL(0x00000000, PCIX0_PIM0LAH);
+ PCIX_WRITEL(0x00000000, PCIX0_PIM0LAL);
+ PCIX_WRITEL(0xc0000007, PCIX0_PIM0SA);
+ PCIX_WRITEL(0xffffffff, PCIX0_PIM0SAH);
+
+ /* Enable PCIX0 I/O, Mem, and Busmaster cycles */
+ PCIX_WRITEW(PCIX_READW(PCIX0_COMMAND) | PCI_COMMAND_MEMORY |
+ PCI_COMMAND_MASTER, PCIX0_COMMAND);
+
+ iounmap(pcix_reg_base);
+ eieio();
+}
static inline int
yucca_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
@@ -100,7 +189,7 @@ yucca_map_irq(struct pci_dev *dev, unsig
* A B C D
*/
{
- { 81, -1, -1, -1 }, /* IDSEL 1 - PCIX0 Slot 0 */
+ { 49, -1, -1, -1 }, /* IDSEL 1 - PCIX0 Slot 0 */
};
const long min_idsel = 1, max_idsel = 1, irqs_per_slot = 4;
return PCI_IRQ_TABLE_LOOKUP;
@@ -141,19 +230,6 @@ yucca_map_irq(struct pci_dev *dev, unsig
return -1;
}
-static void __init yucca_set_emacdata(void)
-{
- struct ocp_def *def;
- struct ocp_func_emac_data *emacdata;
-
- /* Set phy_map, phy_mode, and mac_addr for the EMAC */
- def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 0);
- emacdata = def->additions;
- emacdata->phy_map = 0x00000001; /* Skip 0x00 */
- emacdata->phy_mode = PHY_MODE_GMII;
- memcpy(emacdata->mac_addr, __res.bi_enetaddr, 6);
-}
-
static int __init yucca_pcie_card_present(int port)
{
void __iomem *pcie_fpga_base;
@@ -240,35 +316,44 @@ yucca_setup_hoses(void)
{
struct pci_controller *hose;
char name[20];
+ enum yucca_hoses hs;
int bus_no = 0;
- int i;
- for (i = 0; i <= 2; ++i) {
- if (!yucca_pcie_card_present(i))
- continue;
-
- printk(KERN_INFO "PCIE%d: card present\n", i);
- yucca_setup_pcie_fpga_rootpoint(i);
- if (ppc440spe_init_pcie_rootport(i)) {
- printk(KERN_WARNING "PCIE%d: initialization failed\n", i);
- continue;
+ for (hs = HOSE_PCIX; hs < HOSE_MAX; ++hs) {
+ if (is_pcie_hose(hs)) {
+ if (!yucca_pcie_card_present(pcie_hose_num(hs)))
+ continue;
+
+ printk(KERN_INFO "PCIE%d: card present\n",
+ pcie_hose_num(hs));
+
+ yucca_setup_pcie_fpga_rootpoint(pcie_hose_num(hs));
+ if (ppc440spe_init_pcie_rootport(pcie_hose_num(hs))) {
+ printk(KERN_ERR "PCIE%d: initialization "
+ "failed\n", pcie_hose_num(hs));
+ continue;
+ }
}
hose = pcibios_alloc_controller();
+
if (!hose)
return;
- sprintf(name, "PCIE%d host bridge", i);
+ sprintf(name, "PCI%s%d host bridge",
+ is_pcix_hose(hs) ? "X" : "E",
+ is_pcie_hose(hs) ? pcie_hose_num(hs) : 0
+ );
pci_init_resource(&hose->io_resource,
YUCCA_PCIX_LOWER_IO,
YUCCA_PCIX_UPPER_IO,
IORESOURCE_IO,
name);
- hose->mem_space.start = YUCCA_PCIE_LOWER_MEM +
- i * YUCCA_PCIE_MEM_SIZE;
+ hose->mem_space.start = YUCCA_PCIX_LOWER_MEM +
+ hs * YUCCA_PCIX_MEM_SIZE;
hose->mem_space.end = hose->mem_space.start +
- YUCCA_PCIE_MEM_SIZE - 1;
+ YUCCA_PCIX_MEM_SIZE - 1;
pci_init_resource(&hose->mem_resources[0],
hose->mem_space.start,
@@ -278,9 +363,24 @@ yucca_setup_hoses(void)
hose->first_busno = bus_no;
hose->last_busno = 0xFF;
- hose_type[hose->index] = HOSE_PCIE0 + i;
+ hose_type[hose->index] = hs;
+
+ if (is_pcix_hose(hs)) {
+ hose->io_space.start = YUCCA_PCIX_LOWER_IO;
+ hose->io_space.end = YUCCA_PCIX_UPPER_IO;
+ isa_io_base =
+ (unsigned long)
+ ioremap64(PCIX0_IO_BASE, PCIX_IO_SIZE);
+ hose->io_base_virt = (void *)isa_io_base;
+
+ ppc440spe_setup_pcix(hose);
+
+ setup_indirect_pci(hose, PCIX0_CFGA, PCIX0_CFGD);
+ hose->set_cfg_type = 1;
+ } else {
+ ppc440spe_setup_pcie(hose, pcie_hose_num(hs));
+ }
- ppc440spe_setup_pcie(hose, i);
hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
bus_no = hose->last_busno + 1;
printk(KERN_INFO "%s: resources allocated\n", name);
diff --git a/include/asm-ppc/ibm44x.h b/include/asm-ppc/ibm44x.h
--- a/include/asm-ppc/ibm44x.h
+++ b/include/asm-ppc/ibm44x.h
@@ -557,12 +557,19 @@
#define PCIX1_CFGD 0x1ec00004UL
#define PCIX2_CFGD 0x2ec00004UL
+#if defined (CONFIG_440SPE)
+#define PCIX0_IO_BASE 0x0000000C08000000ULL
+#else
#define PCIX0_IO_BASE 0x0000000908000000ULL
#define PCIX1_IO_BASE 0x0000000908000000ULL
#define PCIX2_IO_BASE 0x0000000908000000ULL
+#endif
+
#define PCIX_IO_SIZE 0x00010000
-#ifdef CONFIG_440SP
+#if defined (CONFIG_440SPE)
+#define PCIX0_REG_BASE 0x0000000c0ec80000ULL
+#elif defined(CONFIG_440SP)
#define PCIX0_REG_BASE 0x000000090ec80000ULL
#else
#define PCIX0_REG_BASE 0x000000020ec80000ULL
^ permalink raw reply
* [PATCH 4/5] ppc32: Fix the PCI bus numbering assignment for Yucca PCI initialization.
From: Ruslan V. Sushko @ 2005-12-06 12:50 UTC (permalink / raw)
To: rollandd; +Cc: linuxppc-embedded
[-- Attachment #1: Type: text/plain, Size: 161 bytes --]
Fix the PCI bus numbering assignment. This will be an issue if more
than one PCI card will be inserted.
Signed-off-by: Ruslan V. Sushko <rsushko@ru.mvista.com>
[-- Attachment #2: yucca_pci_bus_num.patch --]
[-- Type: text/x-patch, Size: 1331 bytes --]
Fix the PCI bus numbering assignment for PCI initialization for Yucca board.
This will be an issue if more than one PCI card is inserted.
---
commit 9bc85a59a27ae0559a59a852f3ce58a49368d3dd
tree cb2b3d77931e4bbc8e98f5ea776514c23e1b50ca
parent 4776902accd7c0721532168f73dc7618675bda1e
author Ruslan V. Sushko <rsushko@ru.mvista.com> Tue, 06 Dec 2005 13:14:17 +0300
committer Ruslan V. Sushko <rsushko@ru.mvista.com> Tue, 06 Dec 2005 13:14:17 +0300
arch/ppc/platforms/4xx/yucca.c | 7 +++++--
1 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/arch/ppc/platforms/4xx/yucca.c b/arch/ppc/platforms/4xx/yucca.c
--- a/arch/ppc/platforms/4xx/yucca.c
+++ b/arch/ppc/platforms/4xx/yucca.c
@@ -240,6 +240,7 @@ yucca_setup_hoses(void)
{
struct pci_controller *hose;
char name[20];
+ int bus_no = 0;
int i;
for (i = 0; i <= 2; ++i) {
@@ -275,12 +276,14 @@ yucca_setup_hoses(void)
IORESOURCE_MEM,
name);
- hose->first_busno = 0;
- hose->last_busno = 15;
+ hose->first_busno = bus_no;
+ hose->last_busno = 0xFF;
hose_type[hose->index] = HOSE_PCIE0 + i;
ppc440spe_setup_pcie(hose, i);
hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
+ bus_no = hose->last_busno + 1;
+ printk(KERN_INFO "%s: resources allocated\n", name);
}
ppc_md.pci_swizzle = common_swizzle;
^ permalink raw reply
* [PATCH 3/5] ppc32: Fix config space address calculation for Yucca PCIE initialization
From: Ruslan V. Sushko @ 2005-12-06 12:50 UTC (permalink / raw)
To: rollandd; +Cc: linuxppc-embedded
[-- Attachment #1: Type: text/plain, Size: 338 bytes --]
Fix config space address calculation for Yucca PCIE initialization. The
problem was in signed integer using. The size of each config space
segment is 0x40000000 so the offset of config space for third hose will
be calculated as negative number if number of hose signed integer.
Signed-off-by: Ruslan V. Sushko <rsushko@ru.mvista.com>
[-- Attachment #2: yucca_pciecfg_fix.patch --]
[-- Type: text/x-patch, Size: 1852 bytes --]
Fix config space address calculation for Yucca PCIE initialization. The problem
was in signed integer using. The size of each config space segment is
0x40000000 so the offset of config space for 3d hose will be calculated as
negative number if number of hose signed integer.
---
commit 4776902accd7c0721532168f73dc7618675bda1e
tree 770f0d58f4a6598028fe2dfd16b5226c7bcd0c27
parent 18b959b9ab80f8cb2fa1eff0a68cca3b5aa2f642
author Ruslan V. Sushko <rsushko@ru.mvista.com> Tue, 06 Dec 2005 13:01:57 +0300
committer Ruslan V. Sushko <rsushko@ru.mvista.com> Tue, 06 Dec 2005 13:01:57 +0300
arch/ppc/syslib/ppc440spe_pcie.c | 4 ++--
arch/ppc/syslib/ppc440spe_pcie.h | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/ppc/syslib/ppc440spe_pcie.c b/arch/ppc/syslib/ppc440spe_pcie.c
--- a/arch/ppc/syslib/ppc440spe_pcie.c
+++ b/arch/ppc/syslib/ppc440spe_pcie.c
@@ -181,7 +181,7 @@ int ppc440spe_init_pcie(void)
return 0;
}
-int ppc440spe_init_pcie_rootport(int port)
+int ppc440spe_init_pcie_rootport(u32 port)
{
static int core_init;
void __iomem *utl_base;
@@ -380,7 +380,7 @@ int ppc440spe_init_pcie_rootport(int por
return 0;
}
-void ppc440spe_setup_pcie(struct pci_controller *hose, int port)
+void ppc440spe_setup_pcie(struct pci_controller *hose, u32 port)
{
void __iomem *mbase;
diff --git a/arch/ppc/syslib/ppc440spe_pcie.h b/arch/ppc/syslib/ppc440spe_pcie.h
--- a/arch/ppc/syslib/ppc440spe_pcie.h
+++ b/arch/ppc/syslib/ppc440spe_pcie.h
@@ -143,7 +143,7 @@
#define PECFG_POM0LAH 0x384
int ppc440spe_init_pcie(void);
-int ppc440spe_init_pcie_rootport(int port);
-void ppc440spe_setup_pcie(struct pci_controller *hose, int port);
+int ppc440spe_init_pcie_rootport(u32 port);
+void ppc440spe_setup_pcie(struct pci_controller *hose, u32 port);
#endif /* __PPC_SYSLIB_PPC440SPE_PCIE_H */
^ permalink raw reply
* [PATCH 2/5] ppc32: verbose error checking for Yucca PCIE initialization
From: Ruslan V. Sushko @ 2005-12-06 12:49 UTC (permalink / raw)
To: rollandd; +Cc: linuxppc-embedded
[-- Attachment #1: Type: text/plain, Size: 989 bytes --]
> > +
> > + attempts = 10;
> > switch (port) {
> > case 0:
> > - if (!(SDR_READ(PESDR0_RCSSTS) & (1 << 16)))
> > - printk(KERN_WARNING "PCIE0: VC0 not active\n");
> > + while(!(SDR_READ(PESDR0_RCSSTS) & (1 << 16))) {
> > + if (!(attempts--)) {
> > + printk(KERN_WARNING "PCIE0: VC0 not active\n");
> > + return -1;
> > + }
> > + mdelay(1000);
> > + }
> > SDR_WRITE(PESDR0_RCSSET, SDR_READ(PESDR0_RCSSET) | 1 << 20);
>
> what lead you to add 10 tries here? Did this fix an issue you saw
> with a device?
I haven't saw any error but this is potential issue because this flag
asserts only then PCI Express port initialization is completed. I guess
the initialization sequences assumes time using. Therefore the error may
appears in future revision of the boards if Core clock will grow up.
Nevertheless I do not know the time which is necessary for completeness,
so I add this just to be safe.
Signed-off-by: Ruslan V. Sushko <rsushko@ru.mvista.com>
[-- Attachment #2: yucca_pcie_err_chk.patch --]
[-- Type: text/x-patch, Size: 5232 bytes --]
This patch adds verbose error checking for Yucca PCIE initialization
---
commit 18b959b9ab80f8cb2fa1eff0a68cca3b5aa2f642
tree 632d445c219c2a3ff1d56023485efe23e7fd196d
parent 27304e1086e96f8110626096a75cf4783a5512bb
author Ruslan V. Sushko <rsushko@ru.mvista.com> Tue, 06 Dec 2005 12:56:36 +0300
committer Ruslan V. Sushko <rsushko@ru.mvista.com> Tue, 06 Dec 2005 12:56:36 +0300
arch/ppc/syslib/ppc440spe_pcie.c | 74 +++++++++++++++++++++++++-------------
1 files changed, 49 insertions(+), 25 deletions(-)
diff --git a/arch/ppc/syslib/ppc440spe_pcie.c b/arch/ppc/syslib/ppc440spe_pcie.c
--- a/arch/ppc/syslib/ppc440spe_pcie.c
+++ b/arch/ppc/syslib/ppc440spe_pcie.c
@@ -91,9 +91,10 @@ enum {
LNKW_X8 = 0x8
};
-static void check_error(void)
+static int check_error(void)
{
u32 valPE0, valPE1, valPE2;
+ int err = 0;
/* SDR0_PEGPLLLCT1 reset */
if (!(valPE0 = SDR_READ(PESDR0_PLLLCT1) & 0x01000000)) {
@@ -109,6 +110,7 @@ static void check_error(void)
!(valPE1 & 0x01000000) ||
!(valPE2 & 0x01000000)) {
printk(KERN_INFO "PCIE: SDR0_PExRCSSET rstgu error\n");
+ err = -1;
}
/* SDR0_PExRCSSET rstdl */
@@ -116,6 +118,7 @@ static void check_error(void)
!(valPE1 & 0x00010000) ||
!(valPE2 & 0x00010000)) {
printk(KERN_INFO "PCIE: SDR0_PExRCSSET rstdl error\n");
+ err = -1;
}
/* SDR0_PExRCSSET rstpyn */
@@ -123,6 +126,7 @@ static void check_error(void)
(valPE1 & 0x00001000) ||
(valPE2 & 0x00001000)) {
printk(KERN_INFO "PCIE: SDR0_PExRCSSET rstpyn error\n");
+ err = -1;
}
/* SDR0_PExRCSSET hldplb */
@@ -130,6 +134,7 @@ static void check_error(void)
(valPE1 & 0x10000000) ||
(valPE2 & 0x10000000)) {
printk(KERN_INFO "PCIE: SDR0_PExRCSSET hldplb error\n");
+ err = -1;
}
/* SDR0_PExRCSSET rdy */
@@ -137,6 +142,7 @@ static void check_error(void)
(valPE1 & 0x00100000) ||
(valPE2 & 0x00100000)) {
printk(KERN_INFO "PCIE: SDR0_PExRCSSET rdy error\n");
+ err = -1;
}
/* SDR0_PExRCSSET shutdown */
@@ -144,7 +150,9 @@ static void check_error(void)
(valPE1 & 0x00000100) ||
(valPE2 & 0x00000100)) {
printk(KERN_INFO "PCIE: SDR0_PExRCSSET shutdown error\n");
+ err = -1;
}
+ return err;
}
/*
@@ -155,17 +163,20 @@ int ppc440spe_init_pcie(void)
/* Set PLL clock receiver to LVPECL */
SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) | 1 << 28);
- check_error();
+ if (check_error())
+ return -1;
- printk(KERN_INFO "PCIE initialization OK\n");
-
- if (!(SDR_READ(PESDR0_PLLLCT2) & 0x10000))
- printk(KERN_INFO "PESDR_PLLCT2 resistance calibration failed (0x%08x)\n",
+ if (!(SDR_READ(PESDR0_PLLLCT2) & 0x10000)) {
+ printk(KERN_INFO "PCIE: PESDR_PLLCT2 resistance calibration "
+ "failed (0x%08x)\n",
SDR_READ(PESDR0_PLLLCT2));
+ return -1;
+ }
/* De-assert reset of PCIe PLL, wait for lock */
SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) & ~(1 << 24));
udelay(3);
+ printk(KERN_INFO "PCIE initialization OK\n");
return 0;
}
@@ -174,14 +185,13 @@ int ppc440spe_init_pcie_rootport(int por
{
static int core_init;
void __iomem *utl_base;
+ int attempts;
u32 val = 0;
- int i;
if (!core_init) {
+ if(ppc440spe_init_pcie())
+ return -1;
++core_init;
- i = ppc440spe_init_pcie();
- if (i)
- return i;
}
/*
@@ -252,15 +262,10 @@ int ppc440spe_init_pcie_rootport(int por
case 2: val = SDR_READ(PESDR2_RCSSTS); break;
}
- if (!(val & (1 << 20)))
- printk(KERN_INFO "PCIE%d: PGRST inactive\n", port);
- else
- printk(KERN_WARNING "PGRST for PCIE%d failed %08x\n", port, val);
-
- switch (port) {
- case 0: printk(KERN_INFO "PCIE0: LOOP %08x\n", SDR_READ(PESDR0_LOOP)); break;
- case 1: printk(KERN_INFO "PCIE1: LOOP %08x\n", SDR_READ(PESDR1_LOOP)); break;
- case 2: printk(KERN_INFO "PCIE2: LOOP %08x\n", SDR_READ(PESDR2_LOOP)); break;
+ if (val & (1 << 20)) {
+ printk(KERN_WARNING "PGRST for PCIE%d failed %08x\n",
+ port, val);
+ return -1;
}
/*
@@ -333,20 +338,39 @@ int ppc440spe_init_pcie_rootport(int por
/*
* Check for VC0 active and assert RDY.
*/
+
+ attempts = 10;
switch (port) {
case 0:
- if (!(SDR_READ(PESDR0_RCSSTS) & (1 << 16)))
- printk(KERN_WARNING "PCIE0: VC0 not active\n");
+ while(!(SDR_READ(PESDR0_RCSSTS) & (1 << 16))) {
+ if (!(attempts--)) {
+ printk(KERN_WARNING "PCIE0: VC0 not active\n");
+ return -1;
+ }
+ mdelay(1000);
+ }
SDR_WRITE(PESDR0_RCSSET, SDR_READ(PESDR0_RCSSET) | 1 << 20);
break;
case 1:
- if (!(SDR_READ(PESDR1_RCSSTS) & (1 << 16)))
- printk(KERN_WARNING "PCIE0: VC0 not active\n");
+ while(!(SDR_READ(PESDR1_RCSSTS) & (1 << 16))) {
+ if (!(attempts--)) {
+ printk(KERN_WARNING "PCIE1: VC0 not active\n");
+ return -1;
+ }
+ mdelay(1000);
+ }
+
SDR_WRITE(PESDR1_RCSSET, SDR_READ(PESDR1_RCSSET) | 1 << 20);
break;
case 2:
- if (!(SDR_READ(PESDR2_RCSSTS) & (1 << 16)))
- printk(KERN_WARNING "PCIE0: VC0 not active\n");
+ while(!(SDR_READ(PESDR2_RCSSTS) & (1 << 16))) {
+ if (!(attempts--)) {
+ printk(KERN_WARNING "PCIE2: VC0 not active\n");
+ return -1;
+ }
+ mdelay(1000);
+ }
+
SDR_WRITE(PESDR2_RCSSET, SDR_READ(PESDR2_RCSSET) | 1 << 20);
break;
}
^ permalink raw reply
* [PATCH 1/5] ppc32: Removes dead code from original Yucca PCIE initialization sequence
From: Ruslan V. Sushko @ 2005-12-06 12:48 UTC (permalink / raw)
To: rolandd; +Cc: linuxppc-embedded
[-- Attachment #1: Type: text/plain, Size: 121 bytes --]
This patch removes dead code from PCIE initialization sequence
Signed-off-by: Ruslan V. Sushko <rsushko@ru.mvista.com>
[-- Attachment #2: yucca_pcie_rdead_code.patch --]
[-- Type: text/x-patch, Size: 1869 bytes --]
This patch removes dead code from Yucca PCIE initialization sequence
---
commit 27304e1086e96f8110626096a75cf4783a5512bb
tree 5d002bc97c0edcc2646ebd941a9f2b321a4777fc
parent e4f5c82a92c2a546a16af1614114eec19120e40a
author Ruslan V. Sushko <rsushko@ru.mvista.com> Tue, 06 Dec 2005 12:33:57 +0300
committer Ruslan V. Sushko <rsushko@ru.mvista.com> Tue, 06 Dec 2005 12:33:57 +0300
arch/ppc/platforms/4xx/yucca.c | 5 -----
arch/ppc/syslib/ppc440spe_pcie.c | 16 ----------------
2 files changed, 0 insertions(+), 21 deletions(-)
diff --git a/arch/ppc/platforms/4xx/yucca.c b/arch/ppc/platforms/4xx/yucca.c
--- a/arch/ppc/platforms/4xx/yucca.c
+++ b/arch/ppc/platforms/4xx/yucca.c
@@ -242,11 +242,6 @@ yucca_setup_hoses(void)
char name[20];
int i;
- if (0 && ppc440spe_init_pcie()) {
- printk(KERN_WARNING "PPC440SPe PCI Express initialization failed\n");
- return;
- }
-
for (i = 0; i <= 2; ++i) {
if (!yucca_pcie_card_present(i))
continue;
diff --git a/arch/ppc/syslib/ppc440spe_pcie.c b/arch/ppc/syslib/ppc440spe_pcie.c
--- a/arch/ppc/syslib/ppc440spe_pcie.c
+++ b/arch/ppc/syslib/ppc440spe_pcie.c
@@ -47,8 +47,6 @@ pcie_read_config(struct pci_bus *bus, un
break;
}
- if (0) printk("%s: read %x(%d) @ %x\n", __func__, *val, len, offset);
-
return PCIBIOS_SUCCESSFUL;
}
@@ -353,20 +351,6 @@ int ppc440spe_init_pcie_rootport(int por
break;
}
-#if 0
- /* Dump all config regs */
- for (i = 0x300; i <= 0x320; ++i)
- printk("[%04x] 0x%08x\n", i, SDR_READ(i));
- for (i = 0x340; i <= 0x353; ++i)
- printk("[%04x] 0x%08x\n", i, SDR_READ(i));
- for (i = 0x370; i <= 0x383; ++i)
- printk("[%04x] 0x%08x\n", i, SDR_READ(i));
- for (i = 0x3a0; i <= 0x3a2; ++i)
- printk("[%04x] 0x%08x\n", i, SDR_READ(i));
- for (i = 0x3c0; i <= 0x3c3; ++i)
- printk("[%04x] 0x%08x\n", i, SDR_READ(i));
-#endif
-
mdelay(100);
return 0;
^ permalink raw reply
* 回复:Re: Fw: Anyone using CodeWarrior USB TAP?
From: zengshuai @ 2005-12-06 6:55 UTC (permalink / raw)
To: York Sun; +Cc: ppc
I have a question too.
Can we use CodeWarrior USB TAP in GDB?
The CodeWarrior IDE is really expensive.
----- 原文 -----
From: York Sun
To: Kim Phillips
Cc: linuxppc-embedded@ozlabs.org
Subject: Re: Fw: Anyone using CodeWarrior USB TAP?
Sent: Tue Dec 06 03:37:22 CST 2005
> Addison,
>
> I don't know if you can receive this reply since I am not in the mailing
> list.
>
> The answer is that the USB TAP can work under Linux. You will need
> CodeWarrior Linux version. The current version is 2.6. Please contact
> the sales of channels where you got your board.
>
> No specific driver is required for Linux. Just kindly remind you to
> check the writing privilege of /proc/bus/usb/001/* if you not the root
> user.
>
> York
>
>
> On Mon, 2005-12-05 at 13:22 -0600, Kim Phillips wrote:
> > York, know anything about this? If you're subscribed, could you answer directly to the list?
> >
> > Kim
> >
> > Begin forwarded message:
> >
> > Date: Mon, 5 Dec 2005 17:05:39 +0000
> > From: Addison Baldwin <addison.baldwin@gmail.com>
> > To: linuxppc-embedded@ozlabs.org
> > Subject: Anyone using CodeWarrior USB TAP?
> >
> >
> > Hi
> >
> > I received a MPC8272ADS board from Freescale, and I'm trying to use a
> > CodeWarrior USB TAB that has been provided with the board. It seems that
> > such a device only works under Windows, as I didn't find a driver to make it
> > works under Linux.
> >
> > I would like to know if anyone have got the CodeWarrior USB working under
> > Linux.
> >
> > Thanks,
> > Addison
> >
> >
> >
> --
> York Sun
>
> This email, and any associated attachments have been classified as:
> [x] Freescale Semiconductor General Business
> [ ] Freescale Semiconductor Internal Use Only
> [ ] Freescale Semiconductor Confidential Proprietary
>
> _______________________________________________
> Linuxppc-embedded mailing list
> Linuxppc-embedded@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-embedded
------------------------------
我现在使用Sogou.com的2G邮箱了，你也来试试吧!
http://mail.sogou.com/recommend/sogoumail_invite_reg1.jsp?from=sogouinvitation&s_EMAIL=zengshuai%40sogou.com&username=&FullName=&Email=&verify=e197bd6dbd1fc7f8d6a035729df08d63
^ permalink raw reply
* Re: [PATCH] ppc32: Adds MPC885ADS, MPC866ADS and MPC8272ADS-specific platform stuff for fs_enet
From: Matthew McClintock @ 2005-12-06 5:49 UTC (permalink / raw)
To: Vitaly Bordug; +Cc: linuxppc-embedded list
In-Reply-To: <438B379B.6090904@ru.mvista.com>
On Mon, 2005-11-28 at 10:00 -0700, Vitaly Bordug wrote:
> + mpc82xx_fcc1_pdata.dpram_offset =
> mpc82xx_fcc2_pdata.dpram_offset = (u32)cpm2_immr->im_dprambase;
> + mpc82xx_fcc1_pdata.fcc_regs_c = mpc82xx_fcc2_pdata.fcc_regs_c
> = (u32)cpm2_immr->im_fcc_c;
I'm not sure if this has already been discussed, but what is stopping us
from including this in the platform definition files along with the
other offsets?
-Matthew
^ permalink raw reply
* Does this Bug fixed ?
From: sairam k @ 2005-12-06 5:29 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <c6be647f0512052125hecac836pf9891a346e9327e8@mail.gmail.com>
[-- Attachment #1: Type: text/plain, Size: 1591 bytes --]
1) I used linuxppc_2_4_devel PowerPC development tree source(from
ppc.bkbits.net) to build kernel for PowerPC IBM405EP(evb405ep_defconfig) and
montavista's gcc cross compiler for ppc_405-
2)I gave the following commands..
make evb405ep_config
make mrproper
make clean
make dep
make zImage
3) when i gave 'make zImage' command, the compilation stopped abnormally and
gave error that OPB_BASE_START symbol is unknown in file ibm405ep.c
(arch/ppc/platforms/ibm405ep.c)
4) The point in source code where problem is arising is shown below....
-----------------------------------------------------------------------
..................
struct ocp_def core_ocp[] __initdata = {
{ .vendor = OCP_VENDOR_IBM,
.function = OCP_FUNC_OPB,
.index = 0,
.paddr = OPB_BASE_START, // UNKOWN SYMBOL
.irq = OCP_IRQ_NA,
.pm = OCP_CPM_NA,
.........
..........
----------------------------------------------------------------------
Suggestion 1) I fixed this bug by providing the OPB_BASE_START address.
Since the core of ibm405EP is same as that of ibm405Gp & ibm405Gpr, the
OPB_BASE_START address will be same for all.
So just include the following line in ibm405ep.h
(ie., in arch/ppc/platforms/ibm405ep.h)
#define OPB_BASE_START 0x40000000
2) After adding the above line, I recompiled the sources again....and this
time it compiled and i am able to work on IBM405Ep board.
(configuration file for IBm405ep is 'evb405ep_defconfig' in configs folder)
Does anyone fixed this bug........if so why it is not reflected in bkbits
[-- Attachment #2: Type: text/html, Size: 2813 bytes --]
^ permalink raw reply
* Re: PowerBook5,8 - TrackPad update
From: Andy Botting @ 2005-12-06 3:38 UTC (permalink / raw)
To: Michael Hanselmann
Cc: Stelian Pop, Parag Warudkar, linux-kernel, linuxppc-dev,
debian-powerpc, johannes
In-Reply-To: <20051204224221.GA28218@hansmi.ch>
I managed to get this working on my 15" PowerBook, but the USB id for my
Keyboard/Trackpad is 0x0214 as opposed to the 0x0215 you have in the
patch. Are you going to add 0x0214 (and any others?) to this patch
before sending it off?
Also, I found that the patch didn't apply cleanly on my kernel
2.6.15-rc5 kernel. I think many of the line numbers were out, so I ended
up patching the file manually.
cheers,
-Andy
On Sun, 2005-12-04 at 23:42 +0100, Michael Hanselmann wrote:
> On Fri, Dec 02, 2005 at 03:28:31PM +0100, Stelian Pop wrote:
> > Is this version really working well on the new Powerbooks ? From what
> > I've seen in this thread there are still issues and it's still a work
> > in progress, so it may be too early to integrate the changes in the
> > kernel.
>
> It works fine for the 15" PowerBooks (Oct 2005) and has been tested by
> at least three people. 17" should work too, but I can't test that until
> later this week.
>
> > +#if defined(CONFIG_RELAYFS_FS) || defined(CONFIG_RELAYFS_FS_MODULE)
> > +#include <linux/relayfs_fs.h>
> > +#endif
>
> > While the relayfs code is ok for debugging, I'm wondering if it should
> > be left in the final version at all.
>
> It doesn't hurt as it's not much code, it makes updating the driver for
> newer devices easier and it's only enabled if requested. Because of
> that, I would leave it in. However, I can split it into a separate patch
> if wanted.
>
> > + int overflowwarn; /* overflow warning printed? */
>
> > I would use a static variable in the case -OVERFLOW: block here.
>
> As there could be, due to whatever reason, multiple devices using the
> same driver, one could overflow while another doesn't. Therefore, it
> should be device specific.
>
> > + dev->xy_cur[i++] = dev->data[19];
> > + dev->xy_cur[i++] = dev->data[20];
> > + dev->xy_cur[i++] = dev->data[22];
> > + dev->xy_cur[i++] = dev->data[23];
>
> > There is obviously a pattern here:
>
> > for (i = 0; i < 15; i++)
> > dev->xy_cur[i] = dev->data[ 19 + (i * 3) / 2 ]
>
> It's not that easy. This code wouldn't work as it should.
>
> I wrote a working loop into the patch below, but as the code's called
> about 1'000 times a second I unrolled the loop myself. A friend of mine
> calculated that the code would take at least twice the time to run when
> written using a loop.
>
> > I'm wondering if the same formula doesn't apply for more X and Y
> > sensors (like 16 X and 16 Y sensors on the old Powerbooks, 26 for the
> > 17" models)
>
> It does and is addressed in the new patch below.
>
> > What is the point in doing this since the dbg_dump is called a few lines
> > later ?
>
> Those were some leftovers from my debugging and would have been deleted
> before submitting. I just didn't want to take everything out if someone
> else wants to do some extensive debugging or so.
>
> Here's an updated patch including support for the 17" PowerBooks (Oct
> 2005). The informations about the 17" one are from Alex Harper.
>
> ---
> --- linux-2.6.15-rc5/drivers/usb/input/appletouch.c.orig 2005-12-04 20:25:21.000000000 +0100
> +++ linux-2.6.15-rc5/drivers/usb/input/appletouch.c 2005-12-04 23:37:29.000000000 +0100
> @@ -6,9 +6,19 @@
> * Copyright (C) 2005 Stelian Pop (stelian@popies.net)
> * Copyright (C) 2005 Frank Arnold (frank@scirocco-5v-turbo.de)
> * Copyright (C) 2005 Peter Osterlund (petero2@telia.com)
> + * Copyright (C) 2005 Parag Warudkar (parag.warudkar@gmail.com)
> + * Copyright (C) 2005 Michael Hanselmann (linux-kernel@hansmi.ch)
> *
> * Thanks to Alex Harper <basilisk@foobox.net> for his inputs.
> *
> + * Nov 2005 - Parag Warudkar
> + * o Added ability to export data via relayfs
> + *
> + * Nov 2005 - Michael Hanselmann
> + * o Compile relayfs support only if enabled in the kernel
> + * o Enable relayfs only if requested by the user
> + * o Added support for new October 2005 PowerBooks (Geyser 2)
> + *
> * This program is free software; you can redistribute it and/or modify
> * it under the terms of the GNU General Public License as published by
> * the Free Software Foundation; either version 2 of the License, or
> @@ -35,8 +45,13 @@
> #include <linux/input.h>
> #include <linux/usb_input.h>
>
> +#if defined(CONFIG_RELAYFS_FS) || defined(CONFIG_RELAYFS_FS_MODULE)
> +#include <linux/relayfs_fs.h>
> +#endif
> +
> /* Apple has powerbooks which have the keyboard with different Product IDs */
> #define APPLE_VENDOR_ID 0x05AC
> +#define GEYSER_2_PRODUCT_ID 0x0215
>
> #define ATP_DEVICE(prod) \
> .match_flags = USB_DEVICE_ID_MATCH_DEVICE | \
> @@ -51,14 +66,17 @@
> static struct usb_device_id atp_table [] = {
> { ATP_DEVICE(0x020E) },
> { ATP_DEVICE(0x020F) },
> + { ATP_DEVICE(GEYSER_2_PRODUCT_ID) }, /* PowerBooks Oct 2005 */
> { ATP_DEVICE(0x030A) },
> { ATP_DEVICE(0x030B) },
> { } /* Terminating entry */
> };
> MODULE_DEVICE_TABLE (usb, atp_table);
>
> -/* size of a USB urb transfer */
> -#define ATP_DATASIZE 81
> +#if defined(CONFIG_RELAYFS_FS) || defined(CONFIG_RELAYFS_FS_MODULE)
> +struct rchan* rch = NULL;
> +struct rchan_callbacks* rcb = NULL;
> +#endif
>
> /*
> * number of sensors. Note that only 16 instead of 26 X (horizontal)
> @@ -73,6 +91,7 @@
>
> /* maximum pressure this driver will report */
> #define ATP_PRESSURE 300
> +
> /*
> * multiplication factor for the X and Y coordinates.
> * We try to keep the touchpad aspect ratio while still doing only simple
> @@ -108,6 +127,8 @@
> signed char xy_old[ATP_XSENSORS + ATP_YSENSORS];
> /* accumulated sensors */
> int xy_acc[ATP_XSENSORS + ATP_YSENSORS];
> + int overflowwarn; /* overflow warning printed? */
> + int datalen; /* size of an USB urb transfer */
> };
>
> #define dbg_dump(msg, tab) \
> @@ -124,7 +145,11 @@
> if (debug) printk(format, ##a); \
> } while (0)
>
> -MODULE_AUTHOR("Johannes Berg, Stelian Pop, Frank Arnold");
> +/* Checks if the device a Geyser 2 */
> +#define IS_GEYSER_2(dev) \
> + (le16_to_cpu(dev->udev->descriptor.idProduct) == GEYSER_2_PRODUCT_ID)
> +
> +MODULE_AUTHOR("Johannes Berg, Stelian Pop, Frank Arnold, Parag Warudkar, Michael Hanselmann");
> MODULE_DESCRIPTION("Apple PowerBooks USB touchpad driver");
> MODULE_LICENSE("GPL");
>
> @@ -132,6 +157,10 @@
> module_param(debug, int, 0644);
> MODULE_PARM_DESC(debug, "Activate debugging output");
>
> +static int relayfs = 0;
> +module_param(relayfs, int, 0644);
> +MODULE_PARM_DESC(relayfs, "Activate relayfs support");
> +
> static int atp_calculate_abs(int *xy_sensors, int nb_sensors, int fact,
> int *z, int *fingers)
> {
> @@ -175,6 +204,13 @@
> case 0:
> /* success */
> break;
> + case -EOVERFLOW:
> + if(!dev->overflowwarn) {
> + printk("appletouch: OVERFLOW with data "
> + "length %d, actual length is %d\n",
> + dev->datalen, dev->urb->actual_length);
> + dev->overflowwarn = 1;
> + }
> case -ECONNRESET:
> case -ENOENT:
> case -ESHUTDOWN:
> @@ -189,23 +225,83 @@
> }
>
> /* drop incomplete datasets */
> - if (dev->urb->actual_length != ATP_DATASIZE) {
> + if (dev->urb->actual_length != dev->datalen) {
> dprintk("appletouch: incomplete data package.\n");
> goto exit;
> }
>
> +#if defined(CONFIG_RELAYFS_FS) || defined(CONFIG_RELAYFS_FS_MODULE)
> + if (relayfs && dev->data) {
> + relay_write(rch, dev->data, dev->urb->actual_length);
> + }
> +#endif
> +
> /* reorder the sensors values */
> - for (i = 0; i < 8; i++) {
> + if (IS_GEYSER_2(dev)) {
> + memset(dev->xy_cur, 0, sizeof(dev->xy_cur));
> +
> + /*
> + * The values are laid out like this:
> + * Y1, Y2, -, Y3, Y4, -, ...
> + * '-' is an unused value.
> + *
> + * The logic in a loop:
> + * for (i = 0, j = 19; i < 20; i += 2, j += 3) {
> + * dev->xy_cur[i] = dev->data[j];
> + * dev->xy_cur[i + 1] = dev->data[j + 1];
> + * }
> + *
> + * This code is called about 1'000 times per second for each
> + * interrupt from the touchpad. Therefore it should be as fast
> + * as possible. Writing the following code in a loop would take
> + * about twice the time to run if not more.
> + */
> +
> /* X values */
> - dev->xy_cur[i ] = dev->data[5 * i + 2];
> - dev->xy_cur[i + 8] = dev->data[5 * i + 4];
> - dev->xy_cur[i + 16] = dev->data[5 * i + 42];
> - if (i < 2)
> - dev->xy_cur[i + 24] = dev->data[5 * i + 44];
> + dev->xy_cur[0] = dev->data[19];
> + dev->xy_cur[1] = dev->data[20];
> + dev->xy_cur[2] = dev->data[22];
> + dev->xy_cur[3] = dev->data[23];
> + dev->xy_cur[4] = dev->data[25];
> + dev->xy_cur[5] = dev->data[26];
> + dev->xy_cur[6] = dev->data[28];
> + dev->xy_cur[7] = dev->data[29];
> + dev->xy_cur[8] = dev->data[31];
> + dev->xy_cur[9] = dev->data[32];
> + dev->xy_cur[10] = dev->data[34];
> + dev->xy_cur[11] = dev->data[35];
> + dev->xy_cur[12] = dev->data[37];
> + dev->xy_cur[13] = dev->data[38];
> + dev->xy_cur[14] = dev->data[40];
> + dev->xy_cur[15] = dev->data[41];
> + dev->xy_cur[16] = dev->data[43];
> + dev->xy_cur[17] = dev->data[44];
> + dev->xy_cur[18] = dev->data[46];
> + dev->xy_cur[19] = dev->data[47];
>
> /* Y values */
> - dev->xy_cur[i + 26] = dev->data[5 * i + 1];
> - dev->xy_cur[i + 34] = dev->data[5 * i + 3];
> + dev->xy_cur[ATP_XSENSORS + 0] = dev->data[1];
> + dev->xy_cur[ATP_XSENSORS + 1] = dev->data[2];
> + dev->xy_cur[ATP_XSENSORS + 2] = dev->data[4];
> + dev->xy_cur[ATP_XSENSORS + 3] = dev->data[5];
> + dev->xy_cur[ATP_XSENSORS + 4] = dev->data[7];
> + dev->xy_cur[ATP_XSENSORS + 5] = dev->data[8];
> + dev->xy_cur[ATP_XSENSORS + 6] = dev->data[10];
> + dev->xy_cur[ATP_XSENSORS + 7] = dev->data[11];
> + dev->xy_cur[ATP_XSENSORS + 8] = dev->data[13];
> + } else {
> + for (i = 0; i < 8; i++) {
> + /* X values */
> + dev->xy_cur[i ] = dev->data[5 * i + 2];
> + dev->xy_cur[i + 8] = dev->data[5 * i + 4];
> + dev->xy_cur[i + 16] = dev->data[5 * i + 42];
> + if (i < 2)
> + dev->xy_cur[i + 24] = dev->data[5 * i + 44];
> +
> + /* Y values */
> + dev->xy_cur[i + 26] = dev->data[5 * i + 1];
> + dev->xy_cur[i + 34] = dev->data[5 * i + 3];
> + }
> }
>
> dbg_dump("sample", dev->xy_cur);
> @@ -216,16 +312,23 @@
> dev->x_old = dev->y_old = -1;
> memcpy(dev->xy_old, dev->xy_cur, sizeof(dev->xy_old));
>
> - /* 17" Powerbooks have 10 extra X sensors */
> - for (i = 16; i < ATP_XSENSORS; i++)
> - if (dev->xy_cur[i]) {
> - printk("appletouch: 17\" model detected.\n");
> + /* 17" Powerbooks have extra X sensors */
> + for (i = (IS_GEYSER_2(dev)?15:16); i < ATP_XSENSORS; i++) {
> + if (!dev->xy_cur[i]) continue;
> +
> + printk("appletouch: 17\" model detected.\n");
> + if(IS_GEYSER_2(dev))
> + input_set_abs_params(dev->input, ABS_X, 0,
> + (20 - 1) *
> + ATP_XFACT - 1,
> + ATP_FUZZ, 0);
> + else
> input_set_abs_params(dev->input, ABS_X, 0,
> (ATP_XSENSORS - 1) *
> ATP_XFACT - 1,
> ATP_FUZZ, 0);
> - break;
> - }
> + break;
> + }
>
> goto exit;
> }
> @@ -282,7 +385,8 @@
> memset(dev->xy_acc, 0, sizeof(dev->xy_acc));
> }
>
> - input_report_key(dev->input, BTN_LEFT, !!dev->data[80]);
> + input_report_key(dev->input, BTN_LEFT,
> + !!dev->data[dev->datalen - 1]);
>
> input_sync(dev->input);
>
> @@ -323,7 +427,6 @@
> int int_in_endpointAddr = 0;
> int i, retval = -ENOMEM;
>
> -
> /* set up the endpoint information */
> /* use only the first interrupt-in endpoint */
> iface_desc = iface->cur_altsetting;
> @@ -353,6 +456,8 @@
>
> dev->udev = udev;
> dev->input = input_dev;
> + dev->overflowwarn = 0;
> + dev->datalen = (IS_GEYSER_2(dev)?64:81);
>
> dev->urb = usb_alloc_urb(0, GFP_KERNEL);
> if (!dev->urb) {
> @@ -360,7 +465,7 @@
> goto err_free_devs;
> }
>
> - dev->data = usb_buffer_alloc(dev->udev, ATP_DATASIZE, GFP_KERNEL,
> + dev->data = usb_buffer_alloc(dev->udev, dev->datalen, GFP_KERNEL,
> &dev->urb->transfer_dma);
> if (!dev->data) {
> retval = -ENOMEM;
> @@ -369,7 +474,7 @@
>
> usb_fill_int_urb(dev->urb, udev,
> usb_rcvintpipe(udev, int_in_endpointAddr),
> - dev->data, ATP_DATASIZE, atp_complete, dev, 1);
> + dev->data, dev->datalen, atp_complete, dev, 1);
>
> usb_make_path(udev, dev->phys, sizeof(dev->phys));
> strlcat(dev->phys, "/input0", sizeof(dev->phys));
> @@ -385,14 +490,25 @@
>
> set_bit(EV_ABS, input_dev->evbit);
>
> - /*
> - * 12" and 15" Powerbooks only have 16 x sensors,
> - * 17" models are detected later.
> - */
> - input_set_abs_params(input_dev, ABS_X, 0,
> - (16 - 1) * ATP_XFACT - 1, ATP_FUZZ, 0);
> - input_set_abs_params(input_dev, ABS_Y, 0,
> - (ATP_YSENSORS - 1) * ATP_YFACT - 1, ATP_FUZZ, 0);
> + if (IS_GEYSER_2(dev)) {
> + /*
> + * Oct 2005 15" PowerBooks have 15 X sensors, 17" are detected
> + * later.
> + */
> + input_set_abs_params(input_dev, ABS_X, 0,
> + ((15 - 1) * ATP_XFACT) - 1, ATP_FUZZ, 0);
> + input_set_abs_params(input_dev, ABS_Y, 0,
> + ((9 - 1) * ATP_YFACT) - 1, ATP_FUZZ, 0);
> + } else {
> + /*
> + * 12" and 15" Powerbooks only have 16 x sensors,
> + * 17" models are detected later.
> + */
> + input_set_abs_params(input_dev, ABS_X, 0,
> + (16 - 1) * ATP_XFACT - 1, ATP_FUZZ, 0);
> + input_set_abs_params(input_dev, ABS_Y, 0,
> + (ATP_YSENSORS - 1) * ATP_YFACT - 1, ATP_FUZZ, 0);
> + }
> input_set_abs_params(input_dev, ABS_PRESSURE, 0, ATP_PRESSURE, 0, 0);
>
> set_bit(EV_KEY, input_dev->evbit);
> @@ -427,7 +543,7 @@
> usb_kill_urb(dev->urb);
> input_unregister_device(dev->input);
> usb_free_urb(dev->urb);
> - usb_buffer_free(dev->udev, ATP_DATASIZE,
> + usb_buffer_free(dev->udev, dev->datalen,
> dev->data, dev->urb->transfer_dma);
> kfree(dev);
> }
> @@ -463,11 +579,30 @@
>
> static int __init atp_init(void)
> {
> +#if defined(CONFIG_RELAYFS_FS) || defined(CONFIG_RELAYFS_FS_MODULE)
> + if (relayfs) {
> + rcb = kmalloc(sizeof(struct rchan_callbacks), GFP_KERNEL);
> + rcb->subbuf_start = NULL;
> + rcb->buf_mapped = NULL;
> + rcb->buf_unmapped = NULL;
> + rch = relay_open("atpdata", NULL, 256, 256, NULL);
> + if (!rch) return -ENOMEM;
> + printk("appletouch: Relayfs enabled.\n");
> + } else {
> + printk("appletouch: Relayfs disabled.\n");
> + }
> +#endif
> return usb_register(&atp_driver);
> }
>
> static void __exit atp_exit(void)
> {
> +#if defined(CONFIG_RELAYFS_FS) || defined(CONFIG_RELAYFS_FS_MODULE)
> + if (relayfs) {
> + relay_close(rch);
> + kfree(rcb);
> + }
> +#endif
> usb_deregister(&atp_driver);
> }
>
>
>
^ permalink raw reply
* SPI on the MPC8541
From: Gabe.Johnson @ 2005-12-05 21:46 UTC (permalink / raw)
To: linuxppc-embedded
[-- Attachment #1: Type: text/plain, Size: 501 bytes --]
This is my first time using the mailing list so hello.
I am trying to find a SPI driver. The SPI is located in the CPM2 block on
a MPC8541. I am working with the freescale MPC85xxCDS reference board.
Could someone point me in the right direction or let me know if I should
just write my own driver. All of the SPI code I have found seems to just
use a serial port, parallel port or bit bang the data out a GPIO. I want
a driver that uses the registers that are available to me.
Thanks,
Gabe
[-- Attachment #2: Type: text/html, Size: 699 bytes --]
^ permalink raw reply
* Re: [PATCH 1/2] Move Virtex-II Pro / ML300 port over to the platform bus.
From: Peter Korsgaard @ 2005-12-05 20:52 UTC (permalink / raw)
To: Grant Likely; +Cc: linuxppc-embedded
In-Reply-To: <43947B7E.7080204@gmail.com>
>>>>> "Grant" == Grant Likely <glikely@gmail.com> writes:
Grant> Hey, what boards do you have access to? I'm going to lose my ML300
Grant> shortly, but I've just got an ML403.
I don't have access to any Xilinx eval boards, but we have done quite
some V2P/PPC based designs that I could test it on.
--
Bye, Peter Korsgaard
^ permalink raw reply
* [PATCH] STXXTC: Delete commented out code.
From: Pantelis Antoniou @ 2005-12-05 21:19 UTC (permalink / raw)
To: Marcelo Tosatti, Dan Malek, linuxppc-embedded,
Benjamin Herrenschmidt
STXXTC: Deleted commented out code. Ugh.
---
commit 3c8f5b1e6edbe76619011e505e009aad6df0bd91
tree eb1769cf2e0c2095a5d51d28f489e4b3aa44773c
parent fac9bbd80d8f8ab3c6af5a417f804dbf8537c700
author Pantelis Antoniou <pantelis.antoniou@gmail.com> Mon, 05 Dec 2005 23:15:03 +0200
committer Pantelis Antoniou <pantelis.antoniou@gmail.com> Mon, 05 Dec 2005 23:15:03 +0200
arch/ppc/platforms/stxxtc_setup.c | 11 -------
drivers/mtd/maps/stxxtc_nor.c | 58 -------------------------------------
2 files changed, 0 insertions(+), 69 deletions(-)
diff --git a/arch/ppc/platforms/stxxtc_setup.c b/arch/ppc/platforms/stxxtc_setup.c
--- a/arch/ppc/platforms/stxxtc_setup.c
+++ b/arch/ppc/platforms/stxxtc_setup.c
@@ -30,17 +30,6 @@
/***********************************************************************/
-#ifdef CONFIG_FW_ENV
-#include <syslib/fw_env.h>
-
-static const char *ro_vars[] = {
- "ethaddr", "eth1addr", "adsladdr", "serial#", "usbaddr", "usb1addr", "ver", "board",
- NULL
-};
-#endif
-
-/***********************************************************************/
-
static spinlock_t port_spinlock;
unsigned long pin_lock(void)
diff --git a/drivers/mtd/maps/stxxtc_nor.c b/drivers/mtd/maps/stxxtc_nor.c
--- a/drivers/mtd/maps/stxxtc_nor.c
+++ b/drivers/mtd/maps/stxxtc_nor.c
@@ -114,8 +114,6 @@ static struct stxxtc_nor_info info[NR_CH
}
};
-#if 1
-
int __init init_stxxtc_nor(void)
{
struct stxxtc_nor_info *ni;
@@ -262,62 +260,6 @@ static void __exit cleanup_stxxtc_nor(vo
}
-#else
-
-int __init init_stxxtc_nor(void)
-{
- int err = 0;
- static const char *probes[] = { "cfi_probe", NULL };
- const char **sv, *s;
-
- stxxtc_map.virt = (void __iomem *)ioremap(WINDOW_ADDR, WINDOW_SIZE);
- if (!stxxtc_map.virt) {
- printk("stxxtc_nor: Failed to ioremap\n");
- err = -ENXIO;
- goto out;
- }
- simple_map_init(&stxxtc_map);
-
- sv = probes;
- while ((s = *sv++) != NULL) {
- stxxtc_mtd = do_map_probe(s, &stxxtc_map);
- if (stxxtc_mtd != NULL)
- break;
- }
-
- if (!stxxtc_mtd) {
- printk(KERN_NOTICE "stxxtc_nor: probe failed flash device: %x at %x\n", WINDOW_SIZE, WINDOW_ADDR);
- err = -ENXIO;
- goto out_unmap;
- }
-
- stxxtc_mtd->owner = THIS_MODULE;
- add_mtd_partitions(stxxtc_mtd, pi, NUM_PARTITIONS);
-
- return 0;
-
-out_unmap:
- iounmap((void *)stxxtc_map.virt);
-out:
-
- return err;
-}
-
-static void __exit cleanup_stxxtc_nor(void)
-{
- if (stxxtc_mtd) {
- del_mtd_partitions(stxxtc_mtd);
- map_destroy(stxxtc_mtd);
- stxxtc_mtd = 0;
- }
- if (stxxtc_map.virt) {
- iounmap(stxxtc_map.virt);
- stxxtc_map.virt = 0;
- }
-}
-
-#endif
-
module_init(init_stxxtc_nor);
module_exit(cleanup_stxxtc_nor);
!-------------------------------------------------------------flip-
^ permalink raw reply
* RFC: Rev 0.5 Booting the Linux/ppc kernel without Open Firmware
From: Jon Loeliger @ 2005-12-05 21:06 UTC (permalink / raw)
To: linuxppc-dev@ozlabs.org, linuxppc64-dev
Folks,
Included below is a proposed Revision 0.5 of the
"Booting the Linux/ppc kernel without Open Firmware"
document. This modification primarily extends the
Revision 0.4 by adding definitions for OF Nodes that
cover the System-On-a-Chip features found on PPC parts.
It also generalizes some earlier wording that pertained
to only PPC64 parts and covers the new, merged PPC 32
and 64 parts together. Finally, minor typos, style
consistency and grammar problems were corrected.
Please review this document, primarily Chapter VI, so
that we may all proceed with the PPC32/64 merge tree
development in a consistent, unified direction.
While some effort has been made to follow standard OF
nomenclature, terminology and standards, I confess that
the authors of these additions are not experts in this
area and my have missed details or key insights, or
allowed for glaring errors. Our goal is collective
improvement here, so be gentle when you call us stupid. :-)
Thanks,
jdl
Booting the Linux/ppc kernel without Open Firmware
--------------------------------------------------
(c) 2005 Benjamin Herrenschmidt <benh at kernel.crashing.org>,
IBM Corp.
(c) 2005 Becky Bruce <becky.bruce at freescale.com>,
Freescale Semiconductor, FSL SOC and 32-bit additions
May 18, 2005: Rev 0.1 - Initial draft, no chapter III yet.
May 19, 2005: Rev 0.2 - Add chapter III and bits & pieces here or
clarifies the fact that a lot of things are
optional, the kernel only requires a very
small device tree, though it is encouraged
to provide an as complete one as possible.
May 24, 2005: Rev 0.3 - Precise that DT block has to be in RAM
- Misc fixes
- Define version 3 and new format version 16
for the DT block (version 16 needs kernel
patches, will be fwd separately).
String block now has a size, and full path
is replaced by unit name for more
compactness.
linux,phandle is made optional, only nodes
that are referenced by other nodes need it.
"name" property is now automatically
deduced from the unit name
June 1, 2005: Rev 0.4 - Correct confusion between OF_DT_END and
OF_DT_END_NODE in structure definition.
- Change version 16 format to always align
property data to 4 bytes. Since tokens are
already aligned, that means no specific
required alignement between property size
and property data. The old style variable
alignment would make it impossible to do
"simple" insertion of properties using
memove (thanks Milton for
noticing). Updated kernel patch as well
- Correct a few more alignement constraints
- Add a chapter about the device-tree
compiler and the textural representation of
the tree that can be "compiled" by dtc.
November 21, 2005: Rev 0.5
- Additions/generalizations for 32-bit
- Changed to reflect the new arch/powerpc
structure
- Added chapter VI
ToDo:
- Add some definitions of interrupt tree (simple/complex)
- Add some definitions for pci host bridges
- Add some common address format examples
- Add definitions for standard properties and "compatible"
names for cells that are not already defined by the existing
OF spec.
- Compare FSL SOC use of PCI to standard and make sure no new
node definition required.
- Add more information about node definitions for SOC devices
that currently have no standard, like the FSL CPM.
I - Introduction
================
During the recent development of the Linux/ppc64 kernel, and more
specifically, the addition of new platform types outside of the old
IBM pSeries/iSeries pair, it was decided to enforce some strict rules
regarding the kernel entry and bootloader <-> kernel interfaces, in
order to avoid the degeneration that had become the ppc32 kernel entry
point and the way a new platform should be added to the kernel. The
legacy iSeries platform breaks those rules as it predates this scheme,
but no new board support will be accepted in the main tree that
doesn't follows them properly. In addition, since the advent of the
arch/powerpc merged architecture for ppc32 and ppc64, new 32-bit
platforms and 32-bit platforms which move into arch/powerpc will be
required to use these rules as well.
The main requirement that will be defined in more detail below is
the presence of a device-tree whose format is defined after Open
Firmware specification. However, in order to make life easier
to embedded board vendors, the kernel doesn't require the device-tree
to represent every device in the system and only requires some nodes
and properties to be present. This will be described in detail in
section III, but, for example, the kernel does not require you to
create a node for every PCI device in the system. It is a requirement
to have a node for PCI host bridges in order to provide interrupt
routing informations and memory/IO ranges, among others. It is also
recommended to define nodes for on chip devices and other busses that
don't specifically fit in an existing OF specification. This creates a
great flexibility in the way the kernel can then probe those and match
drivers to device, without having to hard code all sorts of tables. It
also makes it more flexible for board vendors to do minor hardware
upgrades without significantly impacting the kernel code or cluttering
it with special cases.
1) Entry point for arch/powerpc
-------------------------------
There is one and one single entry point to the kernel, at the start
of the kernel image. That entry point supports two calling
conventions:
a) Boot from Open Firmware. If your firmware is compatible
with Open Firmware (IEEE 1275) or provides an OF compatible
client interface API (support for "interpret" callback of
forth words isn't required), you can enter the kernel with:
r5 : OF callback pointer as defined by IEEE 1275
bindings to powerpc. Only the 32 bit client interface
is currently supported
r3, r4 : address & length of an initrd if any or 0
The MMU is either on or off; the kernel will run the
trampoline located in arch/powerpc/kernel/prom_init.c to
extract the device-tree and other information from open
firmware and build a flattened device-tree as described
in b). prom_init() will then re-enter the kernel using
the second method. This trampoline code runs in the
context of the firmware, which is supposed to handle all
exceptions during that time.
b) Direct entry with a flattened device-tree block. This entry
point is called by a) after the OF trampoline and can also be
called directly by a bootloader that does not support the Open
Firmware client interface. It is also used by "kexec" to
implement "hot" booting of a new kernel from a previous
running one. This method is what I will describe in more
details in this document, as method a) is simply standard Open
Firmware, and thus should be implemented according to the
various standard documents defining it and its binding to the
PowerPC platform. The entry point definition then becomes:
r3 : physical pointer to the device-tree block
(defined in chapter II) in RAM
r4 : physical pointer to the kernel itself. This is
used by the assembly code to properly disable the MMU
in case you are entering the kernel with MMU enabled
and a non-1:1 mapping.
r5 : NULL (as to differenciate with method a)
Note about SMP entry: Either your firmware puts your other
CPUs in some sleep loop or spin loop in ROM where you can get
them out via a soft reset or some other means, in which case
you don't need to care, or you'll have to enter the kernel
with all CPUs. The way to do that with method b) will be
described in a later revision of this document.
2) Board support
----------------
64-bit kernels:
Board supports (platforms) are not exclusive config options. An
arbitrary set of board supports can be built in a single kernel
image. The kernel will "know" what set of functions to use for a
given platform based on the content of the device-tree. Thus, you
should:
a) add your platform support as a _boolean_ option in
arch/powerpc/Kconfig, following the example of PPC_PSERIES,
PPC_PMAC and PPC_MAPLE. The later is probably a good
example of a board support to start from.
b) create your main platform file as
"arch/powerpc/platforms/myplatform/myboard_setup.c" and add it
to the Makefile under the condition of your CONFIG_
option. This file will define a structure of type "ppc_md"
containing the various callbacks that the generic code will
use to get to your platform specific code
c) Add a reference to your "ppc_md" structure in the
"machines" table in arch/powerpc/kernel/setup_64.c if you are
a 64-bit platform.
d) request and get assigned a platform number (see PLATFORM_*
constants in include/asm-powerpc/processor.h
32-bit embedded kernels:
Currently, board support is essentially an exclusive config option.
The kernel is configured for a single platform. Part of the reason
for this is to keep kernels on embedded systems small and efficient;
part of this is due to the fact the code is already that way. In the
future, a kernel may support multiple platforms, but only if the
platforms feature the same core architectire. A single kernel build
cannot support both configurations with Book E and configurations
with classic Powerpc architectures.
32-bit embedded platforms that are moved into arch/powerpc using a
flattened device tree should adopt the merged tree practice of
setting ppc_md up dynamically, even though the kernel is currently
built with support for only a single platform at a time. This allows
unification of the setup code, and will make it easier to go to a
multiple-platform-support model in the future.
NOTE: I believe the above will be true once Ben's done with the merge
of the boot sequences.... someone speak up if this is wrong!
To add a 32-bit embedded platform support, follow the instructions
for 64-bit platforms above, with the exception that the Kconfig
option should be set up such that the kernel builds exclusively for
the platform selected. The processor type for the platform should
enable another config option to select the specific board
supported.
NOTE: If ben doesn't merge the setup files, may need to change this to
point to setup_32.c
I will describe later the boot process and various callbacks that
your platform should implement.
II - The DT block format
========================
This chapter defines the actual format of the flattened device-tree
passed to the kernel. The actual content of it and kernel requirements
are described later. You can find example of code manipulating that
format in various places, including arch/powerpc/kernel/prom_init.c
which will generate a flattened device-tree from the Open Firmware
representation, or the fs2dt utility which is part of the kexec tools
which will generate one from a filesystem representation. It is
expected that a bootloader like uboot provides a bit more support,
that will be discussed later as well.
Note: The block has to be in main memory. It has to be accessible in
both real mode and virtual mode with no mapping other than main
memory. If you are writing a simple flash bootloader, it should copy
the block to RAM before passing it to the kernel.
1) Header
---------
The kernel is entered with r3 pointing to an area of memory that is
roughtly described in include/asm-powerpc/prom.h by the structure
boot_param_header:
struct boot_param_header {
u32 magic; /* magic word OF_DT_HEADER */
u32 totalsize; /* total size of DT block */
u32 off_dt_struct; /* offset to structure */
u32 off_dt_strings; /* offset to strings */
u32 off_mem_rsvmap; /* offset to memory reserve map
*/
u32 version; /* format version */
u32 last_comp_version; /* last compatible version */
/* version 2 fields below */
u32 boot_cpuid_phys; /* Which physical CPU id we're
booting on */
/* version 3 fields below */
u32 size_dt_strings; /* size of the strings block */
};
Along with the constants:
/* Definitions used by the flattened device tree */
#define OF_DT_HEADER 0xd00dfeed /* 4: version,
4: total size */
#define OF_DT_BEGIN_NODE 0x1 /* Start node: full name
*/
#define OF_DT_END_NODE 0x2 /* End node */
#define OF_DT_PROP 0x3 /* Property: name off,
size, content */
#define OF_DT_END 0x9
All values in this header are in big endian format, the various
fields in this header are defined more precisely below. All
"offset" values are in bytes from the start of the header; that is
from the value of r3.
- magic
This is a magic value that "marks" the beginning of the
device-tree block header. It contains the value 0xd00dfeed and is
defined by the constant OF_DT_HEADER
- totalsize
This is the total size of the DT block including the header. The
"DT" block should enclose all data structures defined in this
chapter (who are pointed to by offsets in this header). That is,
the device-tree structure, strings, and the memory reserve map.
- off_dt_struct
This is an offset from the beginning of the header to the start
of the "structure" part the device tree. (see 2) device tree)
- off_dt_strings
This is an offset from the beginning of the header to the start
of the "strings" part of the device-tree
- off_mem_rsvmap
This is an offset from the beginning of the header to the start
of the reserved memory map. This map is a list of pairs of 64
bit integers. Each pair is a physical address and a size. The
list is terminated by an entry of size 0. This map provides the
kernel with a list of physical memory areas that are "reserved"
and thus not to be used for memory allocations, especially during
early initialization. The kernel needs to allocate memory during
boot for things like un-flattening the device-tree, allocating an
MMU hash table, etc... Those allocations must be done in such a
way to avoid overriding critical things like, on Open Firmware
capable machines, the RTAS instance, or on some pSeries, the TCE
tables used for the iommu. Typically, the reserve map should
contain _at least_ this DT block itself (header,total_size). If
you are passing an initrd to the kernel, you should reserve it as
well. You do not need to reserve the kernel image itself. The map
should be 64 bit aligned.
- version
This is the version of this structure. Version 1 stops
here. Version 2 adds an additional field boot_cpuid_phys.
Version 3 adds the size of the strings block, allowing the kernel
to reallocate it easily at boot and free up the unused flattened
structure after expansion. Version 16 introduces a new more
"compact" format for the tree itself that is however not backward
compatible. You should always generate a structure of the highest
version defined at the time of your implementation. Currently
that is version 16, unless you explicitely aim at being backward
compatible.
- last_comp_version
Last compatible version. This indicates down to what version of
the DT block you are backward compatible. For example, version 2
is backward compatible with version 1 (that is, a kernel build
for version 1 will be able to boot with a version 2 format). You
should put a 1 in this field if you generate a device tree of
version 1 to 3, or 0x10 if you generate a tree of version 0x10
using the new unit name format.
- boot_cpuid_phys
This field only exist on version 2 headers. It indicate which
physical CPU ID is calling the kernel entry point. This is used,
among others, by kexec. If you are on an SMP system, this value
should match the content of the "reg" property of the CPU node in
the device-tree corresponding to the CPU calling the kernel entry
point (see further chapters for more informations on the required
device-tree contents)
So the typical layout of a DT block (though the various parts don't
need to be in that order) looks like this (addresses go from top to
bottom):
------------------------------
r3 -> | struct boot_param_header |
------------------------------
| (alignment gap) (*) |
------------------------------
| memory reserve map |
------------------------------
| (alignment gap) |
------------------------------
| |
| device-tree structure |
| |
------------------------------
| (alignment gap) |
------------------------------
| |
| device-tree strings |
| |
-----> ------------------------------
|
|
--- (r3 + totalsize)
(*) The alignment gaps are not necessarily present; their presence
and size are dependent on the various alignment requirements of
the individual data blocks.
2) Device tree generalities
---------------------------
This device-tree itself is separated in two different blocks, a
structure block and a strings block. Both need to be aligned to a 4
byte boundary.
First, let's quickly describe the device-tree concept before detailing
the storage format. This chapter does _not_ describe the detail of the
required types of nodes & properties for the kernel, this is done
later in chapter III.
The device-tree layout is strongly inherited from the definition of
the Open Firmware IEEE 1275 device-tree. It's basically a tree of
nodes, each node having two or more named properties. A property can
have a value or not.
It is a tree, so each node has one and only one parent except for the
root node who has no parent.
A node has 2 names. The actual node name is generally contained in a
property of type "name" in the node property list whose value is a
zero terminated string and is mandatory for version 1 to 3 of the
format definition (as it is in Open Firmware). Version 0x10 makes it
optional as it can generate it from the unit name defined below.
There is also a "unit name" that is used to differenciate nodes with
the same name at the same level, it is usually made of the node
name's, the "@" sign, and a "unit address", which definition is
specific to the bus type the node sits on.
The unit name doesn't exist as a property per-se but is included in
the device-tree structure. It is typically used to represent "path" in
the device-tree. More details about the actual format of these will be
below.
The kernel powerpc generic code does not make any formal use of the
unit address (though some board support code may do) so the only real
requirement here for the unit address is to ensure uniqueness of
the node unit name at a given level of the tree. Nodes with no notion
of address and no possible sibling of the same name (like /memory or
/cpus) may omit the unit address in the context of this specification,
or use the "@0" default unit address. The unit name is used to define
a node "full path", which is the concatenation of all parent node
unit names separated with "/".
The root node doesn't have a defined name, and isn't required to have
a name property either if you are using version 3 or earlier of the
format. It also has no unit address (no @ symbol followed by a unit
address). The root node unit name is thus an empty string. The full
path to the root node is "/".
Every node which actually represents an actual device (that is, a node
which isn't only a virtual "container" for more nodes, like "/cpus"
is) is also required to have a "device_type" property indicating the
type of node .
Finally, every node that can be referenced from a property in another
node is required to have a "linux,phandle" property. Real open
firmware implementations provide a unique "phandle" value for every
node that the "prom_init()" trampoline code turns into
"linux,phandle" properties. However, this is made optional if the
flattened device tree is used directly. An example of a node
referencing another node via "phandle" is when laying out the
interrupt tree which will be described in a further version of this
document.
This "linux, phandle" property is a 32 bit value that uniquely
identifies a node. You are free to use whatever values or system of
values, internal pointers, or whatever to generate these, the only
requirement is that every node for which you provide that property has
a unique value for it.
Here is an example of a simple device-tree. In this example, an "o"
designates a node followed by the node unit name. Properties are
presented with their name followed by their content. "content"
represents an ASCII string (zero terminated) value, while <content>
represents a 32 bit hexadecimal value. The various nodes in this
example will be discussed in a later chapter. At this point, it is
only meant to give you a idea of what a device-tree looks like. I have
purposefully kept the "name" and "linux,phandle" properties which
aren't necessary in order to give you a better idea of what the tree
looks like in practice.
/ o device-tree
|- name = "device-tree"
|- model = "MyBoardName"
|- compatible = "MyBoardFamilyName"
|- #address-cells = <2>
|- #size-cells = <2>
|- linux,phandle = <0>
|
o cpus
| | - name = "cpus"
| | - linux,phandle = <1>
| | - #address-cells = <1>
| | - #size-cells = <0>
| |
| o PowerPC,970 at 0
| |- name = "PowerPC,970"
| |- device_type = "cpu"
| |- reg = <0>
| |- clock-frequency = <5f5e1000>
| |- linux,boot-cpu
| |- linux,phandle = <2>
|
o memory at 0
| |- name = "memory"
| |- device_type = "memory"
| |- reg = <00000000 00000000 00000000 20000000>
| |- linux,phandle = <3>
|
o chosen
|- name = "chosen"
|- bootargs = "root=/dev/sda2"
|- linux,platform = <00000600>
|- linux,phandle = <4>
This tree is almost a minimal tree. It pretty much contains the
minimal set of required nodes and properties to boot a linux kernel;
that is, some basic model informations at the root, the CPUs, and the
physical memory layout. It also includes misc information passed
through /chosen, like in this example, the platform type (mandatory)
and the kernel command line arguments (optional).
The /cpus/PowerPC,970 at 0/linux,boot-cpu property is an example of a
property without a value. All other properties have a value. The
significance of the #address-cells and #size-cells properties will be
explained in chapter IV which defines precisely the required nodes and
properties and their content.
3) Device tree "structure" block
The structure of the device tree is a linearized tree structure. The
"OF_DT_BEGIN_NODE" token starts a new node, and the "OF_DT_END_NODE"
ends that node definition. Child nodes are simply defined before
"OF_DT_END_NODE" (that is nodes within the node). A 'token' is a 32
bit value. The tree has to be "finished" with a OF_DT_END token
Here's the basic structure of a single node:
* token OF_DT_BEGIN_NODE (that is 0x00000001)
* for version 1 to 3, this is the node full path as a zero
terminated string, starting with "/". For version 16 and later,
this is the node unit name only (or an empty string for the
root node)
* [align gap to next 4 bytes boundary]
* for each property:
* token OF_DT_PROP (that is 0x00000003)
* 32 bit value of property value size in bytes (or 0 of no
* value)
* 32 bit value of offset in string block of property name
* property value data if any
* [align gap to next 4 bytes boundary]
* [child nodes if any]
* token OF_DT_END_NODE (that is 0x00000002)
So the node content can be summmarised as a start token, a full path,
a list of properties, a list of child node and an end token. Every
child node is a full node structure itself as defined above.
4) Device tree 'strings" block
In order to save space, property names, which are generally redundant,
are stored separately in the "strings" block. This block is simply the
whole bunch of zero terminated strings for all property names
concatenated together. The device-tree property definitions in the
structure block will contain offset values from the beginning of the
strings block.
III - Required content of the device tree
=========================================
WARNING: All "linux,*" properties defined in this document apply only
to a flattened device-tree. If your platform uses a real
implementation of Open Firmware or an implementation compatible with
the Open Firmware client interface, those properties will be created
by the trampoline code in the kernel's prom_init() file. For example,
that's where you'll have to add code to detect your board model and
set the platform number. However, when using the flatenned device-tree
entry point, there is no prom_init() pass, and thus you have to
provide those properties yourself.
1) Note about cells and address representation
----------------------------------------------
The general rule is documented in the various Open Firmware
documentations. If you chose to describe a bus with the device-tree
and there exist an OF bus binding, then you should follow the
specification. However, the kernel does not require every single
device or bus to be described by the device tree.
In general, the format of an address for a device is defined by the
parent bus type, based on the #address-cells and #size-cells
property. In the absence of such a property, the parent's parent
values are used, etc... The kernel requires the root node to have
those properties defining addresses format for devices directly mapped
on the processor bus.
Those 2 properties define 'cells' for representing an address and a
size. A "cell" is a 32 bit number. For example, if both contain 2
like the example tree given above, then an address and a size are both
composed of 2 cells, and each is a 64 bit number (cells are
concatenated and expected to be in big endian format). Another example
is the way Apple firmware defines them, with 2 cells for an address
and one cell for a size. Most 32-bit implementations should define
#address-cells and #size-cells to 1, which represents a 32-bit value.
Some 32-bit processors allow for physical addresses greater than 32
bits; these processors should define #address-cells as 2.
"reg" properties are always a tuple of the type "address size" where
the number of cells of address and size is specified by the bus
#address-cells and #size-cells. When a bus supports various address
spaces and other flags relative to a given address allocation (like
prefetchable, etc...) those flags are usually added to the top level
bits of the physical address. For example, a PCI physical address is
made of 3 cells, the bottom two containing the actual address itself
while the top cell contains address space indication, flags, and pci
bus & device numbers.
For busses that support dynamic allocation, it's the accepted practice
to then not provide the address in "reg" (keep it 0) though while
providing a flag indicating the address is dynamically allocated, and
then, to provide a separate "assigned-addresses" property that
contains the fully allocated addresses. See the PCI OF bindings for
details.
In general, a simple bus with no address space bits and no dynamic
allocation is preferred if it reflects your hardware, as the existing
kernel address parsing functions will work out of the box. If you
define a bus type with a more complex address format, including things
like address space bits, you'll have to add a bus translator to the
prom_parse.c file of the recent kernels for your bus type.
The "reg" property only defines addresses and sizes (if #size-cells
is
non-0) within a given bus. In order to translate addresses upward
(that is into parent bus addresses, and possibly into cpu physical
addresses), all busses must contain a "ranges" property. If the
"ranges" property is missing at a given level, it's assumed that
translation isn't possible. The format of the "ranges" proprety for a
bus is a list of:
bus address, parent bus address, size
"bus address" is in the format of the bus this bus node is defining,
that is, for a PCI bridge, it would be a PCI address. Thus, (bus
address, size) defines a range of addresses for child devices. "parent
bus address" is in the format of the parent bus of this bus. For
example, for a PCI host controller, that would be a CPU address. For a
PCI<->ISA bridge, that would be a PCI address. It defines the base
address in the parent bus where the beginning of that range is mapped.
For a new 64 bit powerpc board, I recommend either the 2/2 format or
Apple's 2/1 format which is slightly more compact since sizes usually
fit in a single 32 bit word. New 32 bit powerpc boards should use a
1/1 format, unless the processor supports physical addresses greater
than 32-bits, in which case a 2/1 format is recommended.
2) Note about "compatible" properties
-------------------------------------
These properties are optional, but recommended in devices and the root
node. The format of a "compatible" property is a list of concatenated
zero terminated strings. They allow a device to express its
compatibility with a family of similar devices, in some cases,
allowing a single driver to match against several devices regardless
of their actual names.
3) Note about "name" properties
-------------------------------
While earlier users of Open Firmware like OldWorld macintoshes tended
to use the actual device name for the "name" property, it's nowadays
considered a good practice to use a name that is closer to the device
class (often equal to device_type). For example, nowadays, ethernet
controllers are named "ethernet", an additional "model" property
defining precisely the chip type/model, and "compatible" property
defining the family in case a single driver can driver more than one
of these chips. However, the kernel doesn't generally put any
restriction on the "name" property; it is simply considered good
practice to follow the standard and its evolutions as closely as
possible.
Note also that the new format version 16 makes the "name" property
optional. If it's absent for a node, then the node's unit name is then
used to reconstruct the name. That is, the part of the unit name
before the "@" sign is used (or the entire unit name if no "@" sign
is present).
4) Note about node and property names and character set
-------------------------------------------------------
While open firmware provides more flexibe usage of 8859-1, this
specification enforces more strict rules. Nodes and properties should
be comprised only of ASCII characters 'a' to 'z', '0' to
'9', ',', '.', '_', '+', '#', '?', and '-'. Node names additionally
allow uppercase characters 'A' to 'Z' (property names should be
lowercase. The fact that vendors like Apple don't respect this rule is
irrelevant here). Additionally, node and property names should always
begin with a character in the range 'a' to 'z' (or 'A' to 'Z' for node
names).
The maximum number of characters for both nodes and property names
is 31. In the case of node names, this is only the leftmost part of
a unit name (the pure "name" property), it doesn't include the unit
address which can extend beyond that limit.
5) Required nodes and properties
--------------------------------
These are all that are currently required. However, it is strongly
recommended that you expose PCI host bridges as documented in the
PCI binding to open firmware, and your interrupt tree as documented
in OF interrupt tree specification.
a) The root node
The root node requires some properties to be present:
- model : this is your board name/model
- #address-cells : address representation for "root" devices
- #size-cells: the size representation for "root" devices
Additionally, some recommended properties are:
- compatible : the board "family" generally finds its way here,
for example, if you have 2 board models with a similar layout,
that typically get driven by the same platform code in the
kernel, you would use a different "model" property but put a
value in "compatible". The kernel doesn't directly use that
value (see /chosen/linux,platform for how the kernel choses a
platform type) but it is generally useful.
The root node is also generally where you add additional properties
specific to your board like the serial number if any, that sort of
thing. it is recommended that if you add any "custom" property whose
name may clash with standard defined ones, you prefix them with your
vendor name and a comma.
b) The /cpus node
This node is the parent of all individual CPU nodes. It doesn't
have any specific requirements, though it's generally good practice
to have at least:
#address-cells = <00000001>
#size-cells = <00000000>
This defines that the "address" for a CPU is a single cell, and has
no meaningful size. This is not necessary but the kernel will assume
that format when reading the "reg" properties of a CPU node, see
below
c) The /cpus/* nodes
So under /cpus, you are supposed to create a node for every CPU on
the machine. There is no specific restriction on the name of the
CPU, though It's common practice to call it PowerPC,<name>. For
example, Apple uses PowerPC,G5 while IBM uses PowerPC,970FX.
Required properties:
- device_type : has to be "cpu"
- reg : This is the physical cpu number, it's a single 32 bit cell
and is also used as-is as the unit number for constructing the
unit name in the full path. For example, with 2 CPUs, you would
have the full path:
/cpus/PowerPC,970FX at 0
/cpus/PowerPC,970FX at 1
(unit addresses do not require leading zeroes)
- d-cache-line-size : one cell, L1 data cache line size in bytes
- i-cache-line-size : one cell, L1 instruction cache line size in
bytes
- d-cache-size : one cell, size of L1 data cache in bytes
- i-cache-size : one cell, size of L1 instruction cache in bytes
- linux, boot-cpu : Should be defined if this cpu is the boot cpu.
Recommended properties:
- timebase-frequency : a cell indicating the frequency of the
timebase in Hz. This is not directly used by the generic code,
but you are welcome to copy/paste the pSeries code for setting
the kernel timebase/decrementer calibration based on this
value.
- clock-frequency : a cell indicating the CPU core clock frequency
in Hz. A new property will be defined for 64 bit values, but if
your frequency is < 4Ghz, one cell is enough. Here as well as
for the above, the common code doesn't use that property, but
you are welcome to re-use the pSeries or Maple one. A future
kernel version might provide a common function for this.
You are welcome to add any property you find relevant to your board,
like some information about the mechanism used to soft-reset the
CPUs. For example, Apple puts the GPIO number for CPU soft reset
lines in there as a "soft-reset" property since they start secondary
CPUs by soft-resetting them.
d) the /memory node(s)
To define the physical memory layout of your board, you should
create one or more memory node(s). You can either create a single
node with all memory ranges in its reg property, or you can create
several nodes, as you wish. The unit address (@ part) used for the
full path is the address of the first range of memory defined by a
given node. If you use a single memory node, this will typically be
@0.
Required properties:
- device_type : has to be "memory"
- reg : This property contains all the physical memory ranges of
your board. It's a list of addresses/sizes concatenated
together, with the number of cells of each defined by the
#address-cells and #size-cells of the root node. For example,
with both of these properties beeing 2 like in the example given
earlier, a 970 based machine with 6Gb of RAM could typically
have a "reg" property here that looks like:
00000000 00000000 00000000 80000000
00000001 00000000 00000001 00000000
That is a range starting at 0 of 0x80000000 bytes and a range
starting at 0x100000000 and of 0x100000000 bytes. You can see
that there is no memory covering the IO hole between 2Gb and
4Gb. Some vendors prefer splitting those ranges into smaller
segments, but the kernel doesn't care.
e) The /chosen node
This node is a bit "special". Normally, that's where open firmware
puts some variable environment information, like the arguments, or
phandle pointers to nodes like the main interrupt controller, or the
default input/output devices.
This specification makes a few of these mandatory, but also defines
some linux-specific properties that would be normally constructed by
the prom_init() trampoline when booting with an OF client interface,
but that you have to provide yourself when using the flattened format.
Required properties:
- linux,platform : This is your platform number as assigned by the
architecture maintainers
Recommended properties:
- bootargs : This zero-terminated string is passed as the kernel
command line
- linux,stdout-path : This is the full path to your standard
console device if any. Typically, if you have serial devices on
your board, you may want to put the full path to the one set as
the default console in the firmware here, for the kernel to pick
it up as it's own default console. If you look at the funciton
set_preferred_console() in arch/ppc64/kernel/setup.c, you'll see
that the kernel tries to find out the default console and has
knowledge of various types like 8250 serial ports. You may want
to extend this function to add your own.
- interrupt-controller : This is one cell containing a phandle
value that matches the "linux,phandle" property of your main
interrupt controller node. May be used for interrupt routing.
Note that u-boot creates and fills in the chosen node for platforms
that use it.
f) the /soc<SOCname> node
This node is used to represent a system-on-a-chip (SOC) and must be
present if the processor is a SOC. The top-level soc node contains
information that is global to all devices on the SOC. The node name
should contain a unit address for the SOC, which is the base address
of the memory-mapped register set for the SOC. The name of an soc
node should start with "soc", and the remainder of the name should
represent the part number for the soc. For example, the MPC8540's
soc node would be called "soc8540".
Required properties:
- device_type : Should be "soc"
- ranges : Should be defined as specified in 1) to describe the
translation of SOC addresses for memory mapped SOC registers.
Recommended properties:
- reg : This property defines the address and size of the
memory-mapped registers that are used for the SOC node itself.
It does not include the child device registers - these will be
defined inside each child node. The address specified in the
"reg" property should match the unit address of the SOC node.
- #address-cells : Address representation for "soc" devices. The
format of this field may vary depending on whether or not the
device registers are memory mapped. For memory mapped
registers, this field represents the number of cells needed to
represent the address of the registers. For SOCs that do not
use MMIO, a special address format should be defined that
contains enough cells to represent the required information.
See 1) above for more details on defining #address-cells.
- #size-cells : Size representation for "soc" devices
- #interrupt-cells : Defines the width of cells used to represent
interrupts. Typically this value is <2>, which includes a
32-bit number that represents the interrupt number, and a
32-bit number that represents the interrupt sense and level.
This field is only needed if the SOC contains an interrupt
controller.
The SOC node may contain child nodes for each SOC device that the
platform uses. Nodes should not be created for devices which exist
on the SOC but are not used by a particular platform. See chapter VI
for more information on how to specify devices that are part of an
SOC.
Example SOC node for the MPC8540:
soc8540@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
device_type = "soc";
ranges = <00000000 e0000000 00100000>
reg = <e0000000 00003000>;
}
IV - "dtc", the device tree compiler
====================================
dtc source code can be found at
<http://ozlabs.org/~dgibson/dtc/dtc.tar.gz>
WARNING: This version is still in early development stage; the
resulting device-tree "blobs" have not yet been validated with the
kernel. The current generated bloc lacks a useful reserve map (it will
be fixed to generate an empty one, it's up to the bootloader to fill
it up) among others. The error handling needs work, bugs are lurking,
etc...
dtc basically takes a device-tree in a given format and outputs a
device-tree in another format. The currently supported formats are:
Input formats:
-------------
- "dtb": "blob" format, that is a flattened device-tree block
with
header all in a binary blob.
- "dts": "source" format. This is a text file containing a
"source" for a device-tree. The format is defined later in this
chapter.
- "fs" format. This is a representation equivalent to the
output of /proc/device-tree, that is nodes are directories and
properties are files
Output formats:
---------------
- "dtb": "blob" format
- "dts": "source" format
- "asm": assembly language file. This is a file that can be
sourced by gas to generate a device-tree "blob". That file can
then simply be added to your Makefile. Additionally, the
assembly file exports some symbols that can be use
The syntax of the dtc tool is
dtc [-I <input-format>] [-O <output-format>]
[-o output-filename] [-V output_version] input_filename
The "output_version" defines what versio of the "blob" format will be
generated. Supported versions are 1,2,3 and 16. The default is
currently version 3 but that may change in the future to version 16.
Additionally, dtc performs various sanity checks on the tree, like the
uniqueness of linux,phandle properties, validity of strings, etc...
The format of the .dts "source" file is "C" like, supports C and C++
style commments.
/ {
}
The above is the "device-tree" definition. It's the only statement
supported currently at the toplevel.
/ {
property1 = "string_value"; /* define a property containing a 0
* terminated string
*/
property2 = <1234abcd>; /* define a property containing a
* numerical 32 bits value (hexadecimal)
*/
property3 = <12345678 12345678 deadbeef>;
/* define a property containing 3
* numerical 32 bits values (cells) in
* hexadecimal
*/
property4 = [0a 0b 0c 0d de ea ad be ef];
/* define a property whose content is
* an arbitrary array of bytes
*/
childnode at addresss { /* define a child node named "childnode"
* whose unit name is "childnode at
* address"
*/
childprop = "hello\n"; /* define a property "childprop" of
* childnode (in this case, a string)
*/
};
};
Nodes can contain other nodes etc... thus defining the hierarchical
structure of the tree.
Strings support common escape sequences from C: "\n", "\t", "\r",
"\(octal value)", "\x(hex value)".
It is also suggested that you pipe your source file through cpp (gcc
preprocessor) so you can use #include's, #define for constants, etc...
Finally, various options are planned but not yet implemented, like
automatic generation of phandles, labels (exported to the asm file so
you can point to a property content and change it easily from whatever
you link the device-tree with), label or path instead of numeric value
in some cells to "point" to a node (replaced by a phandle at compile
time), export of reserve map address to the asm file, ability to
specify reserve map content at compile time, etc...
We may provide a .h include file with common definitions of that
proves useful for some properties (like building PCI properties or
interrupt maps) though it may be better to add a notion of struct
definitions to the compiler...
V - Recommendations for a bootloader
====================================
Here are some various ideas/recommendations that have been proposed
while all this has been defined and implemented.
- The bootloader may want to be able to use the device-tree itself
and may want to manipulate it (to add/edit some properties,
like physical memory size or kernel arguments). At this point, 2
choices can be made. Either the bootloader works directly on the
flattened format, or the bootloader has its own internal tree
representation with pointers (similar to the kernel one) and
re-flattens the tree when booting the kernel. The former is a bit
more difficult to edit/modify, the later requires probably a bit
more code to handle the tree structure. Note that the structure
format has been designed so it's relatively easy to "insert"
properties or nodes or delete them by just memmoving things
around. It contains no internal offsets or pointers for this
purpose.
- An example of code for iterating nodes & retreiving properties
directly from the flattened tree format can be found in the kernel
file arch/ppc64/kernel/prom.c, look at scan_flat_dt() function,
it's usage in early_init_devtree(), and the corresponding various
early_init_dt_scan_*() callbacks. That code can be re-used in a
GPL bootloader, and as the author of that code, I would be happy
do discuss possible free licencing to any vendor who wishes to
integrate all or part of this code into a non-GPL bootloader.
VI - System-on-a-chip devices and nodes
=======================================
Many companies are now starting to develop system-on-a-chip
processors, where the processor core (cpu) and many peripheral devices
exist on a single piece of silicon. For these SOCs, an SOC node
should be used that defines child nodes for the devices that make
up the SOC. While platforms are not required to use this model in
order to boot the kernel, it is highly encouraged that all SOC
implementations define as complete a flat-device-tree as possible to
describe the devices on the SOC. This will allow for the
genericization of much of the kernel code.
1) Defining child nodes of an SOC
---------------------------------
Each device that is part of an SOC may have its own node entry inside
the SOC node. For each device that is included in the SOC, the unit
address property represents the address offset for this device's
memory-mapped registers in the parent's address space. The parent's
address space is defined by the "ranges" property in the top-level soc
node. The "reg" property for each node that exists directly under the
SOC node should contain the address mapping from the child address space
to the parent SOC address space and the size of the device's
memory-mapped register file.
For many devices that may exist inside an SOC, there are predefined
specifications for the format of the device tree node. All SOC child
nodes should follow these specifications, except where noted in this
document.
See appendix A for an example partial SOC node definition for the
MPC8540.
2) Specifying interrupt information for SOC devices
---------------------------------------------------
Each device that is part of an SOC and which generates interrupts
should have the following properties:
- interrupt-parent : contains the phandle of the interrupt
controller which handles interrupts for this device
- interrupts : a list of tuples representing the interrupt
number and the interrupt sense and level for each interupt
for this device.
This information is used by the kernel to build the interrupt table
for the interrupt controllers in the system.
Sense and level information should be encoded as follows:
Devices connected to openPIC-compatible controllers should encode
sense and polarity as follows:
0 = high to low edge sensitive type enabled
1 = active low level sensitive type enabled
2 = low to high edge sensitive type enabled
3 = active high level sensitive type enabled
ISA PIC interrupt controllers should adhere to the ISA PIC
encodings listed below:
0 = active low level sensitive type enabled
1 = active high level sensitive type enabled
2 = high to low edge sensitive type enabled
3 = low to high edge sensitive type enabled
3) Representing devices without a current OF specification
----------------------------------------------------------
Currently, there are many devices on SOCs that do not have a standard
representation pre-defined as part of the open firmware
specifications, mainly because the boards that contain these SOCs are
not currently booted using open firmware. This section contains
descriptions for the SOC devices for which new nodes have been
defined; this list will expand as more and more SOC-containing
platforms are moved over to use the flattened-device-tree model.
a) MDIO IO device
The MDIO is a bus to which the PHY devices are connected. For each
device that exists on this bus, a child node should be created. See
the definition of the PHY node below for an example of how to define
a PHY.
Required properties:
- reg : Offset and length of the register set for the device
Example:
mdio@24520 {
reg = <24520 20>;
ethernet-phy@0 {
......
};
};
b) Gianfar-compatible ethernet nodes
Required properties:
- device_type : Should be "network"
- model : Model of the device. Can be "TSEC" or "FEC"
- compatible : Should be "gianfar"
- reg : Offset and length of the register set for the device
- address : List of bytes representing the ethernet address of
this controller
- interrupts : <a b> where a is the interrupt number and b is a
field that represents an encoding of the sense and level
information for the interrupt. This should be encoded based on
the information in section 2) depending on the type of interrupt
controller you have.
- interrupt-parent : the phandle for the interrupt controller that
services interrupts for this device.
- phy-handle : The phandle for the PHY connected to this ethernet
controller.
Example:
ethernet@24000 {
#size-cells = <0>;
device_type = "network";
model = "TSEC";
compatible = "gianfar";
reg = <24000 1000>;
address = [ 00 E0 0C 00 73 00 ];
interrupts = <d 3 e 3 12 3>;
interrupt-parent = <40000>;
phy-handle = <2452000>
};
c) PHY nodes
Required properties:
- device_type : Should be "ethernet-phy"
- interrupts : <a b> where a is the interrupt number and b is a
field that represents an encoding of the sense and level
information for the interrupt. This should be encoded based on
the information in section 2) depending on the type of interrupt
controller you have.
- interrupt-parent : the phandle for the interrupt controller that
services interrupts for this device.
- reg : The ID number for the phy, usually a small integer
- linux,phandle : phandle for this node; likely referenced by an
ethernet controller node.
Example:
ethernet-phy@0 {
linux,phandle = <2452000>
interrupt-parent = <40000>;
interrupts = <35 1>;
reg = <0>;
device_type = "ethernet-phy";
};
d) Interrupt controllers
Some SOC devices contain interrupt controllers that are different
from the standard Open PIC specification. The SOC device nodes for
these types of controllers should be specified just like a standard
OpenPIC controller. Sense and level information should be encoded
as specified in section 2) of this chapter for each device that
specifies an interrupt.
Example :
pic@40000 {
linux,phandle = <40000>;
clock-frequency = <0>;
interrupt-controller;
#address-cells = <0>;
reg = <40000 40000>;
built-in;
compatible = "chrp,open-pic";
device_type = "open-pic";
big-endian;
};
e) I2C
Required properties :
- device_type : Should be "i2c"
- reg : Offset and length of the register set for the device
Recommended properties :
- compatible : Should be "fsl-i2c" for parts compatible with
Freescale I2C specifications.
- interrupts : <a b> where a is the interrupt number and b is a
field that represents an encoding of the sense and level
information for the interrupt. This should be encoded based on
the information in section 2) depending on the type of interrupt
controller you have.
- interrupt-parent : the phandle for the interrupt controller that
services interrupts for this device.
- dfsrr : boolean; if defined, indicates that this I2C device has
a digital filter sampling rate register
- fsl5200-clocking : boolean; if defined, indicated that this device
uses the FSL 5200 clocking mechanism.
Example :
i2c@3000 {
interrupt-parent = <40000>;
interrupts = <1b 3>;
reg = <3000 18>;
device_type = "i2c";
compatible = "fsl-i2c";
dfsrr;
};
More devices will be defined as this spec matures.
Appendix A - Sample SOC node for MPC8540
========================================
Note that the #address-cells and #size-cells for the SoC node
in this example have been explicitly listed; these are likely
not necessary as they are usually the same as the root node.
soc8540@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
device_type = "soc";
ranges = <00000000 e0000000 00100000>
reg = <e0000000 00003000>;
mdio@24520 {
reg = <24520 20>;
ethernet-phy@0 {
linux,phandle = <2452000>
interrupt-parent = <40000>;
interrupts = <35 1>;
reg = <0>;
device_type = "ethernet-phy";
};
ethernet-phy@1 {
linux,phandle = <2452001>
interrupt-parent = <40000>;
interrupts = <35 1>;
reg = <1>;
device_type = "ethernet-phy";
};
ethernet-phy@3 {
linux,phandle = <2452002>
interrupt-parent = <40000>;
interrupts = <35 1>;
reg = <3>;
device_type = "ethernet-phy";
};
};
ethernet@24000 {
#size-cells = <0>;
device_type = "network";
model = "TSEC";
compatible = "gianfar";
reg = <24000 1000>;
address = [ 00 E0 0C 00 73 00 ];
interrupts = <d 3 e 3 12 3>;
interrupt-parent = <40000>;
phy-handle = <2452000>;
};
ethernet@25000 {
#address-cells = <1>;
#size-cells = <0>;
device_type = "network";
model = "TSEC";
compatible = "gianfar";
reg = <25000 1000>;
address = [ 00 E0 0C 00 73 01 ];
interrupts = <13 3 14 3 18 3>;
interrupt-parent = <40000>;
phy-handle = <2452001>;
};
ethernet@26000 {
#address-cells = <1>;
#size-cells = <0>;
device_type = "network";
model = "FEC";
compatible = "gianfar";
reg = <26000 1000>;
address = [ 00 E0 0C 00 73 02 ];
interrupts = <19 3>;
interrupt-parent = <40000>;
phy-handle = <2452002>;
};
serial@4500 {
device_type = "serial";
compatible = "ns16550";
reg = <4500 100>;
clock-frequency = <0>;
interrupts = <1a 3>;
interrupt-parent = <40000>;
};
pic@40000 {
linux,phandle = <40000>;
clock-frequency = <0>;
interrupt-controller;
#address-cells = <0>;
reg = <40000 40000>;
built-in;
compatible = "chrp,open-pic";
device_type = "open-pic";
big-endian;
};
i2c@3000 {
interrupt-parent = <40000>;
interrupts = <1b 3>;
reg = <3000 18>;
device_type = "i2c";
compatible = "fsl-i2c";
dfsrr;
};
};
^ permalink raw reply
* Re: Video Card to Lite5200
From: Alessandro Rubini @ 2005-12-05 20:39 UTC (permalink / raw)
To: wd; +Cc: linuxppc-embedded
In-Reply-To: <20051205203515.51D4C353F5E@atlas.denx.de>
> Note that the 5200 code in the kernel is work in progress. I do not
> cleaim that it does work in any way. If you want stable code use our
> 2.4.25 kernel instead.
FWIW, I have your 2.6.14 happily running on the lite5200, with PCI,
IDE (no DMA though) and flash.
I can publish the patches, if anyone is interested. Until now I didn't,
as Sylvain's work is considered the official one (but it didn't have
IDE last time I checked -- and I don't have bitkeeper to pull it).
/alessandro
^ permalink raw reply
* Re: Video Card to Lite5200
From: Wolfgang Denk @ 2005-12-05 20:35 UTC (permalink / raw)
To: Alan Carvalho; +Cc: linuxppc-embedded
In-Reply-To: <dc70db7d0512051130s498f7d5fk42a0f4886c006efd@mail.gmail.com>
Dear Alan,
in message <dc70db7d0512051130s498f7d5fk42a0f4886c006efd@mail.gmail.com> you wrote:
>
> I am just looking for a cheaper video card to use with Lite5200 board.
> CoralP is very expansive, then I will use ATI Rage Mobility.
Make sure that you don't need to run any (x86) BIOS code on your card
to initialize it. This is the main issue with most graphics cards.
> Well, my video card is not ATI Rage Mobility M1 EVA, it has not 723
> regulator, it use MTD3302 as regulator, do you know if I need change
> something on the Lite5200's PCI slot to it work with this video card?
If your card is a true 3.3V PCI card it should be at least possible
to attach and test it. Chances are that it does not work (at least
not without some amount of work).
> My Lite5200 is Version 2.0, and Freescale connected some wire (small cables)
> to PCI slot, maybe to fix some PCI problems.
You probably want to ask FS about this.
> I am using linux kernel 2.6.14, downloaded from denx's web site. Linux is
Note that the 5200 code in the kernel is work in progress. I do not
cleaim that it does work in any way. If you want stable code use our
2.4.25 kernel instead.
> running fine in this board, but until now I am using only serial console.
> Now I want use a video card with it.
Well, if your time is worth anything you might find out that the
CoralP is the cheaper solution - or using a graphics controller that
can be attached directly to the bus.
Best regards,
Wolfgang Denk
--
Software Engineering: Embedded and Realtime Systems, Embedded Linux
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de
In general, they do what you want, unless you want consistency.
- Larry Wall in the perl man page
^ permalink raw reply
* Re: Fw: Anyone using CodeWarrior USB TAP?
From: York Sun @ 2005-12-05 19:37 UTC (permalink / raw)
To: Kim Phillips; +Cc: linuxppc-embedded
In-Reply-To: <20051205132239.4a67e575.kim.phillips@freescale.com>
Addison,
I don't know if you can receive this reply since I am not in the mailing
list.
The answer is that the USB TAP can work under Linux. You will need
CodeWarrior Linux version. The current version is 2.6. Please contact
the sales of channels where you got your board.
No specific driver is required for Linux. Just kindly remind you to
check the writing privilege of /proc/bus/usb/001/* if you not the root
user.
York
On Mon, 2005-12-05 at 13:22 -0600, Kim Phillips wrote:
> York, know anything about this? If you're subscribed, could you answer directly to the list?
>
> Kim
>
> Begin forwarded message:
>
> Date: Mon, 5 Dec 2005 17:05:39 +0000
> From: Addison Baldwin <addison.baldwin@gmail.com>
> To: linuxppc-embedded@ozlabs.org
> Subject: Anyone using CodeWarrior USB TAP?
>
>
> Hi
>
> I received a MPC8272ADS board from Freescale, and I'm trying to use a
> CodeWarrior USB TAB that has been provided with the board. It seems that
> such a device only works under Windows, as I didn't find a driver to make it
> works under Linux.
>
> I would like to know if anyone have got the CodeWarrior USB working under
> Linux.
>
> Thanks,
> Addison
>
>
>
--
York Sun
This email, and any associated attachments have been classified as:
[x] Freescale Semiconductor General Business
[ ] Freescale Semiconductor Internal Use Only
[ ] Freescale Semiconductor Confidential Proprietary
^ permalink raw reply
* Video Card to Lite5200
From: Alan Carvalho @ 2005-12-05 19:30 UTC (permalink / raw)
To: Wolfgang Denk; +Cc: linuxppc-embedded
[-- Attachment #1: Type: text/plain, Size: 1110 bytes --]
Hi Denx,
I am just looking for a cheaper video card to use with Lite5200 board.
CoralP is very expansive, then I will use ATI Rage Mobility.
I see some reference to this board at:
http://ozlabs.org/pipermail/linuxppc-embedded/2004-July/014848.html
Here in Brazil I get an "ATI RAGE XL 8MB PCI" (ATI Mobility 8M TV PCI),
it is PCI v. 2.2 (support 3.3V and 5V).
But I found some tips here at ozlabs:
"Other possible problem is that i found with ATI Rage Mobility M1 EVA board
that it's 723 3.3V regulator needed as default +12V to operate."
Well, my video card is not ATI Rage Mobility M1 EVA, it has not 723
regulator, it use MTD3302 as regulator, do you know if I need change
something on the Lite5200's PCI slot to it work with this video card?
My Lite5200 is Version 2.0, and Freescale connected some wire (small cables)
to PCI slot, maybe to fix some PCI problems.
I am using linux kernel 2.6.14, downloaded from denx's web site. Linux is
running fine in this board, but until now I am using only serial console.
Now I want use a video card with it.
Best regards,
Alan
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^ permalink raw reply
* [PATCH] Support 8xx based Silicon Turnkey XTc
From: Pantelis Antoniou @ 2005-12-05 19:15 UTC (permalink / raw)
To: Marcelo Tosatti, Dan Malek, Robert Applebaum, linuxppc-embedded,
Benjamin Herrenschmidt
Support of Silicon Turnkey's XTc.
---
commit fac9bbd80d8f8ab3c6af5a417f804dbf8537c700
tree 7863f94249651a26ca3eb29aed4c65c214968dda
parent e4f5c82a92c2a546a16af1614114eec19120e40a
author Pantelis Antoniou <pantelis.antoniou@gmail.com> Mon, 05 Dec 2005 21:13:56 +0200
committer Pantelis Antoniou <pantelis.antoniou@gmail.com> Mon, 05 Dec 2005 21:13:56 +0200
arch/ppc/Kconfig | 5
arch/ppc/configs/stxxtc_defconfig | 804 +++++++++++++++++++++++++++++++++++++
arch/ppc/platforms/Makefile | 1
arch/ppc/platforms/stxxtc.h | 285 +++++++++++++
arch/ppc/platforms/stxxtc_setup.c | 193 +++++++++
arch/ppc/syslib/m8xx_setup.c | 14 +
drivers/mtd/maps/Kconfig | 6
drivers/mtd/maps/Makefile | 1
drivers/mtd/maps/stxxtc_nor.c | 326 +++++++++++++++
drivers/mtd/nand/Kconfig | 8
drivers/mtd/nand/Makefile | 1
drivers/mtd/nand/stxxtc_nand.c | 277 +++++++++++++
include/asm-ppc/mpc8xx.h | 4
13 files changed, 1922 insertions(+), 3 deletions(-)
diff --git a/arch/ppc/Kconfig b/arch/ppc/Kconfig
--- a/arch/ppc/Kconfig
+++ b/arch/ppc/Kconfig
@@ -504,6 +504,11 @@ config WINCEPT
MPC821 PowerPC, introduced in 1998 and designed to be used in
thin-client machines. Say Y to support it directly.
+config STXXTC
+ bool "Silicon Turnkey eXpress XTc"
+ help
+ Select STXXTC if configuring for an Silicon Turnkey eXpress XTc
+
endchoice
choice
diff --git a/arch/ppc/configs/stxxtc_defconfig b/arch/ppc/configs/stxxtc_defconfig
new file mode 100644
--- /dev/null
+++ b/arch/ppc/configs/stxxtc_defconfig
@@ -0,0 +1,804 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.15-rc5
+# Mon Dec 5 19:57:09 2005
+#
+CONFIG_MMU=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_RWSEM_XCHGADD_ALGORITHM=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_PPC=y
+CONFIG_PPC32=y
+CONFIG_GENERIC_NVRAM=y
+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+CONFIG_ARCH_MAY_HAVE_PC_FDC=y
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_CLEAN_COMPILE=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+
+#
+# General setup
+#
+CONFIG_LOCALVERSION="-stxxtc"
+# CONFIG_LOCALVERSION_AUTO is not set
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_SYSCTL=y
+# CONFIG_AUDIT is not set
+# CONFIG_HOTPLUG is not set
+CONFIG_KOBJECT_UEVENT=y
+# CONFIG_IKCONFIG is not set
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_EMBEDDED=y
+CONFIG_KALLSYMS=y
+CONFIG_KALLSYMS_ALL=y
+CONFIG_KALLSYMS_EXTRA_PASS=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SHMEM=y
+CONFIG_CC_ALIGN_FUNCTIONS=0
+CONFIG_CC_ALIGN_LABELS=0
+CONFIG_CC_ALIGN_LOOPS=0
+CONFIG_CC_ALIGN_JUMPS=0
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+
+#
+# Loadable module support
+#
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+CONFIG_OBSOLETE_MODPARM=y
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+# CONFIG_KMOD is not set
+
+#
+# Block layer
+#
+# CONFIG_LBD is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+CONFIG_DEFAULT_AS=y
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="anticipatory"
+
+#
+# Processor
+#
+# CONFIG_6xx is not set
+# CONFIG_40x is not set
+# CONFIG_44x is not set
+# CONFIG_POWER3 is not set
+# CONFIG_POWER4 is not set
+CONFIG_8xx=y
+# CONFIG_E200 is not set
+# CONFIG_E500 is not set
+CONFIG_MATH_EMULATION=y
+# CONFIG_KEXEC is not set
+# CONFIG_CPU_FREQ is not set
+# CONFIG_WANT_EARLY_SERIAL is not set
+CONFIG_EMBEDDEDBOOT=y
+CONFIG_NOT_COHERENT_CACHE=y
+
+#
+# Platform options
+#
+# CONFIG_RPXLITE is not set
+# CONFIG_RPXCLASSIC is not set
+# CONFIG_BSEIP is not set
+# CONFIG_MPC8XXFADS is not set
+# CONFIG_MPC86XADS is not set
+# CONFIG_MPC885ADS is not set
+# CONFIG_TQM823L is not set
+# CONFIG_TQM850L is not set
+# CONFIG_TQM855L is not set
+# CONFIG_TQM860L is not set
+# CONFIG_FPS850L is not set
+# CONFIG_IVMS8 is not set
+# CONFIG_IVML24 is not set
+# CONFIG_HERMES_PRO is not set
+# CONFIG_IP860 is not set
+# CONFIG_LWMON is not set
+# CONFIG_PCU_E is not set
+# CONFIG_CCM is not set
+# CONFIG_LANTEC is not set
+# CONFIG_MBX is not set
+# CONFIG_WINCEPT is not set
+CONFIG_STXXTC=y
+CONFIG_CPM1=y
+# CONFIG_HIGHMEM is not set
+# CONFIG_HZ_100 is not set
+CONFIG_HZ_250=y
+# CONFIG_HZ_1000 is not set
+CONFIG_HZ=250
+CONFIG_PREEMPT_NONE=y
+# CONFIG_PREEMPT_VOLUNTARY is not set
+# CONFIG_PREEMPT is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_CMDLINE_BOOL is not set
+# CONFIG_PM is not set
+# CONFIG_SOFTWARE_SUSPEND is not set
+# CONFIG_SECCOMP is not set
+CONFIG_ISA_DMA_API=y
+
+#
+# Bus options
+#
+# CONFIG_PPC_I8259 is not set
+# CONFIG_PCI is not set
+# CONFIG_PCI_DOMAINS is not set
+# CONFIG_PCI_QSPAN is not set
+
+#
+# PCCARD (PCMCIA/CardBus) support
+#
+# CONFIG_PCCARD is not set
+
+#
+# Advanced setup
+#
+CONFIG_ADVANCED_OPTIONS=y
+CONFIG_HIGHMEM_START=0xfe000000
+# CONFIG_LOWMEM_SIZE_BOOL is not set
+CONFIG_LOWMEM_SIZE=0x30000000
+# CONFIG_KERNEL_START_BOOL is not set
+CONFIG_KERNEL_START=0xc0000000
+# CONFIG_TASK_SIZE_BOOL is not set
+CONFIG_TASK_SIZE=0x80000000
+CONFIG_CONSISTENT_START_BOOL=y
+CONFIG_CONSISTENT_START=0xe0000000
+# CONFIG_CONSISTENT_SIZE_BOOL is not set
+CONFIG_CONSISTENT_SIZE=0x00200000
+# CONFIG_BOOT_LOAD_BOOL is not set
+CONFIG_BOOT_LOAD=0x00400000
+# CONFIG_PIN_TLB is not set
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+# CONFIG_IP_PNP_DHCP is not set
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+CONFIG_SYN_COOKIES=y
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_BIC=y
+# CONFIG_IPV6 is not set
+# CONFIG_NETFILTER is not set
+
+#
+# DCCP Configuration (EXPERIMENTAL)
+#
+# CONFIG_IP_DCCP is not set
+
+#
+# SCTP Configuration (EXPERIMENTAL)
+#
+# CONFIG_IP_SCTP is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_IEEE80211 is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_FW_LOADER is not set
+# CONFIG_DEBUG_DRIVER is not set
+
+#
+# Connector - unified userspace <-> kernelspace linker
+#
+# CONFIG_CONNECTOR is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_CONCAT=y
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_GEN_PROBE=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_NOSWAP=y
+# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
+# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
+# CONFIG_MTD_CFI_GEOMETRY is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_OTP is not set
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_AMDSTD_RETRY=0
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PHYSMAP is not set
+# CONFIG_MTD_CFI_FLAGADM is not set
+# CONFIG_MTD_PLATRAM is not set
+CONFIG_MTD_STXXTC_NOR=y
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLKMTD is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+
+#
+# NAND Flash Device Drivers
+#
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_VERIFY_WRITE=y
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+CONFIG_MTD_NAND_STXXTC=y
+
+#
+# OneNAND Flash Device Drivers
+#
+# CONFIG_MTD_ONENAND is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Plug and Play support
+#
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=4096
+CONFIG_BLK_DEV_INITRD=y
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+
+#
+# ATA/ATAPI/MFM/RLL support
+#
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+
+#
+# Fusion MPT device support
+#
+# CONFIG_FUSION is not set
+
+#
+# IEEE 1394 (FireWire) support
+#
+
+#
+# I2O device support
+#
+
+#
+# Macintosh device drivers
+#
+# CONFIG_WINDFARM is not set
+
+#
+# Network device support
+#
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+
+#
+# PHY device support
+#
+# CONFIG_PHYLIB is not set
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_FEC_8XX is not set
+CONFIG_FS_ENET=y
+# CONFIG_FS_ENET_HAS_SCC is not set
+CONFIG_FS_ENET_HAS_FEC=y
+
+#
+# Ethernet (1000 Mbit)
+#
+
+#
+# Ethernet (10000 Mbit)
+#
+
+#
+# Token Ring devices
+#
+
+#
+# Wireless LAN (non-hamradio)
+#
+# CONFIG_NET_RADIO is not set
+
+#
+# Wan interfaces
+#
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_SHAPER is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# Telephony Support
+#
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+# CONFIG_INPUT is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_SERIAL_CPM=y
+CONFIG_SERIAL_CPM_CONSOLE=y
+# CONFIG_SERIAL_CPM_SCC1 is not set
+# CONFIG_SERIAL_CPM_SCC2 is not set
+# CONFIG_SERIAL_CPM_SCC3 is not set
+# CONFIG_SERIAL_CPM_SCC4 is not set
+CONFIG_SERIAL_CPM_SMC1=y
+# CONFIG_SERIAL_CPM_SMC2 is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+
+#
+# IPMI
+#
+# CONFIG_IPMI_HANDLER is not set
+
+#
+# Watchdog Cards
+#
+CONFIG_WATCHDOG=y
+# CONFIG_WATCHDOG_NOWAYOUT is not set
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+CONFIG_8xx_WDT=y
+# CONFIG_NVRAM is not set
+# CONFIG_GEN_RTC is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_AGP is not set
+# CONFIG_RAW_DRIVER is not set
+
+#
+# TPM devices
+#
+# CONFIG_TCG_TPM is not set
+# CONFIG_TELCLOCK is not set
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# Dallas's 1-wire bus
+#
+# CONFIG_W1 is not set
+
+#
+# Hardware Monitoring support
+#
+CONFIG_HWMON=y
+# CONFIG_HWMON_VID is not set
+# CONFIG_HWMON_DEBUG_CHIP is not set
+
+#
+# Misc devices
+#
+
+#
+# Multimedia Capabilities Port drivers
+#
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# Digital Video Broadcasting Devices
+#
+# CONFIG_DVB is not set
+
+#
+# Graphics support
+#
+# CONFIG_FB is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+# CONFIG_USB_ARCH_HAS_HCD is not set
+# CONFIG_USB_ARCH_HAS_OHCI is not set
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+
+#
+# USB Gadget Support
+#
+# CONFIG_USB_GADGET is not set
+
+#
+# MMC/SD Card support
+#
+# CONFIG_MMC is not set
+
+#
+# InfiniBand support
+#
+
+#
+# SN Devices
+#
+
+#
+# File systems
+#
+# CONFIG_EXT2_FS is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_JBD is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_INOTIFY=y
+# CONFIG_QUOTA is not set
+# CONFIG_DNOTIFY is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_RAMFS=y
+# CONFIG_RELAYFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+CONFIG_CRAMFS=y
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+
+#
+# Network File Systems
+#
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+# CONFIG_NFS_DIRECTIO is not set
+# CONFIG_NFSD is not set
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+# CONFIG_9P_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+# CONFIG_MSDOS_PARTITION is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+
+#
+# Native Language Support
+#
+# CONFIG_NLS is not set
+
+#
+# MPC8xx CPM Options
+#
+# CONFIG_SCC_ENET is not set
+# CONFIG_FEC_ENET is not set
+
+#
+# Generic MPC8xx Options
+#
+CONFIG_8xx_COPYBACK=y
+# CONFIG_8xx_CPU6 is not set
+CONFIG_NO_UCODE_PATCH=y
+# CONFIG_USB_SOF_UCODE_PATCH is not set
+# CONFIG_I2C_SPI_UCODE_PATCH is not set
+# CONFIG_I2C_SPI_SMC1_UCODE_PATCH is not set
+
+#
+# Library routines
+#
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+CONFIG_CRC32=y
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+# CONFIG_PROFILING is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_MAGIC_SYSRQ is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_DETECT_SOFTLOCKUP is not set
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_KOBJECT is not set
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_FS is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_XMON is not set
+# CONFIG_BDI_SWITCH is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+
+#
+# Cryptographic options
+#
+# CONFIG_CRYPTO is not set
+
+#
+# Hardware crypto devices
+#
diff --git a/arch/ppc/platforms/Makefile b/arch/ppc/platforms/Makefile
--- a/arch/ppc/platforms/Makefile
+++ b/arch/ppc/platforms/Makefile
@@ -45,6 +45,7 @@ obj-$(CONFIG_SBC82xx) += sbc82xx.o
obj-$(CONFIG_SPRUCE) += spruce.o
obj-$(CONFIG_LITE5200) += lite5200.o
obj-$(CONFIG_EV64360) += ev64360.o
+obj-$(CONFIG_STXXTC) += stxxtc_setup.o
ifeq ($(CONFIG_SMP),y)
obj-$(CONFIG_PPC_PMAC) += pmac_smp.o
diff --git a/arch/ppc/platforms/stxxtc.h b/arch/ppc/platforms/stxxtc.h
new file mode 100644
--- /dev/null
+++ b/arch/ppc/platforms/stxxtc.h
@@ -0,0 +1,285 @@
+/*
+ * A collection of structures, addresses, and values associated with
+ * the STXXTC systems.
+ *
+ * Copyright (c) 2005 Pantelis Antoniou <pantelis.antoniou@gmail.com>
+ * Dan Malek <dan@embeddedalley.com>
+ *
+ */
+#ifndef __MACH_STXXTC_DEFS
+#define __MACH_STXXTC_DEFS
+
+#include <linux/config.h>
+
+#ifndef __ASSEMBLY__
+
+#include <asm/ppcboot.h>
+
+#include <asm/8xx_immap.h>
+#include <asm/commproc.h>
+#include <asm/mpc8xx.h>
+#include <asm/delay.h>
+
+#endif
+
+#define IMAP_ADDR 0xFF000000 /* physical base address of IMMR area */
+#define IMAP_SIZE (64 * 1024) /* mapped size of IMMR area */
+
+/* We don't use the 8259.
+*/
+#define NR_8259_INTS 0
+
+#define NAND_SIZE 0x00010000
+#define NAND_BASE 0xF1000000
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ *
+ */
+#define PCMCIA_MEM_SIZE ( 64 << 20 )
+
+#define MAX_HWIFS 1 /* overwrite default in include/asm-ppc/ide.h */
+
+/*
+ * Definitions for IDE0 Interface
+ */
+#define IDE0_BASE_OFFSET 0
+#define IDE0_DATA_REG_OFFSET (PCMCIA_MEM_SIZE + 0x320)
+#define IDE0_ERROR_REG_OFFSET (2 * PCMCIA_MEM_SIZE + 0x320 + 1)
+#define IDE0_NSECTOR_REG_OFFSET (2 * PCMCIA_MEM_SIZE + 0x320 + 2)
+#define IDE0_SECTOR_REG_OFFSET (2 * PCMCIA_MEM_SIZE + 0x320 + 3)
+#define IDE0_LCYL_REG_OFFSET (2 * PCMCIA_MEM_SIZE + 0x320 + 4)
+#define IDE0_HCYL_REG_OFFSET (2 * PCMCIA_MEM_SIZE + 0x320 + 5)
+#define IDE0_SELECT_REG_OFFSET (2 * PCMCIA_MEM_SIZE + 0x320 + 6)
+#define IDE0_STATUS_REG_OFFSET (2 * PCMCIA_MEM_SIZE + 0x320 + 7)
+#define IDE0_CONTROL_REG_OFFSET 0x0106
+#define IDE0_IRQ_REG_OFFSET 0x000A /* not used */
+
+#define IDE0_INTERRUPT 13
+
+/* XXX FUCK!, for IDE disk set to 0, for normal PCMCIA set to 1 */
+/* XXX don't ask me why.. */
+#if 1
+/* define IO_BASE for PCMCIA */
+#define _IO_BASE 0x80000000
+#define _IO_BASE_SIZE (64<<10)
+#endif
+
+/***********************************************************************/
+
+/* shorthand for the ports data registers */
+#define PORTA (((volatile immap_t *)IMAP_ADDR)->im_ioport.iop_padat)
+#define PORTB (((volatile immap_t *)IMAP_ADDR)->im_cpm.cp_pbdat)
+#define PORTC (((volatile immap_t *)IMAP_ADDR)->im_ioport.iop_pcdat)
+#define PORTD (((volatile immap_t *)IMAP_ADDR)->im_ioport.iop_pddat)
+#define PORTE (((volatile immap_t *)IMAP_ADDR)->im_cpm.cp_pedat)
+
+/********************************************************************************/
+
+#define PIN_PORT_EQ(p, x) ((void *) & x ## _PORT == (void *) & p)
+#define PIN_PORT_NE(p, x) ((void *) & x ## _PORT != (void *) & p)
+
+#define PIN_PORT_RW(x) (PIN_PORT_NE(PORTXWO, x) && PIN_PORT_NE(PORTXRO, x))
+#define PIN_PORT_RO(x) PIN_PORT_EQ(PORTXRO, x)
+#define PIN_PORT_WO(x) PIN_PORT_EQ(PORTXWO, x)
+
+/********************************************************************************/
+
+#define PIN_SFT(x) ((sizeof(x ## _PORT) * 8 - 1) - x ## _BIT)
+#define PIN_MSK(x) (1U << PIN_SFT(x))
+
+/********************************************************************************/
+
+/* normal m8xx pins */
+#define _PIN_HI(x) \
+ do { \
+ x ## _PORT |= PIN_MSK(x); \
+ } while(0)
+
+#define _PIN_LO(x) \
+ do { \
+ x ## _PORT &= ~PIN_MSK(x); \
+ } while(0)
+
+#define _PIN_TGL(x) \
+ do { \
+ x ## _PORT ^= PIN_MSK(x); \
+ } while(0)
+
+#define _PIN_GET(x) \
+ (!!(x ## _PORT & PIN_MSK(x)))
+
+#define _PIN_SET(x, v) \
+ do { \
+ if (__builtin_constant_p(v)) { \
+ if ((v) != 0) \
+ _PIN_HI(x); \
+ else \
+ _PIN_LO(x); \
+ } else \
+ x ## _PORT = ( x ## _PORT & ~PIN_MSK(x)) | (!!(v) << PIN_SFT(x)); \
+ } while(0)
+
+#define _PIN_CFG_IN(x) \
+ do { \
+ if (PIN_PORT_EQ(PORTA, x)) \
+ PORTA_config(PIN_MSK(x), 0, 0); \
+ if (PIN_PORT_EQ(PORTB, x)) \
+ PORTB_config(PIN_MSK(x), 0, 0); \
+ if (PIN_PORT_EQ(PORTC, x)) \
+ PORTC_config(PIN_MSK(x), 0, 0); \
+ if (PIN_PORT_EQ(PORTD, x)) \
+ PORTD_config(PIN_MSK(x), 0, 0); \
+ if (PIN_PORT_EQ(PORTE, x)) \
+ PORTE_config(PIN_MSK(x), 0, 0); \
+ } while(0)
+
+#define _PIN_CFG_INT_ANY(x) \
+ do { \
+ if (PIN_PORT_EQ(PORTC, x)) \
+ PORTC_config(PIN_MSK(x), 0, 0); \
+ } while(0)
+
+#define _PIN_CFG_INT_FALL(x) \
+ do { \
+ if (PIN_PORT_EQ(PORTC, x)) \
+ PORTC_config(PIN_MSK(x), 0, 0); \
+ } while(0)
+
+#define _PIN_CFG_OUT(x, v) \
+ do { \
+ _PIN_SET(x, v); \
+ if (PIN_PORT_EQ(PORTA, x)) \
+ PORTA_config(0, PIN_MSK(x), 0); \
+ if (PIN_PORT_EQ(PORTB, x)) \
+ PORTB_config(0, PIN_MSK(x), 0); \
+ if (PIN_PORT_EQ(PORTC, x)) \
+ PORTC_config(0, PIN_MSK(x), 0); \
+ if (PIN_PORT_EQ(PORTD, x)) \
+ PORTD_config(0, PIN_MSK(x), 0); \
+ if (PIN_PORT_EQ(PORTE, x)) \
+ PORTE_config(0, PIN_MSK(x), 0); \
+ } while(0)
+
+#define _PIN_CFG_OUT_HI(x) _PIN_CFG_OUT(x, 1)
+#define _PIN_CFG_OUT_LO(x) _PIN_CFG_OUT(x, 0)
+
+#ifndef __ASSEMBLY__
+
+static inline void PORTA_config(uint inmsk, uint outmsk, uint dummy)
+{
+ volatile immap_t *imap = (volatile immap_t *)IMAP_ADDR;
+ ushort msk = (ushort)inmsk | (ushort)outmsk;
+
+ imap->im_ioport.iop_padir = (imap->im_ioport.iop_padir & ~(ushort)inmsk) | (ushort)outmsk;
+ imap->im_ioport.iop_paodr &= ~msk;
+ imap->im_ioport.iop_papar &= ~msk;
+}
+
+static inline void PORTB_config(uint inmsk, uint outmsk, uint dummy)
+{
+ volatile immap_t *imap = (volatile immap_t *)IMAP_ADDR;
+ uint msk = inmsk | outmsk;
+
+ imap->im_cpm.cp_pbdir = (imap->im_cpm.cp_pbdir & ~inmsk) | outmsk;
+ imap->im_cpm.cp_pbodr &= ~msk;
+ imap->im_cpm.cp_pbpar &= ~msk;
+}
+
+static inline void PORTC_config(uint inmsk, uint outmsk, uint fallmsk)
+{
+ volatile immap_t *imap = (volatile immap_t *)IMAP_ADDR;
+ ushort msk = (ushort)inmsk | (ushort)outmsk;
+
+ imap->im_ioport.iop_pcdir = (imap->im_ioport.iop_pcdir & ~(ushort)inmsk) | (ushort)outmsk;
+ imap->im_ioport.iop_pcso &= ~msk;
+ imap->im_ioport.iop_pcint = (imap->im_ioport.iop_pcint & ~(ushort)inmsk) | ((ushort)fallmsk & (ushort)inmsk);
+ imap->im_ioport.iop_pcpar &= ~msk;
+}
+
+static inline void PORTD_config(uint inmsk, uint outmsk, uint dummy)
+{
+ volatile immap_t *imap = (volatile immap_t *)IMAP_ADDR;
+ ushort msk = (ushort)inmsk | (ushort)outmsk;
+
+ imap->im_ioport.iop_pddir = (imap->im_ioport.iop_pddir & ~(ushort)inmsk) | (ushort)outmsk;
+ imap->im_ioport.iop_pdpar &= ~msk;
+}
+
+static inline void PORTE_config(uint inmsk, uint outmsk, uint dummy)
+{
+ volatile immap_t *imap = (volatile immap_t *)IMAP_ADDR;
+ uint msk = inmsk | outmsk;
+
+ imap->im_cpm.cp_pedir = (imap->im_cpm.cp_pedir & ~inmsk) | outmsk;
+ imap->im_cpm.cp_peodr &= ~msk;
+ imap->im_cpm.cp_pepar &= ~msk;
+}
+
+/**********************************************/
+
+unsigned long pin_lock(void);
+void pin_unlock(unsigned long flags);
+
+#endif /* __ASSEMBLY */
+
+/******************************************************************************/
+
+/* NAND flash pins */
+
+#define F_ALE_PORT PORTC
+#define F_ALE_BIT 15
+
+#define F_CLE_PORT PORTB
+#define F_CLE_BIT 23
+
+#define F_CE_PORT PORTA
+#define F_CE_BIT 7
+
+#define F_RY_BY_PORT PORTA
+#define F_RY_BY_BIT 6
+
+/***********************************************************************/
+
+/* SPI pin definitions */
+
+#define SPI_RXD_PORT PORTB
+#define SPI_RXD_BIT 28
+
+#define SPI_TXD_PORT PORTB
+#define SPI_TXD_BIT 29
+
+#define SPI_CLK_PORT PORTB
+#define SPI_CLK_BIT 30
+
+#define SPI_DELAY() udelay(1)
+
+#ifndef __ASSEMBLY__
+
+static inline unsigned int spi_transfer(unsigned int tx)
+{
+ unsigned int rx;
+ int i;
+
+ rx = 0;
+ for (i = 0; i < 8; i++) {
+ _PIN_SET(SPI_TXD, tx & 0x80);
+ tx <<= 1;
+ _PIN_TGL(SPI_CLK);
+ SPI_DELAY();
+ rx <<= 1;
+ rx |= _PIN_GET(SPI_RXD);
+ _PIN_TGL(SPI_CLK);
+ SPI_DELAY();
+ }
+
+ return rx;
+}
+
+#endif
+
+#define BOARD_CHIP_NAME "MPC870"
+
+#endif /* __MACH_STXXTC_DEFS */
+
diff --git a/arch/ppc/platforms/stxxtc_setup.c b/arch/ppc/platforms/stxxtc_setup.c
new file mode 100644
--- /dev/null
+++ b/arch/ppc/platforms/stxxtc_setup.c
@@ -0,0 +1,193 @@
+/*
+ * arch/ppc/platforms/stxxtc.c
+ *
+ * Platform setup for the Silicon Turnkey eXpress XTc
+ */
+
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/param.h>
+#include <linux/string.h>
+#include <linux/ioport.h>
+#include <linux/device.h>
+
+#include <asm/delay.h>
+#include <asm/io.h>
+#include <asm/machdep.h>
+#include <asm/page.h>
+#include <asm/processor.h>
+#include <asm/system.h>
+#include <asm/time.h>
+#include <asm/ppcboot.h>
+#include <asm/ppc_sys.h>
+
+#include <linux/stddef.h>
+
+#include <linux/fs_enet_pd.h>
+
+#include <platforms/stxxtc.h>
+
+/***********************************************************************/
+
+#ifdef CONFIG_FW_ENV
+#include <syslib/fw_env.h>
+
+static const char *ro_vars[] = {
+ "ethaddr", "eth1addr", "adsladdr", "serial#", "usbaddr", "usb1addr", "ver", "board",
+ NULL
+};
+#endif
+
+/***********************************************************************/
+
+static spinlock_t port_spinlock;
+
+unsigned long pin_lock(void)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&port_spinlock, flags);
+ return flags;
+}
+EXPORT_SYMBOL(pin_lock);
+
+void pin_unlock(unsigned long flags)
+{
+ spin_unlock_irqrestore(&port_spinlock, flags);
+}
+EXPORT_SYMBOL(pin_unlock);
+
+/***********************************************************************/
+
+static struct fs_mii_bus_info fec_mii_bus_info = {
+ .method = fsmii_fec,
+ .id = 0,
+};
+
+static struct fs_platform_info mpc8xx_fec_pdata[2] = {
+ [0] = {
+ .phy_addr = 0x01,
+ .phy_irq = -1,
+ .fs_no = fsid_fec1,
+ .rx_ring = 128,
+ .tx_ring = 16,
+ .napi_weight = 17,
+ .bus_info = &fec_mii_bus_info,
+ .rx_copybreak = 240,
+ .use_napi = 1,
+ .use_rmii = 0,
+ },
+ [1] = {
+ .phy_addr = 0x03,
+ .phy_irq = -1,
+ .fs_no = fsid_fec2,
+ .rx_ring = 128,
+ .tx_ring = 16,
+ .napi_weight = 17,
+ .bus_info = &fec_mii_bus_info,
+ .rx_copybreak = 240,
+ .use_napi = 1,
+ .use_rmii = 0,
+ }
+};
+
+/***********************************************************************/
+
+static void stxxtc_fixup_fs_pdata(struct platform_device *pd, int fs_no)
+{
+ struct fs_platform_info *fpi;
+ bd_t *bd;
+ int idx;
+
+ idx = fs_get_fec_index(fs_no);
+ if (idx == -1) {
+ printk(KERN_ERR "stxxtc_setup: Only FEC ethernets supported by STXXTC.\n");
+ return;
+ }
+
+ fpi = &mpc8xx_fec_pdata[idx];
+
+ bd = (bd_t *)__res;
+
+ memcpy(fpi->macaddr, bd->bi_enetaddr, 6);
+ fpi->macaddr[5] += idx; /* different per interface */
+
+ pd->dev.platform_data = fpi;
+
+ /* we don't setup *any* pins, we trust the bootloader */
+}
+
+static void stxxtc_fixup_fec_pdata(struct platform_device *pd, int idx)
+{
+ int fs_no = fsid_fec1 + pd->id - 1;
+
+ stxxtc_fixup_fs_pdata(pd, fs_no);
+}
+
+static int stxxtc_platform_notify(struct device *dev)
+{
+ static struct {
+ const char *bus_id;
+ void (*rtn)(struct platform_device * pdev, int idx);
+ } dev_map[] = {
+ { "fsl-cpm-fec", stxxtc_fixup_fec_pdata },
+ };
+ struct platform_device *pdev;
+ int i, j, idx;
+ const char *s;
+
+ if (dev && dev->bus_id)
+ for (i = 0; i < ARRAY_SIZE(dev_map); i++) {
+ idx = -1;
+ if ((s = strrchr(dev->bus_id, '.')) != NULL)
+ idx = (int)simple_strtol(s + 1, NULL, 10);
+ else
+ s = dev->bus_id + strlen(s);
+
+ j = s - dev->bus_id;
+
+ if (!strncmp(dev->bus_id, dev_map[i].bus_id, j)) {
+ pdev = container_of(dev, struct platform_device, dev);
+ dev_map[i].rtn(pdev, idx);
+ }
+ }
+
+ return 0;
+}
+
+int __init
+stxxtc_init(void)
+{
+ immap_t *imap = (immap_t *)IMAP_ADDR;
+
+ spin_lock_init(&port_spinlock);
+
+ imap->im_siu_conf.sc_sypcr |= 0x0000FF00;
+
+ /* configure SPI pins */
+ _PIN_CFG_OUT_HI(SPI_TXD);
+ _PIN_CFG_OUT_HI(SPI_CLK);
+ _PIN_CFG_IN(SPI_RXD);
+
+ /* configure NAND pins */
+ _PIN_CFG_OUT_LO(F_ALE);
+ _PIN_CFG_OUT_LO(F_CLE);
+ _PIN_CFG_OUT_HI(F_CE);
+ _PIN_CFG_IN(F_RY_BY);
+
+ platform_notify = stxxtc_platform_notify;
+
+ identify_ppc_sys_by_name("MPC885");
+
+ /* remove these devices */
+ ppc_sys_device_remove(MPC8xx_CPM_SCC1);
+ ppc_sys_device_remove(MPC8xx_CPM_SCC2);
+ ppc_sys_device_remove(MPC8xx_CPM_SCC3);
+ ppc_sys_device_remove(MPC8xx_CPM_SCC4);
+
+ return 0;
+}
+
+arch_initcall(stxxtc_init);
+
diff --git a/arch/ppc/syslib/m8xx_setup.c b/arch/ppc/syslib/m8xx_setup.c
--- a/arch/ppc/syslib/m8xx_setup.c
+++ b/arch/ppc/syslib/m8xx_setup.c
@@ -370,16 +370,26 @@ m8xx_map_io(void)
#if defined(CONFIG_NETTA)
io_block_mapping(_IO_BASE,_IO_BASE,_IO_BASE_SIZE, _PAGE_IO);
#endif
+#if defined(CONFIG_STXXTC)
+ io_block_mapping(_IO_BASE,_IO_BASE,64 << 10, _PAGE_IO);
+#endif
}
void __init
platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
unsigned long r6, unsigned long r7)
{
+ bd_t *bd;
+
parse_bootinfo(find_bootinfo());
- if ( r3 )
- memcpy( (void *)__res,(void *)(r3+KERNELBASE), sizeof(bd_t) );
+ if ( r3 ) {
+ bd = (bd_t *)(r3+KERNELBASE);
+ /* skip OF tree if present */
+ if (*(u32 *)bd == 0xd00dfeed)
+ bd = (bd_t *)((char *)bd + ((u32 *)bd)[1]);
+ memcpy(__res, bd, sizeof(bd_t));
+ }
#ifdef CONFIG_PCI
m8xx_setup_pci_ptrs();
diff --git a/drivers/mtd/maps/Kconfig b/drivers/mtd/maps/Kconfig
--- a/drivers/mtd/maps/Kconfig
+++ b/drivers/mtd/maps/Kconfig
@@ -639,5 +639,11 @@ config MTD_PLATRAM
This selection automatically selects the map_ram driver.
+config MTD_STXXTC_NOR
+ tristate "NOR Map driver for STXXTC NOR flash"
+ depends on STXXTC && MTD_CONCAT && MTD_PARTITIONS && MTD_CFI_INTELEXT
+ help
+ Map driver for Silicon Turnkey eXpress XTc NOR flash.
+
endmenu
diff --git a/drivers/mtd/maps/Makefile b/drivers/mtd/maps/Makefile
--- a/drivers/mtd/maps/Makefile
+++ b/drivers/mtd/maps/Makefile
@@ -72,3 +72,4 @@ obj-$(CONFIG_MTD_PLATRAM) += plat-ram.o
obj-$(CONFIG_MTD_OMAP_NOR) += omap_nor.o
obj-$(CONFIG_MTD_MTX1) += mtx-1_flash.o
obj-$(CONFIG_MTD_TQM834x) += tqm834x.o
+obj-$(CONFIG_MTD_STXXTC_NOR) += stxxtc_nor.o
diff --git a/drivers/mtd/maps/stxxtc_nor.c b/drivers/mtd/maps/stxxtc_nor.c
new file mode 100644
--- /dev/null
+++ b/drivers/mtd/maps/stxxtc_nor.c
@@ -0,0 +1,326 @@
+/*
+ * Handle mapping of the flash on the STXXTC board
+ */
+
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/ioport.h>
+#include <asm/io.h>
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/map.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/concat.h>
+
+/* Boot flash; same on every board */
+static struct mtd_info *stxxtc_mtd;
+
+#define SECTORSZ(x) ((x) * 64 * 1024)
+
+#define UBOOT_CODE_SECTORS 4
+
+#define ENV1_PART 0
+#define ENV2_PART 1
+
+#define CHKP1_PART 2
+#define CHKP2_PART 3
+
+#define STRG1_PART 4
+
+#define BOOT_PART 5
+
+#define STRG2_PART 6
+
+/* partition_info gives details on the logical partitions that the split the
+ * single flash device into. If the size if zero we use up to the end of the
+ * device. */
+static struct mtd_partition pi[]= {
+ [ENV1_PART] = {
+ .name = "u-boot env #1 0 4000",
+ .size = SECTORSZ(1),
+ .offset = SECTORSZ(0),
+ },
+ [ENV2_PART] = {
+ .name = "u-boot env #2 0 4000",
+ .size = SECTORSZ(1),
+ .offset = SECTORSZ(1),
+ },
+ [CHKP1_PART] = {
+ .name = "checkpoint #1",
+ .size = SECTORSZ(1),
+ .offset = SECTORSZ(2),
+ },
+ [CHKP2_PART] = {
+ .name = "checkpoint #2",
+ .size = SECTORSZ(1),
+ .offset = SECTORSZ(3),
+ },
+ [STRG1_PART] = {
+ .name = "storage #1",
+ .size = 0, /* to be filled */
+ .offset = SECTORSZ(4),
+ },
+ [BOOT_PART] = {
+ .name = "u-boot code",
+ .size = SECTORSZ(UBOOT_CODE_SECTORS),
+ .offset = 0, /* to be filled */
+ .mask_flags = MTD_WRITEABLE, /* don't allow writes at all */
+ },
+ [STRG2_PART] = {
+ .name = "storage #2",
+ .size = 0, /* what ever remains */
+ .offset = 0, /* to be filled */
+ }
+};
+
+#define NUM_PARTITIONS (sizeof(pi) / sizeof(pi[0]))
+
+#define WINDOW_ADDR 0x40000000
+#define WINDOW_SIZE 0x00200000
+
+struct map_info stxxtc_map = {
+ .name = "STXXTC boot flash",
+ .size = WINDOW_SIZE,
+ .bankwidth = 2,
+ .phys = WINDOW_ADDR,
+};
+
+/* two chips supported */
+#define NR_CHIPS 2
+
+struct stxxtc_nor_info {
+ unsigned long base;
+ unsigned long map_size;
+ char *mapname;
+ int width;
+ struct map_info map;
+ struct mtd_info *mtd;
+ struct resource *res;
+};
+
+static struct stxxtc_nor_info info[NR_CHIPS] = {
+ {
+ .base = 0x40000000,
+ .map_size = 0x01000000,
+ .width = 2,
+ .mapname = "stxxtc NOR flash #1",
+ }, {
+ .base = 0x42000000,
+ .map_size = 0x01000000,
+ .width = 2,
+ .mapname = "stxxtc NOR flash #2",
+ }
+};
+
+#if 1
+
+int __init init_stxxtc_nor(void)
+{
+ struct stxxtc_nor_info *ni;
+ int i, j, r = 0, found = 0;
+ unsigned long mask, off;
+ struct mtd_info *subdev[NR_CHIPS];
+
+ memset(subdev, 0, sizeof(subdev));
+
+ for (i = 0, ni = info; i < NR_CHIPS; i++, ni++) {
+
+ memset(&ni->map, 0, sizeof(ni->map));
+
+ ni->res = request_mem_region(ni->base, ni->map_size, ni->mapname);
+ if (ni->res == NULL) {
+ r = -EBUSY;
+ goto err;
+ }
+
+ ni->map.virt = ioremap(ni->base, ni->map_size);
+ if (ni->map.virt == NULL) {
+ r = -ENOMEM;
+ goto err;
+ }
+ ni->map.name = ni->mapname;
+ ni->map.phys = ni->base;
+ ni->map.bankwidth = 2;
+ ni->map.size = ni->map_size;
+ simple_map_init(&ni->map);
+
+ ni->mtd = do_map_probe("cfi_probe", &ni->map);
+ if (ni->mtd == NULL) {
+ /* chip missing; just cleanup and continue */
+ iounmap(ni->map.virt);
+ release_resource(ni->res);
+ ni->res = NULL;
+ memset(&ni->map, 0, sizeof(ni->map));
+ continue;
+ }
+
+ ni->mtd->owner = THIS_MODULE;
+
+ found++;
+
+ }
+
+ /* no chips found... */
+ if (found == 0) {
+ printk(KERN_INFO "stxxtc_nor: No devices found\n");
+ return -ENXIO;
+ }
+
+ /* first chip must exist. */
+ ni = &info[0]; i = 0; j = 0;
+ if (ni->mtd == NULL) {
+ printk(KERN_INFO "stxxtc_nor: First chip missing, not able to continue\n");
+ r = -ENXIO;
+ goto err;
+ }
+
+ printk(KERN_INFO "stxxtc_nor: CFI device found at 0x%08lx, "
+ "%dMiB, %d-bit wide\n",
+ ni->base, ni->mtd->size >> 20, ni->width * 8);
+
+ /* find out where u-boot code is. It's size is 256K and is located
+ * at the last megabyte of the first flash, for example a 2M flash
+ * will have the u-boot part at offset 0x00100000
+ */
+
+ mask = ni->mtd->size - 1;
+ off = 0xFFF00000 & mask;
+ printk(KERN_INFO "u-boot offset is at 0x%08lx\n", off);
+
+ /* keep it */
+ subdev[j++] = ni->mtd;
+
+ /* next */
+ i++; ni++;
+
+ /* report what we found */
+ for (; i < NR_CHIPS; i++, ni++) {
+ if (ni->mtd == NULL)
+ continue;
+ printk(KERN_INFO "stxxtc_nor: CFI device found at 0x%08lx, "
+ "%dMiB, %d-bit wide\n",
+ ni->base, ni->mtd->size >> 20, ni->width * 8);
+ subdev[j++] = ni->mtd;
+ }
+
+ /* concat all the devices into one */
+ stxxtc_mtd = mtd_concat_create(subdev, found, "stxxtc NOR flash");
+ if (stxxtc_mtd == NULL) {
+ r = -ENXIO;
+ goto err;
+ }
+ stxxtc_mtd->owner = THIS_MODULE;
+
+ /* fixup partitions */
+ pi[STRG1_PART].size = off - pi[STRG1_PART].offset;
+ pi[BOOT_PART].offset = off;
+ pi[STRG2_PART].offset = pi[BOOT_PART].offset + pi[BOOT_PART].size;
+
+ add_mtd_partitions(stxxtc_mtd, pi, NUM_PARTITIONS);
+
+ return 0;
+
+err:
+ if (stxxtc_mtd != NULL) {
+ del_mtd_partitions(stxxtc_mtd);
+ mtd_concat_destroy(stxxtc_mtd);
+ }
+
+ for (i = NR_CHIPS - 1, ni = info + i; i >= 0; i--, ni--) {
+ if (ni->mtd)
+ map_destroy(ni->mtd);
+ if (ni->map.virt)
+ iounmap(ni->map.virt);
+ if (ni->res != NULL)
+ release_resource(ni->res);
+ }
+
+
+ return r;
+}
+
+static void __exit cleanup_stxxtc_nor(void)
+{
+ int i;
+ struct stxxtc_nor_info *ni;
+
+ if (stxxtc_mtd != NULL) {
+ del_mtd_partitions(stxxtc_mtd);
+ mtd_concat_destroy(stxxtc_mtd);
+ }
+
+ for (i = NR_CHIPS - 1, ni = info + i; i >= 0; i--, ni--) {
+ if (ni->mtd)
+ map_destroy(ni->mtd);
+ if (ni->map.virt)
+ iounmap(ni->map.virt);
+ if (ni->res != NULL)
+ release_resource(ni->res);
+ }
+
+}
+
+#else
+
+int __init init_stxxtc_nor(void)
+{
+ int err = 0;
+ static const char *probes[] = { "cfi_probe", NULL };
+ const char **sv, *s;
+
+ stxxtc_map.virt = (void __iomem *)ioremap(WINDOW_ADDR, WINDOW_SIZE);
+ if (!stxxtc_map.virt) {
+ printk("stxxtc_nor: Failed to ioremap\n");
+ err = -ENXIO;
+ goto out;
+ }
+ simple_map_init(&stxxtc_map);
+
+ sv = probes;
+ while ((s = *sv++) != NULL) {
+ stxxtc_mtd = do_map_probe(s, &stxxtc_map);
+ if (stxxtc_mtd != NULL)
+ break;
+ }
+
+ if (!stxxtc_mtd) {
+ printk(KERN_NOTICE "stxxtc_nor: probe failed flash device: %x at %x\n", WINDOW_SIZE, WINDOW_ADDR);
+ err = -ENXIO;
+ goto out_unmap;
+ }
+
+ stxxtc_mtd->owner = THIS_MODULE;
+ add_mtd_partitions(stxxtc_mtd, pi, NUM_PARTITIONS);
+
+ return 0;
+
+out_unmap:
+ iounmap((void *)stxxtc_map.virt);
+out:
+
+ return err;
+}
+
+static void __exit cleanup_stxxtc_nor(void)
+{
+ if (stxxtc_mtd) {
+ del_mtd_partitions(stxxtc_mtd);
+ map_destroy(stxxtc_mtd);
+ stxxtc_mtd = 0;
+ }
+ if (stxxtc_map.virt) {
+ iounmap(stxxtc_map.virt);
+ stxxtc_map.virt = 0;
+ }
+}
+
+#endif
+
+module_init(init_stxxtc_nor);
+module_exit(cleanup_stxxtc_nor);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Pantelis Antoniou <pantelis.antoniou@gmail.com>");
+MODULE_DESCRIPTION("MTD map driver for STXXTC boards");
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -190,5 +190,11 @@ config MTD_NAND_DISKONCHIP_BBTWRITE
help
The simulator may simulate verious NAND flash chips for the
MTD nand layer.
-
+
+config MTD_NAND_STXXTC
+ tristate "NAND Flash support for STXXTC"
+ depends on STXXTC && MTD_NAND
+ help
+ Use the NAND flash present on Silicon Turnkey eXpress XTc.
+
endmenu
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -18,5 +18,6 @@ obj-$(CONFIG_MTD_NAND_H1900) += h1910.o
obj-$(CONFIG_MTD_NAND_RTC_FROM4) += rtc_from4.o
obj-$(CONFIG_MTD_NAND_SHARPSL) += sharpsl.o
obj-$(CONFIG_MTD_NAND_NANDSIM) += nandsim.o
+obj-$(CONFIG_MTD_NAND_STXXTC) += stxxtc_nand.o
nand-objs = nand_base.o nand_bbt.o
diff --git a/drivers/mtd/nand/stxxtc_nand.c b/drivers/mtd/nand/stxxtc_nand.c
new file mode 100644
--- /dev/null
+++ b/drivers/mtd/nand/stxxtc_nand.c
@@ -0,0 +1,277 @@
+/*
+ * drivers/mtd/nand/stxxtc_nand.c
+ *
+ * Copyright (C) 2005 Pantelis Antoniou <pantelis.antoniou@gmail.com>
+ * Dan Malek <dan@embeddedalley.com>
+ *
+ * Derived from drivers/mtd/nand/edb7312.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/config.h>
+
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/partitions.h>
+#include <linux/init.h>
+#include <asm/io.h>
+#include <asm/semaphore.h>
+
+#include <platforms/stxxtc.h>
+
+/******************************************************************************/
+
+static struct mtd_info *stxxtc_mtd = NULL;
+static unsigned int stxxtc_fio_base;
+static int mtd_parts_nb = 0;
+static struct mtd_partition *mtd_parts;
+static const char *part_type = NULL;
+static const char *part_probes[] = { "cmdlinepart", NULL };
+
+/* we need these */
+extern struct semaphore mtd_table_mutex;
+extern struct mtd_info *mtd_table[MAX_MTD_DEVICES];
+
+/******************************************************************************/
+
+/*
+ * hardware specific access to control-lines
+ */
+static void stxxtc_hwcontrol(struct mtd_info *mtd, int cmd)
+{
+ unsigned long flags;
+
+ local_irq_save(flags);
+
+ switch (cmd) {
+
+ case NAND_CTL_SETNCE:
+ _PIN_LO(F_CE);
+ break;
+
+ case NAND_CTL_CLRNCE:
+ _PIN_HI(F_CE);
+ break;
+
+ case NAND_CTL_SETCLE:
+ _PIN_HI(F_CLE);
+ break;
+
+ case NAND_CTL_CLRCLE:
+ _PIN_LO(F_CLE);
+ break;
+
+ case NAND_CTL_SETALE:
+ _PIN_HI(F_ALE);
+ break;
+
+ case NAND_CTL_CLRALE:
+ _PIN_LO(F_ALE);
+ break;
+ }
+
+ local_irq_restore(flags);
+}
+
+/*
+ * read device ready pin
+ */
+static int stxxtc_device_ready(struct mtd_info *mtd)
+{
+ return _PIN_GET(F_RY_BY);
+}
+
+/*
+ * Main initialization routine
+ */
+static int __init stxxtc_init(void)
+{
+ struct nand_chip *this = NULL;
+ int i, j, err = 0, rootidx;
+ const char *s, *rootmark="root=/dev/mtdblock";
+ unsigned int curroff, sz;
+ struct mtd_partition *part;
+
+ /* Allocate memory for MTD device structure and private data */
+ stxxtc_mtd = kmalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip), GFP_KERNEL);
+ if (!stxxtc_mtd) {
+ printk("Unable to allocate STXXTC NAND MTD device structure.\n");
+ err = -ENOMEM;
+ goto out;
+ }
+
+ /* map physical adress */
+ stxxtc_fio_base = (unsigned long)ioremap(NAND_BASE, NAND_SIZE);
+ if(!stxxtc_fio_base) {
+ printk("ioremap STXXTC NAND flash failed\n");
+ err = -EIO;
+ goto out;
+ }
+
+ /* Get pointer to private data */
+ this = (struct nand_chip *)&stxxtc_mtd[1];
+
+ /* Initialize structures */
+ memset((char *) stxxtc_mtd, 0, sizeof(struct mtd_info));
+ memset((char *) this, 0, sizeof(struct nand_chip));
+
+ /* Link the private data with the MTD structure */
+ stxxtc_mtd->priv = this;
+
+ /* insert callbacks */
+ this->IO_ADDR_R = (void __iomem *)stxxtc_fio_base;
+ this->IO_ADDR_W = (void __iomem *)stxxtc_fio_base;
+ this->hwcontrol = stxxtc_hwcontrol;
+ this->dev_ready = stxxtc_device_ready;
+ /* 15 us command delay time (XXX actually not used) */
+ this->chip_delay = 15;
+ /* TODO F_RY_BY pin is interrupt capable but it's not used as such */
+ this->eccmode = NAND_ECC_SOFT;
+
+ /* Scan to find existence of the device (minimum size is 8MiB) */
+ if (nand_scan(stxxtc_mtd, 1) || stxxtc_mtd->size < 8 * 1024 * 1024) {
+ err = -ENXIO;
+ goto out;
+ }
+
+ /* Set internal data buffer */
+ this->data_buf = kmalloc(stxxtc_mtd->oobblock + stxxtc_mtd->oobsize, GFP_KERNEL);
+ if (this->data_buf == NULL) {
+ printk(KERN_ERR "stxxtc_nand: Unable to allocate data buffer\n");
+ err = -ENOMEM;
+ goto out;
+ }
+
+
+#ifdef CONFIG_MTD_CMDLINE_PARTS
+ stxxtc_mtd->name = "stxxtc-nand";
+ mtd_parts_nb = parse_mtd_partitions(stxxtc_mtd, part_probes, &mtd_parts, 0);
+ if (mtd_parts_nb > 0)
+ part_type = "command line";
+ else
+ mtd_parts_nb = 0;
+#endif
+ if (mtd_parts_nb == 0) {
+
+ mtd_parts_nb = 3;
+
+ mtd_parts = kmalloc(sizeof(*mtd_parts) * mtd_parts_nb, GFP_KERNEL);
+ if (mtd_parts == NULL) {
+ printk(KERN_ERR "stxxtc_nand: Unable to allocate partition table buffer\n");
+ err = -ENOMEM;
+ goto out;
+ }
+ memset(mtd_parts, 0, sizeof(*mtd_parts) * mtd_parts_nb);
+
+ part = mtd_parts;
+
+ curroff = 0;
+
+ sz = (stxxtc_mtd->size - 512 * 1024) / 2;
+
+ part->name = "STXXTC root fs #1";
+ part->offset = curroff;
+ part->size = sz;
+ /* part->mask_flags= MTD_WRITEABLE; */
+ part++;
+ curroff += sz;
+
+ part->name = "STXXTC root fs #2";
+ part->offset = curroff;
+ part->size = sz;
+ part++;
+ curroff += sz;
+
+ part->name = "Persistent storage";
+ part->offset = curroff;
+ part->size = stxxtc_mtd->size - curroff;
+ part++;
+
+ part_type = "static";
+ }
+
+ /* lookup index of root MTD partition (if any) */
+ if ((s = strstr(saved_command_line, rootmark)) != NULL) {
+
+ rootidx = simple_strtoul(s + strlen(rootmark), NULL, 10);
+
+ /* XXX we assume that no-one will interrupts afterwards */
+ down(&mtd_table_mutex);
+ for (i = 0, j = 0; i < MAX_MTD_DEVICES; i++) {
+
+ if (mtd_table[i] != NULL)
+ continue;
+
+ if (i == rootidx) {
+ printk(KERN_INFO "stxxtc_nand: Marking root device mtd%d as read-only (%d)\n", i, j);
+ mtd_parts[j].mask_flags = MTD_WRITEABLE;
+ break;
+ }
+
+ if (++j >= mtd_parts_nb)
+ break;
+ }
+ up(&mtd_table_mutex);
+
+ }
+
+ /* Register the partitions */
+ printk(KERN_NOTICE "Using %s partition definition\n", part_type);
+ err = add_mtd_partitions(stxxtc_mtd, mtd_parts, mtd_parts_nb);
+ if (err != 0) {
+ printk(KERN_ERR "stxxtc_nand: Unable to add mtd partitions\n");
+ goto out;
+ }
+
+ kfree(mtd_parts);
+ mtd_parts = NULL;
+
+ return 0;
+
+out:
+ if (mtd_parts)
+ kfree(mtd_parts);
+ if (stxxtc_fio_base)
+ iounmap((void *)stxxtc_fio_base);
+ if (this && this->data_buf)
+ kfree(this->data_buf);
+ if (stxxtc_mtd)
+ kfree(stxxtc_mtd);
+ return err;
+}
+
+/*
+ * Clean up routine
+ */
+static void __exit stxxtc_cleanup(void)
+{
+ struct nand_chip *this = (struct nand_chip *) &stxxtc_mtd[1];
+
+ /* Unregister the device */
+ del_mtd_device(stxxtc_mtd);
+
+ /* unmap */
+ iounmap((void *)stxxtc_fio_base);
+
+ /* free data buffer */
+ kfree(this->data_buf);
+
+ /* Free the MTD device structure */
+ kfree(stxxtc_mtd);
+}
+
+module_init(stxxtc_init);
+module_exit(stxxtc_cleanup);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Pantelis Antoniou <pantelis.antoniou@gmail.com>");
+MODULE_DESCRIPTION("MTD map driver for STXXTC");
+
+
diff --git a/include/asm-ppc/mpc8xx.h b/include/asm-ppc/mpc8xx.h
--- a/include/asm-ppc/mpc8xx.h
+++ b/include/asm-ppc/mpc8xx.h
@@ -68,6 +68,10 @@
#include <platforms/mpc885ads.h>
#endif
+#if defined(CONFIG_STXXTC)
+#include <platforms/stxxtc.h>
+#endif
+
/* Currently, all 8xx boards that support a processor to PCI/ISA bridge
* use the same memory map.
*/
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