* Re: [PATCH 2/7] powerpc numa: Minor debugging code changes
From: Nathan Lynch @ 2006-03-21 18:54 UTC (permalink / raw)
To: Dave Hansen; +Cc: linuxppc-dev
In-Reply-To: <1142965632.10906.163.camel@localhost.localdomain>
On Tue, 2006-03-21 at 10:27 -0800, Dave Hansen wrote:
> On Mon, 2006-03-20 at 18:34 -0600, Nathan Lynch wrote:
> > Don't print a meaningless associativity depth (-1) on non-numa systems.
> ...
> > - dbg("NUMA associativity depth for CPU/Memory: %d\n", min_common_depth);
> > if (min_common_depth < 0)
> > return min_common_depth;
> >
> > + dbg("NUMA associativity depth for CPU/Memory: %d\n", min_common_depth);
>
> This is debugging code anyway, right?
>
> I thought this might be useful when you're booting on a machine which
> you _think_ should be NUMA, but doesn't come up that way. Did you boot
> a non-NUMA kernel, or is something in the reporting wrong? It makes it
> pretty obvious when you see this printout.
I think it's pretty obvious anyway -- we still print a message about not
finding the ibm,associativity-reference-points property, which is the
only reason min_common_depth would be -1.
This file isn't built when CONFIG_NUMA=n, so the placement of the dbg()
isn't going to shed any light on that particular operator error.
^ permalink raw reply
* Re: [PATCH 1/3] msi vector targeting abstractions
From: Mark Maule @ 2006-03-21 19:14 UTC (permalink / raw)
To: Andreas Schwab
Cc: Tony Luck, linux-ia64, gregkh, linux-kernel, Jun'ichi Nomura,
linuxppc64-dev, linux-pci
In-Reply-To: <jebqvzhhxr.fsf@sykes.suse.de>
On Tue, Mar 21, 2006 at 05:38:08PM +0100, Andreas Schwab wrote:
> "Jun'ichi Nomura" <j-nomura@ce.jp.nec.com> writes:
>
> > Hi Mark,
> >
> > Mark Maule wrote:
> >> Index: linux-2.6.16/include/asm-ia64/msi.h
> >> ===================================================================
> >> --- linux-2.6.16.orig/include/asm-ia64/msi.h 2006-03-19 23:53:29.000000000 -0600
> >> +++ linux-2.6.16/include/asm-ia64/msi.h 2006-03-20 14:50:53.331368084 -0600
> >> @@ -14,4 +14,16 @@
> >> #define ack_APIC_irq ia64_eoi
> >> #define MSI_TARGET_CPU_SHIFT 4
> >>
> >> +extern struct msi_ops msi_apic_ops;
> >> +
> >> +static inline int msi_arch_init(void)
> >> +{
> >> + if (platform_msi_init)
> >> + return platform_msi_init();
> >> +
> >> + /* default ops for most ia64 platforms */
> >> + msi_register(&msi_apic_ops);
> >> + return 0;
> >> +}
> >> +
> >> #endif /* ASM_MSI_H */
> >
> > It turned out that the above code breaks configs other
> > than CONFIG_IA64_SN and CONFIG_IA64_GENERIC.
> > e.g. CONFIG_IA64_DIG.
> >
> > In file included from /build/16.msi/drivers/pci/msi.h:71,
> > from /build/16.msi/drivers/pci/msi.c:24:
> > include2/asm/msi.h: In function `msi_arch_init':
> > include2/asm/msi.h:22: error: called object is not a function
> > make[3]: *** [drivers/pci/msi.o] Error 1
> >
> > Something like below might fix this problem:
> > if (platform_msi_init) {
> > ia64_mv_msi_init_t *fn = platform_msi_init;
> > return (*fn)();
> > }
>
> platform_msi_init should have the right type in the first place,
> ie. defined to ((ia64_mv_msi_init_t*)NULL) instead of just NULL.
>
> Andreas.
The following resend of 1/3 fixes this:
Abstract portions of the MSI core for platforms that do not use standard
APIC interrupt controllers. This is implemented through a new arch-specific
msi setup routine, and a set of msi ops which can be set on a per platform
basis.
Signed-off-by: Mark Maule <maule@sgi.com>
Index: linux-2.6.16/drivers/pci/msi.c
===================================================================
--- linux-2.6.16.orig/drivers/pci/msi.c 2006-03-21 11:13:59.726139722 -0600
+++ linux-2.6.16/drivers/pci/msi.c 2006-03-21 11:14:06.210856320 -0600
@@ -23,8 +23,6 @@
#include "pci.h"
#include "msi.h"
-#define MSI_TARGET_CPU first_cpu(cpu_online_map)
-
static DEFINE_SPINLOCK(msi_lock);
static struct msi_desc* msi_desc[NR_IRQS] = { [0 ... NR_IRQS-1] = NULL };
static kmem_cache_t* msi_cachep;
@@ -40,6 +38,15 @@
u8 irq_vector[NR_IRQ_VECTORS] = { FIRST_DEVICE_VECTOR , 0 };
#endif
+static struct msi_ops *msi_ops;
+
+int
+msi_register(struct msi_ops *ops)
+{
+ msi_ops = ops;
+ return 0;
+}
+
static void msi_cache_ctor(void *p, kmem_cache_t *cache, unsigned long flags)
{
memset(p, 0, NR_IRQS * sizeof(struct msi_desc));
@@ -92,7 +99,7 @@
static void set_msi_affinity(unsigned int vector, cpumask_t cpu_mask)
{
struct msi_desc *entry;
- struct msg_address address;
+ u32 address_hi, address_lo;
unsigned int irq = vector;
unsigned int dest_cpu = first_cpu(cpu_mask);
@@ -108,28 +115,36 @@
if (!(pos = pci_find_capability(entry->dev, PCI_CAP_ID_MSI)))
return;
+ pci_read_config_dword(entry->dev, msi_upper_address_reg(pos),
+ &address_hi);
pci_read_config_dword(entry->dev, msi_lower_address_reg(pos),
- &address.lo_address.value);
- address.lo_address.value &= MSI_ADDRESS_DEST_ID_MASK;
- address.lo_address.value |= (cpu_physical_id(dest_cpu) <<
- MSI_TARGET_CPU_SHIFT);
- entry->msi_attrib.current_cpu = cpu_physical_id(dest_cpu);
+ &address_lo);
+
+ msi_ops->target(vector, dest_cpu, &address_hi, &address_lo);
+
+ pci_write_config_dword(entry->dev, msi_upper_address_reg(pos),
+ address_hi);
pci_write_config_dword(entry->dev, msi_lower_address_reg(pos),
- address.lo_address.value);
+ address_lo);
set_native_irq_info(irq, cpu_mask);
break;
}
case PCI_CAP_ID_MSIX:
{
- int offset = entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
- PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET;
+ int offset_hi =
+ entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
+ PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET;
+ int offset_lo =
+ entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
+ PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET;
+
+ address_hi = readl(entry->mask_base + offset_hi);
+ address_lo = readl(entry->mask_base + offset_lo);
- address.lo_address.value = readl(entry->mask_base + offset);
- address.lo_address.value &= MSI_ADDRESS_DEST_ID_MASK;
- address.lo_address.value |= (cpu_physical_id(dest_cpu) <<
- MSI_TARGET_CPU_SHIFT);
- entry->msi_attrib.current_cpu = cpu_physical_id(dest_cpu);
- writel(address.lo_address.value, entry->mask_base + offset);
+ msi_ops->target(vector, dest_cpu, &address_hi, &address_lo);
+
+ writel(address_hi, entry->mask_base + offset_hi);
+ writel(address_lo, entry->mask_base + offset_lo);
set_native_irq_info(irq, cpu_mask);
break;
}
@@ -251,30 +266,6 @@
.set_affinity = set_msi_affinity
};
-static void msi_data_init(struct msg_data *msi_data,
- unsigned int vector)
-{
- memset(msi_data, 0, sizeof(struct msg_data));
- msi_data->vector = (u8)vector;
- msi_data->delivery_mode = MSI_DELIVERY_MODE;
- msi_data->level = MSI_LEVEL_MODE;
- msi_data->trigger = MSI_TRIGGER_MODE;
-}
-
-static void msi_address_init(struct msg_address *msi_address)
-{
- unsigned int dest_id;
- unsigned long dest_phys_id = cpu_physical_id(MSI_TARGET_CPU);
-
- memset(msi_address, 0, sizeof(struct msg_address));
- msi_address->hi_address = (u32)0;
- dest_id = (MSI_ADDRESS_HEADER << MSI_ADDRESS_HEADER_SHIFT);
- msi_address->lo_address.u.dest_mode = MSI_PHYSICAL_MODE;
- msi_address->lo_address.u.redirection_hint = MSI_REDIRECTION_HINT_MODE;
- msi_address->lo_address.u.dest_id = dest_id;
- msi_address->lo_address.value |= (dest_phys_id << MSI_TARGET_CPU_SHIFT);
-}
-
static int msi_free_vector(struct pci_dev* dev, int vector, int reassign);
static int assign_msi_vector(void)
{
@@ -369,6 +360,20 @@
return status;
}
+ if ((status = msi_arch_init()) < 0) {
+ pci_msi_enable = 0;
+ printk(KERN_WARNING
+ "PCI: MSI arch init failed. MSI disabled.\n");
+ return status;
+ }
+
+ if (! msi_ops) {
+ printk(KERN_WARNING
+ "PCI: MSI ops not registered. MSI disabled.\n");
+ status = -EINVAL;
+ return status;
+ }
+
if ((status = msi_cache_init()) < 0) {
pci_msi_enable = 0;
printk(KERN_WARNING "PCI: MSI cache init failed\n");
@@ -514,9 +519,11 @@
**/
static int msi_capability_init(struct pci_dev *dev)
{
+ int status;
struct msi_desc *entry;
- struct msg_address address;
- struct msg_data data;
+ u32 address_lo;
+ u32 address_hi;
+ u32 data;
int pos, vector;
u16 control;
@@ -543,23 +550,27 @@
entry->mask_base = (void __iomem *)(long)msi_mask_bits_reg(pos,
is_64bit_address(control));
}
+ /* Configure MSI capability structure */
+ status = msi_ops->setup(dev, vector,
+ &address_hi,
+ &address_lo,
+ &data);
+ if (status < 0) {
+ dev->irq = entry->msi_attrib.default_vector;
+ kmem_cache_free(msi_cachep, entry);
+ return status;
+ }
/* Replace with MSI handler */
irq_handler_init(PCI_CAP_ID_MSI, vector, entry->msi_attrib.maskbit);
- /* Configure MSI capability structure */
- msi_address_init(&address);
- msi_data_init(&data, vector);
- entry->msi_attrib.current_cpu = ((address.lo_address.u.dest_id >>
- MSI_TARGET_CPU_SHIFT) & MSI_TARGET_CPU_MASK);
- pci_write_config_dword(dev, msi_lower_address_reg(pos),
- address.lo_address.value);
+
+ pci_write_config_dword(dev, msi_lower_address_reg(pos), address_lo);
if (is_64bit_address(control)) {
pci_write_config_dword(dev,
- msi_upper_address_reg(pos), address.hi_address);
- pci_write_config_word(dev,
- msi_data_reg(pos, 1), *((u32*)&data));
+ msi_upper_address_reg(pos), address_hi);
+ pci_write_config_word(dev, msi_data_reg(pos, 1), data);
} else
- pci_write_config_word(dev,
- msi_data_reg(pos, 0), *((u32*)&data));
+ pci_write_config_word(dev, msi_data_reg(pos, 0), data);
+
if (entry->msi_attrib.maskbit) {
unsigned int maskbits, temp;
/* All MSIs are unmasked by default, Mask them all */
@@ -594,13 +605,15 @@
struct msix_entry *entries, int nvec)
{
struct msi_desc *head = NULL, *tail = NULL, *entry = NULL;
- struct msg_address address;
- struct msg_data data;
+ u32 address_hi;
+ u32 address_lo;
+ u32 data;
int vector, pos, i, j, nr_entries, temp = 0;
u32 phys_addr, table_offset;
u16 control;
u8 bir;
void __iomem *base;
+ int status;
pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
/* Request & Map MSI-X table region */
@@ -647,18 +660,20 @@
/* Replace with MSI-X handler */
irq_handler_init(PCI_CAP_ID_MSIX, vector, 1);
/* Configure MSI-X capability structure */
- msi_address_init(&address);
- msi_data_init(&data, vector);
- entry->msi_attrib.current_cpu =
- ((address.lo_address.u.dest_id >>
- MSI_TARGET_CPU_SHIFT) & MSI_TARGET_CPU_MASK);
- writel(address.lo_address.value,
+ status = msi_ops->setup(dev, vector,
+ &address_hi,
+ &address_lo,
+ &data);
+ if (status < 0)
+ break;
+
+ writel(address_lo,
base + j * PCI_MSIX_ENTRY_SIZE +
PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET);
- writel(address.hi_address,
+ writel(address_hi,
base + j * PCI_MSIX_ENTRY_SIZE +
PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET);
- writel(*(u32*)&data,
+ writel(data,
base + j * PCI_MSIX_ENTRY_SIZE +
PCI_MSIX_ENTRY_DATA_OFFSET);
attach_msi_entry(entry, vector);
@@ -793,6 +808,8 @@
void __iomem *base;
unsigned long flags;
+ msi_ops->teardown(vector);
+
spin_lock_irqsave(&msi_lock, flags);
entry = msi_desc[vector];
if (!entry || entry->dev != dev) {
Index: linux-2.6.16/include/asm-i386/msi.h
===================================================================
--- linux-2.6.16.orig/include/asm-i386/msi.h 2006-03-21 11:13:59.727116189 -0600
+++ linux-2.6.16/include/asm-i386/msi.h 2006-03-21 11:14:06.213785721 -0600
@@ -12,4 +12,12 @@
#define LAST_DEVICE_VECTOR 232
#define MSI_TARGET_CPU_SHIFT 12
+extern struct msi_ops msi_apic_ops;
+
+static inline int msi_arch_init(void)
+{
+ msi_register(&msi_apic_ops);
+ return 0;
+}
+
#endif /* ASM_MSI_H */
Index: linux-2.6.16/include/asm-x86_64/msi.h
===================================================================
--- linux-2.6.16.orig/include/asm-x86_64/msi.h 2006-03-21 11:13:59.728092656 -0600
+++ linux-2.6.16/include/asm-x86_64/msi.h 2006-03-21 11:14:06.214762188 -0600
@@ -13,4 +13,12 @@
#define LAST_DEVICE_VECTOR 232
#define MSI_TARGET_CPU_SHIFT 12
+extern struct msi_ops msi_apic_ops;
+
+static inline int msi_arch_init(void)
+{
+ msi_register(&msi_apic_ops);
+ return 0;
+}
+
#endif /* ASM_MSI_H */
Index: linux-2.6.16/include/asm-ia64/machvec.h
===================================================================
--- linux-2.6.16.orig/include/asm-ia64/machvec.h 2006-03-21 11:13:59.728092656 -0600
+++ linux-2.6.16/include/asm-ia64/machvec.h 2006-03-21 11:14:57.089663570 -0600
@@ -74,6 +74,7 @@
typedef unsigned short ia64_mv_readw_relaxed_t (const volatile void __iomem *);
typedef unsigned int ia64_mv_readl_relaxed_t (const volatile void __iomem *);
typedef unsigned long ia64_mv_readq_relaxed_t (const volatile void __iomem *);
+typedef int ia64_mv_msi_init_t (void);
static inline void
machvec_noop (void)
@@ -146,6 +147,7 @@
# define platform_readw_relaxed ia64_mv.readw_relaxed
# define platform_readl_relaxed ia64_mv.readl_relaxed
# define platform_readq_relaxed ia64_mv.readq_relaxed
+# define platform_msi_init ia64_mv.msi_init
# endif
/* __attribute__((__aligned__(16))) is required to make size of the
@@ -194,6 +196,7 @@
ia64_mv_readw_relaxed_t *readw_relaxed;
ia64_mv_readl_relaxed_t *readl_relaxed;
ia64_mv_readq_relaxed_t *readq_relaxed;
+ ia64_mv_msi_init_t *msi_init;
} __attribute__((__aligned__(16))); /* align attrib? see above comment */
#define MACHVEC_INIT(name) \
@@ -238,6 +241,7 @@
platform_readw_relaxed, \
platform_readl_relaxed, \
platform_readq_relaxed, \
+ platform_msi_init, \
}
extern struct ia64_machine_vector ia64_mv;
@@ -386,5 +390,8 @@
#ifndef platform_readq_relaxed
# define platform_readq_relaxed __ia64_readq_relaxed
#endif
+#ifndef platform_msi_init
+# define platform_msi_init ((ia64_mv_msi_init_t*)NULL)
+#endif
#endif /* _ASM_IA64_MACHVEC_H */
Index: linux-2.6.16/include/asm-ia64/machvec_sn2.h
===================================================================
--- linux-2.6.16.orig/include/asm-ia64/machvec_sn2.h 2006-03-21 11:13:59.728092656 -0600
+++ linux-2.6.16/include/asm-ia64/machvec_sn2.h 2006-03-21 11:14:06.216715122 -0600
@@ -66,6 +66,7 @@
extern ia64_mv_dma_sync_sg_for_device sn_dma_sync_sg_for_device;
extern ia64_mv_dma_mapping_error sn_dma_mapping_error;
extern ia64_mv_dma_supported sn_dma_supported;
+extern ia64_mv_msi_init_t sn_msi_init;
/*
* This stuff has dual use!
@@ -115,6 +116,11 @@
#define platform_dma_sync_sg_for_device sn_dma_sync_sg_for_device
#define platform_dma_mapping_error sn_dma_mapping_error
#define platform_dma_supported sn_dma_supported
+#ifdef CONFIG_PCI_MSI
+#define platform_msi_init sn_msi_init
+#else
+#define platform_msi_init NULL
+#endif
#include <asm/sn/io.h>
Index: linux-2.6.16/include/asm-ia64/msi.h
===================================================================
--- linux-2.6.16.orig/include/asm-ia64/msi.h 2006-03-21 11:13:59.729069123 -0600
+++ linux-2.6.16/include/asm-ia64/msi.h 2006-03-21 11:14:06.217691588 -0600
@@ -14,4 +14,16 @@
#define ack_APIC_irq ia64_eoi
#define MSI_TARGET_CPU_SHIFT 4
+extern struct msi_ops msi_apic_ops;
+
+static inline int msi_arch_init(void)
+{
+ if (platform_msi_init)
+ return platform_msi_init();
+
+ /* default ops for most ia64 platforms */
+ msi_register(&msi_apic_ops);
+ return 0;
+}
+
#endif /* ASM_MSI_H */
Index: linux-2.6.16/drivers/pci/Makefile
===================================================================
--- linux-2.6.16.orig/drivers/pci/Makefile 2006-03-21 11:13:59.726139722 -0600
+++ linux-2.6.16/drivers/pci/Makefile 2006-03-21 11:14:06.217691588 -0600
@@ -26,7 +26,11 @@
obj-$(CONFIG_PPC64) += setup-bus.o
obj-$(CONFIG_MIPS) += setup-bus.o setup-irq.o
obj-$(CONFIG_X86_VISWS) += setup-irq.o
-obj-$(CONFIG_PCI_MSI) += msi.o
+
+msiobj-y := msi.o msi-apic.o
+msiobj-$(CONFIG_IA64_GENERIC) += msi-altix.o
+msiobj-$(CONFIG_IA64_SGI_SN2) += msi-altix.o
+obj-$(CONFIG_PCI_MSI) += $(msiobj-y)
#
# ACPI Related PCI FW Functions
Index: linux-2.6.16/drivers/pci/msi-apic.c
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ linux-2.6.16/drivers/pci/msi-apic.c 2006-03-21 11:14:06.220620989 -0600
@@ -0,0 +1,100 @@
+/*
+ * MSI hooks for standard x86 apic
+ */
+
+#include <linux/pci.h>
+#include <linux/irq.h>
+
+#include "msi.h"
+
+/*
+ * Shifts for APIC-based data
+ */
+
+#define MSI_DATA_VECTOR_SHIFT 0
+#define MSI_DATA_VECTOR(v) (((u8)v) << MSI_DATA_VECTOR_SHIFT)
+
+#define MSI_DATA_DELIVERY_SHIFT 8
+#define MSI_DATA_DELIVERY_FIXED (0 << MSI_DATA_DELIVERY_SHIFT)
+#define MSI_DATA_DELIVERY_LOWPRI (1 << MSI_DATA_DELIVERY_SHIFT)
+
+#define MSI_DATA_LEVEL_SHIFT 14
+#define MSI_DATA_LEVEL_DEASSERT (0 << MSI_DATA_LEVEL_SHIFT)
+#define MSI_DATA_LEVEL_ASSERT (1 << MSI_DATA_LEVEL_SHIFT)
+
+#define MSI_DATA_TRIGGER_SHIFT 15
+#define MSI_DATA_TRIGGER_EDGE (0 << MSI_DATA_TRIGGER_SHIFT)
+#define MSI_DATA_TRIGGER_LEVEL (1 << MSI_DATA_TRIGGER_SHIFT)
+
+/*
+ * Shift/mask fields for APIC-based bus address
+ */
+
+#define MSI_ADDR_HEADER 0xfee00000
+
+#define MSI_ADDR_DESTID_MASK 0xfff0000f
+#define MSI_ADDR_DESTID_CPU(cpu) ((cpu) << MSI_TARGET_CPU_SHIFT)
+
+#define MSI_ADDR_DESTMODE_SHIFT 2
+#define MSI_ADDR_DESTMODE_PHYS (0 << MSI_ADDR_DESTMODE_SHIFT)
+#define MSI_ADDR_DESTMODE_LOGIC (1 << MSI_ADDR_DESTMODE_SHIFT)
+
+#define MSI_ADDR_REDIRECTION_SHIFT 3
+#define MSI_ADDR_REDIRECTION_CPU (0 << MSI_ADDR_REDIRECTION_SHIFT)
+#define MSI_ADDR_REDIRECTION_LOWPRI (1 << MSI_ADDR_REDIRECTION_SHIFT)
+
+
+static void
+msi_target_apic(unsigned int vector,
+ unsigned int dest_cpu,
+ u32 *address_hi, /* in/out */
+ u32 *address_lo) /* in/out */
+{
+ u32 addr = *address_lo;
+
+ addr &= MSI_ADDR_DESTID_MASK;
+ addr |= MSI_ADDR_DESTID_CPU(cpu_physical_id(dest_cpu));
+
+ *address_lo = addr;
+}
+
+static int
+msi_setup_apic(struct pci_dev *pdev, /* unused in generic */
+ unsigned int vector,
+ u32 *address_hi,
+ u32 *address_lo,
+ u32 *data)
+{
+ unsigned long dest_phys_id;
+
+ dest_phys_id = cpu_physical_id(first_cpu(cpu_online_map));
+
+ *address_hi = 0;
+ *address_lo = MSI_ADDR_HEADER |
+ MSI_ADDR_DESTMODE_PHYS |
+ MSI_ADDR_REDIRECTION_CPU |
+ MSI_ADDR_DESTID_CPU(dest_phys_id);
+
+ *data = MSI_DATA_TRIGGER_EDGE |
+ MSI_DATA_LEVEL_ASSERT |
+ MSI_DATA_DELIVERY_FIXED |
+ MSI_DATA_VECTOR(vector);
+
+ return 0;
+}
+
+static void
+msi_teardown_apic(unsigned int vector)
+{
+ return; /* no-op */
+}
+
+/*
+ * Generic ops used on most IA archs/platforms. Set with msi_register()
+ */
+
+struct msi_ops msi_apic_ops = {
+ .setup = msi_setup_apic,
+ .teardown = msi_teardown_apic,
+ .target = msi_target_apic,
+};
Index: linux-2.6.16/drivers/pci/msi.h
===================================================================
--- linux-2.6.16.orig/drivers/pci/msi.h 2006-03-21 11:13:59.727116189 -0600
+++ linux-2.6.16/drivers/pci/msi.h 2006-03-21 11:14:06.223550390 -0600
@@ -6,6 +6,68 @@
#ifndef MSI_H
#define MSI_H
+/*
+ * MSI operation vector. Used by the msi core code (drivers/pci/msi.c)
+ * to abstract platform-specific tasks relating to MSI address generation
+ * and resource management.
+ */
+struct msi_ops {
+ /**
+ * setup - generate an MSI bus address and data for a given vector
+ * @pdev: PCI device context (in)
+ * @vector: vector allocated by the msi core (in)
+ * @addr_hi: upper 32 bits of PCI bus MSI address (out)
+ * @addr_lo: lower 32 bits of PCI bus MSI address (out)
+ * @data: MSI data payload (out)
+ *
+ * Description: The setup op is used to generate a PCI bus addres and
+ * data which the msi core will program into the card MSI capability
+ * registers. The setup routine is responsible for picking an initial
+ * cpu to target the MSI at. The setup routine is responsible for
+ * examining pdev to determine the MSI capabilities of the card and
+ * generating a suitable address/data. The setup routine is
+ * responsible for allocating and tracking any system resources it
+ * needs to route the MSI to the cpu it picks, and for associating
+ * those resources with the passed in vector.
+ *
+ * Returns 0 if the MSI address/data was successfully setup.
+ **/
+
+ int (*setup) (struct pci_dev *pdev, unsigned int vector,
+ u32 *addr_hi, u32 *addr_lo, u32 *data);
+
+ /**
+ * teardown - release resources allocated by setup
+ * @vector: vector context for resources (in)
+ *
+ * Description: The teardown op is used to release any resources
+ * that were allocated in the setup routine associated with the passed
+ * in vector.
+ **/
+
+ void (*teardown) (unsigned int vector);
+
+ /**
+ * target - retarget an MSI at a different cpu
+ * @vector: vector context for resources (in)
+ * @cpu: new cpu to direct vector at (in)
+ * @addr_hi: new value of PCI bus upper 32 bits (in/out)
+ * @addr_lo: new value of PCI bus lower 32 bits (in/out)
+ *
+ * Description: The target op is used to redirect an MSI vector
+ * at a different cpu. addr_hi/addr_lo coming in are the existing
+ * values that the MSI core has programmed into the card. The
+ * target code is responsible for freeing any resources (if any)
+ * associated with the old address, and generating a new PCI bus
+ * addr_hi/addr_lo that will redirect the vector at the indicated cpu.
+ **/
+
+ void (*target) (unsigned int vector, unsigned int cpu,
+ u32 *addr_hi, u32 *addr_lo);
+};
+
+extern int msi_register(struct msi_ops *ops);
+
#include <asm/msi.h>
/*
@@ -63,67 +125,6 @@
#define msix_mask(address) (address | PCI_MSIX_FLAGS_BITMASK)
#define msix_is_pending(address) (address & PCI_MSIX_FLAGS_PENDMASK)
-/*
- * MSI Defined Data Structures
- */
-#define MSI_ADDRESS_HEADER 0xfee
-#define MSI_ADDRESS_HEADER_SHIFT 12
-#define MSI_ADDRESS_HEADER_MASK 0xfff000
-#define MSI_ADDRESS_DEST_ID_MASK 0xfff0000f
-#define MSI_TARGET_CPU_MASK 0xff
-#define MSI_DELIVERY_MODE 0
-#define MSI_LEVEL_MODE 1 /* Edge always assert */
-#define MSI_TRIGGER_MODE 0 /* MSI is edge sensitive */
-#define MSI_PHYSICAL_MODE 0
-#define MSI_LOGICAL_MODE 1
-#define MSI_REDIRECTION_HINT_MODE 0
-
-struct msg_data {
-#if defined(__LITTLE_ENDIAN_BITFIELD)
- __u32 vector : 8;
- __u32 delivery_mode : 3; /* 000b: FIXED | 001b: lowest prior */
- __u32 reserved_1 : 3;
- __u32 level : 1; /* 0: deassert | 1: assert */
- __u32 trigger : 1; /* 0: edge | 1: level */
- __u32 reserved_2 : 16;
-#elif defined(__BIG_ENDIAN_BITFIELD)
- __u32 reserved_2 : 16;
- __u32 trigger : 1; /* 0: edge | 1: level */
- __u32 level : 1; /* 0: deassert | 1: assert */
- __u32 reserved_1 : 3;
- __u32 delivery_mode : 3; /* 000b: FIXED | 001b: lowest prior */
- __u32 vector : 8;
-#else
-#error "Bitfield endianness not defined! Check your byteorder.h"
-#endif
-} __attribute__ ((packed));
-
-struct msg_address {
- union {
- struct {
-#if defined(__LITTLE_ENDIAN_BITFIELD)
- __u32 reserved_1 : 2;
- __u32 dest_mode : 1; /*0:physic | 1:logic */
- __u32 redirection_hint: 1; /*0: dedicated CPU
- 1: lowest priority */
- __u32 reserved_2 : 4;
- __u32 dest_id : 24; /* Destination ID */
-#elif defined(__BIG_ENDIAN_BITFIELD)
- __u32 dest_id : 24; /* Destination ID */
- __u32 reserved_2 : 4;
- __u32 redirection_hint: 1; /*0: dedicated CPU
- 1: lowest priority */
- __u32 dest_mode : 1; /*0:physic | 1:logic */
- __u32 reserved_1 : 2;
-#else
-#error "Bitfield endianness not defined! Check your byteorder.h"
-#endif
- }u;
- __u32 value;
- }lo_address;
- __u32 hi_address;
-} __attribute__ ((packed));
-
struct msi_desc {
struct {
__u8 type : 5; /* {0: unused, 5h:MSI, 11h:MSI-X} */
@@ -132,7 +133,7 @@
__u8 reserved: 1; /* reserved */
__u8 entry_nr; /* specific enabled entry */
__u8 default_vector; /* default pre-assigned vector */
- __u8 current_cpu; /* current destination cpu */
+ __u8 unused; /* formerly unused destination cpu*/
}msi_attrib;
struct {
Index: linux-2.6.16/drivers/pci/msi-altix.c
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ linux-2.6.16/drivers/pci/msi-altix.c 2006-03-21 11:14:06.229409191 -0600
@@ -0,0 +1,18 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2006 Silicon Graphics, Inc. All Rights Reserved.
+ */
+
+#include <asm/errno.h>
+
+int
+sn_msi_init(void)
+{
+ /*
+ * return error until MSI is supported on altix platforms
+ */
+ return -EINVAL;
+}
^ permalink raw reply
* Re: [PATCH 7/7] powerpc numa: Consolidate assignment of cpus to nodes
From: Nathan Lynch @ 2006-03-21 19:16 UTC (permalink / raw)
To: Dave Hansen; +Cc: linuxppc-dev
In-Reply-To: <1142966317.10906.172.camel@localhost.localdomain>
On Tue, 2006-03-21 at 10:38 -0800, Dave Hansen wrote:
> On Mon, 2006-03-20 at 18:37 -0600, Nathan Lynch wrote:
> > + cpu_numa_callback(&ppc64_numa_nb, CPU_UP_PREPARE,
> > + (void *)(unsigned long)boot_cpuid);
>
> That double-cast really caught my eye. cpu_numa_callback() looks a
> little bit confused about what type cpuids should be.
>
> Its lcpu is an "unsigned long", but it has integers passed into it
> (boot_cpuid), and calls map_cpu_to_node(lcpu, 0), where the first
> argument is an integer, but an "unsigned long" is passed in. This may
> be harmless, but I still have to think about it, which is bad.
>
> Seems like just making cpu_numa_callback()'s lcpu an int would get rid
> of at least one net cast. Why not just pass &boot_cpuid in there, and
> do this:
>
> int lcpu = *(int *)hcpu;
That's not the convention for cpu hotplug notifiers. The id of the cpu
subject to online/offline is passed in the void * argument. I'd have to
change the cpu hotplug core and every notifier in the kernel to
implement your suggestion.
>
> That makes it _really_ obvious what is going on. While it isn't
> horribly uncommon to pass integers around inside of void*s, it can be a
> bit confusing. You also get readability issues with long<->int
> conversions as you saw.
>
> By the way, what do the "l" and "h" in front of "cpu" mean anyway?
"logical" and "hot"? I dunno, just seemed to be the convention in other
cpu notifiers at the time the code was written.
^ permalink raw reply
* Re: [PATCH 1/3] msi vector targeting abstractions
From: Jun'ichi Nomura @ 2006-03-21 19:23 UTC (permalink / raw)
To: Mark Maule
Cc: Tony Luck, linux-ia64, gregkh, linux-kernel, linuxppc64-dev,
linux-pci
In-Reply-To: <20060321191414.GE22524@sgi.com>
Hi,
Mark Maule wrote:
> @@ -386,5 +390,8 @@
> #ifndef platform_readq_relaxed
> # define platform_readq_relaxed __ia64_readq_relaxed
> #endif
> +#ifndef platform_msi_init
> +# define platform_msi_init ((ia64_mv_msi_init_t*)NULL)
> +#endif
You may also need to change the sn specific header below.
> @@ -115,6 +116,11 @@
> #define platform_dma_sync_sg_for_device sn_dma_sync_sg_for_device
> #define platform_dma_mapping_error sn_dma_mapping_error
> #define platform_dma_supported sn_dma_supported
> +#ifdef CONFIG_PCI_MSI
> +#define platform_msi_init sn_msi_init
> +#else
> +#define platform_msi_init NULL
> +#endif
Thanks,
--
Jun'ichi Nomura, NEC Solutions (America), Inc.
^ permalink raw reply
* Re: [PATCH 2/7] powerpc numa: Minor debugging code changes
From: Dave Hansen @ 2006-03-21 18:27 UTC (permalink / raw)
To: Nathan Lynch; +Cc: linuxppc-dev
In-Reply-To: <11429012851755-git-send-email-nathanl@austin.ibm.com>
On Mon, 2006-03-20 at 18:34 -0600, Nathan Lynch wrote:
> Don't print a meaningless associativity depth (-1) on non-numa systems.
...
> - dbg("NUMA associativity depth for CPU/Memory: %d\n", min_common_depth);
> if (min_common_depth < 0)
> return min_common_depth;
>
> + dbg("NUMA associativity depth for CPU/Memory: %d\n", min_common_depth);
This is debugging code anyway, right?
I thought this might be useful when you're booting on a machine which
you _think_ should be NUMA, but doesn't come up that way. Did you boot
a non-NUMA kernel, or is something in the reporting wrong? It makes it
pretty obvious when you see this printout.
-- Dave
^ permalink raw reply
* Re: [PATCH] powerpc: Add FSL SEC node to documentation
From: Hollis Blanchard @ 2006-03-21 19:28 UTC (permalink / raw)
To: Kumar Gala; +Cc: linuxppc-dev
In-Reply-To: <1DBAE58F-2152-4074-B9BA-ADB1FA63DD1B@kernel.crashing.org>
On Tue, 2006-03-21 at 12:25 -0600, Kumar Gala wrote:
> On Mar 20, 2006, at 8:14 PM, Hollis Blanchard wrote:
>
> > On Monday 20 March 2006 19:59, Kim Phillips wrote:
> >> diff --git a/Documentation/powerpc/booting-without-of.txt
> > b/Documentation/powerpc/booting-without-of.txt
> >> index d02c649..72f3241 100644
> >> --- a/Documentation/powerpc/booting-without-of.txt
> >> +++ b/Documentation/powerpc/booting-without-of.txt
> >> @@ -1365,6 +1365,79 @@ platforms are moved over to use the flat
> >> };
> >>
> >>
> >> + g) Freescale SOC SEC Security Engines
> >> +
> >> + Required properties:
> >> +
> >> + - device_type : Should be "crypto"
> >> + - model : Model of the device. Should be "SEC1" or "SEC2"
> >> + - compatible : Should be "talitos"
> > [snip]
> >
> > Have you consulted with any other vendors regarding these
> > properties? I know
> > there is no IEEE1275 binding for these sorts of devices, but we can
> > at least
> > attempt to standardize it (even in the absence of the Open Firmware
> > Working
> > Group)...
>
> Beyond the device_type, I'm not sure if there is much more one could
> standardize one. The other fields that Kim spec'd are either generic
> OF fields (reg, interrupts, etc.) or specific to the Freescale devices.
The device_type and compatible properties are exactly what I'm talking
about.
-Hollis
^ permalink raw reply
* Re: [PATCH 1/3] msi vector targeting abstractions
From: Mark Maule @ 2006-03-21 19:38 UTC (permalink / raw)
To: Jun'ichi Nomura
Cc: Tony Luck, linux-ia64, gregkh, linux-kernel, linuxppc64-dev,
linux-pci
In-Reply-To: <442052C0.8050304@ce.jp.nec.com>
On Tue, Mar 21, 2006 at 02:23:44PM -0500, Jun'ichi Nomura wrote:
> Hi,
>
> Mark Maule wrote:
> >@@ -386,5 +390,8 @@
> > #ifndef platform_readq_relaxed
> > # define platform_readq_relaxed __ia64_readq_relaxed
> > #endif
> >+#ifndef platform_msi_init
> >+# define platform_msi_init ((ia64_mv_msi_init_t*)NULL)
> >+#endif
>
> You may also need to change the sn specific header below.
>
> >@@ -115,6 +116,11 @@
> > #define platform_dma_sync_sg_for_device sn_dma_sync_sg_for_device
> > #define platform_dma_mapping_error sn_dma_mapping_error
> > #define platform_dma_supported sn_dma_supported
> >+#ifdef CONFIG_PCI_MSI
> >+#define platform_msi_init sn_msi_init
> >+#else
> >+#define platform_msi_init NULL
> >+#endif
>
> Thanks,
> --
> Jun'ichi Nomura, NEC Solutions (America), Inc.
Right - patch attached:
Abstract portions of the MSI core for platforms that do not use standard
APIC interrupt controllers. This is implemented through a new arch-specific
msi setup routine, and a set of msi ops which can be set on a per platform
basis.
Signed-off-by: Mark Maule <maule@sgi.com>
Index: linux-2.6.16/drivers/pci/msi.c
===================================================================
--- linux-2.6.16.orig/drivers/pci/msi.c 2006-03-21 11:13:59.726139722 -0600
+++ linux-2.6.16/drivers/pci/msi.c 2006-03-21 11:14:06.210856320 -0600
@@ -23,8 +23,6 @@
#include "pci.h"
#include "msi.h"
-#define MSI_TARGET_CPU first_cpu(cpu_online_map)
-
static DEFINE_SPINLOCK(msi_lock);
static struct msi_desc* msi_desc[NR_IRQS] = { [0 ... NR_IRQS-1] = NULL };
static kmem_cache_t* msi_cachep;
@@ -40,6 +38,15 @@
u8 irq_vector[NR_IRQ_VECTORS] = { FIRST_DEVICE_VECTOR , 0 };
#endif
+static struct msi_ops *msi_ops;
+
+int
+msi_register(struct msi_ops *ops)
+{
+ msi_ops = ops;
+ return 0;
+}
+
static void msi_cache_ctor(void *p, kmem_cache_t *cache, unsigned long flags)
{
memset(p, 0, NR_IRQS * sizeof(struct msi_desc));
@@ -92,7 +99,7 @@
static void set_msi_affinity(unsigned int vector, cpumask_t cpu_mask)
{
struct msi_desc *entry;
- struct msg_address address;
+ u32 address_hi, address_lo;
unsigned int irq = vector;
unsigned int dest_cpu = first_cpu(cpu_mask);
@@ -108,28 +115,36 @@
if (!(pos = pci_find_capability(entry->dev, PCI_CAP_ID_MSI)))
return;
+ pci_read_config_dword(entry->dev, msi_upper_address_reg(pos),
+ &address_hi);
pci_read_config_dword(entry->dev, msi_lower_address_reg(pos),
- &address.lo_address.value);
- address.lo_address.value &= MSI_ADDRESS_DEST_ID_MASK;
- address.lo_address.value |= (cpu_physical_id(dest_cpu) <<
- MSI_TARGET_CPU_SHIFT);
- entry->msi_attrib.current_cpu = cpu_physical_id(dest_cpu);
+ &address_lo);
+
+ msi_ops->target(vector, dest_cpu, &address_hi, &address_lo);
+
+ pci_write_config_dword(entry->dev, msi_upper_address_reg(pos),
+ address_hi);
pci_write_config_dword(entry->dev, msi_lower_address_reg(pos),
- address.lo_address.value);
+ address_lo);
set_native_irq_info(irq, cpu_mask);
break;
}
case PCI_CAP_ID_MSIX:
{
- int offset = entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
- PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET;
+ int offset_hi =
+ entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
+ PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET;
+ int offset_lo =
+ entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
+ PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET;
+
+ address_hi = readl(entry->mask_base + offset_hi);
+ address_lo = readl(entry->mask_base + offset_lo);
- address.lo_address.value = readl(entry->mask_base + offset);
- address.lo_address.value &= MSI_ADDRESS_DEST_ID_MASK;
- address.lo_address.value |= (cpu_physical_id(dest_cpu) <<
- MSI_TARGET_CPU_SHIFT);
- entry->msi_attrib.current_cpu = cpu_physical_id(dest_cpu);
- writel(address.lo_address.value, entry->mask_base + offset);
+ msi_ops->target(vector, dest_cpu, &address_hi, &address_lo);
+
+ writel(address_hi, entry->mask_base + offset_hi);
+ writel(address_lo, entry->mask_base + offset_lo);
set_native_irq_info(irq, cpu_mask);
break;
}
@@ -251,30 +266,6 @@
.set_affinity = set_msi_affinity
};
-static void msi_data_init(struct msg_data *msi_data,
- unsigned int vector)
-{
- memset(msi_data, 0, sizeof(struct msg_data));
- msi_data->vector = (u8)vector;
- msi_data->delivery_mode = MSI_DELIVERY_MODE;
- msi_data->level = MSI_LEVEL_MODE;
- msi_data->trigger = MSI_TRIGGER_MODE;
-}
-
-static void msi_address_init(struct msg_address *msi_address)
-{
- unsigned int dest_id;
- unsigned long dest_phys_id = cpu_physical_id(MSI_TARGET_CPU);
-
- memset(msi_address, 0, sizeof(struct msg_address));
- msi_address->hi_address = (u32)0;
- dest_id = (MSI_ADDRESS_HEADER << MSI_ADDRESS_HEADER_SHIFT);
- msi_address->lo_address.u.dest_mode = MSI_PHYSICAL_MODE;
- msi_address->lo_address.u.redirection_hint = MSI_REDIRECTION_HINT_MODE;
- msi_address->lo_address.u.dest_id = dest_id;
- msi_address->lo_address.value |= (dest_phys_id << MSI_TARGET_CPU_SHIFT);
-}
-
static int msi_free_vector(struct pci_dev* dev, int vector, int reassign);
static int assign_msi_vector(void)
{
@@ -369,6 +360,20 @@
return status;
}
+ if ((status = msi_arch_init()) < 0) {
+ pci_msi_enable = 0;
+ printk(KERN_WARNING
+ "PCI: MSI arch init failed. MSI disabled.\n");
+ return status;
+ }
+
+ if (! msi_ops) {
+ printk(KERN_WARNING
+ "PCI: MSI ops not registered. MSI disabled.\n");
+ status = -EINVAL;
+ return status;
+ }
+
if ((status = msi_cache_init()) < 0) {
pci_msi_enable = 0;
printk(KERN_WARNING "PCI: MSI cache init failed\n");
@@ -514,9 +519,11 @@
**/
static int msi_capability_init(struct pci_dev *dev)
{
+ int status;
struct msi_desc *entry;
- struct msg_address address;
- struct msg_data data;
+ u32 address_lo;
+ u32 address_hi;
+ u32 data;
int pos, vector;
u16 control;
@@ -543,23 +550,27 @@
entry->mask_base = (void __iomem *)(long)msi_mask_bits_reg(pos,
is_64bit_address(control));
}
+ /* Configure MSI capability structure */
+ status = msi_ops->setup(dev, vector,
+ &address_hi,
+ &address_lo,
+ &data);
+ if (status < 0) {
+ dev->irq = entry->msi_attrib.default_vector;
+ kmem_cache_free(msi_cachep, entry);
+ return status;
+ }
/* Replace with MSI handler */
irq_handler_init(PCI_CAP_ID_MSI, vector, entry->msi_attrib.maskbit);
- /* Configure MSI capability structure */
- msi_address_init(&address);
- msi_data_init(&data, vector);
- entry->msi_attrib.current_cpu = ((address.lo_address.u.dest_id >>
- MSI_TARGET_CPU_SHIFT) & MSI_TARGET_CPU_MASK);
- pci_write_config_dword(dev, msi_lower_address_reg(pos),
- address.lo_address.value);
+
+ pci_write_config_dword(dev, msi_lower_address_reg(pos), address_lo);
if (is_64bit_address(control)) {
pci_write_config_dword(dev,
- msi_upper_address_reg(pos), address.hi_address);
- pci_write_config_word(dev,
- msi_data_reg(pos, 1), *((u32*)&data));
+ msi_upper_address_reg(pos), address_hi);
+ pci_write_config_word(dev, msi_data_reg(pos, 1), data);
} else
- pci_write_config_word(dev,
- msi_data_reg(pos, 0), *((u32*)&data));
+ pci_write_config_word(dev, msi_data_reg(pos, 0), data);
+
if (entry->msi_attrib.maskbit) {
unsigned int maskbits, temp;
/* All MSIs are unmasked by default, Mask them all */
@@ -594,13 +605,15 @@
struct msix_entry *entries, int nvec)
{
struct msi_desc *head = NULL, *tail = NULL, *entry = NULL;
- struct msg_address address;
- struct msg_data data;
+ u32 address_hi;
+ u32 address_lo;
+ u32 data;
int vector, pos, i, j, nr_entries, temp = 0;
u32 phys_addr, table_offset;
u16 control;
u8 bir;
void __iomem *base;
+ int status;
pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
/* Request & Map MSI-X table region */
@@ -647,18 +660,20 @@
/* Replace with MSI-X handler */
irq_handler_init(PCI_CAP_ID_MSIX, vector, 1);
/* Configure MSI-X capability structure */
- msi_address_init(&address);
- msi_data_init(&data, vector);
- entry->msi_attrib.current_cpu =
- ((address.lo_address.u.dest_id >>
- MSI_TARGET_CPU_SHIFT) & MSI_TARGET_CPU_MASK);
- writel(address.lo_address.value,
+ status = msi_ops->setup(dev, vector,
+ &address_hi,
+ &address_lo,
+ &data);
+ if (status < 0)
+ break;
+
+ writel(address_lo,
base + j * PCI_MSIX_ENTRY_SIZE +
PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET);
- writel(address.hi_address,
+ writel(address_hi,
base + j * PCI_MSIX_ENTRY_SIZE +
PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET);
- writel(*(u32*)&data,
+ writel(data,
base + j * PCI_MSIX_ENTRY_SIZE +
PCI_MSIX_ENTRY_DATA_OFFSET);
attach_msi_entry(entry, vector);
@@ -793,6 +808,8 @@
void __iomem *base;
unsigned long flags;
+ msi_ops->teardown(vector);
+
spin_lock_irqsave(&msi_lock, flags);
entry = msi_desc[vector];
if (!entry || entry->dev != dev) {
Index: linux-2.6.16/include/asm-i386/msi.h
===================================================================
--- linux-2.6.16.orig/include/asm-i386/msi.h 2006-03-21 11:13:59.727116189 -0600
+++ linux-2.6.16/include/asm-i386/msi.h 2006-03-21 11:14:06.213785721 -0600
@@ -12,4 +12,12 @@
#define LAST_DEVICE_VECTOR 232
#define MSI_TARGET_CPU_SHIFT 12
+extern struct msi_ops msi_apic_ops;
+
+static inline int msi_arch_init(void)
+{
+ msi_register(&msi_apic_ops);
+ return 0;
+}
+
#endif /* ASM_MSI_H */
Index: linux-2.6.16/include/asm-x86_64/msi.h
===================================================================
--- linux-2.6.16.orig/include/asm-x86_64/msi.h 2006-03-21 11:13:59.728092656 -0600
+++ linux-2.6.16/include/asm-x86_64/msi.h 2006-03-21 11:14:06.214762188 -0600
@@ -13,4 +13,12 @@
#define LAST_DEVICE_VECTOR 232
#define MSI_TARGET_CPU_SHIFT 12
+extern struct msi_ops msi_apic_ops;
+
+static inline int msi_arch_init(void)
+{
+ msi_register(&msi_apic_ops);
+ return 0;
+}
+
#endif /* ASM_MSI_H */
Index: linux-2.6.16/include/asm-ia64/machvec.h
===================================================================
--- linux-2.6.16.orig/include/asm-ia64/machvec.h 2006-03-21 11:13:59.728092656 -0600
+++ linux-2.6.16/include/asm-ia64/machvec.h 2006-03-21 11:14:57.089663570 -0600
@@ -74,6 +74,7 @@
typedef unsigned short ia64_mv_readw_relaxed_t (const volatile void __iomem *);
typedef unsigned int ia64_mv_readl_relaxed_t (const volatile void __iomem *);
typedef unsigned long ia64_mv_readq_relaxed_t (const volatile void __iomem *);
+typedef int ia64_mv_msi_init_t (void);
static inline void
machvec_noop (void)
@@ -146,6 +147,7 @@
# define platform_readw_relaxed ia64_mv.readw_relaxed
# define platform_readl_relaxed ia64_mv.readl_relaxed
# define platform_readq_relaxed ia64_mv.readq_relaxed
+# define platform_msi_init ia64_mv.msi_init
# endif
/* __attribute__((__aligned__(16))) is required to make size of the
@@ -194,6 +196,7 @@
ia64_mv_readw_relaxed_t *readw_relaxed;
ia64_mv_readl_relaxed_t *readl_relaxed;
ia64_mv_readq_relaxed_t *readq_relaxed;
+ ia64_mv_msi_init_t *msi_init;
} __attribute__((__aligned__(16))); /* align attrib? see above comment */
#define MACHVEC_INIT(name) \
@@ -238,6 +241,7 @@
platform_readw_relaxed, \
platform_readl_relaxed, \
platform_readq_relaxed, \
+ platform_msi_init, \
}
extern struct ia64_machine_vector ia64_mv;
@@ -386,5 +390,8 @@
#ifndef platform_readq_relaxed
# define platform_readq_relaxed __ia64_readq_relaxed
#endif
+#ifndef platform_msi_init
+# define platform_msi_init ((ia64_mv_msi_init_t*)NULL)
+#endif
#endif /* _ASM_IA64_MACHVEC_H */
Index: linux-2.6.16/include/asm-ia64/machvec_sn2.h
===================================================================
--- linux-2.6.16.orig/include/asm-ia64/machvec_sn2.h 2006-03-21 11:13:59.728092656 -0600
+++ linux-2.6.16/include/asm-ia64/machvec_sn2.h 2006-03-21 13:26:22.138073104 -0600
@@ -66,6 +66,7 @@
extern ia64_mv_dma_sync_sg_for_device sn_dma_sync_sg_for_device;
extern ia64_mv_dma_mapping_error sn_dma_mapping_error;
extern ia64_mv_dma_supported sn_dma_supported;
+extern ia64_mv_msi_init_t sn_msi_init;
/*
* This stuff has dual use!
@@ -115,6 +116,11 @@
#define platform_dma_sync_sg_for_device sn_dma_sync_sg_for_device
#define platform_dma_mapping_error sn_dma_mapping_error
#define platform_dma_supported sn_dma_supported
+#ifdef CONFIG_PCI_MSI
+#define platform_msi_init sn_msi_init
+#else
+#define platform_msi_init ((ia64_mv_msi_init_t*)NULL)
+#endif
#include <asm/sn/io.h>
Index: linux-2.6.16/include/asm-ia64/msi.h
===================================================================
--- linux-2.6.16.orig/include/asm-ia64/msi.h 2006-03-21 11:13:59.729069123 -0600
+++ linux-2.6.16/include/asm-ia64/msi.h 2006-03-21 11:14:06.217691588 -0600
@@ -14,4 +14,16 @@
#define ack_APIC_irq ia64_eoi
#define MSI_TARGET_CPU_SHIFT 4
+extern struct msi_ops msi_apic_ops;
+
+static inline int msi_arch_init(void)
+{
+ if (platform_msi_init)
+ return platform_msi_init();
+
+ /* default ops for most ia64 platforms */
+ msi_register(&msi_apic_ops);
+ return 0;
+}
+
#endif /* ASM_MSI_H */
Index: linux-2.6.16/drivers/pci/Makefile
===================================================================
--- linux-2.6.16.orig/drivers/pci/Makefile 2006-03-21 11:13:59.726139722 -0600
+++ linux-2.6.16/drivers/pci/Makefile 2006-03-21 11:14:06.217691588 -0600
@@ -26,7 +26,11 @@
obj-$(CONFIG_PPC64) += setup-bus.o
obj-$(CONFIG_MIPS) += setup-bus.o setup-irq.o
obj-$(CONFIG_X86_VISWS) += setup-irq.o
-obj-$(CONFIG_PCI_MSI) += msi.o
+
+msiobj-y := msi.o msi-apic.o
+msiobj-$(CONFIG_IA64_GENERIC) += msi-altix.o
+msiobj-$(CONFIG_IA64_SGI_SN2) += msi-altix.o
+obj-$(CONFIG_PCI_MSI) += $(msiobj-y)
#
# ACPI Related PCI FW Functions
Index: linux-2.6.16/drivers/pci/msi-apic.c
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ linux-2.6.16/drivers/pci/msi-apic.c 2006-03-21 11:14:06.220620989 -0600
@@ -0,0 +1,100 @@
+/*
+ * MSI hooks for standard x86 apic
+ */
+
+#include <linux/pci.h>
+#include <linux/irq.h>
+
+#include "msi.h"
+
+/*
+ * Shifts for APIC-based data
+ */
+
+#define MSI_DATA_VECTOR_SHIFT 0
+#define MSI_DATA_VECTOR(v) (((u8)v) << MSI_DATA_VECTOR_SHIFT)
+
+#define MSI_DATA_DELIVERY_SHIFT 8
+#define MSI_DATA_DELIVERY_FIXED (0 << MSI_DATA_DELIVERY_SHIFT)
+#define MSI_DATA_DELIVERY_LOWPRI (1 << MSI_DATA_DELIVERY_SHIFT)
+
+#define MSI_DATA_LEVEL_SHIFT 14
+#define MSI_DATA_LEVEL_DEASSERT (0 << MSI_DATA_LEVEL_SHIFT)
+#define MSI_DATA_LEVEL_ASSERT (1 << MSI_DATA_LEVEL_SHIFT)
+
+#define MSI_DATA_TRIGGER_SHIFT 15
+#define MSI_DATA_TRIGGER_EDGE (0 << MSI_DATA_TRIGGER_SHIFT)
+#define MSI_DATA_TRIGGER_LEVEL (1 << MSI_DATA_TRIGGER_SHIFT)
+
+/*
+ * Shift/mask fields for APIC-based bus address
+ */
+
+#define MSI_ADDR_HEADER 0xfee00000
+
+#define MSI_ADDR_DESTID_MASK 0xfff0000f
+#define MSI_ADDR_DESTID_CPU(cpu) ((cpu) << MSI_TARGET_CPU_SHIFT)
+
+#define MSI_ADDR_DESTMODE_SHIFT 2
+#define MSI_ADDR_DESTMODE_PHYS (0 << MSI_ADDR_DESTMODE_SHIFT)
+#define MSI_ADDR_DESTMODE_LOGIC (1 << MSI_ADDR_DESTMODE_SHIFT)
+
+#define MSI_ADDR_REDIRECTION_SHIFT 3
+#define MSI_ADDR_REDIRECTION_CPU (0 << MSI_ADDR_REDIRECTION_SHIFT)
+#define MSI_ADDR_REDIRECTION_LOWPRI (1 << MSI_ADDR_REDIRECTION_SHIFT)
+
+
+static void
+msi_target_apic(unsigned int vector,
+ unsigned int dest_cpu,
+ u32 *address_hi, /* in/out */
+ u32 *address_lo) /* in/out */
+{
+ u32 addr = *address_lo;
+
+ addr &= MSI_ADDR_DESTID_MASK;
+ addr |= MSI_ADDR_DESTID_CPU(cpu_physical_id(dest_cpu));
+
+ *address_lo = addr;
+}
+
+static int
+msi_setup_apic(struct pci_dev *pdev, /* unused in generic */
+ unsigned int vector,
+ u32 *address_hi,
+ u32 *address_lo,
+ u32 *data)
+{
+ unsigned long dest_phys_id;
+
+ dest_phys_id = cpu_physical_id(first_cpu(cpu_online_map));
+
+ *address_hi = 0;
+ *address_lo = MSI_ADDR_HEADER |
+ MSI_ADDR_DESTMODE_PHYS |
+ MSI_ADDR_REDIRECTION_CPU |
+ MSI_ADDR_DESTID_CPU(dest_phys_id);
+
+ *data = MSI_DATA_TRIGGER_EDGE |
+ MSI_DATA_LEVEL_ASSERT |
+ MSI_DATA_DELIVERY_FIXED |
+ MSI_DATA_VECTOR(vector);
+
+ return 0;
+}
+
+static void
+msi_teardown_apic(unsigned int vector)
+{
+ return; /* no-op */
+}
+
+/*
+ * Generic ops used on most IA archs/platforms. Set with msi_register()
+ */
+
+struct msi_ops msi_apic_ops = {
+ .setup = msi_setup_apic,
+ .teardown = msi_teardown_apic,
+ .target = msi_target_apic,
+};
Index: linux-2.6.16/drivers/pci/msi.h
===================================================================
--- linux-2.6.16.orig/drivers/pci/msi.h 2006-03-21 11:13:59.727116189 -0600
+++ linux-2.6.16/drivers/pci/msi.h 2006-03-21 11:14:06.223550390 -0600
@@ -6,6 +6,68 @@
#ifndef MSI_H
#define MSI_H
+/*
+ * MSI operation vector. Used by the msi core code (drivers/pci/msi.c)
+ * to abstract platform-specific tasks relating to MSI address generation
+ * and resource management.
+ */
+struct msi_ops {
+ /**
+ * setup - generate an MSI bus address and data for a given vector
+ * @pdev: PCI device context (in)
+ * @vector: vector allocated by the msi core (in)
+ * @addr_hi: upper 32 bits of PCI bus MSI address (out)
+ * @addr_lo: lower 32 bits of PCI bus MSI address (out)
+ * @data: MSI data payload (out)
+ *
+ * Description: The setup op is used to generate a PCI bus addres and
+ * data which the msi core will program into the card MSI capability
+ * registers. The setup routine is responsible for picking an initial
+ * cpu to target the MSI at. The setup routine is responsible for
+ * examining pdev to determine the MSI capabilities of the card and
+ * generating a suitable address/data. The setup routine is
+ * responsible for allocating and tracking any system resources it
+ * needs to route the MSI to the cpu it picks, and for associating
+ * those resources with the passed in vector.
+ *
+ * Returns 0 if the MSI address/data was successfully setup.
+ **/
+
+ int (*setup) (struct pci_dev *pdev, unsigned int vector,
+ u32 *addr_hi, u32 *addr_lo, u32 *data);
+
+ /**
+ * teardown - release resources allocated by setup
+ * @vector: vector context for resources (in)
+ *
+ * Description: The teardown op is used to release any resources
+ * that were allocated in the setup routine associated with the passed
+ * in vector.
+ **/
+
+ void (*teardown) (unsigned int vector);
+
+ /**
+ * target - retarget an MSI at a different cpu
+ * @vector: vector context for resources (in)
+ * @cpu: new cpu to direct vector at (in)
+ * @addr_hi: new value of PCI bus upper 32 bits (in/out)
+ * @addr_lo: new value of PCI bus lower 32 bits (in/out)
+ *
+ * Description: The target op is used to redirect an MSI vector
+ * at a different cpu. addr_hi/addr_lo coming in are the existing
+ * values that the MSI core has programmed into the card. The
+ * target code is responsible for freeing any resources (if any)
+ * associated with the old address, and generating a new PCI bus
+ * addr_hi/addr_lo that will redirect the vector at the indicated cpu.
+ **/
+
+ void (*target) (unsigned int vector, unsigned int cpu,
+ u32 *addr_hi, u32 *addr_lo);
+};
+
+extern int msi_register(struct msi_ops *ops);
+
#include <asm/msi.h>
/*
@@ -63,67 +125,6 @@
#define msix_mask(address) (address | PCI_MSIX_FLAGS_BITMASK)
#define msix_is_pending(address) (address & PCI_MSIX_FLAGS_PENDMASK)
-/*
- * MSI Defined Data Structures
- */
-#define MSI_ADDRESS_HEADER 0xfee
-#define MSI_ADDRESS_HEADER_SHIFT 12
-#define MSI_ADDRESS_HEADER_MASK 0xfff000
-#define MSI_ADDRESS_DEST_ID_MASK 0xfff0000f
-#define MSI_TARGET_CPU_MASK 0xff
-#define MSI_DELIVERY_MODE 0
-#define MSI_LEVEL_MODE 1 /* Edge always assert */
-#define MSI_TRIGGER_MODE 0 /* MSI is edge sensitive */
-#define MSI_PHYSICAL_MODE 0
-#define MSI_LOGICAL_MODE 1
-#define MSI_REDIRECTION_HINT_MODE 0
-
-struct msg_data {
-#if defined(__LITTLE_ENDIAN_BITFIELD)
- __u32 vector : 8;
- __u32 delivery_mode : 3; /* 000b: FIXED | 001b: lowest prior */
- __u32 reserved_1 : 3;
- __u32 level : 1; /* 0: deassert | 1: assert */
- __u32 trigger : 1; /* 0: edge | 1: level */
- __u32 reserved_2 : 16;
-#elif defined(__BIG_ENDIAN_BITFIELD)
- __u32 reserved_2 : 16;
- __u32 trigger : 1; /* 0: edge | 1: level */
- __u32 level : 1; /* 0: deassert | 1: assert */
- __u32 reserved_1 : 3;
- __u32 delivery_mode : 3; /* 000b: FIXED | 001b: lowest prior */
- __u32 vector : 8;
-#else
-#error "Bitfield endianness not defined! Check your byteorder.h"
-#endif
-} __attribute__ ((packed));
-
-struct msg_address {
- union {
- struct {
-#if defined(__LITTLE_ENDIAN_BITFIELD)
- __u32 reserved_1 : 2;
- __u32 dest_mode : 1; /*0:physic | 1:logic */
- __u32 redirection_hint: 1; /*0: dedicated CPU
- 1: lowest priority */
- __u32 reserved_2 : 4;
- __u32 dest_id : 24; /* Destination ID */
-#elif defined(__BIG_ENDIAN_BITFIELD)
- __u32 dest_id : 24; /* Destination ID */
- __u32 reserved_2 : 4;
- __u32 redirection_hint: 1; /*0: dedicated CPU
- 1: lowest priority */
- __u32 dest_mode : 1; /*0:physic | 1:logic */
- __u32 reserved_1 : 2;
-#else
-#error "Bitfield endianness not defined! Check your byteorder.h"
-#endif
- }u;
- __u32 value;
- }lo_address;
- __u32 hi_address;
-} __attribute__ ((packed));
-
struct msi_desc {
struct {
__u8 type : 5; /* {0: unused, 5h:MSI, 11h:MSI-X} */
@@ -132,7 +133,7 @@
__u8 reserved: 1; /* reserved */
__u8 entry_nr; /* specific enabled entry */
__u8 default_vector; /* default pre-assigned vector */
- __u8 current_cpu; /* current destination cpu */
+ __u8 unused; /* formerly unused destination cpu*/
}msi_attrib;
struct {
Index: linux-2.6.16/drivers/pci/msi-altix.c
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ linux-2.6.16/drivers/pci/msi-altix.c 2006-03-21 11:14:06.229409191 -0600
@@ -0,0 +1,18 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2006 Silicon Graphics, Inc. All Rights Reserved.
+ */
+
+#include <asm/errno.h>
+
+int
+sn_msi_init(void)
+{
+ /*
+ * return error until MSI is supported on altix platforms
+ */
+ return -EINVAL;
+}
^ permalink raw reply
* [Fwd: Re: make install on ppc]
From: Hans Fugal @ 2006-03-21 14:08 UTC (permalink / raw)
To: linuxppc-dev
[-- Attachment #1: Type: text/plain, Size: 76 bytes --]
Is there something that stops us from having a make install target for ppc?
[-- Attachment #2: Re: make install on ppc --]
[-- Type: message/rfc822, Size: 1900 bytes --]
From: Sam Ravnborg <sam@ravnborg.org>
To: Hans Fugal <hans@fugal.net>
Cc: kai@germaschewski.name
Subject: Re: make install on ppc
Date: Tue, 21 Mar 2006 07:29:43 +0100
Message-ID: <20060321062943.GA3677@mars.ravnborg.org>
On Sat, Mar 18, 2006 at 05:19:19PM -0700, Hans Fugal wrote:
> I apologize if you are not the right people to send this to. On i386
> there is a make install target, but on ppc there is not. The
> distribution is Debian in both cases, and the sources are plain vanilla.
>
> Is this an oversight?
This is up to the arch maintainers to add as required.
Please ask the at relevant ppc mailing list.
Sam
^ permalink raw reply
* Re: [PATCH] powerpc: Add FSL SEC node to documentation
From: Paul Nasrat @ 2006-03-21 21:23 UTC (permalink / raw)
To: Hollis Blanchard; +Cc: linuxppc-dev
In-Reply-To: <1142969335.395.6.camel@basalt>
On Tue, 2006-03-21 at 13:28 -0600, Hollis Blanchard wrote:
> On Tue, 2006-03-21 at 12:25 -0600, Kumar Gala wrote:
> > On Mar 20, 2006, at 8:14 PM, Hollis Blanchard wrote:
> > > Have you consulted with any other vendors regarding these
> > > properties? I know
> > > there is no IEEE1275 binding for these sorts of devices, but we can
> > > at least
> > > attempt to standardize it (even in the absence of the Open Firmware
> > > Working
> > > Group)...
> >
> > Beyond the device_type, I'm not sure if there is much more one could
> > standardize one. The other fields that Kim spec'd are either generic
> > OF fields (reg, interrupts, etc.) or specific to the Freescale devices.
>
> The device_type and compatible properties are exactly what I'm talking
> about.
The Working Group lists still exist but are pretty dead. I agree we
really want to ensure that both OF based and dtc based new hardware is
consistent. I'm not sure how we want to do this, but we can document in
Documentation and then use eg SLOF to mock out the OF interfaces and
create proposals and kick some life into the OF working group.
Paul
^ permalink raw reply
* Re: [PATCH 0/3] msi abstractions and support for altix
From: David S. Miller @ 2006-03-21 21:53 UTC (permalink / raw)
To: maule
Cc: tony.luck, linux-ia64, gregkh, linux-kernel, j-nomura,
linuxppc64-dev, linux-pci
In-Reply-To: <20060321143444.9913.48372.11324@lnx-maule.americas.sgi.com>
From: Mark Maule <maule@sgi.com>
Date: Tue, 21 Mar 2006 08:34:44 -0600 (CST)
> Mark
>
> 1/3 msi-ops.patch
> Add an msi_arch_init() hook which can be used to perform platform
> specific setup prior to msi use.
>
> Define a set of msi ops to implement the platform-specific tasks:
>
> setup - set up plumbing to get a vector directed at a default
> cpu, and return the corresponding MSI bus address and data.
> teardown - inverse of msi_setup
> target - retarget a vector to a given cpu
>
> Define the routine msi_register() called from msi_arch_init()
> to set the desired ops.
>
> Move a bunch of apic-specific code out of the msi core .h/.c and
> into a new msi-apic.c file.
Mark, thanks for doing this work. The better abstracted out the
so-called generic MSI support code is, the better. Several platforms
will benefit from this, such as PPC and Sparc64, both of which
cannot take advantage of MSI support in their PCI controllers because
of how x86 centric the current MSI support layer is.
Thanks again.
^ permalink raw reply
* Emulating button 3 on 2 button ADB mice.
From: Nick Vetter @ 2006-03-21 21:56 UTC (permalink / raw)
To: linuxppc-dev
[-- Attachment #1: Type: text/plain, Size: 921 bytes --]
Dear Sir: do you have a patch for this kensington orbit trackball mouse that
I can use with Debian? If so I will post it in the pmac-Linux-nubus-users
group at the Glist site in source forge.
I would also like to use it for my old powerbook 1400c which is running
debian sarge.
Thanks
Nick
_______________________________________
NOTICE OF CONFIDENTIALITY: The information contained in this e-mail is intended only for the use of the individual or entity to which it is addressed and it may contain information that is privileged, confidential and exempt from disclosure under applicable law. If you are not the intended recipient of this e-mail message, you are hereby notified that any disclosure, dissemination or copying of this communication is strictly prohibited. If you received this communication in error, please notify and delete the original message. Thank you for your cooperation.
[-- Attachment #2: Type: text/html, Size: 1921 bytes --]
^ permalink raw reply
* Re: [PATCH 7/7] powerpc numa: Consolidate assignment of cpus to nodes
From: Michael Ellerman @ 2006-03-21 23:09 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Nathan Lynch
In-Reply-To: <1142968571.27114.28.camel@pants.austin.ibm.com>
[-- Attachment #1: Type: text/plain, Size: 782 bytes --]
On Wed, 22 Mar 2006 06:16, Nathan Lynch wrote:
> On Tue, 2006-03-21 at 10:38 -0800, Dave Hansen wrote:
> > By the way, what do the "l" and "h" in front of "cpu" mean anyway?
>
> "logical" and "hot"? I dunno, just seemed to be the convention in other
> cpu notifiers at the time the code was written.
Ouch, that's unfortunate. In the powerpc code hcpu _usually_ means hard cpu
number, as opposed to logical (lcpu). In this case though it looks like hcpu
holds the logical cpu number, which is a bit icky. That might be worth
fixing.
cheers
--
Michael Ellerman
IBM OzLabs
wwweb: http://michael.ellerman.id.au
phone: +61 2 6212 1183 (tie line 70 21183)
We do not inherit the earth from our ancestors,
we borrow it from our children. - S.M.A.R.T Person
[-- Attachment #2: Type: application/pgp-signature, Size: 189 bytes --]
^ permalink raw reply
* Re: [PATCH 8/11] powerpc: Add strne2a() to convert a string from EBCDIC to ASCII
From: Michael Ellerman @ 2006-03-21 23:25 UTC (permalink / raw)
To: Olof Johansson; +Cc: Paul Mackerras, linuxppc-dev
In-Reply-To: <20060321184358.GB5248@pb15.lixom.net>
[-- Attachment #1: Type: text/plain, Size: 545 bytes --]
On Wed, 22 Mar 2006 05:43, Olof Johansson wrote:
> On Tue, Mar 21, 2006 at 07:32:39PM +0100, Andreas Schwab wrote:
> > Olof Johansson <olof@lixom.net> writes:
> > > Why iterate over the string twice? Why not do
> > > for (..; i < n && src[n]; ...)
> >
> > ITYM i < n && src[i].
>
> Doh, right.
That's why :)
--
Michael Ellerman
IBM OzLabs
wwweb: http://michael.ellerman.id.au
phone: +61 2 6212 1183 (tie line 70 21183)
We do not inherit the earth from our ancestors,
we borrow it from our children. - S.M.A.R.T Person
[-- Attachment #2: Type: application/pgp-signature, Size: 189 bytes --]
^ permalink raw reply
* Re: [PATCH 7/7] powerpc numa: Consolidate assignment of cpus to nodes
From: Nathan Lynch @ 2006-03-21 23:22 UTC (permalink / raw)
To: michael; +Cc: linuxppc-dev
In-Reply-To: <200603221009.19523.michael@ellerman.id.au>
On Wed, 2006-03-22 at 10:09 +1100, Michael Ellerman wrote:
> On Wed, 22 Mar 2006 06:16, Nathan Lynch wrote:
> > On Tue, 2006-03-21 at 10:38 -0800, Dave Hansen wrote:
> > > By the way, what do the "l" and "h" in front of "cpu" mean anyway?
> >
> > "logical" and "hot"? I dunno, just seemed to be the convention in other
> > cpu notifiers at the time the code was written.
>
> Ouch, that's unfortunate. In the powerpc code hcpu _usually_ means hard cpu
> number, as opposed to logical (lcpu).
Grep begs to differ:
$ grep -rw hcpu arch/powerpc include/asm-powerpc
arch/powerpc/kernel/sysfs.c: unsigned long action, void *hcpu)
arch/powerpc/kernel/sysfs.c: unsigned int cpu = (unsigned int)(long)hcpu;
arch/powerpc/mm/numa.c: void *hcpu)
arch/powerpc/mm/numa.c: unsigned long lcpu = (unsigned long)hcpu;
^ permalink raw reply
* Re: [PATCH 7/7] powerpc numa: Consolidate assignment of cpus to nodes
From: Michael Ellerman @ 2006-03-21 23:34 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Nathan Lynch
In-Reply-To: <1142983379.28864.9.camel@pants.austin.ibm.com>
[-- Attachment #1: Type: text/plain, Size: 1332 bytes --]
On Wed, 22 Mar 2006 10:22, Nathan Lynch wrote:
> On Wed, 2006-03-22 at 10:09 +1100, Michael Ellerman wrote:
> > On Wed, 22 Mar 2006 06:16, Nathan Lynch wrote:
> > > On Tue, 2006-03-21 at 10:38 -0800, Dave Hansen wrote:
> > > > By the way, what do the "l" and "h" in front of "cpu" mean anyway?
> > >
> > > "logical" and "hot"? I dunno, just seemed to be the convention in
> > > other cpu notifiers at the time the code was written.
> >
> > Ouch, that's unfortunate. In the powerpc code hcpu _usually_ means hard
> > cpu number, as opposed to logical (lcpu).
>
> Grep begs to differ:
>
> $ grep -rw hcpu arch/powerpc include/asm-powerpc
> arch/powerpc/kernel/sysfs.c: unsigned long
> action, void *hcpu) arch/powerpc/kernel/sysfs.c: unsigned int cpu =
> (unsigned int)(long)hcpu; arch/powerpc/mm/numa.c: void
> *hcpu)
> arch/powerpc/mm/numa.c: unsigned long lcpu = (unsigned long)hcpu;
You're right, it's actually a mixture of pcpu, hw_cpuid, hardid etc. So there
should be no confusion by using hcpu for "hot" cpu.
cheers
--
Michael Ellerman
IBM OzLabs
wwweb: http://michael.ellerman.id.au
phone: +61 2 6212 1183 (tie line 70 21183)
We do not inherit the earth from our ancestors,
we borrow it from our children. - S.M.A.R.T Person
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^ permalink raw reply
* Running Linux 2.6.16 and Xorg 7.0 on iMac G5 rev C (iSight)
From: Étienne Bersac @ 2006-03-22 0:11 UTC (permalink / raw)
To: Linuxppc-dev, debian-powerpc, ubuntu-devel
Hello,
With the great help of Benjamin Herrenschmidt, i reach to run linux =20
and Xorg on an iMac G5 rev C 20" (the iSight line) with an Ati Radeon =20=
X600 XT Pro (RV380). Make your backup ! You should verify each file i =20=
ship with this howto. Conf files are available at http://=20
bersace03.free.fr/pub/Linux/iMac%20G5/.
You need at least a 2.6.15-rc1 kernel, a Mac OS X installation and an =20=
install cd. (I use an ubuntu one). I advice you to make a place for =20
linux before installation.
- Get Ben's kernel at http://bersace03.free.fr/pub/iMac%20G5/=20
vmlinux.bz2 (mirror of http://gate.crashing.org/~benh/vmlinux.bz2). =20
bunzip2 it at /.
- Copy install/yaboot and initrd.gz from the installer to /. Rename =20=
initrd.gz to initrd-cd.gz. Copy yaboot.conf from the website to /. I =20
assume you will install linux in /dev/sda5, if this is not the case, =20
edit yaboot.conf
- Insert your cd. It's time to reboot !
- Type Option+Command+O+F at boot time. This should open the OF =20
terminal.
- Type "boot hd:X,yaboot" where X is the number of the Mac OS X =20
volume (often 3). Remember this each time you have to use yaboot =20
while we have not run "ybin".
- Choose the "cd" label at yaboot prompt. First questions should =20
arrives such as language, country, etc. Then the installation should =20
go on.
- Reboot at the end of the installation, using yaboot from OF prompt.
- Choose the "rescue" label to boot. Copy the installed initrd.gz =20
to your Macintosh Volume, using an usb key/hd/whatever you want. Copy =20=
this initrd.gz as /initrd-hd.gz at root of your Macintosh Volume. =20
Here you may have to change the /yaboot.conf to reflect the =20
installation (especially the root=3D/dev/sda5 option). This might be =20
possible to run ybin here, but i'm not sure.
- Disable the display manager (e.g. update-rc.d -f gdm remove).
- Now it's time to boot the installed system, still using ben's =20
kernel. Choose the "hd" label at yaboot prompt. Once your system is =20
booted, configure network (network-manager work fine), install build-=20
essential and other good stuffs like kernel-package and fakeroot. Get =20=
the source ! 2.6.16 is fine. use g5_defconfig as .config and compile =20
the kernel.
- Modify /etc/yaboot.conf, add an entry for your kernel and set it =20
as default (of course), add macosx option, etc.. When you are sure, =20
run ybin. Now you don't need OF prompt anymore.
- You may want to restart, but we can continue.
Next step is xorg. You need a special branch of the ati driver for =20
xorg. Thanks to the new modular Xorg :)
- Install automake-1.7, x11proto-*, xserver-xorg-dev, xlibs-dev and =20=
other stuff you may need to compile this. ./configure will help you. =20
The CVSROOT is :pserver:anoncvs@cvs.freedesktop.org:/cvs/xorg . I =20
install stuff with --prefix=3D/usr.
- Checkout and install util/macros.
- Use ati-1-0-branch branch of the ati driver ( http://=20
webcvs.freedesktop.org/xorg/driver/xf86-video-ati/?=20
only_with_tag=3Dati-1-0-branch ). Checkout and install it.
- Use the xorg.conf available at http://bersace03.free.fr/pub/Linux/=20=
iMac%20G5/xorg.conf . I own an iMac G5 20", so if you have the 17" =20
one, you must use the result of 'parse-edid $(find /proc/device-tree -=20=
name EDID)' as Screen Section, and use the resolution from xresprobe =20=
radeon in the PanelSize option of the Device Section. You should =20
check xorg.conf and track error.
- Pray and run your display manager (e.g. invocke-rc.d gdm start). =20
If you are lucky, you will see the charming waiting cursor and then =20
the dm prompt. Eur=EAka !!
- If it work, enable your diplays manager with z.B. dpkg-=20
reconfigure gdm.
OR
- If you get a blank screen, try to play with radeon(4) options in =20
xorg.conf. Send feedbacks. Blank screen seems to mean that you won't =20
see anything while you do not reboot the box. This is where ssh is =20
usefull.
This is the end of this howto.
I had had some difficulties to write this howto because i did the two =20=
step with several weeks and a lot of failures between them . So i =20
might have forgottent some important points. Please send feedbacks.
I really want to thank Benjamin Herrenschmidt who helps me several =20
times and does great work to support those computers. Merci Benjamin !
=C9tienne.
^ permalink raw reply
* Re: [RFC/PATCH] powerpc: Make BUG_ON & WARN_ON play nice with compile-time optimisations
From: Stephen Rothwell @ 2006-03-22 0:16 UTC (permalink / raw)
To: Michael Ellerman; +Cc: linuxppc-dev, paulus
In-Reply-To: <20060321055203.EF12167A39@ozlabs.org>
[-- Attachment #1: Type: text/plain, Size: 504 bytes --]
On Tue, 21 Mar 2006 16:51:29 +1100 Michael Ellerman <michael@ellerman.id.au> wrote:
>
> Although we could do this. It relys on firmware_has_feature() being a macro,
> but perhaps that's ok. This isn't exactly ideal, as it encourages us to use
> macros where we could otherwise use static inlines, but perhaps it's ok.
In this case the macros are small and the overall effect looks good.
--
Cheers,
Stephen Rothwell sfr@canb.auug.org.au
http://www.canb.auug.org.au/~sfr/
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^ permalink raw reply
* [PATCH] powerpc: update mailing list addresses
From: Stephen Rothwell @ 2006-03-22 0:26 UTC (permalink / raw)
To: paulus; +Cc: linuxppc-dev
In-Reply-To: <96AB6792-D07B-4E5D-B43F-5D2D233B1131@kernel.crashing.org>
Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
---
Documentation/powerpc/hvcs.txt | 4 ++--
MAINTAINERS | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
--
Cheers,
Stephen Rothwell sfr@canb.auug.org.au
http://www.canb.auug.org.au/~sfr/
0e626f91110ad84ae04809aec8a9458c6bdf3c64
diff --git a/Documentation/powerpc/hvcs.txt b/Documentation/powerpc/hvcs.txt
index dca75cb..1e38166 100644
--- a/Documentation/powerpc/hvcs.txt
+++ b/Documentation/powerpc/hvcs.txt
@@ -558,9 +558,9 @@ partitions.
The proper channel for reporting bugs is either through the Linux OS
distribution company that provided your OS or by posting issues to the
-ppc64 development mailing list at:
+PowerPC development mailing list at:
-linuxppc64-dev@lists.linuxppc.org
+linuxppc-dev@ozlabs.org
This request is to provide a documented and searchable public exchange
of the problems and solutions surrounding this driver for the benefit of
diff --git a/MAINTAINERS b/MAINTAINERS
index 8db5c33..d8878ca 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -534,7 +534,7 @@ S: Supported
BROADBAND PROCESSOR ARCHITECTURE
P: Arnd Bergmann
M: arnd@arndb.de
-L: linuxppc64-dev@ozlabs.org
+L: linuxppc-dev@ozlabs.org
W: http://linuxppc64.org
S: Supported
@@ -1626,7 +1626,7 @@ P: Anton Blanchard
M: anton@samba.org
M: anton@au.ibm.com
W: http://linuxppc64.org
-L: linuxppc64-dev@ozlabs.org
+L: linuxppc-dev@ozlabs.org
S: Supported
LINUX SECURITY MODULE (LSM) FRAMEWORK
--
1.2.4
^ permalink raw reply related
* Re: [PATCH 4/11] powerpc: Replace platform_is_lpar() with a firmware feature
From: Stephen Rothwell @ 2006-03-22 0:35 UTC (permalink / raw)
To: Michael Ellerman; +Cc: linuxppc-dev, paulus
In-Reply-To: <20060321094630.E7AD067B21@ozlabs.org>
[-- Attachment #1: Type: text/plain, Size: 808 bytes --]
On Tue, 21 Mar 2006 20:45:59 +1100 Michael Ellerman <michael@ellerman.id.au> wrote:
>
> It has been decreed that platform numbers are evil, so as a step in that
> direction, replace platform_is_lpar() with a FW_FEATURE_LPAR bit.
>
> Currently FW_FEATURE_LPAR really means i/pSeries LPAR, in the future we might
> have to clean that up if we need to be more specific about what LPAR actually
> means. But that's another patch ...
>
> Signed-off-by: Michael Ellerman <michael@ellerman.id.au>
Just wondering if you considered just #defining platform_is_lpar() to be
firmware_has_feature(FW_FEATURE_LPAR) ...
Otherwise looks good.
Acked-by: Stephen Rothwell <sfr@canb.auug.org.au>
--
Cheers,
Stephen Rothwell sfr@canb.auug.org.au
http://www.canb.auug.org.au/~sfr/
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^ permalink raw reply
* Re: [PATCH 5/11] powerpc: iseries: mf related cleanups
From: Stephen Rothwell @ 2006-03-22 0:39 UTC (permalink / raw)
To: Michael Ellerman; +Cc: linuxppc-dev, paulus
In-Reply-To: <20060321094632.ADC4467B6B@ozlabs.org>
[-- Attachment #1: Type: text/plain, Size: 495 bytes --]
Hi Michael,
Just some small nits ...
On Tue, 21 Mar 2006 20:46:02 +1100 Michael Ellerman <michael@ellerman.id.au> wrote:
>
> +static int mf_initialized = 0;
We don't generally put the "= 0".
> + mf_initialized = 1;
> + mb();
Do we really need the mb(). If so, a comment saying why would be good.
(Yes, I know that you are just moving code.)
Otherwise looks good.
--
Cheers,
Stephen Rothwell sfr@canb.auug.org.au
http://www.canb.auug.org.au/~sfr/
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^ permalink raw reply
* Re: [PATCH 4/11] powerpc: Replace platform_is_lpar() with a firmware feature
From: Michael Ellerman @ 2006-03-22 0:48 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Stephen Rothwell, paulus
In-Reply-To: <20060322113508.08b07cb4.sfr@canb.auug.org.au>
[-- Attachment #1: Type: text/plain, Size: 1053 bytes --]
On Wed, 22 Mar 2006 11:35, Stephen Rothwell wrote:
> On Tue, 21 Mar 2006 20:45:59 +1100 Michael Ellerman <michael@ellerman.id.au>
wrote:
> > It has been decreed that platform numbers are evil, so as a step in that
> > direction, replace platform_is_lpar() with a FW_FEATURE_LPAR bit.
> >
> > Currently FW_FEATURE_LPAR really means i/pSeries LPAR, in the future we
> > might have to clean that up if we need to be more specific about what
> > LPAR actually means. But that's another patch ...
> >
> > Signed-off-by: Michael Ellerman <michael@ellerman.id.au>
>
> Just wondering if you considered just #defining platform_is_lpar() to be
> firmware_has_feature(FW_FEATURE_LPAR) ...
Thought about it, but decided it was ugly, and obscures what's really
happening, ie. LPAR-ness is just a FW_FEATURE bit.
cheers
--
Michael Ellerman
IBM OzLabs
wwweb: http://michael.ellerman.id.au
phone: +61 2 6212 1183 (tie line 70 21183)
We do not inherit the earth from our ancestors,
we borrow it from our children. - S.M.A.R.T Person
[-- Attachment #2: Type: application/pgp-signature, Size: 189 bytes --]
^ permalink raw reply
* Re: [PATCH] powerpc: Add FSL SEC node to documentation
From: Kim Phillips @ 2006-03-22 1:10 UTC (permalink / raw)
To: Kumar Gala; +Cc: linuxppc-dev
In-Reply-To: <3C6218C3-3FC0-437E-A798-3AD6FEB69713@kernel.crashing.org>
On Tue, 21 Mar 2006 12:21:47 -0600
Kumar Gala <galak@kernel.crashing.org> wrote:
> Drop the part about Most modern... in five years when someone reads
> this it will not be modern anymore.
>
[snip]
>
> ditto about modern.
>
[snip]
>
> Would this be a bit more clear, if you explicitly stated that the
> DESC_TYPE value directly corresponds to the bit encoding, like you
> did for EU_SEL0.
>
[snip]
ok, here's the replacement replacement patch with the above fixes:
Documentation: Added FSL SOC SEC node definition
Updated the documentation to include the definition of the SEC device
node format for Freescale SOC devices.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
---
commit e1e1b8f7d958d7f25a0085ec529a3ebbd6dc1fa5
tree 2e2b12fe07b6d367da4c5609971178838c9321a2
parent 6b0efd3e3b07afc9fc7222066b0b37ecd1d31e44
author Kim Phillips <kim.phillips@freescale.com> Tue, 21 Mar 2006 16:43:16 -0600
committer Kim Phillips <kim.phillips@freescale.com> Tue, 21 Mar 2006 16:43:16 -0600
Documentation/powerpc/booting-without-of.txt | 72 ++++++++++++++++++++++++++
1 files changed, 72 insertions(+), 0 deletions(-)
diff --git a/Documentation/powerpc/booting-without-of.txt b/Documentation/powerpc/booting-without-of.txt
index d02c649..d6626b6 100644
--- a/Documentation/powerpc/booting-without-of.txt
+++ b/Documentation/powerpc/booting-without-of.txt
@@ -1365,6 +1365,78 @@ platforms are moved over to use the flat
};
+ g) Freescale SOC SEC Security Engines
+
+ Required properties:
+
+ - device_type : Should be "crypto"
+ - model : Model of the device. Should be "SEC1" or "SEC2"
+ - compatible : Should be "talitos"
+ - reg : Offset and length of the register set for the device
+ - interrupts : <a b> where a is the interrupt number and b is a
+ field that represents an encoding of the sense and level
+ information for the interrupt. This should be encoded based on
+ the information in section 2) depending on the type of interrupt
+ controller you have.
+ - interrupt-parent : the phandle for the interrupt controller that
+ services interrupts for this device.
+ - num-channels : An integer representing the number of channels
+ available.
+ - channel-fifo-len : An integer representing the number of
+ descriptor pointers each channel fetch fifo can hold.
+ - exec-units-mask : The bitmask representing what execution units
+ (EUs) are available. It's a single 32 bit cell. EU information
+ should be encoded following the SEC's Descriptor Header Dword
+ EU_SEL0 field documentation, i.e. as follows:
+
+ bit 0 = reserved - should be 0
+ bit 1 = set if SEC has the ARC4 EU (AFEU)
+ bit 2 = set if SEC has the DES/3DES EU (DEU)
+ bit 3 = set if SEC has the message digest EU (MDEU)
+ bit 4 = set if SEC has the random number generator EU (RNG)
+ bit 5 = set if SEC has the public key EU (PKEU)
+ bit 6 = set if SEC has the AES EU (AESU)
+ bit 7 = set if SEC has the Kasumi EU (KEU)
+
+ bits 8 through 31 are reserved for future SEC EUs.
+
+ - descriptor-types-mask : The bitmask representing what descriptors
+ are available. It's a single 32 bit cell. Descriptor type
+ information should be encoded following the SEC's Descriptor
+ Header Dword DESC_TYPE field documentation, i.e. as follows:
+
+ bit 0 = set if SEC supports the aesu_ctr_nonsnoop desc. type
+ bit 1 = set if SEC supports the ipsec_esp descriptor type
+ bit 2 = set if SEC supports the common_nonsnoop desc. type
+ bit 3 = set if SEC supports the 802.11i AES ccmp desc. type
+ bit 4 = set if SEC supports the hmac_snoop_no_afeu desc. type
+ bit 5 = set if SEC supports the srtp descriptor type
+ bit 6 = set if SEC supports the non_hmac_snoop_no_afeu desc.type
+ bit 7 = set if SEC supports the pkeu_assemble descriptor type
+ bit 8 = set if SEC supports the aesu_key_expand_output desc.type
+ bit 9 = set if SEC supports the pkeu_ptmul descriptor type
+ bit 10 = set if SEC supports the common_nonsnoop_afeu desc. type
+ bit 11 = set if SEC supports the pkeu_ptadd_dbl descriptor type
+
+ ..and so on and so forth.
+
+ Example:
+
+ /* MPC8548E */
+ crypto@30000 {
+ device_type = "crypto";
+ model = "SEC2";
+ compatible = "talitos";
+ reg = <30000 10000>;
+ interrupts = <1d 3>;
+ interrupt-parent = <40000>;
+ num-channels = <4>;
+ channel-fifo-len = <24>;
+ exec-units-mask = <000000fe>;
+ descriptor-types-mask = <073f1127>;
+ };
+
+
More devices will be defined as this spec matures.
^ permalink raw reply related
* Re: Running Linux 2.6.16 and Xorg 7.0 on iMac G5 rev C (iSight)
From: Benjamin Herrenschmidt @ 2006-03-22 2:03 UTC (permalink / raw)
To: Étienne Bersac; +Cc: Linuxppc-dev, debian-powerpc, ubuntu-devel
In-Reply-To: <82FEFC77-5EDB-4349-B935-AD422913F3F7@laposte.net>
> - Get Ben's kernel at http://bersace03.free.fr/pub/iMac%20G5/
> vmlinux.bz2 (mirror of http://gate.crashing.org/~benh/vmlinux.bz2).
> bunzip2 it at /.
Don't do that ! :)
There is no such thing as benh's kernels :) that's long gone. In fact, I
just removed the above one from the site... it was just a build to help
you. 2.6.16 should work on this machine, if you need a pre-build version
of it, try to get somebody on this list or post yourself one somewhere
but don't spread the idea that there is still such a thing as "benh's
kernel" :)
Ben.
^ permalink raw reply
* Re: [PATCH] powerpc: Add FSL SEC node to documentation
From: Paul Mackerras @ 2006-03-22 4:09 UTC (permalink / raw)
To: Kim Phillips; +Cc: linuxppc-dev
In-Reply-To: <20060321191012.2ef20179.kim.phillips@freescale.com>
Kim Phillips writes:
> ok, here's the replacement replacement patch with the above fixes:
Unfortunately your mailer wrecked the whitespace and it doesn't
apply. Please resend with a better mailer.
Thanks,
Paul.
^ permalink raw reply
* please pull powerpc.git
From: Paul Mackerras @ 2006-03-22 5:28 UTC (permalink / raw)
To: torvalds; +Cc: linuxppc-dev
Linus,
Please do a pull from
git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc.git
to get the PowerPC updates that have been queued up to go into
2.6.17.
Thanks,
Paul.
Adrian Cox:
ppc: Fix platform_notify functions marked __init
Andy Fleming:
powerpc: Add PCI support for 8540 ADS to powerpc tree
Becky Bruce:
powerpc: Updated Initial MPC8540 ADS port with OF Flat Dev
powerpc: Fix Kernel FP unavail exception for BookE
powerpc: mpc85xx_ads.c include file cleanup
powerpc: rename mpc85xx.c to misc.c
powerpc: lindent 85xx platform code
powerpc/ppc: Add missing isyncs in head_fsl_booke.S
Christoph Hellwig:
powerpc: add for_each_node_by_foo helpers
spidernet: select FW_LOADER
David Gibson:
powerpc: Fixup for STRICT_MM_TYPECHECKS
powerpc: Better pmd_bad() and pud_bad() checks
Domen Puncer:
powerpc: Remove arch/ppc/syslib/ppc4xx_pm.c
Eric Sesterhenn:
kzalloc() conversion in arch/ppc
Geoff Levand:
powerpc: Add missing vmlinux.bin target
Grant C. Likely:
powerpc: Move xparameters.h into xilinx virtex device specific path
powerpc: Make Virtex-II Pro support generic for all Virtex devices
powerpc: Migrate Xilinx Vertex support from the OCP bus to the platfom bus.
powerpc: Migrate ML300 reference design to the platform bus
powerpc: Add ML300 defconfig
powerpc: Add Virtex-4 FX to cpu table
powerpc: Add xparameters file for Xilinx ML403 reference design
powerpc: Add support for Xilinx ML403 reference design
powerpc: Add ML403 defconfig
Grant Likely:
Fix compile error for ML300/403
Horst Kronstorfer:
ppc32: Fix BCSR_SIZE for MPC834x SYS
Jon Mason:
powerpc: trivial: modify comments to refer to new location of files
Kumar Gala:
powerpc: Add CONFIG_DEFAULT_UIMAGE to build a uImage by default for a board
powerpc: cleaned up fsl_soc.c
powerpc: Add platform support for MPC834x USB controllers
powerpc: Cleanup MPC83xx platform support
powerpc: Lindent platforms/83xx
powerpc: Fix mpc83xx restart bug
Marcelo Tosatti:
powerpc: generalize PPC44x_PIN_SIZE
Michael Ellerman:
powerpc: Always panic if lmb_alloc() fails
powerpc: Move LMB_ALLOC_ANYWHERE out of lmb.h
powerpc: Put parameter names in lmb.h prototypes
powerpc: Clean up pSeries firmware feature initialisation
powerpc: Move pSeries firmware feature setup into platforms/pseries
powerpc: Fix bug in bug fix for bug in lmb_alloc()
powerpc: Unconfuse htab_bolt_mapping() callers
powerpc: Remove unused iommu_off logic from pSeries_init_early()
powerpc: trivial: Cleanup whitespace in cputable.h
powerpc: Replace platform_is_lpar() with a firmware feature
powerpc: iseries: mf related cleanups
powerpc: iseries: Remove pointless iSeries_(restart|power_off|halt)
powerpc: iseries: Make more stuff static in platforms/iseries/mf.c
powerpc: Add strne2a() to convert a string from EBCDIC to ASCII
powerpc: iseries: Add /system-id, /model and /compatible
powerpc: iseries: Add bootargs to /chosen
powerpc: Remove calculation of io hole
Nathan Lynch:
powerpc numa: fix boot_cpuid always assigned to node 0
powerpc numa: Minor debugging code changes
powerpc numa: Minor cpu hotplug-related cleanups
powerpc numa: Get rid of "numa domain" terminology
powerpc numa: Consolidate handling of Power4 special case
powerpc numa: Support sparse online node map
powerpc numa: Consolidate assignment of cpus to nodes
Nick Piggin:
powerpc: newline for ISYNC_ON_SMP
powerpc: native atomic_add_unless
Olaf Hering:
powerpc: cleanup pmac_newworld variable usage
powerpc: remove check for ELF offset in powerpc bootimage
powerpc: add a raw dump command to xmon
Paul Mackerras:
powerpc: Implement accurate task and CPU time accounting
powerpc: Export variables used in conversions to/from cputime_t
Stephen Rothwell:
powerpc: update mailing list addresses
Vitaly Bordug:
ppc32 8xx: Added setbitsXX/clrbitsXX macro for read-modify-write operations
PPC32 8xx: support for the physmapped flash on m8xx
ppc32: MPC885ADS, MPC866ADS and MPC8272ADS-specific platform stuff for fs_enet
ppc32: Make platform devices being able to assign functions
Documentation/powerpc/eeh-pci-error-recovery.txt | 15
Documentation/powerpc/hvcs.txt | 4
MAINTAINERS | 4
arch/powerpc/Kconfig | 38 +
arch/powerpc/Makefile | 2
arch/powerpc/boot/install.sh | 2
arch/powerpc/boot/main.c | 4
arch/powerpc/configs/mpc8540_ads_defconfig | 721 +++++++++++++++++++
arch/powerpc/kernel/asm-offsets.c | 3
arch/powerpc/kernel/cputable.c | 12
arch/powerpc/kernel/entry_64.S | 11
arch/powerpc/kernel/firmware.c | 25 -
arch/powerpc/kernel/head_44x.S | 2
arch/powerpc/kernel/head_64.S | 11
arch/powerpc/kernel/head_8xx.S | 2
arch/powerpc/kernel/head_booke.h | 363 ++++++++++
arch/powerpc/kernel/head_fsl_booke.S | 6
arch/powerpc/kernel/iomap.c | 2
arch/powerpc/kernel/iommu.c | 1
arch/powerpc/kernel/irq.c | 32 +
arch/powerpc/kernel/kprobes.c | 1
arch/powerpc/kernel/pci_iommu.c | 1
arch/powerpc/kernel/ppc_ksyms.c | 1
arch/powerpc/kernel/process.c | 9
arch/powerpc/kernel/prom.c | 4
arch/powerpc/kernel/ptrace-common.h | 2
arch/powerpc/kernel/rtas-proc.c | 1
arch/powerpc/kernel/rtas_pci.c | 2
arch/powerpc/kernel/setup_64.c | 2
arch/powerpc/kernel/signal_64.c | 2
arch/powerpc/kernel/smp.c | 4
arch/powerpc/kernel/time.c | 241 ++++++-
arch/powerpc/kernel/vdso.c | 2
arch/powerpc/lib/copypage_64.S | 2
arch/powerpc/lib/copyuser_64.S | 2
arch/powerpc/lib/e2a.c | 14
arch/powerpc/lib/memcpy_64.S | 2
arch/powerpc/lib/rheap.c | 2
arch/powerpc/mm/fault.c | 2
arch/powerpc/mm/hash_low_32.S | 2
arch/powerpc/mm/hash_utils_64.c | 32 -
arch/powerpc/mm/init_64.c | 48 -
arch/powerpc/mm/lmb.c | 16
arch/powerpc/mm/mem.c | 1
arch/powerpc/mm/mmap.c | 2
arch/powerpc/mm/numa.c | 160 ++--
arch/powerpc/mm/slb_low.S | 2
arch/powerpc/mm/stab.c | 4
arch/powerpc/mm/tlb_64.c | 2
arch/powerpc/oprofile/op_model_power4.c | 3
arch/powerpc/platforms/83xx/Makefile | 4
arch/powerpc/platforms/83xx/misc.c | 55 +
arch/powerpc/platforms/83xx/mpc834x_sys.c | 89 --
arch/powerpc/platforms/83xx/mpc834x_sys.h | 2
arch/powerpc/platforms/83xx/mpc83xx.h | 5
arch/powerpc/platforms/83xx/pci.c | 21 -
arch/powerpc/platforms/85xx/Kconfig | 74 --
arch/powerpc/platforms/85xx/Makefile | 6
arch/powerpc/platforms/85xx/misc.c | 31 +
arch/powerpc/platforms/85xx/mpc8540_ads.h | 36 +
arch/powerpc/platforms/85xx/mpc85xx.h | 18
arch/powerpc/platforms/85xx/mpc85xx_ads.c | 244 +++++++
arch/powerpc/platforms/85xx/pci.c | 96 +++
arch/powerpc/platforms/Makefile | 2
arch/powerpc/platforms/chrp/pegasos_eth.c | 2
arch/powerpc/platforms/chrp/setup.c | 2
arch/powerpc/platforms/chrp/time.c | 2
arch/powerpc/platforms/iseries/mf.c | 112 ++-
arch/powerpc/platforms/iseries/setup.c | 72 +-
arch/powerpc/platforms/maple/time.c | 2
arch/powerpc/platforms/powermac/cpufreq_32.c | 2
arch/powerpc/platforms/powermac/feature.c | 2
arch/powerpc/platforms/powermac/nvram.c | 2
arch/powerpc/platforms/powermac/setup.c | 8
arch/powerpc/platforms/pseries/Makefile | 3
arch/powerpc/platforms/pseries/firmware.c | 103 +++
arch/powerpc/platforms/pseries/firmware.h | 17
arch/powerpc/platforms/pseries/hvCall.S | 2
arch/powerpc/platforms/pseries/iommu.c | 4
arch/powerpc/platforms/pseries/pci.c | 2
arch/powerpc/platforms/pseries/setup.c | 67 --
arch/powerpc/platforms/pseries/smp.c | 2
arch/powerpc/platforms/pseries/xics.c | 3
arch/powerpc/sysdev/dart_iommu.c | 2
arch/powerpc/sysdev/dcr.S | 2
arch/powerpc/sysdev/fsl_soc.c | 292 ++++++--
arch/powerpc/sysdev/ipic.h | 2
arch/powerpc/xmon/xmon.c | 30 +
arch/ppc/4xx_io/serial_sicc.c | 5
arch/ppc/8xx_io/commproc.c | 6
arch/ppc/Kconfig | 47 +
arch/ppc/Kconfig.debug | 2
arch/ppc/amiga/amiints.c | 2
arch/ppc/amiga/bootinfo.c | 2
arch/ppc/amiga/cia.c | 2
arch/ppc/amiga/config.c | 2
arch/ppc/amiga/ints.c | 2
arch/ppc/boot/Makefile | 3
arch/ppc/boot/common/Makefile | 3
arch/ppc/boot/common/bootinfo.c | 2
arch/ppc/boot/common/misc-common.c | 2
arch/ppc/boot/common/ns16550.c | 3
arch/ppc/boot/common/serial_stub.c | 2
arch/ppc/boot/common/util.S | 2
arch/ppc/boot/include/mpc10x.h | 2
arch/ppc/boot/simple/Makefile | 1
arch/ppc/boot/simple/cpc700_memory.c | 2
arch/ppc/boot/simple/embed_config.c | 7
arch/ppc/boot/simple/head.S | 9
arch/ppc/boot/simple/misc-chestnut.c | 2
arch/ppc/boot/simple/misc-cpci690.c | 2
arch/ppc/boot/simple/misc-ev64260.c | 2
arch/ppc/boot/simple/misc-ev64360.c | 1
arch/ppc/boot/simple/misc-katana.c | 2
arch/ppc/boot/simple/misc-mv64x60.c | 2
arch/ppc/boot/simple/misc-prep.c | 2
arch/ppc/boot/simple/misc-radstone_ppc7d.c | 2
arch/ppc/boot/simple/misc-spruce.c | 2
arch/ppc/boot/simple/misc.c | 2
arch/ppc/boot/simple/mpc10x_memory.c | 2
arch/ppc/boot/simple/mpc52xx_tty.c | 2
arch/ppc/boot/simple/mv64x60_tty.c | 2
arch/ppc/boot/simple/openbios.c | 2
arch/ppc/boot/simple/relocate.S | 2
arch/ppc/boot/utils/mkbugboot.c | 2
arch/ppc/configs/ml300_defconfig | 739 ++++++++++++++++++++
arch/ppc/configs/ml403_defconfig | 740 ++++++++++++++++++++
arch/ppc/kernel/head_44x.S | 2
arch/ppc/kernel/head_8xx.S | 2
arch/ppc/kernel/head_fsl_booke.S | 6
arch/ppc/kernel/smp-tbsync.c | 3
arch/ppc/kernel/traps.c | 2
arch/ppc/lib/rheap.c | 2
arch/ppc/math-emu/math.c | 2
arch/ppc/mm/44x_mmu.c | 4
arch/ppc/mm/fault.c | 2
arch/ppc/mm/hashtable.S | 2
arch/ppc/platforms/4xx/Kconfig | 23 -
arch/ppc/platforms/4xx/Makefile | 4
arch/ppc/platforms/4xx/bamboo.c | 2
arch/ppc/platforms/4xx/bamboo.h | 2
arch/ppc/platforms/4xx/bubinga.h | 2
arch/ppc/platforms/4xx/cpci405.c | 2
arch/ppc/platforms/4xx/ebony.c | 2
arch/ppc/platforms/4xx/ebony.h | 2
arch/ppc/platforms/4xx/ep405.c | 2
arch/ppc/platforms/4xx/ep405.h | 2
arch/ppc/platforms/4xx/ibm405ep.c | 2
arch/ppc/platforms/4xx/ibm405ep.h | 2
arch/ppc/platforms/4xx/ibm405gp.h | 2
arch/ppc/platforms/4xx/ibm405gpr.c | 2
arch/ppc/platforms/4xx/ibm405gpr.h | 2
arch/ppc/platforms/4xx/ibm440ep.c | 2
arch/ppc/platforms/4xx/ibm440ep.h | 2
arch/ppc/platforms/4xx/ibm440gp.c | 2
arch/ppc/platforms/4xx/ibm440gp.h | 2
arch/ppc/platforms/4xx/ibm440gx.c | 2
arch/ppc/platforms/4xx/ibm440gx.h | 2
arch/ppc/platforms/4xx/ibm440sp.c | 2
arch/ppc/platforms/4xx/ibm440sp.h | 2
arch/ppc/platforms/4xx/ibmnp405h.c | 2
arch/ppc/platforms/4xx/ibmnp405h.h | 2
arch/ppc/platforms/4xx/ibmstb4.c | 2
arch/ppc/platforms/4xx/ibmstb4.h | 2
arch/ppc/platforms/4xx/ibmstbx25.c | 2
arch/ppc/platforms/4xx/ibmstbx25.h | 2
arch/ppc/platforms/4xx/luan.c | 2
arch/ppc/platforms/4xx/luan.h | 2
arch/ppc/platforms/4xx/ocotea.c | 2
arch/ppc/platforms/4xx/ocotea.h | 2
arch/ppc/platforms/4xx/ppc440spe.c | 2
arch/ppc/platforms/4xx/ppc440spe.h | 2
arch/ppc/platforms/4xx/redwood5.c | 2
arch/ppc/platforms/4xx/redwood5.h | 2
arch/ppc/platforms/4xx/redwood6.c | 2
arch/ppc/platforms/4xx/redwood6.h | 2
arch/ppc/platforms/4xx/sycamore.c | 2
arch/ppc/platforms/4xx/sycamore.h | 2
arch/ppc/platforms/4xx/virtex-ii_pro.c | 60 --
arch/ppc/platforms/4xx/virtex-ii_pro.h | 99 ---
arch/ppc/platforms/4xx/virtex.c | 56 ++
arch/ppc/platforms/4xx/virtex.h | 35 +
arch/ppc/platforms/4xx/walnut.c | 2
arch/ppc/platforms/4xx/walnut.h | 2
arch/ppc/platforms/4xx/xilinx_ml300.c | 76 +-
arch/ppc/platforms/4xx/xilinx_ml300.h | 6
arch/ppc/platforms/4xx/xilinx_ml403.c | 177 +++++
arch/ppc/platforms/4xx/xilinx_ml403.h | 49 +
arch/ppc/platforms/4xx/xparameters/xparameters.h | 37 +
.../platforms/4xx/xparameters/xparameters_ml403.h | 243 ++++++++
arch/ppc/platforms/4xx/yucca.c | 2
arch/ppc/platforms/4xx/yucca.h | 2
arch/ppc/platforms/83xx/mpc834x_sys.c | 2
arch/ppc/platforms/83xx/mpc834x_sys.h | 4
arch/ppc/platforms/85xx/mpc8540_ads.c | 2
arch/ppc/platforms/85xx/mpc8540_ads.h | 2
arch/ppc/platforms/85xx/mpc8555_cds.h | 2
arch/ppc/platforms/85xx/mpc8560_ads.c | 2
arch/ppc/platforms/85xx/mpc8560_ads.h | 2
arch/ppc/platforms/85xx/mpc85xx_ads_common.c | 2
arch/ppc/platforms/85xx/mpc85xx_ads_common.h | 2
arch/ppc/platforms/85xx/mpc85xx_cds_common.c | 2
arch/ppc/platforms/85xx/mpc85xx_cds_common.h | 2
arch/ppc/platforms/85xx/sbc8560.c | 2
arch/ppc/platforms/85xx/sbc8560.h | 2
arch/ppc/platforms/85xx/sbc85xx.c | 2
arch/ppc/platforms/85xx/sbc85xx.h | 2
arch/ppc/platforms/85xx/stx_gp3.c | 2
arch/ppc/platforms/85xx/stx_gp3.h | 2
arch/ppc/platforms/85xx/tqm85xx.c | 2
arch/ppc/platforms/85xx/tqm85xx.h | 2
arch/ppc/platforms/Makefile | 3
arch/ppc/platforms/apus_setup.c | 2
arch/ppc/platforms/chestnut.c | 2
arch/ppc/platforms/chestnut.h | 2
arch/ppc/platforms/chrp_pegasos_eth.c | 2
arch/ppc/platforms/chrp_setup.c | 2
arch/ppc/platforms/chrp_time.c | 2
arch/ppc/platforms/cpci690.c | 4
arch/ppc/platforms/cpci690.h | 2
arch/ppc/platforms/ev64260.c | 4
arch/ppc/platforms/ev64260.h | 2
arch/ppc/platforms/ev64360.c | 4
arch/ppc/platforms/ev64360.h | 2
arch/ppc/platforms/fads.h | 2
arch/ppc/platforms/gemini.h | 3
arch/ppc/platforms/gemini_prom.S | 2
arch/ppc/platforms/gemini_setup.c | 2
arch/ppc/platforms/hdpu.c | 5
arch/ppc/platforms/hdpu.h | 2
arch/ppc/platforms/katana.c | 7
arch/ppc/platforms/katana.h | 2
arch/ppc/platforms/lite5200.c | 2
arch/ppc/platforms/lite5200.h | 2
arch/ppc/platforms/lopec.c | 2
arch/ppc/platforms/mpc8272ads_setup.c | 236 ++++++
arch/ppc/platforms/mpc866ads_setup.c | 273 +++++++
arch/ppc/platforms/mpc885ads_setup.c | 389 +++++++++++
arch/ppc/platforms/mvme5100.c | 2
arch/ppc/platforms/pal4.h | 2
arch/ppc/platforms/pal4_pci.c | 2
arch/ppc/platforms/pal4_serial.h | 2
arch/ppc/platforms/pal4_setup.c | 2
arch/ppc/platforms/powerpmc250.c | 2
arch/ppc/platforms/pplus.c | 2
arch/ppc/platforms/pplus.h | 2
arch/ppc/platforms/pq2ads.c | 2
arch/ppc/platforms/pq2ads.h | 4
arch/ppc/platforms/pq2ads_pd.h | 114 +++
arch/ppc/platforms/prep_setup.c | 2
arch/ppc/platforms/prpmc750.c | 2
arch/ppc/platforms/prpmc800.c | 2
arch/ppc/platforms/radstone_ppc7d.c | 7
arch/ppc/platforms/radstone_ppc7d.h | 2
arch/ppc/platforms/sandpoint.c | 2
arch/ppc/platforms/sandpoint.h | 2
arch/ppc/platforms/sbc82xx.c | 2
arch/ppc/platforms/spruce.c | 2
arch/ppc/platforms/tqm8260_setup.c | 2
arch/ppc/syslib/Makefile | 4
arch/ppc/syslib/cpc700.h | 2
arch/ppc/syslib/cpc700_pic.c | 2
arch/ppc/syslib/cpc710.h | 2
arch/ppc/syslib/gen550.h | 2
arch/ppc/syslib/gen550_dbg.c | 2
arch/ppc/syslib/gen550_kgdb.c | 2
arch/ppc/syslib/gt64260_pic.c | 2
arch/ppc/syslib/harrier.c | 2
arch/ppc/syslib/hawk_common.c | 2
arch/ppc/syslib/ibm440gp_common.c | 2
arch/ppc/syslib/ibm440gp_common.h | 2
arch/ppc/syslib/ibm440gx_common.c | 2
arch/ppc/syslib/ibm440gx_common.h | 2
arch/ppc/syslib/ibm440sp_common.c | 2
arch/ppc/syslib/ibm440sp_common.h | 2
arch/ppc/syslib/ibm44x_common.c | 2
arch/ppc/syslib/ibm44x_common.h | 2
arch/ppc/syslib/m8260_pci_erratum9.c | 2
arch/ppc/syslib/m8260_setup.c | 2
arch/ppc/syslib/m8xx_setup.c | 65 ++
arch/ppc/syslib/m8xx_wdt.c | 3
arch/ppc/syslib/mpc10x_common.c | 2
arch/ppc/syslib/mpc52xx_devices.c | 2
arch/ppc/syslib/mpc52xx_pci.c | 2
arch/ppc/syslib/mpc52xx_pci.h | 2
arch/ppc/syslib/mpc52xx_pic.c | 2
arch/ppc/syslib/mpc52xx_setup.c | 2
arch/ppc/syslib/mpc52xx_sys.c | 2
arch/ppc/syslib/mpc83xx_devices.c | 2
arch/ppc/syslib/mpc83xx_sys.c | 2
arch/ppc/syslib/mpc85xx_devices.c | 2
arch/ppc/syslib/mpc85xx_sys.c | 2
arch/ppc/syslib/mpc8xx_devices.c | 2
arch/ppc/syslib/mpc8xx_sys.c | 2
arch/ppc/syslib/mv64360_pic.c | 2
arch/ppc/syslib/mv64x60.c | 2
arch/ppc/syslib/mv64x60_dbg.c | 2
arch/ppc/syslib/mv64x60_win.c | 2
arch/ppc/syslib/ocp.c | 3
arch/ppc/syslib/open_pic.c | 2
arch/ppc/syslib/open_pic2.c | 2
arch/ppc/syslib/open_pic_defs.h | 2
arch/ppc/syslib/pci_auto.c | 2
arch/ppc/syslib/ppc4xx_dma.c | 2
arch/ppc/syslib/ppc4xx_pic.c | 2
arch/ppc/syslib/ppc4xx_pm.c | 47 -
arch/ppc/syslib/ppc4xx_sgdma.c | 2
arch/ppc/syslib/ppc83xx_setup.c | 2
arch/ppc/syslib/ppc83xx_setup.h | 2
arch/ppc/syslib/ppc85xx_common.c | 2
arch/ppc/syslib/ppc85xx_common.h | 2
arch/ppc/syslib/ppc85xx_setup.c | 2
arch/ppc/syslib/ppc85xx_setup.h | 2
arch/ppc/syslib/ppc_sys.c | 179 +++++
arch/ppc/syslib/pq2_devices.c | 2
arch/ppc/syslib/pq2_sys.c | 2
arch/ppc/syslib/prep_nvram.c | 2
arch/ppc/syslib/todc_time.c | 2
arch/ppc/syslib/xilinx_pic.c | 4
drivers/char/hvcs.c | 9
drivers/net/Kconfig | 1
include/asm-powerpc/atomic.h | 38 +
include/asm-powerpc/cputable.h | 38 +
include/asm-powerpc/cputime.h | 202 +++++
include/asm-powerpc/firmware.h | 16
include/asm-powerpc/irq.h | 6
include/asm-powerpc/iseries/mf.h | 7
include/asm-powerpc/lmb.h | 19 -
include/asm-powerpc/mmu.h | 1
include/asm-powerpc/paca.h | 7
include/asm-powerpc/pgtable-4k.h | 11
include/asm-powerpc/pgtable.h | 9
include/asm-powerpc/ppc_asm.h | 42 +
include/asm-powerpc/processor.h | 1
include/asm-powerpc/prom.h | 6
include/asm-powerpc/rwsem.h | 2
include/asm-powerpc/synch.h | 2
include/asm-powerpc/system.h | 6
include/asm-powerpc/time.h | 15
include/asm-ppc/harrier.h | 2
include/asm-ppc/ibm44x.h | 2
include/asm-ppc/ibm4xx.h | 4
include/asm-ppc/io.h | 7
include/asm-ppc/mpc10x.h | 3
include/asm-ppc/mpc52xx.h | 1
include/asm-ppc/mpc8260.h | 1
include/asm-ppc/mpc83xx.h | 1
include/asm-ppc/mpc85xx.h | 1
include/asm-ppc/mpc8xx.h | 3
include/asm-ppc/pgtable.h | 6
include/asm-ppc/ppc_sys.h | 34 +
include/asm-ppc/time.h | 5
include/asm-ppc/todc.h | 2
include/asm-ppc/xparameters.h | 18
kernel/auditsc.c | 2
lib/extable.c | 1
356 files changed, 6497 insertions(+), 1452 deletions(-)
create mode 100644 arch/powerpc/configs/mpc8540_ads_defconfig
create mode 100644 arch/powerpc/kernel/head_booke.h
create mode 100644 arch/powerpc/platforms/83xx/misc.c
create mode 100644 arch/powerpc/platforms/85xx/misc.c
create mode 100644 arch/powerpc/platforms/85xx/mpc8540_ads.h
create mode 100644 arch/powerpc/platforms/85xx/mpc85xx.h
create mode 100644 arch/powerpc/platforms/85xx/mpc85xx_ads.c
create mode 100644 arch/powerpc/platforms/85xx/pci.c
create mode 100644 arch/powerpc/platforms/pseries/firmware.c
create mode 100644 arch/powerpc/platforms/pseries/firmware.h
create mode 100644 arch/ppc/configs/ml300_defconfig
create mode 100644 arch/ppc/configs/ml403_defconfig
delete mode 100644 arch/ppc/platforms/4xx/virtex-ii_pro.c
delete mode 100644 arch/ppc/platforms/4xx/virtex-ii_pro.h
create mode 100644 arch/ppc/platforms/4xx/virtex.c
create mode 100644 arch/ppc/platforms/4xx/virtex.h
create mode 100644 arch/ppc/platforms/4xx/xilinx_ml403.c
create mode 100644 arch/ppc/platforms/4xx/xilinx_ml403.h
create mode 100644 arch/ppc/platforms/4xx/xparameters/xparameters.h
create mode 100644 arch/ppc/platforms/4xx/xparameters/xparameters_ml403.h
create mode 100644 arch/ppc/platforms/mpc8272ads_setup.c
create mode 100644 arch/ppc/platforms/mpc866ads_setup.c
create mode 100644 arch/ppc/platforms/mpc885ads_setup.c
create mode 100644 arch/ppc/platforms/pq2ads_pd.h
delete mode 100644 arch/ppc/syslib/ppc4xx_pm.c
delete mode 100644 include/asm-ppc/xparameters.h
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