* Re: [PATCH 00/15] powerpc: move some header files
From: Stephen Rothwell @ 2006-04-05 16:03 UTC (permalink / raw)
To: Kumar Gala; +Cc: linuxppc-dev, paulus
In-Reply-To: <C40B1083-7953-4104-8FA3-5B9B4EBE1A77@kernel.crashing.org>
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On Wed, 5 Apr 2006 09:28:55 -0500 Kumar Gala <galak@kernel.crashing.org> wrote:
>
> How about we do the following to remove the include hack:
>
> don't move the following (determine what needs them to build and
> fixup, I dont believe any of these need to exist at this point in
> arch/powerpc for it to build any supported arch/powerpc platform:
I only moved the files that were actually required to build the defconfigs
for the three 32 bit builds in arch/powerpc ...
> b/include/asm-powerpc/amigappc.h | 9 ++----
> b/include/asm-powerpc/bootinfo.h | 8 ++---
> b/include/asm-powerpc/mpc8xx.h | 10 +++---
> b/include/asm-powerpc/ocp.h | 7 ++--
> b/include/asm-powerpc/ocp_ids.h | 6 ++--
> b/include/asm-powerpc/open_pic.h | 10 +++---
So maybe I could attempt to remove the dependencies instead of moving the
files. You are right that it is worth it if we can just get rid of these
files.
> Duplicate these headers (then I'll go through and clean them up,
> removing arch/ppc'ism):
>
> b/include/asm-powerpc/mpc83xx.h | 7 ++--
> b/include/asm-powerpc/mpc85xx.h | 9 ++----
I guess that would work, but Paulus is going to not like me as he already
put all these patches into the powerpc tree. :-)
Something to keep me entertained for another day.
--
Cheers,
Stephen Rothwell sfr@canb.auug.org.au
http://www.canb.auug.org.au/~sfr/
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* Re: Anybody applied the patch "Add 85xx CDS to arch/powerpc" on the 2.6.16. I failed to apply it:-(
From: Jon Loeliger @ 2006-04-05 14:38 UTC (permalink / raw)
To: fengcheng lu; +Cc: linuxppc-dev, linuxppc-embedded
In-Reply-To: <e9aafa30604050732g6ede1f37h450243613bcbca85@mail.gmail.com>
So, like, the other day "fengcheng lu" mumbled:
>
> I downloaded this patch from
> http://patchwork.ozlabs.org/linuxppc/patch?id=3D4910. But I failed to apply
> it. The following is the output:
> debian:/usr/src/linux-2.6.16# patch -p1 <powerpc.patch
> patching file arch/powerpc/config/mpc85xx_cds_deconfig
> patching file arch/powerpc/platforms/85xx/Kconfig
> Hunk #1 FAILED at 11
> 1 out of 1 hunk FAILED -- saving rejects to file
> arch/powerpc/platforms/85xx/Kconfig.rej
> patching file arch/powerpc/platforms/85xx/Makefile
> Hunk #1 FAILED at 3
> 1 out of 1 hunk FAILED -- saving rejects to file
> arch/powerpc/platforms/85xx/Makefile.rej
> patching file arch/powerpc/platforms/85xx/mpc85xx_cds.c
> patching file arch/powerpc/platforms/85xx/mpc85xx_cds.h
> patching file include/asm-ppc/mpc85xx.h
>
> It looks seem the Makefile and Kconfig don't match yours.
What was the repository against which you applied this patch?
Was it Linus' or Paul's? I suspect it needs to be Paul's
powerpc.git repository.
HTH,
jdl
^ permalink raw reply
* Anybody applied the patch "Add 85xx CDS to arch/powerpc" on the 2.6.16. I failed to apply it:-(
From: fengcheng lu @ 2006-04-05 14:32 UTC (permalink / raw)
To: linuxppc-dev, linuxppc-embedded
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Hello all
I downloaded this patch from
http://patchwork.ozlabs.org/linuxppc/patch?id=4910. But I failed to apply
it. The following is the output:
debian:/usr/src/linux-2.6.16# patch -p1 <powerpc.patch
patching file arch/powerpc/config/mpc85xx_cds_deconfig
patching file arch/powerpc/platforms/85xx/Kconfig
Hunk #1 FAILED at 11
1 out of 1 hunk FAILED -- saving rejects to file
arch/powerpc/platforms/85xx/Kconfig.rej
patching file arch/powerpc/platforms/85xx/Makefile
Hunk #1 FAILED at 3
1 out of 1 hunk FAILED -- saving rejects to file
arch/powerpc/platforms/85xx/Makefile.rej
patching file arch/powerpc/platforms/85xx/mpc85xx_cds.c
patching file arch/powerpc/platforms/85xx/mpc85xx_cds.h
patching file include/asm-ppc/mpc85xx.h
It looks seem the Makefile and Kconfig don't match yours.
Who have the successful patch experience. Thank you to tell me the right
procedure!
BTW: the patch command version is 2.5.4
Best Regards
Lu
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* Re: [PATCH 00/15] powerpc: move some header files
From: Kumar Gala @ 2006-04-05 14:28 UTC (permalink / raw)
To: sfr; +Cc: linuxppc-dev, paulus
In-Reply-To: <11442138494042-git-send-email-sfr@canb.auug.org.au>
On Apr 5, 2006, at 12:10 AM, sfr@canb.auug.org.au wrote:
> This patch set moves sufficient include files from include/asm-ppc
> to include/asm-powerpc to allow us to remove the include hack in the
> arch/powerpc/Makefile.
>
> b/arch/powerpc/Makefile | 21 ++------------
> b/include/asm-powerpc/amigappc.h | 9 ++----
> b/include/asm-powerpc/bootinfo.h | 8 ++---
> b/include/asm-powerpc/highmem.h | 11 +++----
> b/include/asm-powerpc/hydra.h | 8 ++---
> b/include/asm-powerpc/mpc83xx.h | 7 ++--
> b/include/asm-powerpc/mpc85xx.h | 9 ++----
> b/include/asm-powerpc/mpc8xx.h | 10 +++---
> b/include/asm-powerpc/ocp.h | 7 ++--
> b/include/asm-powerpc/ocp_ids.h | 6 ++--
> b/include/asm-powerpc/open_pic.h | 10 +++---
> b/include/asm-powerpc/pnp.h | 8 ++---
> b/include/asm-powerpc/reg_booke.h | 55 ++++++++++++++++++
> +-------------------
> b/include/asm-powerpc/residual.h | 6 ++--
> b/include/asm-powerpc/suspend.h | 17 +++++++++++
> include/asm-ppc/suspend.h | 12 --------
> 16 files changed, 95 insertions(+), 109 deletions(-)
How about we do the following to remove the include hack:
don't move the following (determine what needs them to build and
fixup, I dont believe any of these need to exist at this point in
arch/powerpc for it to build any supported arch/powerpc platform:
b/include/asm-powerpc/amigappc.h | 9 ++----
b/include/asm-powerpc/bootinfo.h | 8 ++---
b/include/asm-powerpc/mpc8xx.h | 10 +++---
b/include/asm-powerpc/ocp.h | 7 ++--
b/include/asm-powerpc/ocp_ids.h | 6 ++--
b/include/asm-powerpc/open_pic.h | 10 +++---
Duplicate these headers (then I'll go through and clean them up,
removing arch/ppc'ism):
b/include/asm-powerpc/mpc83xx.h | 7 ++--
b/include/asm-powerpc/mpc85xx.h | 9 ++----
- kumar
^ permalink raw reply
* Re: [PATCH 14/15] powerpc: move asm/mpc85xx.h
From: Kumar Gala @ 2006-04-05 14:17 UTC (permalink / raw)
To: sfr; +Cc: linuxppc-dev, paulus
In-Reply-To: <11442138813940-git-send-email-sfr@canb.auug.org.au>
Nack. I was avoiding moving this header since it introduces a number
things that should only exist in arch/ppc.
- k
On Apr 5, 2006, at 12:10 AM, sfr@canb.auug.org.au wrote:
> From: Stephen Rothwell <sfr@canb.auug.org.au>
>
> Since the ARCH=powerpc build depends on this file, move it to
> include/asm-powerpc.
>
> Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
>
> ---
>
> include/asm-powerpc/mpc85xx.h | 195 ++++++++++++++++++++++++++++++
> ++++++++++
> include/asm-ppc/mpc85xx.h | 198
> -----------------------------------------
> 2 files changed, 195 insertions(+), 198 deletions(-)
> create mode 100644 include/asm-powerpc/mpc85xx.h
> delete mode 100644 include/asm-ppc/mpc85xx.h
>
> 4fc7b6e78d24e11e704ef7b5a1ceb659d3a03cc2
> diff --git a/include/asm-powerpc/mpc85xx.h b/include/asm-powerpc/
> mpc85xx.h
> new file mode 100644
> index 0000000..4113165
> --- /dev/null
> +++ b/include/asm-powerpc/mpc85xx.h
> @@ -0,0 +1,195 @@
> +#ifndef _ASM_POWERPC_MPC85XX_H
> +#define _ASM_POWERPC_MPC85XX_H
> +/*
> + * MPC85xx definitions
> + *
> + * Maintainer: Kumar Gala <galak@kernel.crashing.org>
> + *
> + * Copyright 2004 Freescale Semiconductor, Inc
> + *
> + * This program is free software; you can redistribute it and/or
> modify it
> + * under the terms of the GNU General Public License as
> published by the
> + * Free Software Foundation; either version 2 of the License, or
> (at your
> + * option) any later version.
> + */
> +
> +#ifdef __KERNEL__
> +
> +#include <asm/mmu.h>
> +
> +#ifdef CONFIG_85xx
> +
> +#ifdef CONFIG_MPC8540_ADS
> +#include <platforms/85xx/mpc8540_ads.h>
> +#endif
> +#if defined(CONFIG_MPC8555_CDS) || defined(CONFIG_MPC8548_CDS)
> +#include <platforms/85xx/mpc8555_cds.h>
> +#endif
> +#ifdef CONFIG_MPC8560_ADS
> +#include <platforms/85xx/mpc8560_ads.h>
> +#endif
> +#ifdef CONFIG_SBC8560
> +#include <platforms/85xx/sbc8560.h>
> +#endif
> +#ifdef CONFIG_STX_GP3
> +#include <platforms/85xx/stx_gp3.h>
> +#endif
> +#if defined(CONFIG_TQM8540) || defined(CONFIG_TQM8541) || \
> + defined(CONFIG_TQM8555) || defined(CONFIG_TQM8560)
> +#include <platforms/85xx/tqm85xx.h>
> +#endif
> +
> +#define _IO_BASE isa_io_base
> +#define _ISA_MEM_BASE isa_mem_base
> +#ifdef CONFIG_PCI
> +#define PCI_DRAM_OFFSET pci_dram_offset
> +#else
> +#define PCI_DRAM_OFFSET 0
> +#endif
> +
> +/*
> + * The "residual" board information structure the boot loader passes
> + * into the kernel.
> + */
> +extern unsigned char __res[];
> +
> +/* Offset from CCSRBAR */
> +#define MPC85xx_CPM_OFFSET (0x80000)
> +#define MPC85xx_CPM_SIZE (0x40000)
> +#define MPC85xx_DMA_OFFSET (0x21000)
> +#define MPC85xx_DMA_SIZE (0x01000)
> +#define MPC85xx_DMA0_OFFSET (0x21100)
> +#define MPC85xx_DMA0_SIZE (0x00080)
> +#define MPC85xx_DMA1_OFFSET (0x21180)
> +#define MPC85xx_DMA1_SIZE (0x00080)
> +#define MPC85xx_DMA2_OFFSET (0x21200)
> +#define MPC85xx_DMA2_SIZE (0x00080)
> +#define MPC85xx_DMA3_OFFSET (0x21280)
> +#define MPC85xx_DMA3_SIZE (0x00080)
> +#define MPC85xx_ENET1_OFFSET (0x24000)
> +#define MPC85xx_ENET1_SIZE (0x01000)
> +#define MPC85xx_MIIM_OFFSET (0x24520)
> +#define MPC85xx_MIIM_SIZE (0x00018)
> +#define MPC85xx_ENET2_OFFSET (0x25000)
> +#define MPC85xx_ENET2_SIZE (0x01000)
> +#define MPC85xx_ENET3_OFFSET (0x26000)
> +#define MPC85xx_ENET3_SIZE (0x01000)
> +#define MPC85xx_GUTS_OFFSET (0xe0000)
> +#define MPC85xx_GUTS_SIZE (0x01000)
> +#define MPC85xx_IIC1_OFFSET (0x03000)
> +#define MPC85xx_IIC1_SIZE (0x00100)
> +#define MPC85xx_OPENPIC_OFFSET (0x40000)
> +#define MPC85xx_OPENPIC_SIZE (0x40000)
> +#define MPC85xx_PCI1_OFFSET (0x08000)
> +#define MPC85xx_PCI1_SIZE (0x01000)
> +#define MPC85xx_PCI2_OFFSET (0x09000)
> +#define MPC85xx_PCI2_SIZE (0x01000)
> +#define MPC85xx_PERFMON_OFFSET (0xe1000)
> +#define MPC85xx_PERFMON_SIZE (0x01000)
> +#define MPC85xx_SEC2_OFFSET (0x30000)
> +#define MPC85xx_SEC2_SIZE (0x10000)
> +#define MPC85xx_UART0_OFFSET (0x04500)
> +#define MPC85xx_UART0_SIZE (0x00100)
> +#define MPC85xx_UART1_OFFSET (0x04600)
> +#define MPC85xx_UART1_SIZE (0x00100)
> +
> +#define MPC85xx_CCSRBAR_SIZE (1024*1024)
> +
> +/* Let modules/drivers get at CCSRBAR */
> +extern phys_addr_t get_ccsrbar(void);
> +
> +#ifdef MODULE
> +#define CCSRBAR get_ccsrbar()
> +#else
> +#define CCSRBAR BOARD_CCSRBAR
> +#endif
> +
> +enum ppc_sys_devices {
> + MPC85xx_TSEC1,
> + MPC85xx_TSEC2,
> + MPC85xx_FEC,
> + MPC85xx_IIC1,
> + MPC85xx_DMA0,
> + MPC85xx_DMA1,
> + MPC85xx_DMA2,
> + MPC85xx_DMA3,
> + MPC85xx_DUART,
> + MPC85xx_PERFMON,
> + MPC85xx_SEC2,
> + MPC85xx_CPM_SPI,
> + MPC85xx_CPM_I2C,
> + MPC85xx_CPM_USB,
> + MPC85xx_CPM_SCC1,
> + MPC85xx_CPM_SCC2,
> + MPC85xx_CPM_SCC3,
> + MPC85xx_CPM_SCC4,
> + MPC85xx_CPM_FCC1,
> + MPC85xx_CPM_FCC2,
> + MPC85xx_CPM_FCC3,
> + MPC85xx_CPM_MCC1,
> + MPC85xx_CPM_MCC2,
> + MPC85xx_CPM_SMC1,
> + MPC85xx_CPM_SMC2,
> + MPC85xx_eTSEC1,
> + MPC85xx_eTSEC2,
> + MPC85xx_eTSEC3,
> + MPC85xx_eTSEC4,
> + MPC85xx_IIC2,
> + MPC85xx_MDIO,
> + NUM_PPC_SYS_DEVS,
> +};
> +
> +/* Internal interrupts are all Level Sensitive, and Positive
> Polarity */
> +#define MPC85XX_INTERNAL_IRQ_SENSES \
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 0 */ \
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 1 */ \
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 2 */ \
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 3 */ \
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 4 */ \
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 5 */ \
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 6 */ \
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 7 */ \
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 8 */ \
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 9 */ \
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 10 */ \
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 11 */ \
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 12 */ \
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 13 */ \
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 14 */ \
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 15 */ \
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 16 */ \
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 17 */ \
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 18 */ \
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 19 */ \
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 20 */ \
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 21 */ \
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 22 */ \
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 23 */ \
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 24 */ \
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 25 */ \
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 26 */ \
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 27 */ \
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 28 */ \
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 29 */ \
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 30 */ \
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 31 */ \
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 32 */ \
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 33 */ \
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 34 */ \
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 35 */ \
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 36 */ \
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 37 */ \
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 38 */ \
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 39 */ \
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 40 */ \
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 41 */ \
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 42 */ \
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 43 */ \
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 44 */ \
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 45 */ \
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 46 */ \
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE) /* Internal 47 */
> +
> +#endif /* CONFIG_85xx */
> +#endif /* __KERNEL__ */
> +#endif /* _ASM_POWERPC_MPC85XX_H */
> diff --git a/include/asm-ppc/mpc85xx.h b/include/asm-ppc/mpc85xx.h
> deleted file mode 100644
> index f47002a..0000000
> --- a/include/asm-ppc/mpc85xx.h
> +++ /dev/null
> @@ -1,198 +0,0 @@
> -/*
> - * include/asm-ppc/mpc85xx.h
> - *
> - * MPC85xx definitions
> - *
> - * Maintainer: Kumar Gala <galak@kernel.crashing.org>
> - *
> - * Copyright 2004 Freescale Semiconductor, Inc
> - *
> - * This program is free software; you can redistribute it and/or
> modify it
> - * under the terms of the GNU General Public License as
> published by the
> - * Free Software Foundation; either version 2 of the License, or
> (at your
> - * option) any later version.
> - */
> -
> -#ifdef __KERNEL__
> -#ifndef __ASM_MPC85xx_H__
> -#define __ASM_MPC85xx_H__
> -
> -#include <linux/config.h>
> -#include <asm/mmu.h>
> -
> -#ifdef CONFIG_85xx
> -
> -#ifdef CONFIG_MPC8540_ADS
> -#include <platforms/85xx/mpc8540_ads.h>
> -#endif
> -#if defined(CONFIG_MPC8555_CDS) || defined(CONFIG_MPC8548_CDS)
> -#include <platforms/85xx/mpc8555_cds.h>
> -#endif
> -#ifdef CONFIG_MPC8560_ADS
> -#include <platforms/85xx/mpc8560_ads.h>
> -#endif
> -#ifdef CONFIG_SBC8560
> -#include <platforms/85xx/sbc8560.h>
> -#endif
> -#ifdef CONFIG_STX_GP3
> -#include <platforms/85xx/stx_gp3.h>
> -#endif
> -#if defined(CONFIG_TQM8540) || defined(CONFIG_TQM8541) || \
> - defined(CONFIG_TQM8555) || defined(CONFIG_TQM8560)
> -#include <platforms/85xx/tqm85xx.h>
> -#endif
> -
> -#define _IO_BASE isa_io_base
> -#define _ISA_MEM_BASE isa_mem_base
> -#ifdef CONFIG_PCI
> -#define PCI_DRAM_OFFSET pci_dram_offset
> -#else
> -#define PCI_DRAM_OFFSET 0
> -#endif
> -
> -/*
> - * The "residual" board information structure the boot loader passes
> - * into the kernel.
> - */
> -extern unsigned char __res[];
> -
> -/* Offset from CCSRBAR */
> -#define MPC85xx_CPM_OFFSET (0x80000)
> -#define MPC85xx_CPM_SIZE (0x40000)
> -#define MPC85xx_DMA_OFFSET (0x21000)
> -#define MPC85xx_DMA_SIZE (0x01000)
> -#define MPC85xx_DMA0_OFFSET (0x21100)
> -#define MPC85xx_DMA0_SIZE (0x00080)
> -#define MPC85xx_DMA1_OFFSET (0x21180)
> -#define MPC85xx_DMA1_SIZE (0x00080)
> -#define MPC85xx_DMA2_OFFSET (0x21200)
> -#define MPC85xx_DMA2_SIZE (0x00080)
> -#define MPC85xx_DMA3_OFFSET (0x21280)
> -#define MPC85xx_DMA3_SIZE (0x00080)
> -#define MPC85xx_ENET1_OFFSET (0x24000)
> -#define MPC85xx_ENET1_SIZE (0x01000)
> -#define MPC85xx_MIIM_OFFSET (0x24520)
> -#define MPC85xx_MIIM_SIZE (0x00018)
> -#define MPC85xx_ENET2_OFFSET (0x25000)
> -#define MPC85xx_ENET2_SIZE (0x01000)
> -#define MPC85xx_ENET3_OFFSET (0x26000)
> -#define MPC85xx_ENET3_SIZE (0x01000)
> -#define MPC85xx_GUTS_OFFSET (0xe0000)
> -#define MPC85xx_GUTS_SIZE (0x01000)
> -#define MPC85xx_IIC1_OFFSET (0x03000)
> -#define MPC85xx_IIC1_SIZE (0x00100)
> -#define MPC85xx_OPENPIC_OFFSET (0x40000)
> -#define MPC85xx_OPENPIC_SIZE (0x40000)
> -#define MPC85xx_PCI1_OFFSET (0x08000)
> -#define MPC85xx_PCI1_SIZE (0x01000)
> -#define MPC85xx_PCI2_OFFSET (0x09000)
> -#define MPC85xx_PCI2_SIZE (0x01000)
> -#define MPC85xx_PERFMON_OFFSET (0xe1000)
> -#define MPC85xx_PERFMON_SIZE (0x01000)
> -#define MPC85xx_SEC2_OFFSET (0x30000)
> -#define MPC85xx_SEC2_SIZE (0x10000)
> -#define MPC85xx_UART0_OFFSET (0x04500)
> -#define MPC85xx_UART0_SIZE (0x00100)
> -#define MPC85xx_UART1_OFFSET (0x04600)
> -#define MPC85xx_UART1_SIZE (0x00100)
> -
> -#define MPC85xx_CCSRBAR_SIZE (1024*1024)
> -
> -/* Let modules/drivers get at CCSRBAR */
> -extern phys_addr_t get_ccsrbar(void);
> -
> -#ifdef MODULE
> -#define CCSRBAR get_ccsrbar()
> -#else
> -#define CCSRBAR BOARD_CCSRBAR
> -#endif
> -
> -enum ppc_sys_devices {
> - MPC85xx_TSEC1,
> - MPC85xx_TSEC2,
> - MPC85xx_FEC,
> - MPC85xx_IIC1,
> - MPC85xx_DMA0,
> - MPC85xx_DMA1,
> - MPC85xx_DMA2,
> - MPC85xx_DMA3,
> - MPC85xx_DUART,
> - MPC85xx_PERFMON,
> - MPC85xx_SEC2,
> - MPC85xx_CPM_SPI,
> - MPC85xx_CPM_I2C,
> - MPC85xx_CPM_USB,
> - MPC85xx_CPM_SCC1,
> - MPC85xx_CPM_SCC2,
> - MPC85xx_CPM_SCC3,
> - MPC85xx_CPM_SCC4,
> - MPC85xx_CPM_FCC1,
> - MPC85xx_CPM_FCC2,
> - MPC85xx_CPM_FCC3,
> - MPC85xx_CPM_MCC1,
> - MPC85xx_CPM_MCC2,
> - MPC85xx_CPM_SMC1,
> - MPC85xx_CPM_SMC2,
> - MPC85xx_eTSEC1,
> - MPC85xx_eTSEC2,
> - MPC85xx_eTSEC3,
> - MPC85xx_eTSEC4,
> - MPC85xx_IIC2,
> - MPC85xx_MDIO,
> - NUM_PPC_SYS_DEVS,
> -};
> -
> -/* Internal interrupts are all Level Sensitive, and Positive
> Polarity */
> -#define MPC85XX_INTERNAL_IRQ_SENSES \
> - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 0 */ \
> - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 1 */ \
> - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 2 */ \
> - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 3 */ \
> - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 4 */ \
> - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 5 */ \
> - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 6 */ \
> - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 7 */ \
> - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 8 */ \
> - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 9 */ \
> - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 10 */ \
> - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 11 */ \
> - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 12 */ \
> - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 13 */ \
> - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 14 */ \
> - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 15 */ \
> - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 16 */ \
> - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 17 */ \
> - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 18 */ \
> - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 19 */ \
> - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 20 */ \
> - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 21 */ \
> - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 22 */ \
> - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 23 */ \
> - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 24 */ \
> - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 25 */ \
> - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 26 */ \
> - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 27 */ \
> - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 28 */ \
> - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 29 */ \
> - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 30 */ \
> - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 31 */ \
> - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 32 */ \
> - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 33 */ \
> - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 34 */ \
> - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 35 */ \
> - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 36 */ \
> - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 37 */ \
> - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 38 */ \
> - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 39 */ \
> - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 40 */ \
> - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 41 */ \
> - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 42 */ \
> - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 43 */ \
> - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 44 */ \
> - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 45 */ \
> - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 46 */ \
> - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE) /* Internal 47 */
> -
> -#endif /* CONFIG_85xx */
> -#endif /* __ASM_MPC85xx_H__ */
> -#endif /* __KERNEL__ */
> --
> 1.2.4
>
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-dev
^ permalink raw reply
* Re: [PATCH 10/15] powerpc: move asm/mpc83xx.h
From: Kumar Gala @ 2006-04-05 14:17 UTC (permalink / raw)
To: sfr; +Cc: linuxppc-dev, paulus
In-Reply-To: <11442138673826-git-send-email-sfr@canb.auug.org.au>
Nack. I was avoiding moving this header since it introduces a number
things that should only exist in arch/ppc.
- k
On Apr 5, 2006, at 12:10 AM, sfr@canb.auug.org.au wrote:
> From: Stephen Rothwell <sfr@canb.auug.org.au>
>
> Since the ARCH=powerpc build depends on this file, move it to
> include/asm-powerpc.
>
> Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
>
> ---
>
> include/asm-powerpc/mpc83xx.h | 115 ++++++++++++++++++++++++++++++
> +++++++++++
> include/asm-ppc/mpc83xx.h | 116
> -----------------------------------------
> 2 files changed, 115 insertions(+), 116 deletions(-)
> create mode 100644 include/asm-powerpc/mpc83xx.h
> delete mode 100644 include/asm-ppc/mpc83xx.h
>
> ce28e1e8654ad07cc23573a31f8cea992d41f9cc
> diff --git a/include/asm-powerpc/mpc83xx.h b/include/asm-powerpc/
> mpc83xx.h
> new file mode 100644
> index 0000000..da4b0fa
> --- /dev/null
> +++ b/include/asm-powerpc/mpc83xx.h
> @@ -0,0 +1,115 @@
> +#ifndef _ASM_POWERPC_MPC83XX_H
> +#define _ASM_POWERPC_MPC83XX_H
> +/*
> + * include/asm-ppc/mpc83xx.h
> + *
> + * MPC83xx definitions
> + *
> + * Maintainer: Kumar Gala <galak@kernel.crashing.org>
> + *
> + * Copyright 2005 Freescale Semiconductor, Inc
> + *
> + * This program is free software; you can redistribute it and/or
> modify it
> + * under the terms of the GNU General Public License as
> published by the
> + * Free Software Foundation; either version 2 of the License, or
> (at your
> + * option) any later version.
> + */
> +
> +#ifdef __KERNEL__
> +
> +#include <asm/mmu.h>
> +
> +#ifdef CONFIG_83xx
> +
> +#ifdef CONFIG_MPC834x_SYS
> +#include <platforms/83xx/mpc834x_sys.h>
> +#endif
> +
> +#define _IO_BASE isa_io_base
> +#define _ISA_MEM_BASE isa_mem_base
> +#ifdef CONFIG_PCI
> +#define PCI_DRAM_OFFSET pci_dram_offset
> +#else
> +#define PCI_DRAM_OFFSET 0
> +#endif
> +
> +/*
> + * The "residual" board information structure the boot loader passes
> + * into the kernel.
> + */
> +extern unsigned char __res[];
> +
> +/* Internal IRQs on MPC83xx OpenPIC */
> +/* Not all of these exist on all MPC83xx implementations */
> +
> +#ifndef MPC83xx_IPIC_IRQ_OFFSET
> +#define MPC83xx_IPIC_IRQ_OFFSET 0
> +#endif
> +
> +#define NR_IPIC_INTS 128
> +
> +#define MPC83xx_IRQ_UART1 ( 9 + MPC83xx_IPIC_IRQ_OFFSET)
> +#define MPC83xx_IRQ_UART2 (10 + MPC83xx_IPIC_IRQ_OFFSET)
> +#define MPC83xx_IRQ_SEC2 (11 + MPC83xx_IPIC_IRQ_OFFSET)
> +#define MPC83xx_IRQ_IIC1 (14 + MPC83xx_IPIC_IRQ_OFFSET)
> +#define MPC83xx_IRQ_IIC2 (15 + MPC83xx_IPIC_IRQ_OFFSET)
> +#define MPC83xx_IRQ_SPI (16 + MPC83xx_IPIC_IRQ_OFFSET)
> +#define MPC83xx_IRQ_EXT1 (17 + MPC83xx_IPIC_IRQ_OFFSET)
> +#define MPC83xx_IRQ_EXT2 (18 + MPC83xx_IPIC_IRQ_OFFSET)
> +#define MPC83xx_IRQ_EXT3 (19 + MPC83xx_IPIC_IRQ_OFFSET)
> +#define MPC83xx_IRQ_EXT4 (20 + MPC83xx_IPIC_IRQ_OFFSET)
> +#define MPC83xx_IRQ_EXT5 (21 + MPC83xx_IPIC_IRQ_OFFSET)
> +#define MPC83xx_IRQ_EXT6 (22 + MPC83xx_IPIC_IRQ_OFFSET)
> +#define MPC83xx_IRQ_EXT7 (23 + MPC83xx_IPIC_IRQ_OFFSET)
> +#define MPC83xx_IRQ_TSEC1_TX (32 + MPC83xx_IPIC_IRQ_OFFSET)
> +#define MPC83xx_IRQ_TSEC1_RX (33 + MPC83xx_IPIC_IRQ_OFFSET)
> +#define MPC83xx_IRQ_TSEC1_ERROR (34 + MPC83xx_IPIC_IRQ_OFFSET)
> +#define MPC83xx_IRQ_TSEC2_TX (35 + MPC83xx_IPIC_IRQ_OFFSET)
> +#define MPC83xx_IRQ_TSEC2_RX (36 + MPC83xx_IPIC_IRQ_OFFSET)
> +#define MPC83xx_IRQ_TSEC2_ERROR (37 + MPC83xx_IPIC_IRQ_OFFSET)
> +#define MPC83xx_IRQ_USB2_DR (38 + MPC83xx_IPIC_IRQ_OFFSET)
> +#define MPC83xx_IRQ_USB2_MPH (39 + MPC83xx_IPIC_IRQ_OFFSET)
> +#define MPC83xx_IRQ_EXT0 (48 + MPC83xx_IPIC_IRQ_OFFSET)
> +#define MPC83xx_IRQ_RTC_SEC (64 + MPC83xx_IPIC_IRQ_OFFSET)
> +#define MPC83xx_IRQ_PIT (65 + MPC83xx_IPIC_IRQ_OFFSET)
> +#define MPC83xx_IRQ_PCI1 (66 + MPC83xx_IPIC_IRQ_OFFSET)
> +#define MPC83xx_IRQ_PCI2 (67 + MPC83xx_IPIC_IRQ_OFFSET)
> +#define MPC83xx_IRQ_RTC_ALR (68 + MPC83xx_IPIC_IRQ_OFFSET)
> +#define MPC83xx_IRQ_MU (69 + MPC83xx_IPIC_IRQ_OFFSET)
> +#define MPC83xx_IRQ_SBA (70 + MPC83xx_IPIC_IRQ_OFFSET)
> +#define MPC83xx_IRQ_DMA (71 + MPC83xx_IPIC_IRQ_OFFSET)
> +#define MPC83xx_IRQ_GTM4 (72 + MPC83xx_IPIC_IRQ_OFFSET)
> +#define MPC83xx_IRQ_GTM8 (73 + MPC83xx_IPIC_IRQ_OFFSET)
> +#define MPC83xx_IRQ_GPIO1 (74 + MPC83xx_IPIC_IRQ_OFFSET)
> +#define MPC83xx_IRQ_GPIO2 (75 + MPC83xx_IPIC_IRQ_OFFSET)
> +#define MPC83xx_IRQ_DDR (76 + MPC83xx_IPIC_IRQ_OFFSET)
> +#define MPC83xx_IRQ_LBC (77 + MPC83xx_IPIC_IRQ_OFFSET)
> +#define MPC83xx_IRQ_GTM2 (78 + MPC83xx_IPIC_IRQ_OFFSET)
> +#define MPC83xx_IRQ_GTM6 (79 + MPC83xx_IPIC_IRQ_OFFSET)
> +#define MPC83xx_IRQ_PMC (80 + MPC83xx_IPIC_IRQ_OFFSET)
> +#define MPC83xx_IRQ_GTM3 (84 + MPC83xx_IPIC_IRQ_OFFSET)
> +#define MPC83xx_IRQ_GTM7 (85 + MPC83xx_IPIC_IRQ_OFFSET)
> +#define MPC83xx_IRQ_GTM1 (90 + MPC83xx_IPIC_IRQ_OFFSET)
> +#define MPC83xx_IRQ_GTM5 (91 + MPC83xx_IPIC_IRQ_OFFSET)
> +
> +#define MPC83xx_CCSRBAR_SIZE (1024*1024)
> +
> +/* Let modules/drivers get at immrbar (physical) */
> +extern phys_addr_t immrbar;
> +
> +enum ppc_sys_devices {
> + MPC83xx_TSEC1,
> + MPC83xx_TSEC2,
> + MPC83xx_IIC1,
> + MPC83xx_IIC2,
> + MPC83xx_DUART,
> + MPC83xx_SEC2,
> + MPC83xx_USB2_DR,
> + MPC83xx_USB2_MPH,
> + MPC83xx_MDIO,
> + NUM_PPC_SYS_DEVS,
> +};
> +
> +#endif /* CONFIG_83xx */
> +#endif /* __KERNEL__ */
> +#endif /* _ASM_POWERPC_MPC83XX_H */
> diff --git a/include/asm-ppc/mpc83xx.h b/include/asm-ppc/mpc83xx.h
> deleted file mode 100644
> index 3c23fc4..0000000
> --- a/include/asm-ppc/mpc83xx.h
> +++ /dev/null
> @@ -1,116 +0,0 @@
> -/*
> - * include/asm-ppc/mpc83xx.h
> - *
> - * MPC83xx definitions
> - *
> - * Maintainer: Kumar Gala <galak@kernel.crashing.org>
> - *
> - * Copyright 2005 Freescale Semiconductor, Inc
> - *
> - * This program is free software; you can redistribute it and/or
> modify it
> - * under the terms of the GNU General Public License as
> published by the
> - * Free Software Foundation; either version 2 of the License, or
> (at your
> - * option) any later version.
> - */
> -
> -#ifdef __KERNEL__
> -#ifndef __ASM_MPC83xx_H__
> -#define __ASM_MPC83xx_H__
> -
> -#include <linux/config.h>
> -#include <asm/mmu.h>
> -
> -#ifdef CONFIG_83xx
> -
> -#ifdef CONFIG_MPC834x_SYS
> -#include <platforms/83xx/mpc834x_sys.h>
> -#endif
> -
> -#define _IO_BASE isa_io_base
> -#define _ISA_MEM_BASE isa_mem_base
> -#ifdef CONFIG_PCI
> -#define PCI_DRAM_OFFSET pci_dram_offset
> -#else
> -#define PCI_DRAM_OFFSET 0
> -#endif
> -
> -/*
> - * The "residual" board information structure the boot loader passes
> - * into the kernel.
> - */
> -extern unsigned char __res[];
> -
> -/* Internal IRQs on MPC83xx OpenPIC */
> -/* Not all of these exist on all MPC83xx implementations */
> -
> -#ifndef MPC83xx_IPIC_IRQ_OFFSET
> -#define MPC83xx_IPIC_IRQ_OFFSET 0
> -#endif
> -
> -#define NR_IPIC_INTS 128
> -
> -#define MPC83xx_IRQ_UART1 ( 9 + MPC83xx_IPIC_IRQ_OFFSET)
> -#define MPC83xx_IRQ_UART2 (10 + MPC83xx_IPIC_IRQ_OFFSET)
> -#define MPC83xx_IRQ_SEC2 (11 + MPC83xx_IPIC_IRQ_OFFSET)
> -#define MPC83xx_IRQ_IIC1 (14 + MPC83xx_IPIC_IRQ_OFFSET)
> -#define MPC83xx_IRQ_IIC2 (15 + MPC83xx_IPIC_IRQ_OFFSET)
> -#define MPC83xx_IRQ_SPI (16 + MPC83xx_IPIC_IRQ_OFFSET)
> -#define MPC83xx_IRQ_EXT1 (17 + MPC83xx_IPIC_IRQ_OFFSET)
> -#define MPC83xx_IRQ_EXT2 (18 + MPC83xx_IPIC_IRQ_OFFSET)
> -#define MPC83xx_IRQ_EXT3 (19 + MPC83xx_IPIC_IRQ_OFFSET)
> -#define MPC83xx_IRQ_EXT4 (20 + MPC83xx_IPIC_IRQ_OFFSET)
> -#define MPC83xx_IRQ_EXT5 (21 + MPC83xx_IPIC_IRQ_OFFSET)
> -#define MPC83xx_IRQ_EXT6 (22 + MPC83xx_IPIC_IRQ_OFFSET)
> -#define MPC83xx_IRQ_EXT7 (23 + MPC83xx_IPIC_IRQ_OFFSET)
> -#define MPC83xx_IRQ_TSEC1_TX (32 + MPC83xx_IPIC_IRQ_OFFSET)
> -#define MPC83xx_IRQ_TSEC1_RX (33 + MPC83xx_IPIC_IRQ_OFFSET)
> -#define MPC83xx_IRQ_TSEC1_ERROR (34 + MPC83xx_IPIC_IRQ_OFFSET)
> -#define MPC83xx_IRQ_TSEC2_TX (35 + MPC83xx_IPIC_IRQ_OFFSET)
> -#define MPC83xx_IRQ_TSEC2_RX (36 + MPC83xx_IPIC_IRQ_OFFSET)
> -#define MPC83xx_IRQ_TSEC2_ERROR (37 + MPC83xx_IPIC_IRQ_OFFSET)
> -#define MPC83xx_IRQ_USB2_DR (38 + MPC83xx_IPIC_IRQ_OFFSET)
> -#define MPC83xx_IRQ_USB2_MPH (39 + MPC83xx_IPIC_IRQ_OFFSET)
> -#define MPC83xx_IRQ_EXT0 (48 + MPC83xx_IPIC_IRQ_OFFSET)
> -#define MPC83xx_IRQ_RTC_SEC (64 + MPC83xx_IPIC_IRQ_OFFSET)
> -#define MPC83xx_IRQ_PIT (65 + MPC83xx_IPIC_IRQ_OFFSET)
> -#define MPC83xx_IRQ_PCI1 (66 + MPC83xx_IPIC_IRQ_OFFSET)
> -#define MPC83xx_IRQ_PCI2 (67 + MPC83xx_IPIC_IRQ_OFFSET)
> -#define MPC83xx_IRQ_RTC_ALR (68 + MPC83xx_IPIC_IRQ_OFFSET)
> -#define MPC83xx_IRQ_MU (69 + MPC83xx_IPIC_IRQ_OFFSET)
> -#define MPC83xx_IRQ_SBA (70 + MPC83xx_IPIC_IRQ_OFFSET)
> -#define MPC83xx_IRQ_DMA (71 + MPC83xx_IPIC_IRQ_OFFSET)
> -#define MPC83xx_IRQ_GTM4 (72 + MPC83xx_IPIC_IRQ_OFFSET)
> -#define MPC83xx_IRQ_GTM8 (73 + MPC83xx_IPIC_IRQ_OFFSET)
> -#define MPC83xx_IRQ_GPIO1 (74 + MPC83xx_IPIC_IRQ_OFFSET)
> -#define MPC83xx_IRQ_GPIO2 (75 + MPC83xx_IPIC_IRQ_OFFSET)
> -#define MPC83xx_IRQ_DDR (76 + MPC83xx_IPIC_IRQ_OFFSET)
> -#define MPC83xx_IRQ_LBC (77 + MPC83xx_IPIC_IRQ_OFFSET)
> -#define MPC83xx_IRQ_GTM2 (78 + MPC83xx_IPIC_IRQ_OFFSET)
> -#define MPC83xx_IRQ_GTM6 (79 + MPC83xx_IPIC_IRQ_OFFSET)
> -#define MPC83xx_IRQ_PMC (80 + MPC83xx_IPIC_IRQ_OFFSET)
> -#define MPC83xx_IRQ_GTM3 (84 + MPC83xx_IPIC_IRQ_OFFSET)
> -#define MPC83xx_IRQ_GTM7 (85 + MPC83xx_IPIC_IRQ_OFFSET)
> -#define MPC83xx_IRQ_GTM1 (90 + MPC83xx_IPIC_IRQ_OFFSET)
> -#define MPC83xx_IRQ_GTM5 (91 + MPC83xx_IPIC_IRQ_OFFSET)
> -
> -#define MPC83xx_CCSRBAR_SIZE (1024*1024)
> -
> -/* Let modules/drivers get at immrbar (physical) */
> -extern phys_addr_t immrbar;
> -
> -enum ppc_sys_devices {
> - MPC83xx_TSEC1,
> - MPC83xx_TSEC2,
> - MPC83xx_IIC1,
> - MPC83xx_IIC2,
> - MPC83xx_DUART,
> - MPC83xx_SEC2,
> - MPC83xx_USB2_DR,
> - MPC83xx_USB2_MPH,
> - MPC83xx_MDIO,
> - NUM_PPC_SYS_DEVS,
> -};
> -
> -#endif /* CONFIG_83xx */
> -#endif /* __ASM_MPC83xx_H__ */
> -#endif /* __KERNEL__ */
> --
> 1.2.4
>
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-dev
^ permalink raw reply
* Re: [PATCH 12/15] powerpc: move asm/ocp_ids.h
From: Kumar Gala @ 2006-04-05 14:07 UTC (permalink / raw)
To: sfr; +Cc: linuxppc-dev, paulus
In-Reply-To: <1144213870220-git-send-email-sfr@canb.auug.org.au>
Nack. OCP should not exist in arch/powerpc so leave this header where
it is.
- k
On Apr 5, 2006, at 12:10 AM, sfr@canb.auug.org.au wrote:
> From: Stephen Rothwell <sfr@canb.auug.org.au>
>
> Since the ARCH=powerpc build depends on this file, move it to
> include/asm-powerpc.
>
> Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
>
> ---
>
> include/asm-powerpc/ocp_ids.h | 75 ++++++++++++++++++++++++++++++
> +++++++++++
> include/asm-ppc/ocp_ids.h | 73
> ----------------------------------------
> 2 files changed, 75 insertions(+), 73 deletions(-)
> create mode 100644 include/asm-powerpc/ocp_ids.h
> delete mode 100644 include/asm-ppc/ocp_ids.h
>
> a374f458829d868a3142bff918ef872e0ecff1a8
> diff --git a/include/asm-powerpc/ocp_ids.h b/include/asm-powerpc/
> ocp_ids.h
> new file mode 100644
> index 0000000..78e5906
> --- /dev/null
> +++ b/include/asm-powerpc/ocp_ids.h
> @@ -0,0 +1,75 @@
> +#ifndef _ASM_POWERPC_OCP_IDS_H
> +#define _ASM_POWERPC_OCP_IDS_H
> +/*
> + * OCP device ids based on the ideas from PCI
> + *
> + * The numbers below are almost completely arbitrary, and in fact
> + * strings might work better. -- paulus
> + *
> + * This program is free software; you can redistribute it and/or
> modify it
> + * under the terms of the GNU General Public License as
> published by the
> + * Free Software Foundation; either version 2 of the License, or
> (at your
> + * option) any later version.
> + */
> +
> +/*
> + * Vender device
> + * [xxxx] [xxxx]
> + *
> + * Keep in order, please
> + */
> +
> +/* Vendor IDs 0x0001 - 0xFFFF copied from pci_ids.h */
> +
> +#define OCP_VENDOR_INVALID 0x0000
> +#define OCP_VENDOR_ARM 0x0004
> +#define OCP_VENDOR_FREESCALE 0x1057
> +#define OCP_VENDOR_IBM 0x1014
> +#define OCP_VENDOR_MOTOROLA OCP_VENDOR_FREESCALE
> +#define OCP_VENDOR_XILINX 0x10ee
> +#define OCP_VENDOR_UNKNOWN 0xFFFF
> +
> +/* device identification */
> +
> +/* define type */
> +#define OCP_FUNC_INVALID 0x0000
> +
> +/* system 0x0001 - 0x001F */
> +
> +/* Timers 0x0020 - 0x002F */
> +
> +/* Serial 0x0030 - 0x006F*/
> +#define OCP_FUNC_16550 0x0031
> +#define OCP_FUNC_IIC 0x0032
> +#define OCP_FUNC_USB 0x0033
> +#define OCP_FUNC_PSC_UART 0x0034
> +
> +/* Memory devices 0x0090 - 0x009F */
> +#define OCP_FUNC_MAL 0x0090
> +#define OCP_FUNC_DMA 0x0091
> +
> +/* Display 0x00A0 - 0x00AF */
> +
> +/* Sound 0x00B0 - 0x00BF */
> +
> +/* Mass Storage 0x00C0 - 0xxCF */
> +#define OCP_FUNC_IDE 0x00C0
> +
> +/* Misc 0x00D0 - 0x00DF*/
> +#define OCP_FUNC_GPIO 0x00D0
> +#define OCP_FUNC_ZMII 0x00D1
> +#define OCP_FUNC_PERFMON 0x00D2 /* Performance Monitor */
> +#define OCP_FUNC_RGMII 0x00D3
> +#define OCP_FUNC_TAH 0x00D4
> +#define OCP_FUNC_SEC2 0x00D5 /* Crypto/Security 2.0 */
> +
> +/* Network 0x0200 - 0x02FF */
> +#define OCP_FUNC_EMAC 0x0200
> +#define OCP_FUNC_GFAR 0x0201 /* TSEC & FEC */
> +
> +/* Bridge devices 0xE00 - 0xEFF */
> +#define OCP_FUNC_OPB 0x0E00
> +
> +#define OCP_FUNC_UNKNOWN 0xFFFF
> +
> +#endif /* _ASM_POWERPC_OCP_IDS_H */
> diff --git a/include/asm-ppc/ocp_ids.h b/include/asm-ppc/ocp_ids.h
> deleted file mode 100644
> index 8ae4b31..0000000
> --- a/include/asm-ppc/ocp_ids.h
> +++ /dev/null
> @@ -1,73 +0,0 @@
> -/*
> - * ocp_ids.h
> - *
> - * OCP device ids based on the ideas from PCI
> - *
> - * The numbers below are almost completely arbitrary, and in fact
> - * strings might work better. -- paulus
> - *
> - * This program is free software; you can redistribute it and/or
> modify it
> - * under the terms of the GNU General Public License as
> published by the
> - * Free Software Foundation; either version 2 of the License, or
> (at your
> - * option) any later version.
> - */
> -
> -/*
> - * Vender device
> - * [xxxx] [xxxx]
> - *
> - * Keep in order, please
> - */
> -
> -/* Vendor IDs 0x0001 - 0xFFFF copied from pci_ids.h */
> -
> -#define OCP_VENDOR_INVALID 0x0000
> -#define OCP_VENDOR_ARM 0x0004
> -#define OCP_VENDOR_FREESCALE 0x1057
> -#define OCP_VENDOR_IBM 0x1014
> -#define OCP_VENDOR_MOTOROLA OCP_VENDOR_FREESCALE
> -#define OCP_VENDOR_XILINX 0x10ee
> -#define OCP_VENDOR_UNKNOWN 0xFFFF
> -
> -/* device identification */
> -
> -/* define type */
> -#define OCP_FUNC_INVALID 0x0000
> -
> -/* system 0x0001 - 0x001F */
> -
> -/* Timers 0x0020 - 0x002F */
> -
> -/* Serial 0x0030 - 0x006F*/
> -#define OCP_FUNC_16550 0x0031
> -#define OCP_FUNC_IIC 0x0032
> -#define OCP_FUNC_USB 0x0033
> -#define OCP_FUNC_PSC_UART 0x0034
> -
> -/* Memory devices 0x0090 - 0x009F */
> -#define OCP_FUNC_MAL 0x0090
> -#define OCP_FUNC_DMA 0x0091
> -
> -/* Display 0x00A0 - 0x00AF */
> -
> -/* Sound 0x00B0 - 0x00BF */
> -
> -/* Mass Storage 0x00C0 - 0xxCF */
> -#define OCP_FUNC_IDE 0x00C0
> -
> -/* Misc 0x00D0 - 0x00DF*/
> -#define OCP_FUNC_GPIO 0x00D0
> -#define OCP_FUNC_ZMII 0x00D1
> -#define OCP_FUNC_PERFMON 0x00D2 /* Performance Monitor */
> -#define OCP_FUNC_RGMII 0x00D3
> -#define OCP_FUNC_TAH 0x00D4
> -#define OCP_FUNC_SEC2 0x00D5 /* Crypto/Security 2.0 */
> -
> -/* Network 0x0200 - 0x02FF */
> -#define OCP_FUNC_EMAC 0x0200
> -#define OCP_FUNC_GFAR 0x0201 /* TSEC & FEC */
> -
> -/* Bridge devices 0xE00 - 0xEFF */
> -#define OCP_FUNC_OPB 0x0E00
> -
> -#define OCP_FUNC_UNKNOWN 0xFFFF
> --
> 1.2.4
>
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-dev
^ permalink raw reply
* Re: [PATCH 11/15] powerpc: move asm/ocp.h
From: Kumar Gala @ 2006-04-05 14:07 UTC (permalink / raw)
To: sfr; +Cc: linuxppc-dev, paulus
In-Reply-To: <1144213868772-git-send-email-sfr@canb.auug.org.au>
Nack. OCP should not exist in arch/powerpc so leave this header where
it is.
- k
On Apr 5, 2006, at 12:10 AM, sfr@canb.auug.org.au wrote:
> From: Stephen Rothwell <sfr@canb.auug.org.au>
>
> Since the ARCH=powerpc build depends on this file, move it to
> include/asm-powerpc.
>
> Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
>
> ---
>
> include/asm-powerpc/ocp.h | 206 ++++++++++++++++++++++++++++++++++
> +++++++++++
> include/asm-ppc/ocp.h | 207
> ---------------------------------------------
> 2 files changed, 206 insertions(+), 207 deletions(-)
> create mode 100644 include/asm-powerpc/ocp.h
> delete mode 100644 include/asm-ppc/ocp.h
>
> c7b417812dc2ebece32356c0a5e93966de9ba2cd
> diff --git a/include/asm-powerpc/ocp.h b/include/asm-powerpc/ocp.h
> new file mode 100644
> index 0000000..8916c52
> --- /dev/null
> +++ b/include/asm-powerpc/ocp.h
> @@ -0,0 +1,206 @@
> +#ifndef _ASM_POWERPC_OCP_H
> +#define _ASM_POWERPC_OCP_H
> +/*
> + * ocp.h
> + *
> + * (c) Benjamin Herrenschmidt (benh@kernel.crashing.org)
> + * Mipsys - France
> + *
> + * Derived from work (c) Armin Kuster akuster@pacbell.net
> + *
> + * Additional support and port to 2.6 LDM/sysfs by
> + * Matt Porter <mporter@kernel.crashing.org>
> + * Copyright 2003-2004 MontaVista Software, Inc.
> + *
> + * This program is free software; you can redistribute it and/or
> modify it
> + * under the terms of the GNU General Public License as
> published by the
> + * Free Software Foundation; either version 2 of the License, or
> (at your
> + * option) any later version.
> + *
> + * TODO: - Add get/put interface & fixup locking to provide same
> API for
> + * 2.4 and 2.5
> + * - Rework PM callbacks
> + */
> +
> +#ifdef __KERNEL__
> +
> +#include <linux/init.h>
> +#include <linux/list.h>
> +#include <linux/devfs_fs_kernel.h>
> +#include <linux/device.h>
> +
> +#include <asm/mmu.h>
> +#include <asm/ocp_ids.h>
> +#include <asm/rwsem.h>
> +#include <asm/semaphore.h>
> +
> +#ifdef CONFIG_PPC_OCP
> +
> +#define OCP_MAX_IRQS 7
> +#define MAX_EMACS 4
> +#define OCP_IRQ_NA -1 /* used when ocp device does not have an irq */
> +#define OCP_IRQ_MUL -2 /* used for ocp devices with multiply irqs */
> +#define OCP_NULL_TYPE -1 /* used to mark end of list */
> +#define OCP_CPM_NA 0 /* No Clock or Power Management avaliable */
> +#define OCP_PADDR_NA 0 /* No MMIO registers */
> +
> +#define OCP_ANY_ID (~0)
> +#define OCP_ANY_INDEX -1
> +
> +extern struct list_head ocp_devices;
> +extern struct rw_semaphore ocp_devices_sem;
> +
> +struct ocp_device_id {
> + unsigned int vendor, function; /* Vendor and function ID or
> OCP_ANY_ID */
> + unsigned long driver_data; /* Data private to the driver */
> +};
> +
> +
> +/*
> + * Static definition of an OCP device.
> + *
> + * @vendor: Vendor code. It is _STRONGLY_ discouraged to use
> + * the vendor code as a way to match a unique device,
> + * though I kept that possibility open, you should
> + * really define different function codes for different
> + * device types
> + * @function: This is the function code for this device.
> + * @index: This index is used for mapping the Nth function of a
> + * given core. This is typically used for cross-driver
> + * matching, like looking for a given MAL or ZMII from
> + * an EMAC or for getting to the proper set of DCRs.
> + * Indices are no longer magically calculated based on
> + * structure ordering, they have to be actually coded
> + * into the ocp_def to avoid any possible confusion
> + * I _STRONGLY_ (again ? wow !) encourage anybody relying
> + * on index mapping to encode the "target" index in an
> + * associated structure pointed to by "additions", see
> + * how it's done for the EMAC driver.
> + * @paddr: Device physical address (may not mean anything...)
> + * @irq: Interrupt line for this device (TODO: think about
> making
> + * an array with this)
> + * @pm: Currently, contains the bitmask in CPMFR DCR for
> the device
> + * @additions: Optionally points to a function specific structure
> + * providing additional informations for a given device
> + * instance. It's currently used by the EMAC driver
> for MAL
> + * channel & ZMII port mapping among others.
> + * @show: Optionally points to a function specific structure
> + * providing a sysfs show routine for additions fields.
> + */
> +struct ocp_def {
> + unsigned int vendor;
> + unsigned int function;
> + int index;
> + phys_addr_t paddr;
> + int irq;
> + unsigned long pm;
> + void *additions;
> + void (*show)(struct device *);
> +};
> +
> +
> +/* Struct for a given device instance */
> +struct ocp_device {
> + struct list_head link;
> + char name[80]; /* device name */
> + struct ocp_def *def; /* device definition */
> + void *drvdata; /* driver data for this device */
> + struct ocp_driver *driver;
> + u32 current_state; /* Current operating state. In ACPI-speak,
> + this is D0-D3, D0 being fully functional,
> + and D3 being off. */
> + struct device dev;
> +};
> +
> +struct ocp_driver {
> + struct list_head node;
> + char *name;
> + const struct ocp_device_id *id_table; /* NULL if wants all
> devices */
> + int (*probe) (struct ocp_device *dev); /* New device inserted */
> + void (*remove) (struct ocp_device *dev); /* Device removed (NULL
> if not a hot-plug capable driver) */
> + int (*suspend) (struct ocp_device *dev, pm_message_t state); /*
> Device suspended */
> + int (*resume) (struct ocp_device *dev); /*
> Device woken up */
> + struct device_driver driver;
> +};
> +
> +#define to_ocp_dev(n) container_of(n, struct ocp_device, dev)
> +#define to_ocp_drv(n) container_of(n, struct ocp_driver, driver)
> +
> +/* Similar to the helpers above, these manipulate per-ocp_dev
> + * driver-specific data. Currently stored as ocp_dev::ocpdev,
> + * a void pointer, but it is not present on older kernels.
> + */
> +static inline void *
> +ocp_get_drvdata(struct ocp_device *pdev)
> +{
> + return pdev->drvdata;
> +}
> +
> +static inline void
> +ocp_set_drvdata(struct ocp_device *pdev, void *data)
> +{
> + pdev->drvdata = data;
> +}
> +
> +#if defined (CONFIG_PM)
> +/*
> + * This is right for the IBM 405 and 440 but will need to be
> + * generalized if the OCP stuff gets used on other processors.
> + */
> +static inline void
> +ocp_force_power_off(struct ocp_device *odev)
> +{
> + mtdcr(DCRN_CPMFR, mfdcr(DCRN_CPMFR) | odev->def->pm);
> +}
> +
> +static inline void
> +ocp_force_power_on(struct ocp_device *odev)
> +{
> + mtdcr(DCRN_CPMFR, mfdcr(DCRN_CPMFR) & ~odev->def->pm);
> +}
> +#else
> +#define ocp_force_power_off(x) (void)(x)
> +#define ocp_force_power_on(x) (void)(x)
> +#endif
> +
> +/* Register/Unregister an OCP driver */
> +extern int ocp_register_driver(struct ocp_driver *drv);
> +extern void ocp_unregister_driver(struct ocp_driver *drv);
> +
> +/* Build list of devices */
> +extern int ocp_early_init(void) __init;
> +
> +/* Find a device by index */
> +extern struct ocp_device *ocp_find_device(unsigned int vendor,
> unsigned int function, int index);
> +
> +/* Get a def by index */
> +extern struct ocp_def *ocp_get_one_device(unsigned int vendor,
> unsigned int function, int index);
> +
> +/* Add a device by index */
> +extern int ocp_add_one_device(struct ocp_def *def);
> +
> +/* Remove a device by index */
> +extern int ocp_remove_one_device(unsigned int vendor, unsigned int
> function, int index);
> +
> +/* Iterate over devices and execute a routine */
> +extern void ocp_for_each_device(void(*callback)(struct ocp_device
> *, void *arg), void *arg);
> +
> +/* Sysfs support */
> +#define OCP_SYSFS_ADDTL(type, format, name, field) \
> +static ssize_t \
> +show_##name##_##field(struct device *dev, struct device_attribute
> *attr, char *buf) \
> +{ \
> + struct ocp_device *odev = to_ocp_dev(dev); \
> + type *add = odev->def->additions; \
> + \
> + return sprintf(buf, format, add->field); \
> +} \
> +static DEVICE_ATTR(name##_##field, S_IRUGO, show_##name##_##field,
> NULL);
> +
> +#ifdef CONFIG_IBM_OCP
> +#include <asm/ibm_ocp.h>
> +#endif
> +
> +#endif /* CONFIG_PPC_OCP */
> +#endif /* __KERNEL__ */
> +#endif /* _ASM_POWERPC_OCP_H */
> diff --git a/include/asm-ppc/ocp.h b/include/asm-ppc/ocp.h
> deleted file mode 100644
> index 983116f..0000000
> --- a/include/asm-ppc/ocp.h
> +++ /dev/null
> @@ -1,207 +0,0 @@
> -/*
> - * ocp.h
> - *
> - * (c) Benjamin Herrenschmidt (benh@kernel.crashing.org)
> - * Mipsys - France
> - *
> - * Derived from work (c) Armin Kuster akuster@pacbell.net
> - *
> - * Additional support and port to 2.6 LDM/sysfs by
> - * Matt Porter <mporter@kernel.crashing.org>
> - * Copyright 2003-2004 MontaVista Software, Inc.
> - *
> - * This program is free software; you can redistribute it and/or
> modify it
> - * under the terms of the GNU General Public License as
> published by the
> - * Free Software Foundation; either version 2 of the License, or
> (at your
> - * option) any later version.
> - *
> - * TODO: - Add get/put interface & fixup locking to provide same
> API for
> - * 2.4 and 2.5
> - * - Rework PM callbacks
> - */
> -
> -#ifdef __KERNEL__
> -#ifndef __OCP_H__
> -#define __OCP_H__
> -
> -#include <linux/init.h>
> -#include <linux/list.h>
> -#include <linux/config.h>
> -#include <linux/devfs_fs_kernel.h>
> -#include <linux/device.h>
> -
> -#include <asm/mmu.h>
> -#include <asm/ocp_ids.h>
> -#include <asm/rwsem.h>
> -#include <asm/semaphore.h>
> -
> -#ifdef CONFIG_PPC_OCP
> -
> -#define OCP_MAX_IRQS 7
> -#define MAX_EMACS 4
> -#define OCP_IRQ_NA -1 /* used when ocp device does not have an irq */
> -#define OCP_IRQ_MUL -2 /* used for ocp devices with multiply irqs */
> -#define OCP_NULL_TYPE -1 /* used to mark end of list */
> -#define OCP_CPM_NA 0 /* No Clock or Power Management avaliable */
> -#define OCP_PADDR_NA 0 /* No MMIO registers */
> -
> -#define OCP_ANY_ID (~0)
> -#define OCP_ANY_INDEX -1
> -
> -extern struct list_head ocp_devices;
> -extern struct rw_semaphore ocp_devices_sem;
> -
> -struct ocp_device_id {
> - unsigned int vendor, function; /* Vendor and function ID or
> OCP_ANY_ID */
> - unsigned long driver_data; /* Data private to the driver */
> -};
> -
> -
> -/*
> - * Static definition of an OCP device.
> - *
> - * @vendor: Vendor code. It is _STRONGLY_ discouraged to use
> - * the vendor code as a way to match a unique device,
> - * though I kept that possibility open, you should
> - * really define different function codes for different
> - * device types
> - * @function: This is the function code for this device.
> - * @index: This index is used for mapping the Nth function of a
> - * given core. This is typically used for cross-driver
> - * matching, like looking for a given MAL or ZMII from
> - * an EMAC or for getting to the proper set of DCRs.
> - * Indices are no longer magically calculated based on
> - * structure ordering, they have to be actually coded
> - * into the ocp_def to avoid any possible confusion
> - * I _STRONGLY_ (again ? wow !) encourage anybody relying
> - * on index mapping to encode the "target" index in an
> - * associated structure pointed to by "additions", see
> - * how it's done for the EMAC driver.
> - * @paddr: Device physical address (may not mean anything...)
> - * @irq: Interrupt line for this device (TODO: think about
> making
> - * an array with this)
> - * @pm: Currently, contains the bitmask in CPMFR DCR for
> the device
> - * @additions: Optionally points to a function specific structure
> - * providing additional informations for a given device
> - * instance. It's currently used by the EMAC driver
> for MAL
> - * channel & ZMII port mapping among others.
> - * @show: Optionally points to a function specific structure
> - * providing a sysfs show routine for additions fields.
> - */
> -struct ocp_def {
> - unsigned int vendor;
> - unsigned int function;
> - int index;
> - phys_addr_t paddr;
> - int irq;
> - unsigned long pm;
> - void *additions;
> - void (*show)(struct device *);
> -};
> -
> -
> -/* Struct for a given device instance */
> -struct ocp_device {
> - struct list_head link;
> - char name[80]; /* device name */
> - struct ocp_def *def; /* device definition */
> - void *drvdata; /* driver data for this device */
> - struct ocp_driver *driver;
> - u32 current_state; /* Current operating state. In ACPI-speak,
> - this is D0-D3, D0 being fully functional,
> - and D3 being off. */
> - struct device dev;
> -};
> -
> -struct ocp_driver {
> - struct list_head node;
> - char *name;
> - const struct ocp_device_id *id_table; /* NULL if wants all
> devices */
> - int (*probe) (struct ocp_device *dev); /* New device inserted */
> - void (*remove) (struct ocp_device *dev); /* Device removed (NULL
> if not a hot-plug capable driver) */
> - int (*suspend) (struct ocp_device *dev, pm_message_t state); /*
> Device suspended */
> - int (*resume) (struct ocp_device *dev); /*
> Device woken up */
> - struct device_driver driver;
> -};
> -
> -#define to_ocp_dev(n) container_of(n, struct ocp_device, dev)
> -#define to_ocp_drv(n) container_of(n, struct ocp_driver, driver)
> -
> -/* Similar to the helpers above, these manipulate per-ocp_dev
> - * driver-specific data. Currently stored as ocp_dev::ocpdev,
> - * a void pointer, but it is not present on older kernels.
> - */
> -static inline void *
> -ocp_get_drvdata(struct ocp_device *pdev)
> -{
> - return pdev->drvdata;
> -}
> -
> -static inline void
> -ocp_set_drvdata(struct ocp_device *pdev, void *data)
> -{
> - pdev->drvdata = data;
> -}
> -
> -#if defined (CONFIG_PM)
> -/*
> - * This is right for the IBM 405 and 440 but will need to be
> - * generalized if the OCP stuff gets used on other processors.
> - */
> -static inline void
> -ocp_force_power_off(struct ocp_device *odev)
> -{
> - mtdcr(DCRN_CPMFR, mfdcr(DCRN_CPMFR) | odev->def->pm);
> -}
> -
> -static inline void
> -ocp_force_power_on(struct ocp_device *odev)
> -{
> - mtdcr(DCRN_CPMFR, mfdcr(DCRN_CPMFR) & ~odev->def->pm);
> -}
> -#else
> -#define ocp_force_power_off(x) (void)(x)
> -#define ocp_force_power_on(x) (void)(x)
> -#endif
> -
> -/* Register/Unregister an OCP driver */
> -extern int ocp_register_driver(struct ocp_driver *drv);
> -extern void ocp_unregister_driver(struct ocp_driver *drv);
> -
> -/* Build list of devices */
> -extern int ocp_early_init(void) __init;
> -
> -/* Find a device by index */
> -extern struct ocp_device *ocp_find_device(unsigned int vendor,
> unsigned int function, int index);
> -
> -/* Get a def by index */
> -extern struct ocp_def *ocp_get_one_device(unsigned int vendor,
> unsigned int function, int index);
> -
> -/* Add a device by index */
> -extern int ocp_add_one_device(struct ocp_def *def);
> -
> -/* Remove a device by index */
> -extern int ocp_remove_one_device(unsigned int vendor, unsigned int
> function, int index);
> -
> -/* Iterate over devices and execute a routine */
> -extern void ocp_for_each_device(void(*callback)(struct ocp_device
> *, void *arg), void *arg);
> -
> -/* Sysfs support */
> -#define OCP_SYSFS_ADDTL(type, format, name, field) \
> -static ssize_t \
> -show_##name##_##field(struct device *dev, struct device_attribute
> *attr, char *buf) \
> -{ \
> - struct ocp_device *odev = to_ocp_dev(dev); \
> - type *add = odev->def->additions; \
> - \
> - return sprintf(buf, format, add->field); \
> -} \
> -static DEVICE_ATTR(name##_##field, S_IRUGO, show_##name##_##field,
> NULL);
> -
> -#ifdef CONFIG_IBM_OCP
> -#include <asm/ibm_ocp.h>
> -#endif
> -
> -#endif /* CONFIG_PPC_OCP */
> -#endif /* __OCP_H__ */
> -#endif /* __KERNEL__ */
> --
> 1.2.4
>
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-dev
^ permalink raw reply
* Re: [PATCH 08/15] powerpc: move asm/open_pic.h
From: Kumar Gala @ 2006-04-05 14:07 UTC (permalink / raw)
To: sfr; +Cc: linuxppc-dev, paulus
In-Reply-To: <11442138641124-git-send-email-sfr@canb.auug.org.au>
I'd need to check, but I dont think we should move this since arch/
powerpc is using mpic to handle openpic and I'm guessing it has its
own headers.
- k
On Apr 5, 2006, at 12:10 AM, sfr@canb.auug.org.au wrote:
> From: Stephen Rothwell <sfr@canb.auug.org.au>
>
> Since the ARCH=powerpc build depends on this file, move it to
> include/asm-powerpc.
>
> Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
>
> ---
>
> include/asm-powerpc/open_pic.h | 99 +++++++++++++++++++++++++++++
> +++++++++++
> include/asm-ppc/open_pic.h | 99
> ----------------------------------------
> 2 files changed, 99 insertions(+), 99 deletions(-)
> create mode 100644 include/asm-powerpc/open_pic.h
> delete mode 100644 include/asm-ppc/open_pic.h
>
> 54316678b9e6aad8349f2df50dadd2597b675804
> diff --git a/include/asm-powerpc/open_pic.h b/include/asm-powerpc/
> open_pic.h
> new file mode 100644
> index 0000000..3f197cf
> --- /dev/null
> +++ b/include/asm-powerpc/open_pic.h
> @@ -0,0 +1,99 @@
> +#ifndef _ASM_POWERPC_OPEN_PIC_H
> +#define _ASM_POWERPC_OPEN_PIC_H
> +
> +/*
> + * include/asm-ppc/open_pic.h -- OpenPIC Interrupt Handling
> + *
> + * Copyright (C) 1997 Geert Uytterhoeven
> + *
> + * This file is subject to the terms and conditions of the GNU
> General Public
> + * License. See the file COPYING in the main directory of this
> archive
> + * for more details.
> + *
> + */
> +
> +#include <linux/irq.h>
> +
> +#define OPENPIC_SIZE 0x40000
> +
> +/*
> + * Non-offset'ed vector numbers
> + */
> +
> +#define OPENPIC_VEC_TIMER 110 /* and up */
> +#define OPENPIC_VEC_IPI 118 /* and up */
> +#define OPENPIC_VEC_SPURIOUS 255
> +
> +/* Priorities */
> +#define OPENPIC_PRIORITY_IPI_BASE 10
> +#define OPENPIC_PRIORITY_DEFAULT 4
> +#define OPENPIC_PRIORITY_NMI 9
> +
> +/* OpenPIC IRQ controller structure */
> +extern struct hw_interrupt_type open_pic;
> +
> +/* OpenPIC IPI controller structure */
> +#ifdef CONFIG_SMP
> +extern struct hw_interrupt_type open_pic_ipi;
> +#endif /* CONFIG_SMP */
> +
> +extern u_int OpenPIC_NumInitSenses;
> +extern u_char *OpenPIC_InitSenses;
> +extern void __iomem * OpenPIC_Addr;
> +extern int epic_serial_mode;
> +
> +/* Exported functions */
> +extern void openpic_set_sources(int first_irq, int num_irqs, void
> __iomem *isr);
> +extern void openpic_init(int linux_irq_offset);
> +extern void openpic_init_nmi_irq(u_int irq);
> +extern void openpic_set_irq_priority(u_int irq, u_int pri);
> +extern void openpic_hookup_cascade(u_int irq, char *name,
> + int (*cascade_fn)(struct pt_regs *));
> +extern u_int openpic_irq(void);
> +extern void openpic_eoi(void);
> +extern void openpic_request_IPIs(void);
> +extern void do_openpic_setup_cpu(void);
> +extern int openpic_get_irq(struct pt_regs *regs);
> +extern void openpic_reset_processor_phys(u_int cpumask);
> +extern void openpic_setup_ISU(int isu_num, unsigned long addr);
> +extern void openpic_cause_IPI(u_int ipi, cpumask_t cpumask);
> +extern void smp_openpic_message_pass(int target, int msg);
> +extern void openpic_set_k2_cascade(int irq);
> +extern void openpic_set_priority(u_int pri);
> +extern u_int openpic_get_priority(void);
> +
> +extern inline int openpic_to_irq(int irq)
> +{
> + /* IRQ 0 usually means 'disabled'.. don't mess with it
> + * exceptions to this (sandpoint maybe?)
> + * shouldn't use openpic_to_irq
> + */
> + if (irq != 0){
> + return irq += NUM_8259_INTERRUPTS;
> + } else {
> + return 0;
> + }
> +}
> +/* Support for second openpic on G5 macs */
> +
> +// FIXME: To be replaced by sane cascaded controller management */
> +
> +#define PMAC_OPENPIC2_OFFSET 128
> +
> +#define OPENPIC2_VEC_TIMER 110 /* and up */
> +#define OPENPIC2_VEC_IPI 118 /* and up */
> +#define OPENPIC2_VEC_SPURIOUS 127
> +
> +
> +extern void* OpenPIC2_Addr;
> +
> +/* Exported functions */
> +extern void openpic2_set_sources(int first_irq, int num_irqs, void
> *isr);
> +extern void openpic2_init(int linux_irq_offset);
> +extern void openpic2_init_nmi_irq(u_int irq);
> +extern u_int openpic2_irq(void);
> +extern void openpic2_eoi(void);
> +extern int openpic2_get_irq(struct pt_regs *regs);
> +extern void openpic2_setup_ISU(int isu_num, unsigned long addr);
> +
> +#endif /* _ASM_POWERPC_OPEN_PIC_H */
> diff --git a/include/asm-ppc/open_pic.h b/include/asm-ppc/open_pic.h
> deleted file mode 100644
> index ec2f466..0000000
> --- a/include/asm-ppc/open_pic.h
> +++ /dev/null
> @@ -1,99 +0,0 @@
> -/*
> - * include/asm-ppc/open_pic.h -- OpenPIC Interrupt Handling
> - *
> - * Copyright (C) 1997 Geert Uytterhoeven
> - *
> - * This file is subject to the terms and conditions of the GNU
> General Public
> - * License. See the file COPYING in the main directory of this
> archive
> - * for more details.
> - *
> - */
> -
> -#ifndef _PPC_KERNEL_OPEN_PIC_H
> -#define _PPC_KERNEL_OPEN_PIC_H
> -
> -#include <linux/config.h>
> -#include <linux/irq.h>
> -
> -#define OPENPIC_SIZE 0x40000
> -
> -/*
> - * Non-offset'ed vector numbers
> - */
> -
> -#define OPENPIC_VEC_TIMER 110 /* and up */
> -#define OPENPIC_VEC_IPI 118 /* and up */
> -#define OPENPIC_VEC_SPURIOUS 255
> -
> -/* Priorities */
> -#define OPENPIC_PRIORITY_IPI_BASE 10
> -#define OPENPIC_PRIORITY_DEFAULT 4
> -#define OPENPIC_PRIORITY_NMI 9
> -
> -/* OpenPIC IRQ controller structure */
> -extern struct hw_interrupt_type open_pic;
> -
> -/* OpenPIC IPI controller structure */
> -#ifdef CONFIG_SMP
> -extern struct hw_interrupt_type open_pic_ipi;
> -#endif /* CONFIG_SMP */
> -
> -extern u_int OpenPIC_NumInitSenses;
> -extern u_char *OpenPIC_InitSenses;
> -extern void __iomem * OpenPIC_Addr;
> -extern int epic_serial_mode;
> -
> -/* Exported functions */
> -extern void openpic_set_sources(int first_irq, int num_irqs, void
> __iomem *isr);
> -extern void openpic_init(int linux_irq_offset);
> -extern void openpic_init_nmi_irq(u_int irq);
> -extern void openpic_set_irq_priority(u_int irq, u_int pri);
> -extern void openpic_hookup_cascade(u_int irq, char *name,
> - int (*cascade_fn)(struct pt_regs *));
> -extern u_int openpic_irq(void);
> -extern void openpic_eoi(void);
> -extern void openpic_request_IPIs(void);
> -extern void do_openpic_setup_cpu(void);
> -extern int openpic_get_irq(struct pt_regs *regs);
> -extern void openpic_reset_processor_phys(u_int cpumask);
> -extern void openpic_setup_ISU(int isu_num, unsigned long addr);
> -extern void openpic_cause_IPI(u_int ipi, cpumask_t cpumask);
> -extern void smp_openpic_message_pass(int target, int msg);
> -extern void openpic_set_k2_cascade(int irq);
> -extern void openpic_set_priority(u_int pri);
> -extern u_int openpic_get_priority(void);
> -
> -extern inline int openpic_to_irq(int irq)
> -{
> - /* IRQ 0 usually means 'disabled'.. don't mess with it
> - * exceptions to this (sandpoint maybe?)
> - * shouldn't use openpic_to_irq
> - */
> - if (irq != 0){
> - return irq += NUM_8259_INTERRUPTS;
> - } else {
> - return 0;
> - }
> -}
> -/* Support for second openpic on G5 macs */
> -
> -// FIXME: To be replaced by sane cascaded controller management */
> -
> -#define PMAC_OPENPIC2_OFFSET 128
> -
> -#define OPENPIC2_VEC_TIMER 110 /* and up */
> -#define OPENPIC2_VEC_IPI 118 /* and up */
> -#define OPENPIC2_VEC_SPURIOUS 127
> -
> -
> -extern void* OpenPIC2_Addr;
> -
> -/* Exported functions */
> -extern void openpic2_set_sources(int first_irq, int num_irqs, void
> *isr);
> -extern void openpic2_init(int linux_irq_offset);
> -extern void openpic2_init_nmi_irq(u_int irq);
> -extern u_int openpic2_irq(void);
> -extern void openpic2_eoi(void);
> -extern int openpic2_get_irq(struct pt_regs *regs);
> -extern void openpic2_setup_ISU(int isu_num, unsigned long addr);
> -#endif /* _PPC_KERNEL_OPEN_PIC_H */
> --
> 1.2.4
>
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-dev
^ permalink raw reply
* Re: [PATCH 04/15] powerpc: move asm/bootinfo.h
From: Kumar Gala @ 2006-04-05 14:05 UTC (permalink / raw)
To: sfr; +Cc: linuxppc-dev, paulus
In-Reply-To: <11442138551674-git-send-email-sfr@canb.auug.org.au>
Nack, we are using the flat dev tree so old boot methods should stay
in arch/ppc.
- k
On Apr 5, 2006, at 12:10 AM, sfr@canb.auug.org.au wrote:
> From: Stephen Rothwell <sfr@canb.auug.org.au>
>
> Since files in arch/powerpc now depend on asm/bootinfo.h,
> move it to include/asm-powerpc.
>
> Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
>
> ---
>
> include/asm-powerpc/bootinfo.h | 52 +++++++++++++++++++++++++++++
> +++++++++++
> include/asm-ppc/bootinfo.h | 52
> ----------------------------------------
> 2 files changed, 52 insertions(+), 52 deletions(-)
> create mode 100644 include/asm-powerpc/bootinfo.h
> delete mode 100644 include/asm-ppc/bootinfo.h
>
> 355987a8cf0cf4b644e83b8268a9a34cf4524ee0
> diff --git a/include/asm-powerpc/bootinfo.h b/include/asm-powerpc/
> bootinfo.h
> new file mode 100644
> index 0000000..231c534
> --- /dev/null
> +++ b/include/asm-powerpc/bootinfo.h
> @@ -0,0 +1,52 @@
> +#ifndef _ASM_POWERPC_BOOTINFO_H
> +#define _ASM_POWERPC_BOOTINFO_H
> +
> +/*
> + * Non-machine dependent bootinfo structure. Basic idea
> + * borrowed from the m68k.
> + *
> + * Copyright (C) 1999 Cort Dougan <cort@ppc.kernel.org>
> + */
> +
> +#ifdef __KERNEL__
> +
> +#include <asm/page.h>
> +
> +#if defined(CONFIG_APUS) && !defined(__BOOTER__)
> +#include <asm-m68k/bootinfo.h>
> +#else
> +
> +struct bi_record {
> + unsigned long tag; /* tag ID */
> + unsigned long size; /* size of record (in bytes) */
> + unsigned long data[0]; /* data */
> +};
> +
> +#define BI_FIRST 0x1010 /* first record - marker */
> +#define BI_LAST 0x1011 /* last record - marker */
> +#define BI_CMD_LINE 0x1012
> +#define BI_BOOTLOADER_ID 0x1013
> +#define BI_INITRD 0x1014
> +#define BI_SYSMAP 0x1015
> +#define BI_MACHTYPE 0x1016
> +#define BI_MEMSIZE 0x1017
> +#define BI_BOARD_INFO 0x1018
> +
> +extern struct bi_record *find_bootinfo(void);
> +extern void bootinfo_init(struct bi_record *rec);
> +extern void bootinfo_append(unsigned long tag, unsigned long size,
> void * data);
> +extern void parse_bootinfo(struct bi_record *rec);
> +extern unsigned long boot_mem_size;
> +
> +static inline struct bi_record *
> +bootinfo_addr(unsigned long offset)
> +{
> +
> + return (struct bi_record *)_ALIGN((offset) + (1 << 20) - 1,
> + (1 << 20));
> +}
> +#endif /* CONFIG_APUS */
> +
> +
> +#endif /* __KERNEL__ */
> +#endif /* _ASM_POWERPC_BOOTINFO_H */
> diff --git a/include/asm-ppc/bootinfo.h b/include/asm-ppc/bootinfo.h
> deleted file mode 100644
> index 93d955c..0000000
> --- a/include/asm-ppc/bootinfo.h
> +++ /dev/null
> @@ -1,52 +0,0 @@
> -/*
> - * Non-machine dependent bootinfo structure. Basic idea
> - * borrowed from the m68k.
> - *
> - * Copyright (C) 1999 Cort Dougan <cort@ppc.kernel.org>
> - */
> -
> -#ifdef __KERNEL__
> -#ifndef _PPC_BOOTINFO_H
> -#define _PPC_BOOTINFO_H
> -
> -#include <linux/config.h>
> -#include <asm/page.h>
> -
> -#if defined(CONFIG_APUS) && !defined(__BOOTER__)
> -#include <asm-m68k/bootinfo.h>
> -#else
> -
> -struct bi_record {
> - unsigned long tag; /* tag ID */
> - unsigned long size; /* size of record (in bytes) */
> - unsigned long data[0]; /* data */
> -};
> -
> -#define BI_FIRST 0x1010 /* first record - marker */
> -#define BI_LAST 0x1011 /* last record - marker */
> -#define BI_CMD_LINE 0x1012
> -#define BI_BOOTLOADER_ID 0x1013
> -#define BI_INITRD 0x1014
> -#define BI_SYSMAP 0x1015
> -#define BI_MACHTYPE 0x1016
> -#define BI_MEMSIZE 0x1017
> -#define BI_BOARD_INFO 0x1018
> -
> -extern struct bi_record *find_bootinfo(void);
> -extern void bootinfo_init(struct bi_record *rec);
> -extern void bootinfo_append(unsigned long tag, unsigned long size,
> void * data);
> -extern void parse_bootinfo(struct bi_record *rec);
> -extern unsigned long boot_mem_size;
> -
> -static inline struct bi_record *
> -bootinfo_addr(unsigned long offset)
> -{
> -
> - return (struct bi_record *)_ALIGN((offset) + (1 << 20) - 1,
> - (1 << 20));
> -}
> -#endif /* CONFIG_APUS */
> -
> -
> -#endif /* _PPC_BOOTINFO_H */
> -#endif /* __KERNEL__ */
> --
> 1.2.4
>
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-dev
^ permalink raw reply
* Re: Dynamically linking to pthread library
From: Dustin Lang @ 2006-04-05 13:20 UTC (permalink / raw)
To: Usha Rani Konudula; +Cc: linuxppc-dev
In-Reply-To: <C9CDA704CB0EEA4DBE2EFC05AE11851C1C6A8A@SGSGS-EXCH01.apac.borl.net>
Hi,
> Do you need to explicitly specify -pthread option to g++ to make the
> target library link with pthread dynamically. Otherwise does it
> statically link to pthread library on ppc64 power5.
You can use "ldd" to tell you which libraries are dynamically linked to an
executable. Read "man ldd" for more details. You can add the "-v"
(verbose) flag to your g++ link command, which will tell you the full
details of what it's linking in.
My guess is that you need to specify "-pthread" explicitly. What happens
if you create a program that calls a pthread function and you don't
specify "-pthread". Does it link? If it does, then the compiler is
getting that pthread definition from _somewhere_. What does "g++ -v" tell
you? What does "ldd" tell you?
By the way, a better way to ask questions on a mailing list is to explain
what you're trying to do, what you've tried to do to achieve it, and why
it didn't work. It usually helps to be explicit about each step. Show
that you've tried to figure it out for yourself.
Cheers,
dstn.
^ permalink raw reply
* MPC5200 + LocalPlus Bus + memcpy
From: Sascha Hauer @ 2006-04-05 11:38 UTC (permalink / raw)
To: Linuxppc-embedded
Hi all,
I try to use jffs2 on a flash device connected to the mpc5200
LocalPlus Bus. This bus does not allow misaligned accesses.
The jffs2 code uses memcpy to copy from a word aligned address to an
odd address. The ppc memcpy implementation first copies three bytes to get
the target address word aligned, but then the source address is on an
odd address. The following word accesses on this unaligned address fail
badly.
I have fixed my problem by modifying the physmap mtd driver, but some
day someone wants to connect SRAM to the LocalPlus Bus and I guess he
will expect memcpy to work.
(BTW the arm implementation of memcpy seems to work around this problem)
Sascha
^ permalink raw reply
* Re: [RFC/PATCH] powerpc: Use rtas query-cpu-stopped-state in smp spinup
From: Michael Ellerman @ 2006-04-05 11:23 UTC (permalink / raw)
To: Nathan Lynch; +Cc: linuxppc-dev, Paul Mackerras, Arnd Bergmann
In-Reply-To: <20060404172550.GE25663@localdomain>
[-- Attachment #1: Type: text/plain, Size: 1859 bytes --]
On Tue, 2006-04-04 at 12:25 -0500, Nathan Lynch wrote:
> Michael Ellerman wrote:
> > Currently we use a cpumask called of_spin_map to keep track of which threads
> > have been spun up. We basically guess that OF has spun up all even numbered
> > threads, and so all the odd numbered threads need to be brought up.
> >
> > That's a bit of a dicey assumption at best, and is totally incorrect for
> > kexec.
> >
> > Luckily we have an rtas call which can tell us whether a cpu is up
> > or not, so let's use it?
>
> 1. query-cpu-stopped-state isn't available on all RTAS systems (I
> believe it's required only on systems that support cpu offline).
That should be ok, I'm pretty sure the way I've written it if
query-cpu-stopped-state isn't there we try and start it the old way
anyway.
> 2. I've tried it before. Hope I'm remembering this correctly, but I
> think my experience was that query-cpu-stopped-state reported
> nonsense for cpus that were started by OF. This was on Power5,
> btw.
That's not what I see, perhaps I have newer firmware?
> 3. This isn't how query-cpu-stopped-state was intended to be used.
> It's meant to be used by the OS to determine when a thread has
> stopped itself using the stop-self method. Which might partially
> explain (2).
Perhaps, PAPR says: "The query-cpu-stopped-state primitive is used to
query a different processor thread to determine its status with respect
to the RTAS stopped state". I guess I assumed that a thread that's not
started would be in the "RTAS stopped state", which seems logical if not
correct.
cheers
--
Michael Ellerman
IBM OzLabs
wwweb: http://michael.ellerman.id.au
phone: +61 2 6212 1183 (tie line 70 21183)
We do not inherit the earth from our ancestors,
we borrow it from our children. - S.M.A.R.T Person
[-- Attachment #2: This is a digitally signed message part --]
[-- Type: application/pgp-signature, Size: 191 bytes --]
^ permalink raw reply
* SBC 8245 problem with linux kernel PCI bus configuration
From: kevin morizur @ 2006-04-05 10:49 UTC (permalink / raw)
To: linuxppc-embedded
Hi.
I'am using a SBC8245 board,ELDK 4.0 and Linux 2.6.11.
I make a linux kernel for MPC8245 with ELDK version 4.0 and i meet few
problems :
1) I make my kernel configuration and when i activate the PCI bus support i
have errors in compilation: PIRQA,PIRQB,PIRQC,PIRQD,
PCI_INT_MASK_REG,PCI_INT_STAT_REG,PCI_INT_TO_SIU are not defined. When i
compile without PCI bus support, there is no problem. So i don't have PCI
bus activate !
2) When i start the kernel on my target the console displays : Detected
PPCBOOT header
Verifying image CRC...ok
Uncompressing Kernel Image...ok
Starting Linux Kernel.
and it stops. My console is connected via the serial port which is connected
to the MPC8245 via PCI bus. So maybe the linux kernel starts correctly but i
can't see anything ?
So if you could help me to make PCI bus working correctly !
Regards,
Kevin
_________________________________________________________________
Tout savoir sur la sécurité de votre PC !
http://go.msn.fr/10-channel/80-security/spam/default.asp
^ permalink raw reply
* Re: xorg-7.0 freezes on gentoo ppc64 linux with 9800 card
From: Yang Dehua @ 2006-04-05 10:51 UTC (permalink / raw)
To: Brian D. Carlstrom; +Cc: linuxppc-dev
In-Reply-To: <17459.11188.362959.630416@zot.electricrain.com>
RGVhciBCcmlhbiwNClRoYW5rIHlvdS4NCkkganVzdCBmZXRjaGVkIHRoZSBjdnMgb2YgeGY4Ni12
aWRlby1hdGkgZHJpdmVyIGZyb20gZnJlZWRlc2t0b3Aub3JnLCBhbmQgaXQgd29ya2VkIG9uIG15
IDk4MDB4dCBjYXJkLg0KDQpSZWdhcmRzLA0KRGVodWENCg0KLS0tLS0gT3JpZ2luYWwgTWVzc2Fn
ZSAtLS0tLSANCkZyb206ICJCcmlhbiBELiBDYXJsc3Ryb20iIDxiZGNAY2FybHN0cm9tLmNvbT4N
ClRvOiAiWWFuZyBEZWh1YSIgPHlhbmdkaEBjYWJsZXBsdXMuY29tLmNuPg0KQ2M6IDxsaW51eHBw
Yy1kZXZAb3psYWJzLm9yZz4NClNlbnQ6IFdlZG5lc2RheSwgQXByaWwgMDUsIDIwMDYgMTA6MzAg
QU0NClN1YmplY3Q6IHhvcmctNy4wIGZyZWV6ZXMgb24gZ2VudG9vIHBwYzY0IGxpbnV4IHdpdGgg
OTgwMCBjYXJkDQoNCg0KPiBZYW5nIERlaHVhIHdyaXRlczoNCj4gID4gSSBqdXN0IGJvdWdodCBh
IG1hYyA5ODAweHQgY2FyZCB0byByZXBsYWNlIG15IDk2MDBwcm8gb24gbXkgRzUNCj4gID4gcnVu
bmluZyBnZW50b28gcHBjNjQgbGludXgoMjAwNi4wLCA2NC1iaXQgdXNlcmxhbmQpLiBUaGUgc3lz
dGVtDQo+ICA+IHdvcmtlZCBmaW5lIHVudGlsIEkgc3RhcnRlZCB4b3JnLTcuMDogdGhlIHNjcmVl
biBibGFja2VkIGFuZCB0aGUNCj4gID4ga2V5Ym9hcmQgYW5kIG1vdXNlIHdlcmUgbm90IHJlc3Bv
bmRpbmcgYW55IG1vcmUsIHNvIEkgaGFkIHRvIHNodXRkb3duDQo+ICA+IHRoZSBtYWNoaW5lLiBU
aGUgc2FtZSBYIGNvbmZpZyB3b3JrZWQgd2VsbCB3aXRoIDk2MDBwcm8gY2FyZCg2NE0pLg0KPiAN
Cj4gSSByYW4gaW50byB0aGlzIGFuZCBwb3N0ZWQgYSB3b3JrYXJvdW5kIGFib3V0IGl0IGhlcmUg
Zm9yIGZlZG9yYToNCj4gICAgIGh0dHA6Ly9saXN0cy5pbmZyYWRlYWQub3JnL3BpcGVybWFpbC9m
ZWRvcmEtcHBjLzIwMDYtTWFyY2gvMDAwODE2Lmh0bWwNCj4gDQo+IEkgYmFzZWQgdGhpcyB3b3Jr
YXJvdW5kIGJhc2VkIG9uIHRoZSBVYnVudHUgZGlzY3Vzc2lvbiBoZXJlOg0KPiAgICAgaHR0cHM6
Ly9sYXVuY2hwYWQubmV0L2Rpc3Ryb3MvdWJ1bnR1Lytzb3VyY2UveHNlcnZlci14b3JnLWRyaXZl
ci1hdGkvK2J1Zy8zMDQyNg0KPiANCj4gQmFzaWNhbGx5LCBCZW5qYW1pbiBIZXJyZW5zY2htaWR0
IHJlY29tbWVuZHMgImJ1aWxkaW5nIHRoZSBhdGkgZHJpdmVyDQo+IGZyb20gWC5vcmcgYXRpLTEt
MC1icmFuY2ggQ1ZTIGJyYW5jaCIuIFdpdGggdGhhdCwgSSdtIHdvcmtpbmcgaW4gWA0KPiBoYXBw
aWx5LiBJJ2xsIG5vdGUgdGhhdCBhbiBhbHRlcm5hdGl2ZSBiZWZvcmUgdGhhdCB3YXMgdG8gdXNl
IHRoZQ0KPiAiZmJkZXYiIGRyaXZlciBpbnN0ZWFkIG9mIHRoZSAicmFkZW9uIi4NCj4gDQo+IC1i
cmkNCj4gDQo+IA0K
^ permalink raw reply
* Dynamically linking to pthread library
From: Usha Rani Konudula @ 2006-04-05 10:02 UTC (permalink / raw)
To: linuxppc-dev
Do you need to explicitly specify -pthread option to g++ to make the
target library link with pthread dynamically. Otherwise does it
statically link to pthread library on ppc64 power5.
Kindly let me know.
Thanks
Usha.
^ permalink raw reply
* [PATCH 15/15] powerpc: remove include hack
From: sfr @ 2006-04-05 5:10 UTC (permalink / raw)
To: paulus; +Cc: linuxppc-dev, Stephen Rothwell
In-Reply-To: <11442138494042-git-send-email-sfr@canb.auug.org.au>
From: Stephen Rothwell <sfr@canb.auug.org.au>
This patch removes the Makefile hack that allows including files from
include/asm-ppc when doing a 32bit ARCH=powerpc build. Build tested
for all three 32bit defconfigs and pseries_defconfig.
Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
---
arch/powerpc/Makefile | 21 +++------------------
1 files changed, 3 insertions(+), 18 deletions(-)
50d33a5568cebd00d7148e90a6b5b6865f029602
diff --git a/arch/powerpc/Makefile b/arch/powerpc/Makefile
index 6ec84d3..f757532 100644
--- a/arch/powerpc/Makefile
+++ b/arch/powerpc/Makefile
@@ -36,7 +36,7 @@ export CROSS32CC CROSS32AS CROSS32LD CRO
KBUILD_DEFCONFIG := $(shell uname -m)_defconfig
ifeq ($(CONFIG_PPC64),y)
-OLDARCH := ppc64
+UTS_MACHINE := ppc64
SZ := 64
new_nm := $(shell if $(NM) --help 2>&1 | grep -- '--synthetic' > /dev/null; then echo y; else echo n; fi)
@@ -46,12 +46,10 @@ NM := $(NM) --synthetic
endif
else
-OLDARCH := ppc
+UTS_MACHINE := ppc
SZ := 32
endif
-UTS_MACHINE := $(OLDARCH)
-
ifeq ($(HAS_BIARCH),y)
override AS += -a$(SZ)
override LD += -m elf$(SZ)ppc
@@ -60,8 +58,7 @@ endif
LDFLAGS_vmlinux := -Bstatic
-# The -Iarch/$(ARCH)/include is temporary while we are merging
-CPPFLAGS-$(CONFIG_PPC32) := -Iarch/$(ARCH) -Iarch/$(ARCH)/include
+CPPFLAGS-$(CONFIG_PPC32) := -Iarch/$(ARCH)
AFLAGS-$(CONFIG_PPC32) := -Iarch/$(ARCH)
CFLAGS-$(CONFIG_PPC64) := -mminimal-toc -mtraceback=none -mcall-aixdesc
CFLAGS-$(CONFIG_PPC32) := -Iarch/$(ARCH) -ffixed-r2 -mmultiple
@@ -69,9 +66,6 @@ CPPFLAGS += $(CPPFLAGS-y)
AFLAGS += $(AFLAGS-y)
CFLAGS += -msoft-float -pipe $(CFLAGS-y)
CPP = $(CC) -E $(CFLAGS)
-# Temporary hack until we have migrated to asm-powerpc
-LINUXINCLUDE-$(CONFIG_PPC32) := -Iarch/$(ARCH)/include
-LINUXINCLUDE += $(LINUXINCLUDE-y)
CHECKFLAGS += -m$(SZ) -D__powerpc__ -D__powerpc$(SZ)__
@@ -165,18 +159,9 @@ archclean:
$(Q)$(MAKE) $(clean)=$(boot)
archmrproper:
- $(Q)rm -rf arch/$(ARCH)/include
archprepare: checkbin
-ifeq ($(CONFIG_PPC32),y)
-# Temporary hack until we have migrated to asm-powerpc
-include/asm: arch/$(ARCH)/include/asm
-arch/$(ARCH)/include/asm: FORCE
- $(Q)if [ ! -d arch/$(ARCH)/include ]; then mkdir -p arch/$(ARCH)/include; fi
- $(Q)ln -fsn $(srctree)/include/asm-$(OLDARCH) arch/$(ARCH)/include/asm
-endif
-
# Use the file '.tmp_gas_check' for binutils tests, as gas won't output
# to stdout and these checks are run even on install targets.
TOUT := .tmp_gas_check
--
1.2.4
^ permalink raw reply related
* [PATCH 14/15] powerpc: move asm/mpc85xx.h
From: sfr @ 2006-04-05 5:10 UTC (permalink / raw)
To: paulus; +Cc: linuxppc-dev, Stephen Rothwell
In-Reply-To: <11442138494042-git-send-email-sfr@canb.auug.org.au>
From: Stephen Rothwell <sfr@canb.auug.org.au>
Since the ARCH=powerpc build depends on this file, move it to
include/asm-powerpc.
Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
---
include/asm-powerpc/mpc85xx.h | 195 ++++++++++++++++++++++++++++++++++++++++
include/asm-ppc/mpc85xx.h | 198 -----------------------------------------
2 files changed, 195 insertions(+), 198 deletions(-)
create mode 100644 include/asm-powerpc/mpc85xx.h
delete mode 100644 include/asm-ppc/mpc85xx.h
4fc7b6e78d24e11e704ef7b5a1ceb659d3a03cc2
diff --git a/include/asm-powerpc/mpc85xx.h b/include/asm-powerpc/mpc85xx.h
new file mode 100644
index 0000000..4113165
--- /dev/null
+++ b/include/asm-powerpc/mpc85xx.h
@@ -0,0 +1,195 @@
+#ifndef _ASM_POWERPC_MPC85XX_H
+#define _ASM_POWERPC_MPC85XX_H
+/*
+ * MPC85xx definitions
+ *
+ * Maintainer: Kumar Gala <galak@kernel.crashing.org>
+ *
+ * Copyright 2004 Freescale Semiconductor, Inc
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#ifdef __KERNEL__
+
+#include <asm/mmu.h>
+
+#ifdef CONFIG_85xx
+
+#ifdef CONFIG_MPC8540_ADS
+#include <platforms/85xx/mpc8540_ads.h>
+#endif
+#if defined(CONFIG_MPC8555_CDS) || defined(CONFIG_MPC8548_CDS)
+#include <platforms/85xx/mpc8555_cds.h>
+#endif
+#ifdef CONFIG_MPC8560_ADS
+#include <platforms/85xx/mpc8560_ads.h>
+#endif
+#ifdef CONFIG_SBC8560
+#include <platforms/85xx/sbc8560.h>
+#endif
+#ifdef CONFIG_STX_GP3
+#include <platforms/85xx/stx_gp3.h>
+#endif
+#if defined(CONFIG_TQM8540) || defined(CONFIG_TQM8541) || \
+ defined(CONFIG_TQM8555) || defined(CONFIG_TQM8560)
+#include <platforms/85xx/tqm85xx.h>
+#endif
+
+#define _IO_BASE isa_io_base
+#define _ISA_MEM_BASE isa_mem_base
+#ifdef CONFIG_PCI
+#define PCI_DRAM_OFFSET pci_dram_offset
+#else
+#define PCI_DRAM_OFFSET 0
+#endif
+
+/*
+ * The "residual" board information structure the boot loader passes
+ * into the kernel.
+ */
+extern unsigned char __res[];
+
+/* Offset from CCSRBAR */
+#define MPC85xx_CPM_OFFSET (0x80000)
+#define MPC85xx_CPM_SIZE (0x40000)
+#define MPC85xx_DMA_OFFSET (0x21000)
+#define MPC85xx_DMA_SIZE (0x01000)
+#define MPC85xx_DMA0_OFFSET (0x21100)
+#define MPC85xx_DMA0_SIZE (0x00080)
+#define MPC85xx_DMA1_OFFSET (0x21180)
+#define MPC85xx_DMA1_SIZE (0x00080)
+#define MPC85xx_DMA2_OFFSET (0x21200)
+#define MPC85xx_DMA2_SIZE (0x00080)
+#define MPC85xx_DMA3_OFFSET (0x21280)
+#define MPC85xx_DMA3_SIZE (0x00080)
+#define MPC85xx_ENET1_OFFSET (0x24000)
+#define MPC85xx_ENET1_SIZE (0x01000)
+#define MPC85xx_MIIM_OFFSET (0x24520)
+#define MPC85xx_MIIM_SIZE (0x00018)
+#define MPC85xx_ENET2_OFFSET (0x25000)
+#define MPC85xx_ENET2_SIZE (0x01000)
+#define MPC85xx_ENET3_OFFSET (0x26000)
+#define MPC85xx_ENET3_SIZE (0x01000)
+#define MPC85xx_GUTS_OFFSET (0xe0000)
+#define MPC85xx_GUTS_SIZE (0x01000)
+#define MPC85xx_IIC1_OFFSET (0x03000)
+#define MPC85xx_IIC1_SIZE (0x00100)
+#define MPC85xx_OPENPIC_OFFSET (0x40000)
+#define MPC85xx_OPENPIC_SIZE (0x40000)
+#define MPC85xx_PCI1_OFFSET (0x08000)
+#define MPC85xx_PCI1_SIZE (0x01000)
+#define MPC85xx_PCI2_OFFSET (0x09000)
+#define MPC85xx_PCI2_SIZE (0x01000)
+#define MPC85xx_PERFMON_OFFSET (0xe1000)
+#define MPC85xx_PERFMON_SIZE (0x01000)
+#define MPC85xx_SEC2_OFFSET (0x30000)
+#define MPC85xx_SEC2_SIZE (0x10000)
+#define MPC85xx_UART0_OFFSET (0x04500)
+#define MPC85xx_UART0_SIZE (0x00100)
+#define MPC85xx_UART1_OFFSET (0x04600)
+#define MPC85xx_UART1_SIZE (0x00100)
+
+#define MPC85xx_CCSRBAR_SIZE (1024*1024)
+
+/* Let modules/drivers get at CCSRBAR */
+extern phys_addr_t get_ccsrbar(void);
+
+#ifdef MODULE
+#define CCSRBAR get_ccsrbar()
+#else
+#define CCSRBAR BOARD_CCSRBAR
+#endif
+
+enum ppc_sys_devices {
+ MPC85xx_TSEC1,
+ MPC85xx_TSEC2,
+ MPC85xx_FEC,
+ MPC85xx_IIC1,
+ MPC85xx_DMA0,
+ MPC85xx_DMA1,
+ MPC85xx_DMA2,
+ MPC85xx_DMA3,
+ MPC85xx_DUART,
+ MPC85xx_PERFMON,
+ MPC85xx_SEC2,
+ MPC85xx_CPM_SPI,
+ MPC85xx_CPM_I2C,
+ MPC85xx_CPM_USB,
+ MPC85xx_CPM_SCC1,
+ MPC85xx_CPM_SCC2,
+ MPC85xx_CPM_SCC3,
+ MPC85xx_CPM_SCC4,
+ MPC85xx_CPM_FCC1,
+ MPC85xx_CPM_FCC2,
+ MPC85xx_CPM_FCC3,
+ MPC85xx_CPM_MCC1,
+ MPC85xx_CPM_MCC2,
+ MPC85xx_CPM_SMC1,
+ MPC85xx_CPM_SMC2,
+ MPC85xx_eTSEC1,
+ MPC85xx_eTSEC2,
+ MPC85xx_eTSEC3,
+ MPC85xx_eTSEC4,
+ MPC85xx_IIC2,
+ MPC85xx_MDIO,
+ NUM_PPC_SYS_DEVS,
+};
+
+/* Internal interrupts are all Level Sensitive, and Positive Polarity */
+#define MPC85XX_INTERNAL_IRQ_SENSES \
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 0 */ \
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 1 */ \
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 2 */ \
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 3 */ \
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 4 */ \
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 5 */ \
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 6 */ \
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 7 */ \
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 8 */ \
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 9 */ \
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 10 */ \
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 11 */ \
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 12 */ \
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 13 */ \
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 14 */ \
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 15 */ \
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 16 */ \
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 17 */ \
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 18 */ \
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 19 */ \
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 20 */ \
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 21 */ \
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 22 */ \
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 23 */ \
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 24 */ \
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 25 */ \
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 26 */ \
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 27 */ \
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 28 */ \
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 29 */ \
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 30 */ \
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 31 */ \
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 32 */ \
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 33 */ \
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 34 */ \
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 35 */ \
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 36 */ \
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 37 */ \
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 38 */ \
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 39 */ \
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 40 */ \
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 41 */ \
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 42 */ \
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 43 */ \
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 44 */ \
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 45 */ \
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 46 */ \
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE) /* Internal 47 */
+
+#endif /* CONFIG_85xx */
+#endif /* __KERNEL__ */
+#endif /* _ASM_POWERPC_MPC85XX_H */
diff --git a/include/asm-ppc/mpc85xx.h b/include/asm-ppc/mpc85xx.h
deleted file mode 100644
index f47002a..0000000
--- a/include/asm-ppc/mpc85xx.h
+++ /dev/null
@@ -1,198 +0,0 @@
-/*
- * include/asm-ppc/mpc85xx.h
- *
- * MPC85xx definitions
- *
- * Maintainer: Kumar Gala <galak@kernel.crashing.org>
- *
- * Copyright 2004 Freescale Semiconductor, Inc
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- */
-
-#ifdef __KERNEL__
-#ifndef __ASM_MPC85xx_H__
-#define __ASM_MPC85xx_H__
-
-#include <linux/config.h>
-#include <asm/mmu.h>
-
-#ifdef CONFIG_85xx
-
-#ifdef CONFIG_MPC8540_ADS
-#include <platforms/85xx/mpc8540_ads.h>
-#endif
-#if defined(CONFIG_MPC8555_CDS) || defined(CONFIG_MPC8548_CDS)
-#include <platforms/85xx/mpc8555_cds.h>
-#endif
-#ifdef CONFIG_MPC8560_ADS
-#include <platforms/85xx/mpc8560_ads.h>
-#endif
-#ifdef CONFIG_SBC8560
-#include <platforms/85xx/sbc8560.h>
-#endif
-#ifdef CONFIG_STX_GP3
-#include <platforms/85xx/stx_gp3.h>
-#endif
-#if defined(CONFIG_TQM8540) || defined(CONFIG_TQM8541) || \
- defined(CONFIG_TQM8555) || defined(CONFIG_TQM8560)
-#include <platforms/85xx/tqm85xx.h>
-#endif
-
-#define _IO_BASE isa_io_base
-#define _ISA_MEM_BASE isa_mem_base
-#ifdef CONFIG_PCI
-#define PCI_DRAM_OFFSET pci_dram_offset
-#else
-#define PCI_DRAM_OFFSET 0
-#endif
-
-/*
- * The "residual" board information structure the boot loader passes
- * into the kernel.
- */
-extern unsigned char __res[];
-
-/* Offset from CCSRBAR */
-#define MPC85xx_CPM_OFFSET (0x80000)
-#define MPC85xx_CPM_SIZE (0x40000)
-#define MPC85xx_DMA_OFFSET (0x21000)
-#define MPC85xx_DMA_SIZE (0x01000)
-#define MPC85xx_DMA0_OFFSET (0x21100)
-#define MPC85xx_DMA0_SIZE (0x00080)
-#define MPC85xx_DMA1_OFFSET (0x21180)
-#define MPC85xx_DMA1_SIZE (0x00080)
-#define MPC85xx_DMA2_OFFSET (0x21200)
-#define MPC85xx_DMA2_SIZE (0x00080)
-#define MPC85xx_DMA3_OFFSET (0x21280)
-#define MPC85xx_DMA3_SIZE (0x00080)
-#define MPC85xx_ENET1_OFFSET (0x24000)
-#define MPC85xx_ENET1_SIZE (0x01000)
-#define MPC85xx_MIIM_OFFSET (0x24520)
-#define MPC85xx_MIIM_SIZE (0x00018)
-#define MPC85xx_ENET2_OFFSET (0x25000)
-#define MPC85xx_ENET2_SIZE (0x01000)
-#define MPC85xx_ENET3_OFFSET (0x26000)
-#define MPC85xx_ENET3_SIZE (0x01000)
-#define MPC85xx_GUTS_OFFSET (0xe0000)
-#define MPC85xx_GUTS_SIZE (0x01000)
-#define MPC85xx_IIC1_OFFSET (0x03000)
-#define MPC85xx_IIC1_SIZE (0x00100)
-#define MPC85xx_OPENPIC_OFFSET (0x40000)
-#define MPC85xx_OPENPIC_SIZE (0x40000)
-#define MPC85xx_PCI1_OFFSET (0x08000)
-#define MPC85xx_PCI1_SIZE (0x01000)
-#define MPC85xx_PCI2_OFFSET (0x09000)
-#define MPC85xx_PCI2_SIZE (0x01000)
-#define MPC85xx_PERFMON_OFFSET (0xe1000)
-#define MPC85xx_PERFMON_SIZE (0x01000)
-#define MPC85xx_SEC2_OFFSET (0x30000)
-#define MPC85xx_SEC2_SIZE (0x10000)
-#define MPC85xx_UART0_OFFSET (0x04500)
-#define MPC85xx_UART0_SIZE (0x00100)
-#define MPC85xx_UART1_OFFSET (0x04600)
-#define MPC85xx_UART1_SIZE (0x00100)
-
-#define MPC85xx_CCSRBAR_SIZE (1024*1024)
-
-/* Let modules/drivers get at CCSRBAR */
-extern phys_addr_t get_ccsrbar(void);
-
-#ifdef MODULE
-#define CCSRBAR get_ccsrbar()
-#else
-#define CCSRBAR BOARD_CCSRBAR
-#endif
-
-enum ppc_sys_devices {
- MPC85xx_TSEC1,
- MPC85xx_TSEC2,
- MPC85xx_FEC,
- MPC85xx_IIC1,
- MPC85xx_DMA0,
- MPC85xx_DMA1,
- MPC85xx_DMA2,
- MPC85xx_DMA3,
- MPC85xx_DUART,
- MPC85xx_PERFMON,
- MPC85xx_SEC2,
- MPC85xx_CPM_SPI,
- MPC85xx_CPM_I2C,
- MPC85xx_CPM_USB,
- MPC85xx_CPM_SCC1,
- MPC85xx_CPM_SCC2,
- MPC85xx_CPM_SCC3,
- MPC85xx_CPM_SCC4,
- MPC85xx_CPM_FCC1,
- MPC85xx_CPM_FCC2,
- MPC85xx_CPM_FCC3,
- MPC85xx_CPM_MCC1,
- MPC85xx_CPM_MCC2,
- MPC85xx_CPM_SMC1,
- MPC85xx_CPM_SMC2,
- MPC85xx_eTSEC1,
- MPC85xx_eTSEC2,
- MPC85xx_eTSEC3,
- MPC85xx_eTSEC4,
- MPC85xx_IIC2,
- MPC85xx_MDIO,
- NUM_PPC_SYS_DEVS,
-};
-
-/* Internal interrupts are all Level Sensitive, and Positive Polarity */
-#define MPC85XX_INTERNAL_IRQ_SENSES \
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 0 */ \
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 1 */ \
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 2 */ \
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 3 */ \
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 4 */ \
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 5 */ \
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 6 */ \
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 7 */ \
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 8 */ \
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 9 */ \
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 10 */ \
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 11 */ \
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 12 */ \
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 13 */ \
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 14 */ \
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 15 */ \
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 16 */ \
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 17 */ \
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 18 */ \
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 19 */ \
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 20 */ \
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 21 */ \
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 22 */ \
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 23 */ \
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 24 */ \
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 25 */ \
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 26 */ \
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 27 */ \
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 28 */ \
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 29 */ \
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 30 */ \
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 31 */ \
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 32 */ \
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 33 */ \
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 34 */ \
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 35 */ \
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 36 */ \
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 37 */ \
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 38 */ \
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 39 */ \
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 40 */ \
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 41 */ \
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 42 */ \
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 43 */ \
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 44 */ \
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 45 */ \
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 46 */ \
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE) /* Internal 47 */
-
-#endif /* CONFIG_85xx */
-#endif /* __ASM_MPC85xx_H__ */
-#endif /* __KERNEL__ */
--
1.2.4
^ permalink raw reply related
* [PATCH 13/15] powerpc: move asm/reg_booke.h
From: sfr @ 2006-04-05 5:10 UTC (permalink / raw)
To: paulus; +Cc: linuxppc-dev, Stephen Rothwell
In-Reply-To: <11442138494042-git-send-email-sfr@canb.auug.org.au>
From: Stephen Rothwell <sfr@canb.auug.org.au>
Since the ARCH=powerpc build depends on this file, move it to
include/asm-powerpc.
Some white space cleanups.
Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
---
include/asm-powerpc/reg_booke.h | 503 +++++++++++++++++++++++++++++++++++++++
include/asm-ppc/reg_booke.h | 502 ---------------------------------------
2 files changed, 503 insertions(+), 502 deletions(-)
create mode 100644 include/asm-powerpc/reg_booke.h
delete mode 100644 include/asm-ppc/reg_booke.h
c1f8fa598014ca7f56835066255273235543ea91
diff --git a/include/asm-powerpc/reg_booke.h b/include/asm-powerpc/reg_booke.h
new file mode 100644
index 0000000..59531a9
--- /dev/null
+++ b/include/asm-powerpc/reg_booke.h
@@ -0,0 +1,503 @@
+#ifndef _ASM_POWERPC_REG_BOOKE_H
+#define _ASM_POWERPC_REG_BOOKE_H
+/*
+ * Contains register definitions common to the Book E PowerPC
+ * specification. Notice that while the IBM-40x series of CPUs
+ * are not true Book E PowerPCs, they borrowed a number of features
+ * before Book E was finalized, and are included here as well. Unfortunatly,
+ * they sometimes used different locations than true Book E CPUs did.
+ */
+#ifdef __KERNEL__
+
+#ifndef __ASSEMBLY__
+/* Device Control Registers */
+void __mtdcr(int reg, unsigned int val);
+unsigned int __mfdcr(int reg);
+#define mfdcr(rn) \
+ ({unsigned int rval; \
+ if (__builtin_constant_p(rn)) \
+ asm volatile("mfdcr %0," __stringify(rn) \
+ : "=r" (rval)); \
+ else \
+ rval = __mfdcr(rn); \
+ rval;})
+
+#define mtdcr(rn, v) \
+do { \
+ if (__builtin_constant_p(rn)) \
+ asm volatile("mtdcr " __stringify(rn) ",%0" \
+ : : "r" (v)); \
+ else \
+ __mtdcr(rn, v); \
+} while (0)
+
+/* R/W of indirect DCRs make use of standard naming conventions for DCRs */
+#define mfdcri(base, reg) \
+({ \
+ mtdcr(base ## _CFGADDR, base ## _ ## reg); \
+ mfdcr(base ## _CFGDATA); \
+})
+
+#define mtdcri(base, reg, data) \
+do { \
+ mtdcr(base ## _CFGADDR, base ## _ ## reg); \
+ mtdcr(base ## _CFGDATA, data); \
+} while (0)
+
+/* Performance Monitor Registers */
+#define mfpmr(rn) ({unsigned int rval; \
+ asm volatile("mfpmr %0," __stringify(rn) \
+ : "=r" (rval)); rval;})
+#define mtpmr(rn, v) asm volatile("mtpmr " __stringify(rn) ",%0" : : "r" (v))
+#endif /* __ASSEMBLY__ */
+
+/* Freescale Book E Performance Monitor APU Registers */
+#define PMRN_PMC0 0x010 /* Performance Monitor Counter 0 */
+#define PMRN_PMC1 0x011 /* Performance Monitor Counter 1 */
+#define PMRN_PMC2 0x012 /* Performance Monitor Counter 1 */
+#define PMRN_PMC3 0x013 /* Performance Monitor Counter 1 */
+#define PMRN_PMLCA0 0x090 /* PM Local Control A0 */
+#define PMRN_PMLCA1 0x091 /* PM Local Control A1 */
+#define PMRN_PMLCA2 0x092 /* PM Local Control A2 */
+#define PMRN_PMLCA3 0x093 /* PM Local Control A3 */
+
+#define PMLCA_FC 0x80000000 /* Freeze Counter */
+#define PMLCA_FCS 0x40000000 /* Freeze in Supervisor */
+#define PMLCA_FCU 0x20000000 /* Freeze in User */
+#define PMLCA_FCM1 0x10000000 /* Freeze when PMM==1 */
+#define PMLCA_FCM0 0x08000000 /* Freeze when PMM==0 */
+#define PMLCA_CE 0x04000000 /* Condition Enable */
+
+#define PMLCA_EVENT_MASK 0x007f0000 /* Event field */
+#define PMLCA_EVENT_SHIFT 16
+
+#define PMRN_PMLCB0 0x110 /* PM Local Control B0 */
+#define PMRN_PMLCB1 0x111 /* PM Local Control B1 */
+#define PMRN_PMLCB2 0x112 /* PM Local Control B2 */
+#define PMRN_PMLCB3 0x113 /* PM Local Control B3 */
+
+#define PMLCB_THRESHMUL_MASK 0x0700 /* Threshhold Multiple Field */
+#define PMLCB_THRESHMUL_SHIFT 8
+
+#define PMLCB_THRESHOLD_MASK 0x003f /* Threshold Field */
+#define PMLCB_THRESHOLD_SHIFT 0
+
+#define PMRN_PMGC0 0x190 /* PM Global Control 0 */
+
+#define PMGC0_FAC 0x80000000 /* Freeze all Counters */
+#define PMGC0_PMIE 0x40000000 /* Interrupt Enable */
+#define PMGC0_FCECE 0x20000000 /* Freeze countes on
+ Enabled Condition or
+ Event */
+
+#define PMRN_UPMC0 0x000 /* User Performance Monitor Counter 0 */
+#define PMRN_UPMC1 0x001 /* User Performance Monitor Counter 1 */
+#define PMRN_UPMC2 0x002 /* User Performance Monitor Counter 1 */
+#define PMRN_UPMC3 0x003 /* User Performance Monitor Counter 1 */
+#define PMRN_UPMLCA0 0x080 /* User PM Local Control A0 */
+#define PMRN_UPMLCA1 0x081 /* User PM Local Control A1 */
+#define PMRN_UPMLCA2 0x082 /* User PM Local Control A2 */
+#define PMRN_UPMLCA3 0x083 /* User PM Local Control A3 */
+#define PMRN_UPMLCB0 0x100 /* User PM Local Control B0 */
+#define PMRN_UPMLCB1 0x101 /* User PM Local Control B1 */
+#define PMRN_UPMLCB2 0x102 /* User PM Local Control B2 */
+#define PMRN_UPMLCB3 0x103 /* User PM Local Control B3 */
+#define PMRN_UPMGC0 0x180 /* User PM Global Control 0 */
+
+
+/* Machine State Register (MSR) Fields */
+#define MSR_UCLE (1<<26) /* User-mode cache lock enable */
+#define MSR_SPE (1<<25) /* Enable SPE */
+#define MSR_DWE (1<<10) /* Debug Wait Enable */
+#define MSR_UBLE (1<<10) /* BTB lock enable (e500) */
+#define MSR_IS MSR_IR /* Instruction Space */
+#define MSR_DS MSR_DR /* Data Space */
+#define MSR_PMM (1<<2) /* Performance monitor mark bit */
+
+/* Default MSR for kernel mode. */
+#if defined (CONFIG_40x)
+#define MSR_KERNEL (MSR_ME|MSR_RI|MSR_IR|MSR_DR|MSR_CE)
+#elif defined(CONFIG_BOOKE)
+#define MSR_KERNEL (MSR_ME|MSR_RI|MSR_CE)
+#endif
+
+/* Special Purpose Registers (SPRNs)*/
+#define SPRN_DECAR 0x036 /* Decrementer Auto Reload Register */
+#define SPRN_IVPR 0x03F /* Interrupt Vector Prefix Register */
+#define SPRN_USPRG0 0x100 /* User Special Purpose Register General 0 */
+#define SPRN_SPRG4R 0x104 /* Special Purpose Register General 4 Read */
+#define SPRN_SPRG5R 0x105 /* Special Purpose Register General 5 Read */
+#define SPRN_SPRG6R 0x106 /* Special Purpose Register General 6 Read */
+#define SPRN_SPRG7R 0x107 /* Special Purpose Register General 7 Read */
+#define SPRN_SPRG4W 0x114 /* Special Purpose Register General 4 Write */
+#define SPRN_SPRG5W 0x115 /* Special Purpose Register General 5 Write */
+#define SPRN_SPRG6W 0x116 /* Special Purpose Register General 6 Write */
+#define SPRN_SPRG7W 0x117 /* Special Purpose Register General 7 Write */
+#define SPRN_DBCR2 0x136 /* Debug Control Register 2 */
+#define SPRN_IAC3 0x13A /* Instruction Address Compare 3 */
+#define SPRN_IAC4 0x13B /* Instruction Address Compare 4 */
+#define SPRN_DVC1 0x13E /* Data Value Compare Register 1 */
+#define SPRN_DVC2 0x13F /* Data Value Compare Register 2 */
+#define SPRN_IVOR0 0x190 /* Interrupt Vector Offset Register 0 */
+#define SPRN_IVOR1 0x191 /* Interrupt Vector Offset Register 1 */
+#define SPRN_IVOR2 0x192 /* Interrupt Vector Offset Register 2 */
+#define SPRN_IVOR3 0x193 /* Interrupt Vector Offset Register 3 */
+#define SPRN_IVOR4 0x194 /* Interrupt Vector Offset Register 4 */
+#define SPRN_IVOR5 0x195 /* Interrupt Vector Offset Register 5 */
+#define SPRN_IVOR6 0x196 /* Interrupt Vector Offset Register 6 */
+#define SPRN_IVOR7 0x197 /* Interrupt Vector Offset Register 7 */
+#define SPRN_IVOR8 0x198 /* Interrupt Vector Offset Register 8 */
+#define SPRN_IVOR9 0x199 /* Interrupt Vector Offset Register 9 */
+#define SPRN_IVOR10 0x19A /* Interrupt Vector Offset Register 10 */
+#define SPRN_IVOR11 0x19B /* Interrupt Vector Offset Register 11 */
+#define SPRN_IVOR12 0x19C /* Interrupt Vector Offset Register 12 */
+#define SPRN_IVOR13 0x19D /* Interrupt Vector Offset Register 13 */
+#define SPRN_IVOR14 0x19E /* Interrupt Vector Offset Register 14 */
+#define SPRN_IVOR15 0x19F /* Interrupt Vector Offset Register 15 */
+#define SPRN_SPEFSCR 0x200 /* SPE & Embedded FP Status & Control */
+#define SPRN_BBEAR 0x201 /* Branch Buffer Entry Address Register */
+#define SPRN_BBTAR 0x202 /* Branch Buffer Target Address Register */
+#define SPRN_IVOR32 0x210 /* Interrupt Vector Offset Register 32 */
+#define SPRN_IVOR33 0x211 /* Interrupt Vector Offset Register 33 */
+#define SPRN_IVOR34 0x212 /* Interrupt Vector Offset Register 34 */
+#define SPRN_IVOR35 0x213 /* Interrupt Vector Offset Register 35 */
+#define SPRN_MCSRR0 0x23A /* Machine Check Save and Restore Register 0 */
+#define SPRN_MCSRR1 0x23B /* Machine Check Save and Restore Register 1 */
+#define SPRN_MCSR 0x23C /* Machine Check Status Register */
+#define SPRN_MCAR 0x23D /* Machine Check Address Register */
+#define SPRN_DSRR0 0x23E /* Debug Save and Restore Register 0 */
+#define SPRN_DSRR1 0x23F /* Debug Save and Restore Register 1 */
+#define SPRN_MAS0 0x270 /* MMU Assist Register 0 */
+#define SPRN_MAS1 0x271 /* MMU Assist Register 1 */
+#define SPRN_MAS2 0x272 /* MMU Assist Register 2 */
+#define SPRN_MAS3 0x273 /* MMU Assist Register 3 */
+#define SPRN_MAS4 0x274 /* MMU Assist Register 4 */
+#define SPRN_MAS5 0x275 /* MMU Assist Register 5 */
+#define SPRN_MAS6 0x276 /* MMU Assist Register 6 */
+#define SPRN_MAS7 0x3b0 /* MMU Assist Register 7 */
+#define SPRN_PID1 0x279 /* Process ID Register 1 */
+#define SPRN_PID2 0x27A /* Process ID Register 2 */
+#define SPRN_TLB0CFG 0x2B0 /* TLB 0 Config Register */
+#define SPRN_TLB1CFG 0x2B1 /* TLB 1 Config Register */
+#define SPRN_CCR1 0x378 /* Core Configuration Register 1 */
+#define SPRN_ZPR 0x3B0 /* Zone Protection Register (40x) */
+#define SPRN_MMUCR 0x3B2 /* MMU Control Register */
+#define SPRN_CCR0 0x3B3 /* Core Configuration Register 0 */
+#define SPRN_SGR 0x3B9 /* Storage Guarded Register */
+#define SPRN_DCWR 0x3BA /* Data Cache Write-thru Register */
+#define SPRN_SLER 0x3BB /* Little-endian real mode */
+#define SPRN_SU0R 0x3BC /* "User 0" real mode (40x) */
+#define SPRN_DCMP 0x3D1 /* Data TLB Compare Register */
+#define SPRN_ICDBDR 0x3D3 /* Instruction Cache Debug Data Register */
+#define SPRN_EVPR 0x3D6 /* Exception Vector Prefix Register */
+#define SPRN_L1CSR0 0x3F2 /* L1 Cache Control and Status Register 0 */
+#define SPRN_L1CSR1 0x3F3 /* L1 Cache Control and Status Register 1 */
+#define SPRN_PIT 0x3DB /* Programmable Interval Timer */
+#define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */
+#define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */
+#define SPRN_SVR 0x3FF /* System Version Register */
+
+/*
+ * SPRs which have conflicting definitions on true Book E versus classic,
+ * or IBM 40x.
+ */
+#ifdef CONFIG_BOOKE
+#define SPRN_PID 0x030 /* Process ID */
+#define SPRN_PID0 SPRN_PID/* Process ID Register 0 */
+#define SPRN_CSRR0 0x03A /* Critical Save and Restore Register 0 */
+#define SPRN_CSRR1 0x03B /* Critical Save and Restore Register 1 */
+#define SPRN_DEAR 0x03D /* Data Error Address Register */
+#define SPRN_ESR 0x03E /* Exception Syndrome Register */
+#define SPRN_PIR 0x11E /* Processor Identification Register */
+#define SPRN_DBSR 0x130 /* Debug Status Register */
+#define SPRN_DBCR0 0x134 /* Debug Control Register 0 */
+#define SPRN_DBCR1 0x135 /* Debug Control Register 1 */
+#define SPRN_IAC1 0x138 /* Instruction Address Compare 1 */
+#define SPRN_IAC2 0x139 /* Instruction Address Compare 2 */
+#define SPRN_DAC1 0x13C /* Data Address Compare 1 */
+#define SPRN_DAC2 0x13D /* Data Address Compare 2 */
+#define SPRN_TSR 0x150 /* Timer Status Register */
+#define SPRN_TCR 0x154 /* Timer Control Register */
+#endif /* Book E */
+#ifdef CONFIG_40x
+#define SPRN_PID 0x3B1 /* Process ID */
+#define SPRN_DBCR1 0x3BD /* Debug Control Register 1 */
+#define SPRN_ESR 0x3D4 /* Exception Syndrome Register */
+#define SPRN_DEAR 0x3D5 /* Data Error Address Register */
+#define SPRN_TSR 0x3D8 /* Timer Status Register */
+#define SPRN_TCR 0x3DA /* Timer Control Register */
+#define SPRN_SRR2 0x3DE /* Save/Restore Register 2 */
+#define SPRN_SRR3 0x3DF /* Save/Restore Register 3 */
+#define SPRN_DBSR 0x3F0 /* Debug Status Register */
+#define SPRN_DBCR0 0x3F2 /* Debug Control Register 0 */
+#define SPRN_DAC1 0x3F6 /* Data Address Compare 1 */
+#define SPRN_DAC2 0x3F7 /* Data Address Compare 2 */
+#define SPRN_CSRR0 SPRN_SRR2 /* Critical Save and Restore Register 0 */
+#define SPRN_CSRR1 SPRN_SRR3 /* Critical Save and Restore Register 1 */
+#endif
+
+/* Bit definitions for CCR1. */
+#define CCR1_TCS 0x00000080 /* Timer Clock Select */
+
+/* Bit definitions for the MCSR. */
+#ifdef CONFIG_440A
+#define MCSR_MCS 0x80000000 /* Machine Check Summary */
+#define MCSR_IB 0x40000000 /* Instruction PLB Error */
+#define MCSR_DRB 0x20000000 /* Data Read PLB Error */
+#define MCSR_DWB 0x10000000 /* Data Write PLB Error */
+#define MCSR_TLBP 0x08000000 /* TLB Parity Error */
+#define MCSR_ICP 0x04000000 /* I-Cache Parity Error */
+#define MCSR_DCSP 0x02000000 /* D-Cache Search Parity Error */
+#define MCSR_DCFP 0x01000000 /* D-Cache Flush Parity Error */
+#define MCSR_IMPE 0x00800000 /* Imprecise Machine Check Exception */
+#endif
+#ifdef CONFIG_E500
+#define MCSR_MCP 0x80000000UL /* Machine Check Input Pin */
+#define MCSR_ICPERR 0x40000000UL /* I-Cache Parity Error */
+#define MCSR_DCP_PERR 0x20000000UL /* D-Cache Push Parity Error */
+#define MCSR_DCPERR 0x10000000UL /* D-Cache Parity Error */
+#define MCSR_GL_CI 0x00010000UL /* Guarded Load or Cache-Inhibited stwcx. */
+#define MCSR_BUS_IAERR 0x00000080UL /* Instruction Address Error */
+#define MCSR_BUS_RAERR 0x00000040UL /* Read Address Error */
+#define MCSR_BUS_WAERR 0x00000020UL /* Write Address Error */
+#define MCSR_BUS_IBERR 0x00000010UL /* Instruction Data Error */
+#define MCSR_BUS_RBERR 0x00000008UL /* Read Data Bus Error */
+#define MCSR_BUS_WBERR 0x00000004UL /* Write Data Bus Error */
+#define MCSR_BUS_IPERR 0x00000002UL /* Instruction parity Error */
+#define MCSR_BUS_RPERR 0x00000001UL /* Read parity Error */
+#endif
+#ifdef CONFIG_E200
+#define MCSR_MCP 0x80000000UL /* Machine Check Input Pin */
+#define MCSR_CP_PERR 0x20000000UL /* Cache Push Parity Error */
+#define MCSR_CPERR 0x10000000UL /* Cache Parity Error */
+#define MCSR_EXCP_ERR 0x08000000UL /* ISI, ITLB, or Bus Error on 1st insn
+ fetch for an exception handler */
+#define MCSR_BUS_IRERR 0x00000010UL /* Read Bus Error on instruction fetch*/
+#define MCSR_BUS_DRERR 0x00000008UL /* Read Bus Error on data load */
+#define MCSR_BUS_WRERR 0x00000004UL /* Write Bus Error on buffered
+ store or cache line push */
+#endif
+
+/* Bit definitions for the DBSR. */
+/*
+ * DBSR bits which have conflicting definitions on true Book E versus IBM 40x.
+ */
+#ifdef CONFIG_BOOKE
+#define DBSR_IC 0x08000000 /* Instruction Completion */
+#define DBSR_BT 0x04000000 /* Branch Taken */
+#define DBSR_TIE 0x01000000 /* Trap Instruction Event */
+#define DBSR_IAC1 0x00800000 /* Instr Address Compare 1 Event */
+#define DBSR_IAC2 0x00400000 /* Instr Address Compare 2 Event */
+#define DBSR_IAC3 0x00200000 /* Instr Address Compare 3 Event */
+#define DBSR_IAC4 0x00100000 /* Instr Address Compare 4 Event */
+#define DBSR_DAC1R 0x00080000 /* Data Addr Compare 1 Read Event */
+#define DBSR_DAC1W 0x00040000 /* Data Addr Compare 1 Write Event */
+#define DBSR_DAC2R 0x00020000 /* Data Addr Compare 2 Read Event */
+#define DBSR_DAC2W 0x00010000 /* Data Addr Compare 2 Write Event */
+#endif
+#ifdef CONFIG_40x
+#define DBSR_IC 0x80000000 /* Instruction Completion */
+#define DBSR_BT 0x40000000 /* Branch taken */
+#define DBSR_TIE 0x10000000 /* Trap Instruction debug Event */
+#define DBSR_IAC1 0x00800000 /* Instruction Address Compare 1 Event */
+#define DBSR_IAC2 0x00400000 /* Instruction Address Compare 2 Event */
+#define DBSR_IAC3 0x00200000 /* Instruction Address Compare 3 Event */
+#define DBSR_IAC4 0x00100000 /* Instruction Address Compare 4 Event */
+#define DBSR_DAC1R 0x00080000 /* Data Address Compare 1 Read Event */
+#define DBSR_DAC1W 0x00040000 /* Data Address Compare 1 Write Event */
+#define DBSR_DAC2R 0x00020000 /* Data Address Compare 2 Read Event */
+#define DBSR_DAC2W 0x00010000 /* Data Address Compare 2 Write Event */
+#endif
+
+/* Bit definitions related to the ESR. */
+#define ESR_MCI 0x80000000 /* Machine Check - Instruction */
+#define ESR_IMCP 0x80000000 /* Instr. Machine Check - Protection */
+#define ESR_IMCN 0x40000000 /* Instr. Machine Check - Non-config */
+#define ESR_IMCB 0x20000000 /* Instr. Machine Check - Bus error */
+#define ESR_IMCT 0x10000000 /* Instr. Machine Check - Timeout */
+#define ESR_PIL 0x08000000 /* Program Exception - Illegal */
+#define ESR_PPR 0x04000000 /* Program Exception - Priveleged */
+#define ESR_PTR 0x02000000 /* Program Exception - Trap */
+#define ESR_FP 0x01000000 /* Floating Point Operation */
+#define ESR_DST 0x00800000 /* Storage Exception - Data miss */
+#define ESR_DIZ 0x00400000 /* Storage Exception - Zone fault */
+#define ESR_ST 0x00800000 /* Store Operation */
+#define ESR_DLK 0x00200000 /* Data Cache Locking */
+#define ESR_ILK 0x00100000 /* Instr. Cache Locking */
+#define ESR_PUO 0x00040000 /* Unimplemented Operation exception */
+#define ESR_BO 0x00020000 /* Byte Ordering */
+
+/* Bit definitions related to the DBCR0. */
+#define DBCR0_EDM 0x80000000 /* External Debug Mode */
+#define DBCR0_IDM 0x40000000 /* Internal Debug Mode */
+#define DBCR0_RST 0x30000000 /* all the bits in the RST field */
+#define DBCR0_RST_SYSTEM 0x30000000 /* System Reset */
+#define DBCR0_RST_CHIP 0x20000000 /* Chip Reset */
+#define DBCR0_RST_CORE 0x10000000 /* Core Reset */
+#define DBCR0_RST_NONE 0x00000000 /* No Reset */
+#define DBCR0_IC 0x08000000 /* Instruction Completion */
+#define DBCR0_BT 0x04000000 /* Branch Taken */
+#define DBCR0_EDE 0x02000000 /* Exception Debug Event */
+#define DBCR0_TDE 0x01000000 /* TRAP Debug Event */
+#define DBCR0_IA1 0x00800000 /* Instr Addr compare 1 enable */
+#define DBCR0_IA2 0x00400000 /* Instr Addr compare 2 enable */
+#define DBCR0_IA12 0x00200000 /* Instr Addr 1-2 range enable */
+#define DBCR0_IA12X 0x00100000 /* Instr Addr 1-2 range eXclusive */
+#define DBCR0_IA3 0x00080000 /* Instr Addr compare 3 enable */
+#define DBCR0_IA4 0x00040000 /* Instr Addr compare 4 enable */
+#define DBCR0_IA34 0x00020000 /* Instr Addr 3-4 range Enable */
+#define DBCR0_IA34X 0x00010000 /* Instr Addr 3-4 range eXclusive */
+#define DBCR0_IA12T 0x00008000 /* Instr Addr 1-2 range Toggle */
+#define DBCR0_IA34T 0x00004000 /* Instr Addr 3-4 range Toggle */
+#define DBCR0_FT 0x00000001 /* Freeze Timers on debug event */
+
+/* Bit definitions related to the TCR. */
+#define TCR_WP(x) (((x)&0x3)<<30) /* WDT Period */
+#define TCR_WP_MASK TCR_WP(3)
+#define WP_2_17 0 /* 2^17 clocks */
+#define WP_2_21 1 /* 2^21 clocks */
+#define WP_2_25 2 /* 2^25 clocks */
+#define WP_2_29 3 /* 2^29 clocks */
+#define TCR_WRC(x) (((x)&0x3)<<28) /* WDT Reset Control */
+#define TCR_WRC_MASK TCR_WRC(3)
+#define WRC_NONE 0 /* No reset will occur */
+#define WRC_CORE 1 /* Core reset will occur */
+#define WRC_CHIP 2 /* Chip reset will occur */
+#define WRC_SYSTEM 3 /* System reset will occur */
+#define TCR_WIE 0x08000000 /* WDT Interrupt Enable */
+#define TCR_PIE 0x04000000 /* PIT Interrupt Enable */
+#define TCR_DIE TCR_PIE /* DEC Interrupt Enable */
+#define TCR_FP(x) (((x)&0x3)<<24) /* FIT Period */
+#define TCR_FP_MASK TCR_FP(3)
+#define FP_2_9 0 /* 2^9 clocks */
+#define FP_2_13 1 /* 2^13 clocks */
+#define FP_2_17 2 /* 2^17 clocks */
+#define FP_2_21 3 /* 2^21 clocks */
+#define TCR_FIE 0x00800000 /* FIT Interrupt Enable */
+#define TCR_ARE 0x00400000 /* Auto Reload Enable */
+
+/* Bit definitions for the TSR. */
+#define TSR_ENW 0x80000000 /* Enable Next Watchdog */
+#define TSR_WIS 0x40000000 /* WDT Interrupt Status */
+#define TSR_WRS(x) (((x)&0x3)<<28) /* WDT Reset Status */
+#define WRS_NONE 0 /* No WDT reset occurred */
+#define WRS_CORE 1 /* WDT forced core reset */
+#define WRS_CHIP 2 /* WDT forced chip reset */
+#define WRS_SYSTEM 3 /* WDT forced system reset */
+#define TSR_PIS 0x08000000 /* PIT Interrupt Status */
+#define TSR_DIS TSR_PIS /* DEC Interrupt Status */
+#define TSR_FIS 0x04000000 /* FIT Interrupt Status */
+
+/* Bit definitions for the DCCR. */
+#define DCCR_NOCACHE 0 /* Noncacheable */
+#define DCCR_CACHE 1 /* Cacheable */
+
+/* Bit definitions for DCWR. */
+#define DCWR_COPY 0 /* Copy-back */
+#define DCWR_WRITE 1 /* Write-through */
+
+/* Bit definitions for ICCR. */
+#define ICCR_NOCACHE 0 /* Noncacheable */
+#define ICCR_CACHE 1 /* Cacheable */
+
+/* Bit definitions for L1CSR0. */
+#define L1CSR0_CLFC 0x00000100 /* Cache Lock Bits Flash Clear */
+#define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */
+#define L1CSR0_CFI 0x00000002 /* Cache Flash Invalidate */
+#define L1CSR0_DCE 0x00000001 /* Data Cache Enable */
+
+/* Bit definitions for L1CSR1. */
+#define L1CSR1_ICLFR 0x00000100 /* Instr Cache Lock Bits Flash Reset */
+#define L1CSR1_ICFI 0x00000002 /* Instr Cache Flash Invalidate */
+#define L1CSR1_ICE 0x00000001 /* Instr Cache Enable */
+
+/* Bit definitions for SGR. */
+#define SGR_NORMAL 0 /* Speculative fetching allowed. */
+#define SGR_GUARDED 1 /* Speculative fetching disallowed. */
+
+/* Bit definitions for SPEFSCR. */
+#define SPEFSCR_SOVH 0x80000000 /* Summary integer overflow high */
+#define SPEFSCR_OVH 0x40000000 /* Integer overflow high */
+#define SPEFSCR_FGH 0x20000000 /* Embedded FP guard bit high */
+#define SPEFSCR_FXH 0x10000000 /* Embedded FP sticky bit high */
+#define SPEFSCR_FINVH 0x08000000 /* Embedded FP invalid operation high */
+#define SPEFSCR_FDBZH 0x04000000 /* Embedded FP div by zero high */
+#define SPEFSCR_FUNFH 0x02000000 /* Embedded FP underflow high */
+#define SPEFSCR_FOVFH 0x01000000 /* Embedded FP overflow high */
+#define SPEFSCR_FINXS 0x00200000 /* Embedded FP inexact sticky */
+#define SPEFSCR_FINVS 0x00100000 /* Embedded FP invalid op. sticky */
+#define SPEFSCR_FDBZS 0x00080000 /* Embedded FP div by zero sticky */
+#define SPEFSCR_FUNFS 0x00040000 /* Embedded FP underflow sticky */
+#define SPEFSCR_FOVFS 0x00020000 /* Embedded FP overflow sticky */
+#define SPEFSCR_MODE 0x00010000 /* Embedded FP mode */
+#define SPEFSCR_SOV 0x00008000 /* Integer summary overflow */
+#define SPEFSCR_OV 0x00004000 /* Integer overflow */
+#define SPEFSCR_FG 0x00002000 /* Embedded FP guard bit */
+#define SPEFSCR_FX 0x00001000 /* Embedded FP sticky bit */
+#define SPEFSCR_FINV 0x00000800 /* Embedded FP invalid operation */
+#define SPEFSCR_FDBZ 0x00000400 /* Embedded FP div by zero */
+#define SPEFSCR_FUNF 0x00000200 /* Embedded FP underflow */
+#define SPEFSCR_FOVF 0x00000100 /* Embedded FP overflow */
+#define SPEFSCR_FINXE 0x00000040 /* Embedded FP inexact enable */
+#define SPEFSCR_FINVE 0x00000020 /* Embedded FP invalid op. enable */
+#define SPEFSCR_FDBZE 0x00000010 /* Embedded FP div by zero enable */
+#define SPEFSCR_FUNFE 0x00000008 /* Embedded FP underflow enable */
+#define SPEFSCR_FOVFE 0x00000004 /* Embedded FP overflow enable */
+#define SPEFSCR_FRMC 0x00000003 /* Embedded FP rounding mode control */
+
+/*
+ * The IBM-403 is an even more odd special case, as it is much
+ * older than the IBM-405 series. We put these down here incase someone
+ * wishes to support these machines again.
+ */
+#ifdef CONFIG_403GCX
+/* Special Purpose Registers (SPRNs)*/
+#define SPRN_TBHU 0x3CC /* Time Base High User-mode */
+#define SPRN_TBLU 0x3CD /* Time Base Low User-mode */
+#define SPRN_CDBCR 0x3D7 /* Cache Debug Control Register */
+#define SPRN_TBHI 0x3DC /* Time Base High */
+#define SPRN_TBLO 0x3DD /* Time Base Low */
+#define SPRN_DBCR 0x3F2 /* Debug Control Regsiter */
+#define SPRN_PBL1 0x3FC /* Protection Bound Lower 1 */
+#define SPRN_PBL2 0x3FE /* Protection Bound Lower 2 */
+#define SPRN_PBU1 0x3FD /* Protection Bound Upper 1 */
+#define SPRN_PBU2 0x3FF /* Protection Bound Upper 2 */
+
+
+/* Bit definitions for the DBCR. */
+#define DBCR_EDM DBCR0_EDM
+#define DBCR_IDM DBCR0_IDM
+#define DBCR_RST(x) (((x) & 0x3) << 28)
+#define DBCR_RST_NONE 0
+#define DBCR_RST_CORE 1
+#define DBCR_RST_CHIP 2
+#define DBCR_RST_SYSTEM 3
+#define DBCR_IC DBCR0_IC /* Instruction Completion Debug Evnt */
+#define DBCR_BT DBCR0_BT /* Branch Taken Debug Event */
+#define DBCR_EDE DBCR0_EDE /* Exception Debug Event */
+#define DBCR_TDE DBCR0_TDE /* TRAP Debug Event */
+#define DBCR_FER 0x00F80000 /* First Events Remaining Mask */
+#define DBCR_FT 0x00040000 /* Freeze Timers on Debug Event */
+#define DBCR_IA1 0x00020000 /* Instr. Addr. Compare 1 Enable */
+#define DBCR_IA2 0x00010000 /* Instr. Addr. Compare 2 Enable */
+#define DBCR_D1R 0x00008000 /* Data Addr. Compare 1 Read Enable */
+#define DBCR_D1W 0x00004000 /* Data Addr. Compare 1 Write Enable */
+#define DBCR_D1S(x) (((x) & 0x3) << 12) /* Data Adrr. Compare 1 Size */
+#define DAC_BYTE 0
+#define DAC_HALF 1
+#define DAC_WORD 2
+#define DAC_QUAD 3
+#define DBCR_D2R 0x00000800 /* Data Addr. Compare 2 Read Enable */
+#define DBCR_D2W 0x00000400 /* Data Addr. Compare 2 Write Enable */
+#define DBCR_D2S(x) (((x) & 0x3) << 8) /* Data Addr. Compare 2 Size */
+#define DBCR_SBT 0x00000040 /* Second Branch Taken Debug Event */
+#define DBCR_SED 0x00000020 /* Second Exception Debug Event */
+#define DBCR_STD 0x00000010 /* Second Trap Debug Event */
+#define DBCR_SIA 0x00000008 /* Second IAC Enable */
+#define DBCR_SDA 0x00000004 /* Second DAC Enable */
+#define DBCR_JOI 0x00000002 /* JTAG Serial Outbound Int. Enable */
+#define DBCR_JII 0x00000001 /* JTAG Serial Inbound Int. Enable */
+
+#endif /* 403GCX */
+#endif /* __KERNEL__ */
+#endif /* _ASM_POWERPC_REG_BOOKE_H */
diff --git a/include/asm-ppc/reg_booke.h b/include/asm-ppc/reg_booke.h
deleted file mode 100644
index 00ad9c7..0000000
--- a/include/asm-ppc/reg_booke.h
+++ /dev/null
@@ -1,502 +0,0 @@
-/*
- * Contains register definitions common to the Book E PowerPC
- * specification. Notice that while the IBM-40x series of CPUs
- * are not true Book E PowerPCs, they borrowed a number of features
- * before Book E was finalized, and are included here as well. Unfortunatly,
- * they sometimes used different locations than true Book E CPUs did.
- */
-#ifdef __KERNEL__
-#ifndef __ASM_PPC_REG_BOOKE_H__
-#define __ASM_PPC_REG_BOOKE_H__
-
-#ifndef __ASSEMBLY__
-/* Device Control Registers */
-void __mtdcr(int reg, unsigned int val);
-unsigned int __mfdcr(int reg);
-#define mfdcr(rn) \
- ({unsigned int rval; \
- if (__builtin_constant_p(rn)) \
- asm volatile("mfdcr %0," __stringify(rn) \
- : "=r" (rval)); \
- else \
- rval = __mfdcr(rn); \
- rval;})
-
-#define mtdcr(rn, v) \
-do { \
- if (__builtin_constant_p(rn)) \
- asm volatile("mtdcr " __stringify(rn) ",%0" \
- : : "r" (v)); \
- else \
- __mtdcr(rn, v); \
-} while (0)
-
-/* R/W of indirect DCRs make use of standard naming conventions for DCRs */
-#define mfdcri(base, reg) \
-({ \
- mtdcr(base ## _CFGADDR, base ## _ ## reg); \
- mfdcr(base ## _CFGDATA); \
-})
-
-#define mtdcri(base, reg, data) \
-do { \
- mtdcr(base ## _CFGADDR, base ## _ ## reg); \
- mtdcr(base ## _CFGDATA, data); \
-} while (0)
-
-/* Performance Monitor Registers */
-#define mfpmr(rn) ({unsigned int rval; \
- asm volatile("mfpmr %0," __stringify(rn) \
- : "=r" (rval)); rval;})
-#define mtpmr(rn, v) asm volatile("mtpmr " __stringify(rn) ",%0" : : "r" (v))
-#endif /* __ASSEMBLY__ */
-
-/* Freescale Book E Performance Monitor APU Registers */
-#define PMRN_PMC0 0x010 /* Performance Monitor Counter 0 */
-#define PMRN_PMC1 0x011 /* Performance Monitor Counter 1 */
-#define PMRN_PMC2 0x012 /* Performance Monitor Counter 1 */
-#define PMRN_PMC3 0x013 /* Performance Monitor Counter 1 */
-#define PMRN_PMLCA0 0x090 /* PM Local Control A0 */
-#define PMRN_PMLCA1 0x091 /* PM Local Control A1 */
-#define PMRN_PMLCA2 0x092 /* PM Local Control A2 */
-#define PMRN_PMLCA3 0x093 /* PM Local Control A3 */
-
-#define PMLCA_FC 0x80000000 /* Freeze Counter */
-#define PMLCA_FCS 0x40000000 /* Freeze in Supervisor */
-#define PMLCA_FCU 0x20000000 /* Freeze in User */
-#define PMLCA_FCM1 0x10000000 /* Freeze when PMM==1 */
-#define PMLCA_FCM0 0x08000000 /* Freeze when PMM==0 */
-#define PMLCA_CE 0x04000000 /* Condition Enable */
-
-#define PMLCA_EVENT_MASK 0x007f0000 /* Event field */
-#define PMLCA_EVENT_SHIFT 16
-
-#define PMRN_PMLCB0 0x110 /* PM Local Control B0 */
-#define PMRN_PMLCB1 0x111 /* PM Local Control B1 */
-#define PMRN_PMLCB2 0x112 /* PM Local Control B2 */
-#define PMRN_PMLCB3 0x113 /* PM Local Control B3 */
-
-#define PMLCB_THRESHMUL_MASK 0x0700 /* Threshhold Multiple Field */
-#define PMLCB_THRESHMUL_SHIFT 8
-
-#define PMLCB_THRESHOLD_MASK 0x003f /* Threshold Field */
-#define PMLCB_THRESHOLD_SHIFT 0
-
-#define PMRN_PMGC0 0x190 /* PM Global Control 0 */
-
-#define PMGC0_FAC 0x80000000 /* Freeze all Counters */
-#define PMGC0_PMIE 0x40000000 /* Interrupt Enable */
-#define PMGC0_FCECE 0x20000000 /* Freeze countes on
- Enabled Condition or
- Event */
-
-#define PMRN_UPMC0 0x000 /* User Performance Monitor Counter 0 */
-#define PMRN_UPMC1 0x001 /* User Performance Monitor Counter 1 */
-#define PMRN_UPMC2 0x002 /* User Performance Monitor Counter 1 */
-#define PMRN_UPMC3 0x003 /* User Performance Monitor Counter 1 */
-#define PMRN_UPMLCA0 0x080 /* User PM Local Control A0 */
-#define PMRN_UPMLCA1 0x081 /* User PM Local Control A1 */
-#define PMRN_UPMLCA2 0x082 /* User PM Local Control A2 */
-#define PMRN_UPMLCA3 0x083 /* User PM Local Control A3 */
-#define PMRN_UPMLCB0 0x100 /* User PM Local Control B0 */
-#define PMRN_UPMLCB1 0x101 /* User PM Local Control B1 */
-#define PMRN_UPMLCB2 0x102 /* User PM Local Control B2 */
-#define PMRN_UPMLCB3 0x103 /* User PM Local Control B3 */
-#define PMRN_UPMGC0 0x180 /* User PM Global Control 0 */
-
-
-/* Machine State Register (MSR) Fields */
-#define MSR_UCLE (1<<26) /* User-mode cache lock enable */
-#define MSR_SPE (1<<25) /* Enable SPE */
-#define MSR_DWE (1<<10) /* Debug Wait Enable */
-#define MSR_UBLE (1<<10) /* BTB lock enable (e500) */
-#define MSR_IS MSR_IR /* Instruction Space */
-#define MSR_DS MSR_DR /* Data Space */
-#define MSR_PMM (1<<2) /* Performance monitor mark bit */
-
-/* Default MSR for kernel mode. */
-#if defined (CONFIG_40x)
-#define MSR_KERNEL (MSR_ME|MSR_RI|MSR_IR|MSR_DR|MSR_CE)
-#elif defined(CONFIG_BOOKE)
-#define MSR_KERNEL (MSR_ME|MSR_RI|MSR_CE)
-#endif
-
-/* Special Purpose Registers (SPRNs)*/
-#define SPRN_DECAR 0x036 /* Decrementer Auto Reload Register */
-#define SPRN_IVPR 0x03F /* Interrupt Vector Prefix Register */
-#define SPRN_USPRG0 0x100 /* User Special Purpose Register General 0 */
-#define SPRN_SPRG4R 0x104 /* Special Purpose Register General 4 Read */
-#define SPRN_SPRG5R 0x105 /* Special Purpose Register General 5 Read */
-#define SPRN_SPRG6R 0x106 /* Special Purpose Register General 6 Read */
-#define SPRN_SPRG7R 0x107 /* Special Purpose Register General 7 Read */
-#define SPRN_SPRG4W 0x114 /* Special Purpose Register General 4 Write */
-#define SPRN_SPRG5W 0x115 /* Special Purpose Register General 5 Write */
-#define SPRN_SPRG6W 0x116 /* Special Purpose Register General 6 Write */
-#define SPRN_SPRG7W 0x117 /* Special Purpose Register General 7 Write */
-#define SPRN_DBCR2 0x136 /* Debug Control Register 2 */
-#define SPRN_IAC3 0x13A /* Instruction Address Compare 3 */
-#define SPRN_IAC4 0x13B /* Instruction Address Compare 4 */
-#define SPRN_DVC1 0x13E /* Data Value Compare Register 1 */
-#define SPRN_DVC2 0x13F /* Data Value Compare Register 2 */
-#define SPRN_IVOR0 0x190 /* Interrupt Vector Offset Register 0 */
-#define SPRN_IVOR1 0x191 /* Interrupt Vector Offset Register 1 */
-#define SPRN_IVOR2 0x192 /* Interrupt Vector Offset Register 2 */
-#define SPRN_IVOR3 0x193 /* Interrupt Vector Offset Register 3 */
-#define SPRN_IVOR4 0x194 /* Interrupt Vector Offset Register 4 */
-#define SPRN_IVOR5 0x195 /* Interrupt Vector Offset Register 5 */
-#define SPRN_IVOR6 0x196 /* Interrupt Vector Offset Register 6 */
-#define SPRN_IVOR7 0x197 /* Interrupt Vector Offset Register 7 */
-#define SPRN_IVOR8 0x198 /* Interrupt Vector Offset Register 8 */
-#define SPRN_IVOR9 0x199 /* Interrupt Vector Offset Register 9 */
-#define SPRN_IVOR10 0x19A /* Interrupt Vector Offset Register 10 */
-#define SPRN_IVOR11 0x19B /* Interrupt Vector Offset Register 11 */
-#define SPRN_IVOR12 0x19C /* Interrupt Vector Offset Register 12 */
-#define SPRN_IVOR13 0x19D /* Interrupt Vector Offset Register 13 */
-#define SPRN_IVOR14 0x19E /* Interrupt Vector Offset Register 14 */
-#define SPRN_IVOR15 0x19F /* Interrupt Vector Offset Register 15 */
-#define SPRN_SPEFSCR 0x200 /* SPE & Embedded FP Status & Control */
-#define SPRN_BBEAR 0x201 /* Branch Buffer Entry Address Register */
-#define SPRN_BBTAR 0x202 /* Branch Buffer Target Address Register */
-#define SPRN_IVOR32 0x210 /* Interrupt Vector Offset Register 32 */
-#define SPRN_IVOR33 0x211 /* Interrupt Vector Offset Register 33 */
-#define SPRN_IVOR34 0x212 /* Interrupt Vector Offset Register 34 */
-#define SPRN_IVOR35 0x213 /* Interrupt Vector Offset Register 35 */
-#define SPRN_MCSRR0 0x23A /* Machine Check Save and Restore Register 0 */
-#define SPRN_MCSRR1 0x23B /* Machine Check Save and Restore Register 1 */
-#define SPRN_MCSR 0x23C /* Machine Check Status Register */
-#define SPRN_MCAR 0x23D /* Machine Check Address Register */
-#define SPRN_DSRR0 0x23E /* Debug Save and Restore Register 0 */
-#define SPRN_DSRR1 0x23F /* Debug Save and Restore Register 1 */
-#define SPRN_MAS0 0x270 /* MMU Assist Register 0 */
-#define SPRN_MAS1 0x271 /* MMU Assist Register 1 */
-#define SPRN_MAS2 0x272 /* MMU Assist Register 2 */
-#define SPRN_MAS3 0x273 /* MMU Assist Register 3 */
-#define SPRN_MAS4 0x274 /* MMU Assist Register 4 */
-#define SPRN_MAS5 0x275 /* MMU Assist Register 5 */
-#define SPRN_MAS6 0x276 /* MMU Assist Register 6 */
-#define SPRN_MAS7 0x3b0 /* MMU Assist Register 7 */
-#define SPRN_PID1 0x279 /* Process ID Register 1 */
-#define SPRN_PID2 0x27A /* Process ID Register 2 */
-#define SPRN_TLB0CFG 0x2B0 /* TLB 0 Config Register */
-#define SPRN_TLB1CFG 0x2B1 /* TLB 1 Config Register */
-#define SPRN_CCR1 0x378 /* Core Configuration Register 1 */
-#define SPRN_ZPR 0x3B0 /* Zone Protection Register (40x) */
-#define SPRN_MMUCR 0x3B2 /* MMU Control Register */
-#define SPRN_CCR0 0x3B3 /* Core Configuration Register 0 */
-#define SPRN_SGR 0x3B9 /* Storage Guarded Register */
-#define SPRN_DCWR 0x3BA /* Data Cache Write-thru Register */
-#define SPRN_SLER 0x3BB /* Little-endian real mode */
-#define SPRN_SU0R 0x3BC /* "User 0" real mode (40x) */
-#define SPRN_DCMP 0x3D1 /* Data TLB Compare Register */
-#define SPRN_ICDBDR 0x3D3 /* Instruction Cache Debug Data Register */
-#define SPRN_EVPR 0x3D6 /* Exception Vector Prefix Register */
-#define SPRN_L1CSR0 0x3F2 /* L1 Cache Control and Status Register 0 */
-#define SPRN_L1CSR1 0x3F3 /* L1 Cache Control and Status Register 1 */
-#define SPRN_PIT 0x3DB /* Programmable Interval Timer */
-#define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */
-#define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */
-#define SPRN_SVR 0x3FF /* System Version Register */
-
-/*
- * SPRs which have conflicting definitions on true Book E versus classic,
- * or IBM 40x.
- */
-#ifdef CONFIG_BOOKE
-#define SPRN_PID 0x030 /* Process ID */
-#define SPRN_PID0 SPRN_PID/* Process ID Register 0 */
-#define SPRN_CSRR0 0x03A /* Critical Save and Restore Register 0 */
-#define SPRN_CSRR1 0x03B /* Critical Save and Restore Register 1 */
-#define SPRN_DEAR 0x03D /* Data Error Address Register */
-#define SPRN_ESR 0x03E /* Exception Syndrome Register */
-#define SPRN_PIR 0x11E /* Processor Identification Register */
-#define SPRN_DBSR 0x130 /* Debug Status Register */
-#define SPRN_DBCR0 0x134 /* Debug Control Register 0 */
-#define SPRN_DBCR1 0x135 /* Debug Control Register 1 */
-#define SPRN_IAC1 0x138 /* Instruction Address Compare 1 */
-#define SPRN_IAC2 0x139 /* Instruction Address Compare 2 */
-#define SPRN_DAC1 0x13C /* Data Address Compare 1 */
-#define SPRN_DAC2 0x13D /* Data Address Compare 2 */
-#define SPRN_TSR 0x150 /* Timer Status Register */
-#define SPRN_TCR 0x154 /* Timer Control Register */
-#endif /* Book E */
-#ifdef CONFIG_40x
-#define SPRN_PID 0x3B1 /* Process ID */
-#define SPRN_DBCR1 0x3BD /* Debug Control Register 1 */
-#define SPRN_ESR 0x3D4 /* Exception Syndrome Register */
-#define SPRN_DEAR 0x3D5 /* Data Error Address Register */
-#define SPRN_TSR 0x3D8 /* Timer Status Register */
-#define SPRN_TCR 0x3DA /* Timer Control Register */
-#define SPRN_SRR2 0x3DE /* Save/Restore Register 2 */
-#define SPRN_SRR3 0x3DF /* Save/Restore Register 3 */
-#define SPRN_DBSR 0x3F0 /* Debug Status Register */
-#define SPRN_DBCR0 0x3F2 /* Debug Control Register 0 */
-#define SPRN_DAC1 0x3F6 /* Data Address Compare 1 */
-#define SPRN_DAC2 0x3F7 /* Data Address Compare 2 */
-#define SPRN_CSRR0 SPRN_SRR2 /* Critical Save and Restore Register 0 */
-#define SPRN_CSRR1 SPRN_SRR3 /* Critical Save and Restore Register 1 */
-#endif
-
-/* Bit definitions for CCR1. */
-#define CCR1_TCS 0x00000080 /* Timer Clock Select */
-
-/* Bit definitions for the MCSR. */
-#ifdef CONFIG_440A
-#define MCSR_MCS 0x80000000 /* Machine Check Summary */
-#define MCSR_IB 0x40000000 /* Instruction PLB Error */
-#define MCSR_DRB 0x20000000 /* Data Read PLB Error */
-#define MCSR_DWB 0x10000000 /* Data Write PLB Error */
-#define MCSR_TLBP 0x08000000 /* TLB Parity Error */
-#define MCSR_ICP 0x04000000 /* I-Cache Parity Error */
-#define MCSR_DCSP 0x02000000 /* D-Cache Search Parity Error */
-#define MCSR_DCFP 0x01000000 /* D-Cache Flush Parity Error */
-#define MCSR_IMPE 0x00800000 /* Imprecise Machine Check Exception */
-#endif
-#ifdef CONFIG_E500
-#define MCSR_MCP 0x80000000UL /* Machine Check Input Pin */
-#define MCSR_ICPERR 0x40000000UL /* I-Cache Parity Error */
-#define MCSR_DCP_PERR 0x20000000UL /* D-Cache Push Parity Error */
-#define MCSR_DCPERR 0x10000000UL /* D-Cache Parity Error */
-#define MCSR_GL_CI 0x00010000UL /* Guarded Load or Cache-Inhibited stwcx. */
-#define MCSR_BUS_IAERR 0x00000080UL /* Instruction Address Error */
-#define MCSR_BUS_RAERR 0x00000040UL /* Read Address Error */
-#define MCSR_BUS_WAERR 0x00000020UL /* Write Address Error */
-#define MCSR_BUS_IBERR 0x00000010UL /* Instruction Data Error */
-#define MCSR_BUS_RBERR 0x00000008UL /* Read Data Bus Error */
-#define MCSR_BUS_WBERR 0x00000004UL /* Write Data Bus Error */
-#define MCSR_BUS_IPERR 0x00000002UL /* Instruction parity Error */
-#define MCSR_BUS_RPERR 0x00000001UL /* Read parity Error */
-#endif
-#ifdef CONFIG_E200
-#define MCSR_MCP 0x80000000UL /* Machine Check Input Pin */
-#define MCSR_CP_PERR 0x20000000UL /* Cache Push Parity Error */
-#define MCSR_CPERR 0x10000000UL /* Cache Parity Error */
-#define MCSR_EXCP_ERR 0x08000000UL /* ISI, ITLB, or Bus Error on 1st insn
- fetch for an exception handler */
-#define MCSR_BUS_IRERR 0x00000010UL /* Read Bus Error on instruction fetch*/
-#define MCSR_BUS_DRERR 0x00000008UL /* Read Bus Error on data load */
-#define MCSR_BUS_WRERR 0x00000004UL /* Write Bus Error on buffered
- store or cache line push */
-#endif
-
-/* Bit definitions for the DBSR. */
-/*
- * DBSR bits which have conflicting definitions on true Book E versus IBM 40x.
- */
-#ifdef CONFIG_BOOKE
-#define DBSR_IC 0x08000000 /* Instruction Completion */
-#define DBSR_BT 0x04000000 /* Branch Taken */
-#define DBSR_TIE 0x01000000 /* Trap Instruction Event */
-#define DBSR_IAC1 0x00800000 /* Instr Address Compare 1 Event */
-#define DBSR_IAC2 0x00400000 /* Instr Address Compare 2 Event */
-#define DBSR_IAC3 0x00200000 /* Instr Address Compare 3 Event */
-#define DBSR_IAC4 0x00100000 /* Instr Address Compare 4 Event */
-#define DBSR_DAC1R 0x00080000 /* Data Addr Compare 1 Read Event */
-#define DBSR_DAC1W 0x00040000 /* Data Addr Compare 1 Write Event */
-#define DBSR_DAC2R 0x00020000 /* Data Addr Compare 2 Read Event */
-#define DBSR_DAC2W 0x00010000 /* Data Addr Compare 2 Write Event */
-#endif
-#ifdef CONFIG_40x
-#define DBSR_IC 0x80000000 /* Instruction Completion */
-#define DBSR_BT 0x40000000 /* Branch taken */
-#define DBSR_TIE 0x10000000 /* Trap Instruction debug Event */
-#define DBSR_IAC1 0x00800000 /* Instruction Address Compare 1 Event */
-#define DBSR_IAC2 0x00400000 /* Instruction Address Compare 2 Event */
-#define DBSR_IAC3 0x00200000 /* Instruction Address Compare 3 Event */
-#define DBSR_IAC4 0x00100000 /* Instruction Address Compare 4 Event */
-#define DBSR_DAC1R 0x00080000 /* Data Address Compare 1 Read Event */
-#define DBSR_DAC1W 0x00040000 /* Data Address Compare 1 Write Event */
-#define DBSR_DAC2R 0x00020000 /* Data Address Compare 2 Read Event */
-#define DBSR_DAC2W 0x00010000 /* Data Address Compare 2 Write Event */
-#endif
-
-/* Bit definitions related to the ESR. */
-#define ESR_MCI 0x80000000 /* Machine Check - Instruction */
-#define ESR_IMCP 0x80000000 /* Instr. Machine Check - Protection */
-#define ESR_IMCN 0x40000000 /* Instr. Machine Check - Non-config */
-#define ESR_IMCB 0x20000000 /* Instr. Machine Check - Bus error */
-#define ESR_IMCT 0x10000000 /* Instr. Machine Check - Timeout */
-#define ESR_PIL 0x08000000 /* Program Exception - Illegal */
-#define ESR_PPR 0x04000000 /* Program Exception - Priveleged */
-#define ESR_PTR 0x02000000 /* Program Exception - Trap */
-#define ESR_FP 0x01000000 /* Floating Point Operation */
-#define ESR_DST 0x00800000 /* Storage Exception - Data miss */
-#define ESR_DIZ 0x00400000 /* Storage Exception - Zone fault */
-#define ESR_ST 0x00800000 /* Store Operation */
-#define ESR_DLK 0x00200000 /* Data Cache Locking */
-#define ESR_ILK 0x00100000 /* Instr. Cache Locking */
-#define ESR_PUO 0x00040000 /* Unimplemented Operation exception */
-#define ESR_BO 0x00020000 /* Byte Ordering */
-
-/* Bit definitions related to the DBCR0. */
-#define DBCR0_EDM 0x80000000 /* External Debug Mode */
-#define DBCR0_IDM 0x40000000 /* Internal Debug Mode */
-#define DBCR0_RST 0x30000000 /* all the bits in the RST field */
-#define DBCR0_RST_SYSTEM 0x30000000 /* System Reset */
-#define DBCR0_RST_CHIP 0x20000000 /* Chip Reset */
-#define DBCR0_RST_CORE 0x10000000 /* Core Reset */
-#define DBCR0_RST_NONE 0x00000000 /* No Reset */
-#define DBCR0_IC 0x08000000 /* Instruction Completion */
-#define DBCR0_BT 0x04000000 /* Branch Taken */
-#define DBCR0_EDE 0x02000000 /* Exception Debug Event */
-#define DBCR0_TDE 0x01000000 /* TRAP Debug Event */
-#define DBCR0_IA1 0x00800000 /* Instr Addr compare 1 enable */
-#define DBCR0_IA2 0x00400000 /* Instr Addr compare 2 enable */
-#define DBCR0_IA12 0x00200000 /* Instr Addr 1-2 range enable */
-#define DBCR0_IA12X 0x00100000 /* Instr Addr 1-2 range eXclusive */
-#define DBCR0_IA3 0x00080000 /* Instr Addr compare 3 enable */
-#define DBCR0_IA4 0x00040000 /* Instr Addr compare 4 enable */
-#define DBCR0_IA34 0x00020000 /* Instr Addr 3-4 range Enable */
-#define DBCR0_IA34X 0x00010000 /* Instr Addr 3-4 range eXclusive */
-#define DBCR0_IA12T 0x00008000 /* Instr Addr 1-2 range Toggle */
-#define DBCR0_IA34T 0x00004000 /* Instr Addr 3-4 range Toggle */
-#define DBCR0_FT 0x00000001 /* Freeze Timers on debug event */
-
-/* Bit definitions related to the TCR. */
-#define TCR_WP(x) (((x)&0x3)<<30) /* WDT Period */
-#define TCR_WP_MASK TCR_WP(3)
-#define WP_2_17 0 /* 2^17 clocks */
-#define WP_2_21 1 /* 2^21 clocks */
-#define WP_2_25 2 /* 2^25 clocks */
-#define WP_2_29 3 /* 2^29 clocks */
-#define TCR_WRC(x) (((x)&0x3)<<28) /* WDT Reset Control */
-#define TCR_WRC_MASK TCR_WRC(3)
-#define WRC_NONE 0 /* No reset will occur */
-#define WRC_CORE 1 /* Core reset will occur */
-#define WRC_CHIP 2 /* Chip reset will occur */
-#define WRC_SYSTEM 3 /* System reset will occur */
-#define TCR_WIE 0x08000000 /* WDT Interrupt Enable */
-#define TCR_PIE 0x04000000 /* PIT Interrupt Enable */
-#define TCR_DIE TCR_PIE /* DEC Interrupt Enable */
-#define TCR_FP(x) (((x)&0x3)<<24) /* FIT Period */
-#define TCR_FP_MASK TCR_FP(3)
-#define FP_2_9 0 /* 2^9 clocks */
-#define FP_2_13 1 /* 2^13 clocks */
-#define FP_2_17 2 /* 2^17 clocks */
-#define FP_2_21 3 /* 2^21 clocks */
-#define TCR_FIE 0x00800000 /* FIT Interrupt Enable */
-#define TCR_ARE 0x00400000 /* Auto Reload Enable */
-
-/* Bit definitions for the TSR. */
-#define TSR_ENW 0x80000000 /* Enable Next Watchdog */
-#define TSR_WIS 0x40000000 /* WDT Interrupt Status */
-#define TSR_WRS(x) (((x)&0x3)<<28) /* WDT Reset Status */
-#define WRS_NONE 0 /* No WDT reset occurred */
-#define WRS_CORE 1 /* WDT forced core reset */
-#define WRS_CHIP 2 /* WDT forced chip reset */
-#define WRS_SYSTEM 3 /* WDT forced system reset */
-#define TSR_PIS 0x08000000 /* PIT Interrupt Status */
-#define TSR_DIS TSR_PIS /* DEC Interrupt Status */
-#define TSR_FIS 0x04000000 /* FIT Interrupt Status */
-
-/* Bit definitions for the DCCR. */
-#define DCCR_NOCACHE 0 /* Noncacheable */
-#define DCCR_CACHE 1 /* Cacheable */
-
-/* Bit definitions for DCWR. */
-#define DCWR_COPY 0 /* Copy-back */
-#define DCWR_WRITE 1 /* Write-through */
-
-/* Bit definitions for ICCR. */
-#define ICCR_NOCACHE 0 /* Noncacheable */
-#define ICCR_CACHE 1 /* Cacheable */
-
-/* Bit definitions for L1CSR0. */
-#define L1CSR0_CLFC 0x00000100 /* Cache Lock Bits Flash Clear */
-#define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */
-#define L1CSR0_CFI 0x00000002 /* Cache Flash Invalidate */
-#define L1CSR0_DCE 0x00000001 /* Data Cache Enable */
-
-/* Bit definitions for L1CSR1. */
-#define L1CSR1_ICLFR 0x00000100 /* Instr Cache Lock Bits Flash Reset */
-#define L1CSR1_ICFI 0x00000002 /* Instr Cache Flash Invalidate */
-#define L1CSR1_ICE 0x00000001 /* Instr Cache Enable */
-
-/* Bit definitions for SGR. */
-#define SGR_NORMAL 0 /* Speculative fetching allowed. */
-#define SGR_GUARDED 1 /* Speculative fetching disallowed. */
-
-/* Bit definitions for SPEFSCR. */
-#define SPEFSCR_SOVH 0x80000000 /* Summary integer overflow high */
-#define SPEFSCR_OVH 0x40000000 /* Integer overflow high */
-#define SPEFSCR_FGH 0x20000000 /* Embedded FP guard bit high */
-#define SPEFSCR_FXH 0x10000000 /* Embedded FP sticky bit high */
-#define SPEFSCR_FINVH 0x08000000 /* Embedded FP invalid operation high */
-#define SPEFSCR_FDBZH 0x04000000 /* Embedded FP div by zero high */
-#define SPEFSCR_FUNFH 0x02000000 /* Embedded FP underflow high */
-#define SPEFSCR_FOVFH 0x01000000 /* Embedded FP overflow high */
-#define SPEFSCR_FINXS 0x00200000 /* Embedded FP inexact sticky */
-#define SPEFSCR_FINVS 0x00100000 /* Embedded FP invalid op. sticky */
-#define SPEFSCR_FDBZS 0x00080000 /* Embedded FP div by zero sticky */
-#define SPEFSCR_FUNFS 0x00040000 /* Embedded FP underflow sticky */
-#define SPEFSCR_FOVFS 0x00020000 /* Embedded FP overflow sticky */
-#define SPEFSCR_MODE 0x00010000 /* Embedded FP mode */
-#define SPEFSCR_SOV 0x00008000 /* Integer summary overflow */
-#define SPEFSCR_OV 0x00004000 /* Integer overflow */
-#define SPEFSCR_FG 0x00002000 /* Embedded FP guard bit */
-#define SPEFSCR_FX 0x00001000 /* Embedded FP sticky bit */
-#define SPEFSCR_FINV 0x00000800 /* Embedded FP invalid operation */
-#define SPEFSCR_FDBZ 0x00000400 /* Embedded FP div by zero */
-#define SPEFSCR_FUNF 0x00000200 /* Embedded FP underflow */
-#define SPEFSCR_FOVF 0x00000100 /* Embedded FP overflow */
-#define SPEFSCR_FINXE 0x00000040 /* Embedded FP inexact enable */
-#define SPEFSCR_FINVE 0x00000020 /* Embedded FP invalid op. enable */
-#define SPEFSCR_FDBZE 0x00000010 /* Embedded FP div by zero enable */
-#define SPEFSCR_FUNFE 0x00000008 /* Embedded FP underflow enable */
-#define SPEFSCR_FOVFE 0x00000004 /* Embedded FP overflow enable */
-#define SPEFSCR_FRMC 0x00000003 /* Embedded FP rounding mode control */
-
-/*
- * The IBM-403 is an even more odd special case, as it is much
- * older than the IBM-405 series. We put these down here incase someone
- * wishes to support these machines again.
- */
-#ifdef CONFIG_403GCX
-/* Special Purpose Registers (SPRNs)*/
-#define SPRN_TBHU 0x3CC /* Time Base High User-mode */
-#define SPRN_TBLU 0x3CD /* Time Base Low User-mode */
-#define SPRN_CDBCR 0x3D7 /* Cache Debug Control Register */
-#define SPRN_TBHI 0x3DC /* Time Base High */
-#define SPRN_TBLO 0x3DD /* Time Base Low */
-#define SPRN_DBCR 0x3F2 /* Debug Control Regsiter */
-#define SPRN_PBL1 0x3FC /* Protection Bound Lower 1 */
-#define SPRN_PBL2 0x3FE /* Protection Bound Lower 2 */
-#define SPRN_PBU1 0x3FD /* Protection Bound Upper 1 */
-#define SPRN_PBU2 0x3FF /* Protection Bound Upper 2 */
-
-
-/* Bit definitions for the DBCR. */
-#define DBCR_EDM DBCR0_EDM
-#define DBCR_IDM DBCR0_IDM
-#define DBCR_RST(x) (((x) & 0x3) << 28)
-#define DBCR_RST_NONE 0
-#define DBCR_RST_CORE 1
-#define DBCR_RST_CHIP 2
-#define DBCR_RST_SYSTEM 3
-#define DBCR_IC DBCR0_IC /* Instruction Completion Debug Evnt */
-#define DBCR_BT DBCR0_BT /* Branch Taken Debug Event */
-#define DBCR_EDE DBCR0_EDE /* Exception Debug Event */
-#define DBCR_TDE DBCR0_TDE /* TRAP Debug Event */
-#define DBCR_FER 0x00F80000 /* First Events Remaining Mask */
-#define DBCR_FT 0x00040000 /* Freeze Timers on Debug Event */
-#define DBCR_IA1 0x00020000 /* Instr. Addr. Compare 1 Enable */
-#define DBCR_IA2 0x00010000 /* Instr. Addr. Compare 2 Enable */
-#define DBCR_D1R 0x00008000 /* Data Addr. Compare 1 Read Enable */
-#define DBCR_D1W 0x00004000 /* Data Addr. Compare 1 Write Enable */
-#define DBCR_D1S(x) (((x) & 0x3) << 12) /* Data Adrr. Compare 1 Size */
-#define DAC_BYTE 0
-#define DAC_HALF 1
-#define DAC_WORD 2
-#define DAC_QUAD 3
-#define DBCR_D2R 0x00000800 /* Data Addr. Compare 2 Read Enable */
-#define DBCR_D2W 0x00000400 /* Data Addr. Compare 2 Write Enable */
-#define DBCR_D2S(x) (((x) & 0x3) << 8) /* Data Addr. Compare 2 Size */
-#define DBCR_SBT 0x00000040 /* Second Branch Taken Debug Event */
-#define DBCR_SED 0x00000020 /* Second Exception Debug Event */
-#define DBCR_STD 0x00000010 /* Second Trap Debug Event */
-#define DBCR_SIA 0x00000008 /* Second IAC Enable */
-#define DBCR_SDA 0x00000004 /* Second DAC Enable */
-#define DBCR_JOI 0x00000002 /* JTAG Serial Outbound Int. Enable */
-#define DBCR_JII 0x00000001 /* JTAG Serial Inbound Int. Enable */
-#endif /* 403GCX */
-#endif /* __ASM_PPC_REG_BOOKE_H__ */
-#endif /* __KERNEL__ */
--
1.2.4
^ permalink raw reply related
* [PATCH 12/15] powerpc: move asm/ocp_ids.h
From: sfr @ 2006-04-05 5:10 UTC (permalink / raw)
To: paulus; +Cc: linuxppc-dev, Stephen Rothwell
In-Reply-To: <11442138494042-git-send-email-sfr@canb.auug.org.au>
From: Stephen Rothwell <sfr@canb.auug.org.au>
Since the ARCH=powerpc build depends on this file, move it to
include/asm-powerpc.
Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
---
include/asm-powerpc/ocp_ids.h | 75 +++++++++++++++++++++++++++++++++++++++++
include/asm-ppc/ocp_ids.h | 73 ----------------------------------------
2 files changed, 75 insertions(+), 73 deletions(-)
create mode 100644 include/asm-powerpc/ocp_ids.h
delete mode 100644 include/asm-ppc/ocp_ids.h
a374f458829d868a3142bff918ef872e0ecff1a8
diff --git a/include/asm-powerpc/ocp_ids.h b/include/asm-powerpc/ocp_ids.h
new file mode 100644
index 0000000..78e5906
--- /dev/null
+++ b/include/asm-powerpc/ocp_ids.h
@@ -0,0 +1,75 @@
+#ifndef _ASM_POWERPC_OCP_IDS_H
+#define _ASM_POWERPC_OCP_IDS_H
+/*
+ * OCP device ids based on the ideas from PCI
+ *
+ * The numbers below are almost completely arbitrary, and in fact
+ * strings might work better. -- paulus
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+/*
+ * Vender device
+ * [xxxx] [xxxx]
+ *
+ * Keep in order, please
+ */
+
+/* Vendor IDs 0x0001 - 0xFFFF copied from pci_ids.h */
+
+#define OCP_VENDOR_INVALID 0x0000
+#define OCP_VENDOR_ARM 0x0004
+#define OCP_VENDOR_FREESCALE 0x1057
+#define OCP_VENDOR_IBM 0x1014
+#define OCP_VENDOR_MOTOROLA OCP_VENDOR_FREESCALE
+#define OCP_VENDOR_XILINX 0x10ee
+#define OCP_VENDOR_UNKNOWN 0xFFFF
+
+/* device identification */
+
+/* define type */
+#define OCP_FUNC_INVALID 0x0000
+
+/* system 0x0001 - 0x001F */
+
+/* Timers 0x0020 - 0x002F */
+
+/* Serial 0x0030 - 0x006F*/
+#define OCP_FUNC_16550 0x0031
+#define OCP_FUNC_IIC 0x0032
+#define OCP_FUNC_USB 0x0033
+#define OCP_FUNC_PSC_UART 0x0034
+
+/* Memory devices 0x0090 - 0x009F */
+#define OCP_FUNC_MAL 0x0090
+#define OCP_FUNC_DMA 0x0091
+
+/* Display 0x00A0 - 0x00AF */
+
+/* Sound 0x00B0 - 0x00BF */
+
+/* Mass Storage 0x00C0 - 0xxCF */
+#define OCP_FUNC_IDE 0x00C0
+
+/* Misc 0x00D0 - 0x00DF*/
+#define OCP_FUNC_GPIO 0x00D0
+#define OCP_FUNC_ZMII 0x00D1
+#define OCP_FUNC_PERFMON 0x00D2 /* Performance Monitor */
+#define OCP_FUNC_RGMII 0x00D3
+#define OCP_FUNC_TAH 0x00D4
+#define OCP_FUNC_SEC2 0x00D5 /* Crypto/Security 2.0 */
+
+/* Network 0x0200 - 0x02FF */
+#define OCP_FUNC_EMAC 0x0200
+#define OCP_FUNC_GFAR 0x0201 /* TSEC & FEC */
+
+/* Bridge devices 0xE00 - 0xEFF */
+#define OCP_FUNC_OPB 0x0E00
+
+#define OCP_FUNC_UNKNOWN 0xFFFF
+
+#endif /* _ASM_POWERPC_OCP_IDS_H */
diff --git a/include/asm-ppc/ocp_ids.h b/include/asm-ppc/ocp_ids.h
deleted file mode 100644
index 8ae4b31..0000000
--- a/include/asm-ppc/ocp_ids.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * ocp_ids.h
- *
- * OCP device ids based on the ideas from PCI
- *
- * The numbers below are almost completely arbitrary, and in fact
- * strings might work better. -- paulus
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- */
-
-/*
- * Vender device
- * [xxxx] [xxxx]
- *
- * Keep in order, please
- */
-
-/* Vendor IDs 0x0001 - 0xFFFF copied from pci_ids.h */
-
-#define OCP_VENDOR_INVALID 0x0000
-#define OCP_VENDOR_ARM 0x0004
-#define OCP_VENDOR_FREESCALE 0x1057
-#define OCP_VENDOR_IBM 0x1014
-#define OCP_VENDOR_MOTOROLA OCP_VENDOR_FREESCALE
-#define OCP_VENDOR_XILINX 0x10ee
-#define OCP_VENDOR_UNKNOWN 0xFFFF
-
-/* device identification */
-
-/* define type */
-#define OCP_FUNC_INVALID 0x0000
-
-/* system 0x0001 - 0x001F */
-
-/* Timers 0x0020 - 0x002F */
-
-/* Serial 0x0030 - 0x006F*/
-#define OCP_FUNC_16550 0x0031
-#define OCP_FUNC_IIC 0x0032
-#define OCP_FUNC_USB 0x0033
-#define OCP_FUNC_PSC_UART 0x0034
-
-/* Memory devices 0x0090 - 0x009F */
-#define OCP_FUNC_MAL 0x0090
-#define OCP_FUNC_DMA 0x0091
-
-/* Display 0x00A0 - 0x00AF */
-
-/* Sound 0x00B0 - 0x00BF */
-
-/* Mass Storage 0x00C0 - 0xxCF */
-#define OCP_FUNC_IDE 0x00C0
-
-/* Misc 0x00D0 - 0x00DF*/
-#define OCP_FUNC_GPIO 0x00D0
-#define OCP_FUNC_ZMII 0x00D1
-#define OCP_FUNC_PERFMON 0x00D2 /* Performance Monitor */
-#define OCP_FUNC_RGMII 0x00D3
-#define OCP_FUNC_TAH 0x00D4
-#define OCP_FUNC_SEC2 0x00D5 /* Crypto/Security 2.0 */
-
-/* Network 0x0200 - 0x02FF */
-#define OCP_FUNC_EMAC 0x0200
-#define OCP_FUNC_GFAR 0x0201 /* TSEC & FEC */
-
-/* Bridge devices 0xE00 - 0xEFF */
-#define OCP_FUNC_OPB 0x0E00
-
-#define OCP_FUNC_UNKNOWN 0xFFFF
--
1.2.4
^ permalink raw reply related
* [PATCH 11/15] powerpc: move asm/ocp.h
From: sfr @ 2006-04-05 5:10 UTC (permalink / raw)
To: paulus; +Cc: linuxppc-dev, Stephen Rothwell
In-Reply-To: <11442138494042-git-send-email-sfr@canb.auug.org.au>
From: Stephen Rothwell <sfr@canb.auug.org.au>
Since the ARCH=powerpc build depends on this file, move it to
include/asm-powerpc.
Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
---
include/asm-powerpc/ocp.h | 206 +++++++++++++++++++++++++++++++++++++++++++++
include/asm-ppc/ocp.h | 207 ---------------------------------------------
2 files changed, 206 insertions(+), 207 deletions(-)
create mode 100644 include/asm-powerpc/ocp.h
delete mode 100644 include/asm-ppc/ocp.h
c7b417812dc2ebece32356c0a5e93966de9ba2cd
diff --git a/include/asm-powerpc/ocp.h b/include/asm-powerpc/ocp.h
new file mode 100644
index 0000000..8916c52
--- /dev/null
+++ b/include/asm-powerpc/ocp.h
@@ -0,0 +1,206 @@
+#ifndef _ASM_POWERPC_OCP_H
+#define _ASM_POWERPC_OCP_H
+/*
+ * ocp.h
+ *
+ * (c) Benjamin Herrenschmidt (benh@kernel.crashing.org)
+ * Mipsys - France
+ *
+ * Derived from work (c) Armin Kuster akuster@pacbell.net
+ *
+ * Additional support and port to 2.6 LDM/sysfs by
+ * Matt Porter <mporter@kernel.crashing.org>
+ * Copyright 2003-2004 MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * TODO: - Add get/put interface & fixup locking to provide same API for
+ * 2.4 and 2.5
+ * - Rework PM callbacks
+ */
+
+#ifdef __KERNEL__
+
+#include <linux/init.h>
+#include <linux/list.h>
+#include <linux/devfs_fs_kernel.h>
+#include <linux/device.h>
+
+#include <asm/mmu.h>
+#include <asm/ocp_ids.h>
+#include <asm/rwsem.h>
+#include <asm/semaphore.h>
+
+#ifdef CONFIG_PPC_OCP
+
+#define OCP_MAX_IRQS 7
+#define MAX_EMACS 4
+#define OCP_IRQ_NA -1 /* used when ocp device does not have an irq */
+#define OCP_IRQ_MUL -2 /* used for ocp devices with multiply irqs */
+#define OCP_NULL_TYPE -1 /* used to mark end of list */
+#define OCP_CPM_NA 0 /* No Clock or Power Management avaliable */
+#define OCP_PADDR_NA 0 /* No MMIO registers */
+
+#define OCP_ANY_ID (~0)
+#define OCP_ANY_INDEX -1
+
+extern struct list_head ocp_devices;
+extern struct rw_semaphore ocp_devices_sem;
+
+struct ocp_device_id {
+ unsigned int vendor, function; /* Vendor and function ID or OCP_ANY_ID */
+ unsigned long driver_data; /* Data private to the driver */
+};
+
+
+/*
+ * Static definition of an OCP device.
+ *
+ * @vendor: Vendor code. It is _STRONGLY_ discouraged to use
+ * the vendor code as a way to match a unique device,
+ * though I kept that possibility open, you should
+ * really define different function codes for different
+ * device types
+ * @function: This is the function code for this device.
+ * @index: This index is used for mapping the Nth function of a
+ * given core. This is typically used for cross-driver
+ * matching, like looking for a given MAL or ZMII from
+ * an EMAC or for getting to the proper set of DCRs.
+ * Indices are no longer magically calculated based on
+ * structure ordering, they have to be actually coded
+ * into the ocp_def to avoid any possible confusion
+ * I _STRONGLY_ (again ? wow !) encourage anybody relying
+ * on index mapping to encode the "target" index in an
+ * associated structure pointed to by "additions", see
+ * how it's done for the EMAC driver.
+ * @paddr: Device physical address (may not mean anything...)
+ * @irq: Interrupt line for this device (TODO: think about making
+ * an array with this)
+ * @pm: Currently, contains the bitmask in CPMFR DCR for the device
+ * @additions: Optionally points to a function specific structure
+ * providing additional informations for a given device
+ * instance. It's currently used by the EMAC driver for MAL
+ * channel & ZMII port mapping among others.
+ * @show: Optionally points to a function specific structure
+ * providing a sysfs show routine for additions fields.
+ */
+struct ocp_def {
+ unsigned int vendor;
+ unsigned int function;
+ int index;
+ phys_addr_t paddr;
+ int irq;
+ unsigned long pm;
+ void *additions;
+ void (*show)(struct device *);
+};
+
+
+/* Struct for a given device instance */
+struct ocp_device {
+ struct list_head link;
+ char name[80]; /* device name */
+ struct ocp_def *def; /* device definition */
+ void *drvdata; /* driver data for this device */
+ struct ocp_driver *driver;
+ u32 current_state; /* Current operating state. In ACPI-speak,
+ this is D0-D3, D0 being fully functional,
+ and D3 being off. */
+ struct device dev;
+};
+
+struct ocp_driver {
+ struct list_head node;
+ char *name;
+ const struct ocp_device_id *id_table; /* NULL if wants all devices */
+ int (*probe) (struct ocp_device *dev); /* New device inserted */
+ void (*remove) (struct ocp_device *dev); /* Device removed (NULL if not a hot-plug capable driver) */
+ int (*suspend) (struct ocp_device *dev, pm_message_t state); /* Device suspended */
+ int (*resume) (struct ocp_device *dev); /* Device woken up */
+ struct device_driver driver;
+};
+
+#define to_ocp_dev(n) container_of(n, struct ocp_device, dev)
+#define to_ocp_drv(n) container_of(n, struct ocp_driver, driver)
+
+/* Similar to the helpers above, these manipulate per-ocp_dev
+ * driver-specific data. Currently stored as ocp_dev::ocpdev,
+ * a void pointer, but it is not present on older kernels.
+ */
+static inline void *
+ocp_get_drvdata(struct ocp_device *pdev)
+{
+ return pdev->drvdata;
+}
+
+static inline void
+ocp_set_drvdata(struct ocp_device *pdev, void *data)
+{
+ pdev->drvdata = data;
+}
+
+#if defined (CONFIG_PM)
+/*
+ * This is right for the IBM 405 and 440 but will need to be
+ * generalized if the OCP stuff gets used on other processors.
+ */
+static inline void
+ocp_force_power_off(struct ocp_device *odev)
+{
+ mtdcr(DCRN_CPMFR, mfdcr(DCRN_CPMFR) | odev->def->pm);
+}
+
+static inline void
+ocp_force_power_on(struct ocp_device *odev)
+{
+ mtdcr(DCRN_CPMFR, mfdcr(DCRN_CPMFR) & ~odev->def->pm);
+}
+#else
+#define ocp_force_power_off(x) (void)(x)
+#define ocp_force_power_on(x) (void)(x)
+#endif
+
+/* Register/Unregister an OCP driver */
+extern int ocp_register_driver(struct ocp_driver *drv);
+extern void ocp_unregister_driver(struct ocp_driver *drv);
+
+/* Build list of devices */
+extern int ocp_early_init(void) __init;
+
+/* Find a device by index */
+extern struct ocp_device *ocp_find_device(unsigned int vendor, unsigned int function, int index);
+
+/* Get a def by index */
+extern struct ocp_def *ocp_get_one_device(unsigned int vendor, unsigned int function, int index);
+
+/* Add a device by index */
+extern int ocp_add_one_device(struct ocp_def *def);
+
+/* Remove a device by index */
+extern int ocp_remove_one_device(unsigned int vendor, unsigned int function, int index);
+
+/* Iterate over devices and execute a routine */
+extern void ocp_for_each_device(void(*callback)(struct ocp_device *, void *arg), void *arg);
+
+/* Sysfs support */
+#define OCP_SYSFS_ADDTL(type, format, name, field) \
+static ssize_t \
+show_##name##_##field(struct device *dev, struct device_attribute *attr, char *buf) \
+{ \
+ struct ocp_device *odev = to_ocp_dev(dev); \
+ type *add = odev->def->additions; \
+ \
+ return sprintf(buf, format, add->field); \
+} \
+static DEVICE_ATTR(name##_##field, S_IRUGO, show_##name##_##field, NULL);
+
+#ifdef CONFIG_IBM_OCP
+#include <asm/ibm_ocp.h>
+#endif
+
+#endif /* CONFIG_PPC_OCP */
+#endif /* __KERNEL__ */
+#endif /* _ASM_POWERPC_OCP_H */
diff --git a/include/asm-ppc/ocp.h b/include/asm-ppc/ocp.h
deleted file mode 100644
index 983116f..0000000
--- a/include/asm-ppc/ocp.h
+++ /dev/null
@@ -1,207 +0,0 @@
-/*
- * ocp.h
- *
- * (c) Benjamin Herrenschmidt (benh@kernel.crashing.org)
- * Mipsys - France
- *
- * Derived from work (c) Armin Kuster akuster@pacbell.net
- *
- * Additional support and port to 2.6 LDM/sysfs by
- * Matt Porter <mporter@kernel.crashing.org>
- * Copyright 2003-2004 MontaVista Software, Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * TODO: - Add get/put interface & fixup locking to provide same API for
- * 2.4 and 2.5
- * - Rework PM callbacks
- */
-
-#ifdef __KERNEL__
-#ifndef __OCP_H__
-#define __OCP_H__
-
-#include <linux/init.h>
-#include <linux/list.h>
-#include <linux/config.h>
-#include <linux/devfs_fs_kernel.h>
-#include <linux/device.h>
-
-#include <asm/mmu.h>
-#include <asm/ocp_ids.h>
-#include <asm/rwsem.h>
-#include <asm/semaphore.h>
-
-#ifdef CONFIG_PPC_OCP
-
-#define OCP_MAX_IRQS 7
-#define MAX_EMACS 4
-#define OCP_IRQ_NA -1 /* used when ocp device does not have an irq */
-#define OCP_IRQ_MUL -2 /* used for ocp devices with multiply irqs */
-#define OCP_NULL_TYPE -1 /* used to mark end of list */
-#define OCP_CPM_NA 0 /* No Clock or Power Management avaliable */
-#define OCP_PADDR_NA 0 /* No MMIO registers */
-
-#define OCP_ANY_ID (~0)
-#define OCP_ANY_INDEX -1
-
-extern struct list_head ocp_devices;
-extern struct rw_semaphore ocp_devices_sem;
-
-struct ocp_device_id {
- unsigned int vendor, function; /* Vendor and function ID or OCP_ANY_ID */
- unsigned long driver_data; /* Data private to the driver */
-};
-
-
-/*
- * Static definition of an OCP device.
- *
- * @vendor: Vendor code. It is _STRONGLY_ discouraged to use
- * the vendor code as a way to match a unique device,
- * though I kept that possibility open, you should
- * really define different function codes for different
- * device types
- * @function: This is the function code for this device.
- * @index: This index is used for mapping the Nth function of a
- * given core. This is typically used for cross-driver
- * matching, like looking for a given MAL or ZMII from
- * an EMAC or for getting to the proper set of DCRs.
- * Indices are no longer magically calculated based on
- * structure ordering, they have to be actually coded
- * into the ocp_def to avoid any possible confusion
- * I _STRONGLY_ (again ? wow !) encourage anybody relying
- * on index mapping to encode the "target" index in an
- * associated structure pointed to by "additions", see
- * how it's done for the EMAC driver.
- * @paddr: Device physical address (may not mean anything...)
- * @irq: Interrupt line for this device (TODO: think about making
- * an array with this)
- * @pm: Currently, contains the bitmask in CPMFR DCR for the device
- * @additions: Optionally points to a function specific structure
- * providing additional informations for a given device
- * instance. It's currently used by the EMAC driver for MAL
- * channel & ZMII port mapping among others.
- * @show: Optionally points to a function specific structure
- * providing a sysfs show routine for additions fields.
- */
-struct ocp_def {
- unsigned int vendor;
- unsigned int function;
- int index;
- phys_addr_t paddr;
- int irq;
- unsigned long pm;
- void *additions;
- void (*show)(struct device *);
-};
-
-
-/* Struct for a given device instance */
-struct ocp_device {
- struct list_head link;
- char name[80]; /* device name */
- struct ocp_def *def; /* device definition */
- void *drvdata; /* driver data for this device */
- struct ocp_driver *driver;
- u32 current_state; /* Current operating state. In ACPI-speak,
- this is D0-D3, D0 being fully functional,
- and D3 being off. */
- struct device dev;
-};
-
-struct ocp_driver {
- struct list_head node;
- char *name;
- const struct ocp_device_id *id_table; /* NULL if wants all devices */
- int (*probe) (struct ocp_device *dev); /* New device inserted */
- void (*remove) (struct ocp_device *dev); /* Device removed (NULL if not a hot-plug capable driver) */
- int (*suspend) (struct ocp_device *dev, pm_message_t state); /* Device suspended */
- int (*resume) (struct ocp_device *dev); /* Device woken up */
- struct device_driver driver;
-};
-
-#define to_ocp_dev(n) container_of(n, struct ocp_device, dev)
-#define to_ocp_drv(n) container_of(n, struct ocp_driver, driver)
-
-/* Similar to the helpers above, these manipulate per-ocp_dev
- * driver-specific data. Currently stored as ocp_dev::ocpdev,
- * a void pointer, but it is not present on older kernels.
- */
-static inline void *
-ocp_get_drvdata(struct ocp_device *pdev)
-{
- return pdev->drvdata;
-}
-
-static inline void
-ocp_set_drvdata(struct ocp_device *pdev, void *data)
-{
- pdev->drvdata = data;
-}
-
-#if defined (CONFIG_PM)
-/*
- * This is right for the IBM 405 and 440 but will need to be
- * generalized if the OCP stuff gets used on other processors.
- */
-static inline void
-ocp_force_power_off(struct ocp_device *odev)
-{
- mtdcr(DCRN_CPMFR, mfdcr(DCRN_CPMFR) | odev->def->pm);
-}
-
-static inline void
-ocp_force_power_on(struct ocp_device *odev)
-{
- mtdcr(DCRN_CPMFR, mfdcr(DCRN_CPMFR) & ~odev->def->pm);
-}
-#else
-#define ocp_force_power_off(x) (void)(x)
-#define ocp_force_power_on(x) (void)(x)
-#endif
-
-/* Register/Unregister an OCP driver */
-extern int ocp_register_driver(struct ocp_driver *drv);
-extern void ocp_unregister_driver(struct ocp_driver *drv);
-
-/* Build list of devices */
-extern int ocp_early_init(void) __init;
-
-/* Find a device by index */
-extern struct ocp_device *ocp_find_device(unsigned int vendor, unsigned int function, int index);
-
-/* Get a def by index */
-extern struct ocp_def *ocp_get_one_device(unsigned int vendor, unsigned int function, int index);
-
-/* Add a device by index */
-extern int ocp_add_one_device(struct ocp_def *def);
-
-/* Remove a device by index */
-extern int ocp_remove_one_device(unsigned int vendor, unsigned int function, int index);
-
-/* Iterate over devices and execute a routine */
-extern void ocp_for_each_device(void(*callback)(struct ocp_device *, void *arg), void *arg);
-
-/* Sysfs support */
-#define OCP_SYSFS_ADDTL(type, format, name, field) \
-static ssize_t \
-show_##name##_##field(struct device *dev, struct device_attribute *attr, char *buf) \
-{ \
- struct ocp_device *odev = to_ocp_dev(dev); \
- type *add = odev->def->additions; \
- \
- return sprintf(buf, format, add->field); \
-} \
-static DEVICE_ATTR(name##_##field, S_IRUGO, show_##name##_##field, NULL);
-
-#ifdef CONFIG_IBM_OCP
-#include <asm/ibm_ocp.h>
-#endif
-
-#endif /* CONFIG_PPC_OCP */
-#endif /* __OCP_H__ */
-#endif /* __KERNEL__ */
--
1.2.4
^ permalink raw reply related
* [PATCH 10/15] powerpc: move asm/mpc83xx.h
From: sfr @ 2006-04-05 5:10 UTC (permalink / raw)
To: paulus; +Cc: linuxppc-dev, Stephen Rothwell
In-Reply-To: <11442138494042-git-send-email-sfr@canb.auug.org.au>
From: Stephen Rothwell <sfr@canb.auug.org.au>
Since the ARCH=powerpc build depends on this file, move it to
include/asm-powerpc.
Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
---
include/asm-powerpc/mpc83xx.h | 115 +++++++++++++++++++++++++++++++++++++++++
include/asm-ppc/mpc83xx.h | 116 -----------------------------------------
2 files changed, 115 insertions(+), 116 deletions(-)
create mode 100644 include/asm-powerpc/mpc83xx.h
delete mode 100644 include/asm-ppc/mpc83xx.h
ce28e1e8654ad07cc23573a31f8cea992d41f9cc
diff --git a/include/asm-powerpc/mpc83xx.h b/include/asm-powerpc/mpc83xx.h
new file mode 100644
index 0000000..da4b0fa
--- /dev/null
+++ b/include/asm-powerpc/mpc83xx.h
@@ -0,0 +1,115 @@
+#ifndef _ASM_POWERPC_MPC83XX_H
+#define _ASM_POWERPC_MPC83XX_H
+/*
+ * include/asm-ppc/mpc83xx.h
+ *
+ * MPC83xx definitions
+ *
+ * Maintainer: Kumar Gala <galak@kernel.crashing.org>
+ *
+ * Copyright 2005 Freescale Semiconductor, Inc
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#ifdef __KERNEL__
+
+#include <asm/mmu.h>
+
+#ifdef CONFIG_83xx
+
+#ifdef CONFIG_MPC834x_SYS
+#include <platforms/83xx/mpc834x_sys.h>
+#endif
+
+#define _IO_BASE isa_io_base
+#define _ISA_MEM_BASE isa_mem_base
+#ifdef CONFIG_PCI
+#define PCI_DRAM_OFFSET pci_dram_offset
+#else
+#define PCI_DRAM_OFFSET 0
+#endif
+
+/*
+ * The "residual" board information structure the boot loader passes
+ * into the kernel.
+ */
+extern unsigned char __res[];
+
+/* Internal IRQs on MPC83xx OpenPIC */
+/* Not all of these exist on all MPC83xx implementations */
+
+#ifndef MPC83xx_IPIC_IRQ_OFFSET
+#define MPC83xx_IPIC_IRQ_OFFSET 0
+#endif
+
+#define NR_IPIC_INTS 128
+
+#define MPC83xx_IRQ_UART1 ( 9 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_UART2 (10 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_SEC2 (11 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_IIC1 (14 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_IIC2 (15 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_SPI (16 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_EXT1 (17 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_EXT2 (18 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_EXT3 (19 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_EXT4 (20 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_EXT5 (21 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_EXT6 (22 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_EXT7 (23 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_TSEC1_TX (32 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_TSEC1_RX (33 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_TSEC1_ERROR (34 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_TSEC2_TX (35 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_TSEC2_RX (36 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_TSEC2_ERROR (37 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_USB2_DR (38 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_USB2_MPH (39 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_EXT0 (48 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_RTC_SEC (64 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_PIT (65 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_PCI1 (66 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_PCI2 (67 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_RTC_ALR (68 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_MU (69 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_SBA (70 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_DMA (71 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_GTM4 (72 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_GTM8 (73 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_GPIO1 (74 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_GPIO2 (75 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_DDR (76 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_LBC (77 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_GTM2 (78 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_GTM6 (79 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_PMC (80 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_GTM3 (84 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_GTM7 (85 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_GTM1 (90 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_GTM5 (91 + MPC83xx_IPIC_IRQ_OFFSET)
+
+#define MPC83xx_CCSRBAR_SIZE (1024*1024)
+
+/* Let modules/drivers get at immrbar (physical) */
+extern phys_addr_t immrbar;
+
+enum ppc_sys_devices {
+ MPC83xx_TSEC1,
+ MPC83xx_TSEC2,
+ MPC83xx_IIC1,
+ MPC83xx_IIC2,
+ MPC83xx_DUART,
+ MPC83xx_SEC2,
+ MPC83xx_USB2_DR,
+ MPC83xx_USB2_MPH,
+ MPC83xx_MDIO,
+ NUM_PPC_SYS_DEVS,
+};
+
+#endif /* CONFIG_83xx */
+#endif /* __KERNEL__ */
+#endif /* _ASM_POWERPC_MPC83XX_H */
diff --git a/include/asm-ppc/mpc83xx.h b/include/asm-ppc/mpc83xx.h
deleted file mode 100644
index 3c23fc4..0000000
--- a/include/asm-ppc/mpc83xx.h
+++ /dev/null
@@ -1,116 +0,0 @@
-/*
- * include/asm-ppc/mpc83xx.h
- *
- * MPC83xx definitions
- *
- * Maintainer: Kumar Gala <galak@kernel.crashing.org>
- *
- * Copyright 2005 Freescale Semiconductor, Inc
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- */
-
-#ifdef __KERNEL__
-#ifndef __ASM_MPC83xx_H__
-#define __ASM_MPC83xx_H__
-
-#include <linux/config.h>
-#include <asm/mmu.h>
-
-#ifdef CONFIG_83xx
-
-#ifdef CONFIG_MPC834x_SYS
-#include <platforms/83xx/mpc834x_sys.h>
-#endif
-
-#define _IO_BASE isa_io_base
-#define _ISA_MEM_BASE isa_mem_base
-#ifdef CONFIG_PCI
-#define PCI_DRAM_OFFSET pci_dram_offset
-#else
-#define PCI_DRAM_OFFSET 0
-#endif
-
-/*
- * The "residual" board information structure the boot loader passes
- * into the kernel.
- */
-extern unsigned char __res[];
-
-/* Internal IRQs on MPC83xx OpenPIC */
-/* Not all of these exist on all MPC83xx implementations */
-
-#ifndef MPC83xx_IPIC_IRQ_OFFSET
-#define MPC83xx_IPIC_IRQ_OFFSET 0
-#endif
-
-#define NR_IPIC_INTS 128
-
-#define MPC83xx_IRQ_UART1 ( 9 + MPC83xx_IPIC_IRQ_OFFSET)
-#define MPC83xx_IRQ_UART2 (10 + MPC83xx_IPIC_IRQ_OFFSET)
-#define MPC83xx_IRQ_SEC2 (11 + MPC83xx_IPIC_IRQ_OFFSET)
-#define MPC83xx_IRQ_IIC1 (14 + MPC83xx_IPIC_IRQ_OFFSET)
-#define MPC83xx_IRQ_IIC2 (15 + MPC83xx_IPIC_IRQ_OFFSET)
-#define MPC83xx_IRQ_SPI (16 + MPC83xx_IPIC_IRQ_OFFSET)
-#define MPC83xx_IRQ_EXT1 (17 + MPC83xx_IPIC_IRQ_OFFSET)
-#define MPC83xx_IRQ_EXT2 (18 + MPC83xx_IPIC_IRQ_OFFSET)
-#define MPC83xx_IRQ_EXT3 (19 + MPC83xx_IPIC_IRQ_OFFSET)
-#define MPC83xx_IRQ_EXT4 (20 + MPC83xx_IPIC_IRQ_OFFSET)
-#define MPC83xx_IRQ_EXT5 (21 + MPC83xx_IPIC_IRQ_OFFSET)
-#define MPC83xx_IRQ_EXT6 (22 + MPC83xx_IPIC_IRQ_OFFSET)
-#define MPC83xx_IRQ_EXT7 (23 + MPC83xx_IPIC_IRQ_OFFSET)
-#define MPC83xx_IRQ_TSEC1_TX (32 + MPC83xx_IPIC_IRQ_OFFSET)
-#define MPC83xx_IRQ_TSEC1_RX (33 + MPC83xx_IPIC_IRQ_OFFSET)
-#define MPC83xx_IRQ_TSEC1_ERROR (34 + MPC83xx_IPIC_IRQ_OFFSET)
-#define MPC83xx_IRQ_TSEC2_TX (35 + MPC83xx_IPIC_IRQ_OFFSET)
-#define MPC83xx_IRQ_TSEC2_RX (36 + MPC83xx_IPIC_IRQ_OFFSET)
-#define MPC83xx_IRQ_TSEC2_ERROR (37 + MPC83xx_IPIC_IRQ_OFFSET)
-#define MPC83xx_IRQ_USB2_DR (38 + MPC83xx_IPIC_IRQ_OFFSET)
-#define MPC83xx_IRQ_USB2_MPH (39 + MPC83xx_IPIC_IRQ_OFFSET)
-#define MPC83xx_IRQ_EXT0 (48 + MPC83xx_IPIC_IRQ_OFFSET)
-#define MPC83xx_IRQ_RTC_SEC (64 + MPC83xx_IPIC_IRQ_OFFSET)
-#define MPC83xx_IRQ_PIT (65 + MPC83xx_IPIC_IRQ_OFFSET)
-#define MPC83xx_IRQ_PCI1 (66 + MPC83xx_IPIC_IRQ_OFFSET)
-#define MPC83xx_IRQ_PCI2 (67 + MPC83xx_IPIC_IRQ_OFFSET)
-#define MPC83xx_IRQ_RTC_ALR (68 + MPC83xx_IPIC_IRQ_OFFSET)
-#define MPC83xx_IRQ_MU (69 + MPC83xx_IPIC_IRQ_OFFSET)
-#define MPC83xx_IRQ_SBA (70 + MPC83xx_IPIC_IRQ_OFFSET)
-#define MPC83xx_IRQ_DMA (71 + MPC83xx_IPIC_IRQ_OFFSET)
-#define MPC83xx_IRQ_GTM4 (72 + MPC83xx_IPIC_IRQ_OFFSET)
-#define MPC83xx_IRQ_GTM8 (73 + MPC83xx_IPIC_IRQ_OFFSET)
-#define MPC83xx_IRQ_GPIO1 (74 + MPC83xx_IPIC_IRQ_OFFSET)
-#define MPC83xx_IRQ_GPIO2 (75 + MPC83xx_IPIC_IRQ_OFFSET)
-#define MPC83xx_IRQ_DDR (76 + MPC83xx_IPIC_IRQ_OFFSET)
-#define MPC83xx_IRQ_LBC (77 + MPC83xx_IPIC_IRQ_OFFSET)
-#define MPC83xx_IRQ_GTM2 (78 + MPC83xx_IPIC_IRQ_OFFSET)
-#define MPC83xx_IRQ_GTM6 (79 + MPC83xx_IPIC_IRQ_OFFSET)
-#define MPC83xx_IRQ_PMC (80 + MPC83xx_IPIC_IRQ_OFFSET)
-#define MPC83xx_IRQ_GTM3 (84 + MPC83xx_IPIC_IRQ_OFFSET)
-#define MPC83xx_IRQ_GTM7 (85 + MPC83xx_IPIC_IRQ_OFFSET)
-#define MPC83xx_IRQ_GTM1 (90 + MPC83xx_IPIC_IRQ_OFFSET)
-#define MPC83xx_IRQ_GTM5 (91 + MPC83xx_IPIC_IRQ_OFFSET)
-
-#define MPC83xx_CCSRBAR_SIZE (1024*1024)
-
-/* Let modules/drivers get at immrbar (physical) */
-extern phys_addr_t immrbar;
-
-enum ppc_sys_devices {
- MPC83xx_TSEC1,
- MPC83xx_TSEC2,
- MPC83xx_IIC1,
- MPC83xx_IIC2,
- MPC83xx_DUART,
- MPC83xx_SEC2,
- MPC83xx_USB2_DR,
- MPC83xx_USB2_MPH,
- MPC83xx_MDIO,
- NUM_PPC_SYS_DEVS,
-};
-
-#endif /* CONFIG_83xx */
-#endif /* __ASM_MPC83xx_H__ */
-#endif /* __KERNEL__ */
--
1.2.4
^ permalink raw reply related
* [PATCH 09/15] powerpc: move asm/hydra.h
From: sfr @ 2006-04-05 5:10 UTC (permalink / raw)
To: paulus; +Cc: linuxppc-dev, Stephen Rothwell
In-Reply-To: <11442138494042-git-send-email-sfr@canb.auug.org.au>
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain, Size: 7131 bytes --]
From: Stephen Rothwell <sfr@canb.auug.org.au>
Since the ARCH=powerpc build depends on this file, move it to
include/asm-powerpc.
Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
---
include/asm-powerpc/hydra.h | 102 +++++++++++++++++++++++++++++++++++++++++++
include/asm-ppc/hydra.h | 102 -------------------------------------------
2 files changed, 102 insertions(+), 102 deletions(-)
create mode 100644 include/asm-powerpc/hydra.h
delete mode 100644 include/asm-ppc/hydra.h
cdf75e3d546f69e8d3cf7c32b705a40ce2552a22
diff --git a/include/asm-powerpc/hydra.h b/include/asm-powerpc/hydra.h
new file mode 100644
index 0000000..61c8abb
--- /dev/null
+++ b/include/asm-powerpc/hydra.h
@@ -0,0 +1,102 @@
+#ifndef _ASM_POWERCP_HYDRA_H
+#define _ASM_POWERCP_HYDRA_H
+
+/*
+ * include/asm-ppc/hydra.h -- Mac I/O `Hydra' definitions
+ *
+ * Copyright (C) 1997 Geert Uytterhoeven
+ *
+ * This file is based on the following documentation:
+ *
+ * Macintosh Technology in the Common Hardware Reference Platform
+ * Apple Computer, Inc.
+ *
+ * © Copyright 1995 Apple Computer, Inc. All rights reserved.
+ *
+ * It's available online from http://chrp.apple.com/MacTech.pdf.
+ * You can obtain paper copies of this book from computer bookstores or by
+ * writing Morgan Kaufmann Publishers, Inc., 340 Pine Street, Sixth Floor, San
+ * Francisco, CA 94104. Reference ISBN 1-55860-393-X.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file COPYING in the main directory of this archive
+ * for more details.
+ */
+
+#ifdef __KERNEL__
+
+struct Hydra {
+ /* DBDMA Controller Register Space */
+ char Pad1[0x30];
+ u_int CachePD;
+ u_int IDs;
+ u_int Feature_Control;
+ char Pad2[0x7fc4];
+ /* DBDMA Channel Register Space */
+ char SCSI_DMA[0x100];
+ char Pad3[0x300];
+ char SCCA_Tx_DMA[0x100];
+ char SCCA_Rx_DMA[0x100];
+ char SCCB_Tx_DMA[0x100];
+ char SCCB_Rx_DMA[0x100];
+ char Pad4[0x7800];
+ /* Device Register Space */
+ char SCSI[0x1000];
+ char ADB[0x1000];
+ char SCC_Legacy[0x1000];
+ char SCC[0x1000];
+ char Pad9[0x2000];
+ char VIA[0x2000];
+ char Pad10[0x28000];
+ char OpenPIC[0x40000];
+};
+
+extern volatile struct Hydra __iomem *Hydra;
+
+
+ /*
+ * Feature Control Register
+ */
+
+#define HYDRA_FC_SCC_CELL_EN 0x00000001 /* Enable SCC Clock */
+#define HYDRA_FC_SCSI_CELL_EN 0x00000002 /* Enable SCSI Clock */
+#define HYDRA_FC_SCCA_ENABLE 0x00000004 /* Enable SCC A Lines */
+#define HYDRA_FC_SCCB_ENABLE 0x00000008 /* Enable SCC B Lines */
+#define HYDRA_FC_ARB_BYPASS 0x00000010 /* Bypass Internal Arbiter */
+#define HYDRA_FC_RESET_SCC 0x00000020 /* Reset SCC */
+#define HYDRA_FC_MPIC_ENABLE 0x00000040 /* Enable OpenPIC */
+#define HYDRA_FC_SLOW_SCC_PCLK 0x00000080 /* 1=15.6672, 0=25 MHz */
+#define HYDRA_FC_MPIC_IS_MASTER 0x00000100 /* OpenPIC Master Mode */
+
+
+ /*
+ * OpenPIC Interrupt Sources
+ */
+
+#define HYDRA_INT_SIO 0
+#define HYDRA_INT_SCSI_DMA 1
+#define HYDRA_INT_SCCA_TX_DMA 2
+#define HYDRA_INT_SCCA_RX_DMA 3
+#define HYDRA_INT_SCCB_TX_DMA 4
+#define HYDRA_INT_SCCB_RX_DMA 5
+#define HYDRA_INT_SCSI 6
+#define HYDRA_INT_SCCA 7
+#define HYDRA_INT_SCCB 8
+#define HYDRA_INT_VIA 9
+#define HYDRA_INT_ADB 10
+#define HYDRA_INT_ADB_NMI 11
+#define HYDRA_INT_EXT1 12 /* PCI IRQW */
+#define HYDRA_INT_EXT2 13 /* PCI IRQX */
+#define HYDRA_INT_EXT3 14 /* PCI IRQY */
+#define HYDRA_INT_EXT4 15 /* PCI IRQZ */
+#define HYDRA_INT_EXT5 16 /* IDE Primay/Secondary */
+#define HYDRA_INT_EXT6 17 /* IDE Secondary */
+#define HYDRA_INT_EXT7 18 /* Power Off Request */
+#define HYDRA_INT_SPARE 19
+
+extern int hydra_init(void);
+extern void macio_adb_init(void);
+
+#endif /* __KERNEL__ */
+
+#endif /* _ASM_POWERCP_HYDRA_H */
diff --git a/include/asm-ppc/hydra.h b/include/asm-ppc/hydra.h
deleted file mode 100644
index 833a8af..0000000
--- a/include/asm-ppc/hydra.h
+++ /dev/null
@@ -1,102 +0,0 @@
-/*
- * include/asm-ppc/hydra.h -- Mac I/O `Hydra' definitions
- *
- * Copyright (C) 1997 Geert Uytterhoeven
- *
- * This file is based on the following documentation:
- *
- * Macintosh Technology in the Common Hardware Reference Platform
- * Apple Computer, Inc.
- *
- * © Copyright 1995 Apple Computer, Inc. All rights reserved.
- *
- * It's available online from http://chrp.apple.com/MacTech.pdf.
- * You can obtain paper copies of this book from computer bookstores or by
- * writing Morgan Kaufmann Publishers, Inc., 340 Pine Street, Sixth Floor, San
- * Francisco, CA 94104. Reference ISBN 1-55860-393-X.
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file COPYING in the main directory of this archive
- * for more details.
- */
-
-#ifndef _ASMPPC_HYDRA_H
-#define _ASMPPC_HYDRA_H
-
-#ifdef __KERNEL__
-
-struct Hydra {
- /* DBDMA Controller Register Space */
- char Pad1[0x30];
- u_int CachePD;
- u_int IDs;
- u_int Feature_Control;
- char Pad2[0x7fc4];
- /* DBDMA Channel Register Space */
- char SCSI_DMA[0x100];
- char Pad3[0x300];
- char SCCA_Tx_DMA[0x100];
- char SCCA_Rx_DMA[0x100];
- char SCCB_Tx_DMA[0x100];
- char SCCB_Rx_DMA[0x100];
- char Pad4[0x7800];
- /* Device Register Space */
- char SCSI[0x1000];
- char ADB[0x1000];
- char SCC_Legacy[0x1000];
- char SCC[0x1000];
- char Pad9[0x2000];
- char VIA[0x2000];
- char Pad10[0x28000];
- char OpenPIC[0x40000];
-};
-
-extern volatile struct Hydra __iomem *Hydra;
-
-
- /*
- * Feature Control Register
- */
-
-#define HYDRA_FC_SCC_CELL_EN 0x00000001 /* Enable SCC Clock */
-#define HYDRA_FC_SCSI_CELL_EN 0x00000002 /* Enable SCSI Clock */
-#define HYDRA_FC_SCCA_ENABLE 0x00000004 /* Enable SCC A Lines */
-#define HYDRA_FC_SCCB_ENABLE 0x00000008 /* Enable SCC B Lines */
-#define HYDRA_FC_ARB_BYPASS 0x00000010 /* Bypass Internal Arbiter */
-#define HYDRA_FC_RESET_SCC 0x00000020 /* Reset SCC */
-#define HYDRA_FC_MPIC_ENABLE 0x00000040 /* Enable OpenPIC */
-#define HYDRA_FC_SLOW_SCC_PCLK 0x00000080 /* 1=15.6672, 0=25 MHz */
-#define HYDRA_FC_MPIC_IS_MASTER 0x00000100 /* OpenPIC Master Mode */
-
-
- /*
- * OpenPIC Interrupt Sources
- */
-
-#define HYDRA_INT_SIO 0
-#define HYDRA_INT_SCSI_DMA 1
-#define HYDRA_INT_SCCA_TX_DMA 2
-#define HYDRA_INT_SCCA_RX_DMA 3
-#define HYDRA_INT_SCCB_TX_DMA 4
-#define HYDRA_INT_SCCB_RX_DMA 5
-#define HYDRA_INT_SCSI 6
-#define HYDRA_INT_SCCA 7
-#define HYDRA_INT_SCCB 8
-#define HYDRA_INT_VIA 9
-#define HYDRA_INT_ADB 10
-#define HYDRA_INT_ADB_NMI 11
-#define HYDRA_INT_EXT1 12 /* PCI IRQW */
-#define HYDRA_INT_EXT2 13 /* PCI IRQX */
-#define HYDRA_INT_EXT3 14 /* PCI IRQY */
-#define HYDRA_INT_EXT4 15 /* PCI IRQZ */
-#define HYDRA_INT_EXT5 16 /* IDE Primay/Secondary */
-#define HYDRA_INT_EXT6 17 /* IDE Secondary */
-#define HYDRA_INT_EXT7 18 /* Power Off Request */
-#define HYDRA_INT_SPARE 19
-
-extern int hydra_init(void);
-extern void macio_adb_init(void);
-
-#endif /* __KERNEL__ */
-
-#endif /* _ASMPPC_HYDRA_H */
--
1.2.4
^ permalink raw reply related
* [PATCH 08/15] powerpc: move asm/open_pic.h
From: sfr @ 2006-04-05 5:10 UTC (permalink / raw)
To: paulus; +Cc: linuxppc-dev, Stephen Rothwell
In-Reply-To: <11442138494042-git-send-email-sfr@canb.auug.org.au>
From: Stephen Rothwell <sfr@canb.auug.org.au>
Since the ARCH=powerpc build depends on this file, move it to
include/asm-powerpc.
Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
---
include/asm-powerpc/open_pic.h | 99 ++++++++++++++++++++++++++++++++++++++++
include/asm-ppc/open_pic.h | 99 ----------------------------------------
2 files changed, 99 insertions(+), 99 deletions(-)
create mode 100644 include/asm-powerpc/open_pic.h
delete mode 100644 include/asm-ppc/open_pic.h
54316678b9e6aad8349f2df50dadd2597b675804
diff --git a/include/asm-powerpc/open_pic.h b/include/asm-powerpc/open_pic.h
new file mode 100644
index 0000000..3f197cf
--- /dev/null
+++ b/include/asm-powerpc/open_pic.h
@@ -0,0 +1,99 @@
+#ifndef _ASM_POWERPC_OPEN_PIC_H
+#define _ASM_POWERPC_OPEN_PIC_H
+
+/*
+ * include/asm-ppc/open_pic.h -- OpenPIC Interrupt Handling
+ *
+ * Copyright (C) 1997 Geert Uytterhoeven
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file COPYING in the main directory of this archive
+ * for more details.
+ *
+ */
+
+#include <linux/irq.h>
+
+#define OPENPIC_SIZE 0x40000
+
+/*
+ * Non-offset'ed vector numbers
+ */
+
+#define OPENPIC_VEC_TIMER 110 /* and up */
+#define OPENPIC_VEC_IPI 118 /* and up */
+#define OPENPIC_VEC_SPURIOUS 255
+
+/* Priorities */
+#define OPENPIC_PRIORITY_IPI_BASE 10
+#define OPENPIC_PRIORITY_DEFAULT 4
+#define OPENPIC_PRIORITY_NMI 9
+
+/* OpenPIC IRQ controller structure */
+extern struct hw_interrupt_type open_pic;
+
+/* OpenPIC IPI controller structure */
+#ifdef CONFIG_SMP
+extern struct hw_interrupt_type open_pic_ipi;
+#endif /* CONFIG_SMP */
+
+extern u_int OpenPIC_NumInitSenses;
+extern u_char *OpenPIC_InitSenses;
+extern void __iomem * OpenPIC_Addr;
+extern int epic_serial_mode;
+
+/* Exported functions */
+extern void openpic_set_sources(int first_irq, int num_irqs, void __iomem *isr);
+extern void openpic_init(int linux_irq_offset);
+extern void openpic_init_nmi_irq(u_int irq);
+extern void openpic_set_irq_priority(u_int irq, u_int pri);
+extern void openpic_hookup_cascade(u_int irq, char *name,
+ int (*cascade_fn)(struct pt_regs *));
+extern u_int openpic_irq(void);
+extern void openpic_eoi(void);
+extern void openpic_request_IPIs(void);
+extern void do_openpic_setup_cpu(void);
+extern int openpic_get_irq(struct pt_regs *regs);
+extern void openpic_reset_processor_phys(u_int cpumask);
+extern void openpic_setup_ISU(int isu_num, unsigned long addr);
+extern void openpic_cause_IPI(u_int ipi, cpumask_t cpumask);
+extern void smp_openpic_message_pass(int target, int msg);
+extern void openpic_set_k2_cascade(int irq);
+extern void openpic_set_priority(u_int pri);
+extern u_int openpic_get_priority(void);
+
+extern inline int openpic_to_irq(int irq)
+{
+ /* IRQ 0 usually means 'disabled'.. don't mess with it
+ * exceptions to this (sandpoint maybe?)
+ * shouldn't use openpic_to_irq
+ */
+ if (irq != 0){
+ return irq += NUM_8259_INTERRUPTS;
+ } else {
+ return 0;
+ }
+}
+/* Support for second openpic on G5 macs */
+
+// FIXME: To be replaced by sane cascaded controller management */
+
+#define PMAC_OPENPIC2_OFFSET 128
+
+#define OPENPIC2_VEC_TIMER 110 /* and up */
+#define OPENPIC2_VEC_IPI 118 /* and up */
+#define OPENPIC2_VEC_SPURIOUS 127
+
+
+extern void* OpenPIC2_Addr;
+
+/* Exported functions */
+extern void openpic2_set_sources(int first_irq, int num_irqs, void *isr);
+extern void openpic2_init(int linux_irq_offset);
+extern void openpic2_init_nmi_irq(u_int irq);
+extern u_int openpic2_irq(void);
+extern void openpic2_eoi(void);
+extern int openpic2_get_irq(struct pt_regs *regs);
+extern void openpic2_setup_ISU(int isu_num, unsigned long addr);
+
+#endif /* _ASM_POWERPC_OPEN_PIC_H */
diff --git a/include/asm-ppc/open_pic.h b/include/asm-ppc/open_pic.h
deleted file mode 100644
index ec2f466..0000000
--- a/include/asm-ppc/open_pic.h
+++ /dev/null
@@ -1,99 +0,0 @@
-/*
- * include/asm-ppc/open_pic.h -- OpenPIC Interrupt Handling
- *
- * Copyright (C) 1997 Geert Uytterhoeven
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file COPYING in the main directory of this archive
- * for more details.
- *
- */
-
-#ifndef _PPC_KERNEL_OPEN_PIC_H
-#define _PPC_KERNEL_OPEN_PIC_H
-
-#include <linux/config.h>
-#include <linux/irq.h>
-
-#define OPENPIC_SIZE 0x40000
-
-/*
- * Non-offset'ed vector numbers
- */
-
-#define OPENPIC_VEC_TIMER 110 /* and up */
-#define OPENPIC_VEC_IPI 118 /* and up */
-#define OPENPIC_VEC_SPURIOUS 255
-
-/* Priorities */
-#define OPENPIC_PRIORITY_IPI_BASE 10
-#define OPENPIC_PRIORITY_DEFAULT 4
-#define OPENPIC_PRIORITY_NMI 9
-
-/* OpenPIC IRQ controller structure */
-extern struct hw_interrupt_type open_pic;
-
-/* OpenPIC IPI controller structure */
-#ifdef CONFIG_SMP
-extern struct hw_interrupt_type open_pic_ipi;
-#endif /* CONFIG_SMP */
-
-extern u_int OpenPIC_NumInitSenses;
-extern u_char *OpenPIC_InitSenses;
-extern void __iomem * OpenPIC_Addr;
-extern int epic_serial_mode;
-
-/* Exported functions */
-extern void openpic_set_sources(int first_irq, int num_irqs, void __iomem *isr);
-extern void openpic_init(int linux_irq_offset);
-extern void openpic_init_nmi_irq(u_int irq);
-extern void openpic_set_irq_priority(u_int irq, u_int pri);
-extern void openpic_hookup_cascade(u_int irq, char *name,
- int (*cascade_fn)(struct pt_regs *));
-extern u_int openpic_irq(void);
-extern void openpic_eoi(void);
-extern void openpic_request_IPIs(void);
-extern void do_openpic_setup_cpu(void);
-extern int openpic_get_irq(struct pt_regs *regs);
-extern void openpic_reset_processor_phys(u_int cpumask);
-extern void openpic_setup_ISU(int isu_num, unsigned long addr);
-extern void openpic_cause_IPI(u_int ipi, cpumask_t cpumask);
-extern void smp_openpic_message_pass(int target, int msg);
-extern void openpic_set_k2_cascade(int irq);
-extern void openpic_set_priority(u_int pri);
-extern u_int openpic_get_priority(void);
-
-extern inline int openpic_to_irq(int irq)
-{
- /* IRQ 0 usually means 'disabled'.. don't mess with it
- * exceptions to this (sandpoint maybe?)
- * shouldn't use openpic_to_irq
- */
- if (irq != 0){
- return irq += NUM_8259_INTERRUPTS;
- } else {
- return 0;
- }
-}
-/* Support for second openpic on G5 macs */
-
-// FIXME: To be replaced by sane cascaded controller management */
-
-#define PMAC_OPENPIC2_OFFSET 128
-
-#define OPENPIC2_VEC_TIMER 110 /* and up */
-#define OPENPIC2_VEC_IPI 118 /* and up */
-#define OPENPIC2_VEC_SPURIOUS 127
-
-
-extern void* OpenPIC2_Addr;
-
-/* Exported functions */
-extern void openpic2_set_sources(int first_irq, int num_irqs, void *isr);
-extern void openpic2_init(int linux_irq_offset);
-extern void openpic2_init_nmi_irq(u_int irq);
-extern u_int openpic2_irq(void);
-extern void openpic2_eoi(void);
-extern int openpic2_get_irq(struct pt_regs *regs);
-extern void openpic2_setup_ISU(int isu_num, unsigned long addr);
-#endif /* _PPC_KERNEL_OPEN_PIC_H */
--
1.2.4
^ permalink raw reply related
* [PATCH 07/15] powerpc: move asm/amigappc.h
From: sfr @ 2006-04-05 5:10 UTC (permalink / raw)
To: paulus; +Cc: linuxppc-dev, Stephen Rothwell
In-Reply-To: <11442138494042-git-send-email-sfr@canb.auug.org.au>
From: Stephen Rothwell <sfr@canb.auug.org.au>
Since the ARCH=powerpc build depends on this file, move it to
include/asm-powerpc.
Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
---
include/asm-powerpc/amigappc.h | 84 ++++++++++++++++++++++++++++++++++++++++
include/asm-ppc/amigappc.h | 85 ----------------------------------------
2 files changed, 84 insertions(+), 85 deletions(-)
create mode 100644 include/asm-powerpc/amigappc.h
delete mode 100644 include/asm-ppc/amigappc.h
a53c21d9d235cc02ab34d696d1440a1ceda1e3d7
diff --git a/include/asm-powerpc/amigappc.h b/include/asm-powerpc/amigappc.h
new file mode 100644
index 0000000..e7f9c33
--- /dev/null
+++ b/include/asm-powerpc/amigappc.h
@@ -0,0 +1,84 @@
+#ifndef _ASM_POWERPC_AMIGAPPC_H
+#define _ASM_POWERPC_AMIGAPPC_H
+/*
+** This header defines some values and pointers for the Phase 5 PowerUp card.
+**
+** Copyright 1997, 1998 by Phase5, Germany.
+**
+** This file is subject to the terms and conditions of the GNU General Public
+** License. See the file COPYING in the main directory of this archive
+** for more details.
+**
+** Created: 7/22/97 by Jesper Skov
+*/
+
+#ifdef __KERNEL__
+
+#ifndef __ASSEMBLY__
+
+/* #include <asm/system.h> */
+#define mb() __asm__ __volatile__ ("sync" : : : "memory")
+
+#define APUS_WRITE(_a_, _v_) \
+do { \
+ (*((volatile unsigned char *)(_a_)) = (_v_)); \
+ mb(); \
+} while (0)
+
+#define APUS_READ(_a_, _v_) \
+do { \
+ (_v_) = (*((volatile unsigned char *)(_a_))); \
+ mb(); \
+} while (0)
+#endif /* ndef __ASSEMBLY__ */
+
+/* Maybe add a [#ifdef WANT_ZTWOBASE] condition to amigahw.h? */
+#define zTwoBase (0x80000000)
+
+#define APUS_IPL_BASE (zTwoBase + 0x00f60000)
+#define APUS_REG_RESET (APUS_IPL_BASE + 0x00)
+#define APUS_REG_WAITSTATE (APUS_IPL_BASE + 0x10)
+#define APUS_REG_SHADOW (APUS_IPL_BASE + 0x18)
+#define APUS_REG_LOCK (APUS_IPL_BASE + 0x20)
+#define APUS_REG_INT (APUS_IPL_BASE + 0x28)
+#define APUS_IPL_EMU (APUS_IPL_BASE + 0x30)
+#define APUS_INT_LVL (APUS_IPL_BASE + 0x38)
+
+#define REGSHADOW_SETRESET (0x80)
+#define REGSHADOW_SELFRESET (0x40)
+
+#define REGLOCK_SETRESET (0x80)
+#define REGLOCK_BLACKMAGICK1 (0x40)
+#define REGLOCK_BLACKMAGICK2 (0x20)
+#define REGLOCK_BLACKMAGICK3 (0x10)
+
+#define REGWAITSTATE_SETRESET (0x80)
+#define REGWAITSTATE_PPCW (0x08)
+#define REGWAITSTATE_PPCR (0x04)
+
+#define REGRESET_SETRESET (0x80)
+#define REGRESET_PPCRESET (0x10)
+#define REGRESET_M68KRESET (0x08)
+#define REGRESET_AMIGARESET (0x04)
+#define REGRESET_AUXRESET (0x02)
+#define REGRESET_SCSIRESET (0x01)
+
+#define REGINT_SETRESET (0x80)
+#define REGINT_ENABLEIPL (0x02)
+#define REGINT_INTMASTER (0x01)
+
+#define IPLEMU_SETRESET (0x80)
+#define IPLEMU_DISABLEINT (0x40)
+#define IPLEMU_IPL2 (0x20)
+#define IPLEMU_IPL1 (0x10)
+#define IPLEMU_IPL0 (0x08)
+#define IPLEMU_PPCIPL2 (0x04)
+#define IPLEMU_PPCIPL1 (0x02)
+#define IPLEMU_PPCIPL0 (0x01)
+#define IPLEMU_IPLMASK (IPLEMU_PPCIPL2|IPLEMU_PPCIPL1|IPLEMU_PPCIPL0)
+
+#define INTLVL_SETRESET (0x80)
+#define INTLVL_MASK (0x7f)
+
+#endif /* __KERNEL__ */
+#endif /* _ASM_POWERPC_AMIGAPPC_H */
diff --git a/include/asm-ppc/amigappc.h b/include/asm-ppc/amigappc.h
deleted file mode 100644
index 35114ce..0000000
--- a/include/asm-ppc/amigappc.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
-** asm-ppc/amigappc.h -- This header defines some values and pointers for
-** the Phase 5 PowerUp card.
-**
-** Copyright 1997, 1998 by Phase5, Germany.
-**
-** This file is subject to the terms and conditions of the GNU General Public
-** License. See the file COPYING in the main directory of this archive
-** for more details.
-**
-** Created: 7/22/97 by Jesper Skov
-*/
-
-#ifdef __KERNEL__
-#ifndef _M68K_AMIGAPPC_H
-#define _M68K_AMIGAPPC_H
-
-#ifndef __ASSEMBLY__
-
-/* #include <asm/system.h> */
-#define mb() __asm__ __volatile__ ("sync" : : : "memory")
-
-#define APUS_WRITE(_a_, _v_) \
-do { \
- (*((volatile unsigned char *)(_a_)) = (_v_)); \
- mb(); \
-} while (0)
-
-#define APUS_READ(_a_, _v_) \
-do { \
- (_v_) = (*((volatile unsigned char *)(_a_))); \
- mb(); \
-} while (0)
-#endif /* ndef __ASSEMBLY__ */
-
-/* Maybe add a [#ifdef WANT_ZTWOBASE] condition to amigahw.h? */
-#define zTwoBase (0x80000000)
-
-#define APUS_IPL_BASE (zTwoBase + 0x00f60000)
-#define APUS_REG_RESET (APUS_IPL_BASE + 0x00)
-#define APUS_REG_WAITSTATE (APUS_IPL_BASE + 0x10)
-#define APUS_REG_SHADOW (APUS_IPL_BASE + 0x18)
-#define APUS_REG_LOCK (APUS_IPL_BASE + 0x20)
-#define APUS_REG_INT (APUS_IPL_BASE + 0x28)
-#define APUS_IPL_EMU (APUS_IPL_BASE + 0x30)
-#define APUS_INT_LVL (APUS_IPL_BASE + 0x38)
-
-#define REGSHADOW_SETRESET (0x80)
-#define REGSHADOW_SELFRESET (0x40)
-
-#define REGLOCK_SETRESET (0x80)
-#define REGLOCK_BLACKMAGICK1 (0x40)
-#define REGLOCK_BLACKMAGICK2 (0x20)
-#define REGLOCK_BLACKMAGICK3 (0x10)
-
-#define REGWAITSTATE_SETRESET (0x80)
-#define REGWAITSTATE_PPCW (0x08)
-#define REGWAITSTATE_PPCR (0x04)
-
-#define REGRESET_SETRESET (0x80)
-#define REGRESET_PPCRESET (0x10)
-#define REGRESET_M68KRESET (0x08)
-#define REGRESET_AMIGARESET (0x04)
-#define REGRESET_AUXRESET (0x02)
-#define REGRESET_SCSIRESET (0x01)
-
-#define REGINT_SETRESET (0x80)
-#define REGINT_ENABLEIPL (0x02)
-#define REGINT_INTMASTER (0x01)
-
-#define IPLEMU_SETRESET (0x80)
-#define IPLEMU_DISABLEINT (0x40)
-#define IPLEMU_IPL2 (0x20)
-#define IPLEMU_IPL1 (0x10)
-#define IPLEMU_IPL0 (0x08)
-#define IPLEMU_PPCIPL2 (0x04)
-#define IPLEMU_PPCIPL1 (0x02)
-#define IPLEMU_PPCIPL0 (0x01)
-#define IPLEMU_IPLMASK (IPLEMU_PPCIPL2|IPLEMU_PPCIPL1|IPLEMU_PPCIPL0)
-
-#define INTLVL_SETRESET (0x80)
-#define INTLVL_MASK (0x7f)
-
-#endif /* _M68k_AMIGAPPC_H */
-#endif /* __KERNEL__ */
--
1.2.4
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