* Re: Alubook 5,8: No sound with 2.6.17-rc3-g5528e568-dirty
From: Johannes Berg @ 2006-05-11 11:58 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev list
In-Reply-To: <1147304824.32448.82.camel@localhost.localdomain>
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On Thu, 2006-05-11 at 09:47 +1000, Benjamin Herrenschmidt wrote:
> Same as mine, it works fine with snd-aoa
I should build a database with a machine string -> user* mapping... This
means that even my brother has this one and it works great with snd-aoa
as far as I know :)
Though, since the alsa userspace libs absolutely *SUCK* no program I
know of can properly represent the mixer controls except maybe amixer...
I'd hate to work around this in the kernel, but the alsa libs are such
complex beasts that I have a feeling they won't be fixed.
Anyone up to inventing a new mixer API that uses sysfs? ;)
johannes
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^ permalink raw reply
* Re: Alubook 5,8: No sound with 2.6.17-rc3-g5528e568-dirty
From: Benjamin Herrenschmidt @ 2006-05-11 12:04 UTC (permalink / raw)
To: Johannes Berg; +Cc: linuxppc-dev list
In-Reply-To: <1147348702.9630.7.camel@johannes>
On Thu, 2006-05-11 at 13:58 +0200, Johannes Berg wrote:
> On Thu, 2006-05-11 at 09:47 +1000, Benjamin Herrenschmidt wrote:
>
> > Same as mine, it works fine with snd-aoa
>
> I should build a database with a machine string -> user* mapping... This
> means that even my brother has this one and it works great with snd-aoa
> as far as I know :)
>
> Though, since the alsa userspace libs absolutely *SUCK* no program I
> know of can properly represent the mixer controls except maybe amixer...
> I'd hate to work around this in the kernel, but the alsa libs are such
> complex beasts that I have a feeling they won't be fixed.
kmix looks approx. ok
> Anyone up to inventing a new mixer API that uses sysfs? ;)
>
> johannes
^ permalink raw reply
* Help: Linux porting to custom target hw
From: Thiago Galesi @ 2006-05-11 12:02 UTC (permalink / raw)
To: Jayanta Das; +Cc: linuxppc-embedded
In-Reply-To: <8584FDC94AFF7640B17B8A89B23B19B331C626@sbsserver.AlphionCorp.local>
Ok
What is the specific problem you are having?? Based on what you said
all went well, didn't it?
Basically, I think the main thing you have to configure there is flash
location (in the kernel), to be able to use it via MTD.
Booting from NFS or Flash is pretty much effortless, configurable via cmdli=
ne.
Be more specific, so we can help you more...
Thiago
On 5/10/06, Jayanta Das <JDas@alphion.com> wrote:
>
>
> Hello:
>
> Can someone point me in the right direction for some good documentation o=
n
> the above topic. Following is what I so far have done and what I need to =
do.
>
> 1. Set up host environment based on Fedora Core 4
> 2. Downloaded 'ppc4xx' tool chain, ELDK and kernel
> 3. Built U-Boot and uImage
> 4. Flashed U-Boot on the 2nd flash on the Ocotea board (AMCC440GX PowerPC=
)
> 5. Changed the environment variable for NFS mounted root fs and other MAC
> and IP addresses as needed
> 6. TFTP uImage at 400000
> 7. bootm and kernel boots all right with root fs mounted on the host
>
> I am expecting my hardware based on 440GX end of the month. I told the HW
> engineer to follow the peripheral i/f as much possible close to the ref.
> design. We are putting 32MB of Flash and 256MB of RAM.
>
> I need some guidance so that I can port U-Boot and the kernel (minimal
> changes) so that I can bring up the board initially with root fs NFS mint=
ed
> and later on the RAMDISK.
>
> Appreciate the help.
>
> Regards.
> _______________________________________________
> Linuxppc-embedded mailing list
> Linuxppc-embedded@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-embedded
>
>
^ permalink raw reply
* RE: Help Needed: input overrun(s)
From: s.maiti @ 2006-05-11 12:56 UTC (permalink / raw)
To: Rune Torgersen; +Cc: linuxppc-embedded
In-Reply-To: <DCEAAC0833DD314AB0B58112AD99B93B0189DD9F@ismail.innsys.innovsys.com>
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Thanks very much for your reply. It's seems you have already developed the
MCC driver. Are you using channels 32 to 96? Have you made any changes in
the dp ram allocation for uart or ethernet driver?
Please help me...
Thanks and regards,
Souvik Maiti
Tata Consultancy Services Limited
Mailto: s.maiti@tcs.com
Website: http://www.tcs.com
"Rune Torgersen" <runet@innovsys.com>
05/10/2006 08:45 PM
To
"Stevan Ignjatovic" <stevan@iritel.com>, <s.maiti@tcs.com>
cc
<linuxppc-embedded@ozlabs.org>
Subject
RE: Help Needed: input overrun(s)
> -----Original Message-----
> From: Stevan Ignjatovic
> Hello,
>
> > console we are receiving a print "ttyS: 1 input overrun(s)"
> along with
> > other prints of the driver and resulting in scrambled output.
> > Can anyone suggest why this is happening? Is the driver
> affecting the uart
> > driver?
>
> As far as UART driver is concerned, it could be affected if
> you did not
> carefully allocate some resources. Are you using MCC1 or MCC2? Channel
> specific parameters of MCC1 (channels 0-127) are at the
> beginning of the
> DPRAM (channel CH_NUM at address 64*CH_NUM). UART driver (as well as
> ethernet driver) allocates its buffer descriptors with
> m8260_cpm_dpalloc. I think that allocating with this function
> starts at
> the beginning of the DPRAM, so you might have overwritten
> UART's buffer
> descriptors. So, use MCC2 if you can. If you use some BRGs in your MCC
> driver you should check that as well.
We have a MCC driver that we see the same happening on. It only occurs
under heavy load (top sows us usig 20-40 % cpu in interrupt).
I am pretty confident that we are not overwriting uart DPRAM. (MCC1 only
uses the middle 64 channels, skipping over the first 32 where the
conflict witht he UARTS are)
I have not seen it corrupt anything, so we have more or less ignored it.
Our theory is that it happens when the CPM gets overloaded.
It would be nice to actually fix it though....
ForwardSourceID:NT00006D1A
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^ permalink raw reply
* MPC8641(D) software status
From: Sam Song @ 2006-05-11 13:53 UTC (permalink / raw)
To: linuxppc-embedded
Dear all,
Could anyone kindly disclose any info on
its boot code and kernel support?
Mass production is under way if I am not
wrong but less info on software. Just out of
interest to know that... Maybe I could have
the luck to touch it.
Thanks in advance,
Sam
___________________________________________________________
雅虎免费邮箱-3.5G容量，20M附件
http://cn.mail.yahoo.com/
^ permalink raw reply
* Re: MPC8641(D) software status
From: Xianghua Xiao @ 2006-05-11 14:08 UTC (permalink / raw)
To: Sam Song; +Cc: linuxppc-embedded
In-Reply-To: <20060511135328.25523.qmail@web15706.mail.cnb.yahoo.com>
Sam,
We have patches for 8641D against 2.6.15/2.6.16 and it works well in lab
in the last three months along with u-boot code. I think a patch against
2.6.17 or later will be released in the future. However if you need the
2.6.15/2.6.16 patch now, you can contact Freescale directly. In fact,
for all 8641D boards we will ship, we will include the kernel/u-boot
source code on the SATA hard drive directly as well, or you can also
download them from freescale's website.
Hope this helps,
Xianghua
Sam Song wrote:
>Dear all,
>
>Could anyone kindly disclose any info on
>its boot code and kernel support?
>
>Mass production is under way if I am not
>wrong but less info on software. Just out of
>interest to know that... Maybe I could have
>the luck to touch it.
>
>Thanks in advance,
>
>Sam
>
>
>
>
>
>
>___________________________________________________________
>雅虎免费邮箱-3.5G容量，20M附件
>http://cn.mail.yahoo.com/
>_______________________________________________
>Linuxppc-embedded mailing list
>Linuxppc-embedded@ozlabs.org
>https://ozlabs.org/mailman/listinfo/linuxppc-embedded
>
^ permalink raw reply
* RE: Help Needed: input overrun(s)
From: Rune Torgersen @ 2006-05-11 14:14 UTC (permalink / raw)
To: s.maiti; +Cc: linuxppc-embedded
> From: s.maiti@tcs.com [mailto:s.maiti@tcs.com]=20
> Thanks very much for your reply. It's seems you have already=20
> developed the MCC driver. Are you using channels 32 to 96?=20
> Have you made any changes in the dp ram allocation for uart=20
> or ethernet driver?=20
> Please help me...=20
We are using every other channel from 32 to 96 on both MCC's as SS7
receivers.
We did not have to do any relocations for UART or ethernet.=20
Ethernet uses upper DPRAM (above 0x8000) and uarts use the first 128
bytes.
We statically allocate DPRAM with cpm_alloc_fixed. MCC1 use 0x0800 to
0x17ff
MCC2 use 0x2800 to 0x37ff. Extra param RAM is allocated with cpm_alloc
and is allocated as 256*8 bytes, and shared between MCC1 and 2.
All BD and interrupt tables are in main memory.
^ permalink raw reply
* Tests to enable Dcache on MPC8270ZUQLDA PPC board restart the system
From: Om Vadlapatla @ 2006-05-11 16:32 UTC (permalink / raw)
To: linuxppc-embedded@ozlabs.org, U-Boot-Users@lists.sourceforge.net
[-- Attachment #1: Type: text/plain, Size: 6402 bytes --]
Hello,
Processor: MPC8270
Debugger: Abatron BDI 2000
Board & processor Initialization by: Uboot 1.1.2
Aim:
I try to enable d-cache at the Register level with out
having any exceptions. I want to write my own code to
compile into the kernel that is no longer supported by
Montavista (3.0).
Proceedure:
~in window 1 (DIP window) I reset the processor then
the flash mem loads the U-boot version 1.1.2. I do not
load the OS so the system is running at the U-boot
prompt.
=>
~In window 2 (BDI debugger window) I use the Abarton
BDI to force the PPC to enter debug mode by issuing -
"halt" instruction.
MPC8270>halt
Target CPU : MPC8280/MGT5200 (Zeppo)
Target state : debug mode
Debug entry cause : COP halt
Current PC : 0x0ffe935c
Current CR : 0x44004044
Current MSR : 0x0000b002
Current LR : 0x0ffe13a8
~now by issueing commands from the BDI I try to set
the BATs and the MMU as follows:
I tried two BAT schemes on the abatron that are
attached in BAT register setting table.do &
8280_InitMMU.cmm :
Test 1:-
For seting DBAT regs by BDI commands ccording to
(BAT_register_setting_table.doc):
// initialize bats
MPC8270>rm dbat0u 0xffe0003f
MPC8270>rm dbat0l 0xffe00022
MPC8270>rm dbat1u 0x00001fff
MPC8270>rm dbat1l 0x00000002
MPC8270>rm dbat2u 0x300007ff
MPC8270>rm dbat2l 0x30000002
MPC8270>rm dbat3u 0x400003FF
MPC8270>rm dbat3l 0x40000022
MPC8270>rm dbat4u 0xFB0001FF
MPC8270>rm dbat4l 0xFB000022
MPC8270>rm dbat5u 0xFE400003
MPC8270>rm dbat5l 0xFE400022
MPC8270>rm dbat6u 0xF0000003
MPC8270>rm dbat6l 0xF0000022
MPC8270>rm dbat7u 0xFF000003
MPC8270>rm dbat7l 0xFF000022
MPC8270>rm hid0 0x8000c088 // set HID0 to enable
// I & D Cache
MPC8270>go // to let the processor run
I check the PC and it is at 0x200 the Machine check
exception.
Test 2:-
commands I issued throught Abatron BDI window:
// initialization of BATs reffre to (8280_InitMMU.cmm)
// please keep in mind that even though these BAT
// initialization are for a Stand alone systems I only
// plan to test if I am able to initialize the data
// cache without the 0x200 (Machine check exception)
// exception.
MPC8270>rm ibat0u 0x000003fe
MPC8270>rm ibat0l 0x00000002
MPC8270>rm ibat1u 0x04700002
MPC8270>rm ibat1l 0x04700022
MPC8270>rm ibat3u 0xff0000fe
MPC8270>rm ibat3l 0xff000001
MPC8270>rm dbat0u 0x000007fe
MPC8270>rm dbat0l 0x00000002
MPC8270>rm dbat1u 0x0400007e
MPC8270>rm dbat1l 0x0400002a
MPC8270>rm dbat2u 0x0450007e
MPC8270>rm dbat2l 0x0450002a
MPC8270>rm dbat3u 0xff0000fe
MPC8270>rm dbat3l 0xff000022
// the Bats initialize fine no problem till here
MPC8270>rm msr 0x9030 // enable MMU (EE + ME + DR +
IR)
// I feel I may be messing it up here (can some one
// correct me?)
MPC8270>go // this is to let the processor run
// however ends up restarting the system
// I dont issue the foll command coz of reset
MPC8270>rm hid0 0x8000c088 // this is to set and
// enable the I & D Caches
This is how the DIP window where the boot prompt is
looks after this test 2:-
-------------------------------------------------------
U-Boot 1.1.2 (Jan 27 2006 - 14:27:57) ### Release
1.1.5 ###
MPC8260 Reset Status: Bus Monitor, External Soft,
External Hard
MPC8260 Clock Configuration
- Bus-to-Core Mult 4x, VCO Div 2, 60x Bus Freq 25-75
, Core Freq 100-300
- dfbrg 1, corecnf 0x1a, busdf 5, cpmdf 1, plldf 0,
pllmf 5
- vco_out 400000002, scc_clk 100000000, brg_clk
25000000
- cpu_clk 266666668, cpm_clk 200000001, bus_clk
66666667
CPU: MPC8260 (HiP7 Rev 14, Mask 1.0 1K49M) at
266.666 MHz
Board: Fujitsu FW4060
I2C: ready
DRAM: 256 MB
FLASH: 2 MB
In: serial
Out: serial
Err: serial
Net: FCC2 ETHERNET
IDE: Bus 0: OK
Device 0: Model: Hitachi XXM2.3.0 Firm: Rev 3.00
Ser#: X0405 20050304185152
Type: Removable Hard Disk
Capacity: 61.1 MB = 0.0 GB (125184 x 512)
Hit any key to stop autoboot: 0
=>Bad trap at PC: fffffffc, SR: 1000, vector=800
NIP: FFFFFFFC XER: 20000000 LR: 00001088 REGS:
0ffa7dc0 TRAP: 0800 DAR: 0FFE55FC
MSR: 00001000 EE: 0 PR: 0 FP: 0 ME: 1 IR/DR: 00
GPR00: 0000A000 0FFA7EB0 00000004 00000000 0FFF0E80
0000000A FFFFFFFD FFFFFFFF
GPR08: 0FFA7C18 F0000080 00008000 F0000090 00000000
0403FF80 0FFF6000 101C8000
GPR16: 00000000 00000000 00000000 0100FFE0 00000000
00000001 00000000 00000000
GPR24: 00000000 FFFFFFFF 00000001 00000003 0FFFEFC8
0FFA7F64 0FFF74AC 0FFF0E80
Call backtrace:
Exception in kernel pc fffffffc signal 0
U-Boÿ
U-Boot 1.1.2 (Jan 27 2006 - 14:27:57) ### Release
1.1.5 ###
MPC8260 Reset Status: External Soft, External Hard
MPC8260 Clock Configuration
- Bus-to-Core Mult 4x, VCO Div 2, 60x Bus Freq 25-75
, Core Freq 100-300
- dfbrg 1, corecnf 0x1a, busdf 5, cpmdf 1, plldf 0,
pllmf 5
- vco_out 400000002, scc_clk 100000000, brg_clk
25000000
- cpu_clk 266666668, cpm_clk 200000001, bus_clk
66666667
CPU: MPC8260 (HiP7 Rev 14, Mask 1.0 1K49M) at
266.666 MHz
Board: Fujitsu FW4060
I2C: ready
DRAM: 256 MB
FLASH: 2 MB
In: serial
Out: serial
Err: serial
Net: FCC2 ETHERNET
IDE: Bus 0: OK
Device 0: Model: Hitachi XXM2.3.0 Firm: Rev 3.00
Ser#: X0405 20050304185152
Type: Removable Hard Disk
Capacity: 61.1 MB = 0.0 GB (125184 x 512)
Hit any key to stop autoboot: 0
=> Bad trap at PC: fffffffc, SR: 1000, vector=800
NIP: FFFFFFFC XER: 00000000 LR: 00001088 REGS:
0ffa7dc0 TRAP: 0800 DAR: 0FFE55FC
MSR: 00001000 EE: 0 PR: 0 FP: 0 ME: 1 IR/DR: 00
GPR00: 0000A000 0FFA7EB0 00000004 00000000 0FFF0E80
0000000A FFFFFFFD 00000000
GPR08: 00000002 F0000080 00008000 F0000090 00000000
0403FF80 0FFF6000 101C8000
GPR16: 00000000 00000000 00000000 0100FFE0 00003002
00000001 00000000 0FFCB098
GPR24: 0FFCE410 00000001 00000001 00000003 0FFFEFC8
0FFA7F64 0FFF74AC 0FFF0E80
Call backtrace:
Exception in kernel pc fffffffc signal 0
-------------------------------------------------------
Have I wrongly inilialized the MSR?
Please post comments and suggestions of how I can
initialized MMU for d-cache performance. I am very new
to this.
Thanky you,
Best regards,
Om Vadlapatla
__________________________________________________
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[-- Attachment #2: 790078158-8280_InitMMU.cmm --]
[-- Type: application/octet-stream, Size: 1775 bytes --]
; ********************************
; Initialize BATs
; ********************************
INIT_MMU:
; *** Invalidate TLBs
d.a 0x10000 addi r2,0,32
d.a 0x10004 mtctr r2 ; Load CTR with 32.
d.a 0x10008 addi r3,0,0 ; Use r3 as the tlb index
d.a 0x1000C tlbie r3 ; invalidate the tlb entry
d.a 0x10010 sync
d.a 0x10014 addi r3,r3,0x1000 ; increment the index
d.a 0x10018 bdnz 0x1000C
d.a 0x1001C b 0x1001C
r.s IP 0x10000
go
wait 1ms
break
; *** Clear all Upper BATs
d.s SPR:0x218 %l 0 ; DBAT0U
d.s SPR:0x21A %l 0 ; DBAT1U
d.s SPR:0x21C %l 0 ; DBAT2U
d.s SPR:0x21E %l 0 ; DBAT3U
d.s SPR:0x238 %l 0 ; DBAT4U
d.s SPR:0x23A %l 0 ; DBAT5U
d.s SPR:0x23C %l 0 ; DBAT6U
d.s SPR:0x23E %l 0 ; DBAT7U
d.s SPR:0x210 %l 0 ; IBAT0U
d.s SPR:0x212 %l 0 ; IBAT1U
d.s SPR:0x214 %l 0 ; IBAT2U
d.s SPR:0x216 %l 0 ; IBAT3U
d.s SPR:0x230 %l 0 ; IBAT4U
d.s SPR:0x232 %l 0 ; IBAT5U
d.s SPR:0x234 %l 0 ; IBAT6U
d.s SPR:0x236 %l 0 ; IBAT7U
; 60-x SDRAM IBAT
d.s SPR:0x210 %l 0x000003FE ; IBAT0U 32MB
d.s SPR:0x211 %l 0x00000002 ; IBAT0L R/W
; IMMR IBAT
d.s SPR:0x212 %l 0x04700002 ; IBAT1U 128KB
d.s SPR:0x213 %l 0x04700022 ; IBAT0L I R/W
; Flash IBAT
d.s SPR:0x216 %l 0xFF0000FE ; IBAT3U 8MB
d.s SPR:0x217 %l 0xFF000001 ; IBAT3L R/O
; 60-x SDRAM DBAT
d.s SPR:0x218 %l 0x000007FE ; DBAT0U 16MB
d.s SPR:0x219 %l 0x00000002 ; DBAT0L R/W
; Local SDRAM DBAT
d.s SPR:0x21A %l 0x0400007E ; DBAT1U
d.s SPR:0x21B %l 0x0400002A ; DBAT1L I,G R/W
; BCSR DBAT
d.s SPR:0x21C %l 0x0450007E ; DBAT2U BCSR + IMMR space
d.s SPR:0x21D %l 0x0450002A ; DBAT2L I,G R/W
; Flash DBAT
d.s SPR:0x21E %l 0xFF0000FE ; DBAT3U 8MB
d.s SPR:0x21F %l 0xFF000022 ; DBAT3L I R/W
; Enable MMU
;r.s MSR 0x9030 ; EE + ME + DR + IR
[-- Attachment #3: 1927371312-BAT register setting table.doc --]
[-- Type: application/msword, Size: 28672 bytes --]
^ permalink raw reply
* [PATCH 1/2] Support AMCC Taihu 405EP Eval Board
From: John Otken @ 2006-05-11 18:25 UTC (permalink / raw)
To: linuxppc-embedded
This patch adds support for the AMCC Taihu 405EP
evaluation board.
I tested it against the latest Denx git tree
(2.6.17-rc3).
The defconfig file follows.
Comments are welcome.
Signed-off-by: John Otken <jotken@softadvances.com>
arch/ppc/platforms/4xx/Kconfig | 15
arch/ppc/platforms/4xx/Makefile | 1
arch/ppc/platforms/4xx/taihu.c | 260 +++++
arch/ppc/platforms/4xx/taihu.h | 105 ++
drivers/mtd/maps/Kconfig | 8
drivers/mtd/maps/Makefile | 1
drivers/mtd/maps/taihu.c | 155 +++
drivers/usb/gadget/Kconfig | 11
drivers/usb/gadget/Makefile | 1
drivers/usb/gadget/epautoconf.c | 15
drivers/usb/gadget/gadget_chips.h | 8
drivers/usb/gadget/pd12_udc.c | 1821 +++++++++++++++++++++++++++++++++++++
drivers/usb/gadget/pd12_udc.h | 148 +++
include/asm-ppc/ibm4xx.h | 4
14 files changed, 2548 insertions(+), 5 deletions(-)
create mode 100644 arch/ppc/platforms/4xx/taihu.c
create mode 100644 arch/ppc/platforms/4xx/taihu.h
create mode 100644 drivers/mtd/maps/taihu.c
create mode 100755 drivers/usb/gadget/pd12_udc.c
create mode 100644 drivers/usb/gadget/pd12_udc.h
diff --git a/arch/ppc/platforms/4xx/Kconfig b/arch/ppc/platforms/4xx/Kconfig
index 51414c4..4efba1e 100644
--- a/arch/ppc/platforms/4xx/Kconfig
+++ b/arch/ppc/platforms/4xx/Kconfig
@@ -66,6 +66,12 @@ config XILINX_ML403
bool "Xilinx-ML403"
help
This option enables support for the Xilinx ML403 evaluation board.
+
+config TAIHU
+ bool "Taihu"
+ select WANT_EARLY_SERIAL
+ help
+ This option enables support for the AMCC 405EP evaluation board.
endchoice
choice
@@ -120,7 +126,6 @@ config YOSEMITE
select WANT_EARLY_SERIAL
help
This option enables support for the AMCC PPC440EP evaluation board.
-
endchoice
config EP405PC
@@ -201,7 +206,7 @@ config BOOKE
config IBM_OCP
bool
- depends on ASH || BAMBOO || BUBINGA || CPCI405 || EBONY || EP405 || LUAN || YUCCA || OCOTEA || P3P440 || PPChameleonEVB || REDWOOD_5 || REDWOOD_6 || SYCAMORE || WALNUT || YELLOWSTONE || YOSEMITE
+ depends on ASH || BAMBOO || BUBINGA || CPCI405 || EBONY || EP405 || LUAN || YUCCA || OCOTEA || P3P440 || PPChameleonEVB || REDWOOD_5 || REDWOOD_6 || SYCAMORE || TAIHU || WALNUT || YELLOWSTONE || YOSEMITE
default y
config IBM_EMAC4
@@ -211,7 +216,7 @@ config IBM_EMAC4
config BIOS_FIXUP
bool
- depends on BUBINGA || EP405 || SYCAMORE || WALNUT
+ depends on BUBINGA || EP405 || SYCAMORE || TAIHU || WALNUT
default y
# OAK doesn't exist but wanted to keep this around for any future 403GCX boards
@@ -222,7 +227,7 @@ config 403GCX
config 405EP
bool
- depends on BUBINGA || PPChameleonEVB
+ depends on BUBINGA || PPChameleonEVB || TAIHU
default y
config 405GP
@@ -262,7 +267,7 @@ config EMBEDDEDBOOT
config IBM_OPENBIOS
bool
- depends on ASH || REDWOOD_5 || REDWOOD_6
+ depends on ASH || REDWOOD_5 || REDWOOD_6 || TAIHU
default y
config PPC4xx_DMA
diff --git a/arch/ppc/platforms/4xx/Makefile b/arch/ppc/platforms/4xx/Makefile
index d3a7a16..86374ff 100644
--- a/arch/ppc/platforms/4xx/Makefile
+++ b/arch/ppc/platforms/4xx/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_PPChameleonEVB) += ppchamel
obj-$(CONFIG_REDWOOD_5) += redwood5.o
obj-$(CONFIG_REDWOOD_6) += redwood6.o
obj-$(CONFIG_SYCAMORE) += sycamore.o
+obj-$(CONFIG_TAIHU) += taihu.o
obj-$(CONFIG_WALNUT) += walnut.o
obj-$(CONFIG_XILINX_ML300) += xilinx_ml300.o
obj-$(CONFIG_XILINX_ML403) += xilinx_ml403.o
diff --git a/arch/ppc/platforms/4xx/taihu.c b/arch/ppc/platforms/4xx/taihu.c
new file mode 100644
index 0000000..94bd72d
--- /dev/null
+++ b/arch/ppc/platforms/4xx/taihu.c
@@ -0,0 +1,260 @@
+/*
+ * Support for IBM PPC 405EP evaluation board (Taihu).
+ *
+ * Author: SAW (IBM), derived from walnut.c.
+ * Maintained by MontaVista Software <source@mvista.com>
+ *
+ * 2003 (c) MontaVista Softare Inc. This file is licensed under the
+ * terms of the GNU General Public License version 2. This program is
+ * licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/smp.h>
+#include <linux/threads.h>
+#include <linux/param.h>
+#include <linux/string.h>
+#include <linux/blkdev.h>
+#include <linux/pci.h>
+#include <linux/rtc.h>
+#include <linux/tty.h>
+#include <linux/serial.h>
+#include <linux/serial_core.h>
+
+#include <asm/system.h>
+#include <asm/pci-bridge.h>
+#include <asm/processor.h>
+#include <asm/machdep.h>
+#include <asm/page.h>
+#include <asm/time.h>
+#include <asm/io.h>
+#include <asm/todc.h>
+#include <asm/kgdb.h>
+#include <asm/ocp.h>
+#include <asm/ibm_ocp_pci.h>
+
+#include <platforms/4xx/ibm405ep.h>
+
+#undef DEBUG
+
+#ifdef DEBUG
+#define DBG(x...) printk(x)
+#else
+#define DBG(x...)
+#endif
+
+extern bd_t __res;
+
+
+/* Some IRQs unique to the board
+ * Used by the generic 405 PCI setup functions in ppc4xx_pci.c
+ */
+int __init
+ppc405_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
+{
+ static char pci_irq_table[][4] =
+ /*
+ * PCI IDSEL/INTPIN->INTLINE
+ * A B C D
+ */
+ {
+ {25, 26, 27, 28}, /* IDSEL 1 - PCI slot 1 */
+ {26, 27, 28, 25}, /* IDSEL 2 - PCI slot 2 */
+ };
+
+ const long min_idsel = 6, max_idsel = 7, irqs_per_slot = 4;
+ return PCI_IRQ_TABLE_LOOKUP;
+};
+
+/* The serial clock for the chip is an internal clock determined by
+ * different clock speeds/dividers.
+ * Calculate the proper input baud rate and setup the serial driver.
+ */
+static void __init
+taihu_early_serial_map(void)
+{
+ u32 uart_div;
+ int uart_clock;
+ struct uart_port port;
+
+ /* Calculate the serial clock input frequency
+ *
+ * The base baud is the PLL OUTA (provided in the board info
+ * structure) divided by the external UART Divisor, divided
+ * by 16.
+ */
+ uart_div = (mfdcr(DCRN_CPC0_UCR_BASE) & DCRN_CPC0_UCR_U0DIV);
+ uart_clock = __res.bi_pllouta_freq / uart_div;
+
+ /* Setup serial port access */
+ memset(&port, 0, sizeof(port));
+ port.membase = (void*)ACTING_UART0_IO_BASE;
+ port.irq = ACTING_UART0_INT;
+ port.uartclk = uart_clock;
+ port.regshift = 0;
+ port.iotype = SERIAL_IO_MEM;
+ port.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST;
+ port.line = 0;
+
+ if (early_serial_setup(&port) != 0) {
+ printk("Early serial init of port 0 failed\n");
+ }
+
+ port.membase = (void*)ACTING_UART1_IO_BASE;
+ port.irq = ACTING_UART1_INT;
+ port.line = 1;
+
+ if (early_serial_setup(&port) != 0) {
+ printk("Early serial init of port 1 failed\n");
+ }
+}
+
+void __init
+bios_fixup(struct pci_controller *hose, struct pcil0_regs *pcip)
+{
+
+ unsigned int bar_response, bar;
+ /*
+ * Expected PCI mapping:
+ *
+ * PLB addr PCI memory addr
+ * --------------------- ---------------------
+ * 0000'0000 - 7fff'ffff <--- 0000'0000 - 7fff'ffff
+ * 8000'0000 - Bfff'ffff ---> 8000'0000 - Bfff'ffff
+ *
+ * PLB addr PCI io addr
+ * --------------------- ---------------------
+ * e800'0000 - e800'ffff ---> 0000'0000 - 0001'0000
+ *
+ * The following code is simplified by assuming that the bootrom
+ * has been well behaved in following this mapping.
+ */
+
+#ifdef DEBUG
+ int i;
+
+ printk("ioremap PCLIO_BASE = 0x%x\n", pcip);
+ printk("PCI bridge regs before fixup \n");
+ for (i = 0; i <= 3; i++) {
+ printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma)));
+ printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].la)));
+ printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pcila)));
+ printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pciha)));
+ }
+ printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms)));
+ printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la)));
+ printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms)));
+ printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la)));
+
+#endif
+
+ /* added for IBM boot rom version 1.15 bios bar changes -AK */
+
+ /* Disable region first */
+ out_le32((void *) &(pcip->pmm[0].ma), 0x00000000);
+ /* PLB starting addr, PCI: 0x80000000 */
+ out_le32((void *) &(pcip->pmm[0].la), 0x80000000);
+ /* PCI start addr, 0x80000000 */
+ out_le32((void *) &(pcip->pmm[0].pcila), PPC405_PCI_MEM_BASE);
+ /* 512MB range of PLB to PCI */
+ out_le32((void *) &(pcip->pmm[0].pciha), 0x00000000);
+ /* Enable no pre-fetch, enable region */
+ out_le32((void *) &(pcip->pmm[0].ma), ((0xffffffff -
+ (PPC405_PCI_UPPER_MEM -
+ PPC405_PCI_MEM_BASE)) | 0x01));
+
+ /* Disable region one */
+ out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
+ out_le32((void *) &(pcip->pmm[1].la), 0x00000000);
+ out_le32((void *) &(pcip->pmm[1].pcila), 0x00000000);
+ out_le32((void *) &(pcip->pmm[1].pciha), 0x00000000);
+ out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
+ out_le32((void *) &(pcip->ptm1ms), 0x00000001);
+
+ /* Disable region two */
+ out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
+ out_le32((void *) &(pcip->pmm[2].la), 0x00000000);
+ out_le32((void *) &(pcip->pmm[2].pcila), 0x00000000);
+ out_le32((void *) &(pcip->pmm[2].pciha), 0x00000000);
+ out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
+ out_le32((void *) &(pcip->ptm2ms), 0x00000000);
+ out_le32((void *) &(pcip->ptm2la), 0x00000000);
+
+ /* Zero config bars */
+ for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) {
+ early_write_config_dword(hose, hose->first_busno,
+ PCI_FUNC(hose->first_busno), bar,
+ 0x00000000);
+ early_read_config_dword(hose, hose->first_busno,
+ PCI_FUNC(hose->first_busno), bar,
+ &bar_response);
+ DBG("BUS %d, device %d, Function %d bar 0x%8.8x is 0x%8.8x\n",
+ hose->first_busno, PCI_SLOT(hose->first_busno),
+ PCI_FUNC(hose->first_busno), bar, bar_response);
+ }
+ /* end work arround */
+
+#ifdef DEBUG
+ printk("PCI bridge regs after fixup \n");
+ for (i = 0; i <= 3; i++) {
+ printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma)));
+ printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].la)));
+ printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pcila)));
+ printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pciha)));
+ }
+ printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms)));
+ printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la)));
+ printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms)));
+ printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la)));
+
+#endif
+}
+
+static void __init
+taihu_set_emacdata(void)
+{
+ struct ocp_def *def;
+ struct ocp_func_emac_data *emacdata;
+
+ def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 0);
+ emacdata = def->additions;
+ emacdata->phy_map = 0x000fffff; /* skip 0x00 .. 0x13 */
+}
+
+void __init
+taihu_setup_arch(void)
+{
+ taihu_set_emacdata();
+
+ ppc4xx_setup_arch();
+
+ ibm_ocp_set_emac(0, 1);
+
+ taihu_early_serial_map();
+
+ /* Identify the system */
+ printk("AMCC PowerPC 405EP Taihu Platform\n");
+}
+
+void __init
+taihu_map_io(void)
+{
+ ppc4xx_map_io();
+}
+
+void __init
+platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
+ unsigned long r6, unsigned long r7)
+{
+ ppc4xx_init(r3, r4, r5, r6, r7);
+
+ ppc_md.setup_arch = taihu_setup_arch;
+ ppc_md.setup_io_mappings = taihu_map_io;
+
+#ifdef CONFIG_KGDB
+ ppc_md.early_serial_map = taihu_early_serial_map;
+#endif
+}
+
diff --git a/arch/ppc/platforms/4xx/taihu.h b/arch/ppc/platforms/4xx/taihu.h
new file mode 100644
index 0000000..eb2aa7a
--- /dev/null
+++ b/arch/ppc/platforms/4xx/taihu.h
@@ -0,0 +1,105 @@
+/*
+ * Support for IBM PPC 405EP evaluation board (Taihu).
+ *
+ * Author: SAW (IBM), derived from walnut.h.
+ * Maintained by MontaVista Software <source@mvista.com>
+ *
+ * 2003 (c) MontaVista Softare Inc. This file is licensed under the
+ * terms of the GNU General Public License version 2. This program is
+ * licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+
+#ifdef __KERNEL__
+#ifndef __TAIHU_H__
+#define __TAIHU_H__
+
+/* 405EP */
+#include <platforms/4xx/ibm405ep.h>
+
+#ifndef __ASSEMBLY__
+/*
+ * Data structure defining board information maintained by the boot
+ * ROM on IBM's evaluation board. An effort has been made to
+ * keep the field names consistent with the 8xx 'bd_t' board info
+ * structures.
+ */
+#define CONFIG_HAS_ETH1 1
+typedef struct board_info {
+ unsigned long bi_memstart; /* start of DRAM memory */
+ unsigned long bi_memsize; /* size of DRAM memory in bytes */
+ unsigned long bi_flashstart; /* start of FLASH memory */
+ unsigned long bi_flashsize; /* size of FLASH memory */
+ unsigned long bi_flashoffset; /* reserved area for startup monitor */
+ unsigned long bi_sramstart; /* start of SRAM memory */
+ unsigned long bi_sramsize; /* size of SRAM memory */
+ unsigned long bi_bootflags; /* boot / reboot flag (for LynxOS) */
+ unsigned long bi_ip_addr; /* IP Address */
+ unsigned char bi_enetaddr[6]; /* Ethernet adress */
+ unsigned short bi_ethspeed; /* Ethernet speed in Mbps */
+ unsigned long bi_intfreq; /* Internal Freq, in MHz */
+ unsigned long bi_busfreq; /* Bus Freq, in MHz */
+ unsigned long bi_baudrate; /* Console Baudrate */
+#if defined(CONFIG_405) || \
+ defined(CONFIG_405GP) || \
+ defined(CONFIG_405CR) || \
+ defined(CONFIG_405EP) || \
+ defined(CONFIG_440)
+ unsigned char bi_s_version[4]; /* Version of this structure */
+ unsigned char bi_r_version[32]; /* Version of the ROM (IBM) */
+ unsigned int bi_pllouta_freq; /* CPU (Internal) Freq, in Hz */
+ unsigned int bi_plb_busfreq; /* PLB Bus speed, in Hz */
+ unsigned int bi_pci_busfreq; /* PCI Bus speed, in Hz */
+ unsigned char bi_pci_enetaddr[6]; /* PCI Ethernet MAC address */
+#endif
+
+#ifdef CONFIG_HAS_ETH1
+ /* second onboard ethernet port */
+ unsigned char bi_enet1addr[6];
+#endif
+#ifdef CONFIG_HAS_ETH2
+ /* third onboard ethernet port */
+ unsigned char bi_enet2addr[6];
+#endif
+#ifdef CONFIG_HAS_ETH3
+ unsigned char bi_enet3addr[6];
+#endif
+
+#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || defined (CONFIG_440GX) || \
+ defined(CONFIG_440EP) || defined(CONFIG_440GR)
+ unsigned int bi_opbfreq; /* OPB clock in Hz */
+ int bi_iic_fast[2]; /* Use fast i2c mode */
+#endif
+#if defined(CONFIG_4xx)
+#if defined(CONFIG_440GX)
+ int bi_phynum[4]; /* Determines phy mapping */
+ int bi_phymode[4]; /* Determines phy mode */
+#elif defined(CONFIG_405EP) || defined(CONFIG_440)
+ int bi_phynum[2]; /* Determines phy mapping */
+ int bi_phymode[2]; /* Determines phy mode */
+#else
+ int bi_phynum[1]; /* Determines phy mapping */
+ int bi_phymode[1]; /* Determines phy mode */
+#endif
+#endif /* defined(CONFIG_4xx) */
+} bd_t;
+
+/* Some 4xx parts use a different timebase frequency from the internal clock.
+*/
+#define bi_tbfreq bi_intfreq
+
+
+/* The UART clock is based off an internal clock -
+ * define BASE_BAUD based on the internal clock and divider(s).
+ * Since BASE_BAUD must be a constant, we will initialize it
+ * using clock/divider values which OpenBIOS initializes
+ * for typical configurations at various CPU speeds.
+ * The base baud is calculated as (FWDA / EXT UART DIV / 16)
+ */
+#define BASE_BAUD 691200
+
+#define PPC4xx_MACHINE_NAME "AMCC Taihu"
+
+#endif /* !__ASSEMBLY__ */
+#endif /* __TAIHU_H__ */
+#endif /* __KERNEL__ */
diff --git a/drivers/mtd/maps/Kconfig b/drivers/mtd/maps/Kconfig
index 9848471..41941c7 100644
--- a/drivers/mtd/maps/Kconfig
+++ b/drivers/mtd/maps/Kconfig
@@ -321,6 +321,14 @@ config MTD_ARCTIC
Arctic board. If you have one of these boards and would like to
use the flash chips on it, say 'Y'.
+config MTD_TAIHU
+ tristate "Flash device mapped on AMCC 405EP Taihu"
+ depends on MTD_CFI && PPC32 && 40x && TAIHU
+ help
+ This enables access routines for the flash chips on the AMCC 405EP
+ Taihu board. If you have one of these boards and would like to
+ use the flash chips on it, say 'Y'.
+
config MTD_WALNUT
tristate "Flash device mapped on AMCC 405GP/r/EP Walnut/Sycamore/Bubinga"
depends on MTD_JEDECPROBE && (WALNUT || SYCAMORE || BUBINGA)
diff --git a/drivers/mtd/maps/Makefile b/drivers/mtd/maps/Makefile
index c2cf73a..b2210de 100644
--- a/drivers/mtd/maps/Makefile
+++ b/drivers/mtd/maps/Makefile
@@ -58,6 +58,7 @@ obj-$(CONFIG_MTD_OCOTEA) += ocotea.o
obj-$(CONFIG_MTD_BAMBOO) += bamboo.o
obj-$(CONFIG_MTD_BEECH) += beech-mtd.o
obj-$(CONFIG_MTD_ARCTIC) += arctic-mtd.o
+obj-$(CONFIG_MTD_TAIHU) += taihu.o
obj-$(CONFIG_MTD_WALNUT) += walnut.o
obj-$(CONFIG_MTD_YOSEMITE) += yosemite.o
obj-$(CONFIG_MTD_H720X) += h720x-flash.o
diff --git a/drivers/mtd/maps/taihu.c b/drivers/mtd/maps/taihu.c
new file mode 100644
index 0000000..432e07d
--- /dev/null
+++ b/drivers/mtd/maps/taihu.c
@@ -0,0 +1,155 @@
+/*
+ *
+ * drivers/mtd/maps/taihu.c
+ *
+ * FLASH map for the AMCC Taihu boards.
+ *
+ * 2005 UDTech, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+
+#include <linux/config.h>
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/map.h>
+#include <linux/mtd/partitions.h>
+
+#include <asm/io.h>
+
+#define BOOTWINDOW_ADDR 0xffe00000
+#define BOOTWINDOW_SIZE 0x00200000
+
+#define APPWINDOW_ADDR 0xfc000000
+#define APPWINDOW_SIZE 0x02000000
+
+
+static struct mtd_partition taihu_bootflash_partitions[] = {
+ {
+ .name = "kozio diags",
+ .offset = 0,
+ .size = 0x001a0000,
+ .mask_flags = MTD_WRITEABLE /* force read-only */
+ },
+ {
+ .name = "u-boot env",
+ .offset = 0x001a0000,
+ .size = 0x00020000
+ },
+ {
+ .name = "u-boot",
+ .offset = 0x001c0000,
+ .size = 0x00040000,
+ .mask_flags = MTD_WRITEABLE /* force read-only */
+ }
+};
+
+struct map_info taihu_bootflash_map = {
+ .name = "AMCC Taihu Boot Flash",
+ .size = BOOTWINDOW_SIZE,
+ .bankwidth = 2,
+ .phys = BOOTWINDOW_ADDR,
+};
+
+static struct mtd_partition taihu_appflash_partitions[] = {
+ {
+ .name = "kernel",
+ .offset = 0,
+ .size = 0x00300000,
+ .mask_flags = MTD_WRITEABLE /* force read-only */
+ },
+ {
+ .name = "initrd",
+ .offset = 0x00300000,
+ .size = 0x01a00000,
+ .mask_flags = MTD_WRITEABLE /* force read-only */
+ },
+ {
+ .name = "jffs2",
+ .offset = 0x01D00000,
+ .size = 0x00300000
+ }
+};
+
+
+struct map_info taihu_appflash_map = {
+ .name = "AMCC Taihu Application Flash",
+ .size = APPWINDOW_SIZE,
+ .bankwidth = 2,
+ .phys = APPWINDOW_ADDR,
+};
+
+
+#define NUM_TAIHU_FLASH_PARTITIONS(parts) \
+ (sizeof(parts)/sizeof(parts[0]))
+
+static struct mtd_info *taihu_mtd;
+
+int __init init_taihu_flash(void)
+{
+
+ printk(KERN_NOTICE "taihu: bootflash mapping: %x at %x\n",
+ BOOTWINDOW_SIZE, BOOTWINDOW_ADDR);
+ taihu_bootflash_map.virt = ioremap(BOOTWINDOW_ADDR, BOOTWINDOW_SIZE);
+ if (!taihu_bootflash_map.virt) {
+ printk("init_taihu_flash: failed to ioremap for bootflash\n");
+ return -EIO;
+ }
+ simple_map_init(&taihu_bootflash_map);
+ taihu_mtd = do_map_probe("cfi_probe", &taihu_bootflash_map);
+ if (taihu_mtd) {
+ taihu_mtd->owner = THIS_MODULE;
+ add_mtd_partitions(taihu_mtd,
+ taihu_bootflash_partitions,
+ ARRAY_SIZE(taihu_bootflash_partitions));
+ } else {
+ printk("map probe failed (bootflash)\n");
+ return -ENXIO;
+ }
+
+ printk(KERN_NOTICE "taihu: appflash mapping: %x at %x\n",
+ APPWINDOW_SIZE, APPWINDOW_ADDR);
+ taihu_appflash_map.virt = ioremap(APPWINDOW_ADDR, APPWINDOW_SIZE);
+ if (!taihu_appflash_map.virt) {
+ printk("init_taihu_flash: failed to ioremap for appflash\n");
+ return -EIO;
+ }
+ simple_map_init(&taihu_appflash_map);
+ taihu_mtd = do_map_probe("cfi_probe", &taihu_appflash_map);
+ if (taihu_mtd) {
+ taihu_mtd->owner = THIS_MODULE;
+ add_mtd_partitions(taihu_mtd,
+ taihu_appflash_partitions,
+ ARRAY_SIZE(taihu_appflash_partitions));
+ } else {
+ printk("map probe failed (appflash)\n");
+ return -ENXIO;
+ }
+
+ return 0;
+}
+
+static void __exit cleanup_taihu_flash(void)
+{
+ if (taihu_mtd) {
+ del_mtd_partitions(taihu_mtd);
+ /* moved iounmap after map_destroy - armin */
+ map_destroy(taihu_mtd);
+ }
+
+ if (taihu_bootflash_map.virt)
+ iounmap((void *)taihu_bootflash_map.virt);
+ if (taihu_appflash_map.virt)
+ iounmap((void *)taihu_appflash_map.virt);
+}
+
+module_init(init_taihu_flash);
+module_exit(cleanup_taihu_flash);
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("MTD map driver for the AMCC Taihu board");
diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig
index 363b2ad..c541e12 100644
--- a/drivers/usb/gadget/Kconfig
+++ b/drivers/usb/gadget/Kconfig
@@ -154,6 +154,17 @@ config USB_LH7A40X
default USB_GADGET
select USB_GADGET_SELECTED
+config USB_GADGET_PD12
+ boolean "PD12 UDC"
+ depends on TAIHU
+ help
+ This driver provides USB Device Controller driver for PD12 UDC
+
+config USB_PD12
+ tristate
+ depends on USB_GADGET_PD12
+ default USB_GADGET
+ select USB_GADGET_SELECTED
config USB_GADGET_OMAP
boolean "OMAP USB Device Controller"
diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile
index 5a28e61..4422f49 100644
--- a/drivers/usb/gadget/Makefile
+++ b/drivers/usb/gadget/Makefile
@@ -8,6 +8,7 @@ obj-$(CONFIG_USB_GOKU) += goku_udc.o
obj-$(CONFIG_USB_OMAP) += omap_udc.o
obj-$(CONFIG_USB_LH7A40X) += lh7a40x_udc.o
obj-$(CONFIG_USB_AT91) += at91_udc.o
+obj-$(CONFIG_USB_PD12) += pd12_udc.o
#
# USB gadget drivers
diff --git a/drivers/usb/gadget/epautoconf.c b/drivers/usb/gadget/epautoconf.c
index f7c6d75..9c32fa8 100644
--- a/drivers/usb/gadget/epautoconf.c
+++ b/drivers/usb/gadget/epautoconf.c
@@ -274,6 +274,21 @@ struct usb_ep * __init usb_ep_autoconfig
ep = find_ep (gadget, "ep1-bulk");
if (ep && ep_matches (gadget, ep, desc))
return ep;
+
+ } else if (gadget_is_pd12 (gadget)) {
+ if (USB_ENDPOINT_XFER_BULK == type
+ && (USB_DIR_IN & desc->bEndpointAddress)) {
+ /* single buffering is enough */
+ ep = find_ep (gadget, "ep2in-bulk");
+ if (ep && ep_matches (gadget, ep, desc))
+ return ep;
+ } else if (USB_ENDPOINT_XFER_BULK == type
+ && (USB_DIR_OUT & desc->bEndpointAddress)) {
+ /* DMA may be available */
+ ep = find_ep (gadget, "ep1out-bulk");
+ if (ep && ep_matches (gadget, ep, desc))
+ return ep;
+ }
}
/* Second, look at endpoints until an unclaimed one looks usable */
diff --git a/drivers/usb/gadget/gadget_chips.h b/drivers/usb/gadget/gadget_chips.h
index aa80f09..af3767c 100644
--- a/drivers/usb/gadget/gadget_chips.h
+++ b/drivers/usb/gadget/gadget_chips.h
@@ -87,6 +87,12 @@
#define gadget_is_at91(g) 0
#endif
+#ifdef CONFIG_USB_GADGET_PD12
+#define gadget_is_pd12(g) !strcmp("pd12_udc", (g)->name)
+#else
+#define gadget_is_pd12(g) 0
+#endif
+
#ifdef CONFIG_USB_GADGET_IMX
#define gadget_is_imx(g) !strcmp("imx_udc", (g)->name)
#else
@@ -169,5 +175,7 @@ static inline int usb_gadget_controller_
return 0x16;
else if (gadget_is_mpc8272(gadget))
return 0x17;
+ else if (gadget_is_pd12(gadget))
+ return 0x18;
return -ENOENT;
}
diff --git a/drivers/usb/gadget/pd12_udc.c b/drivers/usb/gadget/pd12_udc.c
new file mode 100755
index 0000000..6c52353
--- /dev/null
+++ b/drivers/usb/gadget/pd12_udc.c
@@ -0,0 +1,1821 @@
+/*
+ * linux/drivers/usb/gadget/pd12_udc.c
+ * Taihu pd12-udc full speed USB device controllers
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#include "pd12_udc.h"
+
+/*#define DEBUG_PD12 printk*/
+/*#define DEBUG_PD12_EP0 printk*/
+/*#define DEBUG_PD12_SETUP printk*/
+
+#ifndef DEBUG_PD12_EP0
+# define DEBUG_PD12_EP0(fmt,args...)
+#endif
+#ifndef DEBUG_PD12_SETUP
+# define DEBUG_PD12_SETUP(fmt,args...)
+#endif
+#ifndef DEBUG_PD12
+# define NO_STATES
+# define DEBUG_PD12(fmt,args...)
+#endif
+
+#define DRIVER_DESC "PD12 USB Device Controller"
+#define DRIVER_VERSION __DATE__
+
+
+static const char driver_name[] = "pd12_udc";
+static const char driver_desc[] = DRIVER_DESC;
+static const char ep0name[] = "ep0-control";
+static void __iomem *th_pd12_virt;
+static void __iomem *th_cpld_virt;
+static u8 first_tran = 1;
+
+#define DEV_CMD_ADDR ((ulong)th_pd12_virt+1)
+#define DEV_DATA_ADDR (th_pd12_virt)
+
+#define CPLD_REG0_ADDR (th_cpld_virt)
+#define CPLD_REG1_ADDR ((ulong)th_cpld_virt+1)
+/*
+ Local definintions.
+*/
+
+#ifndef NO_STATES
+static char *state_names[] = {
+ "WAIT_FOR_SETUP",
+ "DATA_STATE_XMIT",
+ "DATA_STATE_NEED_ZLP",
+ "WAIT_FOR_OUT_STATUS",
+ "DATA_STATE_RECV"
+};
+#endif
+
+/*
+ Local declarations.
+*/
+static int pd12_ep_enable(struct usb_ep *ep,
+ const struct usb_endpoint_descriptor *);
+static int pd12_ep_disable(struct usb_ep *ep);
+static struct usb_request *pd12_alloc_request(struct usb_ep *ep, unsigned);
+static void pd12_free_request(struct usb_ep *ep, struct usb_request *);
+static void *pd12_alloc_buffer(struct usb_ep *ep, unsigned, dma_addr_t *,
+ unsigned);
+static void pd12_free_buffer(struct usb_ep *ep, void *, dma_addr_t,
+ unsigned);
+static int pd12_queue(struct usb_ep *ep, struct usb_request *, unsigned);
+static int pd12_dequeue(struct usb_ep *ep, struct usb_request *);
+static int pd12_set_halt(struct usb_ep *ep, int);
+static void pd12_ep0_kick(struct pd12_udc *dev, struct pd12_ep *ep);
+static void pd12_handle_ep0(struct pd12_udc *dev);
+
+static void done(struct pd12_ep *ep, struct pd12_request *req,
+ int status);
+static void stop_activity(struct pd12_udc *dev,
+ struct usb_gadget_driver *driver);
+static void flush(struct pd12_ep *ep);
+static void udc_enable(struct pd12_udc *dev);
+static void udc_set_address(struct pd12_udc *dev, unsigned char address);
+
+static struct usb_ep_ops pd12_ep_ops = {
+ .enable = pd12_ep_enable,
+ .disable = pd12_ep_disable,
+
+ .alloc_request = pd12_alloc_request,
+ .free_request = pd12_free_request,
+
+ .alloc_buffer = pd12_alloc_buffer,
+ .free_buffer = pd12_free_buffer,
+
+ .queue = pd12_queue,
+ .dequeue = pd12_dequeue,
+
+ .set_halt = pd12_set_halt,
+};
+
+
+static __inline__ void read_data(volatile u8 *val)
+{
+ *val = *(volatile u8 *)DEV_DATA_ADDR;
+ udelay(5);
+}
+
+static __inline__ void write_data(u8 val)
+{
+ *(volatile u8 *)DEV_DATA_ADDR = val;
+ udelay(5);
+}
+
+static __inline__ void write_cmd(u8 val)
+{
+ *(volatile u8 *)DEV_CMD_ADDR = val;
+ udelay(5);
+}
+
+static __inline__ void usb_set_index(u8 ep)
+{
+ if(ep != 0)
+ ep += 1;
+ write_cmd(ep);
+}
+
+static void pd12_set_ack(u8 index)
+{
+
+ write_cmd(index);
+ write_cmd(PD12_ACK_SETUP);
+ if(index == 0)
+ write_cmd(PD12_CLEAR_BUF);
+
+}
+
+static int write_fifo(struct pd12_ep *ep, struct pd12_request *req)
+{
+ u8 *buf;
+ unsigned count;
+ unsigned length;
+ int is_last;
+ u8 ep_sts;
+
+ buf = req->req.buf + req->req.actual;
+ prefetch(buf);
+
+ count = ep->ep.maxpacket;
+ length = req->req.length - req->req.actual;
+ length = min(length, count);
+ req->req.actual += length;
+
+ DEBUG_PD12("Write %d (max %d), fifo %p\n", length, count, buf);
+ write_cmd(1);
+ read_data(&ep_sts);
+/* write_cmd(PD12_ACK_SETUP); */
+ write_cmd(PD12_WRITE_BUF);
+ write_data(0x0);
+ write_data(length);
+ if(length == 0)
+ write_data(0x0);
+ while(length--)
+ write_data(*buf++);
+ write_cmd(PD12_VALIDATE_BUF);
+ if(length != ep->ep.maxpacket)
+ is_last = 1;
+ else if(req->req.length == req->req.actual
+ && !req->req.zero)
+ is_last = 1;
+ else
+ is_last = 0;
+
+ if(is_last)
+ done(ep,req,0);
+ return is_last;
+
+}
+/*-------------------------------------------------------------------------*/
+
+#ifdef CONFIG_USB_GADGET_DEBUG_PD12_FILES
+
+static const char proc_node_name[] = "driver/udc";
+
+static int
+udc_proc_read(char *page, char **start, off_t off, int count,
+ int *eof, void *_dev)
+{
+ char *buf = page;
+ struct pd12_udc *dev = _dev;
+ char *next = buf;
+ unsigned size = count;
+ unsigned long flags;
+ int t;
+ u8 ep_status[6];
+
+ if (off != 0)
+ return 0;
+
+ local_irq_save(flags);
+
+ /* basic device status */
+ t = scnprintf(next, size,
+ DRIVER_DESC "\n"
+ "%s version: %s\n"
+ "Gadget driver: %s\n"
+ "Host: %s\n\n",
+ driver_name, DRIVER_VERSION,
+ dev->driver ? dev->driver->driver.name : "(none)");
+ size -= t;
+ next += t;
+
+ for(i=0;i<PD12_MAX_ENDPOINTS;i++)
+ {
+ write_cmd(PD12_READ_LAST_STATUS+i);
+ read_data(&ep_status[i]);
+ }
+ t = scnprintf(next, size,
+ "Endpoints last status:\n"
+ " ep0: 0x%x, ep1: 0x%x, ep2: 0x%x\n"
+ " ep3: 0x%x, ep4: 0x%x, ep5: 0x%x\n\n",
+ ep_status[0], ep_status[1], ep_status[2],
+ ep_status[3], ep_status[4], ep_status[5]
+ );
+ size -= t;
+ next += t;
+
+ local_irq_restore(flags);
+ *eof = 1;
+ return count - size;
+}
+
+#define create_proc_files() create_proc_read_entry(proc_node_name, 0, NULL, udc_proc_read, dev)
+#define remove_proc_files() remove_proc_entry(proc_node_name, NULL)
+
+#else /* !CONFIG_USB_GADGET_DEBUG_FILES */
+
+#define create_proc_files() do {} while (0)
+#define remove_proc_files() do {} while (0)
+
+#endif /* CONFIG_USB_GADGET_DEBUG_FILES */
+
+static void pd12_set_mode(u8 val)
+{
+ write_cmd(PD12_SET_MODE);
+ write_data(val);
+ write_data(0x3);/*maybe 0x43*/
+}
+static void pd12_read_int(u16* val)
+{
+ write_cmd(PD12_READ_INT);
+ read_data((u8*)val);
+}
+
+static void pd12_read_lstatus(u8 index, u8* val)
+{
+ write_cmd(PD12_READ_LAST_STATUS + index);
+ read_data(val);
+}
+/*
+ * udc_disable - disable USB device controller
+ */
+static void udc_disable(struct pd12_udc *dev)
+{
+ DEBUG_PD12("%s, %p\n", __FUNCTION__, dev);
+
+ udc_set_address(dev, 0);
+ pd12_set_mode(0x06); /*disconnect soft connect pullup resior */
+
+ dev->ep0state = WAIT_FOR_SETUP;
+ dev->gadget.speed = USB_SPEED_UNKNOWN;
+ dev->usb_address = 0;
+}
+
+
+/*
+ * udc_reinit - initialize software state
+ */
+static void udc_reinit(struct pd12_udc *dev)
+{
+ u8 i;
+ u16 tmp;
+
+ DEBUG_PD12("%s, %p\n", __FUNCTION__, dev);
+
+ udc_set_address(dev, 0);
+ pd12_set_mode(0x06); /*disconnect soft connect pullup resior */
+ mdelay(1500);
+ pd12_set_mode(0x16); /*soft connnect*/
+ pd12_read_int(&tmp);
+ for(i= 0; i< 5; i++)
+ pd12_read_lstatus(i,(u8 *)(&tmp));
+
+ /* device/ep0 records init */
+ INIT_LIST_HEAD(&dev->gadget.ep_list);
+ INIT_LIST_HEAD(&dev->gadget.ep0->ep_list);
+ dev->ep0state = WAIT_FOR_SETUP;
+ dev->gadget.speed = USB_SPEED_UNKNOWN;
+ dev->usb_address = 0;
+
+ /* basic endpoint records init */
+ for (i = 0; i < PD12_MAX_ENDPOINTS; i++) {
+ struct pd12_ep *ep = &dev->ep[i];
+
+ if (i != 0)
+ list_add_tail(&ep->ep.ep_list, &dev->gadget.ep_list);
+
+ ep->desc = 0;
+ ep->stopped = 0;
+ INIT_LIST_HEAD(&ep->queue);
+ }
+
+ /* the rest was statically initialized, and is read-only */
+}
+
+/* until it's enabled, this UDC should be completely invisible
+ * to any USB host.
+ */
+static void udc_enable(struct pd12_udc *dev)
+{
+
+ u8 i;
+ u16 tmp;
+
+ DEBUG_PD12("%s, %p\n", __FUNCTION__, dev);
+
+ pd12_set_mode(0x06); /*disconnect soft connect pullup resior */
+ mdelay(1500);
+ pd12_set_mode(0x16); /*soft connnect*/
+ pd12_read_int(&tmp);
+ for(i= 0; i< 5; i++)
+ pd12_read_lstatus(i,(u8 *)(&tmp));
+ dev->gadget.speed = USB_SPEED_FULL;
+
+}
+
+/*
+ Register entry point for the peripheral controller driver.
+*/
+int usb_gadget_register_driver(struct usb_gadget_driver *driver)
+{
+ struct pd12_udc *dev = the_controller;
+ int retval;
+
+ DEBUG_PD12("%s: %s\n", __FUNCTION__, driver->driver.name);
+ if (!driver
+ || driver->speed != USB_SPEED_FULL
+ || !driver->bind
+ || !driver->unbind || !driver->disconnect || !driver->setup)
+ return -EINVAL;
+ if (!dev)
+ return -ENODEV;
+ if (dev->driver)
+ return -EBUSY;
+ /* first hook up the driver ... */
+ dev->driver = driver;
+ dev->gadget.dev.driver = &driver->driver;
+
+ device_add(&dev->gadget.dev);
+ retval = driver->bind(&dev->gadget);
+ if (retval) {
+ printk("%s: bind to driver %s --> error %d\n", dev->gadget.name,
+ driver->driver.name, retval);
+ device_del(&dev->gadget.dev);
+
+ dev->driver = 0;
+ dev->gadget.dev.driver = 0;
+ return retval;
+ }
+
+ /* ... then enable host detection and ep0; and we're ready
+ * for set_configuration as well as eventual disconnect.
+ * NOTE: this shouldn't power up until later.
+ */
+ printk("%s: registered gadget driver '%s'\n", dev->gadget.name,
+ driver->driver.name);
+
+ udc_enable(dev);
+
+ return 0;
+}
+
+EXPORT_SYMBOL(usb_gadget_register_driver);
+
+/*
+ Unregister entry point for the peripheral controller driver.
+*/
+int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
+{
+ struct pd12_udc *dev = the_controller;
+ unsigned long flags;
+
+ if (!dev)
+ return -ENODEV;
+ if (!driver || driver != dev->driver)
+ return -EINVAL;
+
+ spin_lock_irqsave(&dev->lock, flags);
+ dev->driver = 0;
+ stop_activity(dev, driver);
+ spin_unlock_irqrestore(&dev->lock, flags);
+
+ driver->unbind(&dev->gadget);
+ device_del(&dev->gadget.dev);
+
+ udc_disable(dev);
+
+ DEBUG_PD12("unregistered gadget driver '%s'\n", driver->driver.name);
+ return 0;
+}
+
+EXPORT_SYMBOL(usb_gadget_unregister_driver);
+
+/*-------------------------------------------------------------------------*/
+
+/** Read to request from FIFO (max read == bytes in fifo)
+ * Return: 0 = still running, 1 = completed, negative = errno
+ * NOTE: INDEX register must be set for EP
+ */
+static int read_fifo(struct pd12_ep *ep, struct pd12_request *req)
+{
+ u8 count;
+ u8 ep_sts;
+ u8 *buf;
+ unsigned bufferspace, is_short;
+
+ /* make sure there's a packet in the FIFO. */
+ usb_set_index(ep_index(ep));
+ read_data(&ep_sts);
+ if ((ep_sts & UDC_FIFO_UNREADABLE) == UDC_FIFO_UNREADABLE) {
+ DEBUG_PD12("%s: Packet NOT ready!\n", __FUNCTION__);
+ return -EINVAL;
+ }
+
+ buf = req->req.buf + req->req.actual;
+ prefetchw(buf);
+ bufferspace = req->req.length - req->req.actual;
+
+ /* read all bytes from this packet */
+ write_cmd(PD12_READ_BUF);
+ read_data(&count);
+ read_data(&count);
+ req->req.actual += min((unsigned)count, bufferspace);
+
+ is_short = (count < ep->ep.maxpacket);
+ DEBUG_PD12("read %s %02x, %d bytes%s req %p %d/%d\n",
+ ep->ep.name, ep_sts, count,
+ is_short ? "/S" : "", req, req->req.actual, req->req.length);
+
+ while (count-- != 0) {
+
+ if (bufferspace == 0) {
+ /* this happens when the driver's buffer
+ * is smaller than what the host sent.
+ * discard the extra data.
+ */
+ if (req->req.status != -EOVERFLOW)
+ printk("%s overflow %d\n", ep->ep.name, count);
+ req->req.status = -EOVERFLOW;
+ } else {
+ read_data(buf++);
+ bufferspace--;
+ }
+ }
+
+ write_cmd(PD12_CLEAR_BUF);
+
+ /* completion */
+ if (is_short || req->req.actual == req->req.length) {
+ done(ep, req, 0);
+
+ return 1;
+ }
+
+ /* finished that packet. the next one may be waiting... */
+ return 0;
+}
+
+
+/*
+ * done - retire a request; caller blocked irqs
+ * INDEX register is preserved to keep same
+ */
+static void done(struct pd12_ep *ep, struct pd12_request *req, int status)
+{
+ unsigned int stopped = ep->stopped;
+
+ DEBUG_PD12("%s, %p\n", __FUNCTION__, ep);
+ list_del_init(&req->queue);
+
+ if (req->req.status == -EINPROGRESS)
+ req->req.status = status;
+ else
+ status = req->req.status;
+
+ if (status && status != -ESHUTDOWN)
+ DEBUG_PD12("complete %s req %p stat %d len %u/%u\n",
+ ep->ep.name, &req->req, status,
+ req->req.actual, req->req.length);
+
+ /* don't modify queue heads during completion callback */
+ ep->stopped = 1;
+
+ spin_unlock(&ep->dev->lock);
+ req->req.complete(&ep->ep, &req->req);
+ spin_lock(&ep->dev->lock);
+ ep->stopped = stopped;
+}
+
+
+/*
+ * nuke - dequeue ALL requests
+ */
+void nuke(struct pd12_ep *ep, int status)
+{
+ struct pd12_request *req;
+
+ DEBUG_PD12("%s, %p\n", __FUNCTION__, ep);
+
+ /* Flush FIFO */
+ flush(ep);
+
+ /* called with irqs blocked */
+ while (!list_empty(&ep->queue)) {
+ req = list_entry(ep->queue.next, struct pd12_request, queue);
+ done(ep, req, status);
+ }
+
+}
+
+/** Flush EP
+ * NOTE: INDEX register must be set before this call
+ */
+static void flush(struct pd12_ep *ep)
+{
+}
+
+/**
+ * handle IN interrupt
+ */
+static void pd12_in_epn(struct pd12_udc *dev, u8 ep_idx)
+{
+ u8 ep_sts;
+ struct pd12_ep *ep = &dev->ep[ep_idx];
+ struct pd12_request *req;
+
+ usb_set_index(ep_idx);
+ read_data(&ep_sts);
+ DEBUG_PD12("%s: %d, status %x\n", __FUNCTION__, ep_idx, ep_sts);
+
+ if (ep_sts & UDC_EP_STALL) {
+ DEBUG_PD12("USB_EP_STALL\n");
+ return;
+ }
+
+ if (!ep->desc) {
+ DEBUG_PD12("%s: NO EP DESC\n", __FUNCTION__);
+ return;
+ }
+
+ if (list_empty(&ep->queue))
+ req = 0;
+ else
+ req = list_entry(ep->queue.next, struct pd12_request, queue);
+
+ DEBUG_PD12("req: %p\n", req);
+
+ if (!req)
+ return;
+
+ write_fifo(ep, req);
+}
+
+/*
+* handle OUT interrupt(recv)
+ */
+
+static void pd12_out_epn(struct pd12_udc *dev, u8 ep_idx)
+{
+ u8 ep_sts;
+ struct pd12_ep *ep = &dev->ep[ep_idx];
+ struct pd12_request *req;
+
+ DEBUG_PD12("%s: %d\n", __FUNCTION__, ep_idx);
+
+ usb_set_index(ep_idx);
+ read_data(&ep_sts);
+ DEBUG_PD12("%s: %d, status %x\n", __FUNCTION__, ep_idx, ep_sts);
+
+ if (ep_sts & UDC_EP_STALL) {
+ DEBUG_PD12("USB_EP_STALL\n");
+ flush(ep);
+ return;
+ }
+
+ if (ep->desc) {
+
+ if (list_empty(&ep->queue))
+ req = 0;
+ else
+ req = list_entry(ep->queue.next,
+ struct pd12_request,
+ queue);
+
+ if (!req) {
+ printk("%s: NULL REQ %d\n",
+ __FUNCTION__, ep_idx);
+ flush(ep);
+ } else {
+ read_fifo(ep, req);
+ }
+
+ } else {
+ /* Throw packet away.. */
+ printk("%s: No descriptor?!?\n", __FUNCTION__);
+ flush(ep);
+ }
+}
+
+static void stop_activity(struct pd12_udc *dev,
+ struct usb_gadget_driver *driver)
+{
+ int i;
+
+ /* don't disconnect drivers more than once */
+ if (dev->gadget.speed == USB_SPEED_UNKNOWN)
+ driver = 0;
+ dev->gadget.speed = USB_SPEED_UNKNOWN;
+
+ /* prevent new request submissions, kill any outstanding requests */
+ for (i = 0; i < PD12_MAX_ENDPOINTS - 1; i++) {
+ struct pd12_ep *ep = &dev->ep[i];
+ ep->stopped = 1;
+
+ usb_set_index(i);
+ write_cmd(PD12_SET_STATUS);
+ write_data(0x1);
+ nuke(ep, -ESHUTDOWN);
+ }
+
+ write_cmd(1);
+ write_cmd(PD12_SET_STATUS);
+ write_data(0x1);
+
+ /* report disconnect; the driver is already quiesced */
+ if (driver) {
+ spin_unlock(&dev->lock);
+ driver->disconnect(&dev->gadget);
+ spin_lock(&dev->lock);
+ }
+
+ /* re-init driver-visible data structures */
+ udc_reinit(dev);
+}
+
+/** Handle USB RESET interrupt
+ */
+static void pd12_reset_intr(struct pd12_udc *dev)
+{
+
+ struct pd12_request *req;
+ struct pd12_ep *ep = &dev->ep[0];
+
+ DEBUG_PD12_EP0("%s: \n", __FUNCTION__);
+
+ if (list_empty(&ep->queue))
+ req = 0;
+ else
+ req = list_entry(ep->queue.next, struct pd12_request, queue);
+
+ if (req){
+ done(ep,req,0);
+ } else {
+ DEBUG_PD12_EP0("%s: NULL REQ\n", __FUNCTION__);
+ }
+
+ udc_set_address(dev, 0);
+ pd12_set_ack(0);
+ pd12_set_ack(1);
+ dev->ep0state = WAIT_FOR_SETUP;
+ first_tran = 1;
+}
+
+/*
+ * pd12 usb client interrupt handler.
+ */
+static irqreturn_t pd12_udc_irq(int irq, void *_dev, struct pt_regs *r)
+{
+ struct pd12_udc *dev = _dev;
+ volatile u8 int_status;
+ unsigned long flags;
+
+ spin_lock_irqsave(&dev->lock,flags);
+
+ DEBUG_PD12("%s (on state %s)\n", __FUNCTION__,
+ state_names[dev->ep0state]);
+ write_cmd(PD12_READ_INT);
+ read_data(&int_status);
+ if (int_status & (PD12_CNTL_IN | PD12_CNTL_OUT))
+ {
+ if((int_status & PD12_CNTL_OUT) == PD12_CNTL_OUT)
+ dev->ep0state = WAIT_FOR_SETUP;
+ int_status &= ~(PD12_CNTL_IN | PD12_CNTL_OUT);
+ DEBUG_PD12("PD12_EP0 (control)\n");
+ pd12_handle_ep0(dev);
+
+ }
+ if (int_status & PD12_SUSPEND_CHG)
+ {
+ u8 tmp;
+ tmp = *(volatile char *)CPLD_REG0_ADDR;
+ int_status &= ~PD12_SUSPEND_CHG;
+ if(tmp & USB_SUSPEND)
+ {
+ /* write_cmd(PD12_SND_RESUME); */
+ if (dev->gadget.speed != USB_SPEED_UNKNOWN
+ && dev->driver
+ && dev->driver->resume)
+ dev->driver->resume(&dev->gadget);
+ }
+ else
+ {
+ if (dev->gadget.speed !=
+ USB_SPEED_FULL && dev->driver
+ && dev->driver->suspend)
+ dev->driver->suspend(&dev->gadget);
+ }
+ }
+ if (int_status & PD12_BUS_RST)
+ {
+ int_status &= ~PD12_BUS_RST;
+ pd12_reset_intr(dev);
+ }
+ if (int_status & PD12_EP1_IN)
+ {
+ int_status &= ~PD12_EP1_IN;
+ DEBUG_PD12("PD12_EP1_IN\n");
+ pd12_in_epn(dev, 2);
+ }
+ if (int_status & PD12_MAIN_IN)
+ {
+ int_status &= ~PD12_MAIN_IN;
+ DEBUG_PD12("PD12_MAIN_IN\n");
+ pd12_in_epn(dev, 4);
+ }
+ if (int_status & PD12_EP1_OUT)
+ {
+ int_status &= ~PD12_EP1_OUT;
+ DEBUG_PD12("PD12_EP1_OUT\n");
+ pd12_out_epn(dev, 1);
+ }
+ if (int_status & PD12_MAIN_OUT)
+ {
+ int_status &= ~PD12_MAIN_OUT;
+ DEBUG_PD12("PD12_MAIN_OUT\n");
+ pd12_out_epn(dev, 3);
+ }
+
+ spin_unlock_irqrestore(&dev->lock,flags);
+ return IRQ_HANDLED;
+}
+
+static int pd12_ep_enable(struct usb_ep *_ep,
+ const struct usb_endpoint_descriptor *desc)
+{
+ struct pd12_ep *ep;
+ struct pd12_udc *dev;
+ unsigned long flags;
+
+ DEBUG_PD12("%s, %p\n", __FUNCTION__, _ep);
+
+ ep = container_of(_ep, struct pd12_ep, ep);
+ if (!_ep || !desc || ep->desc || _ep->name == ep0name
+ || desc->bDescriptorType != USB_DT_ENDPOINT
+ || ep->bEndpointAddress != desc->bEndpointAddress
+ || ep_maxpacket(ep) < le16_to_cpu(desc->wMaxPacketSize)) {
+ DEBUG_PD12("%s, bad ep or descriptor\n", __FUNCTION__);
+ return -EINVAL;
+ }
+
+ /* xfer types must match, except that interrupt ~= bulk */
+ if (ep->bmAttributes != desc->bmAttributes ) {
+ DEBUG_PD12("%s, %s type mismatch\n", __FUNCTION__, _ep->name);
+ return -EINVAL;
+ }
+
+ /* hardware _could_ do smaller, but driver doesn't */
+ if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK
+ && le16_to_cpu(desc->wMaxPacketSize) != ep_maxpacket(ep))
+ || !desc->wMaxPacketSize) {
+ DEBUG_PD12("%s, bad %s maxpacket\n", __FUNCTION__, _ep->name);
+ return -ERANGE;
+ }
+
+ dev = ep->dev;
+ if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN) {
+ DEBUG_PD12("%s, bogus device state\n", __FUNCTION__);
+ return -ESHUTDOWN;
+ }
+
+ spin_lock_irqsave(&ep->dev->lock, flags);
+
+ ep->stopped = 0;
+ ep->desc = desc;
+ ep->ep.maxpacket = le16_to_cpu(desc->wMaxPacketSize);
+
+ /* Reset halt state (does flush) */
+ pd12_set_halt(_ep, 0);
+
+ spin_unlock_irqrestore(&ep->dev->lock, flags);
+
+ DEBUG_PD12("%s: enabled %s\n", __FUNCTION__, _ep->name);
+ return 0;
+}
+
+/** Disable EP
+ * NOTE: Sets INDEX register
+ */
+static int pd12_ep_disable(struct usb_ep *_ep)
+{
+ struct pd12_ep *ep;
+ unsigned long flags;
+
+ DEBUG_PD12("%s, %p\n", __FUNCTION__, _ep);
+
+ ep = container_of(_ep, struct pd12_ep, ep);
+ if (!_ep || !ep->desc) {
+ DEBUG_PD12("%s, %s not enabled\n", __FUNCTION__,
+ _ep ? ep->ep.name : NULL);
+ return -EINVAL;
+ }
+
+ spin_lock_irqsave(&ep->dev->lock, flags);
+
+ usb_set_index(ep_index(ep));
+
+ /* Nuke all pending requests (does flush) */
+ nuke(ep, -ESHUTDOWN);
+
+ /* Disable ep */
+ write_cmd(PD12_SET_EP_EN);
+ write_data(0x0);
+
+ ep->desc = 0;
+ ep->stopped = 1;
+
+ spin_unlock_irqrestore(&ep->dev->lock, flags);
+
+ DEBUG_PD12("%s: disabled %s\n", __FUNCTION__, _ep->name);
+ return 0;
+}
+
+static struct usb_request *pd12_alloc_request(struct usb_ep *ep,
+ unsigned gfp_flags)
+{
+ struct pd12_request *req;
+
+ DEBUG_PD12("%s, %p\n", __FUNCTION__, ep);
+
+ req = kmalloc(sizeof *req, gfp_flags);
+ if (!req)
+ return 0;
+
+ memset(req, 0, sizeof *req);
+ INIT_LIST_HEAD(&req->queue);
+
+ return &req->req;
+}
+
+static void pd12_free_request(struct usb_ep *ep, struct usb_request *_req)
+{
+ struct pd12_request *req;
+
+ DEBUG_PD12("%s, %p\n", __FUNCTION__, ep);
+
+ req = container_of(_req, struct pd12_request, req);
+ WARN_ON(!list_empty(&req->queue));
+ kfree(req);
+}
+
+static void *pd12_alloc_buffer(struct usb_ep *ep, unsigned bytes,
+ dma_addr_t * dma, unsigned gfp_flags)
+{
+ char *retval;
+
+ DEBUG_PD12("%s (%p, %d, %d)\n", __FUNCTION__, ep, bytes, gfp_flags);
+
+ retval = kmalloc(bytes, gfp_flags & ~(__GFP_DMA | __GFP_HIGHMEM));
+ if (retval)
+ *dma = virt_to_bus(retval);
+ return retval;
+}
+
+static void pd12_free_buffer(struct usb_ep *ep, void *buf, dma_addr_t dma,
+ unsigned bytes)
+{
+ DEBUG_PD12("%s, %p\n", __FUNCTION__, ep);
+ kfree(buf);
+}
+
+/** Queue one request
+ * Kickstart transfer if needed
+ * NOTE: Sets INDEX register
+ */
+static int pd12_queue(struct usb_ep *_ep, struct usb_request *_req,
+ unsigned gfp_flags)
+{
+ struct pd12_request *req;
+ struct pd12_ep *ep;
+ struct pd12_udc *dev;
+ unsigned long flags;
+ u8 ep_status;
+
+ DEBUG_PD12("\n\n\n%s, %p\n", __FUNCTION__, _ep);
+
+ req = container_of(_req, struct pd12_request, req);
+ if (!_req || !_req->complete || !_req->buf
+ || !list_empty(&req->queue)) {
+ DEBUG_PD12("%s, bad params\n", __FUNCTION__);
+ return -EINVAL;
+ }
+
+ ep = container_of(_ep, struct pd12_ep, ep);
+ if (!_ep || (!ep->desc && (ep->ep.name != ep0name))) {
+ DEBUG_PD12("%s, bad ep\n", __FUNCTION__);
+ return -EINVAL;
+ }
+
+ dev = ep->dev;
+ if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN) {
+ DEBUG_PD12("%s, bogus device state %p\n", __FUNCTION__, dev->driver);
+ return -ESHUTDOWN;
+ }
+
+ DEBUG_PD12("%s queue req %p, len %d buf %p\n", _ep->name, _req, _req->length,
+ _req->buf);
+
+ spin_lock_irqsave(&dev->lock, flags);
+
+ _req->status = -EINPROGRESS;
+ _req->actual = 0;
+
+ /* kickstart this i/o queue? */
+ DEBUG_PD12("Add to %d Q %d %d\n", ep_index(ep), list_empty(&ep->queue),
+ ep->stopped);
+ if (list_empty(&ep->queue) && !ep->stopped) {
+
+ if (ep_index(ep) == 0) {
+ /* EP0 */
+ list_add_tail(&req->queue, &ep->queue);
+ pd12_ep0_kick(dev, ep);
+ req = 0;
+ } else if (ep_is_in(ep)) {
+ /* EP2 & EP4 */
+ usb_set_index(ep_index(ep));
+ read_data(&ep_status);
+ if ((ep_status & 0x0) == 0x0) {
+ if (write_fifo(ep, req) == 1)
+ req = 0;
+ }
+ } else {
+ /* EP1 & EP3 */
+ usb_set_index(ep_index(ep));
+ read_data(&ep_status);
+ if ((ep_status & 0x01) == 0x01) {
+ if (read_fifo(ep, req) == 1)
+ req = 0;
+ }
+ }
+ }
+
+ /* pio or dma irq handler advances the queue. */
+ if (req != 0)
+ list_add_tail(&req->queue, &ep->queue);
+
+ spin_unlock_irqrestore(&dev->lock, flags);
+
+ return 0;
+}
+
+/* dequeue JUST ONE request */
+static int pd12_dequeue(struct usb_ep *_ep, struct usb_request *_req)
+{
+ struct pd12_ep *ep;
+ struct pd12_request *req;
+ unsigned long flags;
+
+ DEBUG_PD12("%s, %p\n", __FUNCTION__, _ep);
+
+ ep = container_of(_ep, struct pd12_ep, ep);
+ if (!_ep || ep->ep.name == ep0name )
+ return -EINVAL;
+
+ spin_lock_irqsave(&ep->dev->lock, flags);
+
+ /* make sure it's actually queued on this endpoint */
+ list_for_each_entry(req, &ep->queue, queue) {
+ if (&req->req == _req)
+ break;
+ }
+ if (&req->req != _req) {
+ spin_unlock_irqrestore(&ep->dev->lock, flags);
+ return -EINVAL;
+ }
+
+ done(ep, req, -ECONNRESET);
+
+ spin_unlock_irqrestore(&ep->dev->lock, flags);
+ return 0;
+}
+
+/** Halt specific EP
+ * Return 0 if success
+ * NOTE: Sets INDEX register to EP !
+ */
+static int pd12_set_halt(struct usb_ep *_ep, int value)
+{
+ struct pd12_ep *ep;
+ unsigned long flags;
+ u8 ep_status;
+
+ ep = container_of(_ep, struct pd12_ep, ep);
+ if (!_ep || (!ep->desc && ep->ep.name != ep0name)) {
+ DEBUG_PD12("%s, bad ep\n", __FUNCTION__);
+ return -EINVAL;
+ }
+
+ usb_set_index(ep_index(ep));
+
+ DEBUG_PD12("%s, ep %d, val %d\n", __FUNCTION__, ep_index(ep), value);
+
+ spin_lock_irqsave(&ep->dev->lock, flags);
+
+ if (ep_index(ep) == 0) {
+ /* EP0 */
+ write_cmd(PD12_SET_STATUS | ep_index(ep));
+ write_data(0x01);
+ } else if (ep_is_in(ep)) {
+ write_cmd(PD12_READ_EP_STATUS);
+ read_data(&ep_status);
+ if (value && ((ep_status & 0x60) /*buffer 0 or 1 full*/
+ || !list_empty(&ep->queue))) {
+ /*
+ * Attempts to halt IN endpoints will fail (returning -EAGAIN)
+ * if any transfer requests are still queued, or if the controller
+ * FIFO still holds bytes that the host hasn't collected.
+ */
+ spin_unlock_irqrestore(&ep->dev->lock, flags);
+ DEBUG_PD12
+ ("Attempt to halt IN endpoint failed (returning -EAGAIN) %d %d\n",
+ (ep_status & 0x60),
+ !list_empty(&ep->queue));
+ return -EAGAIN;
+ }
+ flush(ep);
+ if (value)
+ {
+ write_cmd(PD12_SET_STATUS | ep_index(ep));
+ write_data(0x01);
+ } else {
+ write_cmd(PD12_SET_STATUS | ep_index(ep));
+ write_data(0x00);
+ }
+
+ } else {
+
+ flush(ep);
+ if (value)
+ {
+ write_cmd(PD12_SET_STATUS | ep_index(ep));
+ write_data(0x01);
+ } else {
+ write_cmd(PD12_SET_STATUS | ep_index(ep));
+ write_data(0x00);
+ }
+ }
+
+ if (value) {
+ ep->stopped = 1;
+ } else {
+ ep->stopped = 0;
+ }
+
+ spin_unlock_irqrestore(&ep->dev->lock, flags);
+
+ DEBUG_PD12("%s %s halted\n", _ep->name, value == 0 ? "NOT" : "IS");
+
+ return 0;
+}
+
+
+/****************************************************************/
+/* End Point 0 related functions */
+/****************************************************************/
+
+/* return: 0 = still running, 1 = completed, negative = errno */
+static int write_fifo_ep0(struct pd12_ep *ep, struct pd12_request *req)
+{
+ u8 max;
+ unsigned count;
+ int is_last;
+ unsigned length;
+ u8* buf;
+ u8 ep_sts;
+
+ write_cmd(1); /* index 1*/
+ read_data(&ep_sts);
+/* pd12_set_ack(1); */
+ max = ep_maxpacket(ep);
+ buf = req->req.buf + req->req.actual;
+ prefetch(buf);
+
+ DEBUG_PD12_EP0("%s\n", __FUNCTION__);
+
+ length = req->req.length - req->req.actual;
+ length = min(length, (unsigned)max);
+ req->req.actual += length;
+
+ DEBUG_PD12("Write %d (max %d), fifo %p\n", length, max, buf);
+
+ count = length;
+ write_cmd(PD12_WRITE_BUF);
+ write_data(0x0);
+ write_data(count);
+ while (length--) {
+ write_data(*buf++);
+ }
+
+ write_cmd(PD12_VALIDATE_BUF);
+ /* last packet is usually short (or a zlp) */
+ if (unlikely(count != max))
+ is_last = 1;
+ else {
+ if (likely(req->req.length != req->req.actual) || req->req.zero)
+ is_last = 0;
+ else
+ is_last = 1;
+ }
+
+ DEBUG_PD12_EP0("%s: wrote %s %d bytes%s %d left %p\n", __FUNCTION__,
+ ep->ep.name, count,
+ is_last ? "/L" : "", req->req.length - req->req.actual, req);
+
+ /* requests complete when all IN data is in the FIFO */
+ if (is_last) {
+ done(ep, req, 0);
+ return 1;
+ }
+
+ return 0;
+}
+
+static __inline__ void pd12_fifo_read(struct pd12_ep *ep,
+ unsigned char *cp, u8 max)
+{
+ u8 count;
+
+ usb_set_index(0);
+ write_cmd(PD12_READ_BUF);
+ read_data(&count);
+ read_data(&count);
+ if (count > max)
+ count = max;
+ while (count--){
+ read_data(cp++);
+ }
+ write_cmd(PD12_CLEAR_BUF);
+}
+
+static __inline__ void pd12_fifo_write(struct pd12_ep *ep,
+ unsigned char *cp, u8 count)
+{
+ write_cmd(1); /* index 1 */
+ write_cmd(PD12_WRITE_BUF);
+ write_data(0x0);
+ write_data(count);
+ DEBUG_PD12_EP0("fifo_write: %d %d\n", ep_index(ep), count);
+ while (count--)
+ write_data(*cp++);
+ write_cmd(PD12_VALIDATE_BUF);
+}
+static int read_fifo_ep0(struct pd12_ep *ep, struct pd12_request *req)
+{
+ u8 ep_status;
+ u8 len;
+ u8 *buf;
+ unsigned bufferspace, count, is_short;
+
+ DEBUG_PD12_EP0("%s\n", __FUNCTION__);
+
+ usb_set_index(0); /* index 0*/
+ read_data(&ep_status);
+ if ((ep_status & UDC_FIFO_UNREADABLE) == UDC_FIFO_UNREADABLE)
+ return 0;
+
+ buf = req->req.buf + req->req.actual;
+ prefetchw(buf);
+ bufferspace = req->req.length - req->req.actual;
+
+ write_cmd(PD12_READ_BUF);
+ read_data(&len);
+ read_data(&len);
+ count = (unsigned)len;
+
+ is_short = (count < ep->ep.maxpacket);
+ DEBUG_PD12_EP0("read %s, %d bytes%s req %p %d/%d\n",
+ ep->ep.name, count,
+ is_short ? "/S" : "", req, req->req.actual, req->req.length);
+
+ while (count--) {
+ u8 byte;
+ read_data(&byte);
+ if (unlikely(bufferspace == 0)) {
+ /* this happens when the driver's buffer
+ * is smaller than what the host sent.
+ * discard the extra data.
+ */
+ if (req->req.status != -EOVERFLOW)
+ DEBUG_PD12_EP0("%s overflow %d\n", ep->ep.name,
+ count);
+ req->req.status = -EOVERFLOW;
+ } else {
+ *buf++ = byte;
+ bufferspace--;
+ }
+ }
+
+ /* completion */
+ if (is_short || req->req.actual == req->req.length) {
+ done(ep, req, 0);
+ return 1;
+ }
+
+ /* finished that packet. the next one may be waiting... */
+ return 0;
+}
+
+/**
+ * udc_set_address - set the USB address for this device
+ * @address:
+ *
+ * Called from control endpoint function after it decodes a set address setup packet.
+ */
+static void udc_set_address(struct pd12_udc *dev, unsigned char address)
+{
+ DEBUG_PD12_EP0("%s: %d\n", __FUNCTION__, address);
+
+ dev->usb_address = address;
+ write_cmd(PD12_SET_ADDR_EN);
+ write_data(0x80 | address);
+}
+
+/*
+ * DATA_STATE_RECV (OUT_PKT_RDY)
+ * - if error
+ * set EP0_CLR_OUT | EP0_DATA_END | EP0_SEND_STALL bits
+ * - else
+ * set EP0_CLR_OUT bit
+ if last set EP0_DATA_END bit
+ */
+static void pd12_ep0_out(struct pd12_udc *dev)
+{
+ struct pd12_request *req;
+ struct pd12_ep *ep = &dev->ep[0];
+ int ret;
+
+ DEBUG_PD12_EP0("%s: \n", __FUNCTION__);
+
+ if (list_empty(&ep->queue))
+ req = 0;
+ else
+ req = list_entry(ep->queue.next, struct pd12_request, queue);
+
+ if (req) {
+
+ if (req->req.length == 0) {
+ DEBUG_PD12_EP0("ZERO LENGTH OUT!\n");
+ dev->ep0state = WAIT_FOR_SETUP;
+ return;
+ }
+ ret = read_fifo_ep0(ep, req);
+ if (ret) {
+ /* Done! */
+ DEBUG_PD12_EP0("%s: finished, waiting for status\n",
+ __FUNCTION__);
+ /* read last status here ?*/
+ dev->ep0state = WAIT_FOR_SETUP;
+ } else {
+ /* Not done yet.. */
+ DEBUG_PD12_EP0("%s: not finished\n", __FUNCTION__);
+ /* usb_set(EP0_CLR_OUT, USB_EP0_CSR); */
+ }
+ } else {
+ DEBUG_PD12_EP0("NO REQ??!\n");
+ }
+}
+
+/*
+ * DATA_STATE_XMIT
+ */
+static int pd12_ep0_in(struct pd12_udc *dev)
+{
+ struct pd12_request *req;
+ struct pd12_ep *ep = &dev->ep[0];
+ int ret, need_zlp = 0;
+ u8 val;
+
+ DEBUG_PD12_EP0("%s: \n", __FUNCTION__);
+
+
+ pd12_read_lstatus(1,&val);
+ pd12_set_ack(1);
+ if(((val & 0x1) != 0x1) && !first_tran){
+ /* printk("return from ep0_in\n"); */
+ return 0;
+ }
+ if (list_empty(&ep->queue))
+ req = 0;
+ else
+ req = list_entry(ep->queue.next, struct pd12_request, queue);
+
+ if (!req) {
+ dev->ep0state = WAIT_FOR_SETUP;
+ DEBUG_PD12_EP0("%s: NULL REQ\n", __FUNCTION__);
+ return 0;
+ }
+
+ if (req->req.length == 0) {
+ dev->ep0state = WAIT_FOR_SETUP;
+ return 1;
+ }
+
+ ret = write_fifo_ep0(ep, req);
+ first_tran = 0;
+ if (ret == 1 && !need_zlp) {
+ /* Last packet */
+ DEBUG_PD12_EP0("%s: finished, waiting for status\n", __FUNCTION__);
+ dev->ep0state = WAIT_FOR_SETUP;
+ } else {
+ DEBUG_PD12_EP0("%s: not finished\n", __FUNCTION__);
+ }
+
+ return 1;
+}
+
+static int pd12_handle_get_status(struct pd12_udc *dev,
+ struct usb_ctrlrequest *ctrl)
+{
+ struct pd12_ep *ep0 = &dev->ep[0];
+ struct pd12_ep *qep;
+ int reqtype = (ctrl->bRequestType & USB_RECIP_MASK);
+ u16 val = 0;
+ u8 ep_sts;
+
+ if (reqtype == USB_RECIP_INTERFACE) {
+ /* This is not supported.
+ * And according to the USB spec, this one does nothing..
+ * Just return 0
+ */
+ DEBUG_PD12_SETUP("GET_STATUS: USB_RECIP_INTERFACE\n");
+ } else if (reqtype == USB_RECIP_DEVICE) {
+ DEBUG_PD12_SETUP("GET_STATUS: USB_RECIP_DEVICE\n");
+ val |= (1 << 0); /* Self powered */
+ /*val |= (1<<1); */ /* Remote wakeup */
+ } else if (reqtype == USB_RECIP_ENDPOINT) {
+ int ep_num = (ctrl->wIndex & ~USB_DIR_IN);
+
+ DEBUG_PD12_SETUP
+ ("GET_STATUS: USB_RECIP_ENDPOINT (%d), ctrl->wLength = %d\n",
+ ep_num, ctrl->wLength);
+
+ if (ctrl->wLength > 2 || ep_num > 3) /* ep_num cannt abouve maxenpoint?*/
+ return -EOPNOTSUPP;
+
+ qep = &dev->ep[ep_num];
+ if (ep_is_in(qep) != ((ctrl->wIndex & USB_DIR_IN) ? 1 : 0)
+ && ep_index(qep) != 0) {
+ return -EOPNOTSUPP;
+ }
+
+ usb_set_index(ep_index(qep));
+ read_data(&ep_sts);
+ val = (u16)ep_sts;
+
+ /* Back to EP0 index */
+ usb_set_index(0);
+
+ DEBUG_PD12_SETUP("GET_STATUS, ep: %d (%x), val = %d\n", ep_num,
+ ctrl->wIndex, val);
+ } else {
+ DEBUG_PD12_SETUP("Unknown REQ TYPE: %d\n", reqtype);
+ return -EOPNOTSUPP;
+ }
+
+ /* Put status to FIFO */
+ pd12_fifo_write(ep0, (u8 *) & val, sizeof(val));
+
+ return 0;
+}
+
+/*
+ * WAIT_FOR_SETUP
+ * - read data packet from EP0 FIFO
+ * - decode command
+ * - if error
+ * set EP0_CLR_OUT | EP0_DATA_END | EP0_SEND_STALL bits
+ * - else
+ * set EP0_CLR_OUT | EP0_DATA_END bits
+ */
+static void pd12_ep0_setup(struct pd12_udc *dev)
+{
+ struct pd12_ep *ep = &dev->ep[0];
+ struct usb_ctrlrequest ctrl;
+ int i;
+ u8 stat;
+ u8 inbuf[16];
+
+ DEBUG_PD12_SETUP("%s: \n", __FUNCTION__);
+
+ /* Nuke all previous transfers */
+ nuke(ep, -EPROTO);
+ pd12_read_lstatus(0,&stat);
+ pd12_set_ack(0);
+ pd12_set_ack(1);
+ if((stat & 0x01) != 0x01){
+ return ;
+ }
+ pd12_fifo_read(ep, (u8 *)&ctrl, 8);
+
+ DEBUG_PD12_SETUP("CTRL.bRequestType = 0x%x (is_in 0x%x)\n", ctrl.bRequestType,
+ ctrl.bRequestType == USB_DIR_IN);
+ DEBUG_PD12_SETUP("CTRL.bRequest = 0x%x\n", ctrl.bRequest);
+ DEBUG_PD12_SETUP("CTRL.wLength = 0x%x\n", ctrl.wLength);
+ DEBUG_PD12_SETUP("CTRL.wValue = 0x%x (%d)\n", ctrl.wValue, ctrl.wValue >> 8);
+ DEBUG_PD12_SETUP("CTRL.wIndex = 0x%x\n", ctrl.wIndex);
+
+ /* Set direction of EP0 */
+ if (ctrl.bRequestType & USB_DIR_IN) {
+ ep->bEndpointAddress |= USB_DIR_IN;
+ } else {
+ ep->bEndpointAddress &= ~USB_DIR_IN;
+ }
+
+
+ /* Handle some SETUP packets ourselves */
+ switch (ctrl.bRequest) {
+ case USB_REQ_SET_ADDRESS:
+ if (ctrl.bRequestType != (USB_TYPE_STANDARD | USB_RECIP_DEVICE))
+ break;
+
+ DEBUG_PD12_SETUP("USB_REQ_SET_ADDRESS (%d)\n", ctrl.wValue);
+ udc_set_address(dev, le16_to_cpu(ctrl.wValue));
+ pd12_fifo_write(ep,inbuf,0);
+ return;
+
+ case USB_REQ_GET_STATUS:{
+ if (pd12_handle_get_status(dev, &ctrl) == 0)
+ return;
+
+ case USB_REQ_CLEAR_FEATURE:
+ case USB_REQ_SET_FEATURE:
+ if (ctrl.bRequestType == USB_RECIP_ENDPOINT) {
+ struct pd12_ep *qep;
+ int ep_num = (ctrl.wIndex & 0x0f);
+
+ /* Support only HALT feature */
+ if (ctrl.wValue != 0 || ctrl.wLength != 0
+ || ep_num > 4 || ep_num < 1)
+ break;
+
+ qep = &dev->ep[ep_num];
+ if (ctrl.bRequest == USB_REQ_SET_FEATURE) {
+ DEBUG_PD12_SETUP("SET_FEATURE (%d)\n",
+ ep_num);
+ pd12_set_halt(&qep->ep, 1);
+ } else {
+ DEBUG_PD12_SETUP("CLR_FEATURE (%d)\n",
+ ep_num);
+ pd12_set_halt(&qep->ep, 0);
+ }
+ usb_set_index(0);
+
+ return;
+ }
+ break;
+ }
+
+ default:
+ break;
+ }
+
+ if (dev->driver) {
+ /* device-2-host (IN) or no data setup command, process immediately */
+ spin_unlock(&dev->lock);
+ i = dev->driver->setup(&dev->gadget, &ctrl);
+ spin_lock(&dev->lock);
+
+ if (i < 0) {
+ pd12_ep0_in(dev);
+ /* setup processing failed, force stall */
+ DEBUG_PD12_SETUP
+ (" --> ERROR: gadget setup FAILED (stalling), setup returned %d\n",
+ i);
+ /* usb_set_index(0); */
+ write_cmd(PD12_SET_STATUS);
+ write_data(0x1);
+ write_cmd(PD12_SET_STATUS + 0x1);
+ write_data(0x1);
+ /* ep->stopped = 1; */
+ dev->ep0state = WAIT_FOR_SETUP;
+ }
+ }
+}
+
+/*
+ * handle ep0 in interrupt
+ */
+static void pd12_handle_ep0(struct pd12_udc *dev)
+{
+ struct pd12_ep *ep = &dev->ep[0];
+ u8 ep0in_sts,ep0out_sts/*,int_sts*/;
+
+ /* Set index 0 */
+ write_cmd(0x0);
+ read_data(&ep0out_sts);
+
+ write_cmd(0x1);
+ read_data(&ep0in_sts);
+
+
+ /*
+ * if STALL is set, clear STALL bit
+ */
+ if (ep0out_sts & UDC_EP_STALL ) {
+/* DEBUG_PD12_EP0("%s: EP0_SENT_STALL is set: %x\n", __FUNCTION__, status); */
+ write_cmd(PD12_SET_STATUS);
+ write_data(0x0);
+ nuke(ep, -ECONNABORTED);
+ dev->ep0state = WAIT_FOR_SETUP;
+ return;
+ }
+
+ if (ep0in_sts & UDC_EP_STALL ) {
+/* DEBUG_PD12_EP0("%s: EP0_SENT_STALL is set: %x\n", __FUNCTION__, status); */
+ write_cmd(PD12_SET_STATUS + 0x1);
+ write_data(0x0);
+ nuke(ep, -ECONNABORTED);
+ dev->ep0state = WAIT_FOR_SETUP;
+ return;
+ }
+
+ switch (dev->ep0state) {
+ case WAIT_FOR_SETUP:
+ DEBUG_PD12_EP0("WAIT_FOR_SETUP\n");
+ pd12_ep0_setup(dev);
+ break;
+ case DATA_STATE_RECV:
+ DEBUG_PD12_EP0("DATA_STATE_RECV\n");
+ pd12_ep0_out(dev);
+ break;
+ case DATA_STATE_XMIT:
+ DEBUG_PD12_EP0("continue with DATA_STATE_XMIT\n");
+ pd12_ep0_in(dev);
+ return;
+ default:
+ /* Stall? */
+ DEBUG_PD12_EP0("Odd state!! state = %s\n",
+ state_names[dev->ep0state]);
+ dev->ep0state = WAIT_FOR_SETUP;
+ /* nuke(ep, 0); */
+ /* usb_set(EP0_SEND_STALL, ep->csr1); */
+ break;
+ }
+
+}
+
+static void pd12_ep0_kick(struct pd12_udc *dev, struct pd12_ep *ep)
+{
+
+ if (ep_is_in(ep)) {
+ dev->ep0state = DATA_STATE_XMIT;
+ pd12_ep0_in(dev);
+ } else {
+ dev->ep0state = DATA_STATE_RECV;
+ pd12_ep0_out(dev);
+ }
+}
+
+/* ---------------------------------------------------------------------------
+ * device-scoped parts of the api to the usb controller hardware
+ * ---------------------------------------------------------------------------
+ */
+
+static int pd12_udc_get_frame(struct usb_gadget *_gadget)
+{
+ u16 frame1,frame2;
+ write_cmd(PD12_RD_CUR_FRAME_NUM);
+ read_data((u8 *)&frame1);/* Least significant 8 bits */
+ read_data((u8 *)&frame2);/* Most significant 3 bits */
+ DEBUG_PD12("%s, %p\n", __FUNCTION__, _gadget);
+ return ((frame2 & 0x07) << 8) | (frame1 & 0xff);
+}
+
+static int pd12_udc_wakeup(struct usb_gadget *_gadget)
+{
+ /* host may not have enabled remote wakeup */
+ /*if ((UDCCS0 & UDCCS0_DRWF) == 0)
+ return -EHOSTUNREACH;
+ udc_set_mask_UDCCR(UDCCR_RSM); */
+ return -ENOTSUPP;
+}
+
+static const struct usb_gadget_ops pd12_udc_ops = {
+ .get_frame = pd12_udc_get_frame,
+ .wakeup = pd12_udc_wakeup,
+ /* current versions must always be self-powered */
+};
+
+static void nop_release(struct device *dev)
+{
+ DEBUG_PD12("%s %s\n", __FUNCTION__, dev->bus_id);
+}
+
+static struct pd12_udc usb_memory = {
+ .usb_address = 0,
+
+ .gadget = {
+ .ops = &pd12_udc_ops,
+ .ep0 = &usb_memory.ep[0].ep,
+ .name = driver_name,
+ .dev = {
+ .bus_id = "gadget",
+ .release = nop_release,
+ },
+ },
+
+ /* control endpoint */
+ .ep[0] = {
+ .ep = {
+ .name = ep0name,
+ .ops = &pd12_ep_ops,
+ .maxpacket = 16,
+ },
+ .dev = &usb_memory,
+
+ .bEndpointAddress = 0,
+ .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
+ },
+
+ /* first group of endpoints */
+ .ep[1] = {
+ .ep = {
+ .name = "ep1out-bulk",
+ .ops = &pd12_ep_ops,
+ .maxpacket = 16,
+ },
+ .dev = &usb_memory,
+
+ .bEndpointAddress = 1,
+ .bmAttributes = USB_ENDPOINT_XFER_BULK,
+
+ },
+
+ .ep[2] = {
+ .ep = {
+ .name = "ep2in-bulk",
+ .ops = &pd12_ep_ops,
+ .maxpacket = 16,
+ },
+ .dev = &usb_memory,
+
+ .bEndpointAddress = 2 | USB_DIR_IN,
+ .bmAttributes = USB_ENDPOINT_XFER_BULK,
+
+ },
+ .ep[3] = {
+ .ep = {
+ .name = "ep3out-int",
+ .ops = &pd12_ep_ops,
+ .maxpacket = 64,
+ },
+ .dev = &usb_memory,
+
+ .bEndpointAddress = 3,
+ .bmAttributes = USB_ENDPOINT_XFER_INT,
+
+ },
+ .ep[4] = {
+ .ep = {
+ .name = "ep3in-int",
+ .ops = &pd12_ep_ops,
+ .maxpacket = 64,
+ },
+ .dev = &usb_memory,
+
+ .bEndpointAddress = 4 | USB_DIR_IN,
+ .bmAttributes = USB_ENDPOINT_XFER_INT,
+
+ },
+};
+
+/*
+ * probe - binds to the platform device
+ */
+static int __devinit pd12_udc_probe(struct device *_dev)
+{
+ struct pd12_udc *dev = &usb_memory;
+ int retval;
+
+ DEBUG_PD12("%s: %p\n", __FUNCTION__, _dev);
+ spin_lock_init(&dev->lock);
+ dev->dev = _dev;
+
+ device_initialize(&dev->gadget.dev);
+ dev->gadget.dev.parent = _dev;
+
+ the_controller = dev;
+ dev_set_drvdata(_dev, dev);
+
+ udc_reinit(dev);
+
+ dev->gadget.speed = USB_SPEED_FULL;
+ /* irq setup after old hardware state is cleaned up */
+ retval =
+ request_irq(IRQ_USBINTR, pd12_udc_irq, /*SA_INTERRUPT*/SA_SAMPLE_RANDOM, driver_name,
+ dev);
+ if (retval != 0) {
+ DEBUG_PD12(KERN_ERR "%s: can't get irq %i, err %d\n", driver_name,
+ IRQ_USBINTR, retval);
+ return -EBUSY;
+ }
+
+ create_proc_files();
+
+ return retval;
+}
+
+static int __devexit pd12_udc_remove(struct device *_dev)
+{
+ struct pd12_udc *dev = _dev->driver_data;
+
+ DEBUG_PD12("%s: %p\n", __FUNCTION__, dev);
+
+ udc_disable(dev);
+ remove_proc_files();
+ usb_gadget_unregister_driver(dev->driver);
+
+ free_irq(IRQ_USBINTR, dev);
+
+ dev_set_drvdata(_dev, 0);
+
+ the_controller = 0;
+
+ return 0;
+}
+static struct platform_device pd12_pdev = {
+ .name = (char *) driver_name,
+ .id = -1,
+};
+
+/*-------------------------------------------------------------------------*/
+
+static struct device_driver udc_driver = {
+ .name = (char *)driver_name,
+ .bus = &platform_bus_type,
+ .probe = pd12_udc_probe,
+ .remove = pd12_udc_remove
+ /* FIXME power management support */
+ /* .suspend = ... disable UDC */
+ /* .resume = ... re-enable UDC */
+};
+
+static int __init udc_init(void)
+{
+ int retval;
+
+ DEBUG_PD12("%s: %s version %s\n", __FUNCTION__, driver_name, DRIVER_VERSION);
+ th_pd12_virt = ioremap((ulong)TH_PD12_ADDR,0x10);
+ if(!th_pd12_virt){
+ printk("%s: ioremap fail\n",__FUNCTION__);
+ return -EIO;
+ }
+ th_cpld_virt = ioremap((ulong)TH_CPLD_ADDR,0x10);
+ if(!th_cpld_virt){
+ printk("%s: ioremap fail\n",__FUNCTION__);
+ return -EIO;
+ }
+ retval = platform_device_register (&pd12_pdev);
+ if (retval < 0){
+ platform_device_unregister (&pd12_pdev);
+ return retval;
+ }
+ return driver_register(&udc_driver);
+}
+
+static void __exit udc_exit(void)
+{
+ if(th_pd12_virt){
+ iounmap((void*)th_pd12_virt);
+ th_pd12_virt = NULL;
+ }
+ if(th_cpld_virt){
+ iounmap((void*)th_cpld_virt);
+ th_cpld_virt = NULL;
+ }
+ driver_unregister(&udc_driver);
+}
+
+module_init(udc_init);
+module_exit(udc_exit);
+
+MODULE_DESCRIPTION(DRIVER_DESC);
+MODULE_LICENSE("GPL");
diff --git a/drivers/usb/gadget/pd12_udc.h b/drivers/usb/gadget/pd12_udc.h
new file mode 100644
index 0000000..3ffd07e
--- /dev/null
+++ b/drivers/usb/gadget/pd12_udc.h
@@ -0,0 +1,148 @@
+/*
+ * linux/drivers/usb/gadget/pd12_udc.h
+ * Taihu pd12 full speed USB device controllers
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#ifndef __PD12_UDC_H_
+#define __PD12_UDC_H_
+
+#include <linux/config.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/ioport.h>
+#include <linux/types.h>
+#include <linux/version.h>
+#include <linux/errno.h>
+#include <linux/delay.h>
+#include <linux/sched.h>
+#include <linux/slab.h>
+#include <linux/init.h>
+#include <linux/timer.h>
+#include <linux/list.h>
+#include <linux/interrupt.h>
+#include <linux/proc_fs.h>
+#include <linux/mm.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+
+#include <asm/byteorder.h>
+#include <asm/dma.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/system.h>
+#include <asm/unaligned.h>
+#include <asm/ibm4xx.h>
+
+#include <linux/usb_ch9.h>
+#include <linux/usb_gadget.h>
+
+#define TH_PD12_ADDR 0x50000000
+#define TH_CPLD_ADDR 0x50100000
+
+#define IRQ_USBINTR 29
+#define USB_SUSPEND 0x20
+
+#define UDC_FIFO_EMPTY 0x0
+#define UDC_FIFO_FULL 0x01
+#define UDC_EP_STALL 0x02
+#define UDC_FIFO_UNWRITABLE (UDC_EP_STALL | UDC_FIFO_FULL)
+#define UDC_FIFO_UNREADABLE (UDC_FIFO_EMPTY | UDC_EP_STALL)
+
+/* pd12 udc command */
+#define PD12_SET_ADDR_EN 0xd0
+#define PD12_SET_EP_EN 0xd8
+#define PD12_SET_MODE 0xf3
+#define PD12_SET_DMA 0xfb
+#define PD12_READ_INT 0xf4
+#define PD12_READ_LAST_STATUS 0x40
+#define PD12_SET_STATUS 0x40
+#define PD12_READ_EP_STATUS 0x80
+#define PD12_READ_BUF 0xf0
+#define PD12_WRITE_BUF 0xf0
+#define PD12_SET_EP_STATUS 0x40
+#define PD12_ACK_SETUP 0xf1
+#define PD12_CLEAR_BUF 0xf2
+#define PD12_VALIDATE_BUF 0xfa
+#define PD12_SND_RESUME 0xf6
+#define PD12_RD_CUR_FRAME_NUM 0xf5
+
+
+#define WAIT_FOR_SETUP 0
+#define DATA_STATE_XMIT 1
+#define WAIT_FOR_OUT_STATUS 2
+#define DATA_STATE_RECV 3
+
+#define PD12_SUSPEND_CHG 0x80
+#define PD12_BUS_RST 0x40
+#define PD12_MAIN_IN 0x20
+#define PD12_MAIN_OUT 0x10
+#define PD12_EP1_IN 0x08
+#define PD12_EP1_OUT 0x04
+#define PD12_CNTL_IN 0x02
+#define PD12_CNTL_OUT 0x01
+
+
+#define PD12_MAX_ENDPOINTS 6
+
+/* ********************************************************************************************* */
+/* IO
+ */
+
+struct pd12_ep {
+ struct usb_ep ep;
+ struct pd12_udc *dev;
+
+ const struct usb_endpoint_descriptor *desc;
+ struct list_head queue;
+ unsigned long pio_irqs;
+ unsigned long dma_irqs;
+ short dma;
+
+ u8 stopped;
+ u8 bEndpointAddress;
+ u8 bmAttributes;
+
+};
+
+struct pd12_request {
+ struct usb_request req;
+ struct list_head queue;
+};
+
+struct pd12_udc {
+ struct usb_gadget gadget;
+ struct usb_gadget_driver *driver;
+ struct device *dev;
+ spinlock_t lock;
+
+ int ep0state;
+ struct pd12_ep ep[PD12_MAX_ENDPOINTS];
+
+ unsigned char usb_address;
+
+ unsigned req_pending:1, req_std:1, req_config:1;
+};
+
+static struct pd12_udc *the_controller;
+
+#define ep_is_in(EP) (((EP)->bEndpointAddress&USB_DIR_IN)==USB_DIR_IN)
+#define ep_index(EP) ((EP)->bEndpointAddress&0xF)
+#define ep_maxpacket(EP) ((EP)->ep.maxpacket)
+
+#endif
diff --git a/include/asm-ppc/ibm4xx.h b/include/asm-ppc/ibm4xx.h
index b67db19..da0de26 100644
--- a/include/asm-ppc/ibm4xx.h
+++ b/include/asm-ppc/ibm4xx.h
@@ -47,6 +47,10 @@
#include <platforms/4xx/sycamore.h>
#endif
+#if defined(CONFIG_TAIHU)
+#include <platforms/4xx/taihu.h>
+#endif
+
#if defined(CONFIG_WALNUT)
#include <platforms/4xx/walnut.h>
#endif
^ permalink raw reply related
* [PATCH 2/2] Add Taihu 405EP Platform defconfig
From: John Otken @ 2006-05-11 18:27 UTC (permalink / raw)
To: linuxppc-embedded
Add AMCC Taihu 405EP defconfig.
Signed-off-by: John Otken <jotken@softadvances.com>
diff -urN a/arch/ppc/configs/taihu_defconfig a/arch/ppc/configs/taihu_defconfig
--- a/arch/ppc/configs/taihu_defconfig 1970-01-01 08:00:00.000000000 +0800
+++ b/arch/ppc/configs/taihu_defconfig 2006-02-07 23:28:16.000000000 +0800
@@ -0,0 +1,1001 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.13
+# Thu Jan 26 08:23:41 2006
+#
+CONFIG_MMU=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_RWSEM_XCHGADD_ALGORITHM=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_HAVE_DEC_LOCK=y
+CONFIG_PPC=y
+CONFIG_PPC32=y
+CONFIG_GENERIC_NVRAM=y
+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+# CONFIG_CLEAN_COMPILE is not set
+CONFIG_BROKEN=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+
+#
+# General setup
+#
+CONFIG_LOCALVERSION=""
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_SYSCTL=y
+# CONFIG_AUDIT is not set
+CONFIG_HOTPLUG=y
+CONFIG_KOBJECT_UEVENT=y
+# CONFIG_IKCONFIG is not set
+CONFIG_EMBEDDED=y
+# CONFIG_KALLSYMS is not set
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+# CONFIG_EPOLL is not set
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SHMEM=y
+CONFIG_CC_ALIGN_FUNCTIONS=0
+CONFIG_CC_ALIGN_LABELS=0
+CONFIG_CC_ALIGN_LOOPS=0
+CONFIG_CC_ALIGN_JUMPS=0
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+
+#
+# Loadable module support
+#
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+CONFIG_OBSOLETE_MODPARM=y
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
+
+#
+# Processor
+#
+# CONFIG_6xx is not set
+CONFIG_40x=y
+# CONFIG_44x is not set
+# CONFIG_POWER3 is not set
+# CONFIG_POWER4 is not set
+# CONFIG_8xx is not set
+# CONFIG_E200 is not set
+# CONFIG_E500 is not set
+CONFIG_MATH_EMULATION=y
+# CONFIG_KEXEC is not set
+# CONFIG_CPU_FREQ is not set
+CONFIG_4xx=y
+CONFIG_WANT_EARLY_SERIAL=y
+
+#
+# IBM 4xx options
+#
+# CONFIG_ASH is not set
+# CONFIG_BUBINGA is not set
+# CONFIG_CPCI405 is not set
+# CONFIG_EP405 is not set
+# CONFIG_OAK is not set
+# CONFIG_REDWOOD_5 is not set
+# CONFIG_REDWOOD_6 is not set
+# CONFIG_SYCAMORE is not set
+# CONFIG_WALNUT is not set
+# CONFIG_XILINX_ML300 is not set
+CONFIG_TAIHU=y
+CONFIG_IBM405_ERR77=y
+CONFIG_IBM405_ERR51=y
+CONFIG_IBM_OCP=y
+CONFIG_BIOS_FIXUP=y
+CONFIG_405EP=y
+CONFIG_IBM_OPENBIOS=y
+# CONFIG_PPC4xx_DMA is not set
+CONFIG_PPC_GEN550=y
+# CONFIG_UART0_TTYS0 is not set
+CONFIG_UART0_TTYS1=y
+CONFIG_NOT_COHERENT_CACHE=y
+
+#
+# Platform options
+#
+# CONFIG_PC_KEYBOARD is not set
+# CONFIG_HIGHMEM is not set
+# CONFIG_HZ_100 is not set
+CONFIG_HZ_250=y
+# CONFIG_HZ_1000 is not set
+CONFIG_HZ=250
+CONFIG_PREEMPT_NONE=y
+# CONFIG_PREEMPT_VOLUNTARY is not set
+# CONFIG_PREEMPT is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_CMDLINE_BOOL is not set
+# CONFIG_PM is not set
+CONFIG_SECCOMP=y
+CONFIG_ISA_DMA_API=y
+
+#
+# Bus options
+#
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_LEGACY_PROC=y
+# CONFIG_PCI_NAMES is not set
+# CONFIG_PCI_DEBUG is not set
+
+#
+# PCCARD (PCMCIA/CardBus) support
+#
+CONFIG_PCCARD=y
+# CONFIG_PCMCIA_DEBUG is not set
+CONFIG_PCMCIA=y
+CONFIG_PCMCIA_LOAD_CIS=y
+CONFIG_PCMCIA_IOCTL=y
+CONFIG_CARDBUS=y
+
+#
+# PC-card bridges
+#
+CONFIG_YENTA=y
+# CONFIG_PD6729 is not set
+# CONFIG_I82092 is not set
+# CONFIG_TCIC is not set
+CONFIG_PCCARD_NONSTATIC=y
+
+#
+# Advanced setup
+#
+# CONFIG_ADVANCED_OPTIONS is not set
+
+#
+# Default settings for advanced configuration options are used
+#
+CONFIG_HIGHMEM_START=0xfe000000
+CONFIG_LOWMEM_SIZE=0x30000000
+CONFIG_KERNEL_START=0xc0000000
+CONFIG_TASK_SIZE=0x80000000
+CONFIG_CONSISTENT_START=0xff100000
+CONFIG_CONSISTENT_SIZE=0x00200000
+CONFIG_BOOT_LOAD=0x00400000
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+CONFIG_NET_KEY=y
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_IP_TCPDIAG is not set
+# CONFIG_IP_TCPDIAG_IPV6 is not set
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_BIC=y
+# CONFIG_IPV6 is not set
+# CONFIG_NETFILTER is not set
+
+#
+# SCTP Configuration (EXPERIMENTAL)
+#
+# CONFIG_IP_SCTP is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_NET_CLS_ROUTE is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+# CONFIG_STANDALONE is not set
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+# CONFIG_DEBUG_DRIVER is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_NOSWAP=y
+# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
+# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
+CONFIG_MTD_CFI_GEOMETRY=y
+# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_OTP is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_AMDSTD_RETRY=0
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+# CONFIG_MTD_OBSOLETE_CHIPS is not set
+
+#
+# Mapping drivers for chip access
+#
+CONFIG_MTD_COMPLEX_MAPPINGS=y
+# CONFIG_MTD_PHYSMAP is not set
+CONFIG_MTD_TAIHU=y
+# CONFIG_MTD_PCI is not set
+# CONFIG_MTD_PCMCIA is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLKMTD is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+
+#
+# NAND Flash Device Drivers
+#
+# CONFIG_MTD_NAND is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Plug and Play support
+#
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_SX8 is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=4096
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_LBD is not set
+# CONFIG_CDROM_PKTCDVD is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_ATA_OVER_ETH is not set
+
+#
+# ATA/ATAPI/MFM/RLL support
+#
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_SCSI is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+
+#
+# Fusion MPT device support
+#
+# CONFIG_FUSION is not set
+
+#
+# IEEE 1394 (FireWire) support
+#
+# CONFIG_IEEE1394 is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+
+#
+# Macintosh device drivers
+#
+
+#
+# Network device support
+#
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+
+#
+# ARCnet devices
+#
+# CONFIG_ARCNET is not set
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_OAKNET is not set
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_NET_VENDOR_3COM is not set
+
+#
+# Tulip family network device support
+#
+# CONFIG_NET_TULIP is not set
+# CONFIG_HP100 is not set
+CONFIG_IBM_EMAC=y
+# CONFIG_IBM_EMAC_ERRMSG is not set
+CONFIG_IBM_EMAC_RXB=64
+CONFIG_IBM_EMAC_TXB=8
+CONFIG_IBM_EMAC_FGAP=8
+CONFIG_IBM_EMAC_SKBRES=0
+CONFIG_NET_PCI=y
+# CONFIG_PCNET32 is not set
+# CONFIG_AMD8111_ETH is not set
+# CONFIG_ADAPTEC_STARFIRE is not set
+# CONFIG_B44 is not set
+# CONFIG_FORCEDETH is not set
+# CONFIG_DGRS is not set
+# CONFIG_EEPRO100 is not set
+CONFIG_E100=y
+# CONFIG_FEALNX is not set
+# CONFIG_NATSEMI is not set
+# CONFIG_NE2K_PCI is not set
+# CONFIG_8139CP is not set
+# CONFIG_8139TOO is not set
+# CONFIG_SIS900 is not set
+# CONFIG_EPIC100 is not set
+# CONFIG_SUNDANCE is not set
+# CONFIG_TLAN is not set
+# CONFIG_VIA_RHINE is not set
+
+#
+# Ethernet (1000 Mbit)
+#
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_E1000 is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_R8169 is not set
+# CONFIG_SKGE is not set
+# CONFIG_SK98LIN is not set
+# CONFIG_VIA_VELOCITY is not set
+# CONFIG_TIGON3 is not set
+# CONFIG_BNX2 is not set
+
+#
+# Ethernet (10000 Mbit)
+#
+# CONFIG_IXGB is not set
+# CONFIG_S2IO is not set
+
+#
+# Token Ring devices
+#
+# CONFIG_TR is not set
+
+#
+# Wireless LAN (non-hamradio)
+#
+CONFIG_NET_RADIO=y
+
+#
+# Obsolete Wireless cards support (pre-802.11)
+#
+# CONFIG_STRIP is not set
+# CONFIG_PCMCIA_WAVELAN is not set
+# CONFIG_PCMCIA_NETWAVE is not set
+
+#
+# Wireless 802.11 Frequency Hopping cards support
+#
+# CONFIG_PCMCIA_RAYCS is not set
+
+#
+# Wireless 802.11b ISA/PCI cards support
+#
+# CONFIG_HERMES is not set
+# CONFIG_ATMEL is not set
+
+#
+# Wireless 802.11b Pcmcia/Cardbus cards support
+#
+# CONFIG_AIRO_CS is not set
+# CONFIG_PCMCIA_WL3501 is not set
+
+#
+# Prism GT/Duette 802.11(a/b/g) PCI/Cardbus support
+#
+# CONFIG_PRISM54 is not set
+CONFIG_NET_WIRELESS=y
+
+#
+# PCMCIA network device support
+#
+CONFIG_NET_PCMCIA=y
+# CONFIG_PCMCIA_3C589 is not set
+# CONFIG_PCMCIA_3C574 is not set
+# CONFIG_PCMCIA_FMVJ18X is not set
+# CONFIG_PCMCIA_PCNET is not set
+# CONFIG_PCMCIA_NMCLAN is not set
+# CONFIG_PCMCIA_SMC91C92 is not set
+# CONFIG_PCMCIA_XIRC2PS is not set
+# CONFIG_PCMCIA_AXNET is not set
+
+#
+# Wan interfaces
+#
+# CONFIG_WAN is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_SHAPER is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# Telephony Support
+#
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+# CONFIG_INPUT is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+# CONFIG_SERIAL_8250_CS is not set
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_EXTENDED=y
+# CONFIG_SERIAL_8250_MANY_PORTS is not set
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+# CONFIG_SERIAL_8250_DETECT_IRQ is not set
+# CONFIG_SERIAL_8250_RSA is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_JSM is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+
+#
+# IPMI
+#
+# CONFIG_IPMI_HANDLER is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_NVRAM is not set
+# CONFIG_GEN_RTC is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+
+#
+# PCMCIA character devices
+#
+# CONFIG_SYNCLINK_CS is not set
+# CONFIG_RAW_DRIVER is not set
+
+#
+# TPM devices
+#
+# CONFIG_TCG_TPM is not set
+
+#
+# I2C support
+#
+CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
+
+#
+# I2C Algorithms
+#
+# CONFIG_I2C_ALGOBIT is not set
+# CONFIG_I2C_ALGOPCF is not set
+# CONFIG_I2C_ALGOPCA is not set
+
+#
+# I2C Hardware Bus support
+#
+# CONFIG_I2C_ALI1535 is not set
+# CONFIG_I2C_ALI1563 is not set
+# CONFIG_I2C_ALI15X3 is not set
+# CONFIG_I2C_AMD756 is not set
+# CONFIG_I2C_AMD8111 is not set
+# CONFIG_I2C_I801 is not set
+# CONFIG_I2C_I810 is not set
+# CONFIG_I2C_PIIX4 is not set
+CONFIG_I2C_IBM_IIC=y
+# CONFIG_I2C_ISA is not set
+# CONFIG_I2C_MPC is not set
+# CONFIG_I2C_NFORCE2 is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_PROSAVAGE is not set
+# CONFIG_I2C_SAVAGE4 is not set
+# CONFIG_SCx200_ACB is not set
+# CONFIG_I2C_SIS5595 is not set
+# CONFIG_I2C_SIS630 is not set
+# CONFIG_I2C_SIS96X is not set
+# CONFIG_I2C_STUB is not set
+# CONFIG_I2C_VIA is not set
+# CONFIG_I2C_VIAPRO is not set
+# CONFIG_I2C_VOODOO3 is not set
+# CONFIG_I2C_PCA_ISA is not set
+# CONFIG_I2C_SENSOR is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_SENSORS_DS1337 is not set
+# CONFIG_SENSORS_DS1374 is not set
+# CONFIG_SENSORS_EEPROM is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_RTC8564 is not set
+# CONFIG_SENSORS_M41T00 is not set
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+
+#
+# Dallas's 1-wire bus
+#
+# CONFIG_W1 is not set
+
+#
+# Hardware Monitoring support
+#
+CONFIG_HWMON=y
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ADM9240 is not set
+# CONFIG_SENSORS_ASB100 is not set
+# CONFIG_SENSORS_ATXP1 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_FSCHER is not set
+# CONFIG_SENSORS_FSCPOS is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_LM63 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM87 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_LM92 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_SIS5595 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_VIA686A is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+# CONFIG_HWMON_DEBUG_CHIP is not set
+
+#
+# Misc devices
+#
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# Digital Video Broadcasting Devices
+#
+# CONFIG_DVB is not set
+
+#
+# Graphics support
+#
+# CONFIG_FB is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+# CONFIG_USB is not set
+
+#
+# USB Gadget Support
+#
+CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_PXA2XX is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+CONFIG_USB_GADGET_PD12=y
+CONFIG_USB_PD12=y
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+# CONFIG_USB_GADGET_DUALSPEED is not set
+CONFIG_USB_ZERO=y
+# CONFIG_USB_ETH is not set
+# CONFIG_USB_GADGETFS is not set
+# CONFIG_USB_FILE_STORAGE is not set
+# CONFIG_USB_G_SERIAL is not set
+
+#
+# MMC/SD Card support
+#
+# CONFIG_MMC is not set
+
+#
+# InfiniBand support
+#
+# CONFIG_INFINIBAND is not set
+
+#
+# SN Devices
+#
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_XATTR=y
+# CONFIG_EXT3_FS_POSIX_ACL is not set
+# CONFIG_EXT3_FS_SECURITY is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+
+#
+# XFS support
+#
+# CONFIG_XFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_INOTIFY=y
+# CONFIG_QUOTA is not set
+CONFIG_DNOTIFY=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_SYSFS=y
+# CONFIG_DEVPTS_FS_XATTR is not set
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_XATTR is not set
+# CONFIG_HUGETLBFS is not set
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_RAMFS=y
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+
+#
+# Network File Systems
+#
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+# CONFIG_NFS_DIRECTIO is not set
+# CONFIG_NFSD is not set
+# CONFIG_ROOT_NFS is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+# CONFIG_MSDOS_PARTITION is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+
+#
+# Native Language Support
+#
+# CONFIG_NLS is not set
+
+#
+# IBM 40x options
+#
+
+#
+# Library routines
+#
+# CONFIG_CRC_CCITT is not set
+CONFIG_CRC32=y
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+
+#
+# Profiling support
+#
+# CONFIG_PROFILING is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_MAGIC_SYSRQ is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_KGDB is not set
+# CONFIG_XMON is not set
+CONFIG_BDI_SWITCH=y
+# CONFIG_SERIAL_TEXT_DEBUG is not set
+CONFIG_PPC_OCP=y
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+
+#
+# Cryptographic options
+#
+CONFIG_CRYPTO=y
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_WP512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Hardware crypto devices
+#
^ permalink raw reply
* Re: MPC8641(D) software status
From: Wolfgang Denk @ 2006-05-11 19:02 UTC (permalink / raw)
To: Xianghua Xiao; +Cc: linuxppc-embedded
In-Reply-To: <44634541.3040109@freescale.com>
In message <44634541.3040109@freescale.com> you wrote:
> We have patches for 8641D against 2.6.15/2.6.16 and it works well in lab
> in the last three months along with u-boot code. I think a patch against
> 2.6.17 or later will be released in the future. However if you need the
> 2.6.15/2.6.16 patch now, you can contact Freescale directly. In fact,
> for all 8641D boards we will ship, we will include the kernel/u-boot
> source code on the SATA hard drive directly as well, or you can also
> download them from freescale's website.
And when will you start working with the commmunity, and submit your
patches to the public source tree? Will Freescale wait (again) until
they are against such an old version that it's a PITA to merge them?
Best regards,
Wolfgang Denk
--
Software Engineering: Embedded and Realtime Systems, Embedded Linux
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de
Drun'? 'm not drun'! You woudn' dare call m' drun' if I was sober!
- Terry Pratchett, _Men at Arms_
^ permalink raw reply
* ppc32 kernel boot problem (pmu related?)
From: Nathan Pilatzke @ 2006-05-11 19:07 UTC (permalink / raw)
To: linuxppc-dev
Hello, I am not a member of this list and I hope this is the correct
place to report such problems and ask for help.
I am running an eMac first generation powerpc (700MHz) and the Gentoo
distribution. Kernel 2.6.15 (Gentoo revision 1) is working quite well
for me. A few days ago I compiled 2.6.17-rc3 from the vanilla sources
ebuild and am having troubles with the pmu code.
I can boot successfully when my config has
# CONFIG_ADB_PMU is not set
but cannot boot if my config has
CONFIG_ADB_PMU=3Dy
I can post anything you need to help narrow down the problem (ie.
kernel configs, boot msgs). Would turning on the kernel debugging
give more information on the problem? Any help would be greatly
appreciated... even if I can just narrow down the problem further so
that I can make a very specific bug report.
Here is the cpuinfo (as reported under 2.6.17-rc3 without PMU):
cat /proc/cpuinfo
processor : 0
cpu : 7450, altivec supported
clock : 700.000000MHz
revision : 0.1 (pvr 8000 0201)
bogomips : 49.79
timebase : 24913389
platform : PowerMac
machine : PowerMac4,4
motherboard : PowerMac4,4 MacRISC2 MacRISC Power Macintosh
detected as : 80 (eMac)
pmac flags : 00000010
L2 cache : 256K unified
pmac-generation : NewWorld
Thanks.
^ permalink raw reply
* Re: MPC8641(D) software status
From: Xianghua Xiao @ 2006-05-11 19:24 UTC (permalink / raw)
To: Wolfgang Denk; +Cc: linuxppc-embedded
In-Reply-To: <20060511190201.D3818352B0C@atlas.denx.de>
well I am not the one to be allowed to send public patches. However if
someone needs a 2.6.15/2.6.16 patch I can certainly send it out before a
public release(2.6.17?) is ready. It's also available on freescale's
website.
thanks,
xianghua
Wolfgang Denk wrote:
>In message <44634541.3040109@freescale.com> you wrote:
>
>
>>We have patches for 8641D against 2.6.15/2.6.16 and it works well in lab
>>in the last three months along with u-boot code. I think a patch against
>>2.6.17 or later will be released in the future. However if you need the
>>2.6.15/2.6.16 patch now, you can contact Freescale directly. In fact,
>>for all 8641D boards we will ship, we will include the kernel/u-boot
>>source code on the SATA hard drive directly as well, or you can also
>>download them from freescale's website.
>>
>>
>
>And when will you start working with the commmunity, and submit your
>patches to the public source tree? Will Freescale wait (again) until
>they are against such an old version that it's a PITA to merge them?
>
>Best regards,
>
>Wolfgang Denk
>
>
>
--
// Xianghua Xiao
// Freescale Semiconductor x.xiao@freescale.com
// (Tel)1 (512) 996-6768 (Fax) 1 (512) 996-7438
// 7700 W. Parmer Lane, MD: PL30, Austin, TX 78729
^ permalink raw reply
* Re: MPC8641(D) software status
From: Wolfgang Denk @ 2006-05-11 19:55 UTC (permalink / raw)
To: Xianghua Xiao; +Cc: linuxppc-embedded
In-Reply-To: <44638F6D.1030602@freescale.com>
In message <44638F6D.1030602@freescale.com> you wrote:
> well I am not the one to be allowed to send public patches. However if
> someone needs a 2.6.15/2.6.16 patch I can certainly send it out before a
> public release(2.6.17?) is ready. It's also available on freescale's
> website.
Can you please post an URL, both for the Linux and the U-boot
patches?
Best regards,
Wolfgang Denk
--
Software Engineering: Embedded and Realtime Systems, Embedded Linux
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de
You don't have to worry about me. I might have been born yesterday...
but I stayed up all night.
^ permalink raw reply
* Failure of 2 BAT schemes to enable D-cache
From: Om Vadlapatla @ 2006-05-11 20:13 UTC (permalink / raw)
To: linuxppc-embedded@ozlabs.org, U-Boot-Users@lists.sourceforge.net
[-- Attachment #1: Type: text/plain, Size: 4224 bytes --]
Hello,
Processor: MPC8270
Debugger: Abatron BDI 2000
Board & processor Initialization by: Uboot 1.1.2
Aim:
I try to enable d-cache at the Register level with out
having any exceptions. I will write my own code to
compile into the kernel that is no longer supported by
Montavista (3.0) provided it works when I manipulate
the registers.
Proceedure:
~in window 1 (DIP window) I reset the processor then
the flash mem loads the U-boot version 1.1.2. I do not
load the OS so the system is running at the U-boot
prompt.
=>
~In window 2 (BDI debugger window) I use the Abarton
BDI to force the PPC to enter debug mode by issuing -
"halt" instruction.
//this is the BDI window for both tests when "halt"
MPC8270>halt
Target CPU : MPC8280/MGT5200 (Zeppo)
Target state : debug mode
Debug entry cause : COP halt
Current PC : 0x0ffe935c
Current CR : 0x44004044
Current MSR : 0x0000b002
Current LR : 0x0ffe13a8
~now by issueing commands from the BDI I try to set
the BATs and the MMU as follows:
I tried two BAT schemes on the abatron that are
attached in BAT_register_setting_table.txt &
8280_InitMMU.cmm :
-------------------------------------------------------
Test 1:-
For seting DBAT regs by BDI commands ccording to
(BAT_register_setting_table.txt)or:
// initialize bats
MPC8270>rm dbat0u 0xffe0003f
MPC8270>rm dbat0l 0xffe00022
MPC8270>rm dbat1u 0x00001fff
MPC8270>rm dbat1l 0x00000002
MPC8270>rm dbat2u 0x300007ff
MPC8270>rm dbat2l 0x30000002
MPC8270>rm dbat3u 0x400003FF
MPC8270>rm dbat3l 0x40000022
MPC8270>rm dbat4u 0xFB0001FF
MPC8270>rm dbat4l 0xFB000022
MPC8270>rm dbat5u 0xFE400003
MPC8270>rm dbat5l 0xFE400022
MPC8270>rm dbat6u 0xF0000003
MPC8270>rm dbat6l 0xF0000022
MPC8270>rm dbat7u 0xFF000003
MPC8270>rm dbat7l 0xFF000022
MPC8270>rm hid0 0x8000c088 // set HID0 to enable
// I & D Cache
MPC8270>go // to let the processor run
I check the PC and it is at 0x200 the Machine check
exception.
Please post suggestions to avoid the Exception!!
-------------------------------------------------------
Test 2:-
commands I issued throught Abatron BDI window:
// initialization of BATs refer to (8280_InitMMU.cmm)
// please keep in mind that even though these BAT
// initialization are for a Stand alone systems I only
// plan to test if I am able to initialize the data
// cache without the 0x200 (Machine check exception)
// exception.
// 60-x SDRAM IBAT
MPC8270>rm ibat0u 0x000003fe // IBAT0U 32MB
MPC8270>rm ibat0l 0x00000002 // IBAT0L R/W
//IMMR IBAT
MPC8270>rm ibat1u 0x04700002 // IBAT1U 128KB
MPC8270>rm ibat1l 0x04700022 // IBAT0L I R/W
//Flash IBAT
MPC8270>rm ibat3u 0xff0000fe // IBAT3U 8MB
MPC8270>rm ibat3l 0xff000001 // IBAT3L R/O
//60-x SDRAM DBAT
MPC8270>rm dbat0u 0x000007fe // DBAT0U 16MB
MPC8270>rm dbat0l 0x00000002 // DBAT0L R/W
//Local SDRAM DBAT
MPC8270>rm dbat1u 0x0400007e //DBAT1U
MPC8270>rm dbat1l 0x0400002a //DBAT1L I,G R/W
//BCSR DBAT
MPC8270>rm dbat2u 0x0450007e //DBAT2U BCSR + IMMR
space
MPC8270>rm dbat2l 0x0450002a //DBAT2L I,G R/W
//Flash DBAT
MPC8270>rm dbat3u 0xff0000fe //DBAT3U 8MB
MPC8270>rm dbat3l 0xff000022 //DBAT3L I R/W
// the Bats initialize fine no problem till here
// enable MMU (EE + ME + DR +IR)
MPC8270>rm msr 0x9030
// I feel I may be messing it up here (can some one
// please correct me?)
MPC8270>go // this is to let the processor run
// however ends up restarting the system
// I dont issue the foll command coz of reset
MPC8270>rm hid0 0x8000c088 // this is to set and
// enable the I & D Caches
This is how the DIP window where the boot prompt is
looks after this test 2:-
See attached file: DIP_outPut_test2_BATs.txt
Have I wrongly inilialized the MSR?
-------------------------------------------------------
Please post comments and suggestions of how I can
initialized MMU for d-cache performance. I am new
to this.
Thanky you,
Best regards,
Om Vadlapatla
__________________________________________________
Do You Yahoo!?
Tired of spam? Yahoo! Mail has the best spam protection around
http://mail.yahoo.com
[-- Attachment #2: 790078158-8280_InitMMU.cmm --]
[-- Type: application/octet-stream, Size: 1775 bytes --]
; ********************************
; Initialize BATs
; ********************************
INIT_MMU:
; *** Invalidate TLBs
d.a 0x10000 addi r2,0,32
d.a 0x10004 mtctr r2 ; Load CTR with 32.
d.a 0x10008 addi r3,0,0 ; Use r3 as the tlb index
d.a 0x1000C tlbie r3 ; invalidate the tlb entry
d.a 0x10010 sync
d.a 0x10014 addi r3,r3,0x1000 ; increment the index
d.a 0x10018 bdnz 0x1000C
d.a 0x1001C b 0x1001C
r.s IP 0x10000
go
wait 1ms
break
; *** Clear all Upper BATs
d.s SPR:0x218 %l 0 ; DBAT0U
d.s SPR:0x21A %l 0 ; DBAT1U
d.s SPR:0x21C %l 0 ; DBAT2U
d.s SPR:0x21E %l 0 ; DBAT3U
d.s SPR:0x238 %l 0 ; DBAT4U
d.s SPR:0x23A %l 0 ; DBAT5U
d.s SPR:0x23C %l 0 ; DBAT6U
d.s SPR:0x23E %l 0 ; DBAT7U
d.s SPR:0x210 %l 0 ; IBAT0U
d.s SPR:0x212 %l 0 ; IBAT1U
d.s SPR:0x214 %l 0 ; IBAT2U
d.s SPR:0x216 %l 0 ; IBAT3U
d.s SPR:0x230 %l 0 ; IBAT4U
d.s SPR:0x232 %l 0 ; IBAT5U
d.s SPR:0x234 %l 0 ; IBAT6U
d.s SPR:0x236 %l 0 ; IBAT7U
; 60-x SDRAM IBAT
d.s SPR:0x210 %l 0x000003FE ; IBAT0U 32MB
d.s SPR:0x211 %l 0x00000002 ; IBAT0L R/W
; IMMR IBAT
d.s SPR:0x212 %l 0x04700002 ; IBAT1U 128KB
d.s SPR:0x213 %l 0x04700022 ; IBAT0L I R/W
; Flash IBAT
d.s SPR:0x216 %l 0xFF0000FE ; IBAT3U 8MB
d.s SPR:0x217 %l 0xFF000001 ; IBAT3L R/O
; 60-x SDRAM DBAT
d.s SPR:0x218 %l 0x000007FE ; DBAT0U 16MB
d.s SPR:0x219 %l 0x00000002 ; DBAT0L R/W
; Local SDRAM DBAT
d.s SPR:0x21A %l 0x0400007E ; DBAT1U
d.s SPR:0x21B %l 0x0400002A ; DBAT1L I,G R/W
; BCSR DBAT
d.s SPR:0x21C %l 0x0450007E ; DBAT2U BCSR + IMMR space
d.s SPR:0x21D %l 0x0450002A ; DBAT2L I,G R/W
; Flash DBAT
d.s SPR:0x21E %l 0xFF0000FE ; DBAT3U 8MB
d.s SPR:0x21F %l 0xFF000022 ; DBAT3L I R/W
; Enable MMU
;r.s MSR 0x9030 ; EE + ME + DR + IR
[-- Attachment #3: 79201750-BAT_register_setting_table.txt --]
[-- Type: text/plain, Size: 1770 bytes --]
BAT register setting table
I&D-BAT register setting (I-BAT register can not write W and G bit)
|---------------------------------------------------------------------------------------------|
|BAT-No |Base address |Memory Size |WIMG | BAT U |BAT L |Remark |
|-------|---------------|---------------|---------|-------------|---------------|-------------|
|0 |0xFFE00000 |2Mbyte |0100 | FFE0003F |FFE00022 |BOOT Memory |
|-------|---------------|---------------|---------|-------------|---------------|-------------|
|1 |0x00000000 |256Mbyte |0000 | 00001FFF |00000002 |60x-SDRAM |
|-------|---------------|---------------|---------|-------------|---------------|-------------|
|2 |0x30000000 |64Mbyte |0000 | 300007FF |30000002 |Local-SDRAM |
|-------|---------------|---------------|---------|-------------|---------------|-------------|
|3 |0x40000000 |20Mbyte |0100 | 400003FF |40000022 |SDH-I/O |
|-------|---------------|---------------|---------|-------------|---------------|-------------|
|4 |0xFB000000 |12Mbyte |0100 | FB0001FF |FB000022 |RTC and FPGA |
|-------|---------------|---------------|---------|-------------|---------------|-------------|
|5 |0xFE400000 |1Kbyte |0100 | FE400003 |FE400022 |Compact-Flash|
|-------|---------------|---------------|---------|-------------|---------------|-------------|
|6 |0xF0000000 |128Kbyte |0100 | F0000003 |F0000022 |CPU(Master) |
|-------|---------------|---------------|---------|-------------|---------------|-------------|
|7 |0xFF000000 |128Kbyte |0100 | FF000003 |FF000022 |CPU(Slave)** |
|---------------------------------------------------------------------------------------------|
**No.7 of BAT register should be setting for FW4160
[-- Attachment #4: 2552527863-DIP_outPut_Test1_BATs.txt --]
[-- Type: text/plain, Size: 2938 bytes --]
$ telnet 100.0.4.26 5003
Trying 100.0.4.26...
Connected to 100.0.4.26.
Escape character is '^]'.
U-Boot 1.1.2 (Jan 27 2006 - 14:27:57) ### Release 1.1.5 ###
MPC8260 Reset Status: Bus Monitor, External Soft, External Hard
MPC8260 Clock Configuration
- Bus-to-Core Mult 4x, VCO Div 2, 60x Bus Freq 25-75 , Core Freq 100-300
- dfbrg 1, corecnf 0x1a, busdf 5, cpmdf 1, plldf 0, pllmf 5
- vco_out 400000002, scc_clk 100000000, brg_clk 25000000
- cpu_clk 266666668, cpm_clk 200000001, bus_clk 66666667
CPU: MPC8260 (HiP7 Rev 14, Mask 1.0 1K49M) at 266.666 MHz
Board: Fujitsu FW4060
I2C: ready
DRAM: 256 MB
FLASH: 2 MB
In: serial
Out: serial
Err: serial
Net: FCC2 ETHERNET
IDE: Bus 0: OK
Device 0: Model: Hitachi XXM2.3.0 Firm: Rev 3.00 Ser#: X0405 20050304185152
Type: Removable Hard Disk
Capacity: 61.1 MB = 0.0 GB (125184 x 512)
Hit any key to stop autoboot: 0
=> Bad trap at PC: fffffffc, SR: 1000, vector=800
NIP: FFFFFFFC XER: 20000000 LR: 00001088 REGS: 0ffa7dc0 TRAP: 0800 DAR: 0FFE55FC
MSR: 00001000 EE: 0 PR: 0 FP: 0 ME: 1 IR/DR: 00
GPR00: 0000A000 0FFA7EB0 00000004 00000000 0FFF0E80 0000000A FFFFFFFD FFFFFFFF
GPR08: 0FFA7C18 F0000080 00008000 F0000090 00000000 0403FF80 0FFF6000 101C8000
GPR16: 00000000 00000000 00000000 0100FFE0 00000000 00000001 00000000 00000000
GPR24: 00000000 FFFFFFFF 00000001 00000003 0FFFEFC8 0FFA7F64 0FFF74AC 0FFF0E80
Call backtrace:
Exception in kernel pc fffffffc signal 0
U-Boÿ
U-Boot 1.1.2 (Jan 27 2006 - 14:27:57) ### Release 1.1.5 ###
MPC8260 Reset Status: External Soft, External Hard
MPC8260 Clock Configuration
- Bus-to-Core Mult 4x, VCO Div 2, 60x Bus Freq 25-75 , Core Freq 100-300
- dfbrg 1, corecnf 0x1a, busdf 5, cpmdf 1, plldf 0, pllmf 5
- vco_out 400000002, scc_clk 100000000, brg_clk 25000000
- cpu_clk 266666668, cpm_clk 200000001, bus_clk 66666667
CPU: MPC8260 (HiP7 Rev 14, Mask 1.0 1K49M) at 266.666 MHz
Board: Fujitsu FW4060
I2C: ready
DRAM: 256 MB
FLASH: 2 MB
In: serial
Out: serial
Err: serial
Net: FCC2 ETHERNET
IDE: Bus 0: OK
Device 0: Model: Hitachi XXM2.3.0 Firm: Rev 3.00 Ser#: X0405 20050304185152
Type: Removable Hard Disk
Capacity: 61.1 MB = 0.0 GB (125184 x 512)
Hit any key to stop autoboot: 0
=> Bad trap at PC: fffffffc, SR: 1000, vector=800
NIP: FFFFFFFC XER: 00000000 LR: 00001088 REGS: 0ffa7dc0 TRAP: 0800 DAR: 0FFE55FC
MSR: 00001000 EE: 0 PR: 0 FP: 0 ME: 1 IR/DR: 00
GPR00: 0000A000 0FFA7EB0 00000004 00000000 0FFF0E80 0000000A FFFFFFFD 00000000
GPR08: 00000002 F0000080 00008000 F0000090 00000000 0403FF80 0FFF6000 101C8000
GPR16: 00000000 00000000 00000000 0100FFE0 00003002 00000001 00000000 0FFCB098
GPR24: 0FFCE410 00000001 00000001 00000003 0FFFEFC8 0FFA7F64 0FFF74AC 0FFF0E80
Call backtrace:
Exception in kernel pc fffffffc signal 0
U-Boot 1.1.2 (Jan 27 2006 - 14:ò
^ permalink raw reply
* Help: Linux porting to custom target hw
From: Jayanta Das @ 2006-05-11 20:36 UTC (permalink / raw)
To: linuxppc-embedded
[-- Attachment #1: Type: text/plain, Size: 342 bytes --]
Thanks a lot Thiago.
My specific question was what do I need to change in the kernel and
U-Boot source to boot my target HW. Is flash location and the memory map
only thing I need to worry about or I need to do something more. E.g. I
am looking for a document which will specify the LSP specific files.
Thanks again for the help.
[-- Attachment #2: Type: text/html, Size: 1007 bytes --]
^ permalink raw reply
* Re: Failure of 2 BAT schemes to enable D-cache
From: Wolfgang Denk @ 2006-05-11 22:38 UTC (permalink / raw)
To: Om Vadlapatla
Cc: U-Boot-Users@lists.sourceforge.net, linuxppc-embedded@ozlabs.org
In-Reply-To: <20060511201329.23866.qmail@web37105.mail.mud.yahoo.com>
In message <20060511201329.23866.qmail@web37105.mail.mud.yahoo.com> you wrote:
>
> Please post comments and suggestions of how I can
> initialized MMU for d-cache performance. I am new
> to this.
We have been through this before, several times. Many times actually.
I have explained it to you, and so did others.
It is perfectly fine with me if you ignore my advice. But then please
stop posting the same question again and again here.
You will not receive any new answers.
Again, and definitely for the last time:
It makes no sense to try to enable the data cache on a MPC82xx system
in U-Boot; the time you could save if you succeeded is marginal to
your application startup time.
And in Linux the D-Cache is enabled, so no changes are needed.
Best regards,
Wolfgang Denk
--
Software Engineering: Embedded and Realtime Systems, Embedded Linux
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de
They say a little knowledge is a dangerous thing, but it is not one
half so bad as a lot of ignorance. - Terry Pratchett, _Equal Rites_
^ permalink raw reply
* Re: [RFC/PATCH] Make powerpc64 use __thread for per-cpu variables
From: Segher Boessenkool @ 2006-05-11 23:41 UTC (permalink / raw)
To: Richard Henderson
Cc: linux-arch, linuxppc-dev, Paul Mackerras, David S. Miller,
linux-kernel
In-Reply-To: <20060511002217.GA31481@twiddle.net>
>> Would an asm clobber of GPR13 in the schedule routines (or a wrapper
>> for them, or whatever) work?
>
> No. The address is cse'd symbolically long before the r13
> reference is exposed.
Current GCC won't ever do that over a (non-local, non-inlinable)
function call though. _Current_ GCC.
Segher
^ permalink raw reply
* Re: [RFC/PATCH] Make powerpc64 use __thread for per-cpu variables
From: Segher Boessenkool @ 2006-05-11 23:42 UTC (permalink / raw)
To: Paul Mackerras
Cc: linux-arch, linux-kernel, linuxppc-dev, David S. Miller, rth
In-Reply-To: <17506.37259.755099.974824@cargo.ozlabs.ibm.com>
>> gcc shouldn't think there is any reason to cache the address.
>
> Can I rely on that being true in the future?
As long as the compiler stays smart enough, and doesn't do
stupid things :-)
(i.e., no. Sigh).
Segher
^ permalink raw reply
* Help: Linux porting to custom target hw
From: Thiago Galesi @ 2006-05-12 0:49 UTC (permalink / raw)
To: Jayanta Das; +Cc: linuxppc-embedded
In-Reply-To: <8584FDC94AFF7640B17B8A89B23B19B331C6BA@sbsserver.AlphionCorp.local>
>
> My specific question was what do I need to change in the kernel and U-Boo=
t
> source to boot my target HW. Is flash location and the memory map only th=
ing
> I need to worry about or I need to do something more. E.g. I am looking f=
or
> a document which will specify the LSP specific files.
I'm not very familiar with UBoot but most of the changes will be made
there, not in the kernel (that is, memory size, memory mappings, etc)
AFAIK the only thing you'll have to set up in the kernel is the flash
location, size and configuration (that is, if it is 16 bits, 32 bits,
2x16 bits , etc, etc)
Thiago
^ permalink raw reply
* Re: MPC8641(D) software status
From: Sam Song @ 2006-05-12 1:31 UTC (permalink / raw)
To: Xianghua Xiao; +Cc: linuxppc-embedded
In-Reply-To: <44638F6D.1030602@freescale.com>
Hi Xianghua,
Xianghua Xiao <x.xiao@freescale.com> wrote:
> well I am not the one to be allowed to send
> public patches. However if
> someone needs a 2.6.15/2.6.16 patch I can
> certainly send it out before a
> public release(2.6.17?) is ready. It's also
> available on freescale's
> website.
That's fine. But I couldn't get it on your
website. Not NOW, perhaps? :-)
As wolfgang mentioned, the sooner it released
to community, the better it would be.
Still one thing. Does MPC7447A tool chain
work for MPC8641D?
The big news is that it can be supported
by u-boot and 2.6 kernel. It's so great!
Highly appreciate your info,
Sam
BTW, will you show up at FTF Shangahi at the
end of this month? If so, I could invite you
visit our lab for further communication.
Best regards,
Sam
___________________________________________________________
雅虎免费邮箱-3.5G容量，20M附件
http://cn.mail.yahoo.com/
^ permalink raw reply
* Re: ppc32 kernel boot problem (pmu related?)
From: Benjamin Herrenschmidt @ 2006-05-12 3:12 UTC (permalink / raw)
To: Nathan Pilatzke; +Cc: linuxppc-dev
In-Reply-To: <98889dd30605111207g6afe6158je681717ccacb9e40@mail.gmail.com>
On Thu, 2006-05-11 at 15:07 -0400, Nathan Pilatzke wrote:
> Hello, I am not a member of this list and I hope this is the correct
> place to report such problems and ask for help.
>
> I am running an eMac first generation powerpc (700MHz) and the Gentoo
> distribution. Kernel 2.6.15 (Gentoo revision 1) is working quite well
> for me. A few days ago I compiled 2.6.17-rc3 from the vanilla sources
> ebuild and am having troubles with the pmu code.
>
> I can boot successfully when my config has
> # CONFIG_ADB_PMU is not set
> but cannot boot if my config has
> CONFIG_ADB_PMU=y
What happens when you enable that option ?
> I can post anything you need to help narrow down the problem (ie.
> kernel configs, boot msgs). Would turning on the kernel debugging
> give more information on the problem? Any help would be greatly
> appreciated... even if I can just narrow down the problem further so
> that I can make a very specific bug report.
>
> Here is the cpuinfo (as reported under 2.6.17-rc3 without PMU):
> cat /proc/cpuinfo
> processor : 0
> cpu : 7450, altivec supported
> clock : 700.000000MHz
> revision : 0.1 (pvr 8000 0201)
> bogomips : 49.79
> timebase : 24913389
> platform : PowerMac
> machine : PowerMac4,4
> motherboard : PowerMac4,4 MacRISC2 MacRISC Power Macintosh
> detected as : 80 (eMac)
> pmac flags : 00000010
> L2 cache : 256K unified
> pmac-generation : NewWorld
>
> Thanks.
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-dev
^ permalink raw reply
* scheduler Latecy test on power pc
From: Prabhat_Singh @ 2006-05-12 3:42 UTC (permalink / raw)
To: linuxppc-embedded
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Hi,
I am using denx linux-2.4.24 on our customized board based on
MPC8248 power processor.
I want to do kernel scheduling latency test on my power pc based
board
, can any one please tell me how could I do that?
prabhat
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^ permalink raw reply
* RE: Help Needed: input overrun(s)
From: s.maiti @ 2006-05-12 5:07 UTC (permalink / raw)
To: Rune Torgersen; +Cc: linuxppc-embedded
In-Reply-To: <DCEAAC0833DD314AB0B58112AD99B93B0189DDA7@ismail.innsys.innovsys.com>
Thank you very much for your help. Actually in our driver we are using all
128 channels of MCC1. So we have relocated the dpram for the uart and
ethernet to the dpram 3 and freed the space for the MCC1 accordingly. We
have gone through our allocations, nowhere it's conflicting.
In your case is your driver able to transmit and receive data correctly?
In our case whenever we load the driver the console output gets crambbled.
Through debugging we have identified that the cause of it may be due to
the configuration of L1RSYNC, L1TSYNC, RCLK and TCLK. Can these
configuration cause this ttyS overrun?
Also when the driver is loaded we are not getting any interrupts. We are
writting to the Tx buffer through a user space application, but that is
not resulting in any tx interrupts. Can you help me regarding this.
Also I will be grateful to if let me know which kernel version of linux
you are using and the flow of initialization you are using in your driver.
Looking forward to your help.
Thanks and regards,
Souvik Maiti
Tata Consultancy Services Limited
Mailto: s.maiti@tcs.com
Website: http://www.tcs.com
"Rune Torgersen" <runet@innovsys.com>
05/11/2006 07:44 PM
To
<s.maiti@tcs.com>
cc
<linuxppc-embedded@ozlabs.org>, "Stevan Ignjatovic" <stevan@iritel.com>
Subject
RE: Help Needed: input overrun(s)
> From: s.maiti@tcs.com [mailto:s.maiti@tcs.com]
> Thanks very much for your reply. It's seems you have already
> developed the MCC driver. Are you using channels 32 to 96?
> Have you made any changes in the dp ram allocation for uart
> or ethernet driver?
> Please help me...
We are using every other channel from 32 to 96 on both MCC's as SS7
receivers.
We did not have to do any relocations for UART or ethernet.
Ethernet uses upper DPRAM (above 0x8000) and uarts use the first 128
bytes.
We statically allocate DPRAM with cpm_alloc_fixed. MCC1 use 0x0800 to
0x17ff
MCC2 use 0x2800 to 0x37ff. Extra param RAM is allocated with cpm_alloc
and is allocated as 256*8 bytes, and shared between MCC1 and 2.
All BD and interrupt tables are in main memory.
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^ permalink raw reply
* DMA problem on PPC 74xx
From: Monika Borikar @ 2006-05-12 6:44 UTC (permalink / raw)
To: linuxppc-dev
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Hello All,
I am working on PPC 74xx processor which uses Marvell mv64360 host bridge. On PPC linux-2.6.12.5 (with EV64360 patch ) is running, with CONFIG_NOT_COHERENT_CACHE=y option in .config file.
I have a pci device which has to do DMA transfer from PPC memory. This pci device is DMA master for all dma transactions. The device driver on PPC allocates memory using pci_alloc_consistent & write the data to this allocated memory. Address of this allocated memory is given to device using which device is supposed to do read/write using dma mechanism.
Looks like dma transfer is not happening. I found few mails which talks about some problem with caching. Can anybody guide me if there is any such issue & how to solve that?
Thanks
-Monika
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