* Re: [PATCH] powerpc: Fix cell blade detection
From: Benjamin Herrenschmidt @ 2006-06-08 0:26 UTC (permalink / raw)
To: Segher Boessenkool; +Cc: linuxppc-dev list, Paul Mackerras
In-Reply-To: <3EB64128-691F-4DB9-922E-C60CE739168F@kernel.crashing.org>
On Thu, 2006-06-08 at 01:09 +0200, Segher Boessenkool wrote:
> > +#ifdef CONFIG_PPC64
> > + /* We must make sure we don't detect the IBM Cell
> > + * blades as pSeries due to some firmware issues,
> > + * so we do it here.
> > + */
>
> Is this #ifdef needed? Do we really care about 22 bytes of rodata?
For 32 bits platforms, yes :)
Ben.
^ permalink raw reply
* Re: [PATCH] powerpc: Fix cell blade detection
From: Segher Boessenkool @ 2006-06-07 23:09 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev list, Paul Mackerras
In-Reply-To: <1149645858.27572.93.camel@localhost.localdomain>
> +#ifdef CONFIG_PPC64
> + /* We must make sure we don't detect the IBM Cell
> + * blades as pSeries due to some firmware issues,
> + * so we do it here.
> + */
Is this #ifdef needed? Do we really care about 22 bytes of rodata?
Segher
^ permalink raw reply
* Re: [PATCH] powerpc: Fix call to ibm,client-architecture-support
From: Segher Boessenkool @ 2006-06-07 23:07 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev list, Paul Mackerras
In-Reply-To: <1149645693.27572.90.camel@localhost.localdomain>
> The code in prom_init.c calling the firmware
> ibm,client-architecture-support on pSeries has a bug where it fails to
> properly pass the instance handle of the firmware object when
> trying to
> call a method. Result ranges from the call doing nothing to the
> firmware
> crashing. (Found by Segher, thanks !)
Dry debugging is one of the most fun things in the world, second
only to reverse engineering. Am I pathetic or what?
> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Segher Boessenkool <segher@kernel.crashing.org>
> Index: linux-work/arch/powerpc/kernel/prom_init.c
> ===================================================================
> --- linux-work.orig/arch/powerpc/kernel/prom_init.c 2006-05-30
> 13:00:51.000000000 +1000
> +++ linux-work/arch/powerpc/kernel/prom_init.c 2006-06-06
> 11:59:20.000000000 +1000
> @@ -822,6 +822,7 @@ static void __init prom_send_capabilitie
> /* try calling the ibm,client-architecture-support method */
> if (call_prom_ret("call-method", 3, 2, &ret,
> ADDR("ibm,client-architecture-support"),
> + root,
> ADDR(ibm_architecture_vec)) == 0) {
> /* the call exists... */
> if (ret)
^ permalink raw reply
* Re: [PATCH 3/3] RTAS MSI
From: Nathan Lynch @ 2006-06-07 22:58 UTC (permalink / raw)
To: Jake Moilanen; +Cc: linuxppc-dev, paulus
In-Reply-To: <20060607162540.f53bc270.moilanen@austin.ibm.com>
Hi Jake, some comments below:
Jake Moilanen wrote:
> Index: 2.6/drivers/pci/msi-rtas.c
> ===================================================================
> --- /dev/null 1970-01-01 00:00:00.000000000 +0000
> +++ 2.6/drivers/pci/msi-rtas.c 2006-06-07 15:59:59.000000000 -0500
> @@ -0,0 +1,162 @@
> +/*
> + * Jake Moilanen <moilanen@austin.ibm.com>
> + * Copyright (C) 2006 IBM
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License
> + * as published by the Free Software Foundation; version 2 of the
> + * License.
> + *
> + */
> +
> +#include <linux/pci.h>
> +#include <linux/irq.h>
> +#include <asm/rtas.h>
> +#include <asm/hw_irq.h>
> +
> +int rtas_enable_msi(struct pci_dev* pdev)
> +{
> + static int seq_num = 1;
> + int i;
> + int rc;
> + int query_token = rtas_token("ibm,query-interrupt-source-number");
> + int devfn;
> + int busno;
> + u32 *reg;
> + int reglen;
> + int ret[3];
> + int dummy;
> + unsigned int virq;
> + unsigned int addr;
> + unsigned long buid = -1;
> + unsigned long wait_time;
> + struct device_node * dn;
> +
> + BUG_ON(!pdev);
> +
> + dn = pci_device_to_OF_node(pdev);
> +
> + if (!of_find_property(dn, "ibm,req#msi", &dummy))
> + return -ENOENT;
> +
> + reg = (u32 *) get_property(dn, "reg", ®len);
> + if (reg == NULL || reglen < 20)
> + return -ENXIO;
> +
> + devfn = (reg[0] >> 8) & 0xff;
> + busno = (reg[0] >> 16) & 0xff;
> +
> + buid = get_phb_buid(dn->parent);
> + addr = (busno << 16) | (devfn << 8);
> +
> + while (1) {
> + rc = rtas_call(rtas_token("ibm,change-msi"), 6, 3, ret, addr,
> + buid >> 32, buid & 0xffffffff,
> + 0, 0, seq_num);
> +
> + if (!rc)
> + break;
> + else if (rc == RTAS_BUSY)
> + udelay(1);
> + else if (rtas_is_extended_busy(rc)) {
> + wait_time = rtas_extended_busy_delay_time(rc);
> + udelay(wait_time * 1000);
> + } else {
> + printk(KERN_WARNING "error[%d]: getting the number of "
> + "MSI interrupts for %s\n", rc, dn->name);
> + return -EIO;
> + }
> +
> + seq_num = ret[1];
> + }
Please see John Rose's patch from a few days ago for handling RTAS
delays with msleep instead of udelay. As written, this loop could tie
up the cpu for an arbitrary amount of time, and it is this kind of
situation John's patch is intended to address.
> +
> + /* Return if there's no MSI interrupts */
> + if (!ret[0])
> + return -ENOENT;
> +
> + dn->n_intrs = ret[0];
> +
> + dn->intrs = kmalloc(dn->n_intrs * sizeof(*(dn->intrs)), GFP_KERNEL);
> + if (!dn->intrs) {
> + printk(KERN_WARNING "rtas_enable_msi: can't allocate space\n");
> + return -ENOMEM;
> + }
> +
> + for (i = 0; i < dn->n_intrs; i++) {
> + rc = rtas_call(query_token, 4, 3, ret, addr,
> + buid >> 32, buid & 0xffffffff, i);
> +
> + if (!rc) {
> + virq = virt_irq_create_mapping(ret[0]);
> +
> + dn->intrs[i].line = irq_offset_up(virq);
> + dn->intrs[i].sense = ret[1];
> + } else {
> + printk(KERN_WARNING "error[%d]: query-interrupt-source-number for %s\n",
> + rc, dn->name);
> + }
> + }
> +
> + /* Just give the first vector out for now */
> + pdev->irq = dn->intrs[0].line;
> +
> + return 0;
> +}
> +
> +void rtas_disable_msi(struct pci_dev* pdev)
> +{
> + static int seq_num = 1;
> + struct device_node * dn;
> + int rc;
> + int devfn;
> + int busno;
> + u32 *reg;
> + int reglen;
> + int ret[3];
> + int dummy;
> + unsigned int addr;
> + unsigned long buid = -1;
> + unsigned long wait_time;
> +
> + BUG_ON(!pdev);
> +
> + dn = pci_device_to_OF_node(pdev);
> +
> + if (!of_find_property(dn, "ibm,req#msi", &dummy))
> + return;
> +
> + reg = (u32 *) get_property(dn, "reg", ®len);
> + if (reg == NULL || reglen < 20)
> + return;
> +
> + devfn = (reg[0] >> 8) & 0xff;
> + busno = (reg[0] >> 16) & 0xff;
> +
> + buid = get_phb_buid(dn->parent);
> + addr = (busno << 16) | (devfn << 8);
> +
> + while (1) {
> + rc = rtas_call(rtas_token("ibm,change-msi"), 6, 3, ret, addr,
> + buid >> 32, buid & 0xffffffff,
> + 2, 0, seq_num);
> +
> + if (!rc)
> + break;
> + else if (rc == RTAS_BUSY)
> + udelay(1);
> + else if (rtas_is_extended_busy(rc)) {
> + wait_time = rtas_extended_busy_delay_time(rc);
> + udelay(wait_time * 1000);
> + } else {
> + printk(KERN_WARNING "error[%d]: setting the number of "
> + "MSI interrupts for %s\n", rc, dn->name);
> + return;
> + }
> +
> + seq_num = ret[1];
> + }
Same as above applies here.
> +
> + dn->n_intrs = 0;
> +
> + kfree(dn->intrs);
> +}
> Index: 2.6/drivers/pci/Kconfig
> ===================================================================
> --- 2.6.orig/drivers/pci/Kconfig 2006-06-07 15:29:55.000000000 -0500
> +++ 2.6/drivers/pci/Kconfig 2006-06-07 15:59:28.000000000 -0500
> @@ -4,7 +4,7 @@
> config PCI_MSI
> bool "Message Signaled Interrupts (MSI and MSI-X)"
> depends on PCI
> - depends on (X86_LOCAL_APIC && X86_IO_APIC) || IA64
> + depends on (X86_LOCAL_APIC && X86_IO_APIC) || IA64 || PPC_PSERIES
> help
> This allows device drivers to enable MSI (Message Signaled
> Interrupts). Message Signaled Interrupts enable a device to
> Index: 2.6/arch/powerpc/platforms/pseries/setup.c
> ===================================================================
> --- 2.6.orig/arch/powerpc/platforms/pseries/setup.c 2006-06-07 15:29:55.000000000 -0500
> +++ 2.6/arch/powerpc/platforms/pseries/setup.c 2006-06-07 15:59:28.000000000 -0500
> @@ -78,6 +78,8 @@
> #endif
>
> extern void find_udbg_vterm(void);
> +extern int rtas_enable_msi(struct pci_dev* pdev);
> +extern void rtas_disable_msi(struct pci_dev * pdev);
These belong in a header.
^ permalink raw reply
* Re: [PATCH] powerpc: oprofile support for POWER6
From: Segher Boessenkool @ 2006-06-07 22:59 UTC (permalink / raw)
To: Michael Neuling; +Cc: linuxppc-dev, paulus
In-Reply-To: <20060607012359.D59C467B37@ozlabs.org>
> /*
> - * SIHV / SIPR bits are only implemented on POWER4+ (GQ) and above.
> - * However we disable it on all POWER4 until we verify it works
> - * (I was seeing some strange behaviour last time I tried).
> - *
> - * It has been verified to work on POWER5 so we enable it there.
> - */
The patched code doesn't handle GQ at all. Is this on purpose? Add a
similar comment to the CPU feature tables perhaps?
Segher
^ permalink raw reply
* Re: Collecting hypervisor call stats
From: Segher Boessenkool @ 2006-06-07 22:57 UTC (permalink / raw)
To: Mike Kravetz; +Cc: Bryan Rosenburg, Christopher Yeoh, linuxppc-dev, Chris Yeoh
In-Reply-To: <20060606164646.GA3161@w-mikek2.ibm.com>
> Can you explain the need for barrier(s) before and after the call
> to the
> real routine? It usually takes me a couple days of thought to
> figure out
> exactly where these are needed. :)
The barriers make the timing ever so slightly more deterministic (not
more
"accurate" though), because it has a "sync" insn in it. The sc insn
to do
the actual hypervisor call is a synchronisation point itself of
course, as
probably some things around it are as well. So just blast-em away,
they do
slow down things, and you don't really care about a few cycles more
or less
reported, hypervisor calls are not that fast.
Segher
^ permalink raw reply
* [PATCH 10/10] Prevent duplicate memory reservations for the Device Tree blob itself.
From: Jon Loeliger @ 2006-06-07 22:48 UTC (permalink / raw)
To: linuxppc-dev@ozlabs.org
Signed-off-by: Jon Loeliger <jdl@freescale.com>
---
arch/powerpc/kernel/prom.c | 13 +++++++++++--
1 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/kernel/prom.c b/arch/powerpc/kernel/prom.c
index 969f4ab..0a2c2cb 100644
--- a/arch/powerpc/kernel/prom.c
+++ b/arch/powerpc/kernel/prom.c
@@ -1264,13 +1264,16 @@ static void __init early_reserve_mem(voi
{
u64 base, size;
u64 *reserve_map;
+ unsigned long self_base;
+ unsigned long self_size;
reserve_map = (u64 *)(((unsigned long)initial_boot_params) +
initial_boot_params->off_mem_rsvmap);
/* before we do anything, lets reserve the dt blob */
- lmb_reserve(__pa((unsigned long)initial_boot_params),
- initial_boot_params->totalsize);
+ self_base = __pa((unsigned long)initial_boot_params);
+ self_size = initial_boot_params->totalsize;
+ lmb_reserve(self_base, self_size);
#ifdef CONFIG_PPC32
/*
@@ -1286,6 +1289,9 @@ #ifdef CONFIG_PPC32
size_32 = *(reserve_map_32++);
if (size_32 == 0)
break;
+ /* skip if the reservation is for the blob */
+ if (base_32 == self_base && size_32 == self_size)
+ continue;
DBG("reserving: %x -> %x\n", base_32, size_32);
lmb_reserve(base_32, size_32);
}
@@ -1297,6 +1303,9 @@ #endif
size = *(reserve_map++);
if (size == 0)
break;
+ /* skip if the reservation is for the blob */
+ if (base == self_base && size == self_size)
+ continue;
DBG("reserving: %llx -> %llx\n", base, size);
lmb_reserve(base, size);
}
^ permalink raw reply related
* [PATCH 9/10] Add Vitesse 8244 PHY for MPC8641 HPCN platform.
From: Jon Loeliger @ 2006-06-07 22:45 UTC (permalink / raw)
To: linuxppc-dev@ozlabs.org, netdev, jeff
Signed-off-by: Kriston Carson <KristonCarson@freescale.com>
Signed-off-by: Xianghua Xiao <x.xiao@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>
---
drivers/net/Kconfig | 6 +-
drivers/net/phy/Kconfig | 5 ++
drivers/net/phy/Makefile | 1
drivers/net/phy/vitesse.c | 136 +++++++++++++++++++++++++++++++++++++++++++++
4 files changed, 145 insertions(+), 3 deletions(-)
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index bdaaad8..c1c2758 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -2179,11 +2179,11 @@ config SPIDER_NET
config GIANFAR
tristate "Gianfar Ethernet"
- depends on 85xx || 83xx
+ depends on 85xx || 83xx || PPC_86xx
select PHYLIB
help
- This driver supports the Gigabit TSEC on the MPC85xx
- family of chips, and the FEC on the 8540
+ This driver supports the Gigabit TSEC on the MPC83xx, MPC85xx,
+ and MPC86xx family of chips, and the FEC on the 8540.
config GFAR_NAPI
bool "NAPI Support"
diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index fa39b94..76e51b1 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -44,6 +44,11 @@ config CICADA_PHY
depends on PHYLIB
---help---
Currently supports the cis8204
+config VITESSE_PHY
+ tristate "Drivers for the Vitesse PHYs"
+ depends on PHYLIB
+ ---help---
+ Currently supports the vsc8244
endmenu
diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
index e4116a5..a8d066e 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -8,3 +8,4 @@ obj-$(CONFIG_DAVICOM_PHY) += davicom.o
obj-$(CONFIG_CICADA_PHY) += cicada.o
obj-$(CONFIG_LXT_PHY) += lxt.o
obj-$(CONFIG_QSEMI_PHY) += qsemi.o
+obj-$(CONFIG_VITESSE_PHY) += vitesse.o
diff --git a/drivers/net/phy/vitesse.c b/drivers/net/phy/vitesse.c
new file mode 100644
index 0000000..45a605f
--- /dev/null
+++ b/drivers/net/phy/vitesse.c
@@ -0,0 +1,136 @@
+/*
+ * Driver for Vitesse PHYs
+ *
+ * Author: Kriston Carson
+ *
+ * Copyright (c) 2005 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ */
+
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/string.h>
+#include <linux/errno.h>
+#include <linux/unistd.h>
+#include <linux/slab.h>
+#include <linux/interrupt.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/skbuff.h>
+#include <linux/spinlock.h>
+#include <linux/mm.h>
+#include <linux/module.h>
+#include <linux/version.h>
+#include <linux/mii.h>
+#include <linux/ethtool.h>
+#include <linux/phy.h>
+
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/uaccess.h>
+
+/* Vitesse Extended Control Register 1 */
+#define MII_VSC8244_EXT_CON1 0x17
+#define MII_VSC8244_EXTCON1_INIT 0x0000
+
+/* Vitesse Interrupt Mask Register */
+#define MII_VSC8244_IMASK 0x19
+#define MII_VSC8244_IMASK_IEN 0x8000
+#define MII_VSC8244_IMASK_SPEED 0x4000
+#define MII_VSC8244_IMASK_LINK 0x2000
+#define MII_VSC8244_IMASK_DUPLEX 0x1000
+#define MII_VSC8244_IMASK_MASK 0xf000
+
+/* Vitesse Interrupt Status Register */
+#define MII_VSC8244_ISTAT 0x1a
+#define MII_VSC8244_ISTAT_STATUS 0x8000
+#define MII_VSC8244_ISTAT_SPEED 0x4000
+#define MII_VSC8244_ISTAT_LINK 0x2000
+#define MII_VSC8244_ISTAT_DUPLEX 0x1000
+
+/* Vitesse Auxiliary Control/Status Register */
+#define MII_VSC8244_AUX_CONSTAT 0x1c
+#define MII_VSC8244_AUXCONSTAT_INIT 0x0004
+#define MII_VSC8244_AUXCONSTAT_DUPLEX 0x0020
+#define MII_VSC8244_AUXCONSTAT_SPEED 0x0018
+#define MII_VSC8244_AUXCONSTAT_GBIT 0x0010
+#define MII_VSC8244_AUXCONSTAT_100 0x0008
+
+MODULE_DESCRIPTION("Vitesse PHY driver");
+MODULE_AUTHOR("Kriston Carson");
+MODULE_LICENSE("GPL");
+
+static int vsc824x_config_init(struct phy_device *phydev)
+{
+ int err;
+
+ err = phy_write(phydev, MII_VSC8244_AUX_CONSTAT,
+ MII_VSC8244_AUXCONSTAT_INIT);
+
+ if (err < 0)
+ return err;
+
+ err = phy_write(phydev, MII_VSC8244_EXT_CON1,
+ MII_VSC8244_EXTCON1_INIT);
+
+ return err;
+
+}
+
+static int vsc824x_ack_interrupt(struct phy_device *phydev)
+{
+ int err = phy_read(phydev, MII_VSC8244_ISTAT);
+
+ return (err < 0) ? err : 0;
+
+}
+
+static int vsc824x_config_intr(struct phy_device *phydev)
+{
+ int err;
+
+ if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
+ err = phy_write(phydev, MII_VSC8244_IMASK,
+ MII_VSC8244_IMASK_MASK);
+ else
+ err = phy_write(phydev, MII_VSC8244_IMASK, 0);
+
+ return err;
+
+}
+
+/* Vitesse 824x */
+static struct phy_driver vsc8244_driver = {
+ .phy_id = 0x000fc6c2,
+ .name = "Vitesse VSC8244",
+ .phy_id_mask = 0x000fffc0,
+ .features = PHY_GBIT_FEATURES,
+ .flags = PHY_HAS_INTERRUPT,
+ .config_init = &vsc824x_config_init,
+ .config_aneg = &genphy_config_aneg,
+ .read_status = &genphy_read_status,
+ .ack_interrupt = &vsc824x_ack_interrupt,
+ .config_intr = &vsc824x_config_intr,
+ .driver = { .owner = THIS_MODULE,},
+};
+
+static int __init vsc8244_init(void)
+{
+ return phy_driver_register(&vsc8244_driver);
+}
+
+static void __exit vsc8244_exit(void)
+{
+ phy_driver_unregister(&vsc8244_driver);
+}
+
+module_init(vsc8244_init);
+module_exit(vsc8244_exit);
^ permalink raw reply related
* [PATCH 8/10] Add default mpc8641_hpcn config file.
From: Jon Loeliger @ 2006-06-07 22:43 UTC (permalink / raw)
To: linuxppc-dev@ozlabs.org
Signed-off-by: Jon Loeliger <jdl@freescale.com>
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
---
arch/powerpc/configs/mpc8641_hpcn_defconfig | 923 +++++++++++++++++++++++++++
1 files changed, 923 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/configs/mpc8641_hpcn_defconfig b/arch/powerpc/configs/mpc8641_hpcn_defconfig
new file mode 100644
index 0000000..cf582a0
--- /dev/null
+++ b/arch/powerpc/configs/mpc8641_hpcn_defconfig
@@ -0,0 +1,923 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.17-rc3
+# Fri Jun 2 13:50:35 2006
+#
+# CONFIG_PPC64 is not set
+CONFIG_PPC32=y
+CONFIG_PPC_MERGE=y
+CONFIG_MMU=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_RWSEM_XCHGADD_ALGORITHM=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_PPC=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_GENERIC_NVRAM=y
+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+CONFIG_ARCH_MAY_HAVE_PC_FDC=y
+CONFIG_PPC_OF=y
+CONFIG_PPC_UDBG_16550=y
+CONFIG_GENERIC_TBSYNC=y
+# CONFIG_DEFAULT_UIMAGE is not set
+
+#
+# Processor support
+#
+# CONFIG_CLASSIC32 is not set
+# CONFIG_PPC_52xx is not set
+# CONFIG_PPC_82xx is not set
+# CONFIG_PPC_83xx is not set
+# CONFIG_PPC_85xx is not set
+CONFIG_PPC_86xx=y
+# CONFIG_40x is not set
+# CONFIG_44x is not set
+# CONFIG_8xx is not set
+# CONFIG_E200 is not set
+CONFIG_6xx=y
+CONFIG_PPC_FPU=y
+CONFIG_ALTIVEC=y
+CONFIG_PPC_STD_MMU=y
+CONFIG_PPC_STD_MMU_32=y
+CONFIG_SMP=y
+CONFIG_NR_CPUS=2
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+
+#
+# General setup
+#
+CONFIG_LOCALVERSION=""
+# CONFIG_LOCALVERSION_AUTO is not set
+# CONFIG_SWAP is not set
+# CONFIG_SYSVIPC is not set
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_SYSCTL=y
+# CONFIG_AUDIT is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+# CONFIG_CPUSETS is not set
+# CONFIG_RELAY is not set
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_EMBEDDED=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+CONFIG_KALLSYMS_EXTRA_PASS=y
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+# CONFIG_ELF_CORE is not set
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SHMEM=y
+# CONFIG_SLAB is not set
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+CONFIG_SLOB=y
+
+#
+# Loadable module support
+#
+# CONFIG_MODULES is not set
+
+#
+# Block layer
+#
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+# CONFIG_IOSCHED_AS is not set
+CONFIG_IOSCHED_DEADLINE=y
+# CONFIG_IOSCHED_CFQ is not set
+# CONFIG_DEFAULT_AS is not set
+CONFIG_DEFAULT_DEADLINE=y
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="deadline"
+CONFIG_MPIC=y
+# CONFIG_WANT_EARLY_SERIAL is not set
+CONFIG_PPC_INDIRECT_PCI_BE=y
+
+#
+# Platform Support
+#
+CONFIG_MPC8641_HPCN=y
+CONFIG_MPC8641=y
+CONFIG_PEX=y
+CONFIG_I8259_LEVEL_TRIGGER=y
+
+#
+# Kernel options
+#
+CONFIG_HIGHMEM=y
+# CONFIG_HZ_100 is not set
+# CONFIG_HZ_250 is not set
+CONFIG_HZ_1000=y
+CONFIG_HZ=1000
+CONFIG_PREEMPT_NONE=y
+# CONFIG_PREEMPT_VOLUNTARY is not set
+# CONFIG_PREEMPT is not set
+CONFIG_PREEMPT_BKL=y
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_IRQ_ALL_CPUS is not set
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4
+CONFIG_PROC_DEVICETREE=y
+# CONFIG_CMDLINE_BOOL is not set
+# CONFIG_PM is not set
+# CONFIG_SECCOMP is not set
+CONFIG_ISA_DMA_API=y
+
+#
+# Bus options
+#
+CONFIG_GENERIC_ISA_DMA=y
+CONFIG_PPC_I8259=y
+CONFIG_PPC_INDIRECT_PCI=y
+CONFIG_FSL_SOC=y
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+# CONFIG_PCI_DEBUG is not set
+
+#
+# PCCARD (PCMCIA/CardBus) support
+#
+# CONFIG_PCCARD is not set
+
+#
+# PCI Hotplug Support
+#
+# CONFIG_HOTPLUG_PCI is not set
+
+#
+# Advanced setup
+#
+# CONFIG_ADVANCED_OPTIONS is not set
+
+#
+# Default settings for advanced configuration options are used
+#
+CONFIG_HIGHMEM_START=0xfe000000
+CONFIG_LOWMEM_SIZE=0x30000000
+CONFIG_KERNEL_START=0xc0000000
+CONFIG_TASK_SIZE=0x80000000
+CONFIG_BOOT_LOAD=0x00800000
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+# CONFIG_NETDEBUG is not set
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_BIC=y
+CONFIG_IPV6=y
+# CONFIG_IPV6_PRIVACY is not set
+# CONFIG_IPV6_ROUTER_PREF is not set
+# CONFIG_INET6_AH is not set
+# CONFIG_INET6_ESP is not set
+# CONFIG_INET6_IPCOMP is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+# CONFIG_IPV6_TUNNEL is not set
+# CONFIG_NETFILTER is not set
+
+#
+# DCCP Configuration (EXPERIMENTAL)
+#
+# CONFIG_IP_DCCP is not set
+
+#
+# SCTP Configuration (EXPERIMENTAL)
+#
+# CONFIG_IP_SCTP is not set
+
+#
+# TIPC Configuration (EXPERIMENTAL)
+#
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_IEEE80211 is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+# CONFIG_DEBUG_DRIVER is not set
+
+#
+# Connector - unified userspace <-> kernelspace linker
+#
+# CONFIG_CONNECTOR is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+# CONFIG_MTD is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Plug and Play support
+#
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_SX8 is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=131072
+CONFIG_BLK_DEV_INITRD=y
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+
+#
+# ATA/ATAPI/MFM/RLL support
+#
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+
+#
+# Fusion MPT device support
+#
+# CONFIG_FUSION is not set
+
+#
+# IEEE 1394 (FireWire) support
+#
+# CONFIG_IEEE1394 is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+
+#
+# Macintosh device drivers
+#
+# CONFIG_WINDFARM is not set
+
+#
+# Network device support
+#
+CONFIG_NETDEVICES=y
+CONFIG_DUMMY=y
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+
+#
+# ARCnet devices
+#
+# CONFIG_ARCNET is not set
+
+#
+# PHY device support
+#
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+CONFIG_VITESSE_PHY=y
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_CASSINI is not set
+# CONFIG_NET_VENDOR_3COM is not set
+
+#
+# Tulip family network device support
+#
+# CONFIG_NET_TULIP is not set
+# CONFIG_HP100 is not set
+# CONFIG_NET_PCI is not set
+
+#
+# Ethernet (1000 Mbit)
+#
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_E1000 is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_R8169 is not set
+# CONFIG_SIS190 is not set
+# CONFIG_SKGE is not set
+# CONFIG_SKY2 is not set
+# CONFIG_SK98LIN is not set
+# CONFIG_TIGON3 is not set
+# CONFIG_BNX2 is not set
+CONFIG_GIANFAR=y
+# CONFIG_GFAR_NAPI is not set
+
+#
+# Ethernet (10000 Mbit)
+#
+# CONFIG_CHELSIO_T1 is not set
+# CONFIG_IXGB is not set
+# CONFIG_S2IO is not set
+
+#
+# Token Ring devices
+#
+# CONFIG_TR is not set
+
+#
+# Wireless LAN (non-hamradio)
+#
+# CONFIG_NET_RADIO is not set
+
+#
+# Wan interfaces
+#
+# CONFIG_WAN is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_SHAPER is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# Telephony Support
+#
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_TSDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+CONFIG_SERIO_I8042=y
+CONFIG_SERIO_SERPORT=y
+# CONFIG_SERIO_PCIPS2 is not set
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_SERIO_RAW is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_PCI=y
+CONFIG_SERIAL_8250_NR_UARTS=2
+CONFIG_SERIAL_8250_RUNTIME_UARTS=2
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_MANY_PORTS=y
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_8250_DETECT_IRQ=y
+CONFIG_SERIAL_8250_RSA=y
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_JSM is not set
+CONFIG_UNIX98_PTYS=y
+# CONFIG_LEGACY_PTYS is not set
+
+#
+# IPMI
+#
+# CONFIG_IPMI_HANDLER is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_NVRAM is not set
+# CONFIG_GEN_RTC is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_RAW_DRIVER is not set
+
+#
+# TPM devices
+#
+# CONFIG_TCG_TPM is not set
+# CONFIG_TELCLOCK is not set
+
+#
+# I2C support
+#
+CONFIG_I2C=y
+# CONFIG_I2C_CHARDEV is not set
+
+#
+# I2C Algorithms
+#
+# CONFIG_I2C_ALGOBIT is not set
+# CONFIG_I2C_ALGOPCF is not set
+# CONFIG_I2C_ALGOPCA is not set
+
+#
+# I2C Hardware Bus support
+#
+# CONFIG_I2C_ALI1535 is not set
+# CONFIG_I2C_ALI1563 is not set
+# CONFIG_I2C_ALI15X3 is not set
+# CONFIG_I2C_AMD756 is not set
+# CONFIG_I2C_AMD8111 is not set
+# CONFIG_I2C_I801 is not set
+# CONFIG_I2C_I810 is not set
+# CONFIG_I2C_PIIX4 is not set
+CONFIG_I2C_MPC=y
+# CONFIG_I2C_NFORCE2 is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_PROSAVAGE is not set
+# CONFIG_I2C_SAVAGE4 is not set
+# CONFIG_I2C_SIS5595 is not set
+# CONFIG_I2C_SIS630 is not set
+# CONFIG_I2C_SIS96X is not set
+# CONFIG_I2C_VIA is not set
+# CONFIG_I2C_VIAPRO is not set
+# CONFIG_I2C_VOODOO3 is not set
+# CONFIG_I2C_PCA_ISA is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_SENSORS_DS1337 is not set
+# CONFIG_SENSORS_DS1374 is not set
+CONFIG_SENSORS_EEPROM=y
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_M41T00 is not set
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+
+#
+# SPI support
+#
+# CONFIG_SPI is not set
+# CONFIG_SPI_MASTER is not set
+
+#
+# Dallas's 1-wire bus
+#
+# CONFIG_W1 is not set
+
+#
+# Hardware Monitoring support
+#
+# CONFIG_HWMON is not set
+# CONFIG_HWMON_VID is not set
+
+#
+# Misc devices
+#
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# Digital Video Broadcasting Devices
+#
+# CONFIG_DVB is not set
+
+#
+# Graphics support
+#
+# CONFIG_FB is not set
+
+#
+# Console display driver support
+#
+CONFIG_VGA_CONSOLE=y
+# CONFIG_VGACON_SOFT_SCROLLBACK is not set
+CONFIG_DUMMY_CONSOLE=y
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+CONFIG_USB_ARCH_HAS_EHCI=y
+# CONFIG_USB is not set
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+
+#
+# USB Gadget Support
+#
+# CONFIG_USB_GADGET is not set
+
+#
+# MMC/SD Card support
+#
+# CONFIG_MMC is not set
+
+#
+# LED devices
+#
+# CONFIG_NEW_LEDS is not set
+
+#
+# LED drivers
+#
+
+#
+# LED Triggers
+#
+
+#
+# InfiniBand support
+#
+# CONFIG_INFINIBAND is not set
+
+#
+# EDAC - error detection and reporting (RAS) (EXPERIMENTAL)
+#
+
+#
+# Real Time Clock
+#
+# CONFIG_RTC_CLASS is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_XATTR=y
+# CONFIG_EXT3_FS_POSIX_ACL is not set
+# CONFIG_EXT3_FS_SECURITY is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_INOTIFY is not set
+# CONFIG_QUOTA is not set
+# CONFIG_DNOTIFY is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_RAMFS=y
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+
+#
+# Network File Systems
+#
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+# CONFIG_NFS_DIRECTIO is not set
+CONFIG_NFSD=y
+# CONFIG_NFSD_V3 is not set
+CONFIG_NFSD_TCP=y
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_EXPORTFS=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+# CONFIG_9P_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+CONFIG_LDM_PARTITION=y
+# CONFIG_LDM_DEBUG is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+
+#
+# Native Language Support
+#
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+# CONFIG_NLS_CODEPAGE_437 is not set
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+# CONFIG_NLS_ISO8859_1 is not set
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+
+#
+# Library routines
+#
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+CONFIG_CRC32=y
+# CONFIG_LIBCRC32C is not set
+
+#
+# Instrumentation Support
+#
+# CONFIG_PROFILING is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+# CONFIG_MAGIC_SYSRQ is not set
+CONFIG_DEBUG_KERNEL=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_HIGHMEM is not set
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_UNWIND_INFO is not set
+CONFIG_FORCED_INLINING=y
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_DEBUGGER is not set
+# CONFIG_BDI_SWITCH is not set
+# CONFIG_BOOTX_TEXT is not set
+# CONFIG_PPC_EARLY_DEBUG_LPAR is not set
+# CONFIG_PPC_EARLY_DEBUG_G5 is not set
+# CONFIG_PPC_EARLY_DEBUG_RTAS is not set
+# CONFIG_PPC_EARLY_DEBUG_MAPLE is not set
+# CONFIG_PPC_EARLY_DEBUG_ISERIES is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+
+#
+# Cryptographic options
+#
+# CONFIG_CRYPTO is not set
+
+#
+# Hardware crypto devices
+#
^ permalink raw reply related
* [PATCH 7/10] Add use of mpc86xx.h include files in legacy header files.
From: Jon Loeliger @ 2006-06-07 22:42 UTC (permalink / raw)
To: linuxppc-dev@ozlabs.org
Signed-off-by: Xianghua Xiao <x.xiao@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>
---
include/asm-ppc/io.h | 2 ++
include/asm-ppc/ppc_sys.h | 2 ++
include/asm-ppc/serial.h | 2 ++
3 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/include/asm-ppc/io.h b/include/asm-ppc/io.h
index b919d8f..0802be9 100644
--- a/include/asm-ppc/io.h
+++ b/include/asm-ppc/io.h
@@ -37,6 +37,8 @@ #elif defined(CONFIG_83xx)
#include <asm/mpc83xx.h>
#elif defined(CONFIG_85xx)
#include <asm/mpc85xx.h>
+#elif defined(CONFIG_PPC_86xx)
+#include <asm/mpc86xx.h>
#elif defined(CONFIG_APUS)
#define _IO_BASE 0
#define _ISA_MEM_BASE 0
diff --git a/include/asm-ppc/ppc_sys.h b/include/asm-ppc/ppc_sys.h
index 40f197a..4eaf80d 100644
--- a/include/asm-ppc/ppc_sys.h
+++ b/include/asm-ppc/ppc_sys.h
@@ -27,6 +27,8 @@ #elif defined(CONFIG_83xx)
#include <asm/mpc83xx.h>
#elif defined(CONFIG_85xx)
#include <asm/mpc85xx.h>
+#elif defined(CONFIG_PPC_86xx)
+#include <asm/mpc86xx.h>
#elif defined(CONFIG_8xx)
#include <asm/mpc8xx.h>
#elif defined(CONFIG_PPC_MPC52xx)
diff --git a/include/asm-ppc/serial.h b/include/asm-ppc/serial.h
index b74af54..e819250 100644
--- a/include/asm-ppc/serial.h
+++ b/include/asm-ppc/serial.h
@@ -36,6 +36,8 @@ #elif defined(CONFIG_83xx)
#include <asm/mpc83xx.h>
#elif defined(CONFIG_85xx)
#include <asm/mpc85xx.h>
+#elif defined(CONFIG_PPC_86xx)
+#include <asm/mpc86xx.h>
#elif defined(CONFIG_RADSTONE_PPC7D)
#include <platforms/radstone_ppc7d.h>
#else
^ permalink raw reply related
* [PATCH 6/10] Add 8641 Register space and IRQ definitions.
From: Jon Loeliger @ 2006-06-07 22:40 UTC (permalink / raw)
To: linuxppc-dev@ozlabs.org
Signed-off-by: Jon Loeliger <jdl@freescale.com>
Signed-off-by: Jeff Brown <Jeff.Brown@freescale.com>
Signed-off-by: Xianghua Xiao <x.xiao@freescale.com>
---
include/asm-powerpc/immap_86xx.h | 199 ++++++++++++++++++++++++++++++++++++++
include/asm-powerpc/irq.h | 88 +++++++++++++++++
include/asm-powerpc/mpc86xx.h | 95 ++++++++++++++++++
include/asm-powerpc/reg.h | 1
4 files changed, 383 insertions(+), 0 deletions(-)
diff --git a/include/asm-powerpc/immap_86xx.h b/include/asm-powerpc/immap_86xx.h
new file mode 100644
index 0000000..d905b66
--- /dev/null
+++ b/include/asm-powerpc/immap_86xx.h
@@ -0,0 +1,199 @@
+/*
+ * MPC86xx Internal Memory Map
+ *
+ * Author: Jeff Brown
+ *
+ * Copyright 2004 Freescale Semiconductor, Inc
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ */
+
+#ifndef __ASM_POWERPC_IMMAP_86XX_H__
+#define __ASM_POWERPC_IMMAP_86XX_H__
+#ifdef __KERNEL__
+
+/* Eventually this should define all the IO block registers in 86xx */
+
+/* PCI Registers */
+typedef struct ccsr_pci {
+ uint cfg_addr; /* 0x.000 - PCI Configuration Address Register */
+ uint cfg_data; /* 0x.004 - PCI Configuration Data Register */
+ uint int_ack; /* 0x.008 - PCI Interrupt Acknowledge Register */
+ char res1[3060];
+ uint potar0; /* 0x.c00 - PCI Outbound Transaction Address Register 0 */
+ uint potear0; /* 0x.c04 - PCI Outbound Translation Extended Address Register 0 */
+ uint powbar0; /* 0x.c08 - PCI Outbound Window Base Address Register 0 */
+ char res2[4];
+ uint powar0; /* 0x.c10 - PCI Outbound Window Attributes Register 0 */
+ char res3[12];
+ uint potar1; /* 0x.c20 - PCI Outbound Transaction Address Register 1 */
+ uint potear1; /* 0x.c24 - PCI Outbound Translation Extended Address Register 1 */
+ uint powbar1; /* 0x.c28 - PCI Outbound Window Base Address Register 1 */
+ char res4[4];
+ uint powar1; /* 0x.c30 - PCI Outbound Window Attributes Register 1 */
+ char res5[12];
+ uint potar2; /* 0x.c40 - PCI Outbound Transaction Address Register 2 */
+ uint potear2; /* 0x.c44 - PCI Outbound Translation Extended Address Register 2 */
+ uint powbar2; /* 0x.c48 - PCI Outbound Window Base Address Register 2 */
+ char res6[4];
+ uint powar2; /* 0x.c50 - PCI Outbound Window Attributes Register 2 */
+ char res7[12];
+ uint potar3; /* 0x.c60 - PCI Outbound Transaction Address Register 3 */
+ uint potear3; /* 0x.c64 - PCI Outbound Translation Extended Address Register 3 */
+ uint powbar3; /* 0x.c68 - PCI Outbound Window Base Address Register 3 */
+ char res8[4];
+ uint powar3; /* 0x.c70 - PCI Outbound Window Attributes Register 3 */
+ char res9[12];
+ uint potar4; /* 0x.c80 - PCI Outbound Transaction Address Register 4 */
+ uint potear4; /* 0x.c84 - PCI Outbound Translation Extended Address Register 4 */
+ uint powbar4; /* 0x.c88 - PCI Outbound Window Base Address Register 4 */
+ char res10[4];
+ uint powar4; /* 0x.c90 - PCI Outbound Window Attributes Register 4 */
+ char res11[268];
+ uint pitar3; /* 0x.da0 - PCI Inbound Translation Address Register 3 */
+ char res12[4];
+ uint piwbar3; /* 0x.da8 - PCI Inbound Window Base Address Register 3 */
+ uint piwbear3; /* 0x.dac - PCI Inbound Window Base Extended Address Register 3 */
+ uint piwar3; /* 0x.db0 - PCI Inbound Window Attributes Register 3 */
+ char res13[12];
+ uint pitar2; /* 0x.dc0 - PCI Inbound Translation Address Register 2 */
+ char res14[4];
+ uint piwbar2; /* 0x.dc8 - PCI Inbound Window Base Address Register 2 */
+ uint piwbear2; /* 0x.dcc - PCI Inbound Window Base Extended Address Register 2 */
+ uint piwar2; /* 0x.dd0 - PCI Inbound Window Attributes Register 2 */
+ char res15[12];
+ uint pitar1; /* 0x.de0 - PCI Inbound Translation Address Register 1 */
+ char res16[4];
+ uint piwbar1; /* 0x.de8 - PCI Inbound Window Base Address Register 1 */
+ char res17[4];
+ uint piwar1; /* 0x.df0 - PCI Inbound Window Attributes Register 1 */
+ char res18[12];
+ uint err_dr; /* 0x.e00 - PCI Error Detect Register */
+ uint err_cap_dr; /* 0x.e04 - PCI Error Capture Disable Register */
+ uint err_en; /* 0x.e08 - PCI Error Enable Register */
+ uint err_attrib; /* 0x.e0c - PCI Error Attributes Capture Register */
+ uint err_addr; /* 0x.e10 - PCI Error Address Capture Register */
+ uint err_ext_addr; /* 0x.e14 - PCI Error Extended Address Capture Register */
+ uint err_dl; /* 0x.e18 - PCI Error Data Low Capture Register */
+ uint err_dh; /* 0x.e1c - PCI Error Data High Capture Register */
+ uint gas_timr; /* 0x.e20 - PCI Gasket Timer Register */
+ uint pci_timr; /* 0x.e24 - PCI Timer Register */
+ char res19[472];
+} ccsr_pci_t;
+
+/* PCI Express Registers */
+typedef struct ccsr_pex {
+ uint pex_config_addr; /* 0x.000 - PCI Express Configuration Address Register */
+ uint pex_config_data; /* 0x.004 - PCI Express Configuration Data Register */
+ char res1[4];
+ uint pex_otb_cpl_tor; /* 0x.00c - PCI Express Outbound completion timeout register */
+ uint pex_conf_tor; /* 0x.010 - PCI Express configuration timeout register */
+ char res2[12];
+ uint pex_pme_mes_dr; /* 0x.020 - PCI Express PME and message detect register */
+ uint pex_pme_mes_disr; /* 0x.024 - PCI Express PME and message disable register */
+ uint pex_pme_mes_ier; /* 0x.028 - PCI Express PME and message interrupt enable register */
+ uint pex_pmcr; /* 0x.02c - PCI Express power management command register */
+ char res3[3024];
+ uint pexotar0; /* 0x.c00 - PCI Express outbound translation address register 0 */
+ uint pexotear0; /* 0x.c04 - PCI Express outbound translation extended address register 0*/
+ char res4[8];
+ uint pexowar0; /* 0x.c10 - PCI Express outbound window attributes register 0*/
+ char res5[12];
+ uint pexotar1; /* 0x.c20 - PCI Express outbound translation address register 1 */
+ uint pexotear1; /* 0x.c24 - PCI Express outbound translation extended address register 1*/
+ uint pexowbar1; /* 0x.c28 - PCI Express outbound window base address register 1*/
+ char res6[4];
+ uint pexowar1; /* 0x.c30 - PCI Express outbound window attributes register 1*/
+ char res7[12];
+ uint pexotar2; /* 0x.c40 - PCI Express outbound translation address register 2 */
+ uint pexotear2; /* 0x.c44 - PCI Express outbound translation extended address register 2*/
+ uint pexowbar2; /* 0x.c48 - PCI Express outbound window base address register 2*/
+ char res8[4];
+ uint pexowar2; /* 0x.c50 - PCI Express outbound window attributes register 2*/
+ char res9[12];
+ uint pexotar3; /* 0x.c60 - PCI Express outbound translation address register 3 */
+ uint pexotear3; /* 0x.c64 - PCI Express outbound translation extended address register 3*/
+ uint pexowbar3; /* 0x.c68 - PCI Express outbound window base address register 3*/
+ char res10[4];
+ uint pexowar3; /* 0x.c70 - PCI Express outbound window attributes register 3*/
+ char res11[12];
+ uint pexotar4; /* 0x.c80 - PCI Express outbound translation address register 4 */
+ uint pexotear4; /* 0x.c84 - PCI Express outbound translation extended address register 4*/
+ uint pexowbar4; /* 0x.c88 - PCI Express outbound window base address register 4*/
+ char res12[4];
+ uint pexowar4; /* 0x.c90 - PCI Express outbound window attributes register 4*/
+ char res13[12];
+ char res14[256];
+ uint pexitar3; /* 0x.da0 - PCI Express inbound translation address register 3 */
+ char res15[4];
+ uint pexiwbar3; /* 0x.da8 - PCI Express inbound window base address register 3 */
+ uint pexiwbear3; /* 0x.dac - PCI Express inbound window base extended address register 3 */
+ uint pexiwar3; /* 0x.db0 - PCI Express inbound window attributes register 3 */
+ char res16[12];
+ uint pexitar2; /* 0x.dc0 - PCI Express inbound translation address register 2 */
+ char res17[4];
+ uint pexiwbar2; /* 0x.dc8 - PCI Express inbound window base address register 2 */
+ uint pexiwbear2; /* 0x.dcc - PCI Express inbound window base extended address register 2 */
+ uint pexiwar2; /* 0x.dd0 - PCI Express inbound window attributes register 2 */
+ char res18[12];
+ uint pexitar1; /* 0x.de0 - PCI Express inbound translation address register 2 */
+ char res19[4];
+ uint pexiwbar1; /* 0x.de8 - PCI Express inbound window base address register 2 */
+ uint pexiwbear1; /* 0x.dec - PCI Express inbound window base extended address register 2 */
+ uint pexiwar1; /* 0x.df0 - PCI Express inbound window attributes register 2 */
+ char res20[12];
+ uint pex_err_dr; /* 0x.e00 - PCI Express error detect register */
+ char res21[4];
+ uint pex_err_en; /* 0x.e08 - PCI Express error interrupt enable register */
+ char res22[4];
+ uint pex_err_disr; /* 0x.e10 - PCI Express error disable register */
+ char res23[12];
+ uint pex_err_cap_stat; /* 0x.e20 - PCI Express error capture status register */
+ char res24[4];
+ uint pex_err_cap_r0; /* 0x.e28 - PCI Express error capture register 0 */
+ uint pex_err_cap_r1; /* 0x.e2c - PCI Express error capture register 0 */
+ uint pex_err_cap_r2; /* 0x.e30 - PCI Express error capture register 0 */
+ uint pex_err_cap_r3; /* 0x.e34 - PCI Express error capture register 0 */
+} ccsr_pex_t;
+
+/* Global Utility Registers */
+typedef struct ccsr_guts {
+ uint porpllsr; /* 0x.0000 - POR PLL Ratio Status Register */
+ uint porbmsr; /* 0x.0004 - POR Boot Mode Status Register */
+ uint porimpscr; /* 0x.0008 - POR I/O Impedance Status and Control Register */
+ uint pordevsr; /* 0x.000c - POR I/O Device Status Register */
+ uint pordbgmsr; /* 0x.0010 - POR Debug Mode Status Register */
+ char res1[12];
+ uint gpporcr; /* 0x.0020 - General-Purpose POR Configuration Register */
+ char res2[12];
+ uint gpiocr; /* 0x.0030 - GPIO Control Register */
+ char res3[12];
+ uint gpoutdr; /* 0x.0040 - General-Purpose Output Data Register */
+ char res4[12];
+ uint gpindr; /* 0x.0050 - General-Purpose Input Data Register */
+ char res5[12];
+ uint pmuxcr; /* 0x.0060 - Alternate Function Signal Multiplex Control */
+ char res6[12];
+ uint devdisr; /* 0x.0070 - Device Disable Control */
+ char res7[12];
+ uint powmgtcsr; /* 0x.0080 - Power Management Status and Control Register */
+ char res8[12];
+ uint mcpsumr; /* 0x.0090 - Machine Check Summary Register */
+ char res9[12];
+ uint pvr; /* 0x.00a0 - Processor Version Register */
+ uint svr; /* 0x.00a4 - System Version Register */
+ char res10[3416];
+ uint clkocr; /* 0x.0e00 - Clock Out Select Register */
+ char res11[12];
+ uint ddrdllcr; /* 0x.0e10 - DDR DLL Control Register */
+ char res12[12];
+ uint lbcdllcr; /* 0x.0e20 - LBC DLL Control Register */
+ char res13[61916];
+} ccsr_guts_t;
+
+#endif /* __ASM_POWERPC_IMMAP_86XX_H__ */
+#endif /* __KERNEL__ */
diff --git a/include/asm-powerpc/irq.h b/include/asm-powerpc/irq.h
index 7bc6d73..997d2e8 100644
--- a/include/asm-powerpc/irq.h
+++ b/include/asm-powerpc/irq.h
@@ -348,6 +348,94 @@ #define SIU_INT_PC2 ((uint)0x3d+CPM_IRQ
#define SIU_INT_PC1 ((uint)0x3e+CPM_IRQ_OFFSET)
#define SIU_INT_PC0 ((uint)0x3f+CPM_IRQ_OFFSET)
+#elif defined(CONFIG_PPC_86xx)
+#include <asm/mpc86xx.h>
+
+#define NR_EPIC_INTS 48
+#ifndef NR_8259_INTS
+#define NR_8259_INTS 16 /*ULI 1575 can route 12 interrupts */
+#endif
+#define NUM_8259_INTERRUPTS NR_8259_INTS
+
+#ifndef I8259_OFFSET
+#define I8259_OFFSET 0
+#endif
+
+#define NR_IRQS 256
+
+/* Internal IRQs on MPC86xx OpenPIC */
+
+#ifndef MPC86xx_OPENPIC_IRQ_OFFSET
+#define MPC86xx_OPENPIC_IRQ_OFFSET NR_8259_INTS
+#endif
+
+/* The 48 internal sources */
+#define MPC86xx_IRQ_NULL ( 0 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_MCM ( 1 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_DDR ( 2 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_LBC ( 3 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_DMA0 ( 4 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_DMA1 ( 5 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_DMA2 ( 6 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_DMA3 ( 7 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_PEX1 ( 8 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_PEX2 ( 9 + MPC86xx_OPENPIC_IRQ_OFFSET)
+
+/* no 10,11 */
+#define MPC86xx_IRQ_UART2 (12 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_TSEC1_TX (13 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_TSEC1_RX (14 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_TSEC3_TX (15 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_TSEC3_RX (16 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_TSEC3_ERROR (17 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_TSEC1_ERROR (18 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_TSEC2_TX (19 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_TSEC2_RX (20 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_TSEC4_TX (21 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_TSEC4_RX (22 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_TSEC4_ERROR (23 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_TSEC2_ERROR (24 + MPC86xx_OPENPIC_IRQ_OFFSET)
+/* no 25 */
+#define MPC86xx_IRQ_UART1 (26 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_IIC (27 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_PERFMON (28 + MPC86xx_OPENPIC_IRQ_OFFSET)
+/* no 29,30,31 */
+#define MPC86xx_IRQ_SRIO_ERROR (32 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_SRIO_OUT_BELL (33 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_SRIO_IN_BELL (34 + MPC86xx_OPENPIC_IRQ_OFFSET)
+/* no 35,36 */
+#define MPC86xx_IRQ_SRIO_OUT_MSG1 (37 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_SRIO_IN_MSG1 (38 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_SRIO_OUT_MSG2 (39 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_SRIO_IN_MSG2 (40 + MPC86xx_OPENPIC_IRQ_OFFSET)
+
+/* The 12 external interrupt lines */
+#define MPC86xx_IRQ_EXT_BASE 48
+#define MPC86xx_IRQ_EXT0 (0 + MPC86xx_IRQ_EXT_BASE \
+ + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_EXT1 (1 + MPC86xx_IRQ_EXT_BASE \
+ + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_EXT2 (2 + MPC86xx_IRQ_EXT_BASE \
+ + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_EXT3 (3 + MPC86xx_IRQ_EXT_BASE \
+ + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_EXT4 (4 + MPC86xx_IRQ_EXT_BASE \
+ + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_EXT5 (5 + MPC86xx_IRQ_EXT_BASE \
+ + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_EXT6 (6 + MPC86xx_IRQ_EXT_BASE \
+ + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_EXT7 (7 + MPC86xx_IRQ_EXT_BASE \
+ + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_EXT8 (8 + MPC86xx_IRQ_EXT_BASE \
+ + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_EXT9 (9 + MPC86xx_IRQ_EXT_BASE \
+ + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_EXT10 (10 + MPC86xx_IRQ_EXT_BASE \
+ + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_EXT11 (11 + MPC86xx_IRQ_EXT_BASE \
+ + MPC86xx_OPENPIC_IRQ_OFFSET)
+
#else /* CONFIG_40x + CONFIG_8xx */
/*
* this is the # irq's for all ppc arch's (pmac/chrp/prep)
diff --git a/include/asm-powerpc/mpc86xx.h b/include/asm-powerpc/mpc86xx.h
new file mode 100644
index 0000000..03942a2
--- /dev/null
+++ b/include/asm-powerpc/mpc86xx.h
@@ -0,0 +1,95 @@
+/*
+ * MPC86xx definitions
+ *
+ * Author: Jeff Brown
+ *
+ * Copyright 2004 Freescale Semiconductor, Inc
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#ifdef __KERNEL__
+#ifndef __ASM_POWERPC_MPC86xx_H__
+#define __ASM_POWERPC_MPC86xx_H__
+
+#include <linux/config.h>
+#include <asm/mmu.h>
+
+#ifdef CONFIG_PPC_86xx
+
+#ifdef CONFIG_MPC8641_HPCN
+#include <platforms/86xx/mpc8641_hpcn.h>
+#endif
+
+#define _IO_BASE isa_io_base
+#define _ISA_MEM_BASE isa_mem_base
+#ifdef CONFIG_PCI
+#define PCI_DRAM_OFFSET pci_dram_offset
+#else
+#define PCI_DRAM_OFFSET 0
+#endif
+
+#define CPU0_BOOT_RELEASE 0x01000000
+#define CPU1_BOOT_RELEASE 0x02000000
+#define CPU_ALL_RELEASED (CPU0_BOOT_RELEASE | CPU1_BOOT_RELEASE)
+#define MCM_PORT_CONFIG_OFFSET 0x1010
+
+/* Offset from CCSRBAR */
+#define MPC86xx_DMA_OFFSET (0x21000)
+#define MPC86xx_DMA_SIZE (0x01000)
+#define MPC86xx_DMA0_OFFSET (0x21100)
+#define MPC86xx_DMA0_SIZE (0x00080)
+#define MPC86xx_DMA1_OFFSET (0x21180)
+#define MPC86xx_DMA1_SIZE (0x00080)
+#define MPC86xx_DMA2_OFFSET (0x21200)
+#define MPC86xx_DMA2_SIZE (0x00080)
+#define MPC86xx_DMA3_OFFSET (0x21280)
+#define MPC86xx_DMA3_SIZE (0x00080)
+
+#define MPC86xx_GUTS_OFFSET (0xe0000)
+#define MPC86xx_GUTS_SIZE (0x01000)
+
+#define MPC86xx_OPENPIC_OFFSET (0x40000)
+#define MPC86xx_OPENPIC_SIZE (0x40000)
+#define MPC86xx_PEX1_OFFSET (0x08000)
+#define MPC86xx_PEX1_SIZE (0x01000)
+#define MPC86xx_PEX2_OFFSET (0x09000)
+#define MPC86xx_PEX2_SIZE (0x01000)
+#define MPC86xx_PERFMON_OFFSET (0xe1000)
+#define MPC86xx_PERFMON_SIZE (0x01000)
+#define MPC86xx_UART0_OFFSET (0x04500)
+#define MPC86xx_UART0_SIZE (0x00100)
+#define MPC86xx_UART1_OFFSET (0x04600)
+#define MPC86xx_UART1_SIZE (0x00100)
+#define MPC86xx_MCM_OFFSET (0x00000)
+#define MPC86xx_MCM_SIZE (0x02000)
+
+#define MPC86xx_CCSRBAR_SIZE (1024*1024)
+
+/* Let modules/drivers get at CCSRBAR */
+extern phys_addr_t get_ccsrbar(void);
+
+#ifdef MODULE
+#define CCSRBAR get_ccsrbar()
+#else
+#define CCSRBAR BOARD_CCSRBAR
+#endif
+
+enum ppc_sys_devices {
+ MPC86xx_TSEC1,
+ MPC86xx_TSEC2,
+ MPC86xx_TSEC3,
+ MPC86xx_TSEC4,
+ MPC86xx_DUART,
+ MPC86xx_MDIO,
+ MPC86xx_IIC1,
+ MPC86xx_IIC2,
+ NUM_PPC_SYS_DEVS,
+};
+
+#endif /* CONFIG_PPC_86xx */
+#endif /* __ASM_POWERPC_MPC86xx_H__ */
+#endif /* __KERNEL__ */
diff --git a/include/asm-powerpc/reg.h b/include/asm-powerpc/reg.h
index 0257189..1b1548f 100644
--- a/include/asm-powerpc/reg.h
+++ b/include/asm-powerpc/reg.h
@@ -543,6 +543,7 @@ #define PVR_7410 0x800C0000
#define PVR_7450 0x80000000
#define PVR_8540 0x80200000
#define PVR_8560 0x80200000
+#define PVR_8641 0x80040000
/*
* For the 8xx processors, all of them report the same PVR family for
* the PowerPC core. The various versions of these processors must be
^ permalink raw reply related
* [PATCH 5/10] Add 8641 CPU and i8259 Setup
From: Jon Loeliger @ 2006-06-07 22:39 UTC (permalink / raw)
To: linuxppc-dev@ozlabs.org
Add 8641 CPU table entry.
Add SMP CPU id determination and clear BATS.
Use level triggers on i8259.
Signed-off-by: Wei Zhang <Wei.Zhang@freescale.com>
Signed-off-by: Xianghua Xiao <x.xiao@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>
---
arch/powerpc/kernel/cputable.c | 12 ++++++++++++
arch/powerpc/kernel/head_32.S | 15 +++++++++++++++
arch/powerpc/sysdev/i8259.c | 5 +++++
3 files changed, 32 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c
index 0c487ee..2c8ac7e 100644
--- a/arch/powerpc/kernel/cputable.c
+++ b/arch/powerpc/kernel/cputable.c
@@ -704,6 +704,18 @@ #if CLASSIC_PPC
.oprofile_type = PPC_OPROFILE_G4,
.platform = "ppc7450",
},
+ { /* 8641 */
+ .pvr_mask = 0xffffffff,
+ .pvr_value = 0x80040010,
+ .cpu_name = "8641",
+ .cpu_features = CPU_FTRS_7447A,
+ .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP,
+ .icache_bsize = 32,
+ .dcache_bsize = 32,
+ .num_pmcs = 6,
+ .cpu_setup = __setup_cpu_745x
+ },
+
{ /* 82xx (8240, 8245, 8260 are all 603e cores) */
.pvr_mask = 0x7fff0000,
.pvr_value = 0x00810000,
diff --git a/arch/powerpc/kernel/head_32.S b/arch/powerpc/kernel/head_32.S
index a0579e8..e8f6bfa 100644
--- a/arch/powerpc/kernel/head_32.S
+++ b/arch/powerpc/kernel/head_32.S
@@ -224,6 +224,10 @@ turn_on_mmu:
li r3,1 /* MTX only has 1 cpu */
.globl __secondary_hold
__secondary_hold:
+#ifdef CONFIG_PPC_86xx
+ /* get the cpu id */
+ mfspr r3, SPRN_PIR
+#endif
/* tell the master we're here */
stw r3,__secondary_hold_acknowledge@l(0)
#ifdef CONFIG_SMP
@@ -348,6 +352,16 @@ #define EXC_XFER_EE_LITE(n, hdlr) \
#if defined(CONFIG_GEMINI) && defined(CONFIG_SMP)
. = 0x100
b __secondary_start_gemini
+#endif
+/* we need to ensure that the address translation is disabled */
+#if defined(CONFIG_PPC_86xx) && defined(CONFIG_SMP)
+ . = 0x100
+ mfmsr r3
+ andi. r0, r3, (MSR_IR | MSR_DR)
+ andc r3, r3, r0
+ mtmsr r3
+ isync
+ b __secondary_hold
#else
EXCEPTION(0x100, Reset, unknown_exception, EXC_XFER_STD)
#endif
@@ -1019,6 +1033,7 @@ #endif /* CONFIG_6xx */
stw r0,0(r3)
/* load up the MMU */
+ bl clear_bats
bl load_up_mmu
/* ptr to phys current thread */
diff --git a/arch/powerpc/sysdev/i8259.c b/arch/powerpc/sysdev/i8259.c
index b7ac32f..9b755e1 100644
--- a/arch/powerpc/sysdev/i8259.c
+++ b/arch/powerpc/sysdev/i8259.c
@@ -201,6 +201,11 @@ void __init i8259_init(unsigned long int
outb(0x0B, 0x20);
outb(0x0B, 0xA0);
+#ifdef CONFIG_I8259_LEVEL_TRIGGER
+ outb(0xfa, 0x4d0); /* level triggered */
+ outb(0xde, 0x4d1);
+#endif
+
/* Mask all interrupts */
outb(cached_A1, 0xA1);
outb(cached_21, 0x21);
^ permalink raw reply related
* [PATCH 4/10] Guard L3CR references with CPU_FTR_L3CR.
From: Jon Loeliger @ 2006-06-07 22:38 UTC (permalink / raw)
To: linuxppc-dev@ozlabs.org
Signed-off-by: Jon Loeliger <jdl@freescale.com>
---
arch/powerpc/kernel/cpu_setup_6xx.S | 2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/kernel/cpu_setup_6xx.S b/arch/powerpc/kernel/cpu_setup_6xx.S
index 55ed771..365381f 100644
--- a/arch/powerpc/kernel/cpu_setup_6xx.S
+++ b/arch/powerpc/kernel/cpu_setup_6xx.S
@@ -210,9 +210,11 @@ setup_745x_specifics:
* the firmware. If any, we disable NAP capability as
* it's known to be bogus on rev 2.1 and earlier
*/
+BEGIN_FTR_SECTION
mfspr r11,SPRN_L3CR
andis. r11,r11,L3CR_L3E@h
beq 1f
+END_FTR_SECTION_IFSET(CPU_FTR_L3CR)
lwz r6,CPU_SPEC_FEATURES(r5)
andi. r0,r6,CPU_FTR_L3_DISABLE_NAP
beq 1f
^ permalink raw reply related
* [PATCH 3/10] Add MPC8641 HPCN PCI and PCI-Express files.
From: Jon Loeliger @ 2006-06-07 22:37 UTC (permalink / raw)
To: linuxppc-dev@ozlabs.org
Signed-off-by: Xianghua Xiao <x.xiao@freescale.com>
Signed-off-by: Wei Zhang <Wei.Zhang@freescale.com>
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>
---
arch/powerpc/platforms/86xx/pci.c | 213 +++++++++++++++++++++++++++++++++++++
arch/powerpc/platforms/86xx/pex.c | 173 ++++++++++++++++++++++++++++++
2 files changed, 386 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/platforms/86xx/pci.c b/arch/powerpc/platforms/86xx/pci.c
new file mode 100644
index 0000000..eff6f28
--- /dev/null
+++ b/arch/powerpc/platforms/86xx/pci.c
@@ -0,0 +1,213 @@
+/*
+ * MPC86XX pci setup code
+ *
+ * Recode: ZHANG WEI <wei.zhang@freescale.com>
+ * Initial author: Xianghua Xiao <x.xiao@freescale.com>
+ *
+ * Copyright 2006 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/config.h>
+#include <linux/types.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/pci.h>
+#include <linux/serial.h>
+
+#include <asm/system.h>
+#include <asm/atomic.h>
+#include <asm/io.h>
+#include <asm/prom.h>
+#include <asm/immap_86xx.h>
+#include <asm/pci-bridge.h>
+#include <sysdev/fsl_soc.h>
+
+#include "mpc86xx.h"
+
+
+#ifdef CONFIG_PEX
+static void __init
+mpc86xx_setup_pex(struct pci_controller *hose)
+{
+ volatile struct ccsr_pex *pex;
+ u16 cmd;
+ unsigned int temps;
+ phys_addr_t immr;
+
+ immr = get_immrbase();
+
+ pex = ioremap(immr + MPC86xx_PEX_OFFSET, MPC86xx_PEX_SIZE);
+
+ early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd);
+ cmd |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY
+ | PCI_COMMAND_IO;
+ early_write_config_word(hose, 0, 0, PCI_COMMAND, cmd);
+
+ early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80);
+
+ /* PEX Bus, Fix the MPC8641D host bridge's location to bus 0xFF. */
+ early_read_config_dword(hose, 0, 0, PCI_PRIMARY_BUS, &temps);
+ temps = (temps & 0xff000000) | (0xff) | (0x0 << 8) | (0xfe << 16);
+ early_write_config_dword(hose, 0, 0, PCI_PRIMARY_BUS, temps);
+
+ /* Disable all windows (except pexowar0 since its ignored) */
+ pex->pexowar1 = 0;
+ pex->pexowar2 = 0;
+ pex->pexowar3 = 0;
+ pex->pexowar4 = 0;
+ pex->pexiwar1 = 0;
+ pex->pexiwar2 = 0;
+ pex->pexiwar3 = 0;
+
+ /* Setup Phys:PEX 1:1 outbound mem window @ MPC86XX_PEX_LOWER_MEM */
+ pex->pexotar1 = (MPC86XX_PEX_LOWER_MEM >> 12) & 0x000fffff;
+ pex->pexotear1 = 0x00000000;
+ pex->pexowbar1 = (MPC86XX_PEX_LOWER_MEM >> 12) & 0x000fffff;
+ /* Enable, Mem R/W */
+ pex->pexowar1 = 0x80044000 |
+ (__ilog2(MPC86XX_PEX_UPPER_MEM - MPC86XX_PEX_LOWER_MEM + 1) - 1);
+
+ /* Setup outboud IO windows @ MPC86XX_PEX_IO_BASE */
+ pex->pexotar2 = (MPC86XX_PEX_LOWER_IO >> 12) & 0x000fffff;
+ pex->pexotear2 = 0x00000000;
+ pex->pexowbar2 = (MPC86XX_PEX_IO_BASE >> 12) & 0x000fffff;
+ /* Enable, IO R/W */
+ pex->pexowar2 = 0x80088000 | (__ilog2(MPC86XX_PEX_IO_SIZE) - 1);
+
+ /* Setup 2G inbound Memory Window @ 0 */
+ pex->pexitar1 = 0x00000000;
+ pex->pexiwbar1 = 0x00000000;
+ /* Enable, Prefetch, Local Mem, Snoop R/W, 2G */
+ pex->pexiwar1 = 0xa0f5501e;
+}
+
+int __init add_bridge(struct device_node *dev)
+{
+ int len;
+ struct pci_controller *hose;
+ struct resource rsrc;
+ int *bus_range;
+ int has_address = 0;
+
+ pr_debug("Adding PEX host bridge %s\n", dev->full_name);
+
+ /* Fetch host bridge registers address */
+ has_address = (of_address_to_resource(dev, 0, &rsrc) == 0);
+
+ /* Get bus range if any */
+ bus_range = (int *) get_property(dev, "bus-range", &len);
+ if (bus_range == NULL || len < 2 * sizeof(int))
+ printk(KERN_WARNING "Can't get bus-range for %s, assume"
+ " bus 0\n", dev->full_name);
+
+ hose = pcibios_alloc_controller();
+ if (!hose)
+ return -ENOMEM;
+ hose->arch_data = dev;
+ hose->set_cfg_type = 1;
+
+ /* last_busno = 0xfe cause by PEX bug */
+ hose->first_busno = bus_range ? bus_range[0] : 0x0;
+ hose->last_busno = bus_range ? bus_range[1] : 0xfe;
+
+ setup_indirect_pex(hose, rsrc.start, rsrc.start + 0x4);
+
+ /* Setup the first PEX controller. */
+ if ((rsrc.start & 0xfffff) == 0x8000)
+ mpc86xx_setup_pex(hose);
+
+ printk(KERN_INFO "Found MPC86xx PEX host bridge at 0x%08lx. "
+ "Firmware bus number: %d->%d\n",
+ rsrc.start, hose->first_busno, hose->last_busno);
+
+ pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
+ hose, hose->cfg_addr, hose->cfg_data);
+
+ /* Interpret the "ranges" property */
+ /* This also maps the I/O region and sets isa_io/mem_base */
+ pci_process_bridge_OF_ranges(hose, dev, 1);
+
+ return 0;
+}
+#endif /* CONFIG_PEX */
+
+static void __devinit quirk_ali1575(struct pci_dev *dev)
+{
+ /*
+ * ALI1575 interrupts route table setup:
+ *
+ * IRQ pin IRQ#
+ * PIRQA ---- 3
+ * PIRQB ---- 4
+ * PIRQC ---- 5
+ * PIRQD ---- 6
+ * PIRQE ---- 9
+ * PIRQF ---- 10
+ * PIRQG ---- 11
+ * PIRQH ---- 12
+ *
+ * interrupts for PCI slot0 -- PIRQA / PIRQB / PIRQC / PIRQD
+ * PCI slot1 -- PIRQB / PIRQC / PIRQD / PIRQA
+ */
+ pci_write_config_dword(dev, 0x48, 0xb9317542);
+
+ /* USB 1.1 OHCI controller 1, interrupt: PIRQE */
+ pci_write_config_byte(dev, 0x86, 0x0c);
+
+ /* USB 1.1 OHCI controller 2, interrupt: PIRQF */
+ pci_write_config_byte(dev, 0x87, 0x0d);
+
+ /* USB 1.1 OHCI controller 3, interrupt: PIRQH */
+ pci_write_config_byte(dev, 0x88, 0x0f);
+
+ /* USB 2.0 controller, interrupt: PIRQ7 */
+ pci_write_config_byte(dev, 0x74, 0x06);
+
+ /* Audio controller, interrupt: PIRQE */
+ pci_write_config_byte(dev, 0x8a, 0x0c);
+
+ /* Modem controller, interrupt: PIRQF */
+ pci_write_config_byte(dev, 0x8b, 0x0d);
+
+ /* HD audio controller, interrupt: PIRQG */
+ pci_write_config_byte(dev, 0x8c, 0x0e);
+
+ /* Serial ATA interrupt: PIRQD */
+ pci_write_config_byte(dev, 0x8d, 0x0b);
+
+ /* SMB interrupt: PIRQH */
+ pci_write_config_byte(dev, 0x8e, 0x0f);
+
+ /* PMU ACPI SCI interrupt: PIRQH */
+ pci_write_config_byte(dev, 0x8f, 0x0f);
+
+}
+
+static void __devinit quirk_uli5288(struct pci_dev *dev)
+{
+ unsigned char c;
+
+ pci_read_config_byte(dev,0x83,&c);
+ c |= 0x80;
+ pci_write_config_byte(dev, 0x83, c);
+
+ pci_write_config_byte(dev, 0x09, 0x01);
+ pci_write_config_byte(dev, 0x0a, 0x06);
+
+ pci_read_config_byte(dev,0x83,&c);
+ c &= 0x7f;
+ pci_write_config_byte(dev, 0x83, c);
+
+ pci_read_config_byte(dev,0x84,&c);
+ c |= 0x01;
+ pci_write_config_byte(dev, 0x84, c);
+}
+
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x1575, quirk_ali1575);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5288, quirk_uli5288);
+
diff --git a/arch/powerpc/platforms/86xx/pex.c b/arch/powerpc/platforms/86xx/pex.c
new file mode 100644
index 0000000..2624d3c
--- /dev/null
+++ b/arch/powerpc/platforms/86xx/pex.c
@@ -0,0 +1,173 @@
+/*
+ * Support for indirect PCI bridges.
+ *
+ * Copyright (C) 1998 Gabriel Paubert.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ *
+ * "Temporary" MPC8548 Errata file -
+ * The standard indirect_pci code should work with future silicon versions.
+ */
+
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/delay.h>
+#include <linux/string.h>
+#include <linux/init.h>
+#include <linux/bootmem.h>
+
+#include <asm/io.h>
+#include <asm/prom.h>
+#include <asm/pci-bridge.h>
+#include <asm/machdep.h>
+
+#include "mpc86xx.h"
+
+#define PCI_CFG_OUT out_be32
+
+/* ERRATA PCI-Ex 14 PEX Controller timeout */
+#define PEX_FIX out_be32(hose->cfg_addr+0x4, 0x0400ffff)
+
+
+static int
+indirect_read_config_pex(struct pci_bus *bus, unsigned int devfn, int offset,
+ int len, u32 *val)
+{
+ struct pci_controller *hose = bus->sysdata;
+ volatile void __iomem *cfg_data;
+ u32 temp;
+
+ if (ppc_md.pci_exclude_device)
+ if (ppc_md.pci_exclude_device(bus->number, devfn))
+ return PCIBIOS_DEVICE_NOT_FOUND;
+
+ /* Possible artifact of CDCpp50937 needs further investigation */
+ if (devfn != 0x0 && bus->number == 0xff)
+ return PCIBIOS_DEVICE_NOT_FOUND;
+
+ PEX_FIX;
+ if (bus->number == 0xff) {
+ PCI_CFG_OUT(hose->cfg_addr,
+ (0x80000000 | ((offset & 0xf00) << 16) |
+ ((bus->number - hose->bus_offset) << 16)
+ | (devfn << 8) | ((offset & 0xfc) )));
+ } else {
+ PCI_CFG_OUT(hose->cfg_addr,
+ (0x80000001 | ((offset & 0xf00) << 16) |
+ ((bus->number - hose->bus_offset) << 16)
+ | (devfn << 8) | ((offset & 0xfc) )));
+ }
+
+ /*
+ * Note: the caller has already checked that offset is
+ * suitably aligned and that len is 1, 2 or 4.
+ */
+ /* ERRATA PCI-Ex 12 - Configuration Address/Data Alignment */
+ cfg_data = hose->cfg_data;
+ PEX_FIX;
+ temp = in_le32(cfg_data);
+ switch (len) {
+ case 1:
+ *val = (temp >> (((offset & 3))*8)) & 0xff;
+ break;
+ case 2:
+ *val = (temp >> (((offset & 3))*8)) & 0xffff;
+ break;
+ default:
+ *val = temp;
+ break;
+ }
+ return PCIBIOS_SUCCESSFUL;
+}
+
+static int
+indirect_write_config_pex(struct pci_bus *bus, unsigned int devfn, int offset,
+ int len, u32 val)
+{
+ struct pci_controller *hose = bus->sysdata;
+ volatile void __iomem *cfg_data;
+ u32 temp;
+
+ if (ppc_md.pci_exclude_device)
+ if (ppc_md.pci_exclude_device(bus->number, devfn))
+ return PCIBIOS_DEVICE_NOT_FOUND;
+
+ /* Possible artifact of CDCpp50937 needs further investigation */
+ if (devfn != 0x0 && bus->number == 0xff)
+ return PCIBIOS_DEVICE_NOT_FOUND;
+
+ PEX_FIX;
+ if (bus->number == 0xff) {
+ PCI_CFG_OUT(hose->cfg_addr,
+ (0x80000000 | ((offset & 0xf00) << 16) |
+ ((bus->number - hose->bus_offset) << 16)
+ | (devfn << 8) | ((offset & 0xfc) )));
+ } else {
+ PCI_CFG_OUT(hose->cfg_addr,
+ (0x80000001 | ((offset & 0xf00) << 16) |
+ ((bus->number - hose->bus_offset) << 16)
+ | (devfn << 8) | ((offset & 0xfc) )));
+ }
+
+ /*
+ * Note: the caller has already checked that offset is
+ * suitably aligned and that len is 1, 2 or 4.
+ */
+ /* ERRATA PCI-Ex 12 - Configuration Address/Data Alignment */
+ cfg_data = hose->cfg_data;
+ switch (len) {
+ case 1:
+ PEX_FIX;
+ temp = in_le32(cfg_data);
+ temp = (temp & ~(0xff << ((offset & 3) * 8))) |
+ (val << ((offset & 3) * 8));
+ PEX_FIX;
+ out_le32(cfg_data, temp);
+ break;
+ case 2:
+ PEX_FIX;
+ temp = in_le32(cfg_data);
+ temp = (temp & ~(0xffff << ((offset & 3) * 8)));
+ temp |= (val << ((offset & 3) * 8)) ;
+ PEX_FIX;
+ out_le32(cfg_data, temp);
+ break;
+ default:
+ PEX_FIX;
+ out_le32(cfg_data, val);
+ break;
+ }
+ PEX_FIX;
+ return PCIBIOS_SUCCESSFUL;
+}
+
+static struct pci_ops indirect_pex_ops = {
+ indirect_read_config_pex,
+ indirect_write_config_pex
+};
+
+void __init
+setup_indirect_pex_nomap(struct pci_controller* hose, void __iomem * cfg_addr,
+ void __iomem * cfg_data)
+{
+ hose->cfg_addr = cfg_addr;
+ hose->cfg_data = cfg_data;
+ hose->ops = &indirect_pex_ops;
+}
+
+void __init
+setup_indirect_pex(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data)
+{
+ unsigned long base = cfg_addr & PAGE_MASK;
+ void __iomem *mbase, *addr, *data;
+
+ mbase = ioremap(base, PAGE_SIZE);
+ addr = mbase + (cfg_addr & ~PAGE_MASK);
+ if ((cfg_data & PAGE_MASK) != base)
+ mbase = ioremap(cfg_data & PAGE_MASK, PAGE_SIZE);
+ data = mbase + (cfg_data & ~PAGE_MASK);
+ setup_indirect_pex_nomap(hose, addr, data);
+}
^ permalink raw reply related
* [PATCH 2/10] Add the MPC8641 HPCN platform files.
From: Jon Loeliger @ 2006-06-07 22:35 UTC (permalink / raw)
To: linuxppc-dev@ozlabs.org
Signed-off-by: Xianghua Xiao <x.xiao@freescale.com>
Signed-off-by: Wei Zhang <Wei.Zhang@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>
---
arch/powerpc/platforms/86xx/misc.c | 50 ++++
arch/powerpc/platforms/86xx/mpc8641_hpcn.c | 52 +++++
arch/powerpc/platforms/86xx/mpc8641_hpcn.h | 54 +++++
arch/powerpc/platforms/86xx/mpc86xx.h | 31 +++
arch/powerpc/platforms/86xx/mpc86xx_hpcn.c | 313 ++++++++++++++++++++++++++++
5 files changed, 500 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/platforms/86xx/misc.c b/arch/powerpc/platforms/86xx/misc.c
new file mode 100644
index 0000000..82d981c
--- /dev/null
+++ b/arch/powerpc/platforms/86xx/misc.c
@@ -0,0 +1,50 @@
+/*
+ * MPC86XX generic code
+ *
+ * Author: Xianghua Xiao <x.xiao@freescale.com>
+ *
+ * Copyright 2006 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/irq.h>
+#include <linux/module.h>
+#include <asm/irq.h>
+#include <asm/io.h>
+
+
+void
+mpc86xx_restart(char *cmd)
+{
+ void __iomem *rstcr;
+
+ local_irq_disable();
+
+ /* Assert reset request to Reset Control Register */
+ rstcr = ioremap(get_immrbase() + MPC86XX_RSTCR_OFFSET, 0x100);
+ out_be32(rstcr, 0x2);
+
+ /* not reached */
+}
+
+
+long __init
+mpc86xx_time_init(void)
+{
+ unsigned int temp;
+
+ /* Set the time base to zero */
+ mtspr(SPRN_TBWL, 0);
+ mtspr(SPRN_TBWU, 0);
+
+ temp = mfspr(SPRN_HID0);
+ temp |= HID0_TBEN;
+ mtspr(SPRN_HID0, temp);
+ asm volatile("isync");
+
+ return 0;
+}
diff --git a/arch/powerpc/platforms/86xx/mpc8641_hpcn.c b/arch/powerpc/platforms/86xx/mpc8641_hpcn.c
new file mode 100644
index 0000000..655e2b8
--- /dev/null
+++ b/arch/powerpc/platforms/86xx/mpc8641_hpcn.c
@@ -0,0 +1,52 @@
+/*
+ * MPC8641 HPCN board specific routines
+ *
+ * Author: Xianghua Xiao <x.xiao@freescale.com>
+ *
+ * Copyright 2006 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/config.h>
+#include <linux/stddef.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#include <asm/pgtable.h>
+#include <asm/page.h>
+#include <asm/pci-bridge.h>
+#include <asm-powerpc/mpic.h>
+#include <asm/mpc86xx.h>
+
+#include "mpc86xx.h"
+
+
+#ifdef CONFIG_SMP
+static void __init
+smp_8641_kick_cpu(int nr)
+{
+ *(unsigned long *)KERNELBASE = nr;
+ asm volatile("dcbf 0,%0"::"r"(KERNELBASE):"memory");
+ printk("CPU%d released, waiting\n",nr);
+}
+
+static void __init
+smp_8641_setup_cpu(int cpu_nr)
+{
+ mpic_setup_this_cpu();
+}
+
+
+struct smp_ops_t smp_8641_ops = {
+ .message_pass = smp_mpic_message_pass,
+ .probe = smp_mpic_probe,
+ .kick_cpu = smp_8641_kick_cpu,
+ .setup_cpu = smp_8641_setup_cpu,
+ .take_timebase = smp_generic_take_timebase,
+ .give_timebase = smp_generic_give_timebase,
+};
+#endif /* CONFIG_SMP */
diff --git a/arch/powerpc/platforms/86xx/mpc8641_hpcn.h b/arch/powerpc/platforms/86xx/mpc8641_hpcn.h
new file mode 100644
index 0000000..4ba5b4c
--- /dev/null
+++ b/arch/powerpc/platforms/86xx/mpc8641_hpcn.h
@@ -0,0 +1,54 @@
+/*
+ * MPC8641 HPCN board definitions
+ *
+ * Copyright 2006 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * Author: Xianghua Xiao <x.xiao@freescale.com>
+ */
+
+#ifndef __MPC8641_HPCN_H__
+#define __MPC8641_HPCN_H__
+
+#include <linux/config.h>
+#include <linux/init.h>
+
+/* PCI interrupt controller */
+#define PIRQA 3
+#define PIRQB 4
+#define PIRQC 5
+#define PIRQD 6
+#define PIRQ7 7
+#define PIRQE 9
+#define PIRQF 10
+#define PIRQG 11
+#define PIRQH 12
+
+/* PEX memory map */
+#define MPC86XX_PEX_LOWER_IO 0x00000000
+#define MPC86XX_PEX_UPPER_IO 0x00ffffff
+
+#define MPC86XX_PEX_LOWER_MEM 0x80000000
+#define MPC86XX_PEX_UPPER_MEM 0x9fffffff
+
+#define MPC86XX_PEX_IO_BASE 0xe2000000
+#define MPC86XX_PEX_MEM_OFFSET 0x00000000
+
+#define MPC86XX_PEX_IO_SIZE 0x01000000
+
+#define PEX1_CFG_ADDR_OFFSET (0x8000)
+#define PEX1_CFG_DATA_OFFSET (0x8004)
+
+#define PEX2_CFG_ADDR_OFFSET (0x9000)
+#define PEX2_CFG_DATA_OFFSET (0x9004)
+
+#define MPC86xx_PEX_OFFSET PEX1_CFG_ADDR_OFFSET
+#define MPC86xx_PEX_SIZE (0x1000)
+
+#define MPC86XX_RSTCR_OFFSET (0xe00b0) /* Reset Control Register */
+
+#endif /* __MPC8641_HPCN_H__ */
diff --git a/arch/powerpc/platforms/86xx/mpc86xx.h b/arch/powerpc/platforms/86xx/mpc86xx.h
new file mode 100644
index 0000000..7cc45d4
--- /dev/null
+++ b/arch/powerpc/platforms/86xx/mpc86xx.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright 2006 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __MPC86XX_H__
+#define __MPC86XX_H__
+
+/*
+ * Declaration for the various functions exported by the
+ * mpc86xx_* files. Mostly for use by mpc86xx_setup().
+ */
+
+extern void mpc86xx_restart(char *cmd);
+extern long __init mpc86xx_time_init(void);
+
+extern int __init add_bridge(struct device_node *dev);
+
+extern void __init setup_indirect_pex(struct pci_controller* hose,
+ u32 cfg_addr, u32 cfg_data);
+extern void __init setup_indirect_pex_nomap(struct pci_controller* hose,
+ void __iomem * cfg_addr,
+ void __iomem * cfg_data);
+
+extern struct smp_ops_t smp_8641_ops;
+
+#endif /* __MPC86XX_H__ */
diff --git a/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c b/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c
new file mode 100644
index 0000000..1374f27
--- /dev/null
+++ b/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c
@@ -0,0 +1,313 @@
+/*
+ * MPC86xx HPCN board specific routines
+ *
+ * Recode: ZHANG WEI <wei.zhang@freescale.com>
+ * Initial author: Xianghua Xiao <x.xiao@freescale.com>
+ *
+ * Copyright 2006 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/config.h>
+#include <linux/stddef.h>
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/kdev_t.h>
+#include <linux/delay.h>
+#include <linux/seq_file.h>
+#include <linux/root_dev.h>
+
+#include <asm/system.h>
+#include <asm/time.h>
+#include <asm/machdep.h>
+#include <asm/pci-bridge.h>
+#include <asm/mpc86xx.h>
+#include <asm/prom.h>
+#include <mm/mmu_decl.h>
+#include <asm/udbg.h>
+#include <asm/i8259.h>
+
+#include <asm/mpic.h>
+
+#include <sysdev/fsl_soc.h>
+
+#include "mpc86xx.h"
+
+#ifndef CONFIG_PCI
+unsigned long isa_io_base = 0;
+unsigned long isa_mem_base = 0;
+unsigned long pci_dram_offset = 0;
+#endif
+
+
+/*
+ * Internal interrupts are all Level Sensitive, and Positive Polarity
+ */
+
+static u_char mpc86xx_hpcn_openpic_initsenses[] __initdata = {
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 0: Reserved */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 1: MCM */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 2: DDR DRAM */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 3: LBIU */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 4: DMA 0 */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 5: DMA 1 */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 6: DMA 2 */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 7: DMA 3 */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 8: PEX1 */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 9: PEX2 */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 10: Reserved */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 11: Reserved */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 12: DUART2 */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 13: TSEC 1 Transmit */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 14: TSEC 1 Receive */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 15: TSEC 3 transmit */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 16: TSEC 3 receive */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 17: TSEC 3 error */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 18: TSEC 1 Receive/Transmit Error */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 19: TSEC 2 Transmit */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 20: TSEC 2 Receive */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 21: TSEC 4 transmit */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 22: TSEC 4 receive */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 23: TSEC 4 error */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 24: TSEC 2 Receive/Transmit Error */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 25: Unused */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 26: DUART1 */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 27: I2C */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 28: Performance Monitor */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 29: Unused */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 30: Unused */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 31: Unused */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 32: SRIO error/write-port unit */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 33: SRIO outbound doorbell */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 34: SRIO inbound doorbell */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 35: Unused */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 36: Unused */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 37: SRIO outbound message unit 1 */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 38: SRIO inbound message unit 1 */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 39: SRIO outbound message unit 2 */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 40: SRIO inbound message unit 2 */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 41: Unused */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 42: Unused */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 43: Unused */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 44: Unused */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 45: Unused */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 46: Unused */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 47: Unused */
+ 0x0, /* External 0: */
+ 0x0, /* External 1: */
+ 0x0, /* External 2: */
+ 0x0, /* External 3: */
+ 0x0, /* External 4: */
+ 0x0, /* External 5: */
+ 0x0, /* External 6: */
+ 0x0, /* External 7: */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 8: Pixis FPGA */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* External 9: ULI 8259 INTR Cascade */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 10: Quad ETH PHY */
+ 0x0, /* External 11: */
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+};
+
+
+void __init
+mpc86xx_hpcn_init_IRQ(void)
+{
+ struct mpic *mpic1;
+ phys_addr_t OpenPIC_PAddr;
+
+ /* Determine the Physical Address of the OpenPIC regs */
+ OpenPIC_PAddr = get_immrbase() + MPC86xx_OPENPIC_OFFSET;
+
+ /* Alloc mpic structure and per isu has 16 INT entries. */
+ mpic1 = mpic_alloc(OpenPIC_PAddr,
+ MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
+ 16, MPC86xx_OPENPIC_IRQ_OFFSET, 0, 250,
+ mpc86xx_hpcn_openpic_initsenses,
+ sizeof(mpc86xx_hpcn_openpic_initsenses),
+ " MPIC ");
+ BUG_ON(mpic1 == NULL);
+
+ /* 48 Internal Interrupts */
+ mpic_assign_isu(mpic1, 0, OpenPIC_PAddr + 0x10200);
+ mpic_assign_isu(mpic1, 1, OpenPIC_PAddr + 0x10400);
+ mpic_assign_isu(mpic1, 2, OpenPIC_PAddr + 0x10600);
+
+ /* 16 External interrupts */
+ mpic_assign_isu(mpic1, 3, OpenPIC_PAddr + 0x10000);
+
+ mpic_init(mpic1);
+
+#ifdef CONFIG_PEX
+ mpic_setup_cascade(MPC86xx_IRQ_EXT9, i8259_irq_cascade, NULL);
+ i8259_init(0, I8259_OFFSET);
+#endif
+}
+
+
+
+#ifdef CONFIG_PCI
+/*
+ * interrupt routing
+ */
+
+int
+mpc86xx_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
+{
+ static char pci_irq_table[][4] = {
+ /*
+ * PCI IDSEL/INTPIN->INTLINE
+ * A B C D
+ */
+ {PIRQA, PIRQB, PIRQC, PIRQD}, /* IDSEL 17 -- PCI Slot 1 */
+ {PIRQB, PIRQC, PIRQD, PIRQA}, /* IDSEL 18 -- PCI Slot 2 */
+ {0, 0, 0, 0}, /* IDSEL 19 */
+ {0, 0, 0, 0}, /* IDSEL 20 */
+ {0, 0, 0, 0}, /* IDSEL 21 */
+ {0, 0, 0, 0}, /* IDSEL 22 */
+ {0, 0, 0, 0}, /* IDSEL 23 */
+ {0, 0, 0, 0}, /* IDSEL 24 */
+ {0, 0, 0, 0}, /* IDSEL 25 */
+ {0, 0, 0, 0}, /* IDSEL 26 */
+ {PIRQC, 0, 0, 0}, /* IDSEL 27 -- LAN */
+ {PIRQE, PIRQF, PIRQH, PIRQ7}, /* IDSEL 28 -- USB 1.1 */
+ {PIRQE, PIRQF, PIRQG, 0}, /* IDSEL 29 -- Audio & Modem */
+ {PIRQH, 0, 0, 0}, /* IDSEL 30 -- LPC & PMU*/
+ {PIRQD, 0, 0, 0}, /* IDSEL 31 -- ATA */
+ };
+
+ const long min_idsel = 17, max_idsel = 31, irqs_per_slot = 4;
+ return PCI_IRQ_TABLE_LOOKUP + I8259_OFFSET;
+}
+
+
+int
+mpc86xx_exclude_device(u_char bus, u_char devfn)
+{
+#if !defined(CONFIG_PEX)
+ if (bus == 0 && PCI_SLOT(devfn) == 0)
+ return PCIBIOS_DEVICE_NOT_FOUND;
+#endif
+
+ return PCIBIOS_SUCCESSFUL;
+}
+#endif /* CONFIG_PCI */
+
+
+static void __init
+mpc86xx_hpcn_setup_arch(void)
+{
+ struct device_node *np;
+
+#ifdef CONFIG_SMP
+ phys_addr_t mcm_paddr;
+ void *mcm_vaddr = NULL;
+ unsigned long vaddr;
+#endif
+
+ if (ppc_md.progress)
+ ppc_md.progress("mpc86xx_hpcn_setup_arch()", 0);
+
+ np = of_find_node_by_type(NULL, "cpu");
+ if (np != 0) {
+ unsigned int *fp;
+
+ fp = (int *)get_property(np, "clock-frequency", NULL);
+ if (fp != 0)
+ loops_per_jiffy = *fp / HZ;
+ else
+ loops_per_jiffy = 50000000 / HZ;
+ of_node_put(np);
+ }
+
+#ifdef CONFIG_PEX
+ for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;)
+ add_bridge(np);
+
+ ppc_md.pci_swizzle = common_swizzle;
+ ppc_md.pci_map_irq = mpc86xx_map_irq;
+ ppc_md.pci_exclude_device = mpc86xx_exclude_device;
+#endif
+
+ printk("HPCN board with 86xx from Freescale Semiconductor\n");
+
+#ifdef CONFIG_ROOT_NFS
+ ROOT_DEV = Root_NFS;
+#else
+ ROOT_DEV = Root_HDA1;
+#endif
+
+#ifdef CONFIG_SMP
+ /* Release Core 1 in boot holdoff */
+ mcm_paddr = get_immrbase() + MPC86xx_MCM_OFFSET;
+ mcm_vaddr = ioremap(mcm_paddr, MPC86xx_MCM_SIZE);
+
+ vaddr = (unsigned long)mcm_vaddr + MCM_PORT_CONFIG_OFFSET;
+ out_be32((volatile unsigned *)vaddr, CPU_ALL_RELEASED);
+ smp_ops = &smp_8641_ops;
+#endif
+}
+
+
+void
+mpc86xx_hpcn_show_cpuinfo(struct seq_file *m)
+{
+ uint pvid, svid, phid1;
+ uint memsize = total_memory;
+
+ pvid = mfspr(SPRN_PVR);
+ svid = mfspr(SPRN_SVR);
+
+ seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n");
+
+ switch (pvid & 0xffff0000) {
+ case PVR_8641:
+ seq_printf(m, "Machine\t\t: HPCN 8641 Board\n");
+ break;
+ default:
+ seq_printf(m, "Machine\t\t: unknown\n");
+ break;
+ }
+ seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
+ seq_printf(m, "SVR\t\t: 0x%x\n", svid);
+
+ /* Display cpu Pll setting */
+ phid1 = mfspr(SPRN_HID1);
+ seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
+
+ /* Display the amount of memory */
+ seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
+}
+
+/*
+ * Called very early, device-tree isn't unflattened
+ */
+static int __init mpc86xx_hpcn_probe(void)
+{
+ unsigned long root = of_get_flat_dt_root();
+
+ if (of_flat_dt_is_compatible(root, "mpc86xx"))
+ return 1; /* Looks good */
+
+ return 0;
+}
+
+define_machine(mpc86xx_hpcn) {
+ .name = "MPC86xx HPCN",
+ .probe = mpc86xx_hpcn_probe,
+ .setup_arch = mpc86xx_hpcn_setup_arch,
+ .init_IRQ = mpc86xx_hpcn_init_IRQ,
+ .show_cpuinfo = mpc86xx_hpcn_show_cpuinfo,
+ .get_irq = mpic_get_irq,
+ .restart = mpc86xx_restart,
+ .time_init = mpc86xx_time_init,
+ .calibrate_decr = generic_calibrate_decr,
+ .progress = udbg_progress,
+};
+
^ permalink raw reply related
* [PATCH 1/10] Add the mpc8641 hpcn Kconfig and Makefiles.
From: Jon Loeliger @ 2006-06-07 22:34 UTC (permalink / raw)
To: linuxppc-dev@ozlabs.org
Signed-off-by: Xianghua Xiao <x.xiao@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>
---
arch/powerpc/Kconfig | 15 ++++++++++-
arch/powerpc/platforms/Makefile | 1 +
arch/powerpc/platforms/86xx/Makefile | 7 +++++
arch/powerpc/platforms/86xx/Kconfig | 46 ++++++++++++++++++++++++++++++++++
drivers/i2c/busses/Kconfig | 4 +--
5 files changed, 69 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 75ba0ec..e708401 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -141,6 +141,15 @@ config PPC_85xx
select FSL_SOC
select 85xx
+config PPC_86xx
+ bool "Freescale 86xx"
+ select 6xx
+ select FSL_SOC
+ select PPC_FPU
+ select ALTIVEC
+ help
+ The Freescale E600 SoCs have 74xx cores.
+
config 40x
bool "AMCC 40x"
@@ -549,6 +558,7 @@ source arch/powerpc/platforms/embedded6x
source arch/powerpc/platforms/4xx/Kconfig
source arch/powerpc/platforms/83xx/Kconfig
source arch/powerpc/platforms/85xx/Kconfig
+source arch/powerpc/platforms/86xx/Kconfig
source arch/powerpc/platforms/8xx/Kconfig
source arch/powerpc/platforms/cell/Kconfig
@@ -780,6 +790,7 @@ config GENERIC_ISA_DMA
config PPC_I8259
bool
+ default y if PPC_86xx
default n
config PPC_INDIRECT_PCI
@@ -802,8 +813,8 @@ config MCA
bool
config PCI
- bool "PCI support" if 40x || CPM2 || PPC_83xx || PPC_85xx || PPC_MPC52xx || (EMBEDDED && PPC_ISERIES)
- default y if !40x && !CPM2 && !8xx && !APUS && !PPC_83xx && !PPC_85xx
+ bool "PCI support" if 40x || CPM2 || PPC_83xx || PPC_85xx || PPC_86xx || PPC_MPC52xx || (EMBEDDED && PPC_ISERIES)
+ default y if !40x && !CPM2 && !8xx && !APUS && !PPC_83xx && !PPC_85xx && !PPC_86xx
default PCI_PERMEDIA if !4xx && !CPM2 && !8xx && APUS
default PCI_QSPAN if !4xx && !CPM2 && 8xx
help
diff --git a/arch/powerpc/platforms/Makefile b/arch/powerpc/platforms/Makefile
index c4f6b0d..2928636 100644
--- a/arch/powerpc/platforms/Makefile
+++ b/arch/powerpc/platforms/Makefile
@@ -9,6 +9,7 @@ obj-$(CONFIG_PPC_CHRP) += chrp/
obj-$(CONFIG_4xx) += 4xx/
obj-$(CONFIG_PPC_83xx) += 83xx/
obj-$(CONFIG_PPC_85xx) += 85xx/
+obj-$(CONFIG_PPC_86xx) += 86xx/
obj-$(CONFIG_PPC_PSERIES) += pseries/
obj-$(CONFIG_PPC_ISERIES) += iseries/
obj-$(CONFIG_PPC_MAPLE) += maple/
diff --git a/arch/powerpc/platforms/86xx/Makefile b/arch/powerpc/platforms/86xx/Makefile
new file mode 100644
index 0000000..8a237a1
--- /dev/null
+++ b/arch/powerpc/platforms/86xx/Makefile
@@ -0,0 +1,7 @@
+#
+# Makefile for the PowerPC 86xx linux kernel.
+#
+
+obj-$(CONFIG_PPC_86xx) += mpc86xx_hpcn.o misc.o
+obj-$(CONFIG_MPC8641_HPCN) += mpc8641_hpcn.o
+obj-$(CONFIG_PCI) += pci.o pex.o
diff --git a/arch/powerpc/platforms/86xx/Kconfig b/arch/powerpc/platforms/86xx/Kconfig
new file mode 100644
index 0000000..b8924e7
--- /dev/null
+++ b/arch/powerpc/platforms/86xx/Kconfig
@@ -0,0 +1,46 @@
+menu "Platform Support"
+ depends on PPC_86xx
+
+choice
+ prompt "Machine Type"
+ default MPC8641_HPCN
+
+config MPC8641_HPCN
+ bool "Freescale MPC8641 HPCN"
+ help
+ This option enables support for the MPC8641 HPCN board.
+
+endchoice
+
+
+config MPC8641
+ bool
+ select PPC_INDIRECT_PCI
+ select PPC_UDBG_16550
+ default y if MPC8641_HPCN
+
+config MPIC
+ bool
+ default y
+
+config PPC_INDIRECT_PCI_BE
+ bool
+ depends on PPC_86xx
+ default y
+
+config PEX
+ bool "PCI Express support"
+ depends on PCI && PPC_86xx
+ default y
+
+config I8259_LEVEL_TRIGGER
+ bool
+ depends on MPC8641
+ default y
+
+config PPC_STD_MMU
+ bool
+ depends on PPC_86xx
+ default y
+
+endmenu
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index d6d4494..fbeae82 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -252,12 +252,12 @@ config I2C_POWERMAC
will be called i2c-powermac.
config I2C_MPC
- tristate "MPC107/824x/85xx/52xx"
+ tristate "MPC107/824x/85xx/52xx/86xx"
depends on I2C && PPC32
help
If you say yes to this option, support will be included for the
built-in I2C interface on the MPC107/Tsi107/MPC8240/MPC8245 and
- MPC85xx family processors. The driver may also work on 52xx
+ MPC85xx/MPC8641 family processors. The driver may also work on 52xx
family processors, though interrupts are known not to work.
This driver can also be built as a module. If so, the module
^ permalink raw reply related
* [PATCH 0/10] Add MPC8641 HPCN Platform
From: Jon Loeliger @ 2006-06-07 22:32 UTC (permalink / raw)
To: linuxppc-dev@ozlabs.org
This series of patches introduces the MPC8641 HPCN platform.
Please consider this for addition into the 2.6.18 queue.
Signed-off-by: Jon Loeliger <jdl@freescale.com>
Signed-off-by: Xianghua Xiao <x.xiao@freescale.com>
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Wei Zhang <Wei.Zhang@freescale.com>
Signed-off-by: Jeff Brown <Jeff.Brown@freescale.com>
Signed-off-by: Kriston Carson <KristonCarson@freescale.com>
arch/powerpc/Kconfig | 15
arch/powerpc/platforms/Makefile | 1
arch/powerpc/platforms/86xx/Makefile | 7
arch/powerpc/platforms/86xx/Kconfig | 46 +
drivers/i2c/busses/Kconfig | 4
arch/powerpc/platforms/86xx/misc.c | 50 +
arch/powerpc/platforms/86xx/mpc8641_hpcn.c | 52 ++
arch/powerpc/platforms/86xx/mpc8641_hpcn.h | 54 ++
arch/powerpc/platforms/86xx/mpc86xx.h | 31 +
arch/powerpc/platforms/86xx/mpc86xx_hpcn.c | 313 +++++++++
arch/powerpc/platforms/86xx/pci.c | 213 ++++++
arch/powerpc/platforms/86xx/pex.c | 173 +++++
arch/powerpc/kernel/cpu_setup_6xx.S | 2
arch/powerpc/kernel/cputable.c | 12
arch/powerpc/kernel/head_32.S | 15
arch/powerpc/sysdev/i8259.c | 5
include/asm-powerpc/immap_86xx.h | 199 ++++++
include/asm-powerpc/irq.h | 88 +++
include/asm-powerpc/mpc86xx.h | 95 +++
include/asm-powerpc/reg.h | 1
include/asm-ppc/io.h | 2
include/asm-ppc/ppc_sys.h | 2
include/asm-ppc/serial.h | 2
arch/powerpc/configs/mpc8641_hpcn_defconfig | 923 +++++++++++++++++++++++++++
drivers/net/Kconfig | 6
drivers/net/phy/Kconfig | 5
drivers/net/phy/Makefile | 1
drivers/net/phy/vitesse.c | 136 ++++
arch/powerpc/kernel/prom.c | 13
29 files changed, 2457 insertions(+), 9 deletions(-)
^ permalink raw reply
* MPC5200B SPI PSC3 Problem
From: Trueskew @ 2006-06-07 22:21 UTC (permalink / raw)
To: linuxppc-embedded
[-- Attachment #1: Type: text/plain, Size: 10899 bytes --]
We have an AIC26 codec connected to our Lite5200B platform via J21. I've
used MPC5200BUG to configure PSC3 as an SPI master, along with some samples
I've found online (including here) and some I received from Freescale.
Although the transfers seem to be working as expected (please see the output
file at the end of this message), I get only 0xffff back. This occurs
whether or not the device is attached to J21. A scope shows that PSC3_8
(SPI_SS) and PSC3_9 (SPI_CLK) are low at all times, and I'm concerned I'm
still doing something wrong with respect to enabling SPI over PSC3.
I'm including my driver initialization code, my write code, and output
showing the write behavior. If someone could comment on it, I would greatly
appreciate it... or if someone flat out has code to do this, I'd be happy to
take it from you. I've seen a few variations, but whether I use them
directly or modify them as I need to, I can't seem to get past this. Of
course, any other suggestions are welcome.
Thanks.
Sal
---------------------------------------------------------------------------
Initialization Code
---------------------------------------------------------------------------
#define GPIO_PSC3_PORT_CONFIG_MASK 0x00000f00
#ifdef SPI_USE_MCLK
#define GPIO_PSC3_PORT_CONFIG 0x00000700 /* PSC3 mode with mclk */
#else /* SPI_USE_MCLK */
#define GPIO_PSC3_PORT_CONFIG 0x00000600 /* PSC3 mode */
#endif /* SPI_USE_MCLK */
#define CDM_PSC3_MCLK_ENABLE 0x00000080
#define CDM_PSC3_MCLK_CONFIG 0x8020 /* Divide Fvco ftom 528 to
16Mhz */
#define PSC3_SICR_REG_VALUE 0x0280f000 /* 16-bit select Codec SPI
master mode, msb first,
UseEOF=1. GenClk=1, SIM,
CPOL and CPHA are
function input */
...
/* Select the Pin-Muxing for PSC3 Codec mode */
gpio = (struct mpc52xx_gpio *) ioremap(MPC52xx_GPIO,
sizeof(struct mpc52xx_gpio));
if(gpio)
{
port_config = gpio->port_config;
port_config &= ~GPIO_PSC3_PORT_CONFIG_MASK;
port_config |= GPIO_PSC3_PORT_CONFIG;
gpio->port_config = port_config;
iounmap(gpio);
}
else
{
return(-1);
}
#ifdef SPI_USE_MCLK
/* PSC clock enable */
g_pCDM->clk_enables |= CDM_PSC3_MCLK_ENABLE;
g_pCDM->mclken_div_psc3 = CDM_PSC3_MCLK_CONFIG;
#endif /* SPI_USE_MCLK */
/* Disable rx and tx */
g_pPSC->command = MPC52xx_PSC_RST_RX;
g_pPSC->command = MPC52xx_PSC_RST_TX;
g_pPSC->command = MPC52xx_PSC_SEL_MODE_REG_1;
g_pPSC->command = MPC52xx_PSC_RST_ERR_STAT;
g_pPSC->command = MPC52xx_PSC_RX_DISABLE | MPC52xx_PSC_TX_DISABLE;
g_pPSC->mode = 0;
g_pPSC->sicr = PSC3_SICR_REG_VALUE;
#ifdef SPI_USE_MCLK
g_pPSC->ccr=0x0703; /* set SCK and DSCKL delay */
#else /* SPI_USE_MCLK */
g_pPSC->ccr=0x0003; /* set SCK and DSCKL delay must be > 2 */
#endif /* SPI_USE_MCLK */
g_pPSC->ctur=0x00; /* Set DTL delay 2us */
g_pPSC->ctlr=0x84;
g_pPSC->rfalarm=100; /* Alarm values taken from SPI example sample
*/
g_pPSC->tfalarm=1;
g_pPSC->rfcntl &= 0xf8; /* 0 byte granularity */
g_pPSC->tfcntl = 1;
/* Enable rx & tx */
g_pPSC->command = MPC52xx_PSC_RST_RX;
g_pPSC->command = MPC52xx_PSC_RST_TX;
g_pPSC->command = MPC52xx_PSC_SEL_MODE_REG_1;
g_pPSC->command = MPC52xx_PSC_RST_ERR_STAT;
g_pPSC->command = MPC52xx_PSC_RX_ENABLE | MPC52xx_PSC_TX_ENABLE;
---------------------------------------------------------------------------
Write code
---------------------------------------------------------------------------
static int mpc52xx_spi_transfer(u16 *p_usBuffer, u16 p_usCount)
{
u16 usIndex, usTemp;
printk("------------------------------------------------------\n");
printk("Entry: psc=%x status=%04x tfstat=%04x rfstat=%04x
mode=%02x\n tfnum %3d rfnum %3d\n",
(int)g_pPSC,g_pPSC->mpc52xx_psc_status,g_pPSC->tfstat,g_pPSC->tfstat,g_pPSC-
>mode,
g_pPSC->tfnum, g_pPSC->rfnum);
g_pPSC->command = MPC52xx_PSC_RST_RX;
g_pPSC->command = MPC52xx_PSC_RST_TX;
g_pPSC->command = MPC52xx_PSC_SEL_MODE_REG_1;
g_pPSC->command = MPC52xx_PSC_RST_ERR_STAT;
g_pPSC->command = MPC52xx_PSC_RX_ENABLE | MPC52xx_PSC_TX_ENABLE;
printk("TX-RX Enable: psc=%x status=%04x tfstat=%04x rfstat=%04x
mode=%02x\n tfnum %3d rfnum %3d\n",
(int)g_pPSC,g_pPSC->mpc52xx_psc_status,g_pPSC->tfstat,g_pPSC->tfstat,g_pPSC-
>mode,
g_pPSC->tfnum, g_pPSC->rfnum);
/* Clean out the read FIFO */
usIndex = 0;
while(g_pPSC->mpc52xx_psc_status & MPC52xx_PSC_SR_RXRDY)
{
usTemp = g_pPSC->mpc52xx_psc_buffer_16;
printk("Flushing Rx FIFO: psc=%x status=%04x tfstat=%04x rfstat=%04x
mode=%02x\n tfnum %3d rfnum %3d\n",
(int)g_pPSC,g_pPSC->mpc52xx_psc_status,g_pPSC->tfstat,g_pPSC->tfstat,g_pPSC-
>mode,
g_pPSC->tfnum, g_pPSC->rfnum);
udelay(100000);
udelay(100000);
udelay(100000);
udelay(100000);
udelay(100000);
usIndex++;
if(usIndex == 10) return(-1);
}
/* Send out the buffer */
g_pPSC->command = MPC52xx_PSC_RX_ENABLE | MPC52xx_PSC_TX_DISABLE;
for(usIndex=0; usIndex<p_usCount; usIndex++)
{
printk("Sending %04x: psc=%x status=%04x tfstat=%04x rfstat=%04x
mode=%02x\n tfnum %3d rfnum %3d\n",
p_usBuffer[usIndex],
(int)g_pPSC,g_pPSC->mpc52xx_psc_status,g_pPSC->tfstat,g_pPSC->tfstat,g_pPSC-
>mode,
g_pPSC->tfnum, g_pPSC->rfnum);
g_pPSC->mpc52xx_psc_buffer_16 = p_usBuffer[usIndex];
printk("Sent: psc=%x status=%04x tfstat=%04x rfstat=%04x
mode=%02x\n tfnum %3d rfnum %3d\n",
(int)g_pPSC,g_pPSC->mpc52xx_psc_status,g_pPSC->tfstat,g_pPSC->tfstat,g_pPSC-
>mode,
g_pPSC->tfnum, g_pPSC->rfnum);
}
g_pPSC->command = MPC52xx_PSC_RX_ENABLE | MPC52xx_PSC_TX_ENABLE;
usTemp = 0;
while(g_pPSC->tfnum)
{
printk("TFNUM Wait: psc=%x status=%04x tfstat=%04x rfstat=%04x
mode=%02x\n tfnum %3d rfnum %3d\n",
(int)g_pPSC,g_pPSC->mpc52xx_psc_status,g_pPSC->tfstat,g_pPSC->tfstat,g_pPSC-
>mode,
g_pPSC->tfnum, g_pPSC->rfnum);
udelay(100000);
udelay(100000);
udelay(100000);
udelay(100000);
udelay(100000);
usTemp++;
if(usTemp == 10) return(-1);
};
printk("TxRDY: psc=%x status=%04x tfstat=%04x rfstat=%04x
mode=%02x\n tfnum %3d rfnum %3d\n",
(int)g_pPSC,g_pPSC->mpc52xx_psc_status,g_pPSC->tfstat,g_pPSC->tfstat,g_pPSC-
>mode,
g_pPSC->tfnum, g_pPSC->rfnum);
for(usIndex=0; usIndex<p_usCount; usIndex++)
{
usTemp = 0;
while(!(g_pPSC->mpc52xx_psc_status & MPC52xx_PSC_SR_RXRDY))
{
printk("RxRDY Wait: psc=%x status=%04x tfstat=%04x rfstat=%04x
mode=%02x\n tfnum %3d rfnum %3d\n",
(int)g_pPSC,g_pPSC->mpc52xx_psc_status,g_pPSC->tfstat,g_pPSC->tfstat,g_pPSC-
>mode,
g_pPSC->tfnum, g_pPSC->rfnum);
udelay(100000);
udelay(100000);
udelay(100000);
udelay(100000);
udelay(100000);
usTemp++;
if(usTemp == 10) return(-1);
};
printk("RxRDY: psc=%x status=%04x tfstat=%04x rfstat=%04x
mode=%02x\n tfnum %3d rfnum %3d\n",
(int)g_pPSC,g_pPSC->mpc52xx_psc_status,g_pPSC->tfstat,g_pPSC->tfstat,g_pPSC-
>mode,
g_pPSC->tfnum, g_pPSC->rfnum);
p_usBuffer[usIndex] = g_pPSC->mpc52xx_psc_buffer_16;
printk(" Received %04x\n", p_usBuffer[usIndex]);
}
printk("EXIT: psc=%x status=%04x tfstat=%04x rfstat=%04x
mode=%02x\n tfnum %3d rfnum %3d\n",
(int)g_pPSC,g_pPSC->mpc52xx_psc_status,g_pPSC->tfstat,g_pPSC->tfstat,g_pPSC-
>mode,
g_pPSC->tfnum, g_pPSC->rfnum);
return(usIndex);
}
---------------------------------------------------------------------------
Output
---------------------------------------------------------------------------
The lines below are a capture of register settings from my driver,
along with output lines when trying to write 16 bit words to our
device. This output is consistent whether the device is connected
or not (via J21). Basic operation, delimited by "------...---":
- Disable TX, Enable RX (despite the "TX-RX Enable" heading)
- Send word 1
- Send word 2
- Enable TX, Enable RX
- Wait for tfnum == 0
- Receive data
port_config=91051624 sicr=0280f000 clk_enables=00ffffff div_psc3=800f
------------------------------------------------------
Entry: psc=f0002400 status=0400 tfstat=0003 rfstat=0003 mode=33
tfnum 0 rfnum 0
TX-RX Enable: psc=f0002400 status=0400 tfstat=0003 rfstat=0003 mode=33
tfnum 0 rfnum 0
Sending 0880: psc=f0002400 status=0400 tfstat=0003 rfstat=0003 mode=07
tfnum 0 rfnum 0
Sent: psc=f0002400 status=0000 tfstat=0002 rfstat=0002 mode=07
tfnum 2 rfnum 0
Sending bb00: psc=f0002400 status=0000 tfstat=0002 rfstat=0002 mode=07
tfnum 2 rfnum 0
Sent: psc=f0002400 status=0000 tfstat=0002 rfstat=0002 mode=07
tfnum 4 rfnum 0
TFNUM Wait: psc=f0002400 status=0000 tfstat=0002 rfstat=0002 mode=07
tfnum 2 rfnum 0
TxRDY: psc=f0002400 status=0500 tfstat=0003 rfstat=0003 mode=07
tfnum 0 rfnum 4
RxRDY: psc=f0002400 status=0500 tfstat=0003 rfstat=0003 mode=07
tfnum 0 rfnum 4
Received ffff
RxRDY: psc=f0002400 status=0500 tfstat=0003 rfstat=0003 mode=07
tfnum 0 rfnum 2
Received ffff
EXIT: psc=f0002400 status=0400 tfstat=0003 rfstat=0003 mode=07
tfnum 0 rfnum 0
------------------------------------------------------
Entry: psc=f0002400 status=0400 tfstat=0003 rfstat=0003 mode=07
tfnum 0 rfnum 0
TX-RX Enable: psc=f0002400 status=0400 tfstat=0003 rfstat=0003 mode=33
tfnum 0 rfnum 0
Sending 8820: psc=f0002400 status=0400 tfstat=0003 rfstat=0003 mode=07
tfnum 0 rfnum 0
Sent: psc=f0002400 status=0000 tfstat=0002 rfstat=0002 mode=07
tfnum 2 rfnum 0
Sending 0000: psc=f0002400 status=0000 tfstat=0002 rfstat=0002 mode=07
tfnum 2 rfnum 0
Sent: psc=f0002400 status=0000 tfstat=0002 rfstat=0002 mode=07
tfnum 4 rfnum 0
TFNUM Wait: psc=f0002400 status=0000 tfstat=0002 rfstat=0002 mode=07
tfnum 2 rfnum 0
TxRDY: psc=f0002400 status=0500 tfstat=0003 rfstat=0003 mode=07
tfnum 0 rfnum 4
RxRDY: psc=f0002400 status=0500 tfstat=0003 rfstat=0003 mode=07
tfnum 0 rfnum 4
Received ffff
RxRDY: psc=f0002400 status=0500 tfstat=0003 rfstat=0003 mode=07
tfnum 0 rfnum 2
Received ffff
EXIT: psc=f0002400 status=0400 tfstat=0003 rfstat=0003 mode=07
tfnum 0 rfnum 0
[-- Attachment #2: Type: text/html, Size: 20391 bytes --]
^ permalink raw reply
* Re: [PATCH 2/3] powerpc: Implement support for setting little-endian mode via prctl
From: Paul Mackerras @ 2006-06-07 21:41 UTC (permalink / raw)
To: Olof Johansson; +Cc: akpm, linuxppc-dev
In-Reply-To: <20060607173320.GB5661@pb15.lixom.net>
Olof Johansson writes:
> > #define CPU_FTR_LOCKLESS_TLBIE ASM_CONST(0x0)
> > #define CPU_FTR_MMCRA_SIHV ASM_CONST(0x0)
> > #define CPU_FTR_CI_LARGE_PAGE ASM_CONST(0x0)
> > +#define CPU_FTR_PAUSE_ZERO ASM_CONST(0x0)
> > #define CPU_FTR_PURR ASM_CONST(0x0)
> > #endif
>
> This seems to have snuck in from something else. It's not used anywhere.
Yes, early on I noticed that this one was missing from the dummy
definitions for 32-bit and cleaned it up as I went past. I'll remove
that hunk.
Paul.
^ permalink raw reply
* [PATCH 3/3] RTAS MSI
From: Jake Moilanen @ 2006-06-07 21:25 UTC (permalink / raw)
To: linuxppc-dev; +Cc: paulus
In-Reply-To: <20060607160212.1203d9ea.moilanen@austin.ibm.com>
This provides support for the pSeries RTAS interfaces for MSI.
It follows the altix conventions, and is based on top of the altix patch.
Signed-off-by: Jake Moilanen <moilanen@austin.ibm.com>
Index: 2.6/drivers/pci/Makefile
===================================================================
--- 2.6.orig/drivers/pci/Makefile 2006-06-07 15:29:55.000000000 -0500
+++ 2.6/drivers/pci/Makefile 2006-06-07 15:59:28.000000000 -0500
@@ -26,7 +26,14 @@
obj-$(CONFIG_PPC64) += setup-bus.o
obj-$(CONFIG_MIPS) += setup-bus.o setup-irq.o
obj-$(CONFIG_X86_VISWS) += setup-irq.o
-obj-$(CONFIG_PCI_MSI) += msi.o
+
+msiobj-$(CONFIG_X86) += msi.o msi-apic.o msi-intel.o
+msiobj-$(CONFIG_IA64) += msi.o msi-apic.o msi-intel.o
+msiobj-$(CONFIG_IA64_GENERIC) += msi.o msi-altix.o
+msiobj-$(CONFIG_IA64_SGI_SN2) += msi.o msi-altix.o
+msiobj-$(CONFIG_PPC_PSERIES) += msi-rtas.o
+
+obj-$(CONFIG_PCI_MSI) += $(msiobj-y)
#
# ACPI Related PCI FW Functions
Index: 2.6/drivers/pci/msi-rtas.c
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ 2.6/drivers/pci/msi-rtas.c 2006-06-07 15:59:59.000000000 -0500
@@ -0,0 +1,162 @@
+/*
+ * Jake Moilanen <moilanen@austin.ibm.com>
+ * Copyright (C) 2006 IBM
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; version 2 of the
+ * License.
+ *
+ */
+
+#include <linux/pci.h>
+#include <linux/irq.h>
+#include <asm/rtas.h>
+#include <asm/hw_irq.h>
+
+int rtas_enable_msi(struct pci_dev* pdev)
+{
+ static int seq_num = 1;
+ int i;
+ int rc;
+ int query_token = rtas_token("ibm,query-interrupt-source-number");
+ int devfn;
+ int busno;
+ u32 *reg;
+ int reglen;
+ int ret[3];
+ int dummy;
+ unsigned int virq;
+ unsigned int addr;
+ unsigned long buid = -1;
+ unsigned long wait_time;
+ struct device_node * dn;
+
+ BUG_ON(!pdev);
+
+ dn = pci_device_to_OF_node(pdev);
+
+ if (!of_find_property(dn, "ibm,req#msi", &dummy))
+ return -ENOENT;
+
+ reg = (u32 *) get_property(dn, "reg", ®len);
+ if (reg == NULL || reglen < 20)
+ return -ENXIO;
+
+ devfn = (reg[0] >> 8) & 0xff;
+ busno = (reg[0] >> 16) & 0xff;
+
+ buid = get_phb_buid(dn->parent);
+ addr = (busno << 16) | (devfn << 8);
+
+ while (1) {
+ rc = rtas_call(rtas_token("ibm,change-msi"), 6, 3, ret, addr,
+ buid >> 32, buid & 0xffffffff,
+ 0, 0, seq_num);
+
+ if (!rc)
+ break;
+ else if (rc == RTAS_BUSY)
+ udelay(1);
+ else if (rtas_is_extended_busy(rc)) {
+ wait_time = rtas_extended_busy_delay_time(rc);
+ udelay(wait_time * 1000);
+ } else {
+ printk(KERN_WARNING "error[%d]: getting the number of "
+ "MSI interrupts for %s\n", rc, dn->name);
+ return -EIO;
+ }
+
+ seq_num = ret[1];
+ }
+
+ /* Return if there's no MSI interrupts */
+ if (!ret[0])
+ return -ENOENT;
+
+ dn->n_intrs = ret[0];
+
+ dn->intrs = kmalloc(dn->n_intrs * sizeof(*(dn->intrs)), GFP_KERNEL);
+ if (!dn->intrs) {
+ printk(KERN_WARNING "rtas_enable_msi: can't allocate space\n");
+ return -ENOMEM;
+ }
+
+ for (i = 0; i < dn->n_intrs; i++) {
+ rc = rtas_call(query_token, 4, 3, ret, addr,
+ buid >> 32, buid & 0xffffffff, i);
+
+ if (!rc) {
+ virq = virt_irq_create_mapping(ret[0]);
+
+ dn->intrs[i].line = irq_offset_up(virq);
+ dn->intrs[i].sense = ret[1];
+ } else {
+ printk(KERN_WARNING "error[%d]: query-interrupt-source-number for %s\n",
+ rc, dn->name);
+ }
+ }
+
+ /* Just give the first vector out for now */
+ pdev->irq = dn->intrs[0].line;
+
+ return 0;
+}
+
+void rtas_disable_msi(struct pci_dev* pdev)
+{
+ static int seq_num = 1;
+ struct device_node * dn;
+ int rc;
+ int devfn;
+ int busno;
+ u32 *reg;
+ int reglen;
+ int ret[3];
+ int dummy;
+ unsigned int addr;
+ unsigned long buid = -1;
+ unsigned long wait_time;
+
+ BUG_ON(!pdev);
+
+ dn = pci_device_to_OF_node(pdev);
+
+ if (!of_find_property(dn, "ibm,req#msi", &dummy))
+ return;
+
+ reg = (u32 *) get_property(dn, "reg", ®len);
+ if (reg == NULL || reglen < 20)
+ return;
+
+ devfn = (reg[0] >> 8) & 0xff;
+ busno = (reg[0] >> 16) & 0xff;
+
+ buid = get_phb_buid(dn->parent);
+ addr = (busno << 16) | (devfn << 8);
+
+ while (1) {
+ rc = rtas_call(rtas_token("ibm,change-msi"), 6, 3, ret, addr,
+ buid >> 32, buid & 0xffffffff,
+ 2, 0, seq_num);
+
+ if (!rc)
+ break;
+ else if (rc == RTAS_BUSY)
+ udelay(1);
+ else if (rtas_is_extended_busy(rc)) {
+ wait_time = rtas_extended_busy_delay_time(rc);
+ udelay(wait_time * 1000);
+ } else {
+ printk(KERN_WARNING "error[%d]: setting the number of "
+ "MSI interrupts for %s\n", rc, dn->name);
+ return;
+ }
+
+ seq_num = ret[1];
+ }
+
+ dn->n_intrs = 0;
+
+ kfree(dn->intrs);
+}
Index: 2.6/drivers/pci/Kconfig
===================================================================
--- 2.6.orig/drivers/pci/Kconfig 2006-06-07 15:29:55.000000000 -0500
+++ 2.6/drivers/pci/Kconfig 2006-06-07 15:59:28.000000000 -0500
@@ -4,7 +4,7 @@
config PCI_MSI
bool "Message Signaled Interrupts (MSI and MSI-X)"
depends on PCI
- depends on (X86_LOCAL_APIC && X86_IO_APIC) || IA64
+ depends on (X86_LOCAL_APIC && X86_IO_APIC) || IA64 || PPC_PSERIES
help
This allows device drivers to enable MSI (Message Signaled
Interrupts). Message Signaled Interrupts enable a device to
Index: 2.6/arch/powerpc/platforms/pseries/setup.c
===================================================================
--- 2.6.orig/arch/powerpc/platforms/pseries/setup.c 2006-06-07 15:29:55.000000000 -0500
+++ 2.6/arch/powerpc/platforms/pseries/setup.c 2006-06-07 15:59:28.000000000 -0500
@@ -78,6 +78,8 @@
#endif
extern void find_udbg_vterm(void);
+extern int rtas_enable_msi(struct pci_dev* pdev);
+extern void rtas_disable_msi(struct pci_dev * pdev);
int fwnmi_active; /* TRUE if an FWNMI handler is present */
@@ -205,6 +207,10 @@
} else {
ppc_md.init_IRQ = xics_init_IRQ;
ppc_md.get_irq = xics_get_irq;
+#ifdef CONFIG_PCI_MSI
+ ppc_md.enable_msi = rtas_enable_msi;
+ ppc_md.disable_msi = rtas_disable_msi;
+#endif
}
#ifdef CONFIG_SMP
^ permalink raw reply
* [PATCH 2/3] MSI power abstraction
From: Jake Moilanen @ 2006-06-07 21:15 UTC (permalink / raw)
To: linuxppc-dev; +Cc: paulus
In-Reply-To: <20060607160212.1203d9ea.moilanen@austin.ibm.com>
Instead of trying to make PPC64 MSI fit in a Intel-centric MSI layer, a
simple short-term solution is to hook the pci_{en/dis}able_msi() calls
and make a machdep call.
The rest of the MSI functions are superfluous for what is needed at this
time. Many of which can have machdep calls added as needed.
Ben and Michael Ellerman are looking into rewrite the MSI layer to be
more generic. However, in the meantime this works as a interim
solution.
Signed-off-by: Jake Moilanen <moilanen@austin.ibm.com>
Index: 2.6/arch/powerpc/kernel/irq.c
===================================================================
--- 2.6.orig/arch/powerpc/kernel/irq.c 2006-06-07 15:23:41.000000000 -0500
+++ 2.6/arch/powerpc/kernel/irq.c 2006-06-07 15:29:32.000000000 -0500
@@ -47,6 +47,7 @@
#include <linux/cpumask.h>
#include <linux/profile.h>
#include <linux/bitops.h>
+#include <linux/pci.h>
#include <asm/uaccess.h>
#include <asm/system.h>
@@ -436,6 +437,30 @@
}
EXPORT_SYMBOL(do_softirq);
+#ifdef CONFIG_PCI_MSI
+int pci_enable_msi(struct pci_dev * pdev)
+{
+ if (ppc_md.enable_msi)
+ return ppc_md.enable_msi(pdev);
+ else
+ return -1;
+}
+
+void pci_disable_msi(struct pci_dev * pdev)
+{
+ if (ppc_md.disable_msi)
+ ppc_md.disable_msi(pdev);
+}
+
+void pci_scan_msi_device(struct pci_dev *dev) {}
+int pci_enable_msix(struct pci_dev* dev, struct msix_entry *entries, int nvec) {return -1;}
+void pci_disable_msix(struct pci_dev *dev) {}
+void msi_remove_pci_irq_vectors(struct pci_dev *dev) {}
+void disable_msi_mode(struct pci_dev *dev, int pos, int type) {}
+void pci_no_msi(void) {}
+
+#endif
+
#ifdef CONFIG_PPC64
static int __init setup_noirqdistrib(char *str)
{
Index: 2.6/include/asm-powerpc/machdep.h
===================================================================
--- 2.6.orig/include/asm-powerpc/machdep.h 2006-06-07 15:23:41.000000000 -0500
+++ 2.6/include/asm-powerpc/machdep.h 2006-06-07 15:24:48.000000000 -0500
@@ -238,6 +238,11 @@
*/
void (*machine_kexec)(struct kimage *image);
#endif /* CONFIG_KEXEC */
+
+#ifdef CONFIG_PCI_MSI
+ int (*enable_msi)(struct pci_dev *pdev);
+ void (*disable_msi)(struct pci_dev *pdev);
+#endif /* CONFIG_PCI_MSI */
};
extern void power4_idle(void);
^ permalink raw reply
* [PATCH 1/3] PCIe device_type pciex
From: Jake Moilanen @ 2006-06-07 21:05 UTC (permalink / raw)
To: linuxppc-dev; +Cc: paulus
In-Reply-To: <20060607160212.1203d9ea.moilanen@austin.ibm.com>
This adds support to recognize the PCIe device_type "pciex" and made
the portdrv buildable.
Signed-off-by: Jake Moilanen <moilanen@austin.ibm.com>
Index: 2.6/arch/powerpc/Kconfig
===================================================================
--- 2.6.orig/arch/powerpc/Kconfig 2006-05-31 15:33:57.000000000 -0500
+++ 2.6/arch/powerpc/Kconfig 2006-05-31 15:34:10.000000000 -0500
@@ -849,6 +849,8 @@
endchoice
+source "drivers/pci/pcie/Kconfig"
+
source "drivers/pci/Kconfig"
source "drivers/pcmcia/Kconfig"
Index: 2.6/arch/powerpc/kernel/pci_64.c
===================================================================
--- 2.6.orig/arch/powerpc/kernel/pci_64.c 2006-05-31 15:33:57.000000000 -0500
+++ 2.6/arch/powerpc/kernel/pci_64.c 2006-05-31 15:34:10.000000000 -0500
@@ -396,7 +396,7 @@
dev->current_state = 4; /* unknown power state */
- if (!strcmp(type, "pci")) {
+ if (!strcmp(type, "pci") || !strcmp(type, "pciex")) {
/* a PCI-PCI bridge */
dev->hdr_type = PCI_HEADER_TYPE_BRIDGE;
dev->rom_base_reg = PCI_ROM_ADDRESS1;
Index: 2.6/arch/powerpc/kernel/rtas_pci.c
===================================================================
--- 2.6.orig/arch/powerpc/kernel/rtas_pci.c 2006-05-31 15:33:57.000000000 -0500
+++ 2.6/arch/powerpc/kernel/rtas_pci.c 2006-05-31 15:34:10.000000000 -0500
@@ -313,7 +313,9 @@
for (node = of_get_next_child(root, NULL);
node != NULL;
node = of_get_next_child(root, node)) {
- if (node->type == NULL || strcmp(node->type, "pci") != 0)
+
+ if (node->type == NULL || (strcmp(node->type, "pci") != 0 &&
+ strcmp(node->type, "pciex") != 0))
continue;
phb = pcibios_alloc_controller(node);
^ permalink raw reply
* [PATCH 0/3] PPC64 PCIe support
From: Jake Moilanen @ 2006-06-07 21:02 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Paul Mackerras
Here are the three patches for PCIe/MSI on pSeries for 2.6.18.
Since MSI is a requirement for PCIe, I have put these in one batch.
This is enough to probe, find, configure, and run basic I/O to PCIe
enabled devices. However, these patches do not include support for
PCIe hotplug, nor multiple MSI vectors.
There is a supplemental patches which will be needed in the
future. Specifically adding a PCIe bit for
ibm,client-architecture-support. To my knowledge this bit has not been
defined yet.
^ permalink raw reply
* Re: [Alsa-devel] [RFC 11/12] snd-aoa: add Kconfig and Makefile
From: Takashi Iwai @ 2006-06-07 18:50 UTC (permalink / raw)
To: Johannes Berg; +Cc: linuxppc-dev, alsa-devel, netstar
In-Reply-To: <20060607130917.996988000@sipsolutions.net>
At Wed, 07 Jun 2006 15:09:20 +0200,
Johannes Berg wrote:
>
> This patch adds the simple Kconfig and Makefile files for aoa.
>
> --- /dev/null
> +++ b/sound/aoa/Kconfig
> @@ -0,0 +1,17 @@
> +menu "Apple Onboard Audio driver"
> + depends on SND != n && PPC
> +
> +config SND_AOA
> + tristate "Apple Onboard Audio driver"
> + depends on SOUND && SND_PCM && EXPERIMENTAL
Let's remove EXPERIMENTAL. Or keep snd-powermac untouched.
Takashi
^ permalink raw reply
* Re: [Alsa-devel] [RFC 05/12] snd-aoa: add i2sbus
From: Takashi Iwai @ 2006-06-07 18:44 UTC (permalink / raw)
To: Johannes Berg; +Cc: linuxppc-dev, alsa-devel, netstar
In-Reply-To: <20060607130913.414650000@sipsolutions.net>
At Wed, 07 Jun 2006 15:09:14 +0200,
Johannes Berg wrote:
>
> --- /dev/null
> +++ b/sound/aoa/soundbus/i2sbus/i2sbus-pcm.c
> +static int clock_and_divisors(int mclk, int sclk, int rate, int *out)
> +{
> + /* sclk must be derived from mclk! */
> + if (mclk % sclk)
> + return -1;
> + /* derive sclk register value */
> + if (i2s_sf_sclkdiv(mclk / sclk, out))
> + return -1;
> +
> + if (I2S_CLOCK_SPEED_18MHz % (rate * mclk) == 0) {
> + if (!i2s_sf_mclkdiv(I2S_CLOCK_SPEED_18MHz / rate / mclk, out)) {
I'd use "I2S_CLOCK_SPEED_18MHZ / (rate * mclk)"
> --- /dev/null
> +++ b/sound/aoa/soundbus/i2sbus/i2sbus-core.c
> +static void i2sbus_release_dev(struct device *dev)
> +{
> + struct i2sbus_dev *i2sdev;
> + int i;
> +
> + i2sdev = container_of(dev, struct i2sbus_dev, sound.ofdev.dev);
> +
> + if (i2sdev->intfregs) iounmap(i2sdev->intfregs);
> + if (i2sdev->out.dbdma) iounmap(i2sdev->out.dbdma);
> + if (i2sdev->in.dbdma) iounmap(i2sdev->in.dbdma);
> + for (i=0;i<3;i++)
> + if (i2sdev->allocated_resource[i])
> + release_resource(i2sdev->allocated_resource[i]);
release_resource() doesn't kfree the record returned from
request_mem_region(). ALSA has a helper function
release_and_free_resource() that also does NULL check and kfree:
for (i = 0; i < 3; i++)
release_and_free_resource(i2sdev->allocated_resource[i]);
> +/* FIXME: look at device node refcounting */
> +static int i2sbus_add_dev(struct macio_dev *macio,
> + struct i2sbus_control *control,
> + struct device_node *np)
> +{
(snip)
> + for (i=0;i<3;i++)
> + if (dev->allocated_resource[i])
> + release_resource(dev->allocated_resource[i]);
Ditto.
Takashi
^ permalink raw reply
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