* RE: [PATCH/2.6.17-rc4 4/10]Powerpc: Add tsi108 pic support
From: Zang Roy-r61911 @ 2006-06-09 9:25 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Alexandre Bounine
Cc: linuxppc-dev list, Paul Mackerras, Yang Xin-Xin-r48390
>
> On Tue, 2006-06-06 at 10:45 -0400, Alexandre Bounine wrote:
>
> > We have a level-signalled irq from the cascaded PCI interrupt
> > controller. If I do EOI at this time, level request will not have
> > chance to be cleared (unless all PCI interrupts have an
> SA_INTERRUPT flag) and result in recurring interrupts.
>
> Hrm... Ok, when the cascade is a 8259 or an MPIC, we don't
> have that problem despite the output also being level... I
> think that's because the cascade handler itself will mask the
> cascade interrupt (on MPIC, reading the irq does an ack which
> will mask that priority level). If your cascaded controller
> doesn't act this way, you may need something a bit different
> in your cascade handler rather than changing mpic.
>
> However, I wouldn't bother too much. As I said, this is all
> changing a lot at the moment as I'm porting powerpc to Ingo
> Molnar and Thomas Gleixner's new "genirq" layer. Cascade
> handling will be different and taken out of MPIC, so you'll
> be able to implement it the way your want (with much greater
> control on what happens) without changing the MPIC driver.
>
> I'll have patches posted on the list in a few days hopefully.
>
> > I chose to have an individual flag instead of checking model ID to
> > avoid multiple checks within ISR (in case if we have more
> that one mpic version requiring this option). I also expect
> that it may be
> > useful for any external level-signalling cascades connected
> to MPIC.
>
> As I said above, I think it can just go away with the port to genirq.
>
> > Motivation is the same as above - I just do not want to
> have multiple
> > ID checks here. I agree that it is driven by mpic type (model ID)
> > only. I can remove this one if you do not expect any new
> "broken" MPICs on horizon.
>
> Well, I do expect broken ones but not with that specific issue :)
>
> Cheers,
> Ben.
>
update mpic support for tsi108 .
Any comment?
diff --git a/arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c b/arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c
index db5dc10..efee7da 100644
--- a/arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c
+++ b/arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c
@@ -43,7 +43,16 @@ #include <asm/pci-bridge.h> #include <asm/reg.h> #include <mm/mmu_decl.h> #include "mpc7448_hpc2.h"
-#include <asm/tsi108_pic.h>
+#include <asm/tsi108_irq.h>
+#include <asm/mpic.h>
+
+#undef DEBUG
+
+#ifdef DEBUG
+#define DBG(fmt...) do { printk(fmt); } while(0) #else #define
+DBG(fmt...) do { } while(0) #endif
#ifndef CONFIG_PCI
isa_io_base = MPC7448_HPC2_ISA_IO_BASE; @@ -53,20 +62,8 @@ #endif
extern int add_bridge(struct device_node *dev); extern void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val);
-
-#ifdef TSI108_ETH
-hw_info hw_info_table[TSI108_ETH_MAX_PORTS + 1] = {
- {TSI108_CSR_ADDR_PHYS + TSI108_ETH_OFFSET,
- TSI108_CSR_ADDR_PHYS + TSI108_ETH_OFFSET,
- TSI108_PHY0_ADDR, IRQ_TSI108_GIGE0},
-
- {TSI108_CSR_ADDR_PHYS + TSI108_ETH_OFFSET + 0x400,
- TSI108_CSR_ADDR_PHYS + TSI108_ETH_OFFSET,
- TSI108_PHY1_ADDR, IRQ_TSI108_GIGE1},
-
- {TBL_END, TBL_END, TBL_END, TBL_END}
-};
-#endif
+extern void tsi108_pci_int_init(void);
+extern int tsi108_irq_cascade(struct pt_regs *regs, void *unused);
/*
* Define all of the IRQ senses and polarities. Taken from the @@ -76,10 +73,32 @@ #endif
*/
static u_char mpc7448_hpc2_pic_initsenses[] __initdata = {
+ /* External on-board sources */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* INT[0] XINT0 from FPGA */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* INT[1] XINT1 from FPGA */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* INT[2] PHY_INT from both GIGE */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* INT[3] RESERVED */
+ /* Internal Tsi108/109 interrupt sources */
+ (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* Reserved IRQ */
+ (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* Reserved IRQ */
+ (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* Reserved IRQ */
+ (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* Reserved IRQ */
+ (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* DMA0 */
+ (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* DMA1 */
+ (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* DMA2 */
+ (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* DMA3 */
+ (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* UART0 */
+ (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* UART1 */
+ (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* I2C */
+ (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* GPIO */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* GIGE0 */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* GIGE1 */
+ (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* Reserved IRQ */
+ (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* HLP */
+ (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* SDC */
+ (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* Processor IF */
+ (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE), /* Reserved IRQ */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* PCI/X block */
};
/*
@@ -196,18 +215,43 @@ #endif
*/
static void __init mpc7448_hpc2_init_IRQ(void) {
+ struct mpic *mpic;
+ phys_addr_t mpic_paddr = 0;
+ struct device_node *tsi_pic;
+
+ tsi_pic = of_find_node_by_type(NULL, "open-pic");
+ if (tsi_pic) {
+ unsigned int size;
+ void *prop = get_property(tsi_pic, "reg", &size);
+ mpic_paddr = of_translate_address(tsi_pic, prop);
+ }
- tsi108_pic_init(mpc7448_hpc2_pic_initsenses);
+ if (mpic_paddr == 0) {
+ printk("%s: No tsi108 PIC found !\n", __FUNCTION__);
+ return;
+ }
- /* Configure MPIC outputs to CPU0 */
- tsi108_pic_set_output(0, IRQ_SENSE_EDGE, IRQ_POLARITY_NEGATIVE);
-}
+ DBG("%s: tsi108pic phys_addr = 0x%x\n", __FUNCTION__,
+ (u32) mpic_paddr);
-static void __init mpc7448_hpc2_map_io(void) -{
- /* Tsi108 CSR mapping */
- io_block_mapping(TSI108_CSR_ADDR_VIRT, TSI108_CSR_ADDR_PHYS,
- 0x100000, _PAGE_IO);
+ mpic = mpic_alloc(mpic_paddr,
+ MPIC_PRIMARY | MPIC_BIG_ENDIAN | MPIC_WANTS_RESET |
+ MPIC_SPV_EOI | MPIC_MOD_ID(MPIC_ID_TSI108),
+ 0, /* num_sources used */
+ TSI108_IRQ_BASE,
+ 0, /* num_sources used */
+ NR_IRQS - 4 /* XXXX */,
+ mpc7448_hpc2_pic_initsenses,
+ sizeof(mpc7448_hpc2_pic_initsenses), "Tsi108_PIC");
+
+ BUG_ON(mpic == NULL); /* XXXX */
+
+ mpic_init(mpic);
+ mpic_setup_cascade(IRQ_TSI108_PCI, tsi108_irq_cascade, mpic);
+ tsi108_pci_int_init();
+
+ /* Configure MPIC outputs to CPU0 */
+ tsi108_write_reg(TSI108_MPIC_OFFSET + 0x30c, 0);
}
void mpc7448_hpc2_show_cpuinfo(struct seq_file *m) @@ -269,10 +313,9 @@ define_machine(mpc7448_hpc2){
.setup_arch = mpc7448_hpc2_setup_arch,
.init_IRQ = mpc7448_hpc2_init_IRQ,
.show_cpuinfo = mpc7448_hpc2_show_cpuinfo,
- .get_irq = tsi108_pic_get_irq,
+ .get_irq = mpic_get_irq,
.restart = mpc7448_hpc2_restart,
.calibrate_decr = generic_calibrate_decr,
- .setup_io_mappings = mpc7448_hpc2_map_io,
.machine_check_exception= mpc7448_machine_check_exception,
.progress = udbg_progress,
};
diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile index 8c0afb7..048e1f6 100644
--- a/arch/powerpc/sysdev/Makefile
+++ b/arch/powerpc/sysdev/Makefile
@@ -8,4 +8,4 @@ obj-$(CONFIG_U3_DART) += dart_iommu.o
obj-$(CONFIG_MMIO_NVRAM) += mmio_nvram.o
obj-$(CONFIG_PPC_83xx) += ipic.o
obj-$(CONFIG_FSL_SOC) += fsl_soc.o
-obj-$(CONFIG_TSI108_BRIDGE) += tsi108_common.o tsi108_pic.o
+obj-$(CONFIG_TSI108_BRIDGE) += tsi108_common.o tsi108_pci_int.o
diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c index 7dcdfcb..fc21e47 100644
--- a/arch/powerpc/sysdev/mpic.c
+++ b/arch/powerpc/sysdev/mpic.c
@@ -55,6 +55,78 @@ #define distribute_irqs (0)
#endif
#endif
+static struct mpic_info mpic_infos[] = {
+ [0] = { /* Original OpenPIC compatible MPIC */
+ .greg_base = MPIC_GREG_BASE,
+ .greg_frr0 = MPIC_GREG_FEATURE_0,
+ .greg_config0 = MPIC_GREG_GLOBAL_CONF_0,
+ .greg_vendor_id = MPIC_GREG_VENDOR_ID,
+ .greg_ipi_vp0 = MPIC_GREG_IPI_VECTOR_PRI_0,
+ .greg_ipi_stride = MPIC_GREG_IPI_STRIDE,
+ .greg_spurious = MPIC_GREG_SPURIOUS,
+ .greg_tfrr = MPIC_GREG_TIMER_FREQ,
+
+ .timer_base = MPIC_TIMER_BASE,
+ .timer_stride = MPIC_TIMER_STRIDE,
+ .timer_ccr = MPIC_TIMER_CURRENT_CNT,
+ .timer_bcr = MPIC_TIMER_BASE_CNT,
+ .timer_vpr = MPIC_TIMER_VECTOR_PRI,
+ .timer_dest = MPIC_TIMER_DESTINATION,
+
+ .cpu_base = MPIC_CPU_BASE,
+ .cpu_stride = MPIC_CPU_STRIDE,
+ .cpu_ipi_disp0 = MPIC_CPU_IPI_DISPATCH_0,
+ .cpu_ipi_disp_stride = MPIC_CPU_IPI_DISPATCH_STRIDE,
+ .cpu_task_pri = MPIC_CPU_CURRENT_TASK_PRI,
+ .cpu_whoami = MPIC_CPU_WHOAMI,
+ .cpu_intack = MPIC_CPU_INTACK,
+ .cpu_eoi = MPIC_CPU_EOI,
+
+ .irq_base = MPIC_IRQ_BASE,
+ .irq_stride = MPIC_IRQ_STRIDE,
+ .irq_vpr = MPIC_IRQ_VECTOR_PRI,
+ .irq_vpr_vector = MPIC_VECPRI_VECTOR_MASK,
+ .irq_vpr_polpos = MPIC_VECPRI_POLARITY_POSITIVE,
+ .irq_vpr_senlvl = MPIC_VECPRI_SENSE_LEVEL,
+ .irq_dest = MPIC_IRQ_DESTINATION,
+ },
+
+ [1] = { /* Tsi108/109 PIC */
+ .greg_base = TSI108_GREG_BASE,
+ .greg_frr0 = TSI108_GREG_FEATURE_0,
+ .greg_config0 = TSI108_GREG_GLOBAL_CONF_0,
+ .greg_vendor_id = TSI108_GREG_VENDOR_ID,
+ .greg_ipi_vp0 = TSI108_GREG_IPI_VECTOR_PRI_0,
+ .greg_ipi_stride = TSI108_GREG_IPI_STRIDE,
+ .greg_spurious = TSI108_GREG_SPURIOUS,
+ .greg_tfrr = TSI108_GREG_TIMER_FREQ,
+
+ .timer_base = TSI108_TIMER_BASE,
+ .timer_stride = TSI108_TIMER_STRIDE,
+ .timer_ccr = TSI108_TIMER_CURRENT_CNT,
+ .timer_bcr = TSI108_TIMER_BASE_CNT,
+ .timer_vpr = TSI108_TIMER_VECTOR_PRI,
+ .timer_dest = TSI108_TIMER_DESTINATION,
+
+ .cpu_base = TSI108_CPU_BASE,
+ .cpu_stride = TSI108_CPU_STRIDE,
+ .cpu_ipi_disp0 = TSI108_CPU_IPI_DISPATCH_0,
+ .cpu_ipi_disp_stride = TSI108_CPU_IPI_DISPATCH_STRIDE,
+ .cpu_task_pri = TSI108_CPU_CURRENT_TASK_PRI,
+ .cpu_whoami = 0xFFFFFFFF,
+ .cpu_intack = TSI108_CPU_INTACK,
+ .cpu_eoi = TSI108_CPU_EOI,
+
+ .irq_base = TSI108_IRQ_REG_BASE,
+ .irq_stride = TSI108_IRQ_STRIDE,
+ .irq_vpr = TSI108_IRQ_VECTOR_PRI,
+ .irq_vpr_vector = TSI108_VECPRI_VECTOR_MASK,
+ .irq_vpr_polpos = TSI108_VECPRI_POLARITY_POSITIVE,
+ .irq_vpr_senlvl = TSI108_VECPRI_SENSE_LEVEL,
+ .irq_dest = TSI108_IRQ_DESTINATION,
+ },
+};
+
/*
* Register accessor functions
*/
@@ -81,7 +153,8 @@ static inline void _mpic_write(unsigned static inline u32 _mpic_ipi_read(struct mpic *mpic, unsigned int ipi) {
unsigned int be = (mpic->flags & MPIC_BIG_ENDIAN) != 0;
- unsigned int offset = MPIC_GREG_IPI_VECTOR_PRI_0 + (ipi * 0x10);
+ unsigned int offset = mpic->hw_set->greg_ipi_vp0 +
+ (ipi * mpic->hw_set->greg_ipi_stride);
if (mpic->flags & MPIC_BROKEN_IPI)
be = !be;
@@ -90,7 +163,8 @@ static inline u32 _mpic_ipi_read(struct
static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 value) {
- unsigned int offset = MPIC_GREG_IPI_VECTOR_PRI_0 + (ipi * 0x10);
+ unsigned int offset = mpic->hw_set->greg_ipi_vp0 +
+ (ipi * mpic->hw_set->greg_ipi_stride);
_mpic_write(mpic->flags & MPIC_BIG_ENDIAN, mpic->gregs, offset, value); } @@ -121,7 +195,7 @@ static inline u32 _mpic_irq_read(struct
unsigned int idx = src_no & mpic->isu_mask;
return _mpic_read(mpic->flags & MPIC_BIG_ENDIAN, mpic->isus[isu],
- reg + (idx * MPIC_IRQ_STRIDE));
+ reg + (idx * mpic->hw_set->irq_stride));
}
static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no, @@ -131,7 +205,7 @@ static inline void _mpic_irq_write(struc
unsigned int idx = src_no & mpic->isu_mask;
_mpic_write(mpic->flags & MPIC_BIG_ENDIAN, mpic->isus[isu],
- reg + (idx * MPIC_IRQ_STRIDE), value);
+ reg + (idx * mpic->hw_set->irq_stride), value);
}
#define mpic_read(b,r) _mpic_read(mpic->flags & MPIC_BIG_ENDIAN,(b),(r))
@@ -157,8 +231,8 @@ static void __init mpic_test_broken_ipi( {
u32 r;
- mpic_write(mpic->gregs, MPIC_GREG_IPI_VECTOR_PRI_0, MPIC_VECPRI_MASK);
- r = mpic_read(mpic->gregs, MPIC_GREG_IPI_VECTOR_PRI_0);
+ mpic_write(mpic->gregs, mpic->hw_set->greg_ipi_vp0, MPIC_VECPRI_MASK);
+ r = mpic_read(mpic->gregs, mpic->hw_set->greg_ipi_vp0);
if (r == le32_to_cpu(MPIC_VECPRI_MASK)) {
printk(KERN_INFO "mpic: Detected reversed IPI registers\n"); @@ -392,8 +466,8 @@ static inline struct mpic * mpic_from_ir
/* Send an EOI */
static inline void mpic_eoi(struct mpic *mpic) {
- mpic_cpu_write(MPIC_CPU_EOI, 0);
- (void)mpic_cpu_read(MPIC_CPU_WHOAMI);
+ mpic_cpu_write(mpic->hw_set->cpu_eoi, 0);
+ (void)mpic_cpu_read(mpic->hw_set->cpu_task_pri);
}
#ifdef CONFIG_SMP
@@ -419,8 +493,8 @@ static void mpic_enable_irq(unsigned int
DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, irq, src);
- mpic_irq_write(src, MPIC_IRQ_VECTOR_PRI,
- mpic_irq_read(src, MPIC_IRQ_VECTOR_PRI) &
+ mpic_irq_write(src, mpic->hw_set->irq_vpr,
+ mpic_irq_read(src, mpic->hw_set->irq_vpr) &
~MPIC_VECPRI_MASK);
/* make sure mask gets to controller before we return to user */ @@ -429,7 +503,7 @@ static void mpic_enable_irq(unsigned int
printk(KERN_ERR "mpic_enable_irq timeout\n");
break;
}
- } while(mpic_irq_read(src, MPIC_IRQ_VECTOR_PRI) & MPIC_VECPRI_MASK);
+ } while(mpic_irq_read(src, mpic->hw_set->irq_vpr) & MPIC_VECPRI_MASK);
#ifdef CONFIG_MPIC_BROKEN_U3
if (mpic->flags & MPIC_BROKEN_U3) {
@@ -466,8 +540,8 @@ static void mpic_disable_irq(unsigned in
DBG("%s: disable_irq: %d (src %d)\n", mpic->name, irq, src);
- mpic_irq_write(src, MPIC_IRQ_VECTOR_PRI,
- mpic_irq_read(src, MPIC_IRQ_VECTOR_PRI) |
+ mpic_irq_write(src, mpic->hw_set->irq_vpr,
+ mpic_irq_read(src, mpic->hw_set->irq_vpr) |
MPIC_VECPRI_MASK);
/* make sure mask gets to controller before we return to user */ @@ -476,7 +550,7 @@ static void mpic_disable_irq(unsigned in
printk(KERN_ERR "mpic_enable_irq timeout\n");
break;
}
- } while(!(mpic_irq_read(src, MPIC_IRQ_VECTOR_PRI) & MPIC_VECPRI_MASK));
+ } while(!(mpic_irq_read(src, mpic->hw_set->irq_vpr) &
+MPIC_VECPRI_MASK));
}
static void mpic_shutdown_irq(unsigned int irq) @@ -557,7 +631,7 @@ static void mpic_set_affinity(unsigned i
cpus_and(tmp, cpumask, cpu_online_map);
- mpic_irq_write(irq - mpic->irq_offset, MPIC_IRQ_DESTINATION,
+ mpic_irq_write(irq - mpic->irq_offset, mpic->hw_set->irq_dest,
mpic_physmask(cpus_addr(tmp)[0]));
}
@@ -613,18 +687,20 @@ #endif /* CONFIG_SMP */
mpic->num_sources = 0; /* so far */
mpic->senses = senses;
mpic->senses_count = senses_count;
+ mpic->hw_set = &mpic_infos[MPIC_GET_MOD_ID(flags)];
/* Map the global registers */
- mpic->gregs = ioremap(phys_addr + MPIC_GREG_BASE, 0x1000);
- mpic->tmregs = mpic->gregs + ((MPIC_TIMER_BASE - MPIC_GREG_BASE) >> 2);
+ mpic->gregs = ioremap(phys_addr + mpic->hw_set->greg_base, 0x1000);
+ mpic->tmregs = mpic->gregs +
+ ((mpic->hw_set->timer_base - mpic->hw_set->greg_base) >> 2);
BUG_ON(mpic->gregs == NULL);
/* Reset */
if (flags & MPIC_WANTS_RESET) {
- mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_0,
- mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_0)
+ mpic_write(mpic->gregs, mpic->hw_set->greg_config0,
+ mpic_read(mpic->gregs, mpic->hw_set->greg_config0)
| MPIC_GREG_GCONF_RESET);
- while( mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_0)
+ while( mpic_read(mpic->gregs, mpic->hw_set->greg_config0)
& MPIC_GREG_GCONF_RESET)
mb();
}
@@ -633,7 +709,7 @@ #endif /* CONFIG_SMP */
* MPICs, num sources as well. On ISU MPICs, sources are counted
* as ISUs are added
*/
- reg = mpic_read(mpic->gregs, MPIC_GREG_FEATURE_0);
+ reg = mpic_read(mpic->gregs, mpic->hw_set->greg_frr0);
mpic->num_cpus = ((reg & MPIC_GREG_FEATURE_LAST_CPU_MASK)
>> MPIC_GREG_FEATURE_LAST_CPU_SHIFT) + 1;
if (isu_size == 0)
@@ -642,16 +718,16 @@ #endif /* CONFIG_SMP */
/* Map the per-CPU registers */
for (i = 0; i < mpic->num_cpus; i++) {
- mpic->cpuregs[i] = ioremap(phys_addr + MPIC_CPU_BASE +
- i * MPIC_CPU_STRIDE, 0x1000);
+ mpic->cpuregs[i] = ioremap(phys_addr + mpic->hw_set->cpu_base +
+ i * mpic->hw_set->cpu_stride, 0x1000);
BUG_ON(mpic->cpuregs[i] == NULL);
}
/* Initialize main ISU if none provided */
if (mpic->isu_size == 0) {
mpic->isu_size = mpic->num_sources;
- mpic->isus[0] = ioremap(phys_addr + MPIC_IRQ_BASE,
- MPIC_IRQ_STRIDE * mpic->isu_size);
+ mpic->isus[0] = ioremap(phys_addr + mpic->hw_set->irq_base,
+ mpic->hw_set->irq_stride * mpic->isu_size);
BUG_ON(mpic->isus[0] == NULL);
}
mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1); @@ -693,7 +769,8 @@ void __init mpic_assign_isu(struct mpic
BUG_ON(isu_num >= MPIC_MAX_ISU);
- mpic->isus[isu_num] = ioremap(phys_addr, MPIC_IRQ_STRIDE * mpic->isu_size);
+ mpic->isus[isu_num] = ioremap(phys_addr,
+ mpic->hw_set->irq_stride * mpic->isu_size);
if ((isu_first + mpic->isu_size) > mpic->num_sources)
mpic->num_sources = isu_first + mpic->isu_size; } @@ -729,14 +806,15 @@ void __init mpic_init(struct mpic *mpic)
printk(KERN_INFO "mpic: Initializing for %d sources\n", mpic->num_sources);
/* Set current processor priority to max */
- mpic_cpu_write(MPIC_CPU_CURRENT_TASK_PRI, 0xf);
+ mpic_cpu_write(mpic->hw_set->cpu_task_pri, 0xf);
/* Initialize timers: just disable them all */
for (i = 0; i < 4; i++) {
mpic_write(mpic->tmregs,
- i * MPIC_TIMER_STRIDE + MPIC_TIMER_DESTINATION, 0);
+ i * mpic->hw_set->timer_stride +
+ mpic->hw_set->timer_dest, 0);
mpic_write(mpic->tmregs,
- i * MPIC_TIMER_STRIDE + MPIC_TIMER_VECTOR_PRI,
+ i * mpic->hw_set->timer_stride + mpic->hw_set->timer_vpr,
MPIC_VECPRI_MASK |
(MPIC_VEC_TIMER_0 + i));
}
@@ -780,14 +858,14 @@ #endif /* CONFIG_MPIC_BROKEN_U3 */
/* do senses munging */
if (mpic->senses && i < mpic->senses_count) {
if (mpic->senses[i] & IRQ_SENSE_LEVEL)
- vecpri |= MPIC_VECPRI_SENSE_LEVEL;
+ vecpri |= mpic->hw_set->irq_vpr_senlvl;
if (mpic->senses[i] & IRQ_POLARITY_POSITIVE)
- vecpri |= MPIC_VECPRI_POLARITY_POSITIVE;
+ vecpri |= mpic->hw_set->irq_vpr_polpos;
} else
- vecpri |= MPIC_VECPRI_SENSE_LEVEL;
+ vecpri |= mpic->hw_set->irq_vpr_senlvl;
/* remember if it was a level interrupts */
- level = (vecpri & MPIC_VECPRI_SENSE_LEVEL);
+ level = (vecpri & mpic->hw_set->irq_vpr_senlvl);
/* deal with broken U3 */
if (mpic->flags & MPIC_BROKEN_U3) {
@@ -795,7 +873,7 @@ #ifdef CONFIG_MPIC_BROKEN_U3
if (mpic_is_ht_interrupt(mpic, i)) {
vecpri &= ~(MPIC_VECPRI_SENSE_MASK |
MPIC_VECPRI_POLARITY_MASK);
- vecpri |= MPIC_VECPRI_POLARITY_POSITIVE;
+ vecpri |= mpic->hw_set->irq_vpr_polpos;
}
#else
printk(KERN_ERR "mpic: BROKEN_U3 set, but CONFIG doesn't match\n"); @@ -806,8 +884,8 @@ #endif
(level != 0));
/* init hw */
- mpic_irq_write(i, MPIC_IRQ_VECTOR_PRI, vecpri);
- mpic_irq_write(i, MPIC_IRQ_DESTINATION,
+ mpic_irq_write(i, mpic->hw_set->irq_vpr, vecpri);
+ mpic_irq_write(i, mpic->hw_set->irq_dest,
1 << hard_smp_processor_id());
/* init linux descriptors */
@@ -818,15 +896,16 @@ #endif
}
/* Init spurrious vector */
- mpic_write(mpic->gregs, MPIC_GREG_SPURIOUS, MPIC_VEC_SPURRIOUS);
+ mpic_write(mpic->gregs, mpic->hw_set->greg_spurious,
+MPIC_VEC_SPURRIOUS);
- /* Disable 8259 passthrough */
- mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_0,
- mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_0)
- | MPIC_GREG_GCONF_8259_PTHROU_DIS);
+ /* Disable 8259 passthrough, if supported */
+ if (MPIC_GET_MOD_ID(mpic->flags) != MPIC_ID_TSI108)
+ mpic_write(mpic->gregs, mpic->hw_set->greg_config0,
+ mpic_read(mpic->gregs, mpic->hw_set->greg_config0)
+ | MPIC_GREG_GCONF_8259_PTHROU_DIS);
/* Set current processor priority to 0 */
- mpic_cpu_write(MPIC_CPU_CURRENT_TASK_PRI, 0);
+ mpic_cpu_write(mpic->hw_set->cpu_task_pri, 0);
}
@@ -845,9 +924,9 @@ void mpic_irq_set_priority(unsigned int
mpic_ipi_write(irq - mpic->ipi_offset,
reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
} else {
- reg = mpic_irq_read(irq - mpic->irq_offset,MPIC_IRQ_VECTOR_PRI)
+ reg = mpic_irq_read(irq - mpic->irq_offset,mpic->hw_set->irq_vpr)
& ~MPIC_VECPRI_PRIORITY_MASK;
- mpic_irq_write(irq - mpic->irq_offset, MPIC_IRQ_VECTOR_PRI,
+ mpic_irq_write(irq - mpic->irq_offset, mpic->hw_set->irq_vpr,
reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
}
spin_unlock_irqrestore(&mpic_lock, flags); @@ -864,7 +943,7 @@ unsigned int mpic_irq_get_priority(unsig
if (is_ipi)
reg = mpic_ipi_read(irq - mpic->ipi_offset);
else
- reg = mpic_irq_read(irq - mpic->irq_offset, MPIC_IRQ_VECTOR_PRI);
+ reg = mpic_irq_read(irq - mpic->irq_offset, mpic->hw_set->irq_vpr);
spin_unlock_irqrestore(&mpic_lock, flags);
return (reg & MPIC_VECPRI_PRIORITY_MASK) >> MPIC_VECPRI_PRIORITY_SHIFT; } @@ -890,12 +969,12 @@ #ifdef CONFIG_SMP
*/
if (distribute_irqs) {
for (i = 0; i < mpic->num_sources ; i++)
- mpic_irq_write(i, MPIC_IRQ_DESTINATION,
- mpic_irq_read(i, MPIC_IRQ_DESTINATION) | msk);
+ mpic_irq_write(i, mpic->hw_set->irq_dest,
+ mpic_irq_read(i, mpic->hw_set->irq_dest) | msk);
}
/* Set current processor priority to 0 */
- mpic_cpu_write(MPIC_CPU_CURRENT_TASK_PRI, 0);
+ mpic_cpu_write(mpic->hw_set->cpu_task_pri, 0);
spin_unlock_irqrestore(&mpic_lock, flags); #endif /* CONFIG_SMP */ @@ -905,7 +984,7 @@ int mpic_cpu_get_priority(void) {
struct mpic *mpic = mpic_primary;
- return mpic_cpu_read(MPIC_CPU_CURRENT_TASK_PRI);
+ return mpic_cpu_read(mpic->hw_set->cpu_task_pri);
}
void mpic_cpu_set_priority(int prio)
@@ -913,7 +992,7 @@ void mpic_cpu_set_priority(int prio)
struct mpic *mpic = mpic_primary;
prio &= MPIC_CPU_TASKPRI_MASK;
- mpic_cpu_write(MPIC_CPU_CURRENT_TASK_PRI, prio);
+ mpic_cpu_write(mpic->hw_set->cpu_task_pri, prio);
}
/*
@@ -935,11 +1014,11 @@ void mpic_teardown_this_cpu(int secondar
/* let the mpic know we don't want intrs. */
for (i = 0; i < mpic->num_sources ; i++)
- mpic_irq_write(i, MPIC_IRQ_DESTINATION,
- mpic_irq_read(i, MPIC_IRQ_DESTINATION) & ~msk);
+ mpic_irq_write(i, mpic->hw_set->irq_dest,
+ mpic_irq_read(i, mpic->hw_set->irq_dest) & ~msk);
/* Set current processor priority to max */
- mpic_cpu_write(MPIC_CPU_CURRENT_TASK_PRI, 0xf);
+ mpic_cpu_write(mpic->hw_set->cpu_task_pri, 0xf);
spin_unlock_irqrestore(&mpic_lock, flags); } @@ -955,7 +1034,8 @@ #ifdef DEBUG_IPI
DBG("%s: send_ipi(ipi_no: %d)\n", mpic->name, ipi_no); #endif
- mpic_cpu_write(MPIC_CPU_IPI_DISPATCH_0 + ipi_no * 0x10,
+ mpic_cpu_write(mpic->hw_set->cpu_ipi_disp0 +
+ ipi_no * mpic->hw_set->cpu_ipi_disp_stride,
mpic_physmask(cpu_mask & cpus_addr(cpu_online_map)[0])); }
@@ -963,7 +1043,7 @@ int mpic_get_one_irq(struct mpic *mpic, {
u32 irq;
- irq = mpic_cpu_read(MPIC_CPU_INTACK) & MPIC_VECPRI_VECTOR_MASK;
+ irq = mpic_cpu_read(mpic->hw_set->cpu_intack) &
+mpic->hw_set->irq_vpr_vector;
#ifdef DEBUG_LOW
DBG("%s: get_one_irq(): %d\n", mpic->name, irq); #endif @@ -972,11 +1052,17 @@ #ifdef DEBUG_LOW
DBG("%s: cascading ...\n", mpic->name); #endif
irq = mpic->cascade(regs, mpic->cascade_data);
+#ifdef DEBUG_LOW
+ DBG("%s: cascaded irq: %d\n", mpic->name, irq); #endif
mpic_eoi(mpic);
return irq;
}
- if (unlikely(irq == MPIC_VEC_SPURRIOUS))
+ if (unlikely(irq == MPIC_VEC_SPURRIOUS)) {
+ if (mpic->flags & MPIC_SPV_EOI)
+ mpic_eoi(mpic);
return -1;
+ }
if (irq < MPIC_VEC_IPI_0) {
#ifdef DEBUG_IRQ
DBG("%s: irq %d\n", mpic->name, irq + mpic->irq_offset); diff --git a/arch/powerpc/sysdev/tsi108_common.c b/arch/powerpc/sysdev/tsi108_common.c
index 3c55f99..03b5d8f 100644
--- a/arch/powerpc/sysdev/tsi108_common.c
+++ b/arch/powerpc/sysdev/tsi108_common.c
@@ -90,9 +90,13 @@ tsi108_direct_write_config(struct pci_bu {
volatile unsigned char *cfg_addr;
+ if (ppc_md.pci_exclude_device)
+ if (ppc_md.pci_exclude_device(bus->number, devfunc))
+ return PCIBIOS_DEVICE_NOT_FOUND;
+
cfg_addr = (unsigned char *)(tsi_mk_config_addr(bus->number,
devfunc, offset) |
- (offset & 0x03));
+ (offset & 0x03));
#ifdef TSI108_PCI_DEBUG
printk("PCI CFG write : ");
@@ -172,6 +176,10 @@ tsi108_direct_read_config(struct pci_bus
volatile unsigned char *cfg_addr;
u32 temp;
+ if (ppc_md.pci_exclude_device)
+ if (ppc_md.pci_exclude_device(bus->number, devfn))
+ return PCIBIOS_DEVICE_NOT_FOUND;
+
cfg_addr = (unsigned char *)(tsi_mk_config_addr(bus->number,
devfn,
offset) | (offset &
diff --git a/include/asm-powerpc/mpic.h b/include/asm-powerpc/mpic.h index 6b9e781..72131a4 100644
--- a/include/asm-powerpc/mpic.h
+++ b/include/asm-powerpc/mpic.h
@@ -37,6 +37,7 @@ #define MPIC_GREG_IPI_VECTOR_PRI_0 0x000
#define MPIC_GREG_IPI_VECTOR_PRI_1 0x000b0
#define MPIC_GREG_IPI_VECTOR_PRI_2 0x000c0
#define MPIC_GREG_IPI_VECTOR_PRI_3 0x000d0
+#define MPIC_GREG_IPI_STRIDE 0x10
#define MPIC_GREG_SPURIOUS 0x000e0
#define MPIC_GREG_TIMER_FREQ 0x000f0
@@ -64,6 +65,7 @@ #define MPIC_CPU_IPI_DISPATCH_0 0x00040
#define MPIC_CPU_IPI_DISPATCH_1 0x00050
#define MPIC_CPU_IPI_DISPATCH_2 0x00060
#define MPIC_CPU_IPI_DISPATCH_3 0x00070
+#define MPIC_CPU_IPI_DISPATCH_STRIDE 0x00010
#define MPIC_CPU_CURRENT_TASK_PRI 0x00080
#define MPIC_CPU_TASKPRI_MASK 0x0000000f
#define MPIC_CPU_WHOAMI 0x00090
@@ -91,6 +93,55 @@ #define MPIC_VECPRI_SENSE_EDGE 0x0000
#define MPIC_VECPRI_SENSE_MASK 0x00400000
#define MPIC_IRQ_DESTINATION 0x00010
+/**********************************************************************
+********
+ * Tsi108 implementation of MPIC has many differences form the original
+one */
+
+/*
+ * Global registers
+ */
+
+#define TSI108_GREG_BASE 0x00000
+#define TSI108_GREG_FEATURE_0 0x00000
+#define TSI108_GREG_GLOBAL_CONF_0 0x00004
+#define TSI108_GREG_VENDOR_ID 0x0000c
+#define TSI108_GREG_IPI_VECTOR_PRI_0 0x00204 /* Doorbell 0 */
+#define TSI108_GREG_IPI_STRIDE 0x0c
+#define TSI108_GREG_SPURIOUS 0x00010
+#define TSI108_GREG_TIMER_FREQ 0x00014
+
+/*
+ * Timer registers
+ */
+#define TSI108_TIMER_BASE 0x0030
+#define TSI108_TIMER_STRIDE 0x10
+#define TSI108_TIMER_CURRENT_CNT 0x00000
+#define TSI108_TIMER_BASE_CNT 0x00004
+#define TSI108_TIMER_VECTOR_PRI 0x00008
+#define TSI108_TIMER_DESTINATION 0x0000c
+
+/*
+ * Per-Processor registers
+ */
+#define TSI108_CPU_BASE 0x00300
+#define TSI108_CPU_STRIDE 0x00040
+#define TSI108_CPU_IPI_DISPATCH_0 0x00200
+#define TSI108_CPU_IPI_DISPATCH_STRIDE 0x00000
+#define TSI108_CPU_CURRENT_TASK_PRI 0x00000
+#define TSI108_CPU_INTACK 0x00004
+#define TSI108_CPU_EOI 0x00008
+
+/*
+ * Per-source registers
+ */
+#define TSI108_IRQ_REG_BASE 0x00100
+#define TSI108_IRQ_STRIDE 0x00008
+#define TSI108_IRQ_VECTOR_PRI 0x00000
+#define TSI108_VECPRI_VECTOR_MASK 0x000000ff
+#define TSI108_VECPRI_POLARITY_POSITIVE 0x01000000
+#define TSI108_VECPRI_SENSE_LEVEL 0x02000000
+#define TSI108_IRQ_DESTINATION 0x00004
+
#define MPIC_MAX_IRQ_SOURCES 2048
#define MPIC_MAX_CPUS 32
#define MPIC_MAX_ISU 32
@@ -124,6 +175,40 @@ struct mpic_irq_fixup }; #endif /* CONFIG_MPIC_BROKEN_U3 */
+struct mpic_info {
+ u32 greg_base; /* offset of global registers from MPIC base */
+ u32 greg_frr0; /* FRR0 offset from base */
+ u32 greg_config0; /* Global Config register offset from base */
+ u32 greg_vendor_id; /* VID register offset from base */
+ u32 greg_ipi_vp0; /* IPI Vector/Priority Registers */
+ u32 greg_ipi_stride; /* IPI Vector/Priority Registers spacing */
+ u32 greg_spurious; /* Spurious Vector Register */
+ u32 greg_tfrr; /* Global Timer Frequency Reporting Register */
+
+ u32 timer_base; /* Global Timer Registers base */
+ u32 timer_stride; /* Global Timer Registers spacing */
+ u32 timer_ccr; /* Global Timer Current Count Register */
+ u32 timer_bcr; /* Global Timer Base Count Register */
+ u32 timer_vpr; /* Global Timer Vector/Priority Register */
+ u32 timer_dest; /* Global Timer Destination Register */
+
+ u32 cpu_base; /* Global Timer Destination Register */
+ u32 cpu_stride; /* Global Timer Destination Register */
+ u32 cpu_ipi_disp0; /* IPI 0 Dispatch Command Register */
+ u32 cpu_ipi_disp_stride; /* IPI Dispatch spacing */
+ u32 cpu_task_pri; /* Processor Current Task Priority Register */
+ u32 cpu_whoami; /* Who Am I Register */
+ u32 cpu_intack; /* Interrupt Acknowledge Register */
+ u32 cpu_eoi; /* End of Interrupt Register */
+
+ u32 irq_base; /* Interrupt registers base */
+ u32 irq_stride; /* Interrupt registers spacing */
+ u32 irq_vpr; /* Interrupt Vector/Priority Register */
+ u32 irq_vpr_vector; /* Interrupt Vector Mask */
+ u32 irq_vpr_polpos; /* Interrupt Positive Polarity bit */
+ u32 irq_vpr_senlvl; /* Interrupt Level Sense bit */
+ u32 irq_dest; /* Interrupt Destination Register */
+};
/* The instance data of a given MPIC */ struct mpic @@ -168,6 +253,8 @@ #endif
volatile u32 __iomem *tmregs;
volatile u32 __iomem *cpuregs[MPIC_MAX_CPUS];
volatile u32 __iomem *isus[MPIC_MAX_ISU];
+ /* Pointer to HW info structure */
+ struct mpic_info *hw_set;
/* link */
struct mpic *next;
@@ -186,6 +273,14 @@ #define MPIC_BROKEN_U3 0x00000004
#define MPIC_BROKEN_IPI 0x00000008
/* MPIC wants a reset */
#define MPIC_WANTS_RESET 0x00000010
+/* Spurious vector requires EOI */
+#define MPIC_SPV_EOI 0x00000020
+/* MPIC HW modification ID */
+#define MPIC_MOD_ID_MASK 0x00000f00
+#define MPIC_MOD_ID(val) (((val) << 8) & MPIC_MOD_ID_MASK)
+#define MPIC_GET_MOD_ID(flags) (((flags) & MPIC_MOD_ID_MASK) >> 8)
+#define MPIC_ID_MPIC 0 /* Original MPIC */
+#define MPIC_ID_TSI108 1 /* Tsi108/109 PIC */
/* Allocate the controller structure and setup the linux irq descs
* for the range if interrupts passed in. No HW initialization is diff --git a/include/asm-powerpc/tsi108.h b/include/asm-powerpc/tsi108.h index ed9ec36..850c56d 100644
--- a/include/asm-powerpc/tsi108.h
+++ b/include/asm-powerpc/tsi108.h
@@ -55,6 +55,7 @@ #define TSI108_PCI_IRP_ENABLE (0x188)
#define TSI108_PCI_IRP_INTAD (0x18C)
#define TSI108_PCI_IRP_STAT_P_INT (0x00400000)
+#define TSI108_PCI_IRP_ENABLE_P_INT (0x00400000)
#define TSI108_CG_PWRUP_STATUS (0x234)
diff --git a/arch/powerpc/sysdev/tsi108_pci_int.c b/arch/powerpc/sysdev/tsi108_pci_int.c
index e69de29..c1ca187 100644
--- a/arch/powerpc/sysdev/tsi108_pci_int.c
+++ b/arch/powerpc/sysdev/tsi108_pci_int.c
@@ -0,0 +1,232 @@
+/*
+ * (C) Copyright 2005 Tundra Semiconductor Corp.
+ * Alex Bounine, <alexandreb@tundra.com).
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Tsi108 PCI Interrupt Handling (cascaded to MPIC) */
+
+#include <linux/config.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/init.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <linux/sysdev.h>
+#include <asm/ptrace.h>
+#include <asm/signal.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/prom.h>
+#include <asm/sections.h>
+#include <asm/hardirq.h>
+#include <asm/machdep.h>
+
+#include <asm/tsi108.h>
+#include <asm/tsi108_irq.h>
+
+#undef DEBUG
+#undef DBG_TSI108_INTERRUPT
+
+#ifdef DEBUG
+#define DBG(fmt...) do { printk(fmt); } while(0) #else #define
+DBG(fmt...) do { } while(0) #endif
+
+extern u32 get_vir_csrbase(void);
+extern u32 tsi108_read_reg(u32 reg_offset); extern void
+tsi108_write_reg(u32 reg_offset, u32 val);
+
+/*
+ * Low level utility functions
+ */
+
+static void tsi108_pci_int_mask(u_int irq) {
+ u_int irp_cfg;
+ int int_line = (irq - IRQ_PCI_INTAD_BASE);
+
+ irp_cfg = tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL);
+ mb();
+ irp_cfg |= (1 << int_line); /* INTx_DIR = output */
+ irp_cfg &= ~(3 << (8 + (int_line * 2))); /* INTx_TYPE = unused */
+ tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL, irp_cfg);
+ mb();
+ irp_cfg = tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL);
+}
+
+static void tsi108_pci_int_unmask(u_int irq) {
+ u_int irp_cfg;
+ int int_line = (irq - IRQ_PCI_INTAD_BASE);
+
+ irp_cfg = tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL);
+ mb();
+ irp_cfg &= ~(1 << int_line);
+ irp_cfg |= (3 << (8 + (int_line * 2)));
+ tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL, irp_cfg);
+ mb();
+}
+
+static void init_pci_source(void)
+{
+ tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL,
+ 0x0000ff00);
+ tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_ENABLE,
+ TSI108_PCI_IRP_ENABLE_P_INT);
+ mb();
+}
+
+static inline int get_pci_source(void)
+{
+ u_int temp = 0;
+ int irq = -1;
+ int i;
+ u_int pci_irp_stat;
+ static int mask = 0;
+
+ /* Read PCI/X block interrupt status register */
+ pci_irp_stat = tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_STAT);
+ mb();
+
+ if (pci_irp_stat & TSI108_PCI_IRP_STAT_P_INT) {
+ /* Process Interrupt from PCI bus INTA# - INTD# lines */
+ temp =
+ tsi108_read_reg(TSI108_PCI_OFFSET +
+ TSI108_PCI_IRP_INTAD) & 0xf;
+ mb();
+ for (i = 0; i < 4; i++, mask++) {
+ if (temp & (1 << mask % 4)) {
+ irq = IRQ_PCI_INTA + mask % 4;
+ mask++;
+ break;
+ }
+ }
+
+ /* Disable interrupts from PCI block */
+ temp = tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_ENABLE);
+ tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_ENABLE,
+ temp & ~TSI108_PCI_IRP_ENABLE_P_INT);
+ mb();
+ (void)tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_ENABLE);
+ mb();
+ }
+#ifdef DBG_TSI108_INTERRUPT
+ else {
+ printk("TSI108_PIC: error in TSI108_PCI_IRP_STAT\n");
+ pci_irp_stat =
+ tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_STAT);
+ temp =
+ tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_INTAD);
+ mb();
+ printk(">> stat=0x%08x intad=0x%08x ", pci_irp_stat, temp);
+ temp =
+ tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL);
+ mb();
+ printk("cfg_ctl=0x%08x ", temp);
+ temp =
+ tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_ENABLE);
+ mb();
+ printk("irp_enable=0x%08x\n", temp);
+ }
+#endif /* DBG_TSI108_INTERRUPT */
+
+ return irq;
+}
+
+
+/*
+ * Linux descriptor level callbacks
+ */
+
+static void tsi108_pci_irq_enable(u_int irq) {
+ tsi108_pci_int_unmask(irq);
+}
+
+static void tsi108_pci_irq_disable(u_int irq) {
+ tsi108_pci_int_mask(irq);
+}
+
+static void tsi108_pci_irq_ack(u_int irq) {
+ tsi108_pci_int_mask(irq);
+}
+
+static void tsi108_pci_irq_end(u_int irq) {
+ tsi108_pci_int_unmask(irq);
+
+ /* Enable interrupts from PCI block */
+ tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_ENABLE,
+ tsi108_read_reg(TSI108_PCI_OFFSET +
+ TSI108_PCI_IRP_ENABLE) |
+ TSI108_PCI_IRP_ENABLE_P_INT);
+ mb();
+}
+
+/*
+ * Interrupt controller descriptor for cascaded PCI interrupt controller.
+ */
+
+struct hw_interrupt_type tsi108_pci_irq = {
+ .typename = "tsi108_PCI_int",
+ .enable = tsi108_pci_irq_enable,
+ .disable = tsi108_pci_irq_disable,
+ .ack = tsi108_pci_irq_ack,
+ .end = tsi108_pci_irq_end,
+};
+
+/*
+ * Exported functions
+ */
+
+/*
+ * The Tsi108 PCI interrupts initialization routine.
+ *
+ * The INTA# - INTD# interrupts on the PCI bus are reported by the PCI
+block
+ * to the MPIC using single interrupt source (IRQ_TSI108_PCI).
+Therefore the
+ * PCI block has to be treated as a cascaded interrupt controller
+connected
+ * to the MPIC.
+ */
+
+void __init tsi108_pci_int_init(void)
+{
+ u_int i;
+
+ DBG("Tsi108_pci_int_init: initializing PCI interrupts\n");
+
+ for (i = 0; i < NUM_PCI_IRQS; i++) {
+ irq_desc[i + IRQ_PCI_INTAD_BASE].handler = &tsi108_pci_irq;
+ irq_desc[i + IRQ_PCI_INTAD_BASE].status |= IRQ_LEVEL;
+ }
+
+ init_pci_source();
+}
+
+int tsi108_irq_cascade(struct pt_regs *regs, void *unused) {
+ return get_pci_source();
+}
^ permalink raw reply related
* Re: [PATCH] Compile failure fix for ppc on 2.6.17-rc4-mm3 (2nd attempt)
From: Paul Mackerras @ 2006-06-09 9:36 UTC (permalink / raw)
To: Mel Gorman; +Cc: Andrew Morton, linuxppc-dev, vgoyal, linux-kernel
In-Reply-To: <20060529190515.GA17608@skynet.ie>
Mel Gorman writes:
> + res->end = -(-res->end & ~(unsigned long)mask); \
> + res->end += mask; \
I think this is equivalent to
res->end = (res->end + mask) | mask;
and I have to say the latter seems more understandable to me (and
doesn't need a cast) ...
Regards,
Paul.
^ permalink raw reply
* Re: [PATCH] Provide mechanism for editing builtin command-line in zImage binary.
From: Paul Mackerras @ 2006-06-09 9:47 UTC (permalink / raw)
To: mostrows; +Cc: linuxppc-dev
In-Reply-To: <11489544631499-git-send-email-mostrows@watson.ibm.com>
Michal Ostrowski writes:
> -BOOTCFLAGS += -I$(obj) -I$(srctree)/$(obj)
> +BOOTCFLAGS += -I$(obj) -I$(srctree)/$(obj) -I$(O)/include -I$(O)/include2\
> + -D__KERNEL__
I don't like this; we are trying to keep the boot wrapper separate,
not make it more dependent on the rest of the kernel.
> +#include <linux/autoconf.h>
> +#include <asm/setup.h>
We don't really need COMMAND_LINE_SIZE here - nothing says the command
line from the firmware or the boot wrapper *has* to be the same size
as the kernel's command-line buffer.
> +static char builtin_cmdline[COMMAND_LINE_SIZE]
> + __attribute__((section("__builtin_cmdline"))) = CONFIG_CMDLINE;
> +#endif
If CONFIG_CMDLINE is set, then the kernel image *already* has the
default in it, and we don't need another copy here. Just make your
buffer here some fixed, known size and uninitialized (i.e. all
zeroes). Do the setprop if the /chosen/bootargs is empty and your
buffer has been edited to be non-null.
Paul.
^ permalink raw reply
* Re: pmf_register_irq_client gives sleep with locks held warning
From: Johannes Berg @ 2006-06-08 18:58 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: Andrew Morton, linuxppc-dev list
In-Reply-To: <1149123574.15446.15.camel@localhost.localdomain>
On Thu, 2006-06-01 at 10:59 +1000, Benjamin Herrenschmidt wrote:
> This fixes request_irq() potentially called from atomic context.
> [...]
Sorry, almost forgot about this.
I don't think your patch is right, it seems to me that now
pmf_unregister_irq_client races against pmf_do_irq: what happens when an
interrupt comes in right in the middle of the list_del()?
It might actually not do any harm due to the way list_del() and
pmf_do_irq() work and the fact that client->handler() must still be
prepared to be called... But I'd rather make it explicit.
By the way, what do I do when like this I change a patch? Do I rely on
your Signed-off-by and simply put mine instead (like I did now)?
Anyway, here's a changed patch that illustrates my point. I've tested it
and it works and as expected fixes the problem :)
---
This fixes request_irq() being called with interrupts disabled in the
powermac platform function code when registering the first irq client
for a given platform function.
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Johannes Berg <johannes@sipsolutions.net>
--- a/arch/powerpc/platforms/powermac/pfunc_core.c
+++ b/arch/powerpc/platforms/powermac/pfunc_core.c
@@ -11,6 +11,7 @@ #include <linux/delay.h>
#include <linux/kernel.h>
#include <linux/spinlock.h>
#include <linux/module.h>
+#include <linux/mutex.h>
#include <asm/semaphore.h>
#include <asm/prom.h>
@@ -546,6 +547,7 @@ struct pmf_device {
static LIST_HEAD(pmf_devices);
static spinlock_t pmf_lock = SPIN_LOCK_UNLOCKED;
+static DEFINE_MUTEX(pmf_irq_mutex);
static void pmf_release_device(struct kref *kref)
{
@@ -864,16 +866,25 @@ int pmf_register_irq_client(struct devic
spin_lock_irqsave(&pmf_lock, flags);
func = __pmf_find_function(target, name, PMF_FLAGS_INT_GEN);
- if (func == NULL) {
- spin_unlock_irqrestore(&pmf_lock, flags);
+ if (func)
+ func = pmf_get_function(func);
+ spin_unlock_irqrestore(&pmf_lock, flags);
+ if (func == NULL)
return -ENODEV;
- }
+
+ /* guard against manipulations of list */
+ mutex_lock(&pmf_irq_mutex);
if (list_empty(&func->irq_clients))
func->dev->handlers->irq_enable(func);
+
+ /* guard against pmf_do_irq while changing list */
+ spin_lock_irqsave(&pmf_lock, flags);
list_add(&client->link, &func->irq_clients);
- client->func = func;
spin_unlock_irqrestore(&pmf_lock, flags);
+ client->func = func;
+ mutex_unlock(&pmf_irq_mutex);
+
return 0;
}
EXPORT_SYMBOL_GPL(pmf_register_irq_client);
@@ -885,12 +896,19 @@ void pmf_unregister_irq_client(struct pm
BUG_ON(func == NULL);
- spin_lock_irqsave(&pmf_lock, flags);
+ /* guard against manipulations of list */
+ mutex_lock(&pmf_irq_mutex);
client->func = NULL;
+
+ /* guard against pmf_do_irq while changing list */
+ spin_lock_irqsave(&pmf_lock, flags);
list_del(&client->link);
+ spin_unlock_irqrestore(&pmf_lock, flags);
+
if (list_empty(&func->irq_clients))
func->dev->handlers->irq_disable(func);
- spin_unlock_irqrestore(&pmf_lock, flags);
+ mutex_unlock(&pmf_irq_mutex);
+ pmf_put_function(func);
}
EXPORT_SYMBOL_GPL(pmf_unregister_irq_client);
^ permalink raw reply
* Re: [PATCH] convert powermac ide blink to new led infrastructure
From: Johannes Berg @ 2006-06-09 11:47 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev list
In-Reply-To: <1149726524.23790.5.camel@localhost.localdomain>
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On Thu, 2006-06-08 at 10:28 +1000, Benjamin Herrenschmidt wrote:
> No objection, but a question: how do you bind the led to the hard disk
> by default ? some userland stuff ? can't be automatic at boot by
> default ?
The way it usually works is via sysfs. Automatic at boot could be
default by assigning a default name somewhere IIRC, but since I don't
use the LED I optimised for that case ;)
I'd say having a script that *enables* it at boot is probably cleaner
than having one that *disables* it, and having a Kconfig option just for
the default seems overkill.
johannes
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^ permalink raw reply
* Re: [PATCH] convert powermac ide blink to new led infrastructure
From: Anton Blanchard @ 2006-06-09 11:56 UTC (permalink / raw)
To: Johannes Berg; +Cc: linuxppc-dev list
In-Reply-To: <1149853629.3864.9.camel@johannes.berg>
> The way it usually works is via sysfs. Automatic at boot could be
> default by assigning a default name somewhere IIRC, but since I don't
> use the LED I optimised for that case ;)
> I'd say having a script that *enables* it at boot is probably cleaner
> than having one that *disables* it, and having a Kconfig option just for
> the default seems overkill.
On the other hand, Ive come to expect it on my laptop :)
Anton
^ permalink raw reply
* Re: [PATCH] convert powermac ide blink to new led infrastructure
From: Johannes Berg @ 2006-06-09 12:01 UTC (permalink / raw)
To: Anton Blanchard; +Cc: linuxppc-dev list
In-Reply-To: <20060609115608.GE23891@krispykreme>
[-- Attachment #1: Type: text/plain, Size: 441 bytes --]
On Fri, 2006-06-09 at 21:56 +1000, Anton Blanchard wrote:
> On the other hand, Ive come to expect it on my laptop :)
With my patch, just put
echo -n ide-disk > /sys/class/leds/pmu-front-led/trigger
into some startup script then :)
Do we really want the old Kconfig option in there selecting the new led
option, the ide-disk trigger and modifying the code to make this the
default trigger for the LED? I mean...
johannes
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^ permalink raw reply
* Re: [Alsa-devel] [RFC 03/12] snd-aoa: add aoa core
From: Johannes Berg @ 2006-06-09 12:10 UTC (permalink / raw)
To: Takashi Iwai; +Cc: linuxppc-dev, alsa-devel, netstar
In-Reply-To: <s5hk67s4ywh.wl%tiwai@suse.de>
[-- Attachment #1: Type: text/plain, Size: 1135 bytes --]
On Wed, 2006-06-07 at 20:13 +0200, Takashi Iwai wrote:
> At Wed, 07 Jun 2006 15:09:12 +0200,
> Johannes Berg wrote:
> >
> > --- /dev/null
> > +++ b/sound/aoa/core/snd-aoa-gpio-pmf.c
> (snip)
> > +void pmf_handle_notify_irq(void *data)
> > +{
>
> Missing static.
Added, thanks.
> > --- /dev/null
> > +++ b/sound/aoa/core/snd-aoa-gpio-feature.c
> (snip)
> > +static struct device_node *get_gpio(
> > + char *name, char *altname, int *gpioptr, int *gpioactiveptr)
>
> Unconventional style.
Heh ok, fixed.
> > +irqreturn_t ftr_handle_notify_irq(int xx, void *data, struct pt_regs *regs)
> > +{
>
> Missing static.
Added.
> > +static int ftr_set_notify(struct gpio_runtime *rt,
> > + enum notify_type type,
> > + notify_func_t notify,
> > + void *data)
> (snip)
> > + if (old && !notify) {
> > + free_irq(irq, notif);
> > + }
> > + if (!old && notify) {
> > + request_irq(irq, ftr_handle_notify_irq, 0, name, notif);
> > + }
>
> Remove braces.
Right.
> Any error check from request_irq()?
Ah, I figured it didn't matter, but it indeed does. Fixed.
johannes
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^ permalink raw reply
* Re: [Alsa-devel] [RFC 11/12] snd-aoa: add Kconfig and Makefile
From: Johannes Berg @ 2006-06-09 12:10 UTC (permalink / raw)
To: Takashi Iwai; +Cc: linuxppc-dev, alsa-devel, netstar
In-Reply-To: <s5hejy04x7k.wl%tiwai@suse.de>
[-- Attachment #1: Type: text/plain, Size: 299 bytes --]
On Wed, 2006-06-07 at 20:50 +0200, Takashi Iwai wrote:
> Let's remove EXPERIMENTAL. Or keep snd-powermac untouched.
Good point. It's been working for lots of people and I'm almost done
verifying that it works for all that snd-powermac handled, so I'll
remove the EXPERIMENTAL.
johannes
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^ permalink raw reply
* Re: [Alsa-devel] [RFC 05/12] snd-aoa: add i2sbus
From: Johannes Berg @ 2006-06-09 12:13 UTC (permalink / raw)
To: Takashi Iwai; +Cc: linuxppc-dev, alsa-devel, netstar
In-Reply-To: <s5hfyig4xhm.wl%tiwai@suse.de>
[-- Attachment #1: Type: text/plain, Size: 613 bytes --]
On Wed, 2006-06-07 at 20:44 +0200, Takashi Iwai wrote:
> > + if (I2S_CLOCK_SPEED_18MHz % (rate * mclk) == 0) {
> > + if (!i2s_sf_mclkdiv(I2S_CLOCK_SPEED_18MHz / rate / mclk, out)) {
>
> I'd use "I2S_CLOCK_SPEED_18MHZ / (rate * mclk)"
Yeah, I guess that's clearer then if the multiplication is there twice.
> release_resource() doesn't kfree the record returned from
> request_mem_region().
Hah, ouch. I'll go through and fix them all.
> ALSA has a helper function
> release_and_free_resource() that also does NULL check and kfree:
Why's that helper in alsa of all things? :)
johannes
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^ permalink raw reply
* Re: [Alsa-devel] [RFC 00/12] snd-aoa: add snd-aoa
From: Johannes Berg @ 2006-06-09 12:22 UTC (permalink / raw)
To: Takashi Iwai; +Cc: linuxppc-dev, alsa-devel, netstar
In-Reply-To: <s5hhd2w4yh2.wl%tiwai@suse.de>
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On Wed, 2006-06-07 at 20:22 +0200, Takashi Iwai wrote:
> Yes, I'll apply the patch to snd-powermac separately.
Ok.
> Both for snd-aoa addition and for dropping layout-id support from
> snd-powermac, please.
Will do. How do you want the code? Should I post the final version as
mails again or just provide two download URLs with two patches and
appropriate changelogs?
johannes
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^ permalink raw reply
* Re: [Alsa-devel] [RFC 05/12] snd-aoa: add i2sbus
From: Takashi Iwai @ 2006-06-09 12:23 UTC (permalink / raw)
To: Johannes Berg; +Cc: linuxppc-dev, alsa-devel, netstar
In-Reply-To: <1149855230.3864.19.camel@johannes.berg>
At Fri, 09 Jun 2006 14:13:49 +0200,
Johannes Berg wrote:
>
> > ALSA has a helper function
> > release_and_free_resource() that also does NULL check and kfree:
>
> Why's that helper in alsa of all things? :)
Yeah it's worth for core stuff indeed.
Takashi
^ permalink raw reply
* Re: [Alsa-devel] [RFC 00/12] snd-aoa: add snd-aoa
From: Takashi Iwai @ 2006-06-09 12:34 UTC (permalink / raw)
To: Johannes Berg; +Cc: linuxppc-dev, alsa-devel, netstar
In-Reply-To: <1149855749.3864.21.camel@johannes.berg>
At Fri, 09 Jun 2006 14:22:29 +0200,
Johannes Berg wrote:
>
> On Wed, 2006-06-07 at 20:22 +0200, Takashi Iwai wrote:
>
> > Yes, I'll apply the patch to snd-powermac separately.
>
> Ok.
>
>
> > Both for snd-aoa addition and for dropping layout-id support from
> > snd-powermac, please.
>
> Will do. How do you want the code? Should I post the final version as
> mails again or just provide two download URLs with two patches and
> appropriate changelogs?
I don't mind both ways any more at this stage. It's up to you.
thanks,
Takashi
^ permalink raw reply
* Re: [PATCH 0/5] Sizing zones and holes in an architecture independent manner V7
From: Mel Gorman @ 2006-06-09 12:57 UTC (permalink / raw)
To: Andi Kleen
Cc: Andrew Morton, davej, tony.luck, linux-mm, linux-kernel,
bob.picco, linuxppc-dev
In-Reply-To: <200606071720.22242.ak@suse.de>
On (07/06/06 17:20), Andi Kleen didst pronounce:
>
> > Ok, while true, I'm not sure how it affects performance. The only "real"
> > value affected by present_pages is the number of patches that are
> > allocated in batches to the per-cpu allocator.
>
> It affects the low/high water marks in the VM zone balancer.
>
> Especially for the 16MB DMA zone it can make a difference if you
> account 4MB kernel in there or not.
>
Ok, the following patch will account for memmap usage on all
architectures. Optionally, a set_dma_reserve() may be called to account
for pages in ZONE_DMA that will never be usable. In this patch, only
x86_64 uses it.
After this patch is applied, the zone->present_pages figures are very
similar before and after arch-independent zone-sizing and the watermarks
are the same.
diff -rup -X /usr/src/patchset-0.6/bin//dontdiff linux-2.6.17-rc6-mm1-105-ia64_use_init_nodes/arch/x86_64/mm/init.c linux-2.6.17-rc6-mm1-106-account_kernel_mmap/arch/x86_64/mm/init.c
--- linux-2.6.17-rc6-mm1-105-ia64_use_init_nodes/arch/x86_64/mm/init.c 2006-06-08 13:45:07.000000000 +0100
+++ linux-2.6.17-rc6-mm1-106-account_kernel_mmap/arch/x86_64/mm/init.c 2006-06-09 09:18:55.000000000 +0100
@@ -660,8 +660,10 @@ void __init reserve_bootmem_generic(unsi
#else
reserve_bootmem(phys, len);
#endif
- if (phys+len <= MAX_DMA_PFN*PAGE_SIZE)
+ if (phys+len <= MAX_DMA_PFN*PAGE_SIZE) {
dma_reserve += len / PAGE_SIZE;
+ set_dma_reserve(dma_reserve);
+ }
}
int kern_addr_valid(unsigned long addr)
diff -rup -X /usr/src/patchset-0.6/bin//dontdiff linux-2.6.17-rc6-mm1-105-ia64_use_init_nodes/include/linux/mm.h linux-2.6.17-rc6-mm1-106-account_kernel_mmap/include/linux/mm.h
--- linux-2.6.17-rc6-mm1-105-ia64_use_init_nodes/include/linux/mm.h 2006-06-08 13:42:53.000000000 +0100
+++ linux-2.6.17-rc6-mm1-106-account_kernel_mmap/include/linux/mm.h 2006-06-09 09:18:55.000000000 +0100
@@ -969,6 +969,7 @@ extern void free_bootmem_with_active_reg
unsigned long max_low_pfn);
extern void sparse_memory_present_with_active_regions(int nid);
#endif /* CONFIG_ARCH_POPULATES_NODE_MAP */
+extern void set_dma_reserve(unsigned long new_dma_reserve);
extern void memmap_init_zone(unsigned long, int, unsigned long, unsigned long);
extern void setup_per_zone_pages_min(void);
extern void mem_init(void);
diff -rup -X /usr/src/patchset-0.6/bin//dontdiff linux-2.6.17-rc6-mm1-105-ia64_use_init_nodes/mm/page_alloc.c linux-2.6.17-rc6-mm1-106-account_kernel_mmap/mm/page_alloc.c
--- linux-2.6.17-rc6-mm1-105-ia64_use_init_nodes/mm/page_alloc.c 2006-06-08 13:42:53.000000000 +0100
+++ linux-2.6.17-rc6-mm1-106-account_kernel_mmap/mm/page_alloc.c 2006-06-09 09:18:55.000000000 +0100
@@ -88,6 +88,7 @@ int min_free_kbytes = 1024;
unsigned long __meminitdata nr_kernel_pages;
unsigned long __meminitdata nr_all_pages;
+unsigned long __initdata dma_reserve;
#ifdef CONFIG_ARCH_POPULATES_NODE_MAP
/*
@@ -2459,6 +2460,20 @@ unsigned long __init zone_absent_pages_i
arch_zone_lowest_possible_pfn[zone_type],
arch_zone_highest_possible_pfn[zone_type]);
}
+
+/* Return the zone index a PFN is in */
+int memmap_zone_idx(struct page *lmem_map)
+{
+ int i;
+ unsigned long phys_addr = virt_to_phys(lmem_map);
+ unsigned long pfn = phys_addr >> PAGE_SHIFT;
+
+ for (i = 0; i < MAX_NR_ZONES; i++)
+ if (pfn < arch_zone_highest_possible_pfn[i])
+ break;
+
+ return i;
+}
#else
static inline unsigned long zone_spanned_pages_in_node(int nid,
unsigned long zone_type,
@@ -2476,6 +2491,11 @@ static inline unsigned long zone_absent_
return zholes_size[zone_type];
}
+
+static inline int memmap_zone_idx(struct page *lmem_map)
+{
+ return MAX_NR_ZONES;
+}
#endif
static void __init calculate_node_totalpages(struct pglist_data *pgdat,
@@ -2499,6 +2519,58 @@ static void __init calculate_node_totalp
realtotalpages);
}
+#ifdef CONFIG_FLAT_NODE_MEM_MAP
+/* Account for mem_map for CONFIG_FLAT_NODE_MEM_MAP */
+unsigned long __meminit account_memmap(struct pglist_data *pgdat,
+ int zone_index)
+{
+ unsigned long pages = 0;
+ if (zone_index == memmap_zone_idx(pgdat->node_mem_map)) {
+ pages = pgdat->node_spanned_pages;
+ pages = (pages * sizeof(struct page)) >> PAGE_SHIFT;
+ printk(KERN_DEBUG "%lu pages used for memmap\n", pages);
+ }
+ return pages;
+}
+#else
+/* Account for mem_map for CONFIG_SPARSEMEM */
+unsigned long account_memmap(struct pglist_data *pgdat, int zone_index)
+{
+ unsigned long pages = 0;
+ unsigned long memmap_pfn;
+ struct page *memmap_addr;
+ int pnum;
+ unsigned long pgdat_startpfn, pgdat_endpfn;
+ struct mem_section *section;
+
+ pgdat_startpfn = pgdat->node_start_pfn;
+ pgdat_endpfn = pgdat_startpfn + pgdat->node_spanned_pages;
+
+ /* Go through valid sections looking for memmap */
+ for (pnum = 0; pnum < NR_MEM_SECTIONS; pnum++) {
+ if (!valid_section_nr(pnum))
+ continue;
+
+ section = __nr_to_section(pnum);
+ if (!section_has_mem_map(section))
+ continue;
+
+ memmap_addr = __section_mem_map_addr(section);
+ memmap_pfn = (unsigned long)memmap_addr >> PAGE_SHIFT;
+
+ if (memmap_pfn < pgdat_startpfn || memmap_pfn >= pgdat_endpfn)
+ continue;
+
+ if (zone_index == memmap_zone_idx(memmap_addr))
+ pages += (PAGES_PER_SECTION * sizeof(struct page));
+ }
+
+ pages >>= PAGE_SHIFT;
+ printk(KERN_DEBUG "%lu pages used for SPARSE memmap\n", pages);
+ return pages;
+}
+#endif
+
/*
* Set up the zone data structures:
* - mark all pages reserved
@@ -2525,6 +2597,15 @@ static void __meminit free_area_init_cor
size = zone_spanned_pages_in_node(nid, j, zones_size);
realsize = size - zone_absent_pages_in_node(nid, j,
zholes_size);
+
+ realsize -= account_memmap(pgdat, j);
+ /* Account for reserved DMA pages */
+ if (j == ZONE_DMA && realsize > dma_reserve) {
+ realsize -= dma_reserve;
+ printk(KERN_DEBUG "%lu pages DMA reserved\n",
+ dma_reserve);
+ }
+
if (j < ZONE_HIGHMEM)
nr_kernel_pages += realsize;
nr_all_pages += realsize;
@@ -2849,6 +2930,21 @@ void __init free_area_init_nodes(unsigne
}
#endif /* CONFIG_ARCH_POPULATES_NODE_MAP */
+/**
+ * set_dma_reserve - Account the specified number of pages reserved in ZONE_DMA
+ * @new_dma_reserve - The number of pages to mark reserved
+ *
+ * The per-cpu batchsize and zone watermarks are determined by present_pages.
+ * In the DMA zone, a significant percentage may be consumed by kernel image
+ * and other unfreeable allocations which can skew the watermarks badly. This
+ * function may optionally be used to account for unfreeable pages in
+ * ZONE_DMA. The effect will be lower watermarks and smaller per-cpu batchsize
+ */
+void __init set_dma_reserve(unsigned long new_dma_reserve)
+{
+ dma_reserve = new_dma_reserve;
+}
+
#ifndef CONFIG_NEED_MULTIPLE_NODES
static bootmem_data_t contig_bootmem_data;
struct pglist_data contig_page_data = { .bdata = &contig_bootmem_data };
--
--
Mel Gorman
Part-time Phd Student Linux Technology Center
University of Limerick IBM Dublin Software Lab
^ permalink raw reply
* [PATCH] Editable kernel command-line in zImage binary.
From: mostrows @ 2006-06-09 13:06 UTC (permalink / raw)
To: linuxppc-dev, paulus
In-Reply-To: <17545.17329.227226.926906@cargo.ozlabs.ibm.com>
zImage will set /chosen/bootargs (if it is otherwise empty) with the
contents of a buffer in the section "__builtin_cmdline". This permits
tools to edit zImage binaries to set the command-line eventually
processed by vmlinux.
--
Signed-off-by: Michal Ostrowski <mostrows@watson.ibm.com>
---
arch/powerpc/boot/main.c | 27 +++++++++++++++++++++++++++
arch/powerpc/boot/prom.h | 7 +++++++
2 files changed, 34 insertions(+), 0 deletions(-)
40bea6ace95796a1575437d6dfdbef671012ffc1
diff --git a/arch/powerpc/boot/main.c b/arch/powerpc/boot/main.c
index 816446f..c65a7ba 100644
--- a/arch/powerpc/boot/main.c
+++ b/arch/powerpc/boot/main.c
@@ -33,6 +33,14 @@ extern char _vmlinux_end[];
extern char _initrd_start[];
extern char _initrd_end[];
+/* A buffer that may be edited by tools operating on a zImage binary so as to
+ * edit the command line passed to vmlinux (by setting /chosen/bootargs).
+ * The buffer is put in it's own section so that tools may locate it easier.
+ */
+static char builtin_cmdline[512]
+ __attribute__((section("__builtin_cmdline")));
+
+
struct addr_range {
unsigned long addr;
unsigned long size;
@@ -204,6 +212,23 @@ static int is_elf32(void *hdr)
return 1;
}
+void export_cmdline(void* chosen_handle)
+{
+ int len;
+ char cmdline[2] = { 0, 0 };
+
+ if (builtin_cmdline[0] == 0)
+ return;
+
+ len = getprop(chosen_handle, "bootargs", cmdline, sizeof(cmdline));
+ if (len > 0 && cmdline[0] != 0)
+ return;
+
+ setprop(chosen_handle, "bootargs", builtin_cmdline,
+ strlen(builtin_cmdline) + 1);
+}
+
+
void start(unsigned long a1, unsigned long a2, void *promptr, void *sp)
{
int len;
@@ -289,6 +314,8 @@ void start(unsigned long a1, unsigned lo
memmove((void *)vmlinux.addr,(void *)vmlinuz.addr,vmlinuz.size);
}
+ export_cmdline(chosen_handle);
+
/* Skip over the ELF header */
#ifdef DEBUG
printf("... skipping 0x%lx bytes of ELF header\n\r",
diff --git a/arch/powerpc/boot/prom.h b/arch/powerpc/boot/prom.h
index 3e2ddd4..a57b184 100644
--- a/arch/powerpc/boot/prom.h
+++ b/arch/powerpc/boot/prom.h
@@ -31,4 +31,11 @@ static inline int getprop(void *phandle,
return call_prom("getprop", 4, 1, phandle, name, buf, buflen);
}
+
+static inline int setprop(void *phandle, const char *name,
+ void *buf, int buflen)
+{
+ return call_prom("setprop", 4, 1, phandle, name, buf, buflen);
+}
+
#endif /* _PPC_BOOT_PROM_H_ */
--
1.1.4.g0b63-dirty
^ permalink raw reply related
* Re: [PATCH 10/10 v2] Document I2C_MPC option for 86xx too.
From: Jon Loeliger @ 2006-06-09 13:50 UTC (permalink / raw)
To: Jean Delvare; +Cc: linuxppc-dev
In-Reply-To: <20060609093737.f66d5a41.khali@linux-fr.org>
So, like, the other day Jean Delvare mumbled:
> Hi Jon,
>
> Please add a paragraph explaining what the patch does. It will be used
> as the git commit message.
Hi Jean,
There is a one-line commit message that will come from
the Subject: line. If I add a paragraph, it will be
"Document I2C_MPC option for 86xx too."
which will end up as a duplicate line in the commit message.
Thanks,
jdl
^ permalink raw reply
* Re: a problem of kernel-module version mismatch.
From: Ming Liu @ 2006-06-09 14:02 UTC (permalink / raw)
To: arnd.bergmann; +Cc: linuxppc-embedded
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset=gb2312; format=flowed, Size: 4006 bytes --]
Dear Arnd,
Thanks a lot for your help. Now I have solved the problem of version
mismatch. The reason is I haven't include the sentence of "#define MODULE".
However the problem of unresolved symbol XIo_In32 and XIo_Out32 still
exists. I will try to solve it following your suggestion. If any question,
I will ask you again. Thanks a lot for your help.
Regards
Ming
From: Arnd Bergmann <arnd.bergmann@de.ibm.com>
To: "Ming Liu" <eemingliu@hotmail.com>
CC: linuxppc-embedded@ozlabs.org
Subject: Re: a problem of kernel-module version mismatch.
Date: Thu, 8 Jun 2006 17:25:37 +0200
On Thursday 08 June 2006 15:52, Ming Liu wrote:
> >The easiest way is usually to put the driver in your source tree
> >and compile everything together. That also makes it easier to
> >distribute the complete source tree to your users.
>
> Sorry that I am a novice in Linux. I don't know how can I put the
driver in
> my source tree and compile everything together. It looks like that
there is
> no option in the menuconfig to choose a specially customed
peripheral.
So I
> think I only can include the customed peripheral as a module. Could
you
> please say in a detail on how to do that?
The most simple way would be to put it into linux/drivers/misc and add it
to the Makefile in there.
> > > insmod: unresolved symbol XIo_In32
> > > insmod: unresolved symbol XIO_Out32
> >
> >that looks like part of your module is missing. Try to find where
thses
> >functions are defined in there and why that isn't compiled.
>
> It's very strange because I have checked the source. In the header file
of
> xio.h, there are the following sentences,
>
> /************************** Function Prototypes
> ******************************/
>
> /* The following functions allow the software to be transportable
across
> ? processors which may use memory mapped I/O or I/O which is mapped
into a
> ? seperate address space such as X86. The functions are better
suited
for
> ? debugging and are therefore the default implementation. Macros can
> instead
> ? be used if USE_IO_MACROS is defined.
> ?/
> #ifndef USE_IO_MACROS
The comment tells you that you either need to implement these functions
youself or #define USE_IO_MACROS in the code before this.
> /* Functions */
> Xuint8 XIo_In8(XIo_Address InAddress);
> Xuint16 XIo_In16(XIo_Address InAddress);
> Xuint32 XIo_In32(XIo_Address InAddress);
>
> void XIo_Out8(XIo_Address OutAddress, Xuint8 Value);
> void XIo_Out16(XIo_Address OutAddress, Xuint16 Value);
> void XIo_Out32(XIo_Address OutAddress, Xuint32 Value);
>
> #else
>
> /* The following macros allow optimized I/O operations for memory
mapped
> I/O
> ? Note that the SYNCHRONIZE_IO may be moved by the compiler during
> ? optimization.
> ?/
>
> #define XIo_In8(InputPtr) ?*(volatile Xuint8 ?)(InputPtr));
> SYNCHRONIZE_IO;
> #define XIo_In16(InputPtr) (*(volatile Xuint16 *)(InputPtr));
> SYNCHRONIZE_IO;
> #define XIo_In32(InputPtr) (*(volatile Xuint32 *)(InputPtr));
> SYNCHRONIZE_IO;
>
> #define XIo_Out8(OutputPtr, Value) \
> ??{ (*(volatile Xuint8 ?)(OutputPtr) = Value); SYNCHRONIZE_IO; }
> #define XIo_Out16(OutputPtr, Value) \
> ??{ (*(volatile Xuint16 *)(OutputPtr) = Value); SYNCHRONIZE_IO; }
> #define XIo_Out32(OutputPtr, Value) \
> ??{ (*(volatile Xuint32 *)(OutputPtr) = Value); SYNCHRONIZE_IO; }
>
> #endif
These macros are probably broken on powerpc.
>
> I think these are the defination of XIo_In32 and XIo_Out32. Also,
during
> the compilation, there is no error to complain that "XIo_In32 or
XIo_Out32
> undeclared".
>
I would suggest you remove that part of the header file completely, and
replace it with:
#define XIo_In32(p) in_le32(x)
#define XIO_Out32(p,v) out_le32(p, v)
Arnd <><
_________________________________________________________________
ÓëÁª»úµÄÅóÓѽøÐн»Á÷£¬ÇëʹÓà MSN Messenger: http://messenger.msn.com/cn
^ permalink raw reply
* Re: a problem of kernel-module version mismatch.
From: Ming Liu @ 2006-06-09 14:07 UTC (permalink / raw)
To: arnd.bergmann; +Cc: linuxppc-embedded
In-Reply-To: <200606081725.37621.arnd.bergmann@de.ibm.com>
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset=gb2312; format=flowed, Size: 4608 bytes --]
Dear Arnd,
I have tried to replace the original definations for XIn_In32 and XIn_Out32
by what you suggested:
#define XIo_In32(p) in_le32(x) (Should that be
in_le32(p) instead of x?)
#define XIO_Out32(p,v) out_le32(p, v)
The following warnings are generated:
passing arg 1 of 'in_le32' (and 'out_le32') makes pointer from integer
without a cast
Also, when I try to insmod FIFO.o, the following errors appeared:
insmod: unresolved symbol out_le32
insmod: unresolved symbol in_le32
Are in_le32 and out_le32 two functions defined by the kernel to input and
output 32-bit data? When we define XIo_In32 and XIo_Out32 as them, which is
we use out_le32 and in_le32 to input and output data, they are still not
resolvable. Any other suggestions? Thanks a lot.
Regards
Ming
>From: Arnd Bergmann <arnd.bergmann@de.ibm.com>
>To: "Ming Liu" <eemingliu@hotmail.com>
>CC: linuxppc-embedded@ozlabs.org
>Subject: Re: a problem of kernel-module version mismatch.
>Date: Thu, 8 Jun 2006 17:25:37 +0200
>
>On Thursday 08 June 2006 15:52, Ming Liu wrote:
> > >The easiest way is usually to put the driver in your source tree
> > >and compile everything together. That also makes it easier to
> > >distribute the complete source tree to your users.
> >
> > Sorry that I am a novice in Linux. I don't know how can I put the
driver in
> > my source tree and compile everything together. It looks like that
there is
> > no option in the menuconfig to choose a specially customed peripheral.
So I
> > think I only can include the customed peripheral as a module. Could you
> > please say in a detail on how to do that?
>
>The most simple way would be to put it into linux/drivers/misc and add it
>to the Makefile in there.
>
> > > > insmod: unresolved symbol XIo_In32
> > > > insmod: unresolved symbol XIO_Out32
> > >
> > >that looks like part of your module is missing. Try to find where
thses
> > >functions are defined in there and why that isn't compiled.
> >
> > It's very strange because I have checked the source. In the header file
of
> > xio.h, there are the following sentences,
> >
> > /************************** Function Prototypes
> > ******************************/
> >
> > /* The following functions allow the software to be transportable
across
> > ? processors which may use memory mapped I/O or I/O which is mapped
into a
> > ? seperate address space such as X86. The functions are better suited
for
> > ? debugging and are therefore the default implementation. Macros can
> > instead
> > ? be used if USE_IO_MACROS is defined.
> > ?/
> > #ifndef USE_IO_MACROS
>
>The comment tells you that you either need to implement these functions
>youself or #define USE_IO_MACROS in the code before this.
>
> > /* Functions */
> > Xuint8 XIo_In8(XIo_Address InAddress);
> > Xuint16 XIo_In16(XIo_Address InAddress);
> > Xuint32 XIo_In32(XIo_Address InAddress);
> >
> > void XIo_Out8(XIo_Address OutAddress, Xuint8 Value);
> > void XIo_Out16(XIo_Address OutAddress, Xuint16 Value);
> > void XIo_Out32(XIo_Address OutAddress, Xuint32 Value);
> >
> > #else
> >
> > /* The following macros allow optimized I/O operations for memory
mapped
> > I/O
> > ? Note that the SYNCHRONIZE_IO may be moved by the compiler during
> > ? optimization.
> > ?/
> >
> > #define XIo_In8(InputPtr) ?*(volatile Xuint8 ?)(InputPtr));
> > SYNCHRONIZE_IO;
> > #define XIo_In16(InputPtr) (*(volatile Xuint16 *)(InputPtr));
> > SYNCHRONIZE_IO;
> > #define XIo_In32(InputPtr) (*(volatile Xuint32 *)(InputPtr));
> > SYNCHRONIZE_IO;
> >
> > #define XIo_Out8(OutputPtr, Value) \
> > ??{ (*(volatile Xuint8 ?)(OutputPtr) = Value); SYNCHRONIZE_IO; }
> > #define XIo_Out16(OutputPtr, Value) \
> > ??{ (*(volatile Xuint16 *)(OutputPtr) = Value); SYNCHRONIZE_IO; }
> > #define XIo_Out32(OutputPtr, Value) \
> > ??{ (*(volatile Xuint32 *)(OutputPtr) = Value); SYNCHRONIZE_IO; }
> >
> > #endif
>
>These macros are probably broken on powerpc.
>
> >
> > I think these are the defination of XIo_In32 and XIo_Out32. Also,
during
> > the compilation, there is no error to complain that "XIo_In32 or
XIo_Out32
> > undeclared".
> >
>
>I would suggest you remove that part of the header file completely, and
>replace it with:
>
>#define XIo_In32(p) in_le32(x)
>#define XIO_Out32(p,v) out_le32(p, v)
>
> Arnd <><
>_______________________________________________
>Linuxppc-embedded mailing list
>Linuxppc-embedded@ozlabs.org
>https://ozlabs.org/mailman/listinfo/linuxppc-embedded
_________________________________________________________________
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^ permalink raw reply
* Re: does Gianfar Ethernet Controller Version 1.1 support MARVELL 88E1111?
From: Guo Jaffe @ 2006-06-09 14:56 UTC (permalink / raw)
To: afleming, DaveLiu; +Cc: Linuxppc-embedded
In-Reply-To: <15BDF877-21B2-40BD-A5F6-9CD83E5BB2CE@freescale.com>
>From: Andy Fleming <afleming@freescale.com>
>To: Guo Jaffe <jianfei616@hotmail.com>
>CC: Linuxppc-embedded@ozlabs.org
>Subject: Re: does Gianfar Ethernet Controller Version 1.1 support MARVELL
88E1111?
>Date: Thu, 8 Jun 2006 14:25:44 -0500
>
>
>On Jun 8, 2006, at 12:51, Guo Jaffe wrote:
>
>>Hi Andy,
>>
>>Thank you for your information. So the driver is not the issue, but
>> better to upgraded.
>>
>>I will check the board once more. The PHY doesn't work because the
>>8bit bus between MAC and PHY is locked(TX_EN and RX_DV all disabled
>> from the scope's view) and also you can't see any signals exist
>>at the Magnetic side(nor LED signals). It seems that only MDC/MDIO
>>and CLOCK reference pin works. The PHY's ID must be read from
>>MDC/MDIO interface and Clocks are right showed on the scope.
>
>
>But what error are you getting? What are the symptoms of your
>problem? The GMII interface (the 8-bit bus) is inconsequential to
>PHY configuration and management. Only the MDC/MDIO bus is used.
>Therefore the PHY id should be quite readable. What version of
>Linux are you using? Please describe what the kernel prints out
>when you boot, and when you try to bring up the interface (assuming
>you don't do that at boot).
>
>Andy
^ permalink raw reply
* RE: does Gianfar Ethernet Controller Version 1.1 support MARVELL 88E1111?
From: Guo Jaffe @ 2006-06-09 15:43 UTC (permalink / raw)
To: DaveLiu, afleming; +Cc: Linuxppc-embedded
In-Reply-To: <9FCDBA58F226D911B202000BDBAD4673026FD945@zch01exm40.ap.freescale.net>
Hi Dave,
The PHY ID I read is MARVELL 88E1101(1410cc2)
Today I took the MPC 8540 off the board, and checked the two GMII phy chips
alone. I manually pulled up the phys's RST pins when the cable was in
position. But the link LED still can't light up. So it turned out not the
driver's problem.
The hardware configuration of 88E1111 is GMII to copper, Auto-Neg,
advertise all capabilities, prefer Master.
The PHY's power is correct and clean. And for interface between TESC and
PHY I think even TESC power is set for 3.3V environment it still can work
with the 88e1111 whose VDD is 2.5V. Because the datasheet of 88e1111 says
that input pins are 3.3V tolerant. Am I right?
regards,
Jaffe
----------------------------------------------------------------------------
>As you said, the MDIO bus looks like well. If the PHY address it is right,
>You can read the PHY ID from PHY. What is the PHY ID you read?
>
>Please check the hardware status
>
>1) 8540 hardware reset configuration for GMII interface;
>Make sure it is GMII interface.
>
>2) MARVELL 88E1111 configuration and GMII interface connection.
>You can reference the 8540 ref board.
>
>3)TSEC and PHY power
>
>4)The 125M reference clock---GTX_CLK125, This looks
>well as you said.
>
>5)The GTX_CLK for GMII transmit clock, and TX_CLK for MII transmit clock.
>What speed ethernet does the TSEC connect to? 1000Mbps or 100Mbps?
>
>6) The RX_CLK for receive clock.
>
>7)Of cause, need check the RX_DV and TX_EN to see if have some traffic.
>
>-Dave
^ permalink raw reply
* Re: [PATCH 2/10 v2] Add the MPC8641 HPCN platform files.
From: Jon Loeliger @ 2006-06-09 15:55 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev@ozlabs.org
In-Reply-To: <1149826559.12687.41.camel@localhost.localdomain>
So, like, the other day Benjamin Herrenschmidt mumbled:
> On Thu, 2006-06-08 at 16:57 -0500, Jon Loeliger wrote:
>
> > +void
> > +mpc86xx_restart(char *cmd)
> > +{
> > + void __iomem *rstcr;
> > +
> > + local_irq_disable();
> > +
> > + /* Assert reset request to Reset Control Register */
> > + rstcr = ioremap(get_immrbase() + MPC86XX_RSTCR_OFFSET, 0x100);
> > + out_be32(rstcr, 0x2);
> > +
> > + /* not reached */
> > +}
>
> ioremap with irq disabled isn't great.... You should do the ioremap
> once at boot.
OK. Would this be acceptable instead:
mpc86xx_restart(char *cmd)
{
void __iomem *rstcr;
rstcr = ioremap(get_immrbase() + MPC86XX_RSTCR_OFFSET, 0x100);
local_irq_disable();
/* Assert reset request to Reset Control Register */
out_be32(rstcr, 0x2);
/* not reached */
}
> Overall, that file is too small :) Move those into your setup.c and make
> those static...
Will do.
> [SMP code snipped]
>
> This file could/should be called *_smp.c and not need #ifdef's :)
OK.
> Most of the values above should probably be retreived from the
> device-tree.
I'll see what I can remove. Some of the PCI/PCI-e bits
_will_ be device tree derived, but just not quite there yet...
It's just not going to be a perfect first patch; there
will have to be incremental development in that direction.
> As I suggested before, the 2 above should be static in your setup file.
Right.
> > +extern int __init add_bridge(struct device_node *dev);
>
> Aren't we exposing that already via some header ?
Perhaps. I'll look around for it.
> > +extern void __init setup_indirect_pex_nomap(struct pci_controller* hose,
> > + void __iomem * cfg_addr,
> > + void __iomem * cfg_data);
> > +
> > +extern struct smp_ops_t smp_8641_ops;
>
> See my comments about the PCI stuff with the PCI patch.
and...
> All of the above should of course come from the device-tree. 2.6.18 will
> have the support for having interrupt routing from it without having
> nodes for all devices. I'll post it to the list in a week or so, I'm
> coding right now :)
Right. We're not quite entirely able to convert it
all to device tree yet. Working on it still...
> > + phys_addr_t OpenPIC_PAddr;
> > +
> > + /* Determine the Physical Address of the OpenPIC regs */
> > + OpenPIC_PAddr = get_immrbase() + MPC86xx_OPENPIC_OFFSET;
>
> Do you really _need_ studly caps ? I know we did that before but you
> don't have to copy ugly stuff :)
Uh, sorry. No problem.
> In general, you -need- a device node for the interrupt controller. It
> will be made mandatory by the new code.
I know. There is a fully defined node for that in my
device tree already.
> You'll have to provide proper
> interrupt informations in your device-tree (it's easy, really).
It's there.
> If you get that right, it will be very easy to "just work" with my new
> code.
I'll send that to the list too for reference
just to make sure we are in sync here.
> > + /* Alloc mpic structure and per isu has 16 INT entries. */
> > + mpic1 = mpic_alloc(OpenPIC_PAddr,
> > + MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
> > + 16, MPC86xx_OPENPIC_IRQ_OFFSET, 0, 250,
> > + mpc86xx_hpcn_openpic_initsenses,
> > + sizeof(mpc86xx_hpcn_openpic_initsenses),
> > + " MPIC ");
> > + BUG_ON(mpic1 == NULL);
> > +
> > + /* 48 Internal Interrupts */
> > + mpic_assign_isu(mpic1, 0, OpenPIC_PAddr + 0x10200);
> > + mpic_assign_isu(mpic1, 1, OpenPIC_PAddr + 0x10400);
> > + mpic_assign_isu(mpic1, 2, OpenPIC_PAddr + 0x10600);
>
> I haven't looked in detail at your memory map, but do you need separate
> ISUs ? They seem to be quite close together to me... Also, you should
> invent properties in the mpic node for some of those things, like
> big-endian (like apple does) indicating it's a big endian openpic,
> etc... If you manage to get close enough to spec & common usage, you
> might not even need your own init function at all in the future.
OK. We'll work in that direction, but incrementally.
> > + /* 16 External interrupts */
> > + mpic_assign_isu(mpic1, 3, OpenPIC_PAddr + 0x10000);
>
> That looks like you used ISUs in order to "re-order" them... why ?
Heck if I know. We'll have to ask around some here... :-)
> > +#ifdef CONFIG_PEX
> > + mpic_setup_cascade(MPC86xx_IRQ_EXT9, i8259_irq_cascade, NULL);
> > + i8259_init(0, I8259_OFFSET);
> > +#endif
> > +}
>
> Cascade handling is changing with my genirq port. It will be easy to
> adapt though. Same comments howveer, you should have a device-tree node
> for the 8259 (under an ISA bridge, those shall really be in the
> device-tree). In general, on-board bridges should be in the device-tree,
> only slots or standardly routed child PCI devices need not.
Can you send me an example?
>
> All of the above shall be in the device-tree.
Yes, eventually. But not yet... We're working on
this with other folks like Kumar, and Monta Vista,
and other folks.
> > +static void __init
> > +mpc86xx_hpcn_setup_arch(void)
> > +{
> > + struct device_node *np;
> > +
> > +#ifdef CONFIG_SMP
> > + phys_addr_t mcm_paddr;
> > + void *mcm_vaddr = NULL;
> > + unsigned long vaddr;
> > +#endif
> > +
> > + if (ppc_md.progress)
> > + ppc_md.progress("mpc86xx_hpcn_setup_arch()", 0);
> > +
> > + np = of_find_node_by_type(NULL, "cpu");
> > + if (np != 0) {
> > + unsigned int *fp;
> > +
> > + fp = (int *)get_property(np, "clock-frequency", NULL);
> > + if (fp != 0)
> > + loops_per_jiffy = *fp / HZ;
> > + else
> > + loops_per_jiffy = 50000000 / HZ;
> > + of_node_put(np);
> > + }
>
> The above looks dodgy... powerpc uses the timebase frequency for delays
> anyway, lpj will be initialized by the bogomips code, and should but
> unused mostly nowadays anyway.
Uh, you want I should rip it out, boss? :-)
> > +#ifdef CONFIG_PEX
> > + for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;)
> > + add_bridge(np);
> > +
> > + ppc_md.pci_swizzle = common_swizzle;
> > + ppc_md.pci_map_irq = mpc86xx_map_irq;
> > + ppc_md.pci_exclude_device = mpc86xx_exclude_device;
> > +#endif
>
> I'm not sure I like this CONFIG_PEX (in general). Just use CONFIG_PCI
> for now all over the place. PCI-E has it's own binding that we don't
> quite respect yet but will do and all of that will be in the
> device-tree. However, as far as the kernel is concerned, this is all
> under CONFIG_PCI.
But I think we are looking for independent PCI/PCI-E options
to be independently configurable still...?
> > +#ifdef CONFIG_SMP
> > + /* Release Core 1 in boot holdoff */
> > + mcm_paddr = get_immrbase() + MPC86xx_MCM_OFFSET;
> > + mcm_vaddr = ioremap(mcm_paddr, MPC86xx_MCM_SIZE);
> > +
> > + vaddr = (unsigned long)mcm_vaddr + MCM_PORT_CONFIG_OFFSET;
> > + out_be32((volatile unsigned *)vaddr, CPU_ALL_RELEASED);
> > + smp_ops = &smp_8641_ops;
> > +#endif
> > +}
>
> Instead of ifdef's, just do a mpc86xx_smp_init() and put it somewhere
> with the other SMP things in the file that contains them (and remove the
> #ifdef's there too, just only build the file if CONFIG_SMP is set).
OK, I catch your drift, but if the file is missing and
there is a hard call to mpc86xx_smp_init() here, how is
that resolved? Is mpc86xx_smp_init #defined empty when
compiled non-SMP then? Like in the header file:
#ifndef CONFIG_SMP
#define mpc86xx_smp_init()
#endif
> > +void
> > +mpc86xx_hpcn_show_cpuinfo(struct seq_file *m)
> > +{
> > + uint pvid, svid, phid1;
> > + uint memsize = total_memory;
> > +
> > + pvid = mfspr(SPRN_PVR);
> > + svid = mfspr(SPRN_SVR);
> >
> > + seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n");
> > + seq_printf(m, "Machine\t\t: MPC86xx HPCN Board\n");
> > + seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
> > + seq_printf(m, "SVR\t\t: 0x%x\n", svid);
>
> The PVR is probably a duplicate and the SVR should be added to per-cpu
> info instead.
I confess, I am not sure what you mean here. Could you
clarify this a bit for me, or point to an example perhaps?
Thanks for you feedback!
jdl
^ permalink raw reply
* Re: [PATCH 4/10 v2] Guard L3CR references with CPU_FTR_L3CR.
From: Jon Loeliger @ 2006-06-09 16:00 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev@ozlabs.org
In-Reply-To: <1149826679.12687.44.camel@localhost.localdomain>
So, like, the other day Benjamin Herrenschmidt mumbled:
> On Thu, 2006-06-08 at 16:58 -0500, Jon Loeliger wrote:
> > Signed-off-by: Jon Loeliger <jdl@freescale.com>
>
> Beware about this one... the CPU setup code might run before the feature
> fixup in the future...
> ...
> or go read the feature bit directly in the structure
> rather than relying on the fixup mecanism.
OK.
> you should probably do a separate setup function for your core
Truth be told, this is a pretty generic fix for other
parts as well. If I recall correctly, 7447, 7448, 7448A and 7450
as well as the new 8641 now.
But I can certainly introduce a new setup function here
if you think that is the right thing to do. No problem.
Thanks,
jdl
> > --- a/arch/powerpc/kernel/cpu_setup_6xx.S
> > +++ b/arch/powerpc/kernel/cpu_setup_6xx.S
> > +BEGIN_FTR_SECTION
> > mfspr r11,SPRN_L3CR
> > andis. r11,r11,L3CR_L3E@h
> > beq 1f
> > +END_FTR_SECTION_IFSET(CPU_FTR_L3CR)
> > lwz r6,CPU_SPEC_FEATURES(r5)
> > andi. r0,r6,CPU_FTR_L3_DISABLE_NAP
> > beq 1f
^ permalink raw reply
* Re: [PATCH 5/10 v2] Add 8641 CPU and i8259 Setup
From: Jon Loeliger @ 2006-06-09 16:05 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev@ozlabs.org
In-Reply-To: <1149826989.12687.50.camel@localhost.localdomain>
So, like, the other day Benjamin Herrenschmidt mumbled:
>
> [A bunch of SMP issues.]
>
> The above is wrong, it prevents using the same kernel image on another
> platform.
> Same comment above... #ifdef is bad. You are entering from 0x100 with
> address translation not disabled ?
> > + bl clear_bats
> > bl load_up_mmu
>
> Why do you need to call clear_bats here ? load_up_mmu should load BATs.
> If it doesn't handle the high BATs, then fix it :)
> > +#ifdef CONFIG_I8259_LEVEL_TRIGGER
> > + outb(0xfa, 0x4d0); /* level triggered */
> > + outb(0xde, 0x4d1);
> > +#endif
>
> Another change that breaks multiplatform... Can you explain precisely
> what you are trying to acheive here ? If necessary, we can add an
> argument to i8259_init. Or you could do the above in your platform
> code ... though I agree it would be a bit ugly :)
OK. I don't have direct answers in hand for some of
these questions and issues. I'll get with original
authors and see what we can do clean this up!
Thanks!
jdl
^ permalink raw reply
* Re: [PATCH 3/10 v2] Add MPC8641 HPCN PCI and PCI-Express files.
From: Jon Loeliger @ 2006-06-09 16:09 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev@ozlabs.org
In-Reply-To: <1149827596.12687.53.camel@localhost.localdomain>
So, like, the other day Benjamin Herrenschmidt mumbled:
> On Thu, 2006-06-08 at 16:57 -0500, Jon Loeliger wrote:
> > Signed-off-by: Xianghua Xiao <x.xiao@freescale.com>
> > Signed-off-by: Wei Zhang <Wei.Zhang@freescale.com>
> > Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
> > Signed-off-by: Jon Loeliger <jdl@freescale.com>
>
> There are various things in this code that duplicate names used by other
> platforms and thus makes the board unsuitable for use in a common
> kernel. That needs to be fixed. Try avoiding too generic names. Also,
> PCI Express shall be named "pcie" and not "pex" :)
>
> I don't have time at the moment to go too deep in the details here.
>
> Ben.
I will also prefix some routines with mpc86xx_ to avoid
the generic names problems. But I'm not sure which other
platforms you expect this one kernel image to run on.
Specifically, this pcie code is very similar to the 8548
family, but not exactly the same.
My understanding is that we are shooting for a single 86xx
family kernel image here, with this 8641 HPCN platform being
the first such port.
I will s/pex/pcie/g and rename files accordingly.
jdl
^ permalink raw reply
* Re: a problem of kernel-module version mismatch.
From: Arnd Bergmann @ 2006-06-09 14:18 UTC (permalink / raw)
To: Ming Liu; +Cc: linuxppc-embedded
In-Reply-To: <BAY110-F337711EB19C0B1D8417B18B2880@phx.gbl>
On Friday 09 June 2006 16:07, Ming Liu wrote:
> Are in_le32 and out_le32 two functions defined by the kernel to input and
> output 32-bit data? When we define XIo_In32 and XIo_Out32 as them, which is
> we use out_le32 and in_le32 to input and output data, they are still not
> resolvable. Any other suggestions? Thanks a lot.
They should be defined in include/asm-powerpc/io.h, include <asm/io.h>
to get the definition.
If your kernel is too old, they may not be there however, so you need
to use readl/writel or inl/outl, also defined in that file.
Arnd <><
^ permalink raw reply
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