* snd-aoa issues & fixes
From: Benjamin Herrenschmidt @ 2006-06-28 8:01 UTC (permalink / raw)
To: Johannes Berg; +Cc: linuxppc-dev list
So I've been trying to fix snd-aoa for the G5s and found a few issues...
I think I got most of it right, however I don't have any sound... I hear
"clacs" when I toggle the mutes pretty much as expected and I see
interrupts counting when playing sound but there is no actual sound in
the speaker. I've verified that snd-powermac works on the same machine
(PowerMac7,3 with tas codec). I've been toying with all the controls
available in alsamixer, it didn't help. Sounds to me that there is
nothing going out of the tas... maybe some mixer control that is not
quite right, duno
- Redefinition of various FCR related bits in i2s-control. I've fixed
that in the patch and used existing definitions. However, we still have
a problem that we don't properly lock with pmac_feature for access to
these. We need to either expose new feature calls now that we are
upstream or expose the pmac_feature spinlock
- I noticed you don't call pmac_feature and don't set bits in FCR3
etc... (enabling the 18Mhz clock for example). Is that normal ? You
don't use that clock ? That's the only difference in FCR content that
I've been able to spot between snd-powermac and snd-aoa but hacking it
doesn't seem to make much difference.
- The fabric stuff needs a bit of cleanup... You seem to be fond of
defining lotsa struct's :) Even when they don't contain much :) Triggers
another problem below
- I've had a crash with built-in snd-aoa at boot... The problem is that
when built-in, there is no enforced ordering between module_init() calls
except for link order... What happens here is that soundbus is last in
the Makefile, thus we try to register soundbus devices before we
register the bus type. I fixes that in the patch both by putting
soundbus first in the Make
- If i2sbus is loaded after the codec and fabric, the codec fails to
initialize. I haven't tried to debug that one
- The dmesg output could use some cleanup :)
- The driver is trying to access non existing codecs on the i2c bus,
that's a pretty bad idea.
I think we need to change the codec probe phase dramatically:
1 - codec drivers register the i2c thingy as normal
2 - i2c kicks in, they do the current device-node and/or i2c bus name
check and register
themselves with the core. They do not try to touch the hardware at
this point
3 - fabric kicks in (or was already there). It checks the list of
codecs registered when
loaded and gets notified of new ones added. If codec matches the
layout, then codec
init is called
4 - codec init called by fabric. That is where we try to tap the
hardware. Might fail in
which case the fabric doesn't try to use the codec
(That is, there is a global list of registered codecs at the core, and a
list of "active" codecs in the fabric or bus, whatever...)
Here's my current patch:
Index: linux-snd-aoa/sound/aoa/soundbus/i2sbus/i2sbus-core.c
===================================================================
--- linux-snd-aoa.orig/sound/aoa/soundbus/i2sbus/i2sbus-core.c 2006-06-26 12:29:38.000000000 +1000
+++ linux-snd-aoa/sound/aoa/soundbus/i2sbus/i2sbus-core.c 2006-06-28 16:10:27.000000000 +1000
@@ -7,13 +7,16 @@
*/
#include <linux/module.h>
-#include <asm/macio.h>
-#include <asm/dbdma.h>
#include <linux/pci.h>
#include <linux/interrupt.h>
+#include <linux/dma-mapping.h>
+
#include <sound/driver.h>
#include <sound/core.h>
-#include <linux/dma-mapping.h>
+
+#include <asm/macio.h>
+#include <asm/dbdma.h>
+
#include "../soundbus.h"
#include "i2sbus.h"
@@ -24,6 +27,12 @@ MODULE_DESCRIPTION("Apple Soundbus: I2S
* string that macio puts into the relevant device */
MODULE_ALIAS("of:Ni2sTi2sC");
+static int force;
+module_param(force, int, 0444);
+MODULE_PARM_DESC(force, "Force loading i2sbus even when"
+ " no layout-id property is present");
+
+
static struct of_device_id i2sbus_match[] = {
{ .name = "i2s" },
{ }
@@ -73,7 +82,7 @@ static void i2sbus_release_dev(struct de
if (i2sdev->intfregs) iounmap(i2sdev->intfregs);
if (i2sdev->out.dbdma) iounmap(i2sdev->out.dbdma);
if (i2sdev->in.dbdma) iounmap(i2sdev->in.dbdma);
- for (i=0;i<3;i++)
+ for (i = aoa_resource_i2smmio; i <= aoa_resource_rxdbdma; i++)
if (i2sdev->allocated_resource[i])
release_and_free_resource(i2sdev->allocated_resource[i]);
free_dbdma_descriptor_ring(i2sdev, &i2sdev->out.dbdma_ring);
@@ -101,10 +110,49 @@ static irqreturn_t i2sbus_bus_intr(int i
return IRQ_HANDLED;
}
-static int force;
-module_param(force, int, 0444);
-MODULE_PARM_DESC(force, "Force loading i2sbus even when"
- " no layout-id property is present");
+/*
+ * XXX FIXME: We have to test the layout_id's here to get the proper way
+ * of mapping in various registers, thanks to bugs in Apple device-trees.
+ * Ideally, that should be handled by the layout fabric but doing so would
+ * require a little bit of shuffling around
+ */
+static int i2sbus_get_and_fixup_rsrc(struct device_node *np, int index,
+ int layout, struct resource *res)
+{
+ struct device_node *parent;
+ int pindex, rc = -ENXIO;
+ u32 *reg;
+
+ /* Machines with layout 76 and 36 (K2 based) have a weird device
+ * tree what we need to special case.
+ * Normal machines just fetch the resource from the i2s-X node.
+ * Darwin further divides normal machines into old and new layouts
+ * with a subtely different code path but that doesn't seem necessary
+ * in practice, they just bloated it. In addition, even on our K2
+ * case the i2s-modem node, if we ever want to handle it, uses the
+ * normal layout
+ */
+ if (layout != 76 && layout != 36)
+ return of_address_to_resource(np, index, res);
+
+ parent = of_get_parent(np);
+ pindex = (index == aoa_resource_i2smmio) ? 0 : 1;
+ rc = of_address_to_resource(parent, pindex, res);
+ if (rc)
+ goto bail;
+ reg = (u32 *)get_property(np, "reg", NULL);
+ if (reg == NULL) {
+ rc = -ENXIO;
+ goto bail;
+ }
+ res->start += reg[index * 2];
+ res->end = res->start + reg[index * 2 + 1] - 1;
+ printk("i2sbus rsrc %d -> %lx..%lx\n", index,
+ res->start, res->end);
+ bail:
+ of_node_put(parent);
+ return rc;
+}
/* FIXME: look at device node refcounting */
static int i2sbus_add_dev(struct macio_dev *macio,
@@ -113,7 +161,8 @@ static int i2sbus_add_dev(struct macio_d
{
struct i2sbus_dev *dev;
struct device_node *child = NULL, *sound = NULL;
- int i;
+ struct resource *r;
+ int i, layout = 0;
static const char *rnames[] = { "i2sbus: %s (control)",
"i2sbus: %s (tx)",
"i2sbus: %s (rx)" };
@@ -147,8 +196,9 @@ static int i2sbus_add_dev(struct macio_d
u32 *layout_id;
layout_id = (u32*) get_property(sound, "layout-id", NULL);
if (layout_id) {
+ layout = *layout_id;
snprintf(dev->sound.modalias, 32,
- "sound-layout-%d", *layout_id);
+ "sound-layout-%d", layout);
force = 1;
}
}
@@ -180,20 +230,28 @@ static int i2sbus_add_dev(struct macio_d
for (i=0;i<3;i++) {
dev->interrupts[i] = -1;
- snprintf(dev->rnames[i], sizeof(dev->rnames[i]), rnames[i], np->name);
+ snprintf(dev->rnames[i], sizeof(dev->rnames[i]), rnames[i],
+ np->name);
}
for (i=0;i<3;i++) {
- if (request_irq(np->intrs[i].line, ints[i], 0, dev->rnames[i], dev))
+ if (request_irq(np->intrs[i].line, ints[i], 0, dev->rnames[i],
+ dev))
goto err;
dev->interrupts[i] = np->intrs[i].line;
}
- for (i=0;i<3;i++) {
- if (of_address_to_resource(np, i, &dev->resources[i]))
+ /* Resource handling is problematic as some device-trees contain
+ * useless crap (ugh ugh ugh). We work around that here by calling
+ * specific functions for calculating the appropriate resources.
+ */
+ for (i = aoa_resource_i2smmio; i <= aoa_resource_rxdbdma; i++) {
+ if (i2sbus_get_and_fixup_rsrc(np,i,layout,&dev->resources[i]))
goto err;
- /* if only we could use our resource dev->resources[i]...
+
+ /* If only we could use our resource dev->resources[i]...
* but request_resource doesn't know about parents and
- * contained resources... */
+ * contained resources...
+ */
dev->allocated_resource[i] =
request_mem_region(dev->resources[i].start,
dev->resources[i].end -
@@ -205,12 +263,12 @@ static int i2sbus_add_dev(struct macio_d
}
}
/* should do sanity checking here about length of them */
- dev->intfregs = ioremap(dev->resources[0].start,
- dev->resources[0].end-dev->resources[0].start+1);
- dev->out.dbdma = ioremap(dev->resources[1].start,
- dev->resources[1].end-dev->resources[1].start+1);
- dev->in.dbdma = ioremap(dev->resources[2].start,
- dev->resources[2].end-dev->resources[2].start+1);
+ r = &dev->resources[aoa_resource_i2smmio];
+ dev->intfregs = ioremap(r->start, r->end - r->start + 1);
+ r = &dev->resources[aoa_resource_txdbdma];
+ dev->out.dbdma = ioremap(r->start, r->end - r->start + 1);
+ r = &dev->resources[aoa_resource_rxdbdma];
+ dev->in.dbdma = ioremap(r->start, r->end - r->start + 1);
if (!dev->intfregs || !dev->out.dbdma || !dev->in.dbdma)
goto err;
Index: linux-snd-aoa/sound/aoa/soundbus/i2sbus/i2sbus.h
===================================================================
--- linux-snd-aoa.orig/sound/aoa/soundbus/i2sbus/i2sbus.h 2006-06-26 12:29:38.000000000 +1000
+++ linux-snd-aoa/sound/aoa/soundbus/i2sbus/i2sbus.h 2006-06-28 15:16:40.000000000 +1000
@@ -7,20 +7,22 @@
*/
#ifndef __I2SBUS_H
#define __I2SBUS_H
-#include <asm/dbdma.h>
#include <linux/interrupt.h>
-#include <sound/pcm.h>
#include <linux/spinlock.h>
#include <linux/mutex.h>
+
+#include <sound/pcm.h>
+
#include <asm/prom.h>
+#include <asm/pmac_feature.h>
+#include <asm/dbdma.h>
+
#include "i2sbus-interface.h"
-#include "i2sbus-control.h"
#include "../soundbus.h"
struct i2sbus_control {
- volatile struct i2s_control_regs __iomem *controlregs;
- struct resource rsrc;
struct list_head list;
+ struct macio_chip *macio;
};
#define MAX_DBDMA_COMMANDS 32
@@ -45,6 +47,12 @@ struct pcm_info {
volatile struct dbdma_regs __iomem *dbdma;
};
+enum {
+ aoa_resource_i2smmio = 0,
+ aoa_resource_txdbdma,
+ aoa_resource_rxdbdma,
+};
+
struct i2sbus_dev {
struct soundbus_dev sound;
struct macio_dev *macio;
Index: linux-snd-aoa/sound/aoa/soundbus/i2sbus/i2sbus-control.c
===================================================================
--- linux-snd-aoa.orig/sound/aoa/soundbus/i2sbus/i2sbus-control.c 2006-06-26 12:29:38.000000000 +1000
+++ linux-snd-aoa/sound/aoa/soundbus/i2sbus/i2sbus-control.c 2006-06-28 16:09:44.000000000 +1000
@@ -6,12 +6,16 @@
* GPL v2, can be found in COPYING.
*/
-#include <asm/io.h>
+#include <linux/kernel.h>
#include <linux/delay.h>
+
+#include <asm/io.h>
#include <asm/prom.h>
#include <asm/macio.h>
#include <asm/pmac_feature.h>
#include <asm/pmac_pfunc.h>
+#include <asm/keylargo.h>
+
#include "i2sbus.h"
int i2sbus_control_init(struct macio_dev* dev, struct i2sbus_control **c)
@@ -22,26 +26,12 @@ int i2sbus_control_init(struct macio_dev
INIT_LIST_HEAD(&(*c)->list);
- if (of_address_to_resource(dev->ofdev.node, 0, &(*c)->rsrc))
- goto err;
- /* we really should be using feature calls instead of mapping
- * these registers. It's safe for now since no one else is
- * touching them... */
- (*c)->controlregs = ioremap((*c)->rsrc.start,
- sizeof(struct i2s_control_regs));
- if (!(*c)->controlregs)
- goto err;
-
+ (*c)->macio = dev->bus->chip;
return 0;
- err:
- kfree(*c);
- *c = NULL;
- return -ENODEV;
}
void i2sbus_control_destroy(struct i2sbus_control *c)
{
- iounmap(c->controlregs);
kfree(c);
}
@@ -93,19 +83,20 @@ int i2sbus_control_enable(struct i2sbus_
struct i2sbus_dev *i2sdev)
{
struct pmf_args args = { .count = 0 };
- int cc;
+ struct macio_chip *macio = c->macio;
if (i2sdev->enable)
return pmf_call_one(i2sdev->enable, &args);
+ printk("i2sbus_control_enable fallback\n");
+ if (macio == NULL || macio->base == NULL)
+ return -ENODEV;
switch (i2sdev->bus_number) {
case 0:
- cc = in_le32(&c->controlregs->cell_control);
- out_le32(&c->controlregs->cell_control, cc | CTRL_CLOCK_INTF_0_ENABLE);
+ MACIO_BIS(KEYLARGO_FCR1, KL1_I2S0_ENABLE);
break;
case 1:
- cc = in_le32(&c->controlregs->cell_control);
- out_le32(&c->controlregs->cell_control, cc | CTRL_CLOCK_INTF_1_ENABLE);
+ MACIO_BIS(KEYLARGO_FCR1, KL1_I2S1_ENABLE);
break;
default:
return -ENODEV;
@@ -118,7 +109,7 @@ int i2sbus_control_cell(struct i2sbus_co
int enable)
{
struct pmf_args args = { .count = 0 };
- int cc;
+ struct macio_chip *macio = c->macio;
switch (enable) {
case 0:
@@ -133,18 +124,22 @@ int i2sbus_control_cell(struct i2sbus_co
printk(KERN_ERR "i2sbus: INVALID CELL ENABLE VALUE\n");
return -ENODEV;
}
+
+ printk("i2sbus_control_cell fallback\n");
+ if (macio == NULL || macio->base == NULL)
+ return -ENODEV;
switch (i2sdev->bus_number) {
case 0:
- cc = in_le32(&c->controlregs->cell_control);
- cc &= ~CTRL_CLOCK_CELL_0_ENABLE;
- cc |= enable * CTRL_CLOCK_CELL_0_ENABLE;
- out_le32(&c->controlregs->cell_control, cc);
+ if (enable)
+ MACIO_BIS(KEYLARGO_FCR1, KL1_I2S0_CELL_ENABLE);
+ else
+ MACIO_BIC(KEYLARGO_FCR1, KL1_I2S0_CELL_ENABLE);
break;
case 1:
- cc = in_le32(&c->controlregs->cell_control);
- cc &= ~CTRL_CLOCK_CELL_1_ENABLE;
- cc |= enable * CTRL_CLOCK_CELL_1_ENABLE;
- out_le32(&c->controlregs->cell_control, cc);
+ if (enable)
+ MACIO_BIS(KEYLARGO_FCR1, KL1_I2S1_CELL_ENABLE);
+ else
+ MACIO_BIC(KEYLARGO_FCR1, KL1_I2S1_CELL_ENABLE);
break;
default:
return -ENODEV;
@@ -157,7 +152,7 @@ int i2sbus_control_clock(struct i2sbus_c
int enable)
{
struct pmf_args args = { .count = 0 };
- int cc;
+ struct macio_chip *macio = c->macio;
switch (enable) {
case 0:
@@ -172,18 +167,22 @@ int i2sbus_control_clock(struct i2sbus_c
printk(KERN_ERR "i2sbus: INVALID CLOCK ENABLE VALUE\n");
return -ENODEV;
}
+
+ printk("i2sbus_control_clock fallback\n");
+ if (macio == NULL || macio->base == NULL)
+ return -ENODEV;
switch (i2sdev->bus_number) {
case 0:
- cc = in_le32(&c->controlregs->cell_control);
- cc &= ~CTRL_CLOCK_CLOCK_0_ENABLE;
- cc |= enable * CTRL_CLOCK_CLOCK_0_ENABLE;
- out_le32(&c->controlregs->cell_control, cc);
+ if (enable)
+ MACIO_BIS(KEYLARGO_FCR1, KL1_I2S0_CLK_ENABLE_BIT);
+ else
+ MACIO_BIC(KEYLARGO_FCR1, KL1_I2S0_CLK_ENABLE_BIT);
break;
case 1:
- cc = in_le32(&c->controlregs->cell_control);
- cc &= ~CTRL_CLOCK_CLOCK_1_ENABLE;
- cc |= enable * CTRL_CLOCK_CLOCK_1_ENABLE;
- out_le32(&c->controlregs->cell_control, cc);
+ if (enable)
+ MACIO_BIS(KEYLARGO_FCR1, KL1_I2S1_CLK_ENABLE_BIT);
+ else
+ MACIO_BIC(KEYLARGO_FCR1, KL1_I2S1_CLK_ENABLE_BIT);
break;
default:
return -ENODEV;
Index: linux-snd-aoa/sound/aoa/soundbus/i2sbus/i2sbus-control.h
===================================================================
--- linux-snd-aoa.orig/sound/aoa/soundbus/i2sbus/i2sbus-control.h 2006-06-26 12:29:38.000000000 +1000
+++ /dev/null 1970-01-01 00:00:00.000000000 +0000
@@ -1,37 +0,0 @@
-/*
- * i2sbus driver -- bus register definitions
- *
- * Copyright 2006 Johannes Berg <johannes@sipsolutions.net>
- *
- * GPL v2, can be found in COPYING.
- */
-#ifndef __I2SBUS_CONTROLREGS_H
-#define __I2SBUS_CONTROLREGS_H
-
-/* i2s control registers, at least what we know about them */
-
-#define __PAD(m,n) u8 __pad##m[n]
-#define _PAD(line, n) __PAD(line, n)
-#define PAD(n) _PAD(__LINE__, (n))
-struct i2s_control_regs {
- PAD(0x38);
- __le32 fcr0; /* 0x38 (unknown) */
- __le32 cell_control; /* 0x3c (fcr1) */
- __le32 fcr2; /* 0x40 (unknown) */
- __le32 fcr3; /* 0x44 (fcr3) */
- __le32 clock_control; /* 0x48 (unknown) */
- PAD(4);
- /* total size: 0x50 bytes */
-} __attribute__((__packed__));
-
-#define CTRL_CLOCK_CELL_0_ENABLE (1<<10)
-#define CTRL_CLOCK_CLOCK_0_ENABLE (1<<12)
-#define CTRL_CLOCK_SWRESET_0 (1<<11)
-#define CTRL_CLOCK_INTF_0_ENABLE (1<<13)
-
-#define CTRL_CLOCK_CELL_1_ENABLE (1<<17)
-#define CTRL_CLOCK_CLOCK_1_ENABLE (1<<18)
-#define CTRL_CLOCK_SWRESET_1 (1<<19)
-#define CTRL_CLOCK_INTF_1_ENABLE (1<<20)
-
-#endif /* __I2SBUS_CONTROLREGS_H */
Index: linux-snd-aoa/sound/aoa/Makefile
===================================================================
--- linux-snd-aoa.orig/sound/aoa/Makefile 2006-06-26 12:29:38.000000000 +1000
+++ linux-snd-aoa/sound/aoa/Makefile 2006-06-28 15:51:55.000000000 +1000
@@ -1,4 +1,4 @@
obj-$(CONFIG_SND_AOA) += core/
+obj-$(CONFIG_SND_AOA_SOUNDBUS) += soundbus/
obj-$(CONFIG_SND_AOA) += codecs/
obj-$(CONFIG_SND_AOA) += fabrics/
-obj-$(CONFIG_SND_AOA_SOUNDBUS) += soundbus/
Index: linux-snd-aoa/sound/aoa/codecs/snd-aoa-codec-onyx.c
===================================================================
--- linux-snd-aoa.orig/sound/aoa/codecs/snd-aoa-codec-onyx.c 2006-06-26 12:29:38.000000000 +1000
+++ linux-snd-aoa/sound/aoa/codecs/snd-aoa-codec-onyx.c 2006-06-28 15:37:17.000000000 +1000
@@ -1080,6 +1080,7 @@ static int onyx_i2c_detach(struct i2c_cl
struct onyx *onyx = container_of(client, struct onyx, i2c);
int err;
+ printk("onyx_i2c_detach...\n");
if ((err = i2c_detach_client(client)))
return err;
aoa_codec_unregister(&onyx->codec);
Index: linux-snd-aoa/sound/aoa/soundbus/core.c
===================================================================
--- linux-snd-aoa.orig/sound/aoa/soundbus/core.c 2006-06-26 12:29:38.000000000 +1000
+++ linux-snd-aoa/sound/aoa/soundbus/core.c 2006-06-28 16:00:35.000000000 +1000
@@ -194,16 +194,6 @@ static struct bus_type soundbus_bus_type
.dev_attrs = soundbus_dev_attrs,
};
-static int __init soundbus_init(void)
-{
- return bus_register(&soundbus_bus_type);
-}
-
-static void __exit soundbus_exit(void)
-{
- bus_unregister(&soundbus_bus_type);
-}
-
int soundbus_add_one(struct soundbus_dev *dev)
{
static int devcount;
@@ -246,5 +236,15 @@ void soundbus_unregister_driver(struct s
}
EXPORT_SYMBOL_GPL(soundbus_unregister_driver);
-module_init(soundbus_init);
+static int __init soundbus_init(void)
+{
+ return bus_register(&soundbus_bus_type);
+}
+
+static void __exit soundbus_exit(void)
+{
+ bus_unregister(&soundbus_bus_type);
+}
+
+subsys_initcall(soundbus_init);
module_exit(soundbus_exit);
^ permalink raw reply
* Re: how to get individual patches
From: Alex Zeffertt @ 2006-06-28 8:32 UTC (permalink / raw)
To: dhlii, linuxppc-embedded
In-Reply-To: <44A23488.7030606@dlasys.net>
David H. Lynch Jr. wrote:
> The bsp I am working on works with 2.6.16.21 but fails with 2.6.17.
>
> How can I find the individual patches that make up the transition
> from 2.6.16.21 to 2.6.17 ?
>
> I guess I can use interdiff to create single patch to go from
> 2.6.16.21 to 2.6.17 but I am really looking to get all the individual
> patches so I can try to isolate exactly
> what is giving me trouble.
>
For diffs of individual files between official kernel releases you can
use
http://www.linuxhq.com/kernel/
It's really good!
Alex
^ permalink raw reply
* Re: how to get individual patches
From: Grant Likely @ 2006-06-28 9:09 UTC (permalink / raw)
To: dhlii; +Cc: linuxppc-embedded
In-Reply-To: <44A23488.7030606@dlasys.net>
On 6/28/06, David H. Lynch Jr. <dhlii@dlasys.net> wrote:
>
> The bsp I am working on works with 2.6.16.21 but fails with 2.6.17.
>
> How can I find the individual patches that make up the transition
> from 2.6.16.21 to 2.6.17 ?
Unfortunately, there isn't a direct line between .16.21 and .17 which
makes it complicated. Does your bsp work with .16? If so; you can
use the 'git bisect' command to figure out exactly where the
regression occured.
If it doesn't work on .16; you can do a bisect between .16 and .16.21
to figure out what patch is missing between .16 and .17.
$ git bisect good v2.6.16
$ git bisect bad # the head of the tree
compile, test, etc.
$ git bisect good|bad # depends on whether it works or not
compile, test, etc
$ git bisect good|bad # you get the idea... repeat until it's narrowed down
$ git log # see where you are in the git tree.
Cheers,
g.
--
Grant Likely, B.Sc. P.Eng.
Secret Lab Technologies Ltd.
grant.likely@secretlab.ca
(403) 399-0195
^ permalink raw reply
* [PATCH] powerpc: Do a bit more cpu init cleanups (v3)
From: Olof Johansson @ 2006-06-28 9:30 UTC (permalink / raw)
To: paulus; +Cc: linuxppc-dev
In-Reply-To: <20060628043822.GE5130@pb15.lixom.net>
Last patch had two problems:
* cur_cpu_spec isn't available that early for processors that are
started from prom_init, so call it after release instead of before
* Fumbled with the assembly
It's a wonder that it booted on powermac (which it did).
New version below:
Cleanup CPU inits a bit more, Geoff Levand already did some earlier.
* Rename cpu_setup_power4.S to cpu_setup_ppc970.S
* Move CPU state save to cpu_setup, since cpu_setup is only ever done
on cpu 0 on 64-bit and save is never done more than once.
* Rename __restore_cpu_setup to __restore_cpu_ppc970 and add
function pointers to the cputable to use instead. Powermac always
has 970 so no need to check there. Call it a bit later so we have
cputables set up properly.
* Rename __970_cpu_preinit to __cpu_preinit_ppc970 and check PVR before
calling it instead of in it, it's too early to use cputable.
* Rename pSeries_secondary_smp_init to generic_secondary_smp_init since
everyone but powermac and iSeries use it.
Signed-off-by: Olof Johansson <olof@lixom.net>
Index: linux-2.6/arch/powerpc/kernel/Makefile
===================================================================
--- linux-2.6.orig/arch/powerpc/kernel/Makefile
+++ linux-2.6/arch/powerpc/kernel/Makefile
@@ -16,7 +16,7 @@ obj-y := semaphore.o cputable.o ptrac
obj-y += vdso32/
obj-$(CONFIG_PPC64) += setup_64.o binfmt_elf32.o sys_ppc32.o \
signal_64.o ptrace32.o \
- paca.o cpu_setup_power4.o \
+ paca.o cpu_setup_ppc970.o \
firmware.o sysfs.o
obj-$(CONFIG_PPC64) += vdso64/
obj-$(CONFIG_ALTIVEC) += vecemu.o vector.o
Index: linux-2.6/arch/powerpc/kernel/cpu_setup_power4.S
===================================================================
--- linux-2.6.orig/arch/powerpc/kernel/cpu_setup_power4.S
+++ /dev/null
@@ -1,216 +0,0 @@
-/*
- * This file contains low level CPU setup functions.
- * Copyright (C) 2003 Benjamin Herrenschmidt (benh@kernel.crashing.org)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- *
- */
-
-#include <linux/config.h>
-#include <asm/processor.h>
-#include <asm/page.h>
-#include <asm/cputable.h>
-#include <asm/ppc_asm.h>
-#include <asm/asm-offsets.h>
-#include <asm/cache.h>
-
-_GLOBAL(__970_cpu_preinit)
- /*
- * Do nothing if not running in HV mode
- */
- mfmsr r0
- rldicl. r0,r0,4,63
- beqlr
-
- /*
- * Deal only with PPC970 and PPC970FX.
- */
- mfspr r0,SPRN_PVR
- srwi r0,r0,16
- cmpwi r0,0x39
- beq 1f
- cmpwi r0,0x3c
- beq 1f
- cmpwi r0,0x44
- bnelr
-1:
-
- /* Make sure HID4:rm_ci is off before MMU is turned off, that large
- * pages are enabled with HID4:61 and clear HID5:DCBZ_size and
- * HID5:DCBZ32_ill
- */
- li r0,0
- mfspr r3,SPRN_HID4
- rldimi r3,r0,40,23 /* clear bit 23 (rm_ci) */
- rldimi r3,r0,2,61 /* clear bit 61 (lg_pg_en) */
- sync
- mtspr SPRN_HID4,r3
- isync
- sync
- mfspr r3,SPRN_HID5
- rldimi r3,r0,6,56 /* clear bits 56 & 57 (DCBZ*) */
- sync
- mtspr SPRN_HID5,r3
- isync
- sync
-
- /* Setup some basic HID1 features */
- mfspr r0,SPRN_HID1
- li r3,0x1200 /* enable i-fetch cacheability */
- sldi r3,r3,44 /* and prefetch */
- or r0,r0,r3
- mtspr SPRN_HID1,r0
- mtspr SPRN_HID1,r0
- isync
-
- /* Clear HIOR */
- li r0,0
- sync
- mtspr SPRN_HIOR,0 /* Clear interrupt prefix */
- isync
- blr
-
-_GLOBAL(__setup_cpu_ppc970)
- mfspr r0,SPRN_HID0
- li r11,5 /* clear DOZE and SLEEP */
- rldimi r0,r11,52,8 /* set NAP and DPM */
- mtspr SPRN_HID0,r0
- mfspr r0,SPRN_HID0
- mfspr r0,SPRN_HID0
- mfspr r0,SPRN_HID0
- mfspr r0,SPRN_HID0
- mfspr r0,SPRN_HID0
- mfspr r0,SPRN_HID0
- sync
- isync
- blr
-
-/* Definitions for the table use to save CPU states */
-#define CS_HID0 0
-#define CS_HID1 8
-#define CS_HID4 16
-#define CS_HID5 24
-#define CS_SIZE 32
-
- .data
- .balign L1_CACHE_BYTES,0
-cpu_state_storage:
- .space CS_SIZE
- .balign L1_CACHE_BYTES,0
- .text
-
-/* Called in normal context to backup CPU 0 state. This
- * does not include cache settings. This function is also
- * called for machine sleep. This does not include the MMU
- * setup, BATs, etc... but rather the "special" registers
- * like HID0, HID1, HID4, etc...
- */
-_GLOBAL(__save_cpu_setup)
- /* Some CR fields are volatile, we back it up all */
- mfcr r7
-
- /* Get storage ptr */
- LOAD_REG_IMMEDIATE(r5,cpu_state_storage)
-
- /* We only deal with 970 for now */
- mfspr r0,SPRN_PVR
- srwi r0,r0,16
- cmpwi r0,0x39
- beq 1f
- cmpwi r0,0x3c
- beq 1f
- cmpwi r0,0x44
- bne 2f
-
-1: /* Save HID0,1,4 and 5 */
- mfspr r3,SPRN_HID0
- std r3,CS_HID0(r5)
- mfspr r3,SPRN_HID1
- std r3,CS_HID1(r5)
- mfspr r3,SPRN_HID4
- std r3,CS_HID4(r5)
- mfspr r3,SPRN_HID5
- std r3,CS_HID5(r5)
-
-2:
- mtcr r7
- blr
-
-/* Called with no MMU context (typically MSR:IR/DR off) to
- * restore CPU state as backed up by the previous
- * function. This does not include cache setting
- */
-_GLOBAL(__restore_cpu_setup)
- /* Get storage ptr (FIXME when using anton reloc as we
- * are running with translation disabled here
- */
- LOAD_REG_IMMEDIATE(r5,cpu_state_storage)
-
- /* We only deal with 970 for now */
- mfspr r0,SPRN_PVR
- srwi r0,r0,16
- cmpwi r0,0x39
- beq 1f
- cmpwi r0,0x3c
- beq 1f
- cmpwi r0,0x44
- bnelr
-
-1: /* Before accessing memory, we make sure rm_ci is clear */
- li r0,0
- mfspr r3,SPRN_HID4
- rldimi r3,r0,40,23 /* clear bit 23 (rm_ci) */
- sync
- mtspr SPRN_HID4,r3
- isync
- sync
-
- /* Clear interrupt prefix */
- li r0,0
- sync
- mtspr SPRN_HIOR,0
- isync
-
- /* Restore HID0 */
- ld r3,CS_HID0(r5)
- sync
- isync
- mtspr SPRN_HID0,r3
- mfspr r3,SPRN_HID0
- mfspr r3,SPRN_HID0
- mfspr r3,SPRN_HID0
- mfspr r3,SPRN_HID0
- mfspr r3,SPRN_HID0
- mfspr r3,SPRN_HID0
- sync
- isync
-
- /* Restore HID1 */
- ld r3,CS_HID1(r5)
- sync
- isync
- mtspr SPRN_HID1,r3
- mtspr SPRN_HID1,r3
- sync
- isync
-
- /* Restore HID4 */
- ld r3,CS_HID4(r5)
- sync
- isync
- mtspr SPRN_HID4,r3
- sync
- isync
-
- /* Restore HID5 */
- ld r3,CS_HID5(r5)
- sync
- isync
- mtspr SPRN_HID5,r3
- sync
- isync
- blr
-
Index: linux-2.6/arch/powerpc/kernel/cpu_setup_ppc970.S
===================================================================
--- /dev/null
+++ linux-2.6/arch/powerpc/kernel/cpu_setup_ppc970.S
@@ -0,0 +1,175 @@
+/*
+ * This file contains low level CPU setup functions.
+ * Copyright (C) 2003 Benjamin Herrenschmidt (benh@kernel.crashing.org)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ *
+ */
+
+#include <linux/config.h>
+#include <asm/processor.h>
+#include <asm/page.h>
+#include <asm/cputable.h>
+#include <asm/ppc_asm.h>
+#include <asm/asm-offsets.h>
+#include <asm/cache.h>
+
+_GLOBAL(__cpu_preinit_ppc970)
+ /* Do nothing if not running in HV mode */
+ mfmsr r0
+ rldicl. r0,r0,4,63
+ beqlr
+
+ /* Make sure HID4:rm_ci is off before MMU is turned off, that large
+ * pages are enabled with HID4:61 and clear HID5:DCBZ_size and
+ * HID5:DCBZ32_ill
+ */
+ li r0,0
+ mfspr r3,SPRN_HID4
+ rldimi r3,r0,40,23 /* clear bit 23 (rm_ci) */
+ rldimi r3,r0,2,61 /* clear bit 61 (lg_pg_en) */
+ sync
+ mtspr SPRN_HID4,r3
+ isync
+ sync
+ mfspr r3,SPRN_HID5
+ rldimi r3,r0,6,56 /* clear bits 56 & 57 (DCBZ*) */
+ sync
+ mtspr SPRN_HID5,r3
+ isync
+ sync
+
+ /* Setup some basic HID1 features */
+ mfspr r0,SPRN_HID1
+ li r3,0x1200 /* enable i-fetch cacheability */
+ sldi r3,r3,44 /* and prefetch */
+ or r0,r0,r3
+ mtspr SPRN_HID1,r0
+ mtspr SPRN_HID1,r0
+ isync
+
+ /* Clear HIOR */
+ li r0,0
+ sync
+ mtspr SPRN_HIOR,0 /* Clear interrupt prefix */
+ isync
+ blr
+
+/* Definitions for the table use to save CPU states */
+#define CS_HID0 0
+#define CS_HID1 8
+#define CS_HID4 16
+#define CS_HID5 24
+#define CS_SIZE 32
+
+ .data
+ .balign L1_CACHE_BYTES,0
+cpu_state_storage:
+ .space CS_SIZE
+ .balign L1_CACHE_BYTES,0
+ .text
+
+
+_GLOBAL(__setup_cpu_ppc970)
+ /* Do nothing if not running in HV mode */
+ mfmsr r0
+ rldicl. r0,r0,4,63
+ beqlr
+
+ mfspr r0,SPRN_HID0
+ li r11,5 /* clear DOZE and SLEEP */
+ rldimi r0,r11,52,8 /* set NAP and DPM */
+ mtspr SPRN_HID0,r0
+ mfspr r0,SPRN_HID0
+ mfspr r0,SPRN_HID0
+ mfspr r0,SPRN_HID0
+ mfspr r0,SPRN_HID0
+ mfspr r0,SPRN_HID0
+ mfspr r0,SPRN_HID0
+ sync
+ isync
+
+ /* Save away cpu state */
+ LOAD_REG_IMMEDIATE(r5,cpu_state_storage)
+
+ /* Save HID0,1,4 and 5 */
+ mfspr r3,SPRN_HID0
+ std r3,CS_HID0(r5)
+ mfspr r3,SPRN_HID1
+ std r3,CS_HID1(r5)
+ mfspr r3,SPRN_HID4
+ std r3,CS_HID4(r5)
+ mfspr r3,SPRN_HID5
+ std r3,CS_HID5(r5)
+
+ blr
+
+/* Called with no MMU context (typically MSR:IR/DR off) to
+ * restore CPU state as backed up by the previous
+ * function. This does not include cache setting
+ */
+_GLOBAL(__restore_cpu_ppc970)
+ /* Do nothing if not running in HV mode */
+ mfmsr r0
+ rldicl. r0,r0,4,63
+ beqlr
+
+ LOAD_REG_IMMEDIATE(r5,cpu_state_storage)
+ /* Before accessing memory, we make sure rm_ci is clear */
+ li r0,0
+ mfspr r3,SPRN_HID4
+ rldimi r3,r0,40,23 /* clear bit 23 (rm_ci) */
+ sync
+ mtspr SPRN_HID4,r3
+ isync
+ sync
+
+ /* Clear interrupt prefix */
+ li r0,0
+ sync
+ mtspr SPRN_HIOR,0
+ isync
+
+ /* Restore HID0 */
+ ld r3,CS_HID0(r5)
+ sync
+ isync
+ mtspr SPRN_HID0,r3
+ mfspr r3,SPRN_HID0
+ mfspr r3,SPRN_HID0
+ mfspr r3,SPRN_HID0
+ mfspr r3,SPRN_HID0
+ mfspr r3,SPRN_HID0
+ mfspr r3,SPRN_HID0
+ sync
+ isync
+
+ /* Restore HID1 */
+ ld r3,CS_HID1(r5)
+ sync
+ isync
+ mtspr SPRN_HID1,r3
+ mtspr SPRN_HID1,r3
+ sync
+ isync
+
+ /* Restore HID4 */
+ ld r3,CS_HID4(r5)
+ sync
+ isync
+ mtspr SPRN_HID4,r3
+ sync
+ isync
+
+ /* Restore HID5 */
+ ld r3,CS_HID5(r5)
+ sync
+ isync
+ mtspr SPRN_HID5,r3
+ sync
+ isync
+ blr
+
Index: linux-2.6/arch/powerpc/kernel/head_64.S
===================================================================
--- linux-2.6.orig/arch/powerpc/kernel/head_64.S
+++ linux-2.6/arch/powerpc/kernel/head_64.S
@@ -152,7 +152,7 @@ _GLOBAL(__secondary_hold)
bne 100b
#if defined(CONFIG_SMP) || defined(CONFIG_KEXEC)
- LOAD_REG_IMMEDIATE(r4, .pSeries_secondary_smp_init)
+ LOAD_REG_IMMEDIATE(r4, .generic_secondary_smp_init)
mtctr r4
mr r3,r24
bctr
@@ -1473,19 +1473,17 @@ fwnmi_data_area:
. = 0x8000
/*
- * On pSeries, secondary processors spin in the following code.
+ * On pSeries and most other platforms, secondary processors spin
+ * in the following code.
* At entry, r3 = this processor's number (physical cpu id)
*/
-_GLOBAL(pSeries_secondary_smp_init)
+_GLOBAL(generic_secondary_smp_init)
mr r24,r3
/* turn on 64-bit mode */
bl .enable_64b_mode
isync
- /* Copy some CPU settings from CPU 0 */
- bl .__restore_cpu_setup
-
/* Set up a paca value for this processor. Since we have the
* physical cpu id in r24, we need to search the pacas to find
* which logical id maps to our physical one.
@@ -1511,15 +1509,28 @@ _GLOBAL(pSeries_secondary_smp_init)
/* start. */
sync
- /* Create a temp kernel stack for use before relocation is on. */
+#ifndef CONFIG_SMP
+ b 3b /* Never go on non-SMP */
+#else
+ cmpwi 0,r23,0
+ beq 3b /* Loop until told to go */
+
+ /* See if we need to call a cpu state restore handler */
+ LOAD_REG_IMMEDIATE(r23, cur_cpu_spec)
+ ld r23,0(r23)
+ ld r23,CPU_SPEC_RESTORE(r23)
+ cmpdi 0,r23,0
+ beq 4f
+ ld r23,0(r23)
+ mtctr r23
+ bctrl
+
+4: /* Create a temp kernel stack for use before relocation is on. */
ld r1,PACAEMERGSP(r13)
subi r1,r1,STACK_FRAME_OVERHEAD
- cmpwi 0,r23,0
-#ifdef CONFIG_SMP
- bne .__secondary_start
+ b .__secondary_start
#endif
- b 3b /* Loop until told to go */
#ifdef CONFIG_PPC_ISERIES
_STATIC(__start_initialization_iSeries)
@@ -1600,7 +1611,16 @@ _GLOBAL(__start_initialization_multiplat
bl .enable_64b_mode
/* Setup some critical 970 SPRs before switching MMU off */
- bl .__970_cpu_preinit
+ mfspr r0,SPRN_PVR
+ srwi r0,r0,16
+ cmpwi r0,0x39 /* 970 */
+ beq 1f
+ cmpwi r0,0x3c /* 970FX */
+ beq 1f
+ cmpwi r0,0x44 /* 970MP */
+ bne 2f
+1: bl .__cpu_preinit_ppc970
+2:
/* cpu # */
li r24,0
@@ -1771,7 +1791,7 @@ _GLOBAL(pmac_secondary_start)
isync
/* Copy some CPU settings from CPU 0 */
- bl .__restore_cpu_setup
+ bl .__restore_cpu_ppc970
/* pSeries do that early though I don't think we really need it */
mfmsr r3
@@ -1921,12 +1941,6 @@ _STATIC(start_here_multiplatform)
mr r5,r26
bl .identify_cpu
- /* Save some low level config HIDs of CPU0 to be copied to
- * other CPUs later on, or used for suspend/resume
- */
- bl .__save_cpu_setup
- sync
-
/* Do very early kernel initializations, including initial hash table,
* stab and slb setup before we turn on relocation. */
Index: linux-2.6/arch/powerpc/platforms/cell/smp.c
===================================================================
--- linux-2.6.orig/arch/powerpc/platforms/cell/smp.c
+++ linux-2.6/arch/powerpc/platforms/cell/smp.c
@@ -58,7 +58,7 @@
*/
static cpumask_t of_spin_map;
-extern void pSeries_secondary_smp_init(unsigned long);
+extern void generic_secondary_smp_init(unsigned long);
/**
* smp_startup_cpu() - start the given cpu
@@ -75,7 +75,7 @@ static inline int __devinit smp_startup_
{
int status;
unsigned long start_here = __pa((u32)*((unsigned long *)
- pSeries_secondary_smp_init));
+ generic_secondary_smp_init));
unsigned int pcpu;
int start_cpu;
Index: linux-2.6/arch/powerpc/platforms/pseries/smp.c
===================================================================
--- linux-2.6.orig/arch/powerpc/platforms/pseries/smp.c
+++ linux-2.6/arch/powerpc/platforms/pseries/smp.c
@@ -63,7 +63,7 @@
*/
static cpumask_t of_spin_map;
-extern void pSeries_secondary_smp_init(unsigned long);
+extern void generic_secondary_smp_init(unsigned long);
#ifdef CONFIG_HOTPLUG_CPU
@@ -271,7 +271,7 @@ static inline int __devinit smp_startup_
{
int status;
unsigned long start_here = __pa((u32)*((unsigned long *)
- pSeries_secondary_smp_init));
+ generic_secondary_smp_init));
unsigned int pcpu;
int start_cpu;
Index: linux-2.6/arch/powerpc/kernel/asm-offsets.c
===================================================================
--- linux-2.6.orig/arch/powerpc/kernel/asm-offsets.c
+++ linux-2.6/arch/powerpc/kernel/asm-offsets.c
@@ -241,6 +241,7 @@ int main(void)
DEFINE(CPU_SPEC_PVR_VALUE, offsetof(struct cpu_spec, pvr_value));
DEFINE(CPU_SPEC_FEATURES, offsetof(struct cpu_spec, cpu_features));
DEFINE(CPU_SPEC_SETUP, offsetof(struct cpu_spec, cpu_setup));
+ DEFINE(CPU_SPEC_RESTORE, offsetof(struct cpu_spec, cpu_restore));
#ifndef CONFIG_PPC64
DEFINE(pbe_address, offsetof(struct pbe, address));
Index: linux-2.6/arch/powerpc/kernel/cputable.c
===================================================================
--- linux-2.6.orig/arch/powerpc/kernel/cputable.c
+++ linux-2.6/arch/powerpc/kernel/cputable.c
@@ -40,7 +40,10 @@ extern void __setup_cpu_7400(unsigned lo
extern void __setup_cpu_7410(unsigned long offset, struct cpu_spec* spec);
extern void __setup_cpu_745x(unsigned long offset, struct cpu_spec* spec);
#endif /* CONFIG_PPC32 */
+#ifdef CONFIG_PPC64
extern void __setup_cpu_ppc970(unsigned long offset, struct cpu_spec* spec);
+extern void __restore_cpu_ppc970(void);
+#endif /* CONFIG_PPC64 */
/* This table only contains "desktop" CPUs, it need to be filled with embedded
* ones as well...
@@ -185,6 +188,7 @@ struct cpu_spec cpu_specs[] = {
.dcache_bsize = 128,
.num_pmcs = 8,
.cpu_setup = __setup_cpu_ppc970,
+ .cpu_restore = __restore_cpu_ppc970,
.oprofile_cpu_type = "ppc64/970",
.oprofile_type = PPC_OPROFILE_POWER4,
.platform = "ppc970",
@@ -200,6 +204,7 @@ struct cpu_spec cpu_specs[] = {
.dcache_bsize = 128,
.num_pmcs = 8,
.cpu_setup = __setup_cpu_ppc970,
+ .cpu_restore = __restore_cpu_ppc970,
.oprofile_cpu_type = "ppc64/970",
.oprofile_type = PPC_OPROFILE_POWER4,
.platform = "ppc970",
@@ -215,6 +220,7 @@ struct cpu_spec cpu_specs[] = {
.dcache_bsize = 128,
.num_pmcs = 8,
.cpu_setup = __setup_cpu_ppc970,
+ .cpu_restore = __restore_cpu_ppc970,
.oprofile_cpu_type = "ppc64/970",
.oprofile_type = PPC_OPROFILE_POWER4,
.platform = "ppc970",
Index: linux-2.6/include/asm-powerpc/cputable.h
===================================================================
--- linux-2.6.orig/include/asm-powerpc/cputable.h
+++ linux-2.6/include/asm-powerpc/cputable.h
@@ -36,6 +36,7 @@
struct cpu_spec;
typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec);
+typedef void (*cpu_restore_t)(void);
enum powerpc_oprofile_type {
PPC_OPROFILE_INVALID = 0,
@@ -65,6 +66,8 @@ struct cpu_spec {
* BHT, SPD, etc... from head.S before branching to identify_machine
*/
cpu_setup_t cpu_setup;
+ /* Used to restore cpu setup on secondary processors and at resume */
+ cpu_restore_t cpu_restore;
/* Used by oprofile userspace to select the right counters */
char *oprofile_cpu_type;
^ permalink raw reply
* Re: [PATCH] convert powermac ide blink to new led infrastructure
From: Johannes Berg @ 2006-06-28 9:43 UTC (permalink / raw)
To: Richard Purdie; +Cc: linuxppc-dev list
In-Reply-To: <1151487483.15913.11.camel@localhost.localdomain>
[-- Attachment #1: Type: text/plain, Size: 97 bytes --]
Richard,
Thanks for the explanation. I'll respin the patch to implement caching.
johannes
[-- Attachment #2: This is a digitally signed message part --]
[-- Type: application/pgp-signature, Size: 793 bytes --]
^ permalink raw reply
* [PATCH] powerpc: U4 DART improvements
From: Olof Johansson @ 2006-06-28 9:50 UTC (permalink / raw)
To: paulus; +Cc: linuxppc-dev
Better late than never...
Respin based on previous comment. Only remaining issue last time was an
extra mb() that I've taken out.
---
Implement single-entry TLB invalidations in the U4 DART.
Simple benchmarking with loopback flood pings of various sizes show that
the previous flush-all code will spend ~5% of the time in flush, while
the new selective invalidations will spend about an order of magnitude
less in the same code path.
This could possibly mean that invalidations larger than, say, 16
entries would better be handled in bulk, but until we have a workload
that actually shows problems or bottlenecks let's keep doing single
invalidations at all mapping sizes.
Signed-off-by: Olof Johansson <olof@lixom.net>
Index: linux-2.6/arch/powerpc/sysdev/dart.h
===================================================================
--- linux-2.6.orig/arch/powerpc/sysdev/dart.h
+++ linux-2.6/arch/powerpc/sysdev/dart.h
@@ -47,8 +47,12 @@
/* U4 registers */
#define DART_BASE_U4_BASE_MASK 0xffffff
#define DART_BASE_U4_BASE_SHIFT 0
-#define DART_CNTL_U4_FLUSHTLB 0x20000000
#define DART_CNTL_U4_ENABLE 0x80000000
+#define DART_CNTL_U4_IONE 0x40000000
+#define DART_CNTL_U4_FLUSHTLB 0x20000000
+#define DART_CNTL_U4_IDLE 0x10000000
+#define DART_CNTL_U4_PAR_EN 0x08000000
+#define DART_CNTL_U4_IONE_MASK 0x07ffffff
#define DART_SIZE_U4_SIZE_MASK 0x1fff
#define DART_SIZE_U4_SIZE_SHIFT 0
Index: linux-2.6/arch/powerpc/sysdev/dart_iommu.c
===================================================================
--- linux-2.6.orig/arch/powerpc/sysdev/dart_iommu.c
+++ linux-2.6/arch/powerpc/sysdev/dart_iommu.c
@@ -101,8 +101,8 @@ retry:
if (l == (1L << limit)) {
if (limit < 4) {
limit++;
- reg = DART_IN(DART_CNTL);
- reg &= ~inv_bit;
+ reg = DART_IN(DART_CNTL);
+ reg &= ~inv_bit;
DART_OUT(DART_CNTL, reg);
goto retry;
} else
@@ -111,11 +111,39 @@ retry:
}
}
+static inline void dart_tlb_invalidate_one(unsigned long bus_rpn)
+{
+ unsigned int reg;
+ unsigned int l, limit;
+
+ reg = DART_CNTL_U4_ENABLE | DART_CNTL_U4_IONE |
+ (bus_rpn & DART_CNTL_U4_IONE_MASK);
+ DART_OUT(DART_CNTL, reg);
+
+ limit = 0;
+wait_more:
+ l = 0;
+ while ((DART_IN(DART_CNTL) & DART_CNTL_U4_IONE) && l < (1L << limit)) {
+ rmb();
+ l++;
+ }
+
+ if (l == (1L << limit)) {
+ if (limit < 4) {
+ limit++;
+ goto wait_more;
+ } else
+ panic("DART: TLB did not flush after waiting a long "
+ "time. Buggy U4 ?");
+ }
+}
+
static void dart_flush(struct iommu_table *tbl)
{
- if (dart_dirty)
+ if (dart_dirty) {
dart_tlb_invalidate_all();
- dart_dirty = 0;
+ dart_dirty = 0;
+ }
}
static void dart_build(struct iommu_table *tbl, long index,
@@ -124,6 +152,7 @@ static void dart_build(struct iommu_tabl
{
unsigned int *dp;
unsigned int rpn;
+ long l;
DBG("dart: build at: %lx, %lx, addr: %x\n", index, npages, uaddr);
@@ -135,7 +164,8 @@ static void dart_build(struct iommu_tabl
/* On U3, all memory is contigous, so we can move this
* out of the loop.
*/
- while (npages--) {
+ l = npages;
+ while (l--) {
rpn = virt_to_abs(uaddr) >> DART_PAGE_SHIFT;
*(dp++) = DARTMAP_VALID | (rpn & DARTMAP_RPNMASK);
@@ -143,7 +173,14 @@ static void dart_build(struct iommu_tabl
uaddr += DART_PAGE_SIZE;
}
- dart_dirty = 1;
+ if (dart_is_u4) {
+ rpn = index;
+ mb(); /* make sure all updates have reached memory */
+ while (npages--)
+ dart_tlb_invalidate_one(rpn++);
+ } else {
+ dart_dirty = 1;
+ }
}
^ permalink raw reply
* Re: [PATCH] convert powermac ide blink to new led infrastructure
From: Richard Purdie @ 2006-06-28 9:38 UTC (permalink / raw)
To: Johannes Berg; +Cc: linuxppc-dev list
In-Reply-To: <1151429483.597.12.camel@localhost>
On Tue, 2006-06-27 at 19:31 +0200, Johannes Berg wrote:
> > Looks good. Only one nit: in pmu_led_set(), you should be able to test
> > if the requested state is identical to the current one and do nothing
> > without taking the lock no ?
> >
> > Or does the upper level LED infrastructure takes care of it ?
>
> I don't know, Richard? But yeah, I can do that too.
The core doesn't do that. In some cases setting the LED is easier and
cheaper than checking a cached value. If setting the LED state is
expensive, it would be simple enough to implement value caching in the
driver.
Part of the problem is also that we provide several values to the driver
(brightness, power, blanking, device specific parameters) and it needs
to combine those values in a way that is only meaningful to the specific
driver.
Richard
^ permalink raw reply
* MPC852T help me for: Oops: kernel access of bad area, sig: 11
From: SETTE AGOSTINO - technolabs @ 2006-06-28 10:01 UTC (permalink / raw)
To: linuxppc-embedded
Dear,
Here is my problem,
Our environment is:
OS: Linux-2.4.20
platform: MPC852T
Oops: kernel access of bad area, sig: 11
NIP: C000D440 XER: 00000000 LR: C00BB040 SP: C06BDE50 REGS: c06bdda0
TRAP: 0300 Tainted: P
MSR: 00009032 EE: 1 PR: 0 FP: 0 ME: 1 IR/DR: 11
DAR: 0000205D, DSISR: 000000E4
TASK =3D c06bc000[181] 'L5420' Last syscall: 78
last math 00000000 last altivec 00000000
GPR00: 00000000 C06BDE50 C06BC000 C0D074E0 00002059 0000003C C0D074DC
00000007
GPR08: 00000001 0000003C 00000000 C0D07520 82004084 101B3AF8 3052816C
C3120000
GPR16: C311CB04 C311C8D8 C311C754 C0170000 C3120000 C311CB30 00000001
C0169DA0
GPR24: F0000E00 0000205D C0F58400 0000003C 00000040 C2080100 C0F58200
C0F50360
Call backtrace:
C00BAF8C C00BABC8 C0005848 C3119448 C3119918 C00047A8 100D8AC0
100D6718 100C370C 100674AC 100639E4 1005ED18 10042638 10010E28
1003AC34 1000DA34 100361EC 0FED34A4 0FED32D0 0FFCFEE4 0FD5F590
Kernel panic: Aiee, killing interrupt handler!
In interrupt handler - not syncing
<0>Rebooting in 180 seconds..
How to debug and correct it? Plese help me!
Thanks a lot!
-------------------------------------------
Best Regards
Agostino Sette
^ permalink raw reply
* Re: 2.6.17-mm2
From: Andrew Morton @ 2006-06-28 10:42 UTC (permalink / raw)
To: Martin J. Bligh, Jeremy Fitzhardinge
Cc: linuxppc64-dev, linux-kernel, mbligh, mbligh
In-Reply-To: <44A150C9.7020809@mbligh.org>
On Tue, 27 Jun 2006 08:37:45 -0700
"Martin J. Bligh" <mbligh@mbligh.org> wrote:
> SMP NR_CPUS=32 NUMA
> Modules linked in:
> NIP: C0000000000A311C LR: C0000000000A30D4 CTR: C0000000000A3024
> REGS: c0000007725b38d0 TRAP: 0300 Not tainted (2.6.17-mm3-autokern1)
> MSR: 8000000000001032 <ME,IR,DR> CR: 28224424 XER: 00000000
> DAR: 000000077BCC6180, DSISR: 0000000040000000
> TASK = c00000002fc74670[29812] 'cp' THREAD: c0000007725b0000 CPU: 2
> GPR00: 0000000000000000 C0000007725B3B50 C00000000063B828 C00000001E303EC0
> GPR04: 0000000000000010 0000000000000000 0000000000000000 FFFFFFFFFFFFFFFD
> GPR08: 0000000000000001 0000000000000000 000000077BCC6180 0000000000000000
> GPR12: 0000000000000000 C00000000051FF80 0000000000000000 0000000000000001
> GPR16: 0000000000000000 0000000000000004 0000000000020000 0000000000000000
> GPR20: 0000000000000000 0000000000000000 C0000007759F9D00 0000000000000000
> GPR24: 0000000000000E42 0000000000000000 000000000000474A C00000001E30F300
> GPR28: 0000000000000000 0000000000000000 C000000000537288 C00000001E303E80
> NIP [C0000000000A311C] .s_show+0xf8/0x364
> LR [C0000000000A30D4] .s_show+0xb0/0x364
> Call Trace:
> [C0000007725B3B50] [C0000000000A3334] .s_show+0x310/0x364 (unreliable)
> [C0000007725B3C20] [C0000000000D5E84] .seq_read+0x2f4/0x450
> [C0000007725B3D00] [C0000000000AADF8] .vfs_read+0xe0/0x1b4
> [C0000007725B3D90] [C0000000000AAFD4] .sys_read+0x54/0x98
> [C0000007725B3E30] [C00000000000871C] syscall_exit+0x0/0x40
This is caused by the vsprintf() changes. Right now, if you do
snprintf(buf, 4, "1111111111111");
the memory at `buf' gets [31 31 31 31 00], which is not good.
This'll plug it, but I didn't check very hard whether it still has any
off-by-ones, or if breaks the intent of Jeremy's patch. I think it's OK..
--- a/lib/vsprintf.c~c
+++ a/lib/vsprintf.c
@@ -259,7 +259,9 @@ int vsnprintf(char *buf, size_t size, co
int len;
unsigned long long num;
int i, base;
- char *str, *end, c;
+ char *str; /* Where we're writing to */
+ char *end; /* The last byte we can write to */
+ char c;
const char *s;
int flags; /* flags to number() */
@@ -283,12 +285,12 @@ int vsnprintf(char *buf, size_t size, co
}
str = buf;
- end = buf + size;
+ end = buf + size - 1;
/* Make sure end is always >= buf */
- if (end < buf) {
+ if (end < buf - 1) {
end = ((void *) ~0ull);
- size = end - buf;
+ size = end - buf + 1;
}
for (; *fmt ; ++fmt) {
_
^ permalink raw reply
* Re: 2.6.17-mm2
From: Andrew Morton @ 2006-06-28 10:47 UTC (permalink / raw)
To: mbligh, jeremy, mbligh, linux-kernel, apw, linuxppc64-dev
In-Reply-To: <20060628034215.c3008299.akpm@osdl.org>
On Wed, 28 Jun 2006 03:42:15 -0700
Andrew Morton <akpm@osdl.org> wrote:
> his is caused by the vsprintf() changes. Right now, if you do
>
> snprintf(buf, 4, "1111111111111");
>
> the memory at `buf' gets [31 31 31 31 00], which is not good.
>
> This'll plug it, but I didn't check very hard whether it still has any
> off-by-ones, or if breaks the intent of Jeremy's patch. I think it's OK..
That diff was against an older kernel and doesn't apply. This is against
mainline:
--- a/lib/vsprintf.c~vsnprintf-fix
+++ a/lib/vsprintf.c
@@ -259,7 +259,9 @@ int vsnprintf(char *buf, size_t size, co
int len;
unsigned long long num;
int i, base;
- char *str, *end, c;
+ char *str; /* Where we're writing to */
+ char *end; /* The last byte we can write to */
+ char c;
const char *s;
int flags; /* flags to number() */
@@ -283,12 +285,12 @@ int vsnprintf(char *buf, size_t size, co
}
str = buf;
- end = buf + size;
+ end = buf + size - 1;
/* Make sure end is always >= buf */
- if (end < buf) {
+ if (end < buf - 1) {
end = ((void *)-1);
- size = end - buf;
+ size = end - buf + 1;
}
for (; *fmt ; ++fmt) {
@@ -494,7 +496,6 @@ int vsnprintf(char *buf, size_t size, co
/* the trailing null byte doesn't count towards the total */
return str-buf;
}
-
EXPORT_SYMBOL(vsnprintf);
/**
_
^ permalink raw reply
* Re: [PATCH] powerpc: support ibm,extended-*-frequency properties
From: Segher Boessenkool @ 2006-06-28 11:15 UTC (permalink / raw)
To: Kumar Gala; +Cc: linuxppc-dev, paulus, Anton Blanchard
In-Reply-To: <0107ED1F-B674-48C3-AA07-BDF9FD2F7678@kernel.crashing.org>
> Is it reasonable for cells to be greater than 1 on a 32-bit system?
Yes.
Segher
^ permalink raw reply
* Re: [PATCH] powerpc: support ibm,extended-*-frequency properties
From: Anton Blanchard @ 2006-06-28 11:28 UTC (permalink / raw)
To: Segher Boessenkool; +Cc: linuxppc-dev, paulus
In-Reply-To: <D0B9DD42-E1D3-48E3-A90A-8F8B5718852F@kernel.crashing.org>
> Could you also allow the regular "timebase-frequency" property
> to consist of two cells, with the same semantics? That's what
> some other systems do. Hey, it'd simplify this code, if anything :-)
>
> In fact, some kernel code already does this if I'm not mistaken
> (the Cell port, perhaps?)
Yeah it seems reasonable to just use the property size, I'll submit an
incremental patch for that.
Anton
^ permalink raw reply
* no login prompt with ml403 + uartlite-->major numbers?
From: Robert Zach @ 2006-06-28 12:14 UTC (permalink / raw)
To: linuxppc-embedded
Hello!
I use the "Standart" ml403 Design with the uartlite instead of the
uart16550...
my kernel parameters are:
"console=ttl0 ip=off root=/dev/xsysace/disc0/part3 rw"
It boots correctly, but i got no login prompt!!
getty is started with init.
my inittab looks like:
...
::respawn:/sbin/getty 9600 ttl0
...
I use devfs.
Is the inittab entry correct?
Which device is the uartlite in devfs?
Which major numbers uses the uartlite?
thanks in advanced!
nice greetings,
Robert Zach
loaded at: 00400000 004CC1E0
board data at: 004C9138 004C9150
relocated to: 0040530C 00405324
zimage at: 004058D1 004C885F
avail ram: 004CD000 04000000
Linux/PPC load: console=ttl0 ip=off root=/dev/xsysace/disc0/part3 rw
Uncompressing Linux...done.
Now booting the kernel
Linux version 2.4.26 (sem03@escola06) (gcc version 3.4.1) #3 Wed Jun 28
13:19:30
CEST 2006
Xilinx Virtex-II Pro port (C) 2002 MontaVista Software, Inc.
(source@mvista.com)
On node 0 totalpages: 16384
zone(0): 16384 pages.
zone(1): 0 pages.
zone(2): 0 pages.
Kernel command line: console=ttl0 ip=off root=/dev/xsysace/disc0/part3 rw
Xilinx INTC #0 at 0x41200000 mapped to 0xFDFFF000
Calibrating delay loop... 299.82 BogoMIPS
Memory: 62884k available (1420k kernel code, 400k data, 56k init, 0k
highmem)
Dentry cache hash table entries: 8192 (order: 4, 65536 bytes)
Inode cache hash table entries: 4096 (order: 3, 32768 bytes)
Mount cache hash table entries: 512 (order: 0, 4096 bytes)
Buffer cache hash table entries: 4096 (order: 2, 16384 bytes)
Page-cache hash table entries: 16384 (order: 4, 65536 bytes)
POSIX conformance testing by UNIFIX
Linux NET4.0 for Linux 2.4
Based upon Swansea University Computer Society NET3.039
Initializing RT netlink socket
Starting kswapd
Journalled Block Device driver loaded
devfs: v1.12c (20020818) Richard Gooch (rgooch@atnf.csiro.au)
devfs: devfs_debug: 0x0
devfs: boot_options: 0x1
Installing knfsd (copyright (C) 1996 okir@monad.swb.de).
pty: 256 Unix98 ptys configured
RAMDISK driver initialized: 16 RAM disks of 4096K size 1024 blocksize
Partition check:
xsysacea: p1 p2 p3
System ACE at 0x41800000 mapped to 0xC5000000, irq=28, 500472KB
eth0: using fifo mode.
eth0: No PHY detected. Assuming a PHY at address 0.
eth0: Xilinx EMAC #0 at 0x40C00000 mapped to 0xC5013000, irq=31
eth0: id 2.0h; block id 7, type 1
NET4: Linux TCP/IP 1.0 for NET4.0
IP Protocols: ICMP, UDP, TCP, IGMP
IP: routing cache hash table of 512 buckets, 4Kbytes
TCP: Hash tables configured (established 4096 bind 8192)
NET4: Unix domain sockets 1.0/SMP for Linux NET4.0.
kjournald starting. Commit interval 5 seconds
EXT3 FS 2.4-0.9.19, 19 August 2002 on System ACE(254,3), internal journal
EXT3-fs: recovery complete.
EXT3-fs: mounted filesystem with ordered data mode.
VFS: Mounted root (ext3 filesystem).
Mounted devfs on /dev
Freeing unused kernel memory: 56k init
XDS ML403 powerpc linux 2.4.26 Training
Starting system...
Starting Network
Start syslogd
done.
Start klogd
done.
System Started.
eth0: Link carrier lost.
^ permalink raw reply
* Re: Please pull from 'for_paulus' branch of powerpc
From: Kumar Gala @ 2006-06-28 13:19 UTC (permalink / raw)
To: Zhang Wei-r63237; +Cc: linuxppc-dev, Paul Mackerras, linux-kernel
In-Reply-To: <9FCDBA58F226D911B202000BDBAD467306DD14E0@zch01exm40.ap.freescale.net>
On Jun 28, 2006, at 1:26 AM, Zhang Wei-r63237 wrote:
> Hi, Kumar,
>
> Why moving these codes from pci.c to mpc86xx_hpcn.c? It's not must be.
> These functions relate to PCI device of MPC8641D HPCn platform.
> And we can also see the 'DECLARE_PCI_FIXUP_HEADER()' declaration in
> pci.c of Powermac platform.
The point for moving is 86xx/pci.c should apply to all 86xx systems,
not just the HPCn system.
- kumar
>> -----Original Message-----
>> From: linuxppc-dev-bounces+wei.zhang=freescale.com@ozlabs.org
>> [mailto:linuxppc-dev-bounces+wei.zhang=freescale.com@ozlabs.or
>> g] On Behalf Of Kumar Gala
>> Sent: Wednesday, June 28, 2006 2:01 PM
>> To: Paul Mackerras
>> Cc: linuxppc-dev@ozlabs.org; linux-kernel@vger.kernel.org
>> Subject: Please pull from 'for_paulus' branch of powerpc
>>
>> Please pull from 'for_paulus' branch of
>> master.kernel.org:/pub/scm/linux/kernel/git/galak/powerpc.git
>>
>> to receive the following updates:
>>
>> arch/powerpc/kernel/cputable.c | 12 --
>> arch/powerpc/platforms/86xx/mpc86xx.h | 8 +
>> arch/powerpc/platforms/86xx/mpc86xx_hpcn.c | 128
>> +++++++++++++++++++++++++--
>> arch/powerpc/platforms/86xx/mpc86xx_smp.c | 9 -
>> arch/powerpc/platforms/86xx/pci.c | 136
>> +----------------------------
>> include/asm-powerpc/mpc86xx.h | 4
>> 6 files changed, 138 insertions(+), 159 deletions(-)
>>
>> Kumar Gala:
>> powerpc: minor cleanups for mpc86xx
>>
>> diff --git a/arch/powerpc/kernel/cputable.c
>> b/arch/powerpc/kernel/cputable.c index 1c11488..abf7d42 100644
>> --- a/arch/powerpc/kernel/cputable.c
>> +++ b/arch/powerpc/kernel/cputable.c
>> @@ -722,18 +722,6 @@ #if CLASSIC_PPC
>> .oprofile_type = PPC_OPROFILE_G4,
>> .platform = "ppc7450",
>> },
>> - { /* 8641 */
>> - .pvr_mask = 0xffffffff,
>> - .pvr_value = 0x80040010,
>> - .cpu_name = "8641",
>> - .cpu_features = CPU_FTRS_7447A,
>> - .cpu_user_features = COMMON_USER |
>> PPC_FEATURE_HAS_ALTIVEC_COMP,
>> - .icache_bsize = 32,
>> - .dcache_bsize = 32,
>> - .num_pmcs = 6,
>> - .cpu_setup = __setup_cpu_745x
>> - },
>> -
>> { /* 82xx (8240, 8245, 8260 are all 603e cores) */
>> .pvr_mask = 0x7fff0000,
>> .pvr_value = 0x00810000,
>> diff --git a/arch/powerpc/platforms/86xx/mpc86xx.h
>> b/arch/powerpc/platforms/86xx/mpc86xx.h
>> index e3c9e4f..2834462 100644
>> --- a/arch/powerpc/platforms/86xx/mpc86xx.h
>> +++ b/arch/powerpc/platforms/86xx/mpc86xx.h
>> @@ -15,11 +15,13 @@ #define __MPC86XX_H__
>> * mpc86xx_* files. Mostly for use by mpc86xx_setup().
>> */
>>
>> -extern int __init add_bridge(struct device_node *dev);
>> +extern int add_bridge(struct device_node *dev);
>>
>> -extern void __init setup_indirect_pcie(struct pci_controller *hose,
>> +extern int mpc86xx_exclude_device(u_char bus, u_char devfn);
>> +
>> +extern void setup_indirect_pcie(struct pci_controller *hose,
>> u32 cfg_addr, u32
>> cfg_data); -extern void __init
>> setup_indirect_pcie_nomap(struct pci_controller *hose,
>> +extern void setup_indirect_pcie_nomap(struct pci_controller *hose,
>> void __iomem *cfg_addr,
>> void __iomem *cfg_data);
>>
>> diff --git a/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c
>> b/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c
>> index 483c21d..ac7f418 100644
>> --- a/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c
>> +++ b/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c
>> @@ -36,6 +36,7 @@ #include <asm/mpic.h>
>> #include <sysdev/fsl_soc.h>
>>
>> #include "mpc86xx.h"
>> +#include "mpc8641_hpcn.h"
>>
>> #ifndef CONFIG_PCI
>> unsigned long isa_io_base = 0;
>> @@ -186,17 +187,130 @@ mpc86xx_map_irq(struct pci_dev *dev, uns
>> return PCI_IRQ_TABLE_LOOKUP + I8259_OFFSET; }
>>
>> +static void __devinit quirk_ali1575(struct pci_dev *dev) {
>> + unsigned short temp;
>> +
>> + /*
>> + * ALI1575 interrupts route table setup:
>> + *
>> + * IRQ pin IRQ#
>> + * PIRQA ---- 3
>> + * PIRQB ---- 4
>> + * PIRQC ---- 5
>> + * PIRQD ---- 6
>> + * PIRQE ---- 9
>> + * PIRQF ---- 10
>> + * PIRQG ---- 11
>> + * PIRQH ---- 12
>> + *
>> + * interrupts for PCI slot0 -- PIRQA / PIRQB / PIRQC / PIRQD
>> + * PCI slot1 -- PIRQB / PIRQC / PIRQD / PIRQA
>> + */
>> + pci_write_config_dword(dev, 0x48, 0xb9317542);
>> +
>> + /* USB 1.1 OHCI controller 1, interrupt: PIRQE */
>> + pci_write_config_byte(dev, 0x86, 0x0c);
>> +
>> + /* USB 1.1 OHCI controller 2, interrupt: PIRQF */
>> + pci_write_config_byte(dev, 0x87, 0x0d);
>> +
>> + /* USB 1.1 OHCI controller 3, interrupt: PIRQH */
>> + pci_write_config_byte(dev, 0x88, 0x0f);
>> +
>> + /* USB 2.0 controller, interrupt: PIRQ7 */
>> + pci_write_config_byte(dev, 0x74, 0x06);
>> +
>> + /* Audio controller, interrupt: PIRQE */
>> + pci_write_config_byte(dev, 0x8a, 0x0c);
>> +
>> + /* Modem controller, interrupt: PIRQF */
>> + pci_write_config_byte(dev, 0x8b, 0x0d);
>> +
>> + /* HD audio controller, interrupt: PIRQG */
>> + pci_write_config_byte(dev, 0x8c, 0x0e);
>> +
>> + /* Serial ATA interrupt: PIRQD */
>> + pci_write_config_byte(dev, 0x8d, 0x0b);
>> +
>> + /* SMB interrupt: PIRQH */
>> + pci_write_config_byte(dev, 0x8e, 0x0f);
>> +
>> + /* PMU ACPI SCI interrupt: PIRQH */
>> + pci_write_config_byte(dev, 0x8f, 0x0f);
>> +
>> + /* Primary PATA IDE IRQ: 14
>> + * Secondary PATA IDE IRQ: 15
>> + */
>> + pci_write_config_byte(dev, 0x44, 0x3d);
>> + pci_write_config_byte(dev, 0x75, 0x0f);
>> +
>> + /* Set IRQ14 and IRQ15 to legacy IRQs */
>> + pci_read_config_word(dev, 0x46, &temp);
>> + temp |= 0xc000;
>> + pci_write_config_word(dev, 0x46, temp);
>> +
>> + /* Set i8259 interrupt trigger
>> + * IRQ 3: Level
>> + * IRQ 4: Level
>> + * IRQ 5: Level
>> + * IRQ 6: Level
>> + * IRQ 7: Level
>> + * IRQ 9: Level
>> + * IRQ 10: Level
>> + * IRQ 11: Level
>> + * IRQ 12: Level
>> + * IRQ 14: Edge
>> + * IRQ 15: Edge
>> + */
>> + outb(0xfa, 0x4d0);
>> + outb(0x1e, 0x4d1);
>> +}
>>
>> -int
>> -mpc86xx_exclude_device(u_char bus, u_char devfn)
>> +static void __devinit quirk_uli5288(struct pci_dev *dev)
>> {
>> -#if !defined(CONFIG_PCI)
>> - if (bus == 0 && PCI_SLOT(devfn) == 0)
>> - return PCIBIOS_DEVICE_NOT_FOUND;
>> -#endif
>> + unsigned char c;
>> +
>> + pci_read_config_byte(dev,0x83,&c);
>> + c |= 0x80;
>> + pci_write_config_byte(dev, 0x83, c);
>> +
>> + pci_write_config_byte(dev, 0x09, 0x01);
>> + pci_write_config_byte(dev, 0x0a, 0x06);
>> +
>> + pci_read_config_byte(dev,0x83,&c);
>> + c &= 0x7f;
>> + pci_write_config_byte(dev, 0x83, c);
>>
>> - return PCIBIOS_SUCCESSFUL;
>> + pci_read_config_byte(dev,0x84,&c);
>> + c |= 0x01;
>> + pci_write_config_byte(dev, 0x84, c);
>> }
>> +
>> +static void __devinit quirk_uli5229(struct pci_dev *dev) {
>> + unsigned short temp;
>> + pci_write_config_word(dev, 0x04, 0x0405);
>> + pci_read_config_word(dev, 0x4a, &temp);
>> + temp |= 0x1000;
>> + pci_write_config_word(dev, 0x4a, temp); }
>> +
>> +static void __devinit early_uli5249(struct pci_dev *dev) {
>> + unsigned char temp;
>> + pci_write_config_word(dev, 0x04, 0x0007);
>> + pci_read_config_byte(dev, 0x7c, &temp);
>> + pci_write_config_byte(dev, 0x7c, 0x80);
>> + pci_write_config_byte(dev, 0x09, 0x01);
>> + pci_write_config_byte(dev, 0x7c, temp);
>> + dev->class |= 0x1;
>> +}
>> +
>> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x1575, quirk_ali1575);
>> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5288, quirk_uli5288);
>> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5229, quirk_uli5229);
>> +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AL, 0x5249, early_uli5249);
>> #endif /* CONFIG_PCI */
>>
>>
>> diff --git a/arch/powerpc/platforms/86xx/mpc86xx_smp.c
>> b/arch/powerpc/platforms/86xx/mpc86xx_smp.c
>> index 944ec4b..9cca3d1 100644
>> --- a/arch/powerpc/platforms/86xx/mpc86xx_smp.c
>> +++ b/arch/powerpc/platforms/86xx/mpc86xx_smp.c
>> @@ -34,8 +34,8 @@ extern unsigned long __secondary_hold_ac
>> static void __init smp_86xx_release_core(int nr) {
>> - void *mcm_vaddr;
>> - unsigned long vaddr, pcr;
>> + __be32 __iomem *mcm_vaddr;
>> + unsigned long pcr;
>>
>> if (nr < 0 || nr >= NR_CPUS)
>> return;
>> @@ -45,10 +45,9 @@ smp_86xx_release_core(int nr)
>> */
>> mcm_vaddr = ioremap(get_immrbase() + MPC86xx_MCM_OFFSET,
>> MPC86xx_MCM_SIZE);
>> - vaddr = (unsigned long)mcm_vaddr + MCM_PORT_CONFIG_OFFSET;
>> - pcr = in_be32((volatile unsigned *)vaddr);
>> + pcr = in_be32(mcm_vaddr + (MCM_PORT_CONFIG_OFFSET >> 2));
>> pcr |= 1 << (nr + 24);
>> - out_be32((volatile unsigned *)vaddr, pcr);
>> + out_be32(mcm_vaddr + (MCM_PORT_CONFIG_OFFSET >> 2), pcr);
>> }
>>
>>
>> diff --git a/arch/powerpc/platforms/86xx/pci.c
>> b/arch/powerpc/platforms/86xx/pci.c
>> index 5180df7..0d8b340 100644
>> --- a/arch/powerpc/platforms/86xx/pci.c
>> +++ b/arch/powerpc/platforms/86xx/pci.c
>> @@ -122,15 +122,12 @@ static void __init
>> setup_pcie_atmu(struc static void __init
>> mpc86xx_setup_pcie(struct pci_controller *hose, u32
>> pcie_offset, u32 pcie_size) {
>> - volatile struct ccsr_pex *pcie;
>> u16 cmd;
>> unsigned int temps;
>>
>> DBG("PCIE host controller register offset 0x%08x, size
>> 0x%08x.\n",
>> pcie_offset, pcie_size);
>>
>> - pcie = ioremap(pcie_offset, pcie_size);
>> -
>> early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd);
>> cmd |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER |
>> PCI_COMMAND_MEMORY
>> | PCI_COMMAND_IO;
>> @@ -144,6 +141,14 @@ mpc86xx_setup_pcie(struct pci_controller
>> early_write_config_dword(hose, 0, 0, PCI_PRIMARY_BUS, temps); }
>>
>> +int mpc86xx_exclude_device(u_char bus, u_char devfn) {
>> + if (bus == 0 && PCI_SLOT(devfn) == 0)
>> + return PCIBIOS_DEVICE_NOT_FOUND;
>> +
>> + return PCIBIOS_SUCCESSFUL;
>> +}
>> +
>> int __init add_bridge(struct device_node *dev) {
>> int len;
>> @@ -198,128 +203,3 @@ int __init add_bridge(struct device_node
>>
>> return 0;
>> }
>> -
>> -static void __devinit quirk_ali1575(struct pci_dev *dev) -{
>> - unsigned short temp;
>> -
>> - /*
>> - * ALI1575 interrupts route table setup:
>> - *
>> - * IRQ pin IRQ#
>> - * PIRQA ---- 3
>> - * PIRQB ---- 4
>> - * PIRQC ---- 5
>> - * PIRQD ---- 6
>> - * PIRQE ---- 9
>> - * PIRQF ---- 10
>> - * PIRQG ---- 11
>> - * PIRQH ---- 12
>> - *
>> - * interrupts for PCI slot0 -- PIRQA / PIRQB / PIRQC / PIRQD
>> - * PCI slot1 -- PIRQB / PIRQC / PIRQD / PIRQA
>> - */
>> - pci_write_config_dword(dev, 0x48, 0xb9317542);
>> -
>> - /* USB 1.1 OHCI controller 1, interrupt: PIRQE */
>> - pci_write_config_byte(dev, 0x86, 0x0c);
>> -
>> - /* USB 1.1 OHCI controller 2, interrupt: PIRQF */
>> - pci_write_config_byte(dev, 0x87, 0x0d);
>> -
>> - /* USB 1.1 OHCI controller 3, interrupt: PIRQH */
>> - pci_write_config_byte(dev, 0x88, 0x0f);
>> -
>> - /* USB 2.0 controller, interrupt: PIRQ7 */
>> - pci_write_config_byte(dev, 0x74, 0x06);
>> -
>> - /* Audio controller, interrupt: PIRQE */
>> - pci_write_config_byte(dev, 0x8a, 0x0c);
>> -
>> - /* Modem controller, interrupt: PIRQF */
>> - pci_write_config_byte(dev, 0x8b, 0x0d);
>> -
>> - /* HD audio controller, interrupt: PIRQG */
>> - pci_write_config_byte(dev, 0x8c, 0x0e);
>> -
>> - /* Serial ATA interrupt: PIRQD */
>> - pci_write_config_byte(dev, 0x8d, 0x0b);
>> -
>> - /* SMB interrupt: PIRQH */
>> - pci_write_config_byte(dev, 0x8e, 0x0f);
>> -
>> - /* PMU ACPI SCI interrupt: PIRQH */
>> - pci_write_config_byte(dev, 0x8f, 0x0f);
>> -
>> - /* Primary PATA IDE IRQ: 14
>> - * Secondary PATA IDE IRQ: 15
>> - */
>> - pci_write_config_byte(dev, 0x44, 0x3d);
>> - pci_write_config_byte(dev, 0x75, 0x0f);
>> -
>> - /* Set IRQ14 and IRQ15 to legacy IRQs */
>> - pci_read_config_word(dev, 0x46, &temp);
>> - temp |= 0xc000;
>> - pci_write_config_word(dev, 0x46, temp);
>> -
>> - /* Set i8259 interrupt trigger
>> - * IRQ 3: Level
>> - * IRQ 4: Level
>> - * IRQ 5: Level
>> - * IRQ 6: Level
>> - * IRQ 7: Level
>> - * IRQ 9: Level
>> - * IRQ 10: Level
>> - * IRQ 11: Level
>> - * IRQ 12: Level
>> - * IRQ 14: Edge
>> - * IRQ 15: Edge
>> - */
>> - outb(0xfa, 0x4d0);
>> - outb(0x1e, 0x4d1);
>> -}
>> -
>> -static void __devinit quirk_uli5288(struct pci_dev *dev) -{
>> - unsigned char c;
>> -
>> - pci_read_config_byte(dev,0x83,&c);
>> - c |= 0x80;
>> - pci_write_config_byte(dev, 0x83, c);
>> -
>> - pci_write_config_byte(dev, 0x09, 0x01);
>> - pci_write_config_byte(dev, 0x0a, 0x06);
>> -
>> - pci_read_config_byte(dev,0x83,&c);
>> - c &= 0x7f;
>> - pci_write_config_byte(dev, 0x83, c);
>> -
>> - pci_read_config_byte(dev,0x84,&c);
>> - c |= 0x01;
>> - pci_write_config_byte(dev, 0x84, c);
>> -}
>> -
>> -static void __devinit quirk_uli5229(struct pci_dev *dev) -{
>> - unsigned short temp;
>> - pci_write_config_word(dev, 0x04, 0x0405);
>> - pci_read_config_word(dev, 0x4a, &temp);
>> - temp |= 0x1000;
>> - pci_write_config_word(dev, 0x4a, temp);
>> -}
>> -
>> -static void __devinit early_uli5249(struct pci_dev *dev) -{
>> - unsigned char temp;
>> - pci_write_config_word(dev, 0x04, 0x0007);
>> - pci_read_config_byte(dev, 0x7c, &temp);
>> - pci_write_config_byte(dev, 0x7c, 0x80);
>> - pci_write_config_byte(dev, 0x09, 0x01);
>> - pci_write_config_byte(dev, 0x7c, temp);
>> - dev->class |= 0x1;
>> -}
>> -
>> -DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x1575,
>> quirk_ali1575); -DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL,
>> 0x5288, quirk_uli5288);
>> -DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5229,
>> quirk_uli5229); -DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AL,
>> 0x5249, early_uli5249); diff --git
>> a/include/asm-powerpc/mpc86xx.h
>> b/include/asm-powerpc/mpc86xx.h index d0a6718..00d72a7 100644
>> --- a/include/asm-powerpc/mpc86xx.h
>> +++ b/include/asm-powerpc/mpc86xx.h
>> @@ -20,10 +20,6 @@ #include <asm/mmu.h>
>>
>> #ifdef CONFIG_PPC_86xx
>>
>> -#ifdef CONFIG_MPC8641_HPCN
>> -#include <platforms/86xx/mpc8641_hpcn.h> -#endif
>> -
>> #define _IO_BASE isa_io_base
>> #define _ISA_MEM_BASE isa_mem_base
>> #ifdef CONFIG_PCI
>>
>> _______________________________________________
>> Linuxppc-dev mailing list
>> Linuxppc-dev@ozlabs.org
>> https://ozlabs.org/mailman/listinfo/linuxppc-dev
>>
^ permalink raw reply
* backlight control broken in current Linus' and Paulus' trees
From: Aristeu Sergio Rozanski Filho @ 2006-06-28 13:34 UTC (permalink / raw)
To: linuxppc-dev
Hi,
the backlight control is broken in my PowerBook6,8 in latest git
trees, both for pbbuttonsd (yes, I have CONFIG_PMAC_BACKLIGHT_LEGACY
enabled) and for fblevel. the last one also allows values be set
at least to 1000 and according to new code, it should be able to
reach 127. I gathered some information in
http://www.cathedrallabs.org/~aris/backlight/
if I can provide any other information or help in testing,
please let me know.
--
Aristeu
^ permalink raw reply
* [PATCH 0/7] Add mpc8360epb and QE support to powerpc
From: Li Yang-r58472 @ 2006-06-28 14:22 UTC (permalink / raw)
To: 'Paul Mackerras'
Cc: linuxppc-dev, Chu hanjin-r52514,
'linux-kernel@vger.kernel.org'
This series of patches add support to MPC8360E MDS-PB board into powerpc arch. It provides generic QE API called qe_lib. Other QE device drivers should use this library. It also includes an UCC gigabit Ethernet driver using qe_lib; mtd mapping file to use jffs/jffs2 filesystem.
--
Leo Li
Freescale Semiconductor
LeoLi@freescale.com
^ permalink raw reply
* [PATCH 1/7] powerpc: Add mpc8360epb platform support
From: Li Yang-r58472 @ 2006-06-28 14:23 UTC (permalink / raw)
To: 'Paul Mackerras'
Cc: linuxppc-dev, Phillips Kim-R1AAHA, Chu hanjin-r52514,
Yin Olivia-r63875, 'linux-kernel@vger.kernel.org'
The patch adds mpc8360e MDS Processor Board support.
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Yin Olivia <hong-hua.yin@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
---
arch/powerpc/platforms/83xx/Kconfig | 13 ++
arch/powerpc/platforms/83xx/Makefile | 1
arch/powerpc/platforms/83xx/mpc8360e_pb.c | 213 +++++++++++++++++++++++++++++
arch/powerpc/platforms/83xx/mpc8360e_pb.h | 31 ++++
4 files changed, 258 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/platforms/83xx/Kconfig b/arch/powerpc/platforms/83xx/Kconfig
index 7675e67..04c4508 100644
--- a/arch/powerpc/platforms/83xx/Kconfig
+++ b/arch/powerpc/platforms/83xx/Kconfig
@@ -16,6 +16,13 @@ config MPC834x_SYS
3 PCI slots. The PIBs PCI initialization is the bootloader's
responsiblilty.
+config MPC8360E_PB
+ bool "Freescale MPC8360E PB"
+ select DEFAULT_UIMAGE
+ select QUICC_ENGINE
+ help
+ This option enables support for the MPC836x EMDS Processor Board.
+
endchoice
config MPC834x
@@ -24,4 +31,10 @@ config MPC834x
select PPC_INDIRECT_PCI
default y if MPC834x_SYS
+config MPC836x
+ bool
+ select PPC_UDBG_16550
+ select PPC_INDIRECT_PCI
+ default y if MPC8360E_PB
+
endmenu
diff --git a/arch/powerpc/platforms/83xx/Makefile b/arch/powerpc/platforms/83xx/Makefile
index 5c72367..0c9ea5c 100644
--- a/arch/powerpc/platforms/83xx/Makefile
+++ b/arch/powerpc/platforms/83xx/Makefile
@@ -4,3 +4,4 @@ #
obj-y := misc.o
obj-$(CONFIG_PCI) += pci.o
obj-$(CONFIG_MPC834x_SYS) += mpc834x_sys.o
+obj-$(CONFIG_MPC8360E_PB) += mpc8360e_pb.o
diff --git a/arch/powerpc/platforms/83xx/mpc8360e_pb.c b/arch/powerpc/platforms/83xx/mpc8360e_pb.c
new file mode 100644
index 0000000..b4ddb0a
--- /dev/null
+++ b/arch/powerpc/platforms/83xx/mpc8360e_pb.c
@@ -0,0 +1,213 @@
+/*
+ * Copyright (C) Freescale Semicondutor, Inc. 2006. All rights reserved.
+ *
+ * Author: Li Yang <LeoLi@freescale.com>
+ * Yin Olivia <Hong-hua.Yin@freescale.com>
+ *
+ * Description:
+ * MPC8360E MDS PB board specific routines.
+ *
+ * Changelog:
+ * Jun 21, 2006 Initial version
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/config.h>
+#include <linux/stddef.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/reboot.h>
+#include <linux/pci.h>
+#include <linux/kdev_t.h>
+#include <linux/major.h>
+#include <linux/console.h>
+#include <linux/delay.h>
+#include <linux/seq_file.h>
+#include <linux/root_dev.h>
+#include <linux/initrd.h>
+
+#include <asm/system.h>
+#include <asm/atomic.h>
+#include <asm/time.h>
+#include <asm/io.h>
+#include <asm/machdep.h>
+#include <asm/ipic.h>
+#include <asm/bootinfo.h>
+#include <asm/irq.h>
+#include <asm/prom.h>
+#include <asm/udbg.h>
+#include <sysdev/fsl_soc.h>
+#ifdef CONFIG_QUICC_ENGINE
+#include <asm/immap_qe.h>
+#include <asm/qe_ic.h>
+#endif /* CONFIG_QUICC_ENGINE */
+#include "mpc83xx.h"
+#include "mpc8360e_pb.h"
+
+#undef DEBUG
+
+#ifdef DEBUG
+#define DBG(fmt...) udbg_printf(fmt)
+#else
+#define DBG(fmt...)
+#endif
+
+
+#ifndef CONFIG_PCI
+unsigned long isa_io_base = 0;
+unsigned long isa_mem_base = 0;
+#endif
+
+#ifdef CONFIG_QUICC_ENGINE
+extern void qe_reset(void);
+extern int par_io_of_config(struct device_node *np);
+#endif /* CONFIG_QUICC_ENGINE */
+
+/* ************************************************************************
+ *
+ * Setup the architecture
+ *
+ */
+static void __init mpc8360_sys_setup_arch(void)
+{
+ struct device_node *np;
+
+#ifdef CONFIG_QUICC_ENGINE
+ u8 *bcsr_regs;
+#endif
+
+ if (ppc_md.progress)
+ ppc_md.progress("mpc8360_sys_setup_arch()", 0);
+
+ np = of_find_node_by_type(NULL, "cpu");
+ if (np != 0) {
+ unsigned int *fp =
+ (int *)get_property(np, "clock-frequency", NULL);
+ if (fp != 0)
+ loops_per_jiffy = *fp / HZ;
+ else
+ loops_per_jiffy = 50000000 / HZ;
+ of_node_put(np);
+ }
+#ifdef CONFIG_PCI
+ for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;)
+ add_bridge(np);
+
+ ppc_md.pci_swizzle = common_swizzle;
+ ppc_md.pci_exclude_device = mpc83xx_exclude_device;
+#endif
+
+#ifdef CONFIG_QUICC_ENGINE
+ qe_reset();
+
+ for (np = NULL; (np = of_find_node_by_name(np, "ucc")) != NULL;)
+ par_io_of_config(np);
+
+ /* Reset the Ethernet PHY */
+ bcsr_regs = (u8 *) ioremap(BCSR_PHYS_ADDR, BCSR_SIZE);
+ bcsr_regs[9] &= ~0x20;
+ udelay(1000);
+ bcsr_regs[9] |= 0x20;
+ iounmap(bcsr_regs);
+
+#endif /* CONFIG_QUICC_ENGINE */
+
+#ifdef CONFIG_BLK_DEV_INITRD
+ if (initrd_start)
+ ROOT_DEV = Root_RAM0;
+ else
+#endif
+#ifdef CONFIG_ROOT_NFS
+ ROOT_DEV = Root_NFS;
+#else
+ ROOT_DEV = Root_HDA1;
+#endif
+}
+
+void __init mpc8360_sys_init_IRQ(void)
+{
+ u8 senses[8] = {
+ 0, /* EXT 0 */
+ IRQ_SENSE_LEVEL, /* EXT 1 */
+ IRQ_SENSE_LEVEL, /* EXT 2 */
+ 0, /* EXT 3 */
+#ifdef CONFIG_PCI
+ IRQ_SENSE_LEVEL, /* EXT 4 */
+ IRQ_SENSE_LEVEL, /* EXT 5 */
+ IRQ_SENSE_LEVEL, /* EXT 6 */
+ IRQ_SENSE_LEVEL, /* EXT 7 */
+#else
+ 0, /* EXT 4 */
+ 0, /* EXT 5 */
+ 0, /* EXT 6 */
+ 0, /* EXT 7 */
+#endif
+ };
+
+ ipic_init(get_immrbase() + 0x00700, 0, 0, senses, 8);
+
+ /* Initialize the default interrupt mapping priorities,
+ * in case the boot rom changed something on us.
+ */
+ ipic_set_default_priority();
+
+#ifdef CONFIG_QUICC_ENGINE
+ qe_ic_init(get_qe_base() + 0x00000080,
+ (QE_IC_LOW_SIGNAL | QE_IC_HIGH_SIGNAL), QE_IRQ_OFFSET);
+#endif /* CONFIG_QUICC_ENGINE */
+}
+
+#if defined(CONFIG_I2C_MPC) && defined(CONFIG_SENSORS_DS1374)
+extern ulong ds1374_get_rtc_time(void);
+extern int ds1374_set_rtc_time(ulong);
+
+static int __init mpc8360_rtc_hookup(void)
+{
+ struct timespec tv;
+
+ ppc_md.get_rtc_time = ds1374_get_rtc_time;
+ ppc_md.set_rtc_time = ds1374_set_rtc_time;
+
+ tv.tv_nsec = 0;
+ tv.tv_sec = (ppc_md.get_rtc_time) ();
+ do_settimeofday(&tv);
+
+ return 0;
+}
+
+late_initcall(mpc8360_rtc_hookup);
+#endif
+
+/*
+ * Called very early, MMU is off, device-tree isn't unflattened
+ */
+static int __init mpc8360_sys_probe(void)
+{
+ char *model = of_get_flat_dt_prop(of_get_flat_dt_root(),
+ "model", NULL);
+ if (model == NULL)
+ return 0;
+ if (strcmp(model, "MPC8360EPB"))
+ return 0;
+
+ DBG("MPC8360EMDS-PB found\n");
+
+ return 1;
+}
+
+define_machine(mpc8360_sys) {
+ .name = "MPC8360E PB",
+ .probe = mpc8360_sys_probe,
+ .setup_arch = mpc8360_sys_setup_arch,
+ .init_IRQ = mpc8360_sys_init_IRQ,
+ .get_irq = ipic_get_irq,
+ .restart = mpc83xx_restart,
+ .time_init = mpc83xx_time_init,
+ .calibrate_decr = generic_calibrate_decr,
+ .progress = udbg_progress,
+};
diff --git a/arch/powerpc/platforms/83xx/mpc8360e_pb.h b/arch/powerpc/platforms/83xx/mpc8360e_pb.h
new file mode 100644
index 0000000..4243f4a
--- /dev/null
+++ b/arch/powerpc/platforms/83xx/mpc8360e_pb.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (C) Freescale Semicondutor, Inc. 2006. All rights reserved.
+ *
+ * Author: Li Yang <LeoLi@freescale.com>
+ * Yin Olivia <Hong-hua.Yin@freescale.com>
+ *
+ * Description:
+ * MPC8360E MDS PB board specific header.
+ *
+ * Changelog:
+ * Jun 21, 2006 Initial version
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ */
+
+#ifndef __MACH_MPC83XX_SYS_H__
+#define __MACH_MPC83XX_SYS_H__
+
+#define BCSR_PHYS_ADDR ((uint)0xf8000000)
+#define BCSR_SIZE ((uint)(32 * 1024))
+
+#define PIRQA MPC83xx_IRQ_EXT4
+#define PIRQB MPC83xx_IRQ_EXT5
+#define PIRQC MPC83xx_IRQ_EXT6
+#define PIRQD MPC83xx_IRQ_EXT7
+
+#endif /* __MACH_MPC83XX_SYS_H__ */
^ permalink raw reply related
* [PATCH 2/7] mtd: Add map file for mpc83xx boards
From: Li Yang-r58472 @ 2006-06-28 14:23 UTC (permalink / raw)
To: 'dwmw2@infradead.org'
Cc: Phillips Kim-R1AAHA, Yin Olivia-r63875,
'linux-kernel@vger.kernel.org', linuxppc-dev,
'linux-mtd@lists.infradead.org', Chu hanjin-r52514
Flash mapping file for MPC83xx MDS platforms.
Signed-off-by: Yin Olivia <hong-hua.yin@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
---
drivers/mtd/maps/Kconfig | 6 +
drivers/mtd/maps/Makefile | 1
drivers/mtd/maps/mpc83xx_flash.c | 154 ++++++++++++++++++++++++++++++++++++++
3 files changed, 161 insertions(+), 0 deletions(-)
diff --git a/drivers/mtd/maps/Kconfig b/drivers/mtd/maps/Kconfig
index 7abd7fe..eac049e 100644
--- a/drivers/mtd/maps/Kconfig
+++ b/drivers/mtd/maps/Kconfig
@@ -631,5 +631,11 @@ config MTD_PLATRAM
This selection automatically selects the map_ram driver.
+config MTD_MPC83xx
+ tristate "CFI Flash device map on MPC83xx MDS support"
+ depends on 83xx && MTD_CFI && MTD_PARTITIONS
+ help
+ Freescale MPC83xx board uses CFI compliant flash.
+
endmenu
diff --git a/drivers/mtd/maps/Makefile b/drivers/mtd/maps/Makefile
index ab71f17..f0f8afd 100644
--- a/drivers/mtd/maps/Makefile
+++ b/drivers/mtd/maps/Makefile
@@ -71,3 +71,4 @@ obj-$(CONFIG_MTD_PLATRAM) += plat-ram.o
obj-$(CONFIG_MTD_OMAP_NOR) += omap_nor.o
obj-$(CONFIG_MTD_MTX1) += mtx-1_flash.o
obj-$(CONFIG_MTD_TQM834x) += tqm834x.o
+obj-$(CONFIG_MTD_MPC83xx) += mpc83xx_flash.o
diff --git a/drivers/mtd/maps/mpc83xx_flash.c b/drivers/mtd/maps/mpc83xx_flash.c
new file mode 100644
index 0000000..84f058a
--- /dev/null
+++ b/drivers/mtd/maps/mpc83xx_flash.c
@@ -0,0 +1,154 @@
+/*
+ * Handle mapping of the flash on MPC83xx board
+ *
+ * Copyright (C) 2005 Freescale semicondutor
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <asm/io.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/map.h>
+#include <linux/mtd/partitions.h>
+
+
+/* MPC8349MDS flash layout
+ * 0 : 0xFE00 0000 - 0xFE01 FFFF : HRCW (128KB)
+ * 1 : 0xFE02 0000 - 0xFE5F FFFF : JFFS2 file system (5.875MB)
+ * 2 : 0xFE60 0000 - 0xFE6F FFFF : Kernel (1MB)
+ * 3 : 0xFE70 0000 - 0xFE7F FFFF : U-Boot (1MB)
+ */
+#ifdef CONFIG_MPC834x
+#define WINDOW_ADDR 0xFE000000
+#define WINDOW_SIZE 0x00800000
+#endif
+
+/* MPC8360EPB flash layout
+ * 0 : 0xFE00 0000 - 0xFE01 FFFF : HRCW (128KB)
+ * 1 : 0xFE02 0000 - 0xFE8F FFFF : JFFS2 file system (8.875MB)
+ * 2 : 0xFE90 0000 - 0xFECF FFFF : Ramdisk file system (4MB)
+ * 3 : 0xFED0 0000 - 0xFEEF FFFF : Kernel (2MB)
+ * 4 : 0xFEF0 0000 - 0xFEFF FFFF : U-Boot (1MB)
+ */
+#ifdef CONFIG_MPC8360E_PB
+#define WINDOW_ADDR 0xFE000000
+#define WINDOW_SIZE 0x01000000
+#endif
+
+/* partition_info gives details on the logical partitions that the split the
+ * single flash device into. If the size if zero we use up to the end of the
+ * device. */
+static struct mtd_partition partition_info[]={
+ {
+ .name = "HRCW",
+ .offset = 0,
+ .size = 0x020000,
+ .mask_flags = MTD_WRITEABLE
+ },
+ {
+ .name = "JFFS2",
+ .offset = MTDPART_OFS_APPEND,
+#ifdef CONFIG_MPC834x
+ .size = 0x5E0000
+#endif
+#ifdef CONFIG_MPC8360E_PB
+ .size = 0x8E0000
+#endif
+ },
+#ifdef CONFIG_MPC8360E_PB
+ {
+ .name = "Ramdisk",
+ .offset = MTDPART_OFS_APPEND,
+ .size = 0x400000
+ },
+#endif
+ {
+ .name = "Kernel",
+ .offset = MTDPART_OFS_APPEND,
+#ifdef CONFIG_MPC834x
+ .size = 0x100000
+#endif
+#ifdef CONFIG_MPC8360E_PB
+ .size = 0x200000
+#endif
+ },
+ {
+ .name = "U-Boot",
+ .offset = MTDPART_OFS_APPEND,
+ .size = 0x100000,
+ .mask_flags = MTD_WRITEABLE
+ }
+};
+
+#define PARTITION_NUM (sizeof(partition_info)/sizeof(struct mtd_partition))
+
+static struct mtd_info *mymtd;
+
+
+struct map_info mpc83xx_map = {
+#ifdef CONFIG_MPC834x
+ .name = "MPC8349MDS Flash Map Info",
+#endif
+#ifdef CONFIG_MPC8360E_PB
+ .name = "MPC8360E PB Flash Map Info",
+#endif
+ .size = WINDOW_SIZE,
+ .phys = WINDOW_ADDR,
+ .bankwidth = 2,
+};
+
+int __init init_mpc83xx_mtd(void)
+{
+ char *board;
+#ifdef CONFIG_MPC834x
+ board = "MPC8349MDS";
+#endif
+#ifdef CONFIG_MPC8360E_PB
+ board = "MPC8360E PB";
+#endif
+ printk(KERN_NOTICE "%s flash device: %x at %x Partition number %d\n",
+ board,WINDOW_SIZE, WINDOW_ADDR, PARTITION_NUM);
+ mpc83xx_map.virt = ioremap(WINDOW_ADDR, WINDOW_SIZE);
+
+ if (!mpc83xx_map.virt) {
+ printk("Failed to ioremap\n");
+ return -EIO;
+ }
+ simple_map_init(&mpc83xx_map);
+
+ mymtd = do_map_probe("cfi_probe", &mpc83xx_map);
+ if (mymtd) {
+ mymtd->owner = THIS_MODULE;
+ add_mtd_partitions(mymtd, partition_info, PARTITION_NUM);
+ printk(KERN_NOTICE "%s flash device initialized\n", board);
+ return 0;
+ }
+
+ iounmap((void *)mpc83xx_map.virt);
+ return -ENXIO;
+}
+
+static void __exit cleanup_mpc83xx_mtd(void)
+{
+ if (mymtd) {
+ del_mtd_device(mymtd);
+ map_destroy(mymtd);
+ }
+ if (mpc83xx_map.virt) {
+ iounmap((void *)mpc83xx_map.virt);
+ mpc83xx_map.virt = 0;
+ }
+}
+
+module_init(init_mpc83xx_mtd);
+module_exit(cleanup_mpc83xx_mtd);
+
+MODULE_AUTHOR("FSL");
+MODULE_DESCRIPTION("MTD map driver for Freescale MPC83xx board");
+MODULE_LICENSE("GPL");
^ permalink raw reply related
* [PATCH 3/7] powerpc: Add QE library qe_lib--common files
From: Li Yang-r58472 @ 2006-06-28 14:23 UTC (permalink / raw)
To: 'Paul Mackerras'
Cc: Gridish Shlomi-RM96313, linuxppc-dev, Phillips Kim-R1AAHA,
'linux-kernel@vger.kernel.org', Chu hanjin-r52514
Signed-off-by: Shlomi Gridish <gridish@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
---
arch/powerpc/Kconfig | 12
arch/powerpc/sysdev/Makefile | 1
arch/powerpc/sysdev/ipic.c | 2
arch/powerpc/sysdev/qe_lib/Kconfig | 315 +++++++++++++
arch/powerpc/sysdev/qe_lib/Makefile | 8
arch/powerpc/sysdev/qe_lib/mm.c | 770 ++++++++++++++++++++++++++++++++
arch/powerpc/sysdev/qe_lib/mm.h | 6
arch/powerpc/sysdev/qe_lib/qe.c | 181 ++++++++
arch/powerpc/sysdev/qe_lib/qe_common.c | 401 +++++++++++++++++
arch/powerpc/sysdev/qe_lib/qe_ic.c | 487 ++++++++++++++++++++
arch/powerpc/sysdev/qe_lib/qe_ic.h | 83 +++
arch/powerpc/sysdev/qe_lib/qe_io.c | 275 +++++++++++
12 files changed, 2541 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 6729c98..6d4fc0b 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -334,6 +334,16 @@ config APUS
<http://linux-apus.sourceforge.net/>.
endchoice
+config QUICC_ENGINE
+ bool
+ depends on MPC836x
+ default y
+ help
+ The QE(QUICC Engine) is a new generation of coprocessor on
+ Freescale embedded CPUs(like CPM in older chips). Selecting
+ this option means that you wish to build a kernel for a machine
+ with QE coprocessor on it.
+
config PPC_PSERIES
depends on PPC_MULTIPLATFORM && PPC64
bool " IBM pSeries & new (POWER5-based) iSeries"
@@ -993,6 +1003,8 @@ # XXX source "arch/ppc/8xx_io/Kconfig"
# XXX source "arch/ppc/8260_io/Kconfig"
+source "arch/powerpc/sysdev/qe_lib/Kconfig"
+
source "arch/powerpc/platforms/iseries/Kconfig"
source "lib/Kconfig"
diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile
index 4c2b356..cd1d5cc 100644
--- a/arch/powerpc/sysdev/Makefile
+++ b/arch/powerpc/sysdev/Makefile
@@ -8,3 +8,4 @@ obj-$(CONFIG_U3_DART) += dart_iommu.o
obj-$(CONFIG_MMIO_NVRAM) += mmio_nvram.o
obj-$(CONFIG_PPC_83xx) += ipic.o
obj-$(CONFIG_FSL_SOC) += fsl_soc.o
+obj-$(CONFIG_QUICC_ENGINE) += qe_lib/
diff --git a/arch/powerpc/sysdev/ipic.c b/arch/powerpc/sysdev/ipic.c
index 8f01e0f..dbeccba 100644
--- a/arch/powerpc/sysdev/ipic.c
+++ b/arch/powerpc/sysdev/ipic.c
@@ -537,12 +537,14 @@ void ipic_set_highest_priority(unsigned
void ipic_set_default_priority(void)
{
+#ifdef CONFIG_MPC834x
ipic_set_priority(MPC83xx_IRQ_TSEC1_TX, 0);
ipic_set_priority(MPC83xx_IRQ_TSEC1_RX, 1);
ipic_set_priority(MPC83xx_IRQ_TSEC1_ERROR, 2);
ipic_set_priority(MPC83xx_IRQ_TSEC2_TX, 3);
ipic_set_priority(MPC83xx_IRQ_TSEC2_RX, 4);
ipic_set_priority(MPC83xx_IRQ_TSEC2_ERROR, 5);
+#endif
ipic_set_priority(MPC83xx_IRQ_USB2_DR, 6);
ipic_set_priority(MPC83xx_IRQ_USB2_MPH, 7);
diff --git a/arch/powerpc/sysdev/qe_lib/Kconfig b/arch/powerpc/sysdev/qe_lib/Kconfig
new file mode 100644
index 0000000..6105237
--- /dev/null
+++ b/arch/powerpc/sysdev/qe_lib/Kconfig
@@ -0,0 +1,315 @@
+#
+# QE Communication options
+#
+
+menu "QE Options"
+ depends on QUICC_ENGINE
+
+config UCC1
+ bool "Enable QE UCC1"
+
+choice
+ prompt "UCC1 speed selection"
+ depends on UCC1
+ default UCC1_SLOW
+
+ config UCC1_SLOW
+ bool "UCC1 is slow"
+ config UCC1_FAST
+ bool "UCC1 is fast"
+endchoice
+
+menu "UCC1 Protocols options"
+ depends on UCC1
+
+ choice
+ prompt "UCC1 Slow Protocols selection"
+ depends on UCC1_SLOW
+ default UCC1_UART
+
+ config UCC1_UART
+ bool "UCC1 is UART"
+ endchoice
+
+ choice
+ prompt "UCC1 Fast Protocols selection"
+ depends on UCC1_FAST
+ default UCC1_GETH
+
+ config UCC1_GETH
+ bool "UCC1 is GETH"
+ endchoice
+endmenu
+
+config UCC2
+ bool "Enable QE UCC2"
+
+choice
+ prompt "UCC2 speed selection"
+ depends on UCC2
+ default UCC2_SLOW
+
+ config UCC2_SLOW
+ bool "UCC2 is slow"
+ config UCC2_FAST
+ bool "UCC2 is fast"
+endchoice
+
+menu "UCC2 Protocols options"
+ depends on UCC2
+
+ choice
+ prompt "UCC2 Slow Protocols selection"
+ depends on UCC2_SLOW
+ default UCC2_UART
+
+ config UCC2_UART
+ bool "UCC2 is UART"
+ endchoice
+
+ choice
+ prompt "UCC2 Fast Protocols selection"
+ depends on UCC2_FAST
+ default UCC2_GETH
+
+ config UCC2_GETH
+ bool "UCC2 is GETH"
+ endchoice
+endmenu
+
+config UCC3
+ bool "Enable QE UCC3"
+
+choice
+ prompt "UCC3 speed selection"
+ depends on UCC3
+ default UCC3_SLOW
+
+ config UCC3_SLOW
+ bool "UCC3 is slow"
+ config UCC3_FAST
+ bool "UCC3 is fast"
+endchoice
+
+menu "UCC3 Protocols options"
+ depends on UCC3
+
+ choice
+ prompt "UCC3 Slow Protocols selection"
+ depends on UCC3_SLOW
+ default UCC3_UART
+
+ config UCC3_UART
+ bool "UCC3 is UART"
+ endchoice
+
+ config UCC3_GETH
+ depends on UCC3_FAST
+ bool "UCC3 is GETH"
+
+ config UCC3_ATM
+ depends on UCC3_FAST && !UCC3_GETH
+ tristate "UCC3 is ATM"
+endmenu
+
+config UCC4
+ bool "Enable QE UCC4"
+
+choice
+ prompt "UCC4 speed selection"
+ depends on UCC4
+ default UCC4_SLOW
+
+ config UCC4_SLOW
+ bool "UCC4 is slow"
+ config UCC4_FAST
+ bool "UCC4 is fast"
+endchoice
+
+menu "UCC4 Protocols options"
+ depends on UCC4
+
+ choice
+ prompt "UCC4 Slow Protocols selection"
+ depends on UCC4_SLOW
+ default UCC4_UART
+
+ config UCC4_UART
+ bool "UCC4 is UART"
+ endchoice
+
+ choice
+ prompt "UCC4 Fast Protocols selection"
+ depends on UCC4_FAST
+ default UCC4_GETH
+
+ config UCC4_GETH
+ bool "UCC4 is GETH"
+ endchoice
+endmenu
+
+config UCC5
+ bool "Enable QE UCC5"
+
+choice
+ prompt "UCC5 speed selection"
+ depends on UCC5
+ default UCC5_SLOW
+
+ config UCC5_SLOW
+ bool "UCC5 is slow"
+ config UCC5_FAST
+ bool "UCC5 is fast"
+endchoice
+
+menu "UCC5 Protocols options"
+ depends on UCC5
+
+ choice
+ prompt "UCC5 Slow Protocols selection"
+ depends on UCC5_SLOW
+ default UCC5_UART
+
+ config UCC5_UART
+ bool "UCC5 is UART"
+ endchoice
+
+ choice
+ prompt "UCC5 Fast Protocols selection"
+ depends on UCC5_FAST
+ default UCC5_GETH
+
+ config UCC5_GETH
+ bool "UCC5 is GETH"
+ endchoice
+endmenu
+
+config UCC6
+ bool "Enable QE UCC6"
+
+choice
+ prompt "UCC6 speed selection"
+ depends on UCC6
+ default UCC6_SLOW
+
+ config UCC6_SLOW
+ bool "UCC6 is slow"
+ config UCC6_FAST
+ bool "UCC6 is fast"
+endchoice
+
+menu "UCC6 Protocols options"
+ depends on UCC6
+
+ choice
+ prompt "UCC6 Slow Protocols selection"
+ depends on UCC6_SLOW
+ default UCC6_UART
+
+ config UCC6_UART
+ bool "UCC6 is UART"
+ endchoice
+
+ choice
+ prompt "UCC6 Fast Protocols selection"
+ depends on UCC6_FAST
+ default UCC6_GETH
+
+ config UCC6_GETH
+ bool "UCC6 is GETH"
+ endchoice
+endmenu
+
+config UCC7
+ bool "Enable QE UCC7"
+
+choice
+ prompt "UCC7 speed selection"
+ depends on UCC7
+ default UCC7_SLOW
+
+ config UCC7_SLOW
+ bool "UCC7 is slow"
+ config UCC7_FAST
+ bool "UCC7 is fast"
+endchoice
+
+menu "UCC7 Protocols options"
+ depends on UCC7
+
+ choice
+ prompt "UCC7 Slow Protocols selection"
+ depends on UCC7_SLOW
+ default UCC7_UART
+
+ config UCC7_UART
+ bool "UCC7 is UART"
+ endchoice
+
+ choice
+ prompt "UCC7 Fast Protocols selection"
+ depends on UCC7_FAST
+ default UCC7_GETH
+
+ config UCC7_GETH
+ bool "UCC7 is GETH"
+ endchoice
+endmenu
+
+config UCC8
+ bool "Enable QE UCC8"
+
+choice
+ prompt "UCC8 speed selection"
+ depends on UCC8
+ default UCC8_SLOW
+
+ config UCC8_SLOW
+ bool "UCC8 is slow"
+ config UCC8_FAST
+ bool "UCC8 is fast"
+endchoice
+
+menu "UCC8 Protocols options"
+ depends on UCC8
+
+ choice
+ prompt "UCC8 Slow Protocols selection"
+ depends on UCC8_SLOW
+ default UCC8_UART
+
+ config UCC8_UART
+ bool "UCC8 is UART"
+ endchoice
+
+ choice
+ prompt "UCC8 Fast Protocols selection"
+ depends on UCC8_FAST
+ default UCC8_GETH
+
+ config UCC8_GETH
+ bool "UCC8 is GETH"
+ endchoice
+endmenu
+
+config UCC
+ depends on UCC1 || UCC2 || UCC3 || UCC4 || UCC5 || UCC6 || UCC7 || UCC8
+ default y
+ bool
+
+config UCC_SLOW
+ depends on UCC1_SLOW || UCC2_SLOW || UCC3_SLOW || UCC4_SLOW || UCC5_SLOW || UCC6_SLOW || UCC7_SLOW || UCC8_SLOW
+ default y
+ bool
+
+config UCC_FAST
+ depends on UCC1_FAST || UCC2_FAST || UCC3_FAST || UCC4_FAST || UCC5_FAST || UCC6_FAST || UCC7_FAST || UCC8_FAST
+ default y
+ bool
+
+config UCC_GETH_CONF
+ depends on UCC1_GETH || UCC2_GETH || UCC3_GETH || UCC4_GETH || UCC5_GETH || UCC6_GETH || UCC7_GETH || UCC8_GETH
+ default y
+ bool
+endmenu
+
diff --git a/arch/powerpc/sysdev/qe_lib/Makefile b/arch/powerpc/sysdev/qe_lib/Makefile
new file mode 100644
index 0000000..c04a70c
--- /dev/null
+++ b/arch/powerpc/sysdev/qe_lib/Makefile
@@ -0,0 +1,8 @@
+#
+# Makefile for the linux ppc-specific parts of QE
+#
+obj-$(CONFIG_QUICC_ENGINE)+= qe_common.o mm.o qe.o qe_ic.o qe_io.o
+
+obj-$(CONFIG_UCC) += ucc.o
+obj-$(CONFIG_UCC_SLOW) += ucc_slow.o
+obj-$(CONFIG_UCC_FAST) += ucc_fast.o ucc_slow.o
diff --git a/arch/powerpc/sysdev/qe_lib/mm.c b/arch/powerpc/sysdev/qe_lib/mm.c
new file mode 100644
index 0000000..58984ba
--- /dev/null
+++ b/arch/powerpc/sysdev/qe_lib/mm.c
@@ -0,0 +1,770 @@
+/*
+ * Copyright (C) Freescale Semicondutor, Inc. 2006. All rights reserved.
+ *
+ * Author: Shlomi Gridish <gridish@freescale.com>
+ *
+ * Description:
+ * QE Memory Manager.
+ *
+ * Changelog:
+ * Jun 28, 2006 Li Yang <LeoLi@freescale.com>
+ * - Reorganized as qe_lib
+ * - Merged to powerpc arch; add device tree support
+ * - Style fixes
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+#include <linux/errno.h>
+#include <linux/sched.h>
+#include <linux/kernel.h>
+#include <linux/param.h>
+#include <linux/string.h>
+#include <linux/mm.h>
+#include <linux/interrupt.h>
+#include <linux/bootmem.h>
+#include <linux/module.h>
+#include <asm/irq.h>
+#include <asm/page.h>
+#include <asm/pgtable.h>
+
+#include "mm.h"
+
+#define MAX_ALIGNMENT 20
+#define MAX_NAME_LEN 50
+
+#define MAKE_ALIGNED(adr, align) ( ((u32)adr + (align - 1)) & (~(align - 1)) )
+
+/* mem_block_t data stucutre defines parameters of the Memory Block */
+typedef struct mem_block {
+ struct mem_block *next; /* Pointer to the next memory block */
+
+ u32 base; /* base address of the memory block */
+ u32 end; /* end address of the memory block */
+} mem_block_t;
+
+/* free_block_t data stucutre defines parameters of the Free Block */
+typedef struct free_block {
+ struct free_block *next; /* Pointer to the next free block */
+
+ u32 base; /* base address of the block */
+ u32 end; /* end address of the block */
+} free_block_t;
+
+/* busy_block_t data stucutre defines parameters of the Busy Block */
+typedef struct busy_block {
+ struct busy_block *next; /* Pointer to the next free block */
+
+ u32 base; /* base address of the block */
+ u32 end; /* end address of the block */
+ char name[MAX_NAME_LEN];
+} busy_block_t;
+
+/* mm_t data structure defines parameters of the MM object */
+typedef struct mm {
+ mem_block_t *mem_blocks; /* List of memory blocks (Memory list) */
+ busy_block_t *busy_blocks; /* List of busy blocks (Busy list) */
+ free_block_t *free_blocks[MAX_ALIGNMENT + 1];/* align lists of free
+ blocks (Free lists) */
+} mm_t;
+
+/**********************************************************************
+ * MM internal routines set *
+ **********************************************************************/
+
+/****************************************************************
+ * Routine: mem_block_init
+ *
+ * Description:
+ * Initializes a new memory block of "size" bytes and started
+ * from "base" address.
+ *
+ * Arguments:
+ * mem_blk- handle to the mem_blk object
+ * base - base address of the memory block
+ * size - size of the memory block
+ *
+ * Return value:
+ * 0 is returned on success. E_NOMEMORY is returned
+ * if can't allocate memory for mem_blk object.
+ ****************************************************************/
+static int mem_block_init(void **mem_blk, u32 base, u32 size)
+{
+ mem_block_t *p_mem_blk;
+
+ p_mem_blk = (mem_block_t *) kmalloc(sizeof(mem_block_t), GFP_KERNEL);
+ if (!p_mem_blk)
+ return -ENOMEM;
+
+ p_mem_blk->base = base;
+ p_mem_blk->end = base + size;
+ p_mem_blk->next = 0;
+
+ *mem_blk = p_mem_blk;
+
+ return (0);
+}
+
+/****************************************************************
+ * Routine: free_block_init
+ *
+ * Description:
+ * Initializes a new free block of of "size" bytes and
+ * started from "base" address.
+ *
+ * Arguments:
+ * FreeBlock - handle to the FreeBlock object
+ * base - base address of the free block
+ * size - size of the free block
+ *
+ * Return value:
+ * 0 is returned on success. E_NOMEMORY is returned
+ * if can't allocate memory for a free block.
+ ****************************************************************/
+static int free_block_init(void **FreeBlock, u32 base, u32 size)
+{
+ free_block_t *p_free_blk;
+
+ p_free_blk = (free_block_t *) kmalloc(sizeof(free_block_t), GFP_KERNEL);
+ if (!p_free_blk)
+ return -ENOMEM;
+
+ p_free_blk->base = base;
+ p_free_blk->end = base + size;
+ p_free_blk->next = 0;
+
+ *FreeBlock = p_free_blk;
+
+ return (0);
+}
+
+/****************************************************************
+ * Routine: busy_block_init
+ *
+ * Description:
+ * Initializes a new busy block of "size" bytes and started
+ * rom "base" address. Each busy block has a name that
+ * specified the purpose of the memory allocation.
+ *
+ * Arguments:
+ * BusyBlock - handle to the BusyBlock object
+ * base - base address of the busy block
+ * size - size of the busy block
+ * name - name that specified the busy block
+ *
+ * Return value:
+ * 0 is returned on success. E_NOMEMORY is returned
+ * if can't allocate memory for busy block.
+ ****************************************************************/
+static int busy_block_init(void **BusyBlock, u32 base, u32 size, char *name)
+{
+ busy_block_t *p_busy_blk;
+ int n, NameLen;
+
+ p_busy_blk = (busy_block_t *) kmalloc(sizeof(busy_block_t), GFP_KERNEL);
+ if (!p_busy_blk)
+ return -ENOMEM;
+
+ p_busy_blk->base = base;
+ p_busy_blk->end = base + size;
+ NameLen = (int)strlen(name);
+ n = (NameLen > MAX_NAME_LEN - 1) ? MAX_NAME_LEN - 1 : NameLen;
+ strncpy(p_busy_blk->name, name, (u32) n);
+ p_busy_blk->name[n] = '\0';
+ p_busy_blk->next = 0;
+
+ *BusyBlock = p_busy_blk;
+
+ return (0);
+}
+
+/****************************************************************
+ * Routine: add_free
+ *
+ * Description:
+ * Adds a new free block to the free lists. It updates each
+ * free list to include a new free block.
+ * Note, that all free block in each free list are ordered
+ * by their base address.
+ *
+ * Arguments:
+ * p_mm - pointer to the MM object
+ * base - base address of a given free block
+ * end - end address of a given free block
+ *
+ * Return value:
+ *
+ *
+ ****************************************************************/
+static int add_free(mm_t * p_mm, u32 base, u32 end)
+{
+ free_block_t *p_prev_blk, *p_curr_blk, *p_new_blk;
+ u32 align;
+ int i;
+ u32 align_base;
+
+ /* Updates free lists to include a just released block */
+ for (i = 0; i <= MAX_ALIGNMENT; i++) {
+ p_prev_blk = p_new_blk = 0;
+ p_curr_blk = p_mm->free_blocks[i];
+
+ align = (u32) (0x1 << i);
+ align_base = MAKE_ALIGNED(base, align);
+
+ /* Goes to the next free list if there is no block to free */
+ if (align_base >= end)
+ continue;
+
+ /* Looks for a free block that should be updated */
+ while (p_curr_blk) {
+ if (align_base <= p_curr_blk->end) {
+ if (end > p_curr_blk->end) {
+ free_block_t *p_NextB;
+ while (p_curr_blk->next
+ && end > p_curr_blk->next->end) {
+ p_NextB = p_curr_blk->next;
+ p_curr_blk->next =
+ p_curr_blk->next->next;
+ kfree(p_NextB);
+ }
+
+ p_NextB = p_curr_blk->next;
+ if (!p_NextB
+ || (p_NextB
+ && end < p_NextB->base)) {
+ p_curr_blk->end = end;
+ } else {
+ p_curr_blk->end = p_NextB->end;
+ p_curr_blk->next =
+ p_NextB->next;
+ kfree(p_NextB);
+ }
+ } else if (end < p_curr_blk->base
+ && ((end - align_base) >= align)) {
+ if (free_block_init
+ ((void *)&p_new_blk, align_base,
+ end - align_base) != 0)
+ return -ENOMEM;
+ p_new_blk->next = p_curr_blk;
+ if (p_prev_blk)
+ p_prev_blk->next = p_new_blk;
+ else
+ p_mm->free_blocks[i] =
+ p_new_blk;
+ break;
+ }
+
+ if (align_base < p_curr_blk->base
+ && end >= p_curr_blk->base)
+ p_curr_blk->base = align_base;
+
+ /* if size of the free block is less then
+ * alignment deletes that free block from
+ * the free list. */
+ if ((p_curr_blk->end - p_curr_blk->base) <
+ align) {
+ if (p_prev_blk)
+ p_prev_blk->next =
+ p_curr_blk->next;
+ else
+ p_mm->free_blocks[i] =
+ p_curr_blk->next;
+ kfree(p_curr_blk);
+ }
+ break;
+ } else {
+ p_prev_blk = p_curr_blk;
+ p_curr_blk = p_curr_blk->next;
+ }
+ }
+
+ /* If no free block found to be updated, insert a new free block
+ * to the end of the free list. */
+ if (!p_curr_blk && ((end - base) % align == 0)) {
+ if (free_block_init
+ ((void *)&p_new_blk, align_base, end - base) != 0)
+ return -ENOMEM;
+ if (p_prev_blk)
+ p_prev_blk->next = p_new_blk;
+ else
+ p_mm->free_blocks[i] = p_new_blk;
+ }
+
+ /* Update boundaries of the new free block */
+ if (align == 1 && !p_new_blk) {
+ if (p_curr_blk && base > p_curr_blk->base)
+ base = p_curr_blk->base;
+ if (p_curr_blk && end < p_curr_blk->end)
+ end = p_curr_blk->end;
+ }
+ }
+
+ return (0);
+}
+
+/****************************************************************
+ * Routine: cut_free
+ *
+ * Description:
+ * Cuts a free block from hold_base to hold_end from the free lists.
+ * That is, it updates all free lists of the MM object do
+ * not include a block of memory from hold_base to hold_end.
+ * For each free lists it seek for a free block that holds
+ * either hold_base or hold_end. If such block is found it updates it.
+ *
+ * Arguments:
+ * p_mm - pointer to the MM object
+ * hold_base - base address of the allocated block
+ * hold_end - end address of the allocated block
+ *
+ * Return value:
+ * 0 is returned on success,
+ * otherwise returns an error code.
+ *
+ ****************************************************************/
+static int cut_free(mm_t * p_mm, u32 hold_base, u32 hold_end)
+{
+ free_block_t *p_prev_blk, *p_curr_blk, *p_new_blk;
+ u32 align_base, base, end, align;
+ int i;
+
+ for (i = 0; i <= MAX_ALIGNMENT; i++) {
+ p_prev_blk = p_new_blk = 0;
+ p_curr_blk = p_mm->free_blocks[i];
+
+ align = (u32) 0x1 << i;
+ align_base = MAKE_ALIGNED(hold_end, align);
+
+ while (p_curr_blk) {
+ base = p_curr_blk->base;
+ end = p_curr_blk->end;
+
+ if (hold_base <= base && hold_end <= end
+ && hold_end > base) {
+ if (align_base >= end
+ || (align_base < end
+ && (end - align_base) < align)) {
+ if (p_prev_blk)
+ p_prev_blk->next =
+ p_curr_blk->next;
+ else
+ p_mm->free_blocks[i] =
+ p_curr_blk->next;
+ kfree(p_curr_blk);
+ } else {
+ p_curr_blk->base = align_base;
+ }
+ break;
+ } else if (hold_base > base && hold_end <= end) {
+ if ((hold_base - base) >= align) {
+ if (align_base < end
+ && (end - align_base) >= align) {
+ if (free_block_init
+ ((void *)&p_new_blk,
+ align_base,
+ (end - align_base)) != 0)
+ return -ENOMEM;
+ p_new_blk->next =
+ p_curr_blk->next;
+ p_curr_blk->next = p_new_blk;
+ }
+ p_curr_blk->end = hold_base;
+ } else if (align_base < end
+ && (end - align_base) >= align) {
+ p_curr_blk->base = align_base;
+ } else {
+ if (p_prev_blk)
+ p_prev_blk->next =
+ p_curr_blk->next;
+ else
+ p_mm->free_blocks[i] =
+ p_curr_blk->next;
+ kfree(p_curr_blk);
+ }
+ break;
+ } else {
+ p_prev_blk = p_curr_blk;
+ p_curr_blk = p_curr_blk->next;
+ }
+ }
+ }
+
+ return (0);
+}
+
+/****************************************************************
+ * Routine: add_busy
+ *
+ * Description:
+ * Adds a new busy block to the list of busy blocks. Note,
+ * that all busy blocks are ordered by their base address in
+ * the busy list.
+ *
+ * Arguments:
+ * MM - handler to the MM object
+ * p_new_busy_blk - pointer to the a busy block
+ *
+ * Return value:
+ * None.
+ *
+ ****************************************************************/
+static void add_busy(mm_t * p_mm, busy_block_t * p_new_busy_blk)
+{
+ busy_block_t *p_cur_busy_blk, *p_prev_busy_blk;
+
+ /* finds a place of a new busy block in the list of busy blocks */
+ p_prev_busy_blk = 0;
+ p_cur_busy_blk = p_mm->busy_blocks;
+
+ while (p_cur_busy_blk && p_new_busy_blk->base > p_cur_busy_blk->base) {
+ p_prev_busy_blk = p_cur_busy_blk;
+ p_cur_busy_blk = p_cur_busy_blk->next;
+ }
+
+ /* insert the new busy block into the list of busy blocks */
+ if (p_cur_busy_blk)
+ p_new_busy_blk->next = p_cur_busy_blk;
+ if (p_prev_busy_blk)
+ p_prev_busy_blk->next = p_new_busy_blk;
+ else
+ p_mm->busy_blocks = p_new_busy_blk;
+
+}
+
+/****************************************************************
+ * Routine: get_greater_align
+ *
+ * Description:
+ * Allocates a block of memory according to the given size
+ * and the alignment. That routine is called from the mm_get
+ * routine if the required alignment is grater then MAX_ALIGNMENT.
+ * In that case, it goes over free blocks of 64 byte align list
+ * and checks if it has the required size of bytes of the required
+ * alignment. If no blocks found returns ILLEGAL_BASE.
+ * After the block is found and data is allocated, it calls
+ * the internal cut_free routine to update all free lists
+ * do not include a just allocated block. Of course, each
+ * free list contains a free blocks with the same alignment.
+ * It is also creates a busy block that holds
+ * information about an allocated block.
+ *
+ * Arguments:
+ * MM - handle to the MM object
+ * size - size of the MM
+ * align - index as a power of two defines
+ * a required alignment that is grater then 64.
+ * name - the name that specifies an allocated block.
+ *
+ * Return value:
+ * base address of an allocated block.
+ * ILLEGAL_BASE if can't allocate a block
+ *
+ ****************************************************************/
+static int get_greater_align(void *MM, u32 size, int align, char *name)
+{
+ mm_t *p_mm = (mm_t *) MM;
+ free_block_t *p_free_blk;
+ busy_block_t *p_new_busy_blk;
+ u32 hold_base, hold_end, align_base = 0;
+ u32 ret;
+
+ /* goes over free blocks of the 64 byte alignment list
+ * and look for a block of the suitable size and
+ * base address according to the alignment.
+ */
+ p_free_blk = p_mm->free_blocks[MAX_ALIGNMENT];
+
+ while (p_free_blk) {
+ align_base = MAKE_ALIGNED(p_free_blk->base, align);
+
+ /* the block is found if the aligned base inside the block
+ * and has the anough size.
+ */
+ if (align_base >= p_free_blk->base &&
+ align_base < p_free_blk->end &&
+ size <= (p_free_blk->end - align_base))
+ break;
+ else
+ p_free_blk = p_free_blk->next;
+ }
+
+ /* If such block isn't found */
+ if (!p_free_blk)
+ return -EBUSY;
+
+ hold_base = align_base;
+ hold_end = align_base + size;
+
+ /* init a new busy block */
+ if ((ret =
+ busy_block_init((void *)&p_new_busy_blk, hold_base, size,
+ name)) != 0)
+ return ret;
+
+ /* calls Update routine to update a lists of free blocks */
+ if ((ret = cut_free(MM, hold_base, hold_end)) != 0)
+ return ret;
+
+ /* insert the new busy block into the list of busy blocks */
+ add_busy(p_mm, p_new_busy_blk);
+
+ return (hold_base);
+}
+
+/**********************************************************************
+ * MM API routines set *
+ **********************************************************************/
+int mm_init(void **MM, u32 base, u32 size)
+{
+ mm_t *p_mm;
+ int i;
+ u32 new_base, new_size;
+
+ /* Initializes a new MM object */
+ p_mm = (mm_t *) kmalloc(sizeof(mm_t), GFP_KERNEL);
+ if (p_mm == 0)
+ return -ENOMEM;
+
+ /* initializes a new memory block */
+ if (mem_block_init((void *)&p_mm->mem_blocks, base, size) != 0)
+ return -ENOMEM;
+
+ /* A busy list is empty */
+ p_mm->busy_blocks = 0;
+
+ /*Initializes a new free block for each free list */
+ for (i = 0; i <= MAX_ALIGNMENT; i++) {
+ new_base = MAKE_ALIGNED(base, (0x1 << i));
+ new_size = size - (new_base - base);
+ if (free_block_init((void *)&p_mm->free_blocks[i],
+ new_base, new_size) != 0)
+ return -ENOMEM;
+ }
+
+ *MM = p_mm;
+
+ return (0);
+}
+
+EXPORT_SYMBOL(mm_init);
+
+void mm_free(void *MM)
+{
+ mm_t *p_mm = (mm_t *) MM;
+ mem_block_t *p_mem_blk;
+ busy_block_t *p_busy_blk;
+ free_block_t *p_free_blk;
+ void *p_blk;
+ int i;
+
+ if (!p_mm)
+ return;
+
+ /* release memory allocated for busy blocks */
+ p_busy_blk = p_mm->busy_blocks;
+ while (p_busy_blk) {
+ p_blk = p_busy_blk;
+ p_busy_blk = p_busy_blk->next;
+ kfree(p_blk);
+ }
+
+ /* release memory allocated for free blocks */
+ for (i = 0; i <= MAX_ALIGNMENT; i++) {
+ p_free_blk = p_mm->free_blocks[i];
+ while (p_free_blk) {
+ p_blk = p_free_blk;
+ p_free_blk = p_free_blk->next;
+ kfree(p_blk);
+ }
+ }
+
+ /* release memory allocated for memory blocks */
+ p_mem_blk = p_mm->mem_blocks;
+ while (p_mem_blk) {
+ p_blk = p_mem_blk;
+ p_mem_blk = p_mem_blk->next;
+ kfree(p_blk);
+ }
+
+ /* release memory allocated for MM object itself */
+ kfree(p_mm);
+}
+
+EXPORT_SYMBOL(mm_free);
+
+void *mm_get(void *MM, u32 size, int align, char *name)
+{
+ mm_t *p_mm = (mm_t *) MM;
+ free_block_t *p_free_blk;
+ busy_block_t *p_new_busy_blk;
+ u32 hold_base, hold_end;
+ u32 i = 0, j = (u32) align;
+ u32 ret;
+
+ if (!p_mm)
+ return ERR_PTR(-EINVAL);
+
+ /* checks that align value is grater then zero */
+ if (align == 0)
+ return ERR_PTR(-EINVAL);
+
+ /* checks if alignment is a power of two,
+ * if it correct and if the required size
+ * is multiple of the given alignment.
+ */
+ while ((j & 0x1) == 0) {
+ i++;
+ j = j >> 1;
+ }
+
+ /* if the given alignment isn't power of two, returns an error */
+ if (j != 1)
+ return ERR_PTR(-EINVAL);
+
+ if (i > MAX_ALIGNMENT)
+ return ERR_PTR(get_greater_align(MM, size, align, name));
+
+ /* look for a block of the size grater or equal to the
+ * required size.
+ */
+ p_free_blk = p_mm->free_blocks[i];
+ while (p_free_blk && (p_free_blk->end - p_free_blk->base) < size)
+ p_free_blk = p_free_blk->next;
+
+ /* If such block is found */
+ if (!p_free_blk)
+ return ERR_PTR(-ENOMEM);
+
+ hold_base = p_free_blk->base;
+ hold_end = hold_base + size;
+
+ /* init a new busy block */
+ if ((ret =
+ busy_block_init((void *)&p_new_busy_blk, hold_base, size,
+ name)) != 0)
+ return ERR_PTR(ret);
+
+ /* calls Update routine to update a lists of free blocks */
+ if ((ret = cut_free(MM, hold_base, hold_end)) != 0)
+ return ERR_PTR(ret);
+
+ /* insert the new busy block into the list of busy blocks */
+ add_busy(p_mm, p_new_busy_blk);
+
+ return (void *)(hold_base);
+}
+
+EXPORT_SYMBOL(mm_get);
+
+void *mm_get_force(void *MM, u32 base, u32 size, char *name)
+{
+ mm_t *p_mm = (mm_t *) MM;
+ free_block_t *p_free_blk;
+ busy_block_t *p_new_busy_blk;
+ int blk_is_free = 0;
+ u32 ret;
+
+ p_free_blk = p_mm->free_blocks[0];/* The biggest free blocks are in
+ the free list with alignment 1 */
+ while (p_free_blk) {
+ if (base >= p_free_blk->base
+ && (base + size) <= p_free_blk->end) {
+ blk_is_free = 1;
+ break;
+ } else
+ p_free_blk = p_free_blk->next;
+ }
+
+ if (!blk_is_free)
+ return ERR_PTR(-ENOMEM);
+
+ /* init a new busy block */
+ if ((ret =
+ busy_block_init((void *)&p_new_busy_blk, base, size, name)) != 0)
+ return ERR_PTR(ret);
+
+ /* calls Update routine to update a lists of free blocks */
+ if ((ret = cut_free(MM, base, base + size)) != 0)
+ return ERR_PTR(ret);
+
+ /* insert the new busy block into the list of busy blocks */
+ add_busy(p_mm, p_new_busy_blk);
+ return (void *)(base);
+}
+
+EXPORT_SYMBOL(mm_get_force);
+
+int mm_put(void *MM, u32 base)
+{
+ mm_t *p_mm = (mm_t *) MM;
+ busy_block_t *p_busy_blk, *p_prev_busy_blk;
+ u32 size;
+ u32 ret;
+
+ if (!p_mm)
+ return -EINVAL;
+
+ /* Look for a busy block that have the given base value.
+ * That block will be returned back to the memory.
+ */
+ p_prev_busy_blk = 0;
+ p_busy_blk = p_mm->busy_blocks;
+ while (p_busy_blk && base != p_busy_blk->base) {
+ p_prev_busy_blk = p_busy_blk;
+ p_busy_blk = p_busy_blk->next;
+ }
+
+ if (!p_busy_blk)
+ return -EINVAL;
+
+ if ((ret = add_free(p_mm, p_busy_blk->base, p_busy_blk->end)) != 0)
+ return ret;
+
+ /* removes a busy block form the list of busy blocks */
+ if (p_prev_busy_blk)
+ p_prev_busy_blk->next = p_busy_blk->next;
+ else
+ p_mm->busy_blocks = p_busy_blk->next;
+
+ size = p_busy_blk->end - p_busy_blk->base;
+
+ kfree(p_busy_blk);
+
+ return (0);
+}
+
+EXPORT_SYMBOL(mm_put);
+
+void mm_dump(void *MM)
+{
+ mm_t *p_mm = (mm_t *) MM;
+ free_block_t *p_free_blk;
+ busy_block_t *p_busy_blk;
+ int i;
+
+ p_busy_blk = p_mm->busy_blocks;
+ printk(KERN_INFO "List of busy blocks:\n");
+ while (p_busy_blk) {
+ printk(KERN_INFO "\t0x%08x: (%s: b=0x%08x, e=0x%08x)\n",
+ (u32) p_busy_blk, p_busy_blk->name, p_busy_blk->base,
+ p_busy_blk->end);
+ p_busy_blk = p_busy_blk->next;
+ }
+
+ printk(KERN_INFO "Lists of free blocks according to alignment:\n");
+ for (i = 0; i <= MAX_ALIGNMENT; i++) {
+ printk(KERN_INFO "%d alignment:\n", (0x1 << i));
+ p_free_blk = p_mm->free_blocks[i];
+ while (p_free_blk) {
+ printk(KERN_INFO "\t0x%08x: (b=0x%08x, e=0x%08x)\n",
+ (u32) p_free_blk, p_free_blk->base,
+ p_free_blk->end);
+ p_free_blk = p_free_blk->next;
+ }
+ printk(KERN_INFO "\n");
+ }
+}
+
+EXPORT_SYMBOL(mm_dump);
diff --git a/arch/powerpc/sysdev/qe_lib/mm.h b/arch/powerpc/sysdev/qe_lib/mm.h
new file mode 100644
index 0000000..ab30080
--- /dev/null
+++ b/arch/powerpc/sysdev/qe_lib/mm.h
@@ -0,0 +1,6 @@
+int mm_init ( void **MM, u32 base, u32 size );
+void mm_free (void * MM);
+void *mm_get ( void * MM, u32 size, int align, char* name );
+void *mm_get_force ( void * MM, u32 base, u32 size, char* name );
+int mm_put ( void * MM, u32 base );
+void mm_dump ( void * MM );
diff --git a/arch/powerpc/sysdev/qe_lib/qe.c b/arch/powerpc/sysdev/qe_lib/qe.c
new file mode 100644
index 0000000..0fbb54c
--- /dev/null
+++ b/arch/powerpc/sysdev/qe_lib/qe.c
@@ -0,0 +1,181 @@
+/*
+ * Copyright (C) Freescale Semicondutor, Inc. 2006. All rights reserved.
+ *
+ * Author: Li Yang <LeoLi@freescale.com>
+ *
+ * Description:
+ * FSL QE SOC setup.
+ *
+ * Changelog:
+ * Jun 21, 2006 Initial version
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/config.h>
+#include <linux/stddef.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/major.h>
+#include <linux/delay.h>
+#include <linux/irq.h>
+#include <linux/module.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/fsl_devices.h>
+
+#include <asm/system.h>
+#include <asm/atomic.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/prom.h>
+#include <sysdev/fsl_soc.h>
+#include <mm/mmu_decl.h>
+
+static phys_addr_t qebase = -1;
+
+phys_addr_t get_qe_base(void)
+{
+ struct device_node *qe;
+
+ if (qebase != -1)
+ return qebase;
+
+ qe = of_find_node_by_type(NULL, "qe");
+ if (qe) {
+ unsigned int size;
+ void *prop = get_property(qe, "reg", &size);
+ qebase = of_translate_address(qe, prop);
+ of_node_put(qe);
+ };
+
+ return qebase;
+}
+
+EXPORT_SYMBOL(get_qe_base);
+
+static int __init ucc_geth_of_init(void)
+{
+ struct device_node *np;
+ unsigned int i, ucc_num;
+ struct platform_device *ugeth_dev;
+ struct resource res;
+ int ret;
+
+ for (np = NULL, i = 0;
+ (np = of_find_compatible_node(np, "network", "ucc_geth")) != NULL;
+ i++) {
+ struct resource r[2];
+ struct device_node *phy, *mdio;
+ struct ucc_geth_platform_data ugeth_data;
+ unsigned int *id;
+ char *model;
+ void *mac_addr;
+ phandle *ph;
+
+ memset(r, 0, sizeof(r));
+ memset(&ugeth_data, 0, sizeof(ugeth_data));
+
+ ret = of_address_to_resource(np, 0, &r[0]);
+ if (ret)
+ goto err;
+
+ ugeth_data.phy_reg_addr = r[0].start;
+ r[1].start = np->intrs[0].line;
+ r[1].end = np->intrs[0].line;
+ r[1].flags = IORESOURCE_IRQ;
+
+ model = get_property(np, "model", NULL);
+ ucc_num = *((u32 *) get_property(np, "device-id", NULL));
+ if ((strstr(model, "UCC") == NULL) ||
+ (ucc_num < 1) || (ucc_num > 8)) {
+ ret = -ENODEV;
+ goto err;
+ }
+
+ ugeth_dev =
+ platform_device_register_simple("ucc_geth", ucc_num - 1,
+ &r[0], np->n_intrs + 1);
+
+ if (IS_ERR(ugeth_dev)) {
+ ret = PTR_ERR(ugeth_dev);
+ goto err;
+ }
+
+ mac_addr = get_property(np, "mac-address", NULL);
+
+ memcpy(ugeth_data.mac_addr, mac_addr, 6);
+
+ ugeth_data.rx_clock = *((u32 *) get_property(np, "rx-clock",
+ NULL));
+ ugeth_data.tx_clock = *((u32 *) get_property(np, "tx-clock",
+ NULL));
+
+ ph = (phandle *) get_property(np, "phy-handle", NULL);
+ phy = of_find_node_by_phandle(*ph);
+
+ if (phy == NULL) {
+ ret = -ENODEV;
+ goto unreg;
+ }
+
+ mdio = of_get_parent(phy);
+
+ id = (u32 *) get_property(phy, "reg", NULL);
+ ret = of_address_to_resource(mdio, 0, &res);
+ if (ret) {
+ of_node_put(phy);
+ of_node_put(mdio);
+ goto unreg;
+ }
+
+ ugeth_data.phy_id = *id;
+ ugeth_data.phy_interrupt = phy->intrs[0].line;
+ ugeth_data.phy_interface = *((u32 *) get_property(phy,
+ "interface", NULL));
+
+ /* FIXME: Work around for early chip rev. */
+ /* There's a bug in initial chip rev(s) in the RGMII ac */
+ /* timing. */
+ /* The following compensates by writing to the reserved */
+ /* QE Port Output Hold Registers (CPOH1?). */
+ if ((ugeth_data.phy_interface == ENET_1000_RGMII) ||
+ (ugeth_data.phy_interface == ENET_100_RGMII) ||
+ (ugeth_data.phy_interface == ENET_10_RGMII)) {
+ u32 *tmp_reg = (u32 *) ioremap(get_immrbase()
+ + 0x14A8, 0x4);
+ u32 tmp_val = in_be32(tmp_reg);
+ if (ucc_num == 1)
+ out_be32(tmp_reg, tmp_val | 0x00003000);
+ else if (ucc_num == 2)
+ out_be32(tmp_reg, tmp_val | 0x0c000000);
+ iounmap(tmp_reg);
+ }
+
+ if (phy->intrs[0].line != 0)
+ ugeth_data.board_flags |= FSL_UGETH_BRD_HAS_PHY_INTR;
+
+ of_node_put(phy);
+ of_node_put(mdio);
+
+ ret =
+ platform_device_add_data(ugeth_dev, &ugeth_data,
+ sizeof(struct
+ ucc_geth_platform_data));
+ if (ret)
+ goto unreg;
+ }
+
+ return 0;
+
+unreg:
+ platform_device_unregister(ugeth_dev);
+err:
+ return ret;
+}
+
+arch_initcall(ucc_geth_of_init);
diff --git a/arch/powerpc/sysdev/qe_lib/qe_common.c b/arch/powerpc/sysdev/qe_lib/qe_common.c
new file mode 100644
index 0000000..cd0aca9
--- /dev/null
+++ b/arch/powerpc/sysdev/qe_lib/qe_common.c
@@ -0,0 +1,401 @@
+/*
+ * Copyright (C) Freescale Semicondutor, Inc. 2006. All rights reserved.
+ *
+ * Author: Shlomi Gridish <gridish@freescale.com>
+ *
+ * Description:
+ * General Purpose functions for the global management of the
+ * QUICC Engine (QE).
+ *
+ * Changelog:
+ * Jun 28, 2006 Li Yang <LeoLi@freescale.com>
+ * - Reorganized as qe_lib
+ * - Merged to powerpc arch; add device tree support
+ * - Style fixes
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+#undef USE_RHEAP
+#include <linux/errno.h>
+#include <linux/sched.h>
+#include <linux/kernel.h>
+#include <linux/param.h>
+#include <linux/string.h>
+#include <linux/mm.h>
+#include <linux/interrupt.h>
+#include <linux/bootmem.h>
+#include <linux/module.h>
+#include <linux/delay.h>
+#include <asm/irq.h>
+#include <asm/page.h>
+#include <asm/pgtable.h>
+#include <asm/immap_qe.h>
+#include <asm/qe.h>
+#include <asm/prom.h>
+#ifdef USE_RHEAP
+#include <asm/rheap.h>
+#else
+#include "mm.h"
+#endif /* USE_RHEAP */
+
+/* QE snum state
+*/
+typedef enum qe_snum_state {
+ QE_SNUM_STATE_USED, /* used */
+ QE_SNUM_STATE_FREE /* free */
+} qe_snum_state_e;
+
+/* QE snum
+*/
+typedef struct qe_snum {
+ u8 num; /* snum */
+ qe_snum_state_e state; /* state */
+} qe_snum_t;
+
+/* We allocate this here because it is used almost exclusively for
+ * the communication processor devices.
+ */
+EXPORT_SYMBOL(qe_immr);
+qe_map_t *qe_immr = NULL;
+static qe_snum_t snums[QE_NUM_OF_SNUM]; /* Dynamically allocated SNUMs */
+
+static void qe_snums_init(void);
+static void qe_muram_init(void);
+static int qe_sdma_init(void);
+
+void qe_reset(void)
+{
+ if (qe_immr == NULL)
+ qe_immr = (qe_map_t *) ioremap(get_qe_base(), QE_IMMAP_SIZE);
+
+ qe_snums_init();
+
+ qe_issue_cmd(QE_RESET, QE_CR_SUBBLOCK_INVALID,
+ (u8) QE_CR_PROTOCOL_UNSPECIFIED, 0);
+
+ /* Reclaim the MURAM memory for our use. */
+ qe_muram_init();
+
+#ifdef USE_RHEAP
+ if (qe_sdma_init())
+ panic("sdma init failed!");
+#endif /* USE_RHEAP */
+}
+
+EXPORT_SYMBOL(qe_issue_cmd);
+int qe_issue_cmd(uint cmd, uint device, u8 mcn_protocol, u32 cmd_input)
+{
+ unsigned long flags;
+ u32 cecr;
+ u8 mcn_shift = 0, dev_shift = 0;
+
+ local_irq_save(flags);
+ if (cmd == QE_RESET) {
+ out_be32(&qe_immr->cp.cecr, (u32) (cmd | QE_CR_FLG));
+ } else {
+ if (cmd == QE_ASSIGN_PAGE) {
+ /* Here device is the SNUM, not sub-block */
+ dev_shift = QE_CR_SNUM_SHIFT;
+ } else if (cmd == QE_ASSIGN_RISC) {
+ /* Here device is the SNUM, and mcnProtocol is
+ * e_QeCmdRiscAssignment value */
+ dev_shift = QE_CR_SNUM_SHIFT;
+ mcn_shift = QE_CR_MCN_RISC_ASSIGN_SHIFT;
+ } else {
+ if (device == QE_CR_SUBBLOCK_USB)
+ mcn_shift = QE_CR_MCN_USB_SHIFT;
+ else
+ mcn_shift = QE_CR_MCN_NORMAL_SHIFT;
+ }
+
+ out_be32(&qe_immr->cp.cecdr,
+ immrbar_virt_to_phys((void *)cmd_input));
+ out_be32(&qe_immr->cp.cecr,
+ (cmd | QE_CR_FLG | ((u32) device << dev_shift) | (u32)
+ mcn_protocol << mcn_shift));
+ }
+
+ /* wait for the QE_CR_FLG to clear */
+ do {
+ cecr = in_be32(&qe_immr->cp.cecr);
+ } while (cecr & QE_CR_FLG);
+ local_irq_restore(flags);
+
+ return 0;
+}
+
+/* Set a baud rate generator. This needs lots of work. There are
+ * 16 BRGs, which can be connected to the QE channels or output
+ * as clocks. The BRGs are in two different block of internal
+ * memory mapped space.
+ * The baud rate clock is the system clock divided by something.
+ * It was set up long ago during the initial boot phase and is
+ * is given to us.
+ * Baud rate clocks are zero-based in the driver code (as that maps
+ * to port numbers). Documentation uses 1-based numbering.
+ */
+static unsigned int brg_clk = 0;
+
+unsigned int get_brg_clk(void)
+{
+ struct device_node *qe;
+ if (brg_clk)
+ return brg_clk;
+
+ qe = of_find_node_by_type(NULL, "qe");
+ if (qe) {
+ unsigned int size;
+ u32 *prop = (u32 *) get_property(qe, "brg-frequency", &size);
+ brg_clk = *prop;
+ of_node_put(qe);
+ };
+ return brg_clk;
+}
+
+/* This function is used by UARTS, or anything else that uses a 16x
+ * oversampled clock.
+ */
+void qe_setbrg(uint brg, uint rate)
+{
+ volatile uint *bp;
+ u32 divisor;
+ int div16 = 0;
+
+ bp = (uint *) & qe_immr->brg.brgc1;
+ bp += brg;
+
+ divisor = (get_brg_clk() / rate);
+ if (divisor > QE_BRGC_DIVISOR_MAX + 1) {
+ div16 = 1;
+ divisor /= 16;
+ }
+
+ *bp = ((divisor - 1) << QE_BRGC_DIVISOR_SHIFT) | QE_BRGC_ENABLE;
+ if (div16)
+ *bp |= QE_BRGC_DIV16;
+}
+
+static void qe_snums_init(void)
+{
+ int i;
+
+ /* Initialize the SNUMs array. */
+ for (i = 0; i < QE_NUM_OF_SNUM; i++)
+ snums[i].state = QE_SNUM_STATE_FREE;
+
+ /* Initialize SNUMs (thread serial numbers) according to QE
+ * spec chapter 4, SNUM table */
+ i = 0;
+ snums[i++].num = 0x04;
+ snums[i++].num = 0x05;
+ snums[i++].num = 0x0C;
+ snums[i++].num = 0x0D;
+ snums[i++].num = 0x14;
+ snums[i++].num = 0x15;
+ snums[i++].num = 0x1C;
+ snums[i++].num = 0x1D;
+ snums[i++].num = 0x24;
+ snums[i++].num = 0x25;
+ snums[i++].num = 0x2C;
+ snums[i++].num = 0x2D;
+ snums[i++].num = 0x34;
+ snums[i++].num = 0x35;
+ snums[i++].num = 0x88;
+ snums[i++].num = 0x89;
+ snums[i++].num = 0x98;
+ snums[i++].num = 0x99;
+ snums[i++].num = 0xA8;
+ snums[i++].num = 0xA9;
+ snums[i++].num = 0xB8;
+ snums[i++].num = 0xB9;
+ snums[i++].num = 0xC8;
+ snums[i++].num = 0xC9;
+ snums[i++].num = 0xD8;
+ snums[i++].num = 0xD9;
+ snums[i++].num = 0xE8;
+ snums[i++].num = 0xE9;
+}
+
+int qe_get_snum(void)
+{
+ unsigned long flags;
+ int snum = -EBUSY;
+ int i;
+
+ local_irq_save(flags);
+ for (i = 0; i < QE_NUM_OF_SNUM; i++) {
+ if (snums[i].state == QE_SNUM_STATE_FREE) {
+ snums[i].state = QE_SNUM_STATE_USED;
+ snum = snums[i].num;
+ break;
+ }
+ }
+ local_irq_restore(flags);
+
+ return snum;
+}
+
+EXPORT_SYMBOL(qe_get_snum);
+
+void qe_put_snum(u8 snum)
+{
+ int i;
+
+ for (i = 0; i < QE_NUM_OF_SNUM; i++) {
+ if (snums[i].num == snum) {
+ snums[i].state = QE_SNUM_STATE_FREE;
+ break;
+ }
+ }
+}
+
+EXPORT_SYMBOL(qe_put_snum);
+
+static int qe_sdma_init(void)
+{
+ sdma_t *sdma = &qe_immr->sdma;
+ uint sdma_buf_offset;
+
+ if (!sdma)
+ return -ENODEV;
+
+ /* allocate 2 internal temporary buffers (512 bytes size each) for
+ * the SDMA */
+ sdma_buf_offset = qe_muram_alloc(512 * 2, 64);
+ if (IS_MURAM_ERR(sdma_buf_offset))
+ return -ENOMEM;
+
+ out_be32(&sdma->sdebcr, sdma_buf_offset & QE_SDEBCR_BA_MASK);
+ out_be32(&sdma->sdmr, (QE_SDMR_GLB_1_MSK | (0x1 >>
+ QE_SDMR_CEN_SHIFT)));
+
+ return 0;
+}
+
+/*
+ * muram_alloc / muram_free bits.
+ */
+static spinlock_t qe_muram_lock;
+#ifdef USE_RHEAP
+/* 16 blocks should be enough to satisfy all requests
+ * until the memory subsystem goes up... */
+static rh_block_t qe_boot_muram_rh_block[16];
+static rh_info_t qe_muram_info;
+#else
+static void *mm = NULL;
+#endif /* USE_RHEAP */
+
+static void qe_muram_init(void)
+{
+ spin_lock_init(&qe_muram_lock);
+
+#ifdef USE_RHEAP
+ /* initialize the info header */
+ rh_init(&qe_muram_info, 1,
+ sizeof(qe_boot_muram_rh_block) /
+ sizeof(qe_boot_muram_rh_block[0]), qe_boot_muram_rh_block);
+
+ /* Attach the usable muram area */
+ /* XXX: This is actually crap. QE_DATAONLY_BASE and
+ * QE_DATAONLY_SIZE is only a subset of the available muram. It
+ * varies with the processor and the microcode patches activated.
+ * But the following should be at least safe.
+ */
+ rh_attach_region(&qe_muram_info,
+ (void *)QE_MURAM_DATAONLY_BASE,
+ QE_MURAM_DATAONLY_SIZE);
+#else
+#endif /* USE_RHEAP */
+}
+
+/* This function returns an index into the MURAM area.
+ */
+uint qe_muram_alloc(uint size, uint align)
+{
+ void *start;
+ unsigned long flags;
+
+ spin_lock_irqsave(&qe_muram_lock, flags);
+#ifdef USE_RHEAP
+ qe_muram_info.alignment = align;
+ start = rh_alloc(&qe_muram_info, size, "QE");
+#else
+ if (!mm) {
+ mm_init(&mm, (u32) qe_muram_addr(QE_MURAM_DATAONLY_BASE),
+ QE_MURAM_DATAONLY_SIZE);
+ if (qe_sdma_init())
+ panic("sdma init failed!");
+
+ }
+ start = mm_get(mm, (u32) size, (int)align, "QE");
+ if (!IS_MURAM_ERR((u32) start))
+ start = (void *)((u32) start - (u32) qe_immr->muram);
+#endif /* USE_RHEAP */
+ spin_unlock_irqrestore(&qe_muram_lock, flags);
+
+ return (uint) start;
+}
+
+EXPORT_SYMBOL(qe_muram_alloc);
+
+int qe_muram_free(uint offset)
+{
+ int ret;
+ unsigned long flags;
+
+ spin_lock_irqsave(&qe_muram_lock, flags);
+#ifdef USE_RHEAP
+ ret = rh_free(&qe_muram_info, (void *)offset);
+#else
+ ret = mm_put(mm, (u32) qe_muram_addr(offset));
+#endif /* USE_RHEAP */
+ spin_unlock_irqrestore(&qe_muram_lock, flags);
+
+ return ret;
+}
+
+EXPORT_SYMBOL(qe_muram_free);
+
+/* not sure if this is ever needed */
+uint qe_muram_alloc_fixed(uint offset, uint size, uint align)
+{
+ void *start;
+ unsigned long flags;
+
+ spin_lock_irqsave(&qe_muram_lock, flags);
+#ifdef USE_RHEAP
+ qe_muram_info.alignment = align;
+ start =
+ rh_alloc_fixed(&qe_muram_info, (void *)offset, size, "commproc");
+#else
+ start = mm_get_force(mm, (u32) offset, (u32) size, "QE");
+ if (!IS_MURAM_ERR((u32) start))
+ start = (void *)((u32) start - (u32) qe_immr->muram);
+#endif /* USE_RHEAP */
+ spin_unlock_irqrestore(&qe_muram_lock, flags);
+
+ return (uint) start;
+}
+
+EXPORT_SYMBOL(qe_muram_alloc_fixed);
+
+void qe_muram_dump(void)
+{
+#ifdef USE_RHEAP
+ rh_dump(&qe_muram_info);
+#else
+ mm_dump(mm);
+#endif /* USE_RHEAP */
+}
+
+EXPORT_SYMBOL(qe_muram_dump);
+
+void *qe_muram_addr(uint offset)
+{
+ return (void *)&qe_immr->muram[offset];
+}
+
+EXPORT_SYMBOL(qe_muram_addr);
diff --git a/arch/powerpc/sysdev/qe_lib/qe_ic.c b/arch/powerpc/sysdev/qe_lib/qe_ic.c
new file mode 100644
index 0000000..465630e
--- /dev/null
+++ b/arch/powerpc/sysdev/qe_lib/qe_ic.c
@@ -0,0 +1,487 @@
+/*
+ * Copyright (C) Freescale Semicondutor, Inc. 2006. All rights reserved.
+ *
+ * Author: Shlomi Gridish <gridish@freescale.com>
+ *
+ * Description:
+ * QE Interrupt Controller routines implementations.
+ *
+ * Changelog:
+ * Jun 28, 2006 Li Yang <LeoLi@freescale.com>
+ * - Reorganized as qe_lib
+ * - Merged to powerpc arch; add device tree support
+ * - Style fixes
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/reboot.h>
+#include <linux/slab.h>
+#include <linux/stddef.h>
+#include <linux/sched.h>
+#include <linux/signal.h>
+#include <linux/sysdev.h>
+#include <linux/interrupt.h>
+
+#include <asm/irq.h>
+#include <asm/io.h>
+#include <asm/qe_ic.h>
+
+#include "qe_ic.h"
+
+static struct qe_ic_private p_qe_ic;
+static struct qe_ic_private *primary_qe_ic;
+
+static struct qe_ic_info qe_ic_info[] = {
+ [1] = {
+ .mask = 0x00008000,
+ .qimr = 1,
+ .pri_code = 0},
+ [2] = {
+ .mask = 0x00004000,
+ .qimr = 1,
+ .pri_code = 1},
+ [3] = {
+ .mask = 0x00002000,
+ .qimr = 1,
+ .pri_code = 2},
+ [10] = {
+ .mask = 0x00000040,
+ .qimr = 1,
+ .pri_code = 1},
+ [11] = {
+ .mask = 0x00000020,
+ .qimr = 1,
+ .pri_code = 2},
+ [12] = {
+ .mask = 0x00000010,
+ .qimr = 1,
+ .pri_code = 3},
+ [13] = {
+ .mask = 0x00000008,
+ .qimr = 1,
+ .pri_code = 4},
+ [14] = {
+ .mask = 0x00000004,
+ .qimr = 1,
+ .pri_code = 5},
+ [15] = {
+ .mask = 0x00000002,
+ .qimr = 1,
+ .pri_code = 6},
+ [20] = {
+ .mask = 0x10000000,
+ .qimr = 0,
+ .pri_code = 3},
+ [25] = {
+ .mask = 0x00800000,
+ .qimr = 0,
+ .pri_code = 0},
+ [26] = {
+ .mask = 0x00400000,
+ .qimr = 0,
+ .pri_code = 1},
+ [27] = {
+ .mask = 0x00200000,
+ .qimr = 0,
+ .pri_code = 2},
+ [28] = {
+ .mask = 0x00100000,
+ .qimr = 0,
+ .pri_code = 3},
+ [32] = {
+ .mask = 0x80000000,
+ .qimr = 1,
+ .pri_code = 0},
+ [33] = {
+ .mask = 0x40000000,
+ .qimr = 1,
+ .pri_code = 1},
+ [34] = {
+ .mask = 0x20000000,
+ .qimr = 1,
+ .pri_code = 2},
+ [35] = {
+ .mask = 0x10000000,
+ .qimr = 1,
+ .pri_code = 3},
+ [36] = {
+ .mask = 0x08000000,
+ .qimr = 1,
+ .pri_code = 4},
+ [40] = {
+ .mask = 0x00800000,
+ .qimr = 1,
+ .pri_code = 0},
+ [41] = {
+ .mask = 0x00400000,
+ .qimr = 1,
+ .pri_code = 1},
+ [42] = {
+ .mask = 0x00200000,
+ .qimr = 1,
+ .pri_code = 2},
+ [43] = {
+ .mask = 0x00100000,
+ .qimr = 1,
+ .pri_code = 3},
+};
+
+struct hw_interrupt_type qe_ic = {
+ .typename = "QE IC",
+ .enable = qe_ic_enable_irq,
+ .disable = qe_ic_disable_irq,
+ .ack = qe_ic_disable_irq_and_ack,
+ .end = qe_ic_end_irq,
+};
+
+static int qe_ic_get_low_irq(struct pt_regs *regs)
+{
+ struct qe_ic_private *p_qe_ic = primary_qe_ic;
+ int irq = -1;
+
+ /* get the low byte of SIVEC to get the interrupt source vector. */
+ irq = (in_be32(&p_qe_ic->regs->qivec) >> 24) >> 2;
+
+ if (irq == 0) /* 0 --> no irq is pending */
+ return -1;
+
+ return irq + p_qe_ic->irq_offset;
+}
+
+static int qe_ic_get_high_irq(struct pt_regs *regs)
+{
+ struct qe_ic_private *p_qe_ic = primary_qe_ic;
+ int irq = -1;
+
+ /* get the high byte of SIVEC to get the interrupt source vector. */
+ irq = (in_be32(&p_qe_ic->regs->qhivec) >> 24) >> 2;
+
+ if (irq == 0) /* 0 --> no irq is pending */
+ return -1;
+
+ return irq + p_qe_ic->irq_offset;
+}
+
+static irqreturn_t qe_ic_cascade_low(int irq, void *dev_id,
+ struct pt_regs *regs)
+{
+ while ((irq = qe_ic_get_low_irq(regs)) >= 0)
+ __do_IRQ(irq, regs);
+ return IRQ_HANDLED;
+}
+
+static irqreturn_t qe_ic_cascade_high(int irq, void *dev_id,
+ struct pt_regs *regs)
+{
+ while ((irq = qe_ic_get_high_irq(regs)) >= 0)
+ __do_IRQ(irq, regs);
+ return IRQ_HANDLED;
+}
+
+static struct irqaction qe_ic_low_irqaction = {
+ .handler = qe_ic_cascade_low,
+ .flags = SA_INTERRUPT,
+ .mask = CPU_MASK_NONE,
+ .name = "qe_ic_cascade_low",
+};
+
+static struct irqaction qe_ic_high_irqaction = {
+ .handler = qe_ic_cascade_high,
+ .flags = SA_INTERRUPT,
+ .mask = CPU_MASK_NONE,
+ .name = "qe_ic_cascade_high",
+};
+
+int qe_ic_init(phys_addr_t phys_addr,
+ unsigned int flags, unsigned int irq_offset)
+{
+ struct qe_ic_map *regs;
+ u8 grp, pri, shift = 0;
+ u32 tmp_qicr = 0, tmp_qricr = 0, tmp_qicnr = 0, tmp_mask;
+ int i, high_hctive = 0;
+ const u32 high_signal = 2;
+
+ primary_qe_ic = &p_qe_ic;
+ memset(primary_qe_ic, 0, sizeof(struct qe_ic_private));
+
+ /* initialize QE interrupt controller registers */
+ primary_qe_ic->regs = regs =
+ (struct qe_ic_map *)ioremap(phys_addr, QE_IC_SIZE);
+ primary_qe_ic->irq_offset = irq_offset;
+
+ /* default priority scheme is grouped. If spread mode is */
+ /* required, configure sicr accordingly. */
+ if (flags & QE_IC_SPREADMODE_GRP_W)
+ tmp_qicr |= QICR_GWCC;
+ if (flags & QE_IC_SPREADMODE_GRP_X)
+ tmp_qicr |= QICR_GXCC;
+ if (flags & QE_IC_SPREADMODE_GRP_Y)
+ tmp_qicr |= QICR_GYCC;
+ if (flags & QE_IC_SPREADMODE_GRP_Z)
+ tmp_qicr |= QICR_GZCC;
+ if (flags & QE_IC_SPREADMODE_GRP_RISCA)
+ tmp_qicr |= QICR_GRTA;
+ if (flags & QE_IC_SPREADMODE_GRP_RISCB)
+ tmp_qicr |= QICR_GRTB;
+
+ /* choose destination signal for highest priority interrupt */
+ if (flags & QE_IC_HIGH_SIGNAL) {
+ tmp_qicr |= (high_signal << QICR_HPIT_SHIFT);
+ high_hctive = 1;
+ }
+
+ out_be32(®s->qicr, tmp_qicr);
+
+ tmp_mask = (1 << QE_IC_GRP_W_DEST_SIGNAL_SHIFT);
+ /* choose destination signal for highest priority interrupt in each
+ * group */
+ for (grp = 0; grp < NUM_OF_QE_IC_GROUPS; grp++) {
+ /* the first 2 priorities in each group have a choice of
+ * destination signal */
+ for (pri = 0; pri <= 1; pri++) {
+ if (flags & ((tmp_mask << (grp << 1)) << pri)) {
+ /* indicate whether QE High signal is
+ * required */
+ if (!high_hctive)
+ high_hctive = 1;
+
+ /* The location of the bits relevant to
+ * priority 0 in the */
+ /* registers is always 2 bits left comparing
+ * to priority 1. */
+ if (pri == 0)
+ shift = 2;
+
+ switch (grp) {
+ case (QE_IC_GRP_W):
+ shift += QICNR_WCC1T_SHIFT;
+ tmp_qicnr |= high_signal << shift;
+ break;
+ case (QE_IC_GRP_X):
+ shift += QICNR_XCC1T_SHIFT;
+ tmp_qicnr |= high_signal << shift;
+ break;
+ case (QE_IC_GRP_Y):
+ shift += QICNR_YCC1T_SHIFT;
+ tmp_qicnr |= high_signal << shift;
+ break;
+ case (QE_IC_GRP_Z):
+ shift += QICNR_ZCC1T_SHIFT;
+ tmp_qicnr |= high_signal << shift;
+ break;
+ case (QE_IC_GRP_RISCA):
+ shift += QRICR_RTA1T_SHIFT;
+ tmp_qricr |= high_signal << shift;
+ break;
+ case (QE_IC_GRP_RISCB):
+ shift += QRICR_RTB1T_SHIFT;
+ tmp_qricr |= high_signal << shift;
+ break;
+ default:
+ break;
+ }
+ }
+ }
+ }
+
+ if (tmp_qicnr)
+ out_be32(®s->qicnr, tmp_qicnr);
+ if (tmp_qricr)
+ out_be32(®s->qricr, tmp_qricr);
+
+ for (i = primary_qe_ic->irq_offset;
+ i < (NR_QE_IC_INTS + primary_qe_ic->irq_offset); i++) {
+ irq_desc[i].handler = &qe_ic;
+ irq_desc[i].status = IRQ_LEVEL;
+ }
+
+ /* register QE_IC interrupt controller in the a higher hirarchy
+ * controller */
+ setup_irq(IRQ_QE_LOW, &qe_ic_low_irqaction);
+
+ if (high_hctive)
+ /* register QE_IC high interrupt source in the higher
+ * hirarchy controller */
+ setup_irq(IRQ_QE_HIGH, &qe_ic_high_irqaction);
+
+ printk("QE IC (%d IRQ sources) at %p\n", NR_QE_IC_INTS,
+ primary_qe_ic->regs);
+ return 0;
+}
+
+void qe_ic_free(void)
+{
+}
+
+void qe_ic_enable_irq(unsigned int irq)
+{
+ struct qe_ic_private *p_qe_ic = primary_qe_ic;
+ unsigned int src = irq - p_qe_ic->irq_offset;
+ u32 qimr;
+
+ if (qe_ic_info[src].qimr) {
+ qimr = in_be32(&((struct qe_ic_private *)p_qe_ic)->regs->qimr);
+ out_be32(&((struct qe_ic_private *)p_qe_ic)->regs->qimr,
+ qimr | (qe_ic_info[src].mask));
+ } else {
+ qimr = in_be32(&((struct qe_ic_private *)p_qe_ic)->regs->qrimr);
+ out_be32(&((struct qe_ic_private *)p_qe_ic)->regs->qrimr,
+ qimr | (qe_ic_info[src].mask));
+ }
+}
+
+void qe_ic_disable_irq(unsigned int irq)
+{
+ struct qe_ic_private *p_qe_ic = primary_qe_ic;
+ unsigned int src = irq - p_qe_ic->irq_offset;
+ u32 qimr;
+
+ if (qe_ic_info[src].qimr) {
+ qimr = in_be32(&((struct qe_ic_private *)p_qe_ic)->regs->qimr);
+ out_be32(&((struct qe_ic_private *)p_qe_ic)->regs->qimr,
+ qimr & ~(qe_ic_info[src].mask));
+ } else {
+ qimr = in_be32(&((struct qe_ic_private *)p_qe_ic)->regs->qrimr);
+ out_be32(&((struct qe_ic_private *)p_qe_ic)->regs->qrimr,
+ qimr & ~(qe_ic_info[src].mask));
+ }
+}
+
+void qe_ic_disable_irq_and_ack(unsigned int irq)
+{
+ qe_ic_disable_irq(irq);
+}
+
+void qe_ic_end_irq(unsigned int irq)
+{
+
+ if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))
+ && irq_desc[irq].action)
+ qe_ic_enable_irq(irq);
+}
+
+void qe_ic_modify_highest_priority(unsigned int irq)
+{
+ struct qe_ic_private *p_qe_ic = primary_qe_ic;
+ unsigned int src = irq - p_qe_ic->irq_offset;
+ u32 tmp_qicr = 0;
+
+ tmp_qicr = in_be32(&p_qe_ic->regs->qicr);
+ out_be32(&p_qe_ic->regs->qicr, (u32) (tmp_qicr | ((u8) src << 24)));
+}
+
+void qe_ic_modify_priority(enum qe_ic_grp_id grp,
+ unsigned int pri0,
+ unsigned int pri1,
+ unsigned int pri2,
+ unsigned int pri3,
+ unsigned int pri4,
+ unsigned int pri5,
+ unsigned int pri6, unsigned int pri7)
+{
+ struct qe_ic_private *p_qe_ic = primary_qe_ic;
+ volatile u32 *p_qip = 0;
+ u32 tmp_qip = 0;
+ u8 tmp_array[8] = { 0, 0, 0, 0, 0, 0, 0, 0 };
+ signed char code_array[8], i = 0, j = 0;
+
+ code_array[0] = (signed char)(pri0 ? qe_ic_info[pri0].pri_code : -1);
+ code_array[1] = (signed char)(pri1 ? qe_ic_info[pri1].pri_code : -1);
+ code_array[2] = (signed char)(pri2 ? qe_ic_info[pri2].pri_code : -1);
+ code_array[3] = (signed char)(pri3 ? qe_ic_info[pri3].pri_code : -1);
+ code_array[4] = (signed char)(pri4 ? qe_ic_info[pri4].pri_code : -1);
+ code_array[5] = (signed char)(pri5 ? qe_ic_info[pri5].pri_code : -1);
+ code_array[6] = (signed char)(pri6 ? qe_ic_info[pri6].pri_code : -1);
+ code_array[7] = (signed char)(pri7 ? qe_ic_info[pri7].pri_code : -1);
+
+ for (i = 0; i < 8; i++) {
+ if (code_array[i] == -1)
+ break;
+ tmp_array[code_array[i]] = 1;
+ }
+
+ for (; i < 8; i++) {
+ while (tmp_array[j] && j < 8)
+ j++;
+ code_array[i] = j;
+ tmp_array[j] = 1;
+ }
+
+ tmp_qip = (u32) (code_array[0] << QIPCC_SHIFT_PRI0 |
+ code_array[1] << QIPCC_SHIFT_PRI1 |
+ code_array[2] << QIPCC_SHIFT_PRI2 |
+ code_array[3] << QIPCC_SHIFT_PRI3 |
+ code_array[4] << QIPCC_SHIFT_PRI4 |
+ code_array[5] << QIPCC_SHIFT_PRI5 |
+ code_array[6] << QIPCC_SHIFT_PRI6 |
+ code_array[7] << QIPCC_SHIFT_PRI7);
+
+ switch (grp) {
+ case (QE_IC_GRP_W):
+ p_qip = &(p_qe_ic->regs->qipwcc);
+ break;
+ case (QE_IC_GRP_X):
+ p_qip = &(p_qe_ic->regs->qipxcc);
+ break;
+ case (QE_IC_GRP_Y):
+ p_qip = &(p_qe_ic->regs->qipycc);
+ break;
+ case (QE_IC_GRP_Z):
+ p_qip = &(p_qe_ic->regs->qipzcc);
+ break;
+ case (QE_IC_GRP_RISCA):
+ p_qip = &(p_qe_ic->regs->qiprta);
+ break;
+ case (QE_IC_GRP_RISCB):
+ p_qip = &(p_qe_ic->regs->qiprtb);
+ break;
+ default:
+ break;
+ }
+
+ out_be32(p_qip, tmp_qip);
+}
+
+void qe_ic_dump_regs(void)
+{
+ struct qe_ic_private *p_qe_ic = primary_qe_ic;
+
+ printk(KERN_INFO "QE IC registars:\n");
+ printk(KERN_INFO "Base address: 0x%08x\n", (u32) p_qe_ic->regs);
+ printk(KERN_INFO "qicr : addr - 0x%08x, val - 0x%08x\n",
+ (u32) & p_qe_ic->regs->qicr, in_be32(&p_qe_ic->regs->qicr));
+ printk(KERN_INFO "qivec : addr - 0x%08x, val - 0x%08x\n",
+ (u32) & p_qe_ic->regs->qivec, in_be32(&p_qe_ic->regs->qivec));
+ printk(KERN_INFO "qripnr: addr - 0x%08x, val - 0x%08x\n",
+ (u32) & p_qe_ic->regs->qripnr, in_be32(&p_qe_ic->regs->qripnr));
+ printk(KERN_INFO "qipnr : addr - 0x%08x, val - 0x%08x\n",
+ (u32) & p_qe_ic->regs->qipnr, in_be32(&p_qe_ic->regs->qipnr));
+ printk(KERN_INFO "qipxcc: addr - 0x%08x, val - 0x%08x\n",
+ (u32) & p_qe_ic->regs->qipxcc, in_be32(&p_qe_ic->regs->qipxcc));
+ printk(KERN_INFO "qipycc: addr - 0x%08x, val - 0x%08x\n",
+ (u32) & p_qe_ic->regs->qipycc, in_be32(&p_qe_ic->regs->qipycc));
+ printk(KERN_INFO "qipwcc: addr - 0x%08x, val - 0x%08x\n",
+ (u32) & p_qe_ic->regs->qipwcc, in_be32(&p_qe_ic->regs->qipwcc));
+ printk(KERN_INFO "qipzcc: addr - 0x%08x, val - 0x%08x\n",
+ (u32) & p_qe_ic->regs->qipzcc, in_be32(&p_qe_ic->regs->qipzcc));
+ printk(KERN_INFO "qimr : addr - 0x%08x, val - 0x%08x\n",
+ (u32) & p_qe_ic->regs->qimr, in_be32(&p_qe_ic->regs->qimr));
+ printk(KERN_INFO "qrimr : addr - 0x%08x, val - 0x%08x\n",
+ (u32) & p_qe_ic->regs->qrimr, in_be32(&p_qe_ic->regs->qrimr));
+ printk(KERN_INFO "qicnr : addr - 0x%08x, val - 0x%08x\n",
+ (u32) & p_qe_ic->regs->qicnr, in_be32(&p_qe_ic->regs->qicnr));
+ printk(KERN_INFO "qiprta: addr - 0x%08x, val - 0x%08x\n",
+ (u32) & p_qe_ic->regs->qiprta, in_be32(&p_qe_ic->regs->qiprta));
+ printk(KERN_INFO "qiprtb: addr - 0x%08x, val - 0x%08x\n",
+ (u32) & p_qe_ic->regs->qiprtb, in_be32(&p_qe_ic->regs->qiprtb));
+ printk(KERN_INFO "qricr : addr - 0x%08x, val - 0x%08x\n",
+ (u32) & p_qe_ic->regs->qricr, in_be32(&p_qe_ic->regs->qricr));
+ printk(KERN_INFO "qhivec: addr - 0x%08x, val - 0x%08x\n",
+ (u32) & p_qe_ic->regs->qhivec, in_be32(&p_qe_ic->regs->qhivec));
+}
diff --git a/arch/powerpc/sysdev/qe_lib/qe_ic.h b/arch/powerpc/sysdev/qe_lib/qe_ic.h
new file mode 100644
index 0000000..6662ad2
--- /dev/null
+++ b/arch/powerpc/sysdev/qe_lib/qe_ic.h
@@ -0,0 +1,83 @@
+/*
+ * Copyright (C) Freescale Semicondutor, Inc. 2006. All rights reserved.
+ *
+ * Author: Shlomi Gridish <gridish@freescale.com>
+ *
+ * Description:
+ * QE IC private definitions and structure.
+ *
+ * Changelog:
+ * Jun 21, 2006 Li Yang <LeoLi@freescale.com>
+ * - Style fix; port to powerpc arch
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+#ifndef __QE_IC_H__
+#define __QE_IC_H__
+
+typedef struct qe_ic_map {
+ volatile u32 qicr;
+ volatile u32 qivec;
+ volatile u32 qripnr;
+ volatile u32 qipnr;
+ volatile u32 qipxcc;
+ volatile u32 qipycc;
+ volatile u32 qipwcc;
+ volatile u32 qipzcc;
+ volatile u32 qimr;
+ volatile u32 qrimr;
+ volatile u32 qicnr;
+ volatile u8 res0[0x4];
+ volatile u32 qiprta;
+ volatile u32 qiprtb;
+ volatile u8 res1[0x4];
+ volatile u32 qricr;
+ volatile u8 res2[0x20];
+ volatile u32 qhivec;
+ volatile u8 res3[0x1C];
+} __attribute__ ((packed)) qe_ic_map_t;
+
+
+#define QE_IC_SIZE sizeof(struct qe_ic_map)
+
+/* Interrupt priority registers */
+#define QIPCC_SHIFT_PRI0 29
+#define QIPCC_SHIFT_PRI1 26
+#define QIPCC_SHIFT_PRI2 23
+#define QIPCC_SHIFT_PRI3 20
+#define QIPCC_SHIFT_PRI4 13
+#define QIPCC_SHIFT_PRI5 10
+#define QIPCC_SHIFT_PRI6 7
+#define QIPCC_SHIFT_PRI7 4
+
+/* QICR priority modes */
+#define QICR_GWCC 0x00040000
+#define QICR_GXCC 0x00020000
+#define QICR_GYCC 0x00010000
+#define QICR_GZCC 0x00080000
+#define QICR_GRTA 0x00200000
+#define QICR_GRTB 0x00400000
+#define QICR_HPIT_SHIFT 8
+
+/* QICNR */
+#define QICNR_WCC1T_SHIFT 20
+#define QICNR_ZCC1T_SHIFT 28
+#define QICNR_YCC1T_SHIFT 12
+#define QICNR_XCC1T_SHIFT 4
+
+/* QRICR */
+#define QRICR_RTA1T_SHIFT 20
+#define QRICR_RTB1T_SHIFT 28
+
+struct qe_ic_private {
+ struct qe_ic_map *regs;
+ unsigned int irq_offset;
+} qe_ic_private_t;
+
+extern struct hw_interrupt_type qe_ic;
+extern int qe_ic_get_irq(struct pt_regs *regs);
+
+#endif /* __QE_IC_H__ */
diff --git a/arch/powerpc/sysdev/qe_lib/qe_io.c b/arch/powerpc/sysdev/qe_lib/qe_io.c
new file mode 100644
index 0000000..a943c27
--- /dev/null
+++ b/arch/powerpc/sysdev/qe_lib/qe_io.c
@@ -0,0 +1,275 @@
+/*
+ * Copyright (C) Freescale Semicondutor, Inc. 2006. All rights reserved.
+ *
+ * Author: Li Yang <LeoLi@freescale.com>
+ *
+ * Description:
+ * QE Parallel I/O ports configuration routines. Based on code from
+ * Shlomi Gridish <gridish@freescale.com>
+ *
+ * Changelog:
+ * Jun 21, 2006 Initial version
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/config.h>
+#include <linux/stddef.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/module.h>
+
+#include <asm/io.h>
+#include <asm/prom.h>
+#include <sysdev/fsl_soc.h>
+#undef DEBUG
+
+#define NUM_OF_PINS 32
+#define NUM_OF_PAR_IOS 7
+
+typedef struct par_io {
+ struct {
+ u32 cpodr; /* Open drain register */
+ u32 cpdata; /* Data register */
+ u32 cpdir1; /* Direction register */
+ u32 cpdir2; /* Direction register */
+ u32 cppar1; /* Pin assignment register */
+ u32 cppar2; /* Pin assignment register */
+ } io_regs[NUM_OF_PAR_IOS];
+} par_io_t;
+
+typedef struct qe_par_io {
+ u8 res[0xc];
+ u32 cepier; /* QE ports interrupt event register */
+ u32 cepimr; /* QE ports mask event register */
+ u32 cepicr; /* QE ports control event register */
+} qe_par_io_t;
+
+static int qe_irq_ports[NUM_OF_PAR_IOS][NUM_OF_PINS] = {
+ /* 0-7 */ /* 8-15 */ /* 16 - 23 */ /* 24 - 31 */
+ {0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,1, 1,0,0,0,0,0,0,0, 0,0,0,0,0,1,1,0},
+ {0,0,0,1,0,1,0,0, 0,0,0,0,1,1,0,0, 0,0,0,0,0,0,0,0, 0,0,1,1,0,0,0,0},
+ {0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0, 0,0,0,1,1,1,0,0},
+ {0,0,0,0,0,0,0,0, 0,0,0,0,1,1,0,0, 1,1,0,0,0,0,0,0, 0,0,1,1,0,0,0,0},
+ {0,0,0,0,0,0,0,0, 0,0,0,0,1,1,0,0, 0,0,0,0,0,0,0,0, 1,1,1,1,0,0,0,1},
+ {0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0, 0,0,0,0,1,0,0,0, 0,0,0,0,0,0,0,0},
+ {0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,1}
+};
+
+
+static u8 get_irq_num(u8 port, u8 pin)
+{
+ int i, j;
+ u8 num = 0;
+
+ if (qe_irq_ports[port][pin] == 0)
+ return -1;
+ for (j = 0; j <= port; j++)
+ for (i = 0; i < pin; i++)
+ if (qe_irq_ports[j][i])
+ num++;
+ return num;
+}
+
+static par_io_t *par_io = NULL;
+static qe_par_io_t *qe_par_io = NULL;
+
+int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain,
+ int assignment, int has_irq)
+{
+ u32 pinMask1bit, pinMask2bits, newMask2bits, tmp_val;
+
+ if (!par_io) {
+ par_io = (par_io_t *) ioremap(get_immrbase() + 0x1400,
+ sizeof(par_io_t));
+ qe_par_io = (qe_par_io_t *) ioremap(get_immrbase() + 0xC00,
+ sizeof(qe_par_io_t));
+
+ /* clear event bits in the event register of the QE ports */
+ out_be32(&qe_par_io->cepier, 0xFFFFFFFF);
+ }
+
+ /* calculate pin location for single and 2 bits information */
+ pinMask1bit = (u32) (1 << (NUM_OF_PINS - (pin + 1)));
+
+ /* Set open drain, if required */
+ tmp_val = in_be32(&par_io->io_regs[port].cpodr);
+ if (open_drain)
+ out_be32(&par_io->io_regs[port].cpodr, pinMask1bit | tmp_val);
+ else
+ out_be32(&par_io->io_regs[port].cpodr, ~pinMask1bit & tmp_val);
+
+ /* define direction */
+ tmp_val = (pin > (NUM_OF_PINS / 2) - 1) ?
+ in_be32(&par_io->io_regs[port].cpdir2) :
+ in_be32(&par_io->io_regs[port].cpdir1);
+
+ /* get all bits mask for 2 bit per port */
+ pinMask2bits = (u32) (0x3 <<
+ (NUM_OF_PINS -
+ (pin % (NUM_OF_PINS / 2) + 1) * 2));
+
+ /* Get the final mask we need for the right definition */
+ newMask2bits = (u32) (dir <<
+ (NUM_OF_PINS -
+ (pin % (NUM_OF_PINS / 2) + 1) * 2));
+
+ /* clear and set 2 bits mask */
+ if (pin > (NUM_OF_PINS / 2) - 1) {
+ out_be32(&par_io->io_regs[port].cpdir2,
+ ~pinMask2bits & tmp_val);
+ tmp_val &= ~pinMask2bits;
+ out_be32(&par_io->io_regs[port].cpdir2, newMask2bits | tmp_val);
+ } else {
+ out_be32(&par_io->io_regs[port].cpdir1,
+ ~pinMask2bits & tmp_val);
+ tmp_val &= ~pinMask2bits;
+ out_be32(&par_io->io_regs[port].cpdir1, newMask2bits | tmp_val);
+ }
+ /* define pin assignment */
+ tmp_val = (pin > (NUM_OF_PINS / 2) - 1) ?
+ in_be32(&par_io->io_regs[port].cppar2) :
+ in_be32(&par_io->io_regs[port].cppar1);
+
+ newMask2bits = (u32) (assignment << (NUM_OF_PINS -
+ (pin % (NUM_OF_PINS / 2) + 1) * 2));
+ /* clear and set 2 bits mask */
+ if (pin > (NUM_OF_PINS / 2) - 1) {
+ out_be32(&par_io->io_regs[port].cppar2,
+ ~pinMask2bits & tmp_val);
+ tmp_val &= ~pinMask2bits;
+ out_be32(&par_io->io_regs[port].cppar2, newMask2bits | tmp_val);
+ } else {
+ out_be32(&par_io->io_regs[port].cppar1,
+ ~pinMask2bits & tmp_val);
+ tmp_val &= ~pinMask2bits;
+ out_be32(&par_io->io_regs[port].cppar1, newMask2bits | tmp_val);
+ }
+
+ /* Set interrupt mask if the pin generates interrupt */
+ if (has_irq) {
+ int irq = get_irq_num(port, pin);
+ u32 mask = 0;
+
+ if (irq == -1) {
+ printk(KERN_WARNING "Port %d, pin %d is can't be "
+ "interrupt\n", port, pin);
+ return -EINVAL;
+ }
+ mask = 0x80000000 >> irq;
+
+ tmp_val = in_be32(&qe_par_io->cepimr);
+ out_be32(&qe_par_io->cepimr, mask | tmp_val);
+ }
+
+ return 0;
+}
+
+EXPORT_SYMBOL(par_io_config_pin);
+
+int par_io_data_set(u8 port, u8 pin, u8 val)
+{
+ u32 pin_mask, tmp_val;
+
+ if (port >= NUM_OF_PAR_IOS)
+ return -EINVAL;
+ if (pin >= NUM_OF_PINS)
+ return -EINVAL;
+ /* calculate pin location */
+ pin_mask = (u32) (1 << (NUM_OF_PINS - 1 - pin));
+
+ tmp_val = in_be32(&par_io->io_regs[port].cpdata);
+
+ if (val == 0) /* clear */
+ out_be32(&par_io->io_regs[port].cpdata, ~pin_mask & tmp_val);
+ else /* set */
+ out_be32(&par_io->io_regs[port].cpdata, pin_mask | tmp_val);
+
+ return 0;
+}
+
+EXPORT_SYMBOL(par_io_data_set);
+
+int par_io_of_config(struct device_node *np)
+{
+ struct device_node *pio;
+ phandle *ph;
+ int pio_map_len;
+ unsigned int *pio_map;
+
+ ph = (phandle *) get_property(np, "pio-handle", NULL);
+ if (ph == 0) {
+ printk(KERN_ERR "pio-handle not available \n");
+ return -1;
+ }
+
+ pio = of_find_node_by_phandle(*ph);
+
+ pio_map = (unsigned int *)
+ get_property(pio, "pio-map", &pio_map_len);
+ if (pio_map == NULL) {
+ printk(KERN_ERR "pio-map is not set! \n");
+ return -1;
+ }
+ pio_map_len /= sizeof(unsigned int);
+ if ((pio_map_len % 6) != 0) {
+ printk(KERN_ERR "pio-map format wrong! \n");
+ return -1;
+ }
+
+ while (pio_map_len > 0) {
+ par_io_config_pin((u8) pio_map[0], (u8) pio_map[1],
+ (int) pio_map[2], (int) pio_map[3],
+ (int) pio_map[4], (int) pio_map[5]);
+ pio_map += 6;
+ pio_map_len -= 6;
+ }
+ of_node_put(pio);
+ return 0;
+}
+EXPORT_SYMBOL(par_io_of_config);
+
+#ifdef DEBUG
+static void dump_par_io(void)
+{
+ int i;
+
+ printk(KERN_INFO "PAR IO registars:\n");
+ printk(KERN_INFO "Base address: 0x%08x\n", (u32) par_io);
+ for (i = 0; i < NUM_OF_PAR_IOS; i++) {
+ printk(KERN_INFO "cpodr[%d] : addr - 0x%08x, val - 0x%08x\n",
+ i, (u32) & par_io->io_regs[i].cpodr,
+ in_be32(&par_io->io_regs[i].cpodr));
+ printk(KERN_INFO "cpdata[%d]: addr - 0x%08x, val - 0x%08x\n",
+ i, (u32) & par_io->io_regs[i].cpdata,
+ in_be32(&par_io->io_regs[i].cpdata));
+ printk(KERN_INFO "cpdir1[%d]: addr - 0x%08x, val - 0x%08x\n",
+ i, (u32) & par_io->io_regs[i].cpdir1,
+ in_be32(&par_io->io_regs[i].cpdir1));
+ printk(KERN_INFO "cpdir2[%d]: addr - 0x%08x, val - 0x%08x\n",
+ i, (u32) & par_io->io_regs[i].cpdir2,
+ in_be32(&par_io->io_regs[i].cpdir2));
+ printk(KERN_INFO "cppar1[%d]: addr - 0x%08x, val - 0x%08x\n",
+ i, (u32) & par_io->io_regs[i].cppar1,
+ in_be32(&par_io->io_regs[i].cppar1));
+ printk(KERN_INFO "cppar2[%d]: addr - 0x%08x, val - 0x%08x\n",
+ i, (u32) & par_io->io_regs[i].cppar2,
+ in_be32(&par_io->io_regs[i].cppar2));
+ }
+
+ printk(KERN_INFO "QE PAR IO registars:\n");
+ printk(KERN_INFO "Base address: 0x%08x\n", (u32) qe_par_io);
+ printk(KERN_INFO "cepier : addr - 0x%08x, val - 0x%08x\n",
+ (u32) & qe_par_io->cepier, in_be32(&qe_par_io->cepier));
+ printk(KERN_INFO "cepimr : addr - 0x%08x, val - 0x%08x\n",
+ (u32) & qe_par_io->cepimr, in_be32(&qe_par_io->cepimr));
+ printk(KERN_INFO "cepicr : addr - 0x%08x, val - 0x%08x\n",
+ (u32) & qe_par_io->cepicr, in_be32(&qe_par_io->cepicr));
+}
+
+EXPORT_SYMBOL(dump_par_io);
+#endif
^ permalink raw reply related
* [PATCH 4/7] powerpc: Add QE library qe_lib--ucc support
From: Li Yang-r58472 @ 2006-06-28 14:23 UTC (permalink / raw)
To: 'Paul Mackerras'
Cc: Gridish Shlomi-RM96313, linuxppc-dev, Phillips Kim-R1AAHA,
'linux-kernel@vger.kernel.org', Chu hanjin-r52514
Signed-off-by: Shlomi Gridish <gridish@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
---
arch/powerpc/sysdev/qe_lib/ucc.c | 350 ++++++++++++++++++++++++++++
arch/powerpc/sysdev/qe_lib/ucc_fast.c | 413 +++++++++++++++++++++++++++++++++
arch/powerpc/sysdev/qe_lib/ucc_slow.c | 411 +++++++++++++++++++++++++++++++++
3 files changed, 1174 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/sysdev/qe_lib/ucc.c b/arch/powerpc/sysdev/qe_lib/ucc.c
new file mode 100644
index 0000000..8475d7f
--- /dev/null
+++ b/arch/powerpc/sysdev/qe_lib/ucc.c
@@ -0,0 +1,350 @@
+/*
+ * Copyright (C) Freescale Semicondutor, Inc. 2006. All rights reserved.
+ *
+ * Author: Shlomi Gridish <gridish@freescale.com>
+ *
+ * Description:
+ * QE UCC API Set - UCC specific routines implementations.
+ *
+ * Changelog:
+ * Jun 28, 2006 Li Yang <LeoLi@freescale.com>
+ * - Reorganized as qe_lib
+ * - Merged to powerpc arch; add device tree support
+ * - Style fixes
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/slab.h>
+#include <linux/stddef.h>
+
+#include <asm/irq.h>
+#include <asm/io.h>
+#include <asm/immap_qe.h>
+#include <asm/qe.h>
+
+#include <asm/ucc.h>
+
+int ucc_set_qe_mux_mii_mng(int ucc_num)
+{
+ unsigned long flags;
+
+ local_irq_save(flags);
+ out_be32(&qe_immr->qmx.cmxgcr,
+ ((in_be32(&qe_immr->qmx.cmxgcr) &
+ ~QE_CMXGCR_MII_ENET_MNG) |
+ (ucc_num << QE_CMXGCR_MII_ENET_MNG_SHIFT)));
+ local_irq_restore(flags);
+
+ return 0;
+}
+
+int ucc_set_type(int ucc_num, struct ucc_common *regs,
+ enum ucc_speed_type speed)
+{
+ u8 guemr = 0;
+
+ /* check if the UCC number is in range. */
+ if ((ucc_num > UCC_MAX_NUM - 1) || (ucc_num < 0))
+ return -EINVAL;
+
+ guemr = regs->guemr;
+ guemr &= ~(UCC_GUEMR_MODE_MASK_RX | UCC_GUEMR_MODE_MASK_TX);
+ switch (speed) {
+ case UCC_SPEED_TYPE_SLOW:
+ guemr |= (UCC_GUEMR_MODE_SLOW_RX | UCC_GUEMR_MODE_SLOW_TX);
+ break;
+ case UCC_SPEED_TYPE_FAST:
+ guemr |= (UCC_GUEMR_MODE_FAST_RX | UCC_GUEMR_MODE_FAST_TX);
+ break;
+ default:
+ return -EINVAL;
+ }
+ regs->guemr = guemr;
+
+ return 0;
+}
+
+int ucc_init_guemr(struct ucc_common *regs)
+{
+ u8 guemr = 0;
+
+ if (!regs)
+ return -EINVAL;
+
+ /* Set bit 3 (which is reserved in the GUEMR register) to 1 */
+ guemr = UCC_GUEMR_SET_RESERVED3;
+
+ regs->guemr = guemr;
+
+ return 0;
+}
+
+static void get_cmxucr_reg(int ucc_num, volatile u32 ** p_cmxucr, u8 * reg_num,
+ u8 * shift)
+{
+ switch (ucc_num) {
+ case (0):
+ *p_cmxucr = &(qe_immr->qmx.cmxucr1);
+ *reg_num = 1;
+ *shift = 16;
+ break;
+ case (2):
+ *p_cmxucr = &(qe_immr->qmx.cmxucr1);
+ *reg_num = 1;
+ *shift = 0;
+ break;
+ case (4):
+ *p_cmxucr = &(qe_immr->qmx.cmxucr2);
+ *reg_num = 2;
+ *shift = 16;
+ break;
+ case (6):
+ *p_cmxucr = &(qe_immr->qmx.cmxucr2);
+ *reg_num = 2;
+ *shift = 0;
+ break;
+ case (1):
+ *p_cmxucr = &(qe_immr->qmx.cmxucr3);
+ *reg_num = 3;
+ *shift = 16;
+ break;
+ case (3):
+ *p_cmxucr = &(qe_immr->qmx.cmxucr3);
+ *reg_num = 3;
+ *shift = 0;
+ break;
+ case (5):
+ *p_cmxucr = &(qe_immr->qmx.cmxucr4);
+ *reg_num = 4;
+ *shift = 16;
+ break;
+ case (7):
+ *p_cmxucr = &(qe_immr->qmx.cmxucr4);
+ *reg_num = 4;
+ *shift = 0;
+ break;
+ default:
+ break;
+ }
+}
+
+int ucc_mux_set_grant_tsa_bkpt(int ucc_num, int set, u32 mask)
+{
+ volatile u32 *p_cmxucr;
+ u8 reg_num;
+ u8 shift;
+
+ /* check if the UCC number is in range. */
+ if ((ucc_num > UCC_MAX_NUM - 1) || (ucc_num < 0))
+ return -EINVAL;
+
+ get_cmxucr_reg(ucc_num, &p_cmxucr, ®_num, &shift);
+
+ if (set)
+ out_be32(p_cmxucr, in_be32(p_cmxucr) | (mask << shift));
+ else
+ out_be32(p_cmxucr, in_be32(p_cmxucr) & ~(mask << shift));
+
+ return 0;
+}
+
+int ucc_set_qe_mux_rxtx(int ucc_num, qe_clock_e clock, comm_dir_e mode)
+{
+ volatile u32 *p_cmxucr;
+ u8 reg_num;
+ u8 shift;
+ u32 clockBits;
+ u32 clockMask;
+ int source = -1;
+
+ /* check if the UCC number is in range. */
+ if ((ucc_num > UCC_MAX_NUM - 1) || (ucc_num < 0))
+ return -EINVAL;
+
+ if (!((mode == COMM_DIR_RX) || (mode == COMM_DIR_TX))) {
+ printk(KERN_ERR
+ "ucc_set_qe_mux_rxtx: bad comm mode type passed.");
+ return -EINVAL;
+ }
+
+ get_cmxucr_reg(ucc_num, &p_cmxucr, ®_num, &shift);
+
+ switch (reg_num) {
+ case (1):
+ switch (clock) {
+ case (QE_BRG1):
+ source = 1;
+ break;
+ case (QE_BRG2):
+ source = 2;
+ break;
+ case (QE_BRG7):
+ source = 3;
+ break;
+ case (QE_BRG8):
+ source = 4;
+ break;
+ case (QE_CLK9):
+ source = 5;
+ break;
+ case (QE_CLK10):
+ source = 6;
+ break;
+ case (QE_CLK11):
+ source = 7;
+ break;
+ case (QE_CLK12):
+ source = 8;
+ break;
+ case (QE_CLK15):
+ source = 9;
+ break;
+ case (QE_CLK16):
+ source = 10;
+ break;
+ default:
+ source = -1;
+ break;
+ }
+ break;
+ case (2):
+ switch (clock) {
+ case (QE_BRG5):
+ source = 1;
+ break;
+ case (QE_BRG6):
+ source = 2;
+ break;
+ case (QE_BRG7):
+ source = 3;
+ break;
+ case (QE_BRG8):
+ source = 4;
+ break;
+ case (QE_CLK13):
+ source = 5;
+ break;
+ case (QE_CLK14):
+ source = 6;
+ break;
+ case (QE_CLK19):
+ source = 7;
+ break;
+ case (QE_CLK20):
+ source = 8;
+ break;
+ case (QE_CLK15):
+ source = 9;
+ break;
+ case (QE_CLK16):
+ source = 10;
+ break;
+ default:
+ source = -1;
+ break;
+ }
+ break;
+ case (3):
+ switch (clock) {
+ case (QE_BRG9):
+ source = 1;
+ break;
+ case (QE_BRG10):
+ source = 2;
+ break;
+ case (QE_BRG15):
+ source = 3;
+ break;
+ case (QE_BRG16):
+ source = 4;
+ break;
+ case (QE_CLK3):
+ source = 5;
+ break;
+ case (QE_CLK4):
+ source = 6;
+ break;
+ case (QE_CLK17):
+ source = 7;
+ break;
+ case (QE_CLK18):
+ source = 8;
+ break;
+ case (QE_CLK7):
+ source = 9;
+ break;
+ case (QE_CLK8):
+ source = 10;
+ break;
+ default:
+ source = -1;
+ break;
+ }
+ break;
+ case (4):
+ switch (clock) {
+ case (QE_BRG13):
+ source = 1;
+ break;
+ case (QE_BRG14):
+ source = 2;
+ break;
+ case (QE_BRG15):
+ source = 3;
+ break;
+ case (QE_BRG16):
+ source = 4;
+ break;
+ case (QE_CLK5):
+ source = 5;
+ break;
+ case (QE_CLK6):
+ source = 6;
+ break;
+ case (QE_CLK21):
+ source = 7;
+ break;
+ case (QE_CLK22):
+ source = 8;
+ break;
+ case (QE_CLK7):
+ source = 9;
+ break;
+ case (QE_CLK8):
+ source = 10;
+ break;
+ default:
+ source = -1;
+ break;
+ }
+ break;
+ default:
+ source = -1;
+ break;
+ }
+
+ if (source == -1) {
+ printk(KERN_ERR
+ "ucc_set_qe_mux_rxtx: Bad combination of clock and UCC.");
+ return -ENOENT;
+ }
+
+ clockBits = (u32) source;
+ clockMask = QE_CMXUCR_TX_CLK_SRC_MASK;
+ if (mode == COMM_DIR_RX) {
+ clockBits <<= 4; /* Rx field is 4 bits to left of Tx field */
+ clockMask <<= 4; /* Rx field is 4 bits to left of Tx field */
+ }
+ clockBits <<= shift;
+ clockMask <<= shift;
+
+ out_be32(p_cmxucr, (in_be32(p_cmxucr) & ~clockMask) | clockBits);
+
+ return 0;
+}
diff --git a/arch/powerpc/sysdev/qe_lib/ucc_fast.c b/arch/powerpc/sysdev/qe_lib/ucc_fast.c
new file mode 100644
index 0000000..4c94259
--- /dev/null
+++ b/arch/powerpc/sysdev/qe_lib/ucc_fast.c
@@ -0,0 +1,413 @@
+/*
+ * Copyright (C) Freescale Semicondutor, Inc. 2006. All rights reserved.
+ *
+ * Author: Shlomi Gridish <gridish@freescale.com>
+ *
+ * Description:
+ * QE UCC Fast API Set - UCC Fast specific routines implementations.
+ *
+ * Changelog:
+ * Jun 28, 2006 Li Yang <LeoLi@freescale.com>
+ * - Reorganized as qe_lib
+ * - Merged to powerpc arch; add device tree support
+ * - Style fixes
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/slab.h>
+#include <linux/stddef.h>
+#include <linux/interrupt.h>
+
+#include <asm/io.h>
+#include <asm/immap_qe.h>
+#include <asm/qe.h>
+
+#include <asm/ucc.h>
+#include <asm/ucc_fast.h>
+
+#define uccf_printk(level, format, arg...) \
+ printk(level format "\n", ## arg)
+
+#define uccf_dbg(format, arg...) \
+ uccf_printk(KERN_DEBUG , format , ## arg)
+#define uccf_err(format, arg...) \
+ uccf_printk(KERN_ERR , format , ## arg)
+#define uccf_info(format, arg...) \
+ uccf_printk(KERN_INFO , format , ## arg)
+#define uccf_warn(format, arg...) \
+ uccf_printk(KERN_WARNING , format , ## arg)
+
+#ifdef UCCF_VERBOSE_DEBUG
+#define uccf_vdbg uccf_dbg
+#else
+#define uccf_vdbg(fmt, args...) do { } while (0)
+#endif /* UCCF_VERBOSE_DEBUG */
+
+void ucc_fast_dump_regs(ucc_fast_private_t * uccf)
+{
+ uccf_info("UCC%d Fast registers:", uccf->uf_info->ucc_num);
+ uccf_info("Base address: 0x%08x", (u32) uccf->uf_regs);
+
+ uccf_info("gumr : addr - 0x%08x, val - 0x%08x",
+ (u32) & uccf->uf_regs->gumr, in_be32(&uccf->uf_regs->gumr));
+ uccf_info("upsmr : addr - 0x%08x, val - 0x%08x",
+ (u32) & uccf->uf_regs->upsmr, in_be32(&uccf->uf_regs->upsmr));
+ uccf_info("utodr : addr - 0x%08x, val - 0x%04x",
+ (u32) & uccf->uf_regs->utodr, in_be16(&uccf->uf_regs->utodr));
+ uccf_info("udsr : addr - 0x%08x, val - 0x%04x",
+ (u32) & uccf->uf_regs->udsr, in_be16(&uccf->uf_regs->udsr));
+ uccf_info("ucce : addr - 0x%08x, val - 0x%08x",
+ (u32) & uccf->uf_regs->ucce, in_be32(&uccf->uf_regs->ucce));
+ uccf_info("uccm : addr - 0x%08x, val - 0x%08x",
+ (u32) & uccf->uf_regs->uccm, in_be32(&uccf->uf_regs->uccm));
+ uccf_info("uccs : addr - 0x%08x, val - 0x%02x",
+ (u32) & uccf->uf_regs->uccs, uccf->uf_regs->uccs);
+ uccf_info("urfb : addr - 0x%08x, val - 0x%08x",
+ (u32) & uccf->uf_regs->urfb, in_be32(&uccf->uf_regs->urfb));
+ uccf_info("urfs : addr - 0x%08x, val - 0x%04x",
+ (u32) & uccf->uf_regs->urfs, in_be16(&uccf->uf_regs->urfs));
+ uccf_info("urfet : addr - 0x%08x, val - 0x%04x",
+ (u32) & uccf->uf_regs->urfet, in_be16(&uccf->uf_regs->urfet));
+ uccf_info("urfset: addr - 0x%08x, val - 0x%04x",
+ (u32) & uccf->uf_regs->urfset,
+ in_be16(&uccf->uf_regs->urfset));
+ uccf_info("utfb : addr - 0x%08x, val - 0x%08x",
+ (u32) & uccf->uf_regs->utfb, in_be32(&uccf->uf_regs->utfb));
+ uccf_info("utfs : addr - 0x%08x, val - 0x%04x",
+ (u32) & uccf->uf_regs->utfs, in_be16(&uccf->uf_regs->utfs));
+ uccf_info("utfet : addr - 0x%08x, val - 0x%04x",
+ (u32) & uccf->uf_regs->utfet, in_be16(&uccf->uf_regs->utfet));
+ uccf_info("utftt : addr - 0x%08x, val - 0x%04x",
+ (u32) & uccf->uf_regs->utftt, in_be16(&uccf->uf_regs->utftt));
+ uccf_info("utpt : addr - 0x%08x, val - 0x%04x",
+ (u32) & uccf->uf_regs->utpt, in_be16(&uccf->uf_regs->utpt));
+ uccf_info("urtry : addr - 0x%08x, val - 0x%08x",
+ (u32) & uccf->uf_regs->urtry, in_be32(&uccf->uf_regs->urtry));
+ uccf_info("guemr : addr - 0x%08x, val - 0x%02x",
+ (u32) & uccf->uf_regs->guemr, uccf->uf_regs->guemr);
+}
+
+u32 ucc_fast_get_qe_cr_subblock(int uccf_num)
+{
+ switch (uccf_num) {
+ case (0):
+ return (QE_CR_SUBBLOCK_UCCFAST1);
+ case (1):
+ return (QE_CR_SUBBLOCK_UCCFAST2);
+ case (2):
+ return (QE_CR_SUBBLOCK_UCCFAST3);
+ case (3):
+ return (QE_CR_SUBBLOCK_UCCFAST4);
+ case (4):
+ return (QE_CR_SUBBLOCK_UCCFAST5);
+ case (5):
+ return (QE_CR_SUBBLOCK_UCCFAST6);
+ case (6):
+ return (QE_CR_SUBBLOCK_UCCFAST7);
+ case (7):
+ return (QE_CR_SUBBLOCK_UCCFAST8);
+ default:
+ return QE_CR_SUBBLOCK_INVALID;
+ }
+}
+
+void ucc_fast_transmit_on_demand(ucc_fast_private_t * uccf)
+{
+ out_be16(&uccf->uf_regs->utodr, UCC_FAST_TOD);
+}
+
+void ucc_fast_enable(ucc_fast_private_t * uccf, comm_dir_e mode)
+{
+ ucc_fast_t *uf_regs;
+ u32 gumr;
+
+ uf_regs = uccf->uf_regs;
+
+ /* Enable reception and/or transmission on this UCC. */
+ gumr = in_be32(&uf_regs->gumr);
+ if (mode & COMM_DIR_TX) {
+ gumr |= UCC_FAST_GUMR_ENT;
+ uccf->enabled_tx = 1;
+ }
+ if (mode & COMM_DIR_RX) {
+ gumr |= UCC_FAST_GUMR_ENR;
+ uccf->enabled_rx = 1;
+ }
+ out_be32(&uf_regs->gumr, gumr);
+}
+
+void ucc_fast_disable(ucc_fast_private_t * uccf, comm_dir_e mode)
+{
+ ucc_fast_t *uf_regs;
+ u32 gumr;
+
+ uf_regs = uccf->uf_regs;
+
+ /* Disable reception and/or transmission on this UCC. */
+ gumr = in_be32(&uf_regs->gumr);
+ if (mode & COMM_DIR_TX) {
+ gumr &= ~UCC_FAST_GUMR_ENT;
+ uccf->enabled_tx = 0;
+ }
+ if (mode & COMM_DIR_RX) {
+ gumr &= ~UCC_FAST_GUMR_ENR;
+ uccf->enabled_rx = 0;
+ }
+ out_be32(&uf_regs->gumr, gumr);
+}
+
+int ucc_fast_init(ucc_fast_info_t * uf_info, ucc_fast_private_t ** uccf_ret)
+{
+ ucc_fast_private_t *uccf;
+ ucc_fast_t *uf_regs;
+ u32 gumr = 0;
+ int ret;
+
+ uccf_vdbg("%s: IN", __FUNCTION__);
+
+ if (!uf_info)
+ return -EINVAL;
+
+ /* check if the UCC port number is in range. */
+ if ((uf_info->ucc_num < 0) || (uf_info->ucc_num > UCC_MAX_NUM - 1)) {
+ uccf_err("ucc_fast_init: Illagal UCC number!");
+ return -EINVAL;
+ }
+
+ /* Check that 'max_rx_buf_length' is properly aligned (4). */
+ if (uf_info->max_rx_buf_length & (UCC_FAST_MRBLR_ALIGNMENT - 1)) {
+ uccf_err("ucc_fast_init: max_rx_buf_length not aligned.");
+ return -EINVAL;
+ }
+
+ /* Validate Virtual Fifo register values */
+ if (uf_info->urfs < UCC_FAST_URFS_MIN_VAL) {
+ uccf_err
+ ("ucc_fast_init: Virtual Fifo register urfs too small.");
+ return -EINVAL;
+ }
+
+ if (uf_info->urfs & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) {
+ uccf_err
+ ("ucc_fast_init: Virtual Fifo register urfs not aligned.");
+ return -EINVAL;
+ }
+
+ if (uf_info->urfet & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) {
+ uccf_err
+ ("ucc_fast_init: Virtual Fifo register urfet not aligned.");
+ return -EINVAL;
+ }
+
+ if (uf_info->urfset & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) {
+ uccf_err
+ ("ucc_fast_init: Virtual Fifo register urfset not aligned.");
+ return -EINVAL;
+ }
+
+ if (uf_info->utfs & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) {
+ uccf_err
+ ("ucc_fast_init: Virtual Fifo register utfs not aligned.");
+ return -EINVAL;
+ }
+
+ if (uf_info->utfet & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) {
+ uccf_err
+ ("ucc_fast_init: Virtual Fifo register utfet not aligned.");
+ return -EINVAL;
+ }
+
+ if (uf_info->utftt & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) {
+ uccf_err
+ ("ucc_fast_init: Virtual Fifo register utftt not aligned.");
+ return -EINVAL;
+ }
+
+ uccf =
+ (ucc_fast_private_t *) kmalloc(sizeof(ucc_fast_private_t),
+ GFP_KERNEL);
+ if (!uccf) {
+ uccf_err
+ ("ucc_fast_init: No memory for UCC slow data structure!");
+ return -ENOMEM;
+ }
+ memset(uccf, 0, sizeof(ucc_fast_private_t));
+
+ /* Fill fast UCC structure */
+ uccf->uf_info = uf_info;
+ /* Set the PHY base address */
+ uccf->uf_regs =
+ (ucc_fast_t *) ioremap(uf_info->regs, sizeof(ucc_fast_t));
+ if (uccf->uf_regs == NULL) {
+ uccf_err
+ ("ucc_fast_init: No memory map for UCC slow controller!");
+ return -ENOMEM;
+ }
+
+ uccf->enabled_tx = 0;
+ uccf->enabled_rx = 0;
+ uccf->stopped_tx = 0;
+ uccf->stopped_rx = 0;
+ uf_regs = uccf->uf_regs;
+ uccf->p_ucce = (u32 *) & (uf_regs->ucce);
+ uccf->p_uccm = (u32 *) & (uf_regs->uccm);
+#ifdef STATISTICS
+ uccf->tx_frames = 0;
+ uccf->rx_frames = 0;
+ uccf->rx_discarded = 0;
+#endif /* STATISTICS */
+
+ /* Init Guemr register */
+ if ((ret = ucc_init_guemr((ucc_common_t *) (uf_regs)))) {
+ uccf_err("ucc_fast_init: Could not init the guemr register.");
+ ucc_fast_free(uccf);
+ return ret;
+ }
+
+ /* Set UCC to fast type */
+ if ((ret = ucc_set_type(uf_info->ucc_num,
+ (ucc_common_t *) (uf_regs),
+ UCC_SPEED_TYPE_FAST))) {
+ uccf_err("ucc_fast_init: Could not set type to fast.");
+ ucc_fast_free(uccf);
+ return ret;
+ }
+
+ uccf->mrblr = uf_info->max_rx_buf_length;
+
+ /* Set GUMR. */
+ /* For more details see the hardware spec. */
+ /* gumr starts as zero. */
+ if (uf_info->tci)
+ gumr |= UCC_FAST_GUMR_TCI;
+ gumr |= uf_info->ttx_trx;
+ if (uf_info->cdp)
+ gumr |= UCC_FAST_GUMR_CDP;
+ if (uf_info->ctsp)
+ gumr |= UCC_FAST_GUMR_CTSP;
+ if (uf_info->cds)
+ gumr |= UCC_FAST_GUMR_CDS;
+ if (uf_info->ctss)
+ gumr |= UCC_FAST_GUMR_CTSS;
+ if (uf_info->txsy)
+ gumr |= UCC_FAST_GUMR_TXSY;
+ if (uf_info->rsyn)
+ gumr |= UCC_FAST_GUMR_RSYN;
+ gumr |= uf_info->synl;
+ if (uf_info->rtsm)
+ gumr |= UCC_FAST_GUMR_RTSM;
+ gumr |= uf_info->renc;
+ if (uf_info->revd)
+ gumr |= UCC_FAST_GUMR_REVD;
+ gumr |= uf_info->tenc;
+ gumr |= uf_info->tcrc;
+ gumr |= uf_info->mode;
+ out_be32(&uf_regs->gumr, gumr);
+
+ /* Allocate memory for Tx Virtual Fifo */
+ uccf->ucc_fast_tx_virtual_fifo_base_offset =
+ qe_muram_alloc(uf_info->utfs, UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT);
+ if (IS_MURAM_ERR(uccf->ucc_fast_tx_virtual_fifo_base_offset)) {
+ uccf_err
+ ("ucc_fast_init: Can not allocate MURAM memory for "
+ "ucc_fast_tx_virtual_fifo_base_offset.");
+ uccf->ucc_fast_tx_virtual_fifo_base_offset = 0;
+ ucc_fast_free(uccf);
+ return -ENOMEM;
+ }
+
+ /* Allocate memory for Rx Virtual Fifo */
+ uccf->ucc_fast_rx_virtual_fifo_base_offset =
+ qe_muram_alloc(uf_info->urfs +
+ (u32)
+ UCC_FAST_RECEIVE_VIRTUAL_FIFO_SIZE_FUDGE_FACTOR,
+ UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT);
+ if (IS_MURAM_ERR(uccf->ucc_fast_rx_virtual_fifo_base_offset)) {
+ uccf_err
+ ("ucc_fast_init: Can not allocate MURAM memory for "
+ "ucc_fast_rx_virtual_fifo_base_offset.");
+ uccf->ucc_fast_rx_virtual_fifo_base_offset = 0;
+ ucc_fast_free(uccf);
+ return -ENOMEM;
+ }
+
+ /* Set Virtual Fifo registers */
+ out_be16(&uf_regs->urfs, uf_info->urfs);
+ out_be16(&uf_regs->urfet, uf_info->urfet);
+ out_be16(&uf_regs->urfset, uf_info->urfset);
+ out_be16(&uf_regs->utfs, uf_info->utfs);
+ out_be16(&uf_regs->utfet, uf_info->utfet);
+ out_be16(&uf_regs->utftt, uf_info->utftt);
+ /* utfb, urfb are offsets from MURAM base */
+ out_be32(&uf_regs->utfb, uccf->ucc_fast_tx_virtual_fifo_base_offset);
+ out_be32(&uf_regs->urfb, uccf->ucc_fast_rx_virtual_fifo_base_offset);
+
+ /* Mux clocking */
+ /* Grant Support */
+ ucc_set_qe_mux_grant(uf_info->ucc_num, uf_info->grant_support);
+ /* Breakpoint Support */
+ ucc_set_qe_mux_bkpt(uf_info->ucc_num, uf_info->brkpt_support);
+ /* Set Tsa or NMSI mode. */
+ ucc_set_qe_mux_tsa(uf_info->ucc_num, uf_info->tsa);
+ /* If NMSI (not Tsa), set Tx and Rx clock. */
+ if (!uf_info->tsa) {
+ /* Rx clock routing */
+ if (uf_info->rx_clock != QE_CLK_NONE) {
+ if (ucc_set_qe_mux_rxtx
+ (uf_info->ucc_num, uf_info->rx_clock,
+ COMM_DIR_RX)) {
+ uccf_err
+ ("ucc_fast_init: Illegal value for parameter 'RxClock'.");
+ ucc_fast_free(uccf);
+ return -EINVAL;
+ }
+ }
+ /* Tx clock routing */
+ if (uf_info->tx_clock != QE_CLK_NONE) {
+ if (ucc_set_qe_mux_rxtx
+ (uf_info->ucc_num, uf_info->tx_clock,
+ COMM_DIR_TX)) {
+ uccf_err
+ ("ucc_fast_init: Illegal value for parameter 'TxClock'.");
+ ucc_fast_free(uccf);
+ return -EINVAL;
+ }
+ }
+ }
+
+ /*
+ * INTERRUPTS
+ */
+ /* Set interrupt mask register at UCC level. */
+ out_be32(&uf_regs->uccm, uf_info->uccm_mask);
+
+ /* First, clear anything pending at UCC level, */
+ /* otherwise, old garbage may come through */
+ /* as soon as the dam is opened. */
+
+ /* Writing '1' clears */
+ out_be32(&uf_regs->ucce, 0xffffffff);
+
+ *uccf_ret = uccf;
+ return 0;
+}
+
+void ucc_fast_free(ucc_fast_private_t * uccf)
+{
+ if (!uccf)
+ return;
+
+ if (uccf->ucc_fast_tx_virtual_fifo_base_offset)
+ qe_muram_free(uccf->ucc_fast_tx_virtual_fifo_base_offset);
+
+ if (uccf->ucc_fast_rx_virtual_fifo_base_offset)
+ qe_muram_free(uccf->ucc_fast_rx_virtual_fifo_base_offset);
+
+ kfree(uccf);
+}
diff --git a/arch/powerpc/sysdev/qe_lib/ucc_slow.c b/arch/powerpc/sysdev/qe_lib/ucc_slow.c
new file mode 100644
index 0000000..9ded1b5
--- /dev/null
+++ b/arch/powerpc/sysdev/qe_lib/ucc_slow.c
@@ -0,0 +1,411 @@
+/*
+ * Copyright (C) Freescale Semicondutor, Inc. 2006. All rights reserved.
+ *
+ * Author: Shlomi Gridish <gridish@freescale.com>
+ *
+ * Description:
+ * QE UCC Slow API Set - UCC Slow specific routines implementations.
+ *
+ * Changelog:
+ * Jun 28, 2006 Li Yang <LeoLi@freescale.com>
+ * - Reorganized as qe_lib
+ * - Merged to powerpc arch; add device tree support
+ * - Style fixes
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/slab.h>
+#include <linux/stddef.h>
+#include <linux/interrupt.h>
+
+#include <asm/irq.h>
+#include <asm/io.h>
+#include <asm/immap_qe.h>
+#include <asm/qe.h>
+
+#include <asm/ucc.h>
+#include <asm/ucc_slow.h>
+
+#define uccs_printk(level, format, arg...) \
+ printk(level format "\n", ## arg)
+
+#define uccs_dbg(format, arg...) \
+ uccs_printk(KERN_DEBUG , format , ## arg)
+#define uccs_err(format, arg...) \
+ uccs_printk(KERN_ERR , format , ## arg)
+#define uccs_info(format, arg...) \
+ uccs_printk(KERN_INFO , format , ## arg)
+#define uccs_warn(format, arg...) \
+ uccs_printk(KERN_WARNING , format , ## arg)
+
+#ifdef UCCS_VERBOSE_DEBUG
+#define uccs_vdbg uccs_dbg
+#else
+#define uccs_vdbg(fmt, args...) do { } while (0)
+#endif /* UCCS_VERBOSE_DEBUG */
+
+u32 ucc_slow_get_qe_cr_subblock(int uccs_num)
+{
+ switch (uccs_num) {
+ case (0):
+ return (QE_CR_SUBBLOCK_UCCSLOW1);
+ case (1):
+ return (QE_CR_SUBBLOCK_UCCSLOW2);
+ case (2):
+ return (QE_CR_SUBBLOCK_UCCSLOW3);
+ case (3):
+ return (QE_CR_SUBBLOCK_UCCSLOW4);
+ case (4):
+ return (QE_CR_SUBBLOCK_UCCSLOW5);
+ case (5):
+ return (QE_CR_SUBBLOCK_UCCSLOW6);
+ case (6):
+ return (QE_CR_SUBBLOCK_UCCSLOW7);
+ case (7):
+ return (QE_CR_SUBBLOCK_UCCSLOW8);
+ default:
+ return QE_CR_SUBBLOCK_INVALID;
+ }
+}
+
+void ucc_slow_poll_transmitter_now(ucc_slow_private_t * uccs)
+{
+ out_be16(&uccs->us_regs->utodr, UCC_SLOW_TOD);
+}
+
+void ucc_slow_graceful_stop_tx(ucc_slow_private_t * uccs)
+{
+ ucc_slow_info_t *us_info = uccs->us_info;
+ u32 id;
+
+ id = ucc_slow_get_qe_cr_subblock(us_info->ucc_num);
+ qe_issue_cmd(QE_GRACEFUL_STOP_TX, id, (u8) QE_CR_PROTOCOL_UNSPECIFIED,
+ 0);
+}
+
+void ucc_slow_stop_tx(ucc_slow_private_t * uccs)
+{
+ ucc_slow_info_t *us_info = uccs->us_info;
+ u32 id;
+
+ id = ucc_slow_get_qe_cr_subblock(us_info->ucc_num);
+ qe_issue_cmd(QE_STOP_TX, id, (u8) QE_CR_PROTOCOL_UNSPECIFIED, 0);
+}
+
+void ucc_slow_restart_tx(ucc_slow_private_t * uccs)
+{
+ ucc_slow_info_t *us_info = uccs->us_info;
+ u32 id;
+
+ id = ucc_slow_get_qe_cr_subblock(us_info->ucc_num);
+ qe_issue_cmd(QE_RESTART_TX, id, (u8) QE_CR_PROTOCOL_UNSPECIFIED, 0);
+}
+
+void ucc_slow_enable(ucc_slow_private_t * uccs, comm_dir_e mode)
+{
+ ucc_slow_t *us_regs;
+ u32 gumr_l;
+
+ us_regs = uccs->us_regs;
+
+ /* Enable reception and/or transmission on this UCC. */
+ gumr_l = in_be32(&us_regs->gumr_l);
+ if (mode & COMM_DIR_TX) {
+ gumr_l |= UCC_SLOW_GUMR_L_ENT;
+ uccs->enabled_tx = 1;
+ }
+ if (mode & COMM_DIR_RX) {
+ gumr_l |= UCC_SLOW_GUMR_L_ENR;
+ uccs->enabled_rx = 1;
+ }
+ out_be32(&us_regs->gumr_l, gumr_l);
+}
+
+void ucc_slow_disable(ucc_slow_private_t * uccs, comm_dir_e mode)
+{
+ ucc_slow_t *us_regs;
+ u32 gumr_l;
+
+ us_regs = uccs->us_regs;
+
+ /* Disable reception and/or transmission on this UCC. */
+ gumr_l = in_be32(&us_regs->gumr_l);
+ if (mode & COMM_DIR_TX) {
+ gumr_l &= ~UCC_SLOW_GUMR_L_ENT;
+ uccs->enabled_tx = 0;
+ }
+ if (mode & COMM_DIR_RX) {
+ gumr_l &= ~UCC_SLOW_GUMR_L_ENR;
+ uccs->enabled_rx = 0;
+ }
+ out_be32(&us_regs->gumr_l, gumr_l);
+}
+
+int ucc_slow_init(ucc_slow_info_t * us_info, ucc_slow_private_t ** uccs_ret)
+{
+ u32 i;
+ ucc_slow_t *us_regs;
+ u32 gumr;
+ u8 function_code = 0;
+ u8 *bd;
+ ucc_slow_private_t *uccs;
+ u32 id;
+ u32 command;
+ int ret;
+
+ uccs_vdbg("%s: IN", __FUNCTION__);
+
+ if (!us_info)
+ return -EINVAL;
+
+ /* check if the UCC port number is in range. */
+ if ((us_info->ucc_num < 0) || (us_info->ucc_num > UCC_MAX_NUM - 1)) {
+ uccs_err("ucc_slow_init: Illagal UCC number!");
+ return -EINVAL;
+ }
+
+ /* Set mrblr */
+ /* Check that 'max_rx_buf_length' is properly aligned (4), unless
+ rfw is 1, meaning that QE accepts one byte at a time, unlike normal
+ case when QE accepts 32 bits at a time. */
+ if ((!us_info->rfw)
+ && (us_info->max_rx_buf_length & (UCC_SLOW_MRBLR_ALIGNMENT - 1))) {
+ uccs_err("max_rx_buf_length not aligned.");
+ return -EINVAL;
+ }
+
+ uccs =
+ (ucc_slow_private_t *) kmalloc(sizeof(ucc_slow_private_t),
+ GFP_KERNEL);
+ if (!uccs) {
+ uccs_err
+ ("ucc_slow_init: No memory for UCC slow data structure!");
+ return -ENOMEM;
+ }
+ memset(uccs, 0, sizeof(ucc_slow_private_t));
+
+ /* Fill slow UCC structure */
+ uccs->us_info = us_info;
+ uccs->saved_uccm = 0;
+ uccs->p_rx_frame = 0;
+ uccs->us_regs = us_info->us_regs;
+ us_regs = uccs->us_regs;
+ uccs->p_ucce = (u16 *) & (us_regs->ucce);
+ uccs->p_uccm = (u16 *) & (us_regs->uccm);
+#ifdef STATISTICS
+ uccs->rx_frames = 0;
+ uccs->tx_frames = 0;
+ uccs->rx_discarded = 0;
+#endif /* STATISTICS */
+
+ /* Get PRAM base */
+ uccs->us_pram_offset =
+ qe_muram_alloc(UCC_SLOW_PRAM_SIZE, ALIGNMENT_OF_UCC_SLOW_PRAM);
+ if (IS_MURAM_ERR(uccs->us_pram_offset)) {
+ uccs_err
+ ("ucc_slow_init: Can not allocate MURAM memory " \
+ "for Slow UCC.");
+ ucc_slow_free(uccs);
+ return -ENOMEM;
+ }
+ id = ucc_slow_get_qe_cr_subblock(us_info->ucc_num);
+ qe_issue_cmd(QE_ASSIGN_PAGE_TO_DEVICE, id, QE_CR_PROTOCOL_UNSPECIFIED,
+ (u32) uccs->us_pram_offset);
+
+ uccs->us_pram = qe_muram_addr(uccs->us_pram_offset);
+
+ /* Init Guemr register */
+ if ((ret = ucc_init_guemr((ucc_common_t *) (us_info->us_regs)))) {
+ uccs_err("ucc_slow_init: Could not init the guemr register.");
+ ucc_slow_free(uccs);
+ return ret;
+ }
+
+ /* Set UCC to slow type */
+ if ((ret = ucc_set_type(us_info->ucc_num,
+ (ucc_common_t *) (us_info->us_regs),
+ UCC_SPEED_TYPE_SLOW))) {
+ uccs_err("ucc_slow_init: Could not init the guemr register.");
+ ucc_slow_free(uccs);
+ return ret;
+ }
+
+ out_be16(&uccs->us_pram->mrblr, us_info->max_rx_buf_length);
+
+ INIT_LIST_HEAD(&uccs->confQ);
+
+ /* Allocate BDs. */
+ uccs->rx_base_offset =
+ qe_muram_alloc(us_info->rx_bd_ring_len * UCC_SLOW_SIZE_OF_BD,
+ QE_ALIGNMENT_OF_BD);
+ if (IS_MURAM_ERR(uccs->rx_base_offset)) {
+ uccs_err("ucc_slow_init: No memory for Rx BD's.");
+ uccs->rx_base_offset = 0;
+ ucc_slow_free(uccs);
+ return -ENOMEM;
+ }
+
+ uccs->tx_base_offset =
+ qe_muram_alloc(us_info->tx_bd_ring_len * UCC_SLOW_SIZE_OF_BD,
+ QE_ALIGNMENT_OF_BD);
+ if (IS_MURAM_ERR(uccs->tx_base_offset)) {
+ uccs_err("ucc_slow_init: No memory for Tx BD's.");
+ uccs->tx_base_offset = 0;
+ ucc_slow_free(uccs);
+ return -ENOMEM;
+ }
+
+ /* Init Tx bds */
+ bd = uccs->confBd = uccs->tx_bd = qe_muram_addr(uccs->tx_base_offset);
+ for (i = 0; i < us_info->tx_bd_ring_len; i++) {
+ BD_BUFFER_CLEAR(bd);
+ BD_STATUS_AND_LENGTH_SET(bd, 0);
+ bd += QE_SIZEOF_BD;
+ }
+ bd -= QE_SIZEOF_BD;
+ BD_STATUS_AND_LENGTH_SET(bd, T_W); /* for last BD set Wrap bit */
+
+ /* Init Rx bds */
+ bd = uccs->rx_bd = qe_muram_addr(uccs->rx_base_offset);
+ for (i = 0; i < us_info->rx_bd_ring_len; i++) {
+ BD_STATUS_AND_LENGTH_SET(bd, 0);
+ BD_BUFFER_CLEAR(bd);
+ bd += QE_SIZEOF_BD;
+ }
+ bd -= QE_SIZEOF_BD;
+ BD_STATUS_AND_LENGTH_SET(bd, R_W); /* for last BD set Wrap bit */
+
+ /* Set GUMR (For more details see the hardware spec.). */
+ /* gumr_h */
+ gumr = 0;
+ gumr |= us_info->tcrc;
+ if (us_info->cdp)
+ gumr |= UCC_SLOW_GUMR_H_CDP;
+ if (us_info->ctsp)
+ gumr |= UCC_SLOW_GUMR_H_CTSP;
+ if (us_info->cds)
+ gumr |= UCC_SLOW_GUMR_H_CDS;
+ if (us_info->ctss)
+ gumr |= UCC_SLOW_GUMR_H_CTSS;
+ if (us_info->tfl)
+ gumr |= UCC_SLOW_GUMR_H_TFL;
+ if (us_info->rfw)
+ gumr |= UCC_SLOW_GUMR_H_RFW;
+ if (us_info->txsy)
+ gumr |= UCC_SLOW_GUMR_H_TXSY;
+ if (us_info->rtsm)
+ gumr |= UCC_SLOW_GUMR_H_RTSM;
+ out_be32(&us_regs->gumr_h, gumr);
+
+ /* gumr_l */
+ gumr = 0;
+ if (us_info->tci)
+ gumr |= UCC_SLOW_GUMR_L_TCI;
+ if (us_info->rinv)
+ gumr |= UCC_SLOW_GUMR_L_RINV;
+ if (us_info->tinv)
+ gumr |= UCC_SLOW_GUMR_L_TINV;
+ if (us_info->tend)
+ gumr |= UCC_SLOW_GUMR_L_TEND;
+ gumr |= us_info->tdcr;
+ gumr |= us_info->rdcr;
+ gumr |= us_info->tenc;
+ gumr |= us_info->renc;
+ gumr |= us_info->diag;
+ gumr |= us_info->mode;
+ out_be32(&us_regs->gumr_l, gumr);
+
+ /* Function code registers */
+ /* function_code has initial value 0 */
+
+ /* if the data is in cachable memory, the 'global' */
+ /* in the function code should be set. */
+ function_code |= us_info->data_mem_part;
+ function_code |= QE_BMR_BYTE_ORDER_BO_MOT; /* Required for QE */
+ uccs->us_pram->tfcr = function_code;
+ uccs->us_pram->rfcr = function_code;
+
+ /* rbase, tbase are offsets from MURAM base */
+ out_be16(&uccs->us_pram->rbase, uccs->us_pram_offset);
+ out_be16(&uccs->us_pram->tbase, uccs->us_pram_offset);
+
+ /* Mux clocking */
+ /* Grant Support */
+ ucc_set_qe_mux_grant(us_info->ucc_num, us_info->grant_support);
+ /* Breakpoint Support */
+ ucc_set_qe_mux_bkpt(us_info->ucc_num, us_info->brkpt_support);
+ /* Set Tsa or NMSI mode. */
+ ucc_set_qe_mux_tsa(us_info->ucc_num, us_info->tsa);
+ /* If NMSI (not Tsa), set Tx and Rx clock. */
+ if (!us_info->tsa) {
+ /* Rx clock routing */
+ if (ucc_set_qe_mux_rxtx
+ (us_info->ucc_num, us_info->rx_clock, COMM_DIR_RX)) {
+ uccs_err
+ ("ucc_slow_init: Illegal value for parameter" \
+ " 'RxClock'.");
+ ucc_slow_free(uccs);
+ return -EINVAL;
+ }
+ /* Tx clock routing */
+ if (ucc_set_qe_mux_rxtx
+ (us_info->ucc_num, us_info->tx_clock, COMM_DIR_TX)) {
+ uccs_err
+ ("ucc_slow_init: Illegal value for parameter " \
+ "'TxClock'.");
+ ucc_slow_free(uccs);
+ return -EINVAL;
+ }
+ }
+
+ /*
+ * INTERRUPTS
+ */
+ /* Set interrupt mask register at UCC level. */
+ out_be16(&us_regs->uccm, us_info->uccm_mask);
+
+ /* First, clear anything pending at UCC level, */
+ /* otherwise, old garbage may come through */
+ /* as soon as the dam is opened. */
+
+ /* Writing '1' clears */
+ out_be16(&us_regs->ucce, 0xffff);
+
+ /* Issue QE Init command */
+ if (us_info->init_tx && us_info->init_rx)
+ command = QE_INIT_TX_RX;
+ else if (us_info->init_tx)
+ command = QE_INIT_TX;
+ else
+ command = QE_INIT_RX; /* We know at least one is TRUE */
+ id = ucc_slow_get_qe_cr_subblock(us_info->ucc_num);
+ qe_issue_cmd(command, id, (u8) QE_CR_PROTOCOL_UNSPECIFIED, 0);
+
+ *uccs_ret = uccs;
+ return 0;
+}
+
+void ucc_slow_free(ucc_slow_private_t * uccs)
+{
+ if (!uccs)
+ return;
+
+ if (uccs->rx_base_offset)
+ qe_muram_free(uccs->rx_base_offset);
+
+ if (uccs->tx_base_offset)
+ qe_muram_free(uccs->tx_base_offset);
+
+ if (uccs->us_pram) {
+ qe_muram_free(uccs->us_pram_offset);
+ uccs->us_pram = NULL;
+ }
+
+ kfree(uccs);
+}
^ permalink raw reply related
* [PATCH 5/7] powerpc: Add QE library qe_lib--common headers
From: Li Yang-r58472 @ 2006-06-28 14:23 UTC (permalink / raw)
To: 'Paul Mackerras'
Cc: Gridish Shlomi-RM96313, linuxppc-dev, Phillips Kim-R1AAHA,
'linux-kernel@vger.kernel.org', Chu hanjin-r52514
Signed-off-by: Shlomi Gridish <gridish@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
---
include/asm-powerpc/immap_qe.h | 509 ++++++++++++++++++++++++++++++++++++++++
include/asm-powerpc/irq.h | 11 +
include/asm-powerpc/qe.h | 498 +++++++++++++++++++++++++++++++++++++++
include/asm-powerpc/qe_ic.h | 131 ++++++++++
include/asm-powerpc/ucc.h | 89 +++++++
include/asm-powerpc/ucc_fast.h | 259 ++++++++++++++++++++
include/asm-powerpc/ucc_slow.h | 309 ++++++++++++++++++++++++
include/asm-ppc/mpc83xx.h | 42 +++
include/linux/fsl_devices.h | 39 +++
9 files changed, 1885 insertions(+), 2 deletions(-)
diff --git a/include/asm-powerpc/immap_qe.h b/include/asm-powerpc/immap_qe.h
new file mode 100644
index 0000000..a392431
--- /dev/null
+++ b/include/asm-powerpc/immap_qe.h
@@ -0,0 +1,509 @@
+/*
+ * Copyright (C) Freescale Semicondutor, Inc. 2006. All rights reserved.
+ *
+ * Author: Shlomi Gridish <gridish@freescale.com>
+ *
+ * Description:
+ * QUICC Engine (QE) Internal Memory Map.
+ * The Internal Memory Map for devices with QE on them. This
+ * is the superset of all QE devices (8360, etc.).
+ *
+ * Changelog:
+ * Jun 28, 2006 Li Yang <LeoLi@freescale.com>
+ * - Reorganized as qe_lib
+ * - Merged to powerpc arch; add device tree support
+ * - Style fixes
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+#ifdef __KERNEL__
+#ifndef __IMMAP_QE_H__
+#define __IMMAP_QE_H__
+
+#include <linux/kernel.h>
+
+#define QE_IMMAP_SIZE (1024 * 1024) /* 1MB from 1MB+IMMR */
+
+/* QE I-RAM
+*/
+typedef struct qe_iram {
+ u32 iadd; /* I-RAM Address Register */
+ u32 idata; /* I-RAM Data Register */
+ u8 res0[0x78];
+} __attribute__ ((packed)) qe_iram_t;
+
+/* QE Interrupt Controller
+*/
+typedef struct qe_ic {
+ u32 qicr;
+ u32 qivec;
+ u32 qripnr;
+ u32 qipnr;
+ u32 qipxcc;
+ u32 qipycc;
+ u32 qipwcc;
+ u32 qipzcc;
+ u32 qimr;
+ u32 qrimr;
+ u32 qicnr;
+ u8 res0[0x4];
+ u32 qiprta;
+ u32 qiprtb;
+ u8 res1[0x4];
+ u32 qricr;
+ u8 res2[0x20];
+ u32 qhivec;
+ u8 res3[0x1C];
+} __attribute__ ((packed)) qe_ic_t;
+
+/* Communications Processor
+*/
+typedef struct cp_qe {
+ u32 cecr; /* QE command register */
+ u32 ceccr; /* QE controller configuration register */
+ u32 cecdr; /* QE command data register */
+ u8 res0[0xA];
+ u16 ceter; /* QE timer event register */
+ u8 res1[0x2];
+ u16 cetmr; /* QE timers mask register */
+ u32 cetscr; /* QE time-stamp timer control register */
+ u32 cetsr1; /* QE time-stamp register 1 */
+ u32 cetsr2; /* QE time-stamp register 2 */
+ u8 res2[0x8];
+ u32 cevter; /* QE virtual tasks event register */
+ u32 cevtmr; /* QE virtual tasks mask register */
+ u16 cercr; /* QE RAM control register */
+ u8 res3[0x2];
+ u8 res4[0x24];
+ u16 ceexe1; /* QE external request 1 event register */
+ u8 res5[0x2];
+ u16 ceexm1; /* QE external request 1 mask register */
+ u8 res6[0x2];
+ u16 ceexe2; /* QE external request 2 event register */
+ u8 res7[0x2];
+ u16 ceexm2; /* QE external request 2 mask register */
+ u8 res8[0x2];
+ u16 ceexe3; /* QE external request 3 event register */
+ u8 res9[0x2];
+ u16 ceexm3; /* QE external request 3 mask register */
+ u8 res10[0x2];
+ u16 ceexe4; /* QE external request 4 event register */
+ u8 res11[0x2];
+ u16 ceexm4; /* QE external request 4 mask register */
+ u8 res12[0x2];
+ u8 res13[0x280];
+} __attribute__ ((packed)) cp_qe_t;
+
+/* QE Multiplexer
+*/
+typedef struct qe_mux {
+ u32 cmxgcr; /* CMX general clock route register */
+ u32 cmxsi1cr_l; /* CMX SI1 clock route low register */
+ u32 cmxsi1cr_h; /* CMX SI1 clock route high register */
+ u32 cmxsi1syr; /* CMX SI1 SYNC route register */
+ u32 cmxucr1; /* CMX UCC1, UCC3 clock route register */
+ u32 cmxucr2; /* CMX UCC5, UCC7 clock route register */
+ u32 cmxucr3; /* CMX UCC2, UCC4 clock route register */
+ u32 cmxucr4; /* CMX UCC6, UCC8 clock route register */
+ u32 cmxupcr; /* CMX UPC clock route register */
+ u8 res0[0x1C];
+} __attribute__ ((packed)) qe_mux_t;
+
+/* QE Timers
+*/
+typedef struct qe_timers {
+ u8 gtcfr1; /* Timer 1 and Timer 2 global configuration
+ register */
+ u8 res0[0x3];
+ u8 gtcfr2; /* Timer 3 and timer 4 global configuration
+ register */
+ u8 res1[0xB];
+ u16 gtmdr1; /* Timer 1 mode register */
+ u16 gtmdr2; /* Timer 2 mode register */
+ u16 gtrfr1; /* Timer 1 reference register */
+ u16 gtrfr2; /* Timer 2 reference register */
+ u16 gtcpr1; /* Timer 1 capture register */
+ u16 gtcpr2; /* Timer 2 capture register */
+ u16 gtcnr1; /* Timer 1 counter */
+ u16 gtcnr2; /* Timer 2 counter */
+ u16 gtmdr3; /* Timer 3 mode register */
+ u16 gtmdr4; /* Timer 4 mode register */
+ u16 gtrfr3; /* Timer 3 reference register */
+ u16 gtrfr4; /* Timer 4 reference register */
+ u16 gtcpr3; /* Timer 3 capture register */
+ u16 gtcpr4; /* Timer 4 capture register */
+ u16 gtcnr3; /* Timer 3 counter */
+ u16 gtcnr4; /* Timer 4 counter */
+ u16 gtevr1; /* Timer 1 event register */
+ u16 gtevr2; /* Timer 2 event register */
+ u16 gtevr3; /* Timer 3 event register */
+ u16 gtevr4; /* Timer 4 event register */
+ u16 gtps; /* Timer 1 prescale register */
+ u8 res2[0x46];
+} __attribute__ ((packed)) qe_timers_t;
+
+/* BRG
+*/
+typedef struct qe_brg {
+ u32 brgc1; /* BRG1 configuration register */
+ u32 brgc2; /* BRG2 configuration register */
+ u32 brgc3; /* BRG3 configuration register */
+ u32 brgc4; /* BRG4 configuration register */
+ u32 brgc5; /* BRG5 configuration register */
+ u32 brgc6; /* BRG6 configuration register */
+ u32 brgc7; /* BRG7 configuration register */
+ u32 brgc8; /* BRG8 configuration register */
+ u32 brgc9; /* BRG9 configuration register */
+ u32 brgc10; /* BRG10 configuration register */
+ u32 brgc11; /* BRG11 configuration register */
+ u32 brgc12; /* BRG12 configuration register */
+ u32 brgc13; /* BRG13 configuration register */
+ u32 brgc14; /* BRG14 configuration register */
+ u32 brgc15; /* BRG15 configuration register */
+ u32 brgc16; /* BRG16 configuration register */
+ u8 res0[0x40];
+} __attribute__ ((packed)) qe_brg_t;
+
+/* SPI
+*/
+typedef struct spi {
+ u8 res0[0x20];
+ u32 spmode; /* SPI mode register */
+ u8 res1[0x2];
+ u8 spie; /* SPI event register */
+ u8 res2[0x1];
+ u8 res3[0x2];
+ u8 spim; /* SPI mask register */
+ u8 res4[0x1];
+ u8 res5[0x1];
+ u8 spcom; /* SPI command register */
+ u8 res6[0x2];
+ u32 spitd; /* SPI transmit data register (cpu mode) */
+ u32 spird; /* SPI receive data register (cpu mode) */
+ u8 res7[0x8];
+} __attribute__ ((packed)) spi_t;
+
+/* SI
+*/
+typedef struct si1 {
+ u16 siamr1; /* SI1 TDMA mode register */
+ u16 sibmr1; /* SI1 TDMB mode register */
+ u16 sicmr1; /* SI1 TDMC mode register */
+ u16 sidmr1; /* SI1 TDMD mode register */
+ u8 siglmr1_h; /* SI1 global mode register high */
+ u8 res0[0x1];
+ u8 sicmdr1_h; /* SI1 command register high */
+ u8 res2[0x1];
+ u8 sistr1_h; /* SI1 status register high */
+ u8 res3[0x1];
+ u16 sirsr1_h; /* SI1 RAM shadow address register high */
+ u8 sitarc1; /* SI1 RAM counter Tx TDMA */
+ u8 sitbrc1; /* SI1 RAM counter Tx TDMB */
+ u8 sitcrc1; /* SI1 RAM counter Tx TDMC */
+ u8 sitdrc1; /* SI1 RAM counter Tx TDMD */
+ u8 sirarc1; /* SI1 RAM counter Rx TDMA */
+ u8 sirbrc1; /* SI1 RAM counter Rx TDMB */
+ u8 sircrc1; /* SI1 RAM counter Rx TDMC */
+ u8 sirdrc1; /* SI1 RAM counter Rx TDMD */
+ u8 res4[0x8];
+ u16 siemr1; /* SI1 TDME mode register 16 bits */
+ u16 sifmr1; /* SI1 TDMF mode register 16 bits */
+ u16 sigmr1; /* SI1 TDMG mode register 16 bits */
+ u16 sihmr1; /* SI1 TDMH mode register 16 bits */
+ u8 siglmg1_l; /* SI1 global mode register low 8 bits */
+ u8 res5[0x1];
+ u8 sicmdr1_l; /* SI1 command register low 8 bits */
+ u8 res6[0x1];
+ u8 sistr1_l; /* SI1 status register low 8 bits */
+ u8 res7[0x1];
+ u16 sirsr1_l; /* SI1 RAM shadow address register low 16
+ bits */
+ u8 siterc1; /* SI1 RAM counter Tx TDME 8 bits */
+ u8 sitfrc1; /* SI1 RAM counter Tx TDMF 8 bits */
+ u8 sitgrc1; /* SI1 RAM counter Tx TDMG 8 bits */
+ u8 sithrc1; /* SI1 RAM counter Tx TDMH 8 bits */
+ u8 sirerc1; /* SI1 RAM counter Rx TDME 8 bits */
+ u8 sirfrc1; /* SI1 RAM counter Rx TDMF 8 bits */
+ u8 sirgrc1; /* SI1 RAM counter Rx TDMG 8 bits */
+ u8 sirhrc1; /* SI1 RAM counter Rx TDMH 8 bits */
+ u8 res8[0x8];
+ u32 siml1; /* SI1 multiframe limit register */
+ u8 siedm1; /* SI1 extended diagnostic mode register */
+ u8 res9[0xBB];
+} __attribute__ ((packed)) si1_t;
+
+/* SI Routing Tables
+*/
+typedef struct sir {
+ u8 tx[0x400];
+ u8 rx[0x400];
+ u8 res0[0x800];
+} __attribute__ ((packed)) sir_t;
+
+/* USB Controller.
+*/
+typedef struct usb_ctlr {
+ u8 usb_usmod;
+ u8 usb_usadr;
+ u8 usb_uscom;
+ u8 res1[1];
+ u16 usb_usep1;
+ u16 usb_usep2;
+ u16 usb_usep3;
+ u16 usb_usep4;
+ u8 res2[4];
+ u16 usb_usber;
+ u8 res3[2];
+ u16 usb_usbmr;
+ u8 res4[1];
+ u8 usb_usbs;
+ u16 usb_ussft;
+ u8 res5[2];
+ u16 usb_usfrn;
+ u8 res6[0x22];
+} __attribute__ ((packed)) usb_t;
+
+/* MCC
+*/
+typedef struct mcc {
+ u32 mcce; /* MCC event register */
+ u32 mccm; /* MCC mask register */
+ u32 mccf; /* MCC configuration register */
+ u32 merl; /* MCC emergency request level register */
+ u8 res0[0xF0];
+} __attribute__ ((packed)) mcc_t;
+
+/* QE UCC Slow
+*/
+typedef struct ucc_slow {
+ u32 gumr_l; /* UCCx general mode register (low) */
+ u32 gumr_h; /* UCCx general mode register (high) */
+ u16 upsmr; /* UCCx protocol-specific mode register */
+ u8 res0[0x2];
+ u16 utodr; /* UCCx transmit on demand register */
+ u16 udsr; /* UCCx data synchronization register */
+ u16 ucce; /* UCCx event register */
+ u8 res1[0x2];
+ u16 uccm; /* UCCx mask register */
+ u8 res2[0x1];
+ u8 uccs; /* UCCx status register */
+ u8 res3[0x24];
+ u16 utpt;
+ u8 guemr; /* UCC general extended mode register */
+ u8 res4[0x200 - 0x091];
+} __attribute__ ((packed)) ucc_slow_t;
+
+/* QE UCC Fast
+*/
+typedef struct ucc_fast {
+ u32 gumr; /* UCCx general mode register */
+ u32 upsmr; /* UCCx protocol-specific mode register */
+ u16 utodr; /* UCCx transmit on demand register */
+ u8 res0[0x2];
+ u16 udsr; /* UCCx data synchronization register */
+ u8 res1[0x2];
+ u32 ucce; /* UCCx event register */
+ u32 uccm; /* UCCx mask register. */
+ u8 uccs; /* UCCx status register */
+ u8 res2[0x7];
+ u32 urfb; /* UCC receive FIFO base */
+ u16 urfs; /* UCC receive FIFO size */
+ u8 res3[0x2];
+ u16 urfet; /* UCC receive FIFO emergency threshold */
+ u16 urfset; /* UCC receive FIFO special emergency
+ threshold */
+ u32 utfb; /* UCC transmit FIFO base */
+ u16 utfs; /* UCC transmit FIFO size */
+ u8 res4[0x2];
+ u16 utfet; /* UCC transmit FIFO emergency threshold */
+ u8 res5[0x2];
+ u16 utftt; /* UCC transmit FIFO transmit threshold */
+ u8 res6[0x2];
+ u16 utpt; /* UCC transmit polling timer */
+ u8 res7[0x2];
+ u32 urtry; /* UCC retry counter register */
+ u8 res8[0x4C];
+ u8 guemr; /* UCC general extended mode register */
+ u8 res9[0x100 - 0x091];
+} __attribute__ ((packed)) ucc_fast_t;
+
+/* QE UCC
+*/
+typedef struct ucc_common {
+ u8 res1[0x90];
+ u8 guemr;
+ u8 res2[0x200 - 0x091];
+} __attribute__ ((packed)) ucc_common_t;
+
+typedef struct ucc {
+ union {
+ ucc_slow_t slow;
+ ucc_fast_t fast;
+ ucc_common_t common;
+ };
+} __attribute__ ((packed)) ucc_t;
+
+/* MultiPHY UTOPIA POS Controllers (UPC)
+*/
+typedef struct upc {
+ u32 upgcr; /* UTOPIA/POS general configuration register */
+ u32 uplpa; /* UTOPIA/POS last PHY address */
+ u32 uphec; /* ATM HEC register */
+ u32 upuc; /* UTOPIA/POS UCC configuration */
+ u32 updc1; /* UTOPIA/POS device 1 configuration */
+ u32 updc2; /* UTOPIA/POS device 2 configuration */
+ u32 updc3; /* UTOPIA/POS device 3 configuration */
+ u32 updc4; /* UTOPIA/POS device 4 configuration */
+ u32 upstpa; /* UTOPIA/POS STPA threshold */
+ u8 res0[0xC];
+ u32 updrs1_h; /* UTOPIA/POS device 1 rate select */
+ u32 updrs1_l; /* UTOPIA/POS device 1 rate select */
+ u32 updrs2_h; /* UTOPIA/POS device 2 rate select */
+ u32 updrs2_l; /* UTOPIA/POS device 2 rate select */
+ u32 updrs3_h; /* UTOPIA/POS device 3 rate select */
+ u32 updrs3_l; /* UTOPIA/POS device 3 rate select */
+ u32 updrs4_h; /* UTOPIA/POS device 4 rate select */
+ u32 updrs4_l; /* UTOPIA/POS device 4 rate select */
+ u32 updrp1; /* UTOPIA/POS device 1 receive priority low */
+ u32 updrp2; /* UTOPIA/POS device 2 receive priority low */
+ u32 updrp3; /* UTOPIA/POS device 3 receive priority low */
+ u32 updrp4; /* UTOPIA/POS device 4 receive priority low */
+ u32 upde1; /* UTOPIA/POS device 1 event */
+ u32 upde2; /* UTOPIA/POS device 2 event */
+ u32 upde3; /* UTOPIA/POS device 3 event */
+ u32 upde4; /* UTOPIA/POS device 4 event */
+ u16 uprp1;
+ u16 uprp2;
+ u16 uprp3;
+ u16 uprp4;
+ u8 res1[0x8];
+ u16 uptirr1_0; /* Device 1 transmit internal rate 0 */
+ u16 uptirr1_1; /* Device 1 transmit internal rate 1 */
+ u16 uptirr1_2; /* Device 1 transmit internal rate 2 */
+ u16 uptirr1_3; /* Device 1 transmit internal rate 3 */
+ u16 uptirr2_0; /* Device 2 transmit internal rate 0 */
+ u16 uptirr2_1; /* Device 2 transmit internal rate 1 */
+ u16 uptirr2_2; /* Device 2 transmit internal rate 2 */
+ u16 uptirr2_3; /* Device 2 transmit internal rate 3 */
+ u16 uptirr3_0; /* Device 3 transmit internal rate 0 */
+ u16 uptirr3_1; /* Device 3 transmit internal rate 1 */
+ u16 uptirr3_2; /* Device 3 transmit internal rate 2 */
+ u16 uptirr3_3; /* Device 3 transmit internal rate 3 */
+ u16 uptirr4_0; /* Device 4 transmit internal rate 0 */
+ u16 uptirr4_1; /* Device 4 transmit internal rate 1 */
+ u16 uptirr4_2; /* Device 4 transmit internal rate 2 */
+ u16 uptirr4_3; /* Device 4 transmit internal rate 3 */
+ u32 uper1; /* Device 1 port enable register */
+ u32 uper2; /* Device 2 port enable register */
+ u32 uper3; /* Device 3 port enable register */
+ u32 uper4; /* Device 4 port enable register */
+ u8 res2[0x150];
+} __attribute__ ((packed)) upc_t;
+
+/* SDMA
+*/
+typedef struct sdma {
+ u32 sdsr; /* Serial DMA status register */
+ u32 sdmr; /* Serial DMA mode register */
+ u32 sdtr1; /* SDMA system bus threshold register */
+ u32 sdtr2; /* SDMA secondary bus threshold register */
+ u32 sdhy1; /* SDMA system bus hysteresis register */
+ u32 sdhy2; /* SDMA secondary bus hysteresis register */
+ u32 sdta1; /* SDMA system bus address register */
+ u32 sdta2; /* SDMA secondary bus address register */
+ u32 sdtm1; /* SDMA system bus MSNUM register */
+ u32 sdtm2; /* SDMA secondary bus MSNUM register */
+ u8 res0[0x10];
+ u32 sdaqr; /* SDMA address bus qualify register */
+ u32 sdaqmr; /* SDMA address bus qualify mask register */
+ u8 res1[0x4];
+ u32 sdebcr; /* SDMA CAM entries base register */
+ u8 res2[0x38];
+} __attribute__ ((packed)) sdma_t;
+
+/* Debug Space
+*/
+typedef struct dbg {
+ u32 bpdcr; /* Breakpoint debug command register */
+ u32 bpdsr; /* Breakpoint debug status register */
+ u32 bpdmr; /* Breakpoint debug mask register */
+ u32 bprmrr0; /* Breakpoint request mode risc register 0 */
+ u32 bprmrr1; /* Breakpoint request mode risc register 1 */
+ u8 res0[0x8];
+ u32 bprmtr0; /* Breakpoint request mode trb register 0 */
+ u32 bprmtr1; /* Breakpoint request mode trb register 1 */
+ u8 res1[0x8];
+ u32 bprmir; /* Breakpoint request mode immediate register */
+ u32 bprmsr; /* Breakpoint request mode serial register */
+ u32 bpemr; /* Breakpoint exit mode register */
+ u8 res2[0x48];
+} __attribute__ ((packed)) dbg_t;
+
+/* RISC Special Registers (Trap and Breakpoint)
+*/
+typedef struct rsp {
+ u8 fixme[0x100];
+} __attribute__ ((packed)) rsp_t;
+
+typedef struct qe_immap {
+ qe_iram_t iram; /* I-RAM */
+ qe_ic_t ic; /* Interrupt Controller */
+ cp_qe_t cp; /* Communications Processor */
+ qe_mux_t qmx; /* QE Multiplexer */
+ qe_timers_t qet; /* QE Timers */
+ spi_t spi[0x2]; /* spi */
+ mcc_t mcc; /* mcc */
+ qe_brg_t brg; /* brg */
+ usb_t usb; /* USB */
+ si1_t si1; /* SI */
+ u8 res11[0x800];
+ sir_t sir; /* SI Routing Tables */
+ ucc_t ucc1; /* ucc1 */
+ ucc_t ucc3; /* ucc3 */
+ ucc_t ucc5; /* ucc5 */
+ ucc_t ucc7; /* ucc7 */
+ u8 res12[0x600];
+ upc_t upc1; /* MultiPHY UTOPIA POS Controller 1 */
+ ucc_t ucc2; /* ucc2 */
+ ucc_t ucc4; /* ucc4 */
+ ucc_t ucc6; /* ucc6 */
+ ucc_t ucc8; /* ucc8 */
+ u8 res13[0x600];
+ upc_t upc2; /* MultiPHY UTOPIA POS Controller 2 */
+ sdma_t sdma; /* SDMA */
+ dbg_t dbg; /* Debug Space */
+ rsp_t rsp[0x2]; /* RISC Special Registers (Trap and Breakpoint)
+ */
+ u8 res14[0x300];
+ u8 res15[0x3A00];
+ u8 res16[0x8000]; /* 0x108000 - 0x110000 */
+ u8 muram[0xC000]; /* 0x110000 - 0x11C000 Multi-user RAM */
+ u8 res17[0x24000]; /* 0x11C000 - 0x140000 */
+ u8 res18[0xC0000]; /* 0x140000 - 0x200000 */
+} __attribute__ ((packed)) qe_map_t;
+
+extern qe_map_t *qe_immr;
+extern phys_addr_t get_qe_base(void);
+
+static inline unsigned long immrbar_virt_to_phys(volatile void * address)
+{
+ if ( ((uint)address >= (uint)qe_immr) &&
+ ((uint)address < ((uint)qe_immr + QE_IMMAP_SIZE)) )
+ return (unsigned long)(address - (uint)qe_immr +
+ (uint)get_qe_base());
+ return (unsigned long)virt_to_phys(address);
+}
+
+static inline void * immrbar_phys_to_virt(unsigned long address)
+{
+ if ( (address >= (uint)get_qe_base()) &&
+ (address < ((uint)get_qe_base() + QE_IMMAP_SIZE)) )
+ return (void *)(address - (uint)get_qe_base() + (uint)qe_immr);
+ return (void *)phys_to_virt(address);
+}
+
+#endif /* __IMMAP_QE_H__ */
+#endif /* __KERNEL__ */
diff --git a/include/asm-powerpc/irq.h b/include/asm-powerpc/irq.h
index 7bc6d73..3fbc01e 100644
--- a/include/asm-powerpc/irq.h
+++ b/include/asm-powerpc/irq.h
@@ -225,7 +225,16 @@ #define mk_int_int_mask(IL) (1 << (7 - (
#elif defined(CONFIG_83xx)
#include <asm/mpc83xx.h>
-#define NR_IRQS (NR_IPIC_INTS)
+#ifdef CONFIG_QUICC_ENGINE
+#define QE_IRQ_OFFSET MPC83xx_QE_IRQ_OFFSET
+#define NR_QE_IC_INTS MPC83xx_NR_QE_IC_INTS
+#define IRQ_QE_HIGH MPC83xx_IRQ_QE_HIGH
+#define IRQ_QE_LOW MPC83xx_IRQ_QE_LOW
+
+#define NR_IRQS (NR_IPIC_INTS + NR_QE_IC_INTS)
+#else
+#define NR_IRQS (NR_IPIC_INTS)
+#endif /* CONFIG_QE */
#elif defined(CONFIG_85xx)
/* Now include the board configuration specific associations.
diff --git a/include/asm-powerpc/qe.h b/include/asm-powerpc/qe.h
new file mode 100644
index 0000000..0502a51
--- /dev/null
+++ b/include/asm-powerpc/qe.h
@@ -0,0 +1,498 @@
+/*
+ * Copyright (C) Freescale Semicondutor, Inc. 2006. All rights reserved.
+ *
+ * Author: Shlomi Gridish <gridish@freescale.com>
+ *
+ * Description:
+ * QUICC Engine (QE) external definitions and structure.
+ *
+ * Changelog:
+ * Jun 28, 2006 Li Yang <LeoLi@freescale.com>
+ * - Reorganized as qe_lib
+ * - Merged to powerpc arch; add device tree support
+ * - Style fixes
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+#ifdef __KERNEL__
+#ifndef __QE_H__
+#define __QE_H__
+
+#include <asm/immap_qe.h>
+
+/* Multi User RAM addresses.
+ */
+#define QE_MURAM_DATAONLY_BASE ((uint)0x0)
+#define QE_MURAM_NOSPACE ((uint)0x7fffffff)
+#define QE_MURAM_DATAONLY_SIZE ((uint)(48 * 1024) - QE_MURAM_DATAONLY_BASE)
+
+static inline long IS_MURAM_ERR(const uint offset)
+{
+ return (uint) offset > (uint) - 1000L;
+}
+
+#define QE_NUM_OF_SNUM 28
+#define QE_NUM_OF_BRGS 16
+#define QE_NUM_OF_PORTS 1024
+
+/* Memory partitions
+*/
+#define MEM_PART_SYSTEM 0
+#define MEM_PART_SECONDARY 1
+#define MEM_PART_MURAM 2
+
+/* Export the base address of the communication processor registers
+ * and dual port ram.
+ */
+int qe_issue_cmd(uint cmd, uint device, u8 mcn_protocol, u32 cmd_input);
+void qe_setbrg(uint brg, uint rate);
+int qe_get_snum(void);
+void qe_put_snum(u8 snum);
+uint qe_muram_alloc(uint size, uint align);
+int qe_muram_free(uint offset);
+uint qe_muram_alloc_fixed(uint offset, uint size, uint align);
+void qe_muram_dump(void);
+void *qe_muram_addr(uint offset);
+/* Buffer descriptors.
+*/
+typedef struct qe_bd {
+ u16 status;
+ u16 length;
+ u32 buf;
+} __attribute__ ((packed)) qe_bd_t;
+
+#define QE_SIZEOF_BD sizeof(qe_bd_t)
+
+#define BD_STATUS_MASK 0xffff0000
+#define BD_LENGTH_MASK 0x0000ffff
+
+#define BD_BUFFER_ARG(bd) ((qe_bd_t *)bd)->buf
+#define BD_BUFFER_CLEAR(bd) out_be32(&(BD_BUFFER_ARG(bd)), 0);
+#define BD_BUFFER(bd) in_be32(&(BD_BUFFER_ARG(bd)))
+#define BD_STATUS_AND_LENGTH_SET(bd, val) out_be32((u32*)bd, val)
+#define BD_STATUS_AND_LENGTH(bd) in_be32((u32*)bd)
+#define BD_BUFFER_SET(bd, buffer) out_be32(&(BD_BUFFER_ARG(bd)), \
+ (u32)(buffer))
+/* Macro for retrieving the following BD.
+ example:
+ next = BD_GET_NEXT( currBd, bdStatus, bdBase, SIZEOF_MY_BD, T_W ) */
+#define BD_GET_NEXT( curr_bd, bd_status, bd_base, bd_len, last_bd ) \
+ ( (!((bd_status) & (last_bd))) ? ((curr_bd)+(bd_len)) : (bd_base) )
+
+/* Alignments
+*/
+#define QE_INTR_TABLE_ALIGN 16 /* ??? */
+#define QE_ALIGNMENT_OF_BD 8
+#define QE_ALIGNMENT_OF_PRAM 64
+
+/* RISC allocation
+*/
+typedef enum qe_risc_allocation {
+ QE_RISC_ALLOCATION_RISC1 = 1, /* RISC 1 */
+ QE_RISC_ALLOCATION_RISC2 = 2, /* RISC 2 */
+ QE_RISC_ALLOCATION_RISC1_AND_RISC2 = 3 /* Dynamically choose RISC 1 or
+ RISC 2 */
+} qe_risc_allocation_e;
+
+/* QE extended filtering Table Lookup Key Size
+*/
+typedef enum qe_fltr_tbl_lookup_key_size {
+ QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES
+ = 0x3f, /* LookupKey parsed by the Generate LookupKey
+ CMD is truncated to 8 bytes */
+ QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES
+ = 0x5f, /* LookupKey parsed by the Generate LookupKey
+ CMD is truncated to 16 bytes */
+} qe_fltr_tbl_lookup_key_size_e;
+
+/* QE FLTR extended filtering Largest External Table Lookup Key Size
+*/
+typedef enum qe_fltr_largest_external_tbl_lookup_key_size_ {
+ QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE
+ = 0x0,/* not used */
+ QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_8_BYTES
+ = QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES, /* 8 bytes */
+ QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_16_BYTES
+ = QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES /* 16 bytes */
+} qe_fltr_largest_external_tbl_lookup_key_size_e;
+
+/* structure representing QE parameter RAM
+*/
+typedef struct qe_timer_tables {
+ u16 tm_base; /* QE timer table base adr */
+ u16 tm_ptr; /* QE timer table pointer */
+ u16 r_tmr; /* QE timer mode register */
+ u16 r_tmv; /* QE timer valid register */
+ u32 tm_cmd; /* QE timer cmd register */
+ u32 tm_cnt; /* QE timer internal cnt */
+} __attribute__ ((packed)) qe_timer_tables_t;
+
+#define QE_FLTR_TAD_SIZE 8
+
+/* QE extended filtering Termination Action Descriptor (TAD)
+*/
+typedef struct qe_fltr_tad {
+ u8 serialized[QE_FLTR_TAD_SIZE];
+} __attribute__ ((packed)) qe_fltr_tad_t;
+
+/* Communication Direction.
+*/
+typedef enum comm_dir {
+ COMM_DIR_NONE = 0,
+ COMM_DIR_RX = 1,
+ COMM_DIR_TX = 2,
+ COMM_DIR_RX_AND_TX = 3
+} comm_dir_e;
+
+/* Clocks and GRG's
+*/
+typedef enum qe_clock {
+ QE_CLK_NONE = 0
+ , QE_BRG1 /* Baud Rate Generator 1 */
+ , QE_BRG2 /* Baud Rate Generator 2 */
+ , QE_BRG3 /* Baud Rate Generator 3 */
+ , QE_BRG4 /* Baud Rate Generator 4 */
+ , QE_BRG5 /* Baud Rate Generator 5 */
+ , QE_BRG6 /* Baud Rate Generator 6 */
+ , QE_BRG7 /* Baud Rate Generator 7 */
+ , QE_BRG8 /* Baud Rate Generator 8 */
+ , QE_BRG9 /* Baud Rate Generator 9 */
+ , QE_BRG10 /* Baud Rate Generator 10 */
+ , QE_BRG11 /* Baud Rate Generator 11 */
+ , QE_BRG12 /* Baud Rate Generator 12 */
+ , QE_BRG13 /* Baud Rate Generator 13 */
+ , QE_BRG14 /* Baud Rate Generator 14 */
+ , QE_BRG15 /* Baud Rate Generator 15 */
+ , QE_BRG16 /* Baud Rate Generator 16 */
+ , QE_CLK1 /* Clock 1 */
+ , QE_CLK2 /* Clock 2 */
+ , QE_CLK3 /* Clock 3 */
+ , QE_CLK4 /* Clock 4 */
+ , QE_CLK5 /* Clock 5 */
+ , QE_CLK6 /* Clock 6 */
+ , QE_CLK7 /* Clock 7 */
+ , QE_CLK8 /* Clock 8 */
+ , QE_CLK9 /* Clock 9 */
+ , QE_CLK10 /* Clock 10 */
+ , QE_CLK11 /* Clock 11 */
+ , QE_CLK12 /* Clock 12 */
+ , QE_CLK13 /* Clock 13 */
+ , QE_CLK14 /* Clock 14 */
+ , QE_CLK15 /* Clock 15 */
+ , QE_CLK16 /* Clock 16 */
+ , QE_CLK17 /* Clock 17 */
+ , QE_CLK18 /* Clock 18 */
+ , QE_CLK19 /* Clock 19 */
+ , QE_CLK20 /* Clock 20 */
+ , QE_CLK21 /* Clock 21 */
+ , QE_CLK22 /* Clock 22 */
+ , QE_CLK23 /* Clock 23 */
+ , QE_CLK24 /* Clock 24 */
+ , QE_CLK_DUMMY
+} qe_clock_e;
+
+/* QE CMXUCR Registers.
+ * There are two UCCs represented in each of the four CMXUCR registers.
+ * These values are for the UCC in the LSBs
+ */
+#define QE_CMXUCR_MII_ENET_MNG 0x00007000
+#define QE_CMXUCR_MII_ENET_MNG_SHIFT 12
+#define QE_CMXUCR_GRANT 0x00008000
+#define QE_CMXUCR_TSA 0x00004000
+#define QE_CMXUCR_BKPT 0x00000100
+#define QE_CMXUCR_TX_CLK_SRC_MASK 0x0000000F
+
+/* QE CMXGCR Registers.
+*/
+#define QE_CMXGCR_MII_ENET_MNG 0x00007000
+#define QE_CMXGCR_MII_ENET_MNG_SHIFT 12
+#define QE_CMXGCR_USBCS 0x0000000f
+
+/* QE CECR Commands.
+*/
+#define QE_CR_FLG 0x00010000
+#define QE_RESET 0x80000000
+#define QE_INIT_TX_RX 0x00000000
+#define QE_INIT_RX 0x00000001
+#define QE_INIT_TX 0x00000002
+#define QE_ENTER_HUNT_MODE 0x00000003
+#define QE_STOP_TX 0x00000004
+#define QE_GRACEFUL_STOP_TX 0x00000005
+#define QE_RESTART_TX 0x00000006
+#define QE_CLOSE_RX_BD 0x00000007
+#define QE_SWITCH_COMMAND 0x00000007
+#define QE_SET_GROUP_ADDRESS 0x00000008
+#define QE_START_IDMA 0x00000009
+#define QE_MCC_STOP_RX 0x00000009
+#define QE_ATM_TRANSMIT 0x0000000a
+#define QE_HPAC_CLEAR_ALL 0x0000000b
+#define QE_GRACEFUL_STOP_RX 0x0000001a
+#define QE_RESTART_RX 0x0000001b
+#define QE_HPAC_SET_PRIORITY 0x0000010b
+#define QE_HPAC_STOP_TX 0x0000020b
+#define QE_HPAC_STOP_RX 0x0000030b
+#define QE_HPAC_GRACEFUL_STOP_TX 0x0000040b
+#define QE_HPAC_GRACEFUL_STOP_RX 0x0000050b
+#define QE_HPAC_START_TX 0x0000060b
+#define QE_HPAC_START_RX 0x0000070b
+#define QE_USB_STOP_TX 0x0000000a
+#define QE_USB_RESTART_TX 0x0000000b
+#define QE_QMC_STOP_TX 0x0000000c
+#define QE_QMC_STOP_RX 0x0000000d
+#define QE_SS7_SU_FIL_RESET 0x0000000e
+/* jonathbr added from here down for 83xx */
+#define QE_RESET_BCS 0x0000000a
+#define QE_MCC_INIT_TX_RX_16 0x00000003
+#define QE_MCC_STOP_TX 0x00000004
+#define QE_MCC_INIT_TX_1 0x00000005
+#define QE_MCC_INIT_RX_1 0x00000006
+#define QE_MCC_RESET 0x00000007
+#define QE_SET_TIMER 0x00000008
+#define QE_RANDOM_NUMBER 0x0000000c
+#define QE_ATM_MULTI_THREAD_INIT 0x00000011
+#define QE_ASSIGN_PAGE 0x00000012
+#define QE_ADD_REMOVE_HASH_ENTRY 0x00000013
+#define QE_START_FLOW_CONTROL 0x00000014
+#define QE_STOP_FLOW_CONTROL 0x00000015
+#define QE_ASSIGN_PAGE_TO_DEVICE 0x00000016
+
+#define QE_ASSIGN_RISC 0x00000010
+#define QE_CR_MCN_NORMAL_SHIFT 6
+#define QE_CR_MCN_USB_SHIFT 4
+#define QE_CR_MCN_RISC_ASSIGN_SHIFT 8
+#define QE_CR_SNUM_SHIFT 17
+
+/* QE CECR Sub Block - sub block of QE command.
+*/
+#define QE_CR_SUBBLOCK_INVALID 0x00000000
+#define QE_CR_SUBBLOCK_USB 0x03200000
+#define QE_CR_SUBBLOCK_UCCFAST1 0x02000000
+#define QE_CR_SUBBLOCK_UCCFAST2 0x02200000
+#define QE_CR_SUBBLOCK_UCCFAST3 0x02400000
+#define QE_CR_SUBBLOCK_UCCFAST4 0x02600000
+#define QE_CR_SUBBLOCK_UCCFAST5 0x02800000
+#define QE_CR_SUBBLOCK_UCCFAST6 0x02a00000
+#define QE_CR_SUBBLOCK_UCCFAST7 0x02c00000
+#define QE_CR_SUBBLOCK_UCCFAST8 0x02e00000
+#define QE_CR_SUBBLOCK_UCCSLOW1 0x00000000
+#define QE_CR_SUBBLOCK_UCCSLOW2 0x00200000
+#define QE_CR_SUBBLOCK_UCCSLOW3 0x00400000
+#define QE_CR_SUBBLOCK_UCCSLOW4 0x00600000
+#define QE_CR_SUBBLOCK_UCCSLOW5 0x00800000
+#define QE_CR_SUBBLOCK_UCCSLOW6 0x00a00000
+#define QE_CR_SUBBLOCK_UCCSLOW7 0x00c00000
+#define QE_CR_SUBBLOCK_UCCSLOW8 0x00e00000
+#define QE_CR_SUBBLOCK_MCC1 0x03800000
+#define QE_CR_SUBBLOCK_MCC2 0x03a00000
+#define QE_CR_SUBBLOCK_MCC3 0x03000000
+#define QE_CR_SUBBLOCK_IDMA1 0x02800000
+#define QE_CR_SUBBLOCK_IDMA2 0x02a00000
+#define QE_CR_SUBBLOCK_IDMA3 0x02c00000
+#define QE_CR_SUBBLOCK_IDMA4 0x02e00000
+#define QE_CR_SUBBLOCK_HPAC 0x01e00000
+#define QE_CR_SUBBLOCK_SPI1 0x01400000
+#define QE_CR_SUBBLOCK_SPI2 0x01600000
+#define QE_CR_SUBBLOCK_RAND 0x01c00000
+#define QE_CR_SUBBLOCK_TIMER 0x01e00000
+#define QE_CR_SUBBLOCK_GENERAL 0x03c00000
+
+/* QE CECR Protocol - For non-MCC, specifies mode for QE CECR command.
+*/
+#define QE_CR_PROTOCOL_UNSPECIFIED 0x00 /* For all other protocols */
+#define QE_CR_PROTOCOL_HDLC_TRANSPARENT 0x00
+#define QE_CR_PROTOCOL_ATM_POS 0x0A
+#define QE_CR_PROTOCOL_ETHERNET 0x0C
+#define QE_CR_PROTOCOL_L2_SWITCH 0x0D
+
+/* BMR byte order
+*/
+#define QE_BMR_BYTE_ORDER_BO_PPC 0x08 /* powerpc little endian */
+#define QE_BMR_BYTE_ORDER_BO_MOT 0x10 /* motorola big endian */
+#define QE_BMR_BYTE_ORDER_BO_MAX 0x18
+
+/* BRG configuration register
+*/
+#define QE_BRGC_ENABLE 0x00010000
+#define QE_BRGC_DIVISOR_SHIFT 1
+#define QE_BRGC_DIVISOR_MAX 0xFFF
+#define QE_BRGC_DIV16 1
+/* QE Timers registers */
+#define QE_GTCFR1_PCAS 0x80
+#define QE_GTCFR1_STP2 0x20
+#define QE_GTCFR1_RST2 0x10
+#define QE_GTCFR1_GM2 0x08
+#define QE_GTCFR1_GM1 0x04
+#define QE_GTCFR1_STP1 0x02
+#define QE_GTCFR1_RST1 0x01
+
+/* SDMA registers */
+#define QE_SDSR_BER1 0x02000000
+#define QE_SDSR_BER2 0x01000000
+
+#define QE_SDMR_GLB_1_MSK 0x80000000
+#define QE_SDMR_ADR_SEL 0x20000000
+#define QE_SDMR_BER1_MSK 0x02000000
+#define QE_SDMR_BER2_MSK 0x01000000
+#define QE_SDMR_EB1_MSK 0x00800000
+#define QE_SDMR_ER1_MSK 0x00080000
+#define QE_SDMR_ER2_MSK 0x00040000
+#define QE_SDMR_CEN_MASK 0x0000E000
+#define QE_SDMR_SBER_1 0x00000200
+#define QE_SDMR_SBER_2 0x00000200
+#define QE_SDMR_EB1_PR_MASK 0x000000C0
+#define QE_SDMR_ER1_PR 0x00000008
+
+#define QE_SDMR_CEN_SHIFT 13
+#define QE_SDMR_EB1_PR_SHIFT 6
+
+#define QE_SDTM_MSNUM_SHIFT 24
+
+#define QE_SDEBCR_BA_MASK 0x01FFFFFF
+
+/* UPC
+*/
+#define UPGCR_PROTOCOL 0x80000000 /* protocol ul2 or pl2 */
+#define UPGCR_TMS 0x40000000 /* Transmit master/slave mode */
+#define UPGCR_RMS 0x20000000 /* Receive master/slave mode */
+#define UPGCR_ADDR 0x10000000 /* Master MPHY Addr multiplexing */
+#define UPGCR_DIAG 0x01000000 /* Diagnostic mode */
+
+/* UCC
+*/
+#define UCC_GUEMR_MODE_MASK_RX 0x02
+#define UCC_GUEMR_MODE_MASK_TX 0x01
+#define UCC_GUEMR_MODE_FAST_RX 0x02
+#define UCC_GUEMR_MODE_FAST_TX 0x01
+#define UCC_GUEMR_MODE_SLOW_RX 0x00
+#define UCC_GUEMR_MODE_SLOW_TX 0x00
+#define UCC_GUEMR_SET_RESERVED3 0x10 /* Bit 3 in the guemr is reserved but
+ must be set 1 */
+
+/* structure representing UCC SLOW parameter RAM
+*/
+typedef struct ucc_slow_pram {
+ u16 rbase; /* RX BD base address */
+ u16 tbase; /* TX BD base address */
+ u8 rfcr; /* Rx function code */
+ u8 tfcr; /* Tx function code */
+ u16 mrblr; /* Rx buffer length */
+ u32 rstate; /* Rx internal state */
+ u32 rptr; /* Rx internal data pointer */
+ u16 rbptr; /* rb BD Pointer */
+ u16 rcount; /* Rx internal byte count */
+ u32 rtemp; /* Rx temp */
+ u32 tstate; /* Tx internal state */
+ u32 tptr; /* Tx internal data pointer */
+ u16 tbptr; /* Tx BD pointer */
+ u16 tcount; /* Tx byte count */
+ u32 ttemp; /* Tx temp */
+ u32 rcrc; /* temp receive CRC */
+ u32 tcrc; /* temp transmit CRC */
+} __attribute__ ((packed)) ucc_slow_pram_t;
+
+/* General UCC SLOW Mode Register (GUMRH & GUMRL)
+*/
+#define UCC_SLOW_GUMR_H_CRC16 0x00004000
+#define UCC_SLOW_GUMR_H_CRC16CCITT 0x00000000
+#define UCC_SLOW_GUMR_H_CRC32CCITT 0x00008000
+#define UCC_SLOW_GUMR_H_REVD 0x00002000
+#define UCC_SLOW_GUMR_H_TRX 0x00001000
+#define UCC_SLOW_GUMR_H_TTX 0x00000800
+#define UCC_SLOW_GUMR_H_CDP 0x00000400
+#define UCC_SLOW_GUMR_H_CTSP 0x00000200
+#define UCC_SLOW_GUMR_H_CDS 0x00000100
+#define UCC_SLOW_GUMR_H_CTSS 0x00000080
+#define UCC_SLOW_GUMR_H_TFL 0x00000040
+#define UCC_SLOW_GUMR_H_RFW 0x00000020
+#define UCC_SLOW_GUMR_H_TXSY 0x00000010
+#define UCC_SLOW_GUMR_H_4SYNC 0x00000004
+#define UCC_SLOW_GUMR_H_8SYNC 0x00000008
+#define UCC_SLOW_GUMR_H_16SYNC 0x0000000c
+#define UCC_SLOW_GUMR_H_RTSM 0x00000002
+#define UCC_SLOW_GUMR_H_RSYN 0x00000001
+
+#define UCC_SLOW_GUMR_L_TCI 0x10000000
+#define UCC_SLOW_GUMR_L_RINV 0x02000000
+#define UCC_SLOW_GUMR_L_TINV 0x01000000
+#define UCC_SLOW_GUMR_L_TEND 0x00020000
+#define UCC_SLOW_GUMR_L_ENR 0x00000020
+#define UCC_SLOW_GUMR_L_ENT 0x00000010
+
+/* General UCC FAST Mode Register
+*/
+#define UCC_FAST_GUMR_TCI 0x20000000
+#define UCC_FAST_GUMR_TRX 0x10000000
+#define UCC_FAST_GUMR_TTX 0x08000000
+#define UCC_FAST_GUMR_CDP 0x04000000
+#define UCC_FAST_GUMR_CTSP 0x02000000
+#define UCC_FAST_GUMR_CDS 0x01000000
+#define UCC_FAST_GUMR_CTSS 0x00800000
+#define UCC_FAST_GUMR_TXSY 0x00020000
+#define UCC_FAST_GUMR_RSYN 0x00010000
+#define UCC_FAST_GUMR_RTSM 0x00002000
+#define UCC_FAST_GUMR_REVD 0x00000400
+#define UCC_FAST_GUMR_ENR 0x00000020
+#define UCC_FAST_GUMR_ENT 0x00000010
+
+/* Slow UCC Event Register (UCCE)
+*/
+#define UCC_SLOW_UCCE_GLR 0x1000
+#define UCC_SLOW_UCCE_GLT 0x0800
+#define UCC_SLOW_UCCE_DCC 0x0400
+#define UCC_SLOW_UCCE_FLG 0x0200
+#define UCC_SLOW_UCCE_AB 0x0200
+#define UCC_SLOW_UCCE_IDLE 0x0100
+#define UCC_SLOW_UCCE_GRA 0x0080
+#define UCC_SLOW_UCCE_TXE 0x0010
+#define UCC_SLOW_UCCE_RXF 0x0008
+#define UCC_SLOW_UCCE_CCR 0x0008
+#define UCC_SLOW_UCCE_RCH 0x0008
+#define UCC_SLOW_UCCE_BSY 0x0004
+#define UCC_SLOW_UCCE_TXB 0x0002
+#define UCC_SLOW_UCCE_TX 0x0002
+#define UCC_SLOW_UCCE_RX 0x0001
+#define UCC_SLOW_UCCE_GOV 0x0001
+#define UCC_SLOW_UCCE_GUN 0x0002
+#define UCC_SLOW_UCCE_GINT 0x0004
+#define UCC_SLOW_UCCE_IQOV 0x0008
+
+#define UCC_SLOW_UCCE_HDLC_SET (UCC_SLOW_UCCE_TXE|UCC_SLOW_UCCE_BSY| \
+ UCC_SLOW_UCCE_GRA|UCC_SLOW_UCCE_TXB|UCC_SLOW_UCCE_RXF| \
+ UCC_SLOW_UCCE_DCC|UCC_SLOW_UCCE_GLT|UCC_SLOW_UCCE_GLR)
+#define UCC_SLOW_UCCE_ENET_SET (UCC_SLOW_UCCE_TXE|UCC_SLOW_UCCE_BSY| \
+ UCC_SLOW_UCCE_GRA|UCC_SLOW_UCCE_TXB|UCC_SLOW_UCCE_RXF)
+#define UCC_SLOW_UCCE_TRANS_SET (UCC_SLOW_UCCE_TXE|UCC_SLOW_UCCE_BSY| \
+ UCC_SLOW_UCCE_GRA|UCC_SLOW_UCCE_TX |UCC_SLOW_UCCE_RX | \
+ UCC_SLOW_UCCE_DCC|UCC_SLOW_UCCE_GLT|UCC_SLOW_UCCE_GLR)
+#define UCC_SLOW_UCCE_UART_SET (UCC_SLOW_UCCE_BSY|UCC_SLOW_UCCE_GRA| \
+ UCC_SLOW_UCCE_TXB|UCC_SLOW_UCCE_TX |UCC_SLOW_UCCE_RX | \
+ UCC_SLOW_UCCE_GLT|UCC_SLOW_UCCE_GLR)
+#define UCC_SLOW_UCCE_QMC_SET (UCC_SLOW_UCCE_IQOV|UCC_SLOW_UCCE_GINT| \
+ UCC_SLOW_UCCE_GUN|UCC_SLOW_UCCE_GOV)
+
+#define UCC_SLOW_UCCE_OTHER (UCC_SLOW_UCCE_TXE|UCC_SLOW_UCCE_BSY| \
+ UCC_SLOW_UCCE_GRA|UCC_SLOW_UCCE_DCC|UCC_SLOW_UCCE_GLT| \
+ UCC_SLOW_UCCE_GLR)
+
+#define UCC_SLOW_INTR_TX UCC_SLOW_UCCE_TXB
+#define UCC_SLOW_INTR_RX (UCC_SLOW_UCCE_RXF | UCC_SLOW_UCCE_RX)
+#define UCC_SLOW_INTR (UCC_SLOW_INTR_TX | UCC_SLOW_INTR_RX)
+
+/* Transmit On Demand (UTORD)
+*/
+#define UCC_SLOW_TOD 0x8000
+#define UCC_FAST_TOD 0x8000
+
+/* Function code masks.
+*/
+#define FC_GBL 0x20
+#define FC_DTB_LCL 0x02
+#define UCC_FAST_FUNCTION_CODE_GBL 0x20
+#define UCC_FAST_FUNCTION_CODE_DTB_LCL 0x02
+#define UCC_FAST_FUNCTION_CODE_BDB_LCL 0x01
+
+#endif /* __QE_H__ */
+#endif /* __KERNEL__ */
diff --git a/include/asm-powerpc/qe_ic.h b/include/asm-powerpc/qe_ic.h
new file mode 100644
index 0000000..81bbf2a
--- /dev/null
+++ b/include/asm-powerpc/qe_ic.h
@@ -0,0 +1,131 @@
+/*
+ * Copyright (C) Freescale Semicondutor, Inc. 2006. All rights reserved.
+ *
+ * Author: Shlomi Gridish <gridish@freescale.com>
+ *
+ * Description:
+ * QE IC external definitions and structure.
+ *
+ * Changelog:
+ * Jun 28, 2006 Li Yang <LeoLi@freescale.com>
+ * - Reorganized as qe_lib
+ * - Merged to powerpc arch; add device tree support
+ * - Style fixes
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+#ifdef __KERNEL__
+#ifndef __ASM_QE_IC_H__
+#define __ASM_QE_IC_H__
+
+#include <linux/irq.h>
+
+#define _IO_BASE isa_io_base
+#define _ISA_MEM_BASE isa_mem_base
+#ifdef CONFIG_PCI
+#define PCI_DRAM_OFFSET pci_dram_offset
+#else
+#define PCI_DRAM_OFFSET 0
+#endif
+
+#define NUM_OF_QE_IC_GROUPS 6
+
+/* Flags when we init the QE IC */
+#define QE_IC_SPREADMODE_GRP_W 0x00000001
+#define QE_IC_SPREADMODE_GRP_X 0x00000002
+#define QE_IC_SPREADMODE_GRP_Y 0x00000004
+#define QE_IC_SPREADMODE_GRP_Z 0x00000008
+#define QE_IC_SPREADMODE_GRP_RISCA 0x00000010
+#define QE_IC_SPREADMODE_GRP_RISCB 0x00000020
+
+#define QE_IC_LOW_SIGNAL 0x00000100
+#define QE_IC_HIGH_SIGNAL 0x00000200
+
+#define QE_IC_GRP_W_PRI0_DEST_SIGNAL_HIGH 0x00001000
+#define QE_IC_GRP_W_PRI1_DEST_SIGNAL_HIGH 0x00002000
+#define QE_IC_GRP_X_PRI0_DEST_SIGNAL_HIGH 0x00004000
+#define QE_IC_GRP_X_PRI1_DEST_SIGNAL_HIGH 0x00008000
+#define QE_IC_GRP_Y_PRI0_DEST_SIGNAL_HIGH 0x00010000
+#define QE_IC_GRP_Y_PRI1_DEST_SIGNAL_HIGH 0x00020000
+#define QE_IC_GRP_Z_PRI0_DEST_SIGNAL_HIGH 0x00040000
+#define QE_IC_GRP_Z_PRI1_DEST_SIGNAL_HIGH 0x00080000
+#define QE_IC_GRP_RISCA_PRI0_DEST_SIGNAL_HIGH 0x00100000
+#define QE_IC_GRP_RISCA_PRI1_DEST_SIGNAL_HIGH 0x00200000
+#define QE_IC_GRP_RISCB_PRI0_DEST_SIGNAL_HIGH 0x00400000
+#define QE_IC_GRP_RISCB_PRI1_DEST_SIGNAL_HIGH 0x00800000
+#define QE_IC_GRP_W_DEST_SIGNAL_SHIFT (12)
+
+/*
+ * QE interrupt sources groups
+ */
+enum qe_ic_grp_id {
+ QE_IC_GRP_W = 0, /* QE interrupt controller group W */
+ QE_IC_GRP_X, /* QE interrupt controller group X */
+ QE_IC_GRP_Y, /* QE interrupt controller group Y */
+ QE_IC_GRP_Z, /* QE interrupt controller group Z */
+ QE_IC_GRP_RISCA, /* QE interrupt controller RISC group A */
+ QE_IC_GRP_RISCB /* QE interrupt controller RISC group B */
+};
+
+/*
+ * QE interrupt controller internal structure
+ */
+struct qe_ic_info {
+ u32 mask; /* locaion of this source at the QIMR register. */
+ int qimr; /* TRUE is this source is mappd to QIMR, */
+ /* otherwise - QRIMR (risc). */
+ u8 pri_code; /* for grouped interrupts sources - the interrupt */
+ /* code as appears at the group priority register. */
+};
+
+/*********************************************/
+/****** QE IC API routines *****/
+/*********************************************/
+int qe_ic_init(phys_addr_t phys_addr,
+ unsigned int flags, unsigned int irq_offset);
+void qe_ic_free(void);
+void qe_ic_enable_irq(unsigned int qeIntrSrc);
+void qe_ic_disable_irq(unsigned int qeIntrSrc);
+void qe_ic_disable_irq_and_ack(unsigned int irq);
+void qe_ic_end_irq(unsigned int irq);
+
+/* qe_ic_modify_highest_priority
+ * Optional, used to change default. This routine defines a single interrupt
+ * source to be highest priority. It may be called at any stage, thus enabling
+ * dynamic change of the highest priority interrupt.
+ * In default, Highest priority is XCC1 highest priority interrupt source.
+ *
+ * irq (In) - Interrupt source Id.
+ */
+void qe_ic_modify_highest_priority(unsigned int irq);
+
+/* qe_ic_modify_priority
+ * Optional, used to change default. May be called at run time to manipulate
+ * priorities. This routine is called to reorganize a specific group.
+ *
+ * qeIcGroupId (In) - One of:
+ * e_QE_IC_GRP_W
+ * e_QE_IC_GRP_X
+ * e_QE_IC_GRP_Y
+ * e_QE_IC_GRP_Z
+ * e_QE_IC_GRP_RISCA
+ * e_QE_IC_GRP_RISCB
+ * pri0, pr1,..., pri7 (In) - A list of interrupt sources (of type
+ * unsigned int) in order of priority. The
+ * list must include all and only sources
+ * of the specified group.
+ */
+void qe_ic_modify_priority(enum qe_ic_grp_id qeIcGroupId,
+ unsigned int pri0,
+ unsigned int pri1,
+ unsigned int pri2,
+ unsigned int pri3,
+ unsigned int pri4,
+ unsigned int pri5,
+ unsigned int pri6, unsigned int pri7);
+
+#endif /* __ASM_QE_IC_H__ */
+#endif /* __KERNEL__ */
diff --git a/include/asm-powerpc/ucc.h b/include/asm-powerpc/ucc.h
new file mode 100644
index 0000000..084c786
--- /dev/null
+++ b/include/asm-powerpc/ucc.h
@@ -0,0 +1,89 @@
+/*
+ * aopyright (C) Freescale Semicondutor, Inc. 2006. All rights reserved.
+ *
+ * Author: Shlomi Gridish <gridish@freescale.com>
+ *
+ * Description:
+ * Internal header file for UCC unit routines.
+ *
+ * Changelog:
+ * Jun 28, 2006 Li Yang <LeoLi@freescale.com>
+ * - Reorganized as qe_lib
+ * - Merged to powerpc arch; add device tree support
+ * - Style fixes
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+#ifndef __UCC_H__
+#define __UCC_H__
+
+#include <asm/immap_qe.h>
+#include <asm/qe.h>
+
+#define STATISTICS
+
+#define UCC_MAX_NUM 8
+
+/* Slow or fast type for UCCs.
+*/
+typedef enum ucc_speed_type {
+ UCC_SPEED_TYPE_FAST, UCC_SPEED_TYPE_SLOW
+} ucc_speed_type_e;
+
+/* Initial UCCs Parameter RAM address relative to: MEM_MAP_BASE (IMMR).
+*/
+typedef enum ucc_pram_initial_offset {
+ UCC_PRAM_OFFSET_UCC1 = 0x8400,
+ UCC_PRAM_OFFSET_UCC2 = 0x8500,
+ UCC_PRAM_OFFSET_UCC3 = 0x8600,
+ UCC_PRAM_OFFSET_UCC4 = 0x9000,
+ UCC_PRAM_OFFSET_UCC5 = 0x8000,
+ UCC_PRAM_OFFSET_UCC6 = 0x8100,
+ UCC_PRAM_OFFSET_UCC7 = 0x8200,
+ UCC_PRAM_OFFSET_UCC8 = 0x8300
+} ucc_pram_initial_offset_e;
+
+/* ucc_set_type
+ * Sets UCC to slow or fast mode.
+ *
+ * ucc_num - (In) number of UCC (0-7).
+ * regs - (In) pointer to registers base for the UCC.
+ * speed - (In) slow or fast mode for UCC.
+ */
+int ucc_set_type(int ucc_num, struct ucc_common *regs,
+ enum ucc_speed_type speed);
+
+/* ucc_init_guemr
+ * Init the Guemr register.
+ *
+ * regs - (In) pointer to registers base for the UCC.
+ */
+int ucc_init_guemr(struct ucc_common *regs);
+
+int ucc_set_qe_mux_mii_mng(int ucc_num);
+
+int ucc_set_qe_mux_rxtx(int ucc_num, qe_clock_e clock, comm_dir_e mode);
+
+int ucc_mux_set_grant_tsa_bkpt(int ucc_num, int set, u32 mask);
+
+/* QE MUX clock routing for UCC
+*/
+static inline int ucc_set_qe_mux_grant(int ucc_num, int set)
+{
+ return ucc_mux_set_grant_tsa_bkpt(ucc_num, set, QE_CMXUCR_GRANT);
+}
+
+static inline int ucc_set_qe_mux_tsa(int ucc_num, int set)
+{
+ return ucc_mux_set_grant_tsa_bkpt(ucc_num, set, QE_CMXUCR_TSA);
+}
+
+static inline int ucc_set_qe_mux_bkpt(int ucc_num, int set)
+{
+ return ucc_mux_set_grant_tsa_bkpt(ucc_num, set, QE_CMXUCR_BKPT);
+}
+
+#endif /* __UCC_H__ */
diff --git a/include/asm-powerpc/ucc_fast.h b/include/asm-powerpc/ucc_fast.h
new file mode 100644
index 0000000..a88b97c
--- /dev/null
+++ b/include/asm-powerpc/ucc_fast.h
@@ -0,0 +1,259 @@
+/*
+ * Copyright (C) Freescale Semicondutor, Inc. 2006. All rights reserved.
+ *
+ * Author: Shlomi Gridish <gridish@freescale.com>
+ *
+ * Description:
+ * Internal header file for UCC FAST unit routines.
+ *
+ * Changelog:
+ * Jun 28, 2006 Li Yang <LeoLi@freescale.com>
+ * - Reorganized as qe_lib
+ * - Merged to powerpc arch; add device tree support
+ * - Style fixes
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+#ifndef __UCC_FAST_H__
+#define __UCC_FAST_H__
+
+#include <linux/kernel.h>
+
+#include <asm/immap_qe.h>
+#include <asm/qe.h>
+
+#include "ucc.h"
+
+/* Receive BD's status.
+*/
+#define R_E 0x80000000 /* buffer empty */
+#define R_W 0x20000000 /* wrap bit */
+#define R_I 0x10000000 /* interrupt on reception */
+#define R_L 0x08000000 /* last */
+#define R_F 0x04000000 /* first */
+
+/* transmit BD's status.
+*/
+#define T_R 0x80000000 /* ready bit */
+#define T_W 0x20000000 /* wrap bit */
+#define T_I 0x10000000 /* interrupt on completion */
+#define T_L 0x08000000 /* last */
+
+/* Rx Data buffer must be 4 bytes aligned in most cases.*/
+#define UCC_FAST_RX_ALIGN 4
+#define UCC_FAST_MRBLR_ALIGNMENT 4
+#define UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT 8
+
+/* Sizes
+*/
+#define UCC_FAST_URFS_MIN_VAL 0x88
+#define UCC_FAST_RECEIVE_VIRTUAL_FIFO_SIZE_FUDGE_FACTOR 8
+
+/* ucc_fast_channel_protocol_mode - UCC FAST mode.
+*/
+typedef enum ucc_fast_channel_protocol_mode {
+ UCC_FAST_PROTOCOL_MODE_HDLC = 0x00000000,
+ UCC_FAST_PROTOCOL_MODE_RESERVED01 = 0x00000001,
+ UCC_FAST_PROTOCOL_MODE_RESERVED_QMC = 0x00000002,
+ UCC_FAST_PROTOCOL_MODE_RESERVED02 = 0x00000003,
+ UCC_FAST_PROTOCOL_MODE_RESERVED_UART = 0x00000004,
+ UCC_FAST_PROTOCOL_MODE_RESERVED03 = 0x00000005,
+ UCC_FAST_PROTOCOL_MODE_RESERVED_EX_MAC_1 = 0x00000006,
+ UCC_FAST_PROTOCOL_MODE_RESERVED_EX_MAC_2 = 0x00000007,
+ UCC_FAST_PROTOCOL_MODE_RESERVED_BISYNC = 0x00000008,
+ UCC_FAST_PROTOCOL_MODE_RESERVED04 = 0x00000009,
+ UCC_FAST_PROTOCOL_MODE_ATM = 0x0000000A,
+ UCC_FAST_PROTOCOL_MODE_RESERVED05 = 0x0000000B,
+ UCC_FAST_PROTOCOL_MODE_ETHERNET = 0x0000000C,
+ UCC_FAST_PROTOCOL_MODE_RESERVED06 = 0x0000000D,
+ UCC_FAST_PROTOCOL_MODE_POS = 0x0000000E,
+ UCC_FAST_PROTOCOL_MODE_RESERVED07 = 0x0000000F
+} ucc_fast_channel_protocol_mode_e;
+
+/* ucc_fast_transparent_txrx - UCC Fast Transparent TX & RX
+*/
+typedef enum ucc_fast_transparent_txrx {
+ UCC_FAST_GUMR_TRANSPARENT_TTX_TRX_NORMAL = 0x00000000,
+ UCC_FAST_GUMR_TRANSPARENT_TTX_TRX_TRANSPARENT = 0x18000000
+} ucc_fast_transparent_txrx_e;
+
+/* UCC fast diagnostic mode
+*/
+typedef enum ucc_fast_diag_mode {
+ UCC_FAST_DIAGNOSTIC_NORMAL = 0x0,
+ UCC_FAST_DIAGNOSTIC_LOCAL_LOOP_BACK = 0x40000000,
+ UCC_FAST_DIAGNOSTIC_AUTO_ECHO = 0x80000000,
+ UCC_FAST_DIAGNOSTIC_LOOP_BACK_AND_ECHO = 0xC0000000
+} ucc_fast_diag_mode_e;
+
+/* UCC fast Sync length (transparent mode only)
+*/
+typedef enum ucc_fast_sync_len {
+ UCC_FAST_SYNC_LEN_NOT_USED = 0x0,
+ UCC_FAST_SYNC_LEN_AUTOMATIC = 0x00004000,
+ UCC_FAST_SYNC_LEN_8_BIT = 0x00008000,
+ UCC_FAST_SYNC_LEN_16_BIT = 0x0000C000
+} ucc_fast_sync_len_e;
+
+/* UCC fast RTS mode
+*/
+typedef enum ucc_fast_ready_to_send {
+ UCC_FAST_SEND_IDLES_BETWEEN_FRAMES = 0x00000000,
+ UCC_FAST_SEND_FLAGS_BETWEEN_FRAMES = 0x00002000
+} ucc_fast_ready_to_send_e;
+
+/* UCC fast receiver decoding mode
+*/
+typedef enum ucc_fast_rx_decoding_method {
+ UCC_FAST_RX_ENCODING_NRZ = 0x00000000,
+ UCC_FAST_RX_ENCODING_NRZI = 0x00000800,
+ UCC_FAST_RX_ENCODING_RESERVED0 = 0x00001000,
+ UCC_FAST_RX_ENCODING_RESERVED1 = 0x00001800
+} ucc_fast_rx_decoding_method_e;
+
+/* UCC fast transmitter encoding mode
+*/
+typedef enum ucc_fast_tx_encoding_method {
+ UCC_FAST_TX_ENCODING_NRZ = 0x00000000,
+ UCC_FAST_TX_ENCODING_NRZI = 0x00000100,
+ UCC_FAST_TX_ENCODING_RESERVED0 = 0x00000200,
+ UCC_FAST_TX_ENCODING_RESERVED1 = 0x00000300
+} ucc_fast_tx_encoding_method_e;
+
+/* UCC fast CRC length
+*/
+typedef enum ucc_fast_transparent_tcrc {
+ UCC_FAST_16_BIT_CRC = 0x00000000,
+ UCC_FAST_CRC_RESERVED0 = 0x00000040,
+ UCC_FAST_32_BIT_CRC = 0x00000080,
+ UCC_FAST_CRC_RESERVED1 = 0x000000C0
+} ucc_fast_transparent_tcrc_e;
+
+/* Fast UCC initialization structure.
+*/
+typedef struct ucc_fast_info {
+ int ucc_num;
+ qe_clock_e rx_clock;
+ qe_clock_e tx_clock;
+ u32 regs;
+ int irq;
+ u32 uccm_mask;
+ int bd_mem_part;
+ int brkpt_support;
+ int grant_support;
+ int tsa;
+ int cdp;
+ int cds;
+ int ctsp;
+ int ctss;
+ int tci;
+ int txsy;
+ int rtsm;
+ int revd;
+ int rsyn;
+ u16 max_rx_buf_length;
+ u16 urfs;
+ u16 urfet;
+ u16 urfset;
+ u16 utfs;
+ u16 utfet;
+ u16 utftt;
+ u16 ufpt;
+ ucc_fast_channel_protocol_mode_e mode;
+ ucc_fast_transparent_txrx_e ttx_trx;
+ ucc_fast_tx_encoding_method_e tenc;
+ ucc_fast_rx_decoding_method_e renc;
+ ucc_fast_transparent_tcrc_e tcrc;
+ ucc_fast_sync_len_e synl;
+} ucc_fast_info_t;
+
+typedef struct ucc_fast_private {
+ ucc_fast_info_t *uf_info;
+ ucc_fast_t *uf_regs; /* a pointer to memory map of UCC regs. */
+ u32 *p_ucce; /* a pointer to the event register in memory. */
+ u32 *p_uccm; /* a pointer to the mask register in memory. */
+ int enabled_tx; /* Whether channel is enabled for Tx (ENT) */
+ int enabled_rx; /* Whether channel is enabled for Rx (ENR) */
+ int stopped_tx; /* Whether channel has been stopped for Tx
+ (STOP_TX, etc.) */
+ int stopped_rx; /* Whether channel has been stopped for Rx */
+ u32 ucc_fast_tx_virtual_fifo_base_offset;/* pointer to base of Tx
+ virtual fifo */
+ u32 ucc_fast_rx_virtual_fifo_base_offset;/* pointer to base of Rx
+ virtual fifo */
+#ifdef STATISTICS
+ u32 tx_frames; /* Transmitted frames counter. */
+ u32 rx_frames; /* Received frames counter (only frames
+ passed to application). */
+ u32 tx_discarded; /* Discarded tx frames counter (frames that
+ were discarded by the driver due to errors).
+ */
+ u32 rx_discarded; /* Discarded rx frames counter (frames that
+ were discarded by the driver due to errors).
+ */
+#endif /* STATISTICS */
+ u16 mrblr; /* maximum receive buffer length */
+} ucc_fast_private_t;
+
+/* ucc_fast_init
+ * Initializes Fast UCC according to user provided parameters.
+ *
+ * uf_info - (In) pointer to the fast UCC info structure.
+ * uccf_ret - (Out) pointer to the fast UCC structure.
+ */
+int ucc_fast_init(ucc_fast_info_t * uf_info, ucc_fast_private_t ** uccf_ret);
+
+/* ucc_fast_free
+ * Frees all resources for fast UCC.
+ *
+ * uccf - (In) pointer to the fast UCC structure.
+ */
+void ucc_fast_free(ucc_fast_private_t * uccf);
+
+/* ucc_fast_enable
+ * Enables a fast UCC port.
+ * This routine enables Tx and/or Rx through the General UCC Mode Register.
+ *
+ * uccf - (In) pointer to the fast UCC structure.
+ * mode - (In) TX, RX, or both.
+ */
+void ucc_fast_enable(ucc_fast_private_t * uccf, comm_dir_e mode);
+
+/* ucc_fast_disable
+ * Disables a fast UCC port.
+ * This routine disables Tx and/or Rx through the General UCC Mode Register.
+ *
+ * uccf - (In) pointer to the fast UCC structure.
+ * mode - (In) TX, RX, or both.
+ */
+void ucc_fast_disable(ucc_fast_private_t * uccf, comm_dir_e mode);
+
+/* ucc_fast_irq
+ * Handles interrupts on fast UCC.
+ * Called from the general interrupt routine to handle interrupts on fast UCC.
+ *
+ * uccf - (In) pointer to the fast UCC structure.
+ */
+void ucc_fast_irq(ucc_fast_private_t * uccf);
+
+/* ucc_fast_transmit_on_demand
+ * Immediately forces a poll of the transmitter for data to be sent.
+ * Typically, the hardware performs a periodic poll for data that the
+ * transmit routine has set up to be transmitted. In cases where
+ * this polling cycle is not soon enough, this optional routine can
+ * be invoked to force a poll right away, instead. Proper use for
+ * each transmission for which this functionality is desired is to
+ * call the transmit routine and then this routine right after.
+ *
+ * uccf - (In) pointer to the fast UCC structure.
+ */
+void ucc_fast_transmit_on_demand(ucc_fast_private_t * uccf);
+
+u32 ucc_fast_get_qe_cr_subblock(int uccf_num);
+
+void ucc_fast_dump_regs(ucc_fast_private_t * uccf);
+
+#endif /* __UCC_FAST_H__ */
diff --git a/include/asm-powerpc/ucc_slow.h b/include/asm-powerpc/ucc_slow.h
new file mode 100644
index 0000000..531b87d
--- /dev/null
+++ b/include/asm-powerpc/ucc_slow.h
@@ -0,0 +1,309 @@
+/*
+ * Copyright (C) Freescale Semicondutor, Inc. 2006. All rights reserved.
+ *
+ * Author: Shlomi Gridish <gridish@freescale.com>
+ *
+ * Description:
+ * Internal header file for UCC SLOW unit routines.
+ *
+ * Changelog:
+ * Jun 28, 2006 Li Yang <LeoLi@freescale.com>
+ * - Reorganized as qe_lib
+ * - Merged to powerpc arch; add device tree support
+ * - Style fixes
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+#ifndef __UCC_SLOW_H__
+#define __UCC_SLOW_H__
+
+#include <linux/kernel.h>
+
+#include <asm/immap_qe.h>
+#include <asm/qe.h>
+
+#include "ucc.h"
+
+#define UCC_SLOW_SIZE_OF_BD QE_SIZEOF_BD
+
+/* transmit BD's status.
+*/
+#define T_R 0x80000000 /* ready bit */
+#define T_PAD 0x40000000 /* add pads to short frames */
+#define T_W 0x20000000 /* wrap bit */
+#define T_I 0x10000000 /* interrupt on completion */
+#define T_L 0x08000000 /* last */
+
+#define T_A 0x04000000 /* Address - the data transmitted as address
+ chars */
+#define T_TC 0x04000000 /* transmit CRC */
+#define T_CM 0x02000000 /* continuous mode */
+#define T_DEF 0x02000000 /* collision on previous attempt to transmit. */
+#define T_P 0x01000000 /* Preamble - send Preamble sequence before
+ data */
+#define T_HB 0x01000000 /* heartbeat. */
+#define T_NS 0x00800000 /* No Stop */
+#define T_LC 0x00800000 /* late collision. */
+#define T_RL 0x00400000 /* retransmission limit. */
+#define T_UN 0x00020000 /* underrun */
+#define T_CT 0x00010000 /* CTS lost */
+#define T_CSL 0x00010000 /* carrier sense lost. */
+#define T_RC 0x003c0000 /* retry count. */
+
+/* Receive BD's status.
+*/
+#define R_E 0x80000000 /* buffer empty */
+#define R_W 0x20000000 /* wrap bit */
+#define R_I 0x10000000 /* interrupt on reception */
+#define R_L 0x08000000 /* last */
+#define R_C 0x08000000 /* the last byte in this buffer is a cntl
+ char */
+#define R_F 0x04000000 /* first */
+#define R_A 0x04000000 /* the first byte in this buffer is address
+ byte */
+#define R_CM 0x02000000 /* continuous mode */
+#define R_ID 0x01000000 /* buffer close on reception of idles */
+#define R_M 0x01000000 /* Frame received because of promiscuous
+ mode. */
+#define R_AM 0x00800000 /* Address match */
+#define R_DE 0x00800000 /* Address match */
+#define R_LG 0x00200000 /* Break received */
+#define R_BR 0x00200000 /* Frame length violation */
+#define R_NO 0x00100000 /* Rx Non Octet Aligned Packet */
+#define R_FR 0x00100000 /* Framing Error (no stop bit) character
+ received */
+#define R_PR 0x00080000 /* Parity Error character received */
+#define R_AB 0x00080000 /* Frame Aborted */
+#define R_SH 0x00080000 /* frame is too short. */
+#define R_CR 0x00040000 /* CRC Error */
+#define R_OV 0x00020000 /* Overrun */
+#define R_CD 0x00010000 /* CD lost */
+#define R_CL 0x00010000 /* this frame is closed because of a
+ collision */
+
+/* Rx Data buffer must be 4 bytes aligned in most cases.*/
+#define UCC_SLOW_RX_ALIGN 4
+#define UCC_SLOW_MRBLR_ALIGNMENT 4
+#define UCC_SLOW_PRAM_SIZE 0x100
+#define ALIGNMENT_OF_UCC_SLOW_PRAM 64
+
+/* UCC Slow Channel Protocol Mode
+*/
+typedef enum ucc_slow_channel_protocol_mode {
+ UCC_SLOW_CHANNEL_PROTOCOL_MODE_QMC = 0x00000002, /* QMC */
+ UCC_SLOW_CHANNEL_PROTOCOL_MODE_UART = 0x00000004, /* UART */
+ UCC_SLOW_CHANNEL_PROTOCOL_MODE_BISYNC = 0x00000008 /* BISYNC */
+} ucc_slow_channel_protocol_mode_e;
+
+/* UCC Slow Transparent Transmit CRC (TCRC)
+*/
+typedef enum ucc_slow_transparent_tcrc {
+ UCC_SLOW_TRANSPARENT_TCRC_CCITT_CRC16 = 0x00000000, /* 16-bit
+ CCITT CRC
+ (HDLC).
+ (X16 + X12
+ + X5 + 1) */
+ UCC_SLOW_TRANSPARENT_TCRC_CRC16 = 0x00004000, /* CRC16 (BISYNC).
+ (X16 + X15 + X2 +
+ 1) */
+ UCC_SLOW_TRANSPARENT_TCRC_CCITT_CRC32 = 0x00008000 /* 32-bit
+ CCITT CRC
+ (Ethernet
+ and HDLC).
+ */
+} ucc_slow_transparent_tcrc_e;
+
+/* UCC Slow oversampling rate for transmitter (TDCR)
+*/
+typedef enum ucc_slow_tx_oversampling_rate {
+ UCC_SLOW_OVERSAMPLING_RATE_TX_TDCR_1 = 0x00000000, /* 1x clock
+ mode */
+ UCC_SLOW_OVERSAMPLING_RATE_TX_TDCR_8 = 0x00010000, /* 8x clock
+ mode */
+ UCC_SLOW_OVERSAMPLING_RATE_TX_TDCR_16 = 0x00020000, /* 16x clock
+ mode */
+ UCC_SLOW_OVERSAMPLING_RATE_TX_TDCR_32 = 0x00030000 /* 32x clock
+ mode */
+} ucc_slow_tx_oversampling_rate_e;
+
+/* UCC Slow Oversampling rate for receiver (RDCR)
+*/
+typedef enum ucc_slow_rx_oversampling_rate {
+ UCC_SLOW_OVERSAMPLING_RATE_RX_RDCR_1 = 0x00000000, /* 1x clock
+ mode */
+ UCC_SLOW_OVERSAMPLING_RATE_RX_RDCR_8 = 0x00004000, /* 8x clock
+ mode */
+ UCC_SLOW_OVERSAMPLING_RATE_RX_RDCR_16 = 0x00008000, /* 16x clock
+ mode */
+ UCC_SLOW_OVERSAMPLING_RATE_RX_RDCR_32 = 0x0000c000 /* 32x clock
+ mode */
+} ucc_slow_rx_oversampling_rate_e;
+
+/* UCC Slow Transmitter encoding method (TENC)
+*/
+typedef enum ucc_slow_tx_encoding_method {
+ UCC_SLOW_TRANSMITTER_ENCODING_METHOD_TENC_NRZ = 0x00000000,
+ UCC_SLOW_TRANSMITTER_ENCODING_METHOD_TENC_NRZI = 0x00000100
+} ucc_slow_tx_encoding_method_e;
+
+/* UCC Slow Receiver decoding method (RENC)
+*/
+typedef enum ucc_slow_rx_decoding_method {
+ UCC_SLOW_RECEIVER_DECODING_METHOD_RENC_NRZ = 0x00000000,
+ UCC_SLOW_RECEIVER_DECODING_METHOD_RENC_NRZI = 0x00000800
+} ucc_slow_rx_decoding_method_e;
+
+/* UCC Slow Diagnostic mode (DIAG)
+*/
+typedef enum ucc_slow_diag_mode {
+ UCC_SLOW_DIAG_MODE_NORMAL = 0x00000000,
+ UCC_SLOW_DIAG_MODE_LOOPBACK = 0x00000040,
+ UCC_SLOW_DIAG_MODE_ECHO = 0x00000080,
+ UCC_SLOW_DIAG_MODE_LOOPBACK_ECHO = 0x000000c0
+} ucc_slow_diag_mode_e;
+
+typedef struct ucc_slow_info {
+ int ucc_num;
+ qe_clock_e rx_clock;
+ qe_clock_e tx_clock;
+ ucc_slow_t *us_regs;
+ int irq;
+ u16 uccm_mask;
+ int data_mem_part;
+ int init_tx;
+ int init_rx;
+ u32 tx_bd_ring_len;
+ u32 rx_bd_ring_len;
+ int rx_interrupts;
+ int brkpt_support;
+ int grant_support;
+ int tsa;
+ int cdp;
+ int cds;
+ int ctsp;
+ int ctss;
+ int rinv;
+ int tinv;
+ int rtsm;
+ int rfw;
+ int tci;
+ int tend;
+ int tfl;
+ int txsy;
+ u16 max_rx_buf_length;
+ ucc_slow_transparent_tcrc_e tcrc;
+ ucc_slow_channel_protocol_mode_e mode;
+ ucc_slow_diag_mode_e diag;
+ ucc_slow_tx_oversampling_rate_e tdcr;
+ ucc_slow_rx_oversampling_rate_e rdcr;
+ ucc_slow_tx_encoding_method_e tenc;
+ ucc_slow_rx_decoding_method_e renc;
+} ucc_slow_info_t;
+
+typedef struct ucc_slow_private {
+ ucc_slow_info_t *us_info;
+ ucc_slow_t *us_regs; /* a pointer to memory map of UCC regs. */
+ ucc_slow_pram_t *us_pram; /* a pointer to the parameter RAM. */
+ uint us_pram_offset;
+ int enabled_tx; /* Whether channel is enabled for Tx (ENT) */
+ int enabled_rx; /* Whether channel is enabled for Rx (ENR) */
+ int stopped_tx; /* Whether channel has been stopped for Tx
+ (STOP_TX, etc.) */
+ int stopped_rx; /* Whether channel has been stopped for Rx */
+ struct list_head confQ; /* frames passed to chip waiting for tx */
+ u32 first_tx_bd_mask; /* mask is used in Tx routine to save status
+ and length for first BD in a frame. */
+ uint tx_base_offset; /* first BD in Tx BD table offset (In MURAM) */
+ uint rx_base_offset; /* first BD in Rx BD table offset (In MURAM) */
+ u8 *confBd; /* next BD for confirm after Tx */
+ u8 *tx_bd; /* next BD for new Tx request */
+ u8 *rx_bd; /* next BD to collect after Rx */
+ void *p_rx_frame; /* accumulating receive frame */
+ u16 *p_ucce; /* a pointer to the event register in memory.
+ */
+ u16 *p_uccm; /* a pointer to the mask register in memory.
+ */
+ u16 saved_uccm; /* a saved mask for the RX Interrupt bits. */
+#ifdef STATISTICS
+ u32 tx_frames; /* Transmitted frames counters. */
+ u32 rx_frames; /* Received frames counters (only frames
+ passed to application). */
+ u32 rx_discarded; /* Discarded frames counters (frames that
+ were discarded by the driver due to
+ errors). */
+#endif /* STATISTICS */
+} ucc_slow_private_t;
+
+/* ucc_slow_init
+ * Initializes Slow UCC according to provided parameters.
+ *
+ * us_info - (In) pointer to the slow UCC info structure.
+ * uccs_ret - (Out) pointer to the slow UCC structure.
+ */
+int ucc_slow_init(ucc_slow_info_t * us_info, ucc_slow_private_t ** uccs_ret);
+
+/* ucc_slow_free
+ * Frees all resources for slow UCC.
+ *
+ * uccs - (In) pointer to the slow UCC structure.
+ */
+void ucc_slow_free(ucc_slow_private_t * uccs);
+
+/* ucc_slow_enable
+ * Enables a fast UCC port.
+ * This routine enables Tx and/or Rx through the General UCC Mode Register.
+ *
+ * uccs - (In) pointer to the slow UCC structure.
+ * mode - (In) TX, RX, or both.
+ */
+void ucc_slow_enable(ucc_slow_private_t * uccs, comm_dir_e mode);
+
+/* ucc_slow_disable
+ * Disables a fast UCC port.
+ * This routine disables Tx and/or Rx through the General UCC Mode Register.
+ *
+ * uccs - (In) pointer to the slow UCC structure.
+ * mode - (In) TX, RX, or both.
+ */
+void ucc_slow_disable(ucc_slow_private_t * uccs, comm_dir_e mode);
+
+/* ucc_slow_poll_transmitter_now
+ * Immediately forces a poll of the transmitter for data to be sent.
+ * Typically, the hardware performs a periodic poll for data that the
+ * transmit routine has set up to be transmitted. In cases where
+ * this polling cycle is not soon enough, this optional routine can
+ * be invoked to force a poll right away, instead. Proper use for
+ * each transmission for which this functionality is desired is to
+ * call the transmit routine and then this routine right after.
+ *
+ * uccs - (In) pointer to the slow UCC structure.
+ */
+void ucc_slow_poll_transmitter_now(ucc_slow_private_t * uccs);
+
+/* ucc_slow_graceful_stop_tx
+ * Smoothly stops transmission on a specified slow UCC.
+ *
+ * uccs - (In) pointer to the slow UCC structure.
+ */
+void ucc_slow_graceful_stop_tx(ucc_slow_private_t * uccs);
+
+/* ucc_slow_stop_tx
+ * Stops transmission on a specified slow UCC.
+ *
+ * uccs - (In) pointer to the slow UCC structure.
+ */
+void ucc_slow_stop_tx(ucc_slow_private_t * uccs);
+
+/* ucc_slow_restart_x
+ * Restarts transmitting on a specified slow UCC.
+ *
+ * uccs - (In) pointer to the slow UCC structure.
+ */
+void ucc_slow_restart_x(ucc_slow_private_t * uccs);
+
+u32 ucc_slow_get_qe_cr_subblock(int uccs_num);
+
+#endif /* __UCC_SLOW_H__ */
diff --git a/include/asm-ppc/mpc83xx.h b/include/asm-ppc/mpc83xx.h
index 3c23fc4..6acd82f 100644
--- a/include/asm-ppc/mpc83xx.h
+++ b/include/asm-ppc/mpc83xx.h
@@ -62,12 +62,17 @@ #define MPC83xx_IRQ_EXT4 (20 + MPC83xx_I
#define MPC83xx_IRQ_EXT5 (21 + MPC83xx_IPIC_IRQ_OFFSET)
#define MPC83xx_IRQ_EXT6 (22 + MPC83xx_IPIC_IRQ_OFFSET)
#define MPC83xx_IRQ_EXT7 (23 + MPC83xx_IPIC_IRQ_OFFSET)
+#ifdef CONFIG_QUICC_ENGINE
+#define MPC83xx_IRQ_QE_HIGH (32 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_QE_LOW (33 + MPC83xx_IPIC_IRQ_OFFSET)
+#else
#define MPC83xx_IRQ_TSEC1_TX (32 + MPC83xx_IPIC_IRQ_OFFSET)
#define MPC83xx_IRQ_TSEC1_RX (33 + MPC83xx_IPIC_IRQ_OFFSET)
#define MPC83xx_IRQ_TSEC1_ERROR (34 + MPC83xx_IPIC_IRQ_OFFSET)
#define MPC83xx_IRQ_TSEC2_TX (35 + MPC83xx_IPIC_IRQ_OFFSET)
#define MPC83xx_IRQ_TSEC2_RX (36 + MPC83xx_IPIC_IRQ_OFFSET)
#define MPC83xx_IRQ_TSEC2_ERROR (37 + MPC83xx_IPIC_IRQ_OFFSET)
+#endif
#define MPC83xx_IRQ_USB2_DR (38 + MPC83xx_IPIC_IRQ_OFFSET)
#define MPC83xx_IRQ_USB2_MPH (39 + MPC83xx_IPIC_IRQ_OFFSET)
#define MPC83xx_IRQ_EXT0 (48 + MPC83xx_IPIC_IRQ_OFFSET)
@@ -93,6 +98,29 @@ #define MPC83xx_IRQ_GTM7 (85 + MPC83xx_I
#define MPC83xx_IRQ_GTM1 (90 + MPC83xx_IPIC_IRQ_OFFSET)
#define MPC83xx_IRQ_GTM5 (91 + MPC83xx_IPIC_IRQ_OFFSET)
+#ifdef CONFIG_QUICC_ENGINE
+/* Internal IRQs on MPC83xx QE IC */
+/* Not all of these exist on all MPC83xx QE implementations */
+
+#ifndef MPC83xx_QE_IRQ_OFFSET
+#define MPC83xx_QE_IRQ_OFFSET NR_IPIC_INTS
+#endif /* MPC83xx_QE_IRQ_OFFSET */
+
+#define MPC83xx_NR_QE_IC_INTS 64
+
+#define MPC83xx_QE_IRQ_SPI2 (1 + MPC83xx_QE_IRQ_OFFSET)
+#define MPC83xx_QE_IRQ_SPI1 (2 + MPC83xx_QE_IRQ_OFFSET)
+#define MPC83xx_QE_IRQ_USB (11 + MPC83xx_QE_IRQ_OFFSET)
+#define MPC83xx_QE_IRQ_UCC1 (32 + MPC83xx_QE_IRQ_OFFSET)
+#define MPC83xx_QE_IRQ_UCC2 (33 + MPC83xx_QE_IRQ_OFFSET)
+#define MPC83xx_QE_IRQ_UCC3 (34 + MPC83xx_QE_IRQ_OFFSET)
+#define MPC83xx_QE_IRQ_UCC4 (35 + MPC83xx_QE_IRQ_OFFSET)
+#define MPC83xx_QE_IRQ_UCC5 (40 + MPC83xx_QE_IRQ_OFFSET)
+#define MPC83xx_QE_IRQ_UCC6 (41 + MPC83xx_QE_IRQ_OFFSET)
+#define MPC83xx_QE_IRQ_UCC7 (42 + MPC83xx_QE_IRQ_OFFSET)
+#define MPC83xx_QE_IRQ_UCC8 (43 + MPC83xx_QE_IRQ_OFFSET)
+#endif /* CONFIG_QE */
+
#define MPC83xx_CCSRBAR_SIZE (1024*1024)
/* Let modules/drivers get at immrbar (physical) */
@@ -109,6 +137,20 @@ enum ppc_sys_devices {
MPC83xx_USB2_MPH,
MPC83xx_MDIO,
NUM_PPC_SYS_DEVS,
+#ifdef CONFIG_QUICC_ENGINE
+ MPC83xx_QE_UCC1,
+ MPC83xx_QE_UCC2,
+ MPC83xx_QE_UCC3,
+ MPC83xx_QE_UCC4,
+ MPC83xx_QE_UCC5,
+ MPC83xx_QE_UCC6,
+ MPC83xx_QE_UCC7,
+ MPC83xx_QE_UCC8,
+ MPC83xx_QE_SPI1,
+ MPC83xx_QE_SPI2,
+ MPC83xx_QE_USB,
+#endif /* CONFIG_QE */
+
};
#endif /* CONFIG_83xx */
diff --git a/include/linux/fsl_devices.h b/include/linux/fsl_devices.h
index a3a0e07..532211c 100644
--- a/include/linux/fsl_devices.h
+++ b/include/linux/fsl_devices.h
@@ -83,7 +83,6 @@ struct fsl_i2c_platform_data {
#define FSL_I2C_DEV_SEPARATE_DFSRR 0x00000001
#define FSL_I2C_DEV_CLOCK_5200 0x00000002
-
enum fsl_usb2_operating_modes {
FSL_USB2_MPH_HOST,
FSL_USB2_DR_HOST,
@@ -110,5 +109,43 @@ struct fsl_usb2_platform_data {
#define FSL_USB2_PORT0_ENABLED 0x00000001
#define FSL_USB2_PORT1_ENABLED 0x00000002
+/* Ethernet interface (phy management and speed)
+*/
+typedef enum enet_interface {
+ ENET_10_MII, /* 10 Base T, MII interface */
+ ENET_10_RMII, /* 10 Base T, RMII interface */
+ ENET_10_RGMII, /* 10 Base T, RGMII interface */
+ ENET_100_MII, /* 100 Base T, MII interface */
+ ENET_100_RMII, /* 100 Base T, RMII interface */
+ ENET_100_RGMII, /* 100 Base T, RGMII interface */
+ ENET_1000_GMII, /* 1000 Base T, GMII interface */
+ ENET_1000_RGMII, /* 1000 Base T, RGMII interface */
+ ENET_1000_TBI, /* 1000 Base T, TBI interface */
+ ENET_1000_RTBI /* 1000 Base T, RTBI interface */
+} enet_interface_e;
+
+struct ucc_geth_platform_data {
+ /* device specific information */
+ u32 device_flags;
+ u32 phy_reg_addr;
+
+ /* board specific information */
+ u32 board_flags;
+ u8 rx_clock;
+ u8 tx_clock;
+ u32 phy_id;
+ enet_interface_e phy_interface;
+ u32 phy_interrupt;
+ u8 mac_addr[6];
+};
+
+/* Flags related to UCC Gigabit Ethernet device features */
+#define FSL_UGETH_DEV_HAS_GIGABIT 0x00000001
+#define FSL_UGETH_DEV_HAS_COALESCE 0x00000002
+#define FSL_UGETH_DEV_HAS_RMON 0x00000004
+
+/* Flags in ucc_geth_platform_data */
+#define FSL_UGETH_BRD_HAS_PHY_INTR 0x00000001 /* if not set use a timer */
+
#endif /* _FSL_DEVICE_H_ */
#endif /* __KERNEL__ */
^ permalink raw reply related
* [PATCH 7/7] powerpc: mpc8360epb platform default config
From: Li Yang-r58472 @ 2006-06-28 14:23 UTC (permalink / raw)
To: 'Paul Mackerras'
Cc: linuxppc-dev, Phillips Kim-R1AAHA,
'linux-kernel@vger.kernel.org', Chu hanjin-r52514
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
---
arch/powerpc/configs/mpc8360epb_defconfig | 950 +++++++++++++++++++++++++++++
1 files changed, 950 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/configs/mpc8360epb_defconfig b/arch/powerpc/configs/mpc8360epb_defconfig
new file mode 100644
index 0000000..de8d76d
--- /dev/null
+++ b/arch/powerpc/configs/mpc8360epb_defconfig
@@ -0,0 +1,950 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.17-rc4
+# Wed Jun 28 15:46:59 2006
+#
+# CONFIG_PPC64 is not set
+CONFIG_PPC32=y
+CONFIG_PPC_MERGE=y
+CONFIG_MMU=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_RWSEM_XCHGADD_ALGORITHM=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_PPC=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_GENERIC_NVRAM=y
+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+CONFIG_ARCH_MAY_HAVE_PC_FDC=y
+CONFIG_PPC_OF=y
+CONFIG_PPC_UDBG_16550=y
+# CONFIG_GENERIC_TBSYNC is not set
+CONFIG_DEFAULT_UIMAGE=y
+
+#
+# Processor support
+#
+# CONFIG_CLASSIC32 is not set
+# CONFIG_PPC_52xx is not set
+# CONFIG_PPC_82xx is not set
+CONFIG_PPC_83xx=y
+# CONFIG_PPC_85xx is not set
+# CONFIG_40x is not set
+# CONFIG_44x is not set
+# CONFIG_8xx is not set
+# CONFIG_E200 is not set
+CONFIG_6xx=y
+CONFIG_83xx=y
+CONFIG_PPC_FPU=y
+CONFIG_DT_STATIC=y
+CONFIG_DT_IMAGE="oftree-8360.dts"
+CONFIG_PPC_STD_MMU=y
+CONFIG_PPC_STD_MMU_32=y
+# CONFIG_SMP is not set
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+
+#
+# General setup
+#
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_SYSCTL=y
+# CONFIG_AUDIT is not set
+# CONFIG_IKCONFIG is not set
+# CONFIG_RELAY is not set
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_EMBEDDED=y
+# CONFIG_KALLSYMS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+# CONFIG_EPOLL is not set
+CONFIG_SHMEM=y
+CONFIG_SLAB=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+# CONFIG_SLOB is not set
+
+#
+# Loadable module support
+#
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+# CONFIG_KMOD is not set
+
+#
+# Block layer
+#
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+CONFIG_DEFAULT_AS=y
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="anticipatory"
+CONFIG_QUICC_ENGINE=y
+CONFIG_PPC_GEN550=y
+# CONFIG_WANT_EARLY_SERIAL is not set
+
+#
+# Platform support
+#
+# CONFIG_MPC834x_SYS is not set
+CONFIG_MPC8360E_PB=y
+CONFIG_MPC836x=y
+
+#
+# Kernel options
+#
+# CONFIG_HIGHMEM is not set
+# CONFIG_HZ_100 is not set
+CONFIG_HZ_250=y
+# CONFIG_HZ_1000 is not set
+CONFIG_HZ=250
+CONFIG_PREEMPT_NONE=y
+# CONFIG_PREEMPT_VOLUNTARY is not set
+# CONFIG_PREEMPT is not set
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_PROC_DEVICETREE is not set
+# CONFIG_CMDLINE_BOOL is not set
+# CONFIG_PM is not set
+# CONFIG_SOFTWARE_SUSPEND is not set
+CONFIG_SECCOMP=y
+CONFIG_ISA_DMA_API=y
+
+#
+# Bus options
+#
+CONFIG_GENERIC_ISA_DMA=y
+# CONFIG_PPC_I8259 is not set
+CONFIG_PPC_INDIRECT_PCI=y
+CONFIG_FSL_SOC=y
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+
+#
+# PCCARD (PCMCIA/CardBus) support
+#
+# CONFIG_PCCARD is not set
+
+#
+# PCI Hotplug Support
+#
+# CONFIG_HOTPLUG_PCI is not set
+
+#
+# Advanced setup
+#
+# CONFIG_ADVANCED_OPTIONS is not set
+
+#
+# Default settings for advanced configuration options are used
+#
+CONFIG_HIGHMEM_START=0xfe000000
+CONFIG_LOWMEM_SIZE=0x30000000
+CONFIG_KERNEL_START=0xc0000000
+CONFIG_TASK_SIZE=0x80000000
+CONFIG_BOOT_LOAD=0x00800000
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+# CONFIG_NETDEBUG is not set
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+CONFIG_SYN_COOKIES=y
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_BIC=y
+# CONFIG_IPV6 is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+# CONFIG_NETFILTER is not set
+
+#
+# DCCP Configuration (EXPERIMENTAL)
+#
+# CONFIG_IP_DCCP is not set
+
+#
+# SCTP Configuration (EXPERIMENTAL)
+#
+# CONFIG_IP_SCTP is not set
+
+#
+# TIPC Configuration (EXPERIMENTAL)
+#
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_IEEE80211 is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_FW_LOADER is not set
+
+#
+# Connector - unified userspace <-> kernelspace linker
+#
+# CONFIG_CONNECTOR is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+# CONFIG_MTD is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Plug and Play support
+#
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_SX8 is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=32768
+CONFIG_BLK_DEV_INITRD=y
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+
+#
+# ATA/ATAPI/MFM/RLL support
+#
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+
+#
+# Fusion MPT device support
+#
+# CONFIG_FUSION is not set
+
+#
+# IEEE 1394 (FireWire) support
+#
+# CONFIG_IEEE1394 is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+
+#
+# Macintosh device drivers
+#
+# CONFIG_WINDFARM is not set
+
+#
+# Network device support
+#
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+
+#
+# ARCnet devices
+#
+# CONFIG_ARCNET is not set
+
+#
+# PHY device support
+#
+# CONFIG_PHYLIB is not set
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_CASSINI is not set
+# CONFIG_NET_VENDOR_3COM is not set
+
+#
+# Tulip family network device support
+#
+# CONFIG_NET_TULIP is not set
+# CONFIG_HP100 is not set
+CONFIG_NET_PCI=y
+# CONFIG_PCNET32 is not set
+# CONFIG_AMD8111_ETH is not set
+# CONFIG_ADAPTEC_STARFIRE is not set
+# CONFIG_B44 is not set
+# CONFIG_FORCEDETH is not set
+# CONFIG_DGRS is not set
+# CONFIG_EEPRO100 is not set
+CONFIG_E100=y
+# CONFIG_FEALNX is not set
+# CONFIG_NATSEMI is not set
+# CONFIG_NE2K_PCI is not set
+# CONFIG_8139CP is not set
+# CONFIG_8139TOO is not set
+# CONFIG_SIS900 is not set
+# CONFIG_EPIC100 is not set
+# CONFIG_SUNDANCE is not set
+# CONFIG_TLAN is not set
+# CONFIG_VIA_RHINE is not set
+
+#
+# Ethernet (1000 Mbit)
+#
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_E1000 is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_R8169 is not set
+# CONFIG_SIS190 is not set
+# CONFIG_SKGE is not set
+# CONFIG_SKY2 is not set
+# CONFIG_SK98LIN is not set
+# CONFIG_VIA_VELOCITY is not set
+# CONFIG_TIGON3 is not set
+# CONFIG_BNX2 is not set
+# CONFIG_GIANFAR is not set
+CONFIG_UCC_GETH=y
+# CONFIG_UGETH_NAPI is not set
+# CONFIG_UGETH_MAGIC_PACKET is not set
+# CONFIG_UGETH_FILTERING is not set
+# CONFIG_UGETH_TX_ON_DEMOND is not set
+
+#
+# Ethernet (10000 Mbit)
+#
+# CONFIG_CHELSIO_T1 is not set
+# CONFIG_IXGB is not set
+# CONFIG_S2IO is not set
+
+#
+# Token Ring devices
+#
+# CONFIG_TR is not set
+
+#
+# Wireless LAN (non-hamradio)
+#
+# CONFIG_NET_RADIO is not set
+
+#
+# Wan interfaces
+#
+# CONFIG_WAN is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_SHAPER is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# Telephony Support
+#
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_TSDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+# CONFIG_SERIAL_8250_PCI is not set
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+# CONFIG_SERIAL_8250_EXTENDED is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_JSM is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+
+#
+# IPMI
+#
+# CONFIG_IPMI_HANDLER is not set
+
+#
+# Watchdog Cards
+#
+CONFIG_WATCHDOG=y
+# CONFIG_WATCHDOG_NOWAYOUT is not set
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+CONFIG_83xx_WDT=y
+
+#
+# PCI-based Watchdog Cards
+#
+# CONFIG_PCIPCWATCHDOG is not set
+# CONFIG_WDTPCI is not set
+# CONFIG_NVRAM is not set
+CONFIG_GEN_RTC=y
+# CONFIG_GEN_RTC_X is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_RAW_DRIVER is not set
+
+#
+# TPM devices
+#
+# CONFIG_TCG_TPM is not set
+# CONFIG_TELCLOCK is not set
+
+#
+# I2C support
+#
+CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
+
+#
+# I2C Algorithms
+#
+# CONFIG_I2C_ALGOBIT is not set
+# CONFIG_I2C_ALGOPCF is not set
+# CONFIG_I2C_ALGOPCA is not set
+
+#
+# I2C Hardware Bus support
+#
+# CONFIG_I2C_ALI1535 is not set
+# CONFIG_I2C_ALI1563 is not set
+# CONFIG_I2C_ALI15X3 is not set
+# CONFIG_I2C_AMD756 is not set
+# CONFIG_I2C_AMD8111 is not set
+# CONFIG_I2C_I801 is not set
+# CONFIG_I2C_I810 is not set
+# CONFIG_I2C_PIIX4 is not set
+CONFIG_I2C_MPC=y
+# CONFIG_I2C_NFORCE2 is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_PROSAVAGE is not set
+# CONFIG_I2C_SAVAGE4 is not set
+# CONFIG_I2C_SIS5595 is not set
+# CONFIG_I2C_SIS630 is not set
+# CONFIG_I2C_SIS96X is not set
+# CONFIG_I2C_STUB is not set
+# CONFIG_I2C_VIA is not set
+# CONFIG_I2C_VIAPRO is not set
+# CONFIG_I2C_VOODOO3 is not set
+# CONFIG_I2C_PCA_ISA is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_SENSORS_DS1337 is not set
+# CONFIG_SENSORS_DS1374 is not set
+# CONFIG_SENSORS_EEPROM is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_M41T00 is not set
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+
+#
+# SPI support
+#
+# CONFIG_SPI is not set
+# CONFIG_SPI_MASTER is not set
+
+#
+# Dallas's 1-wire bus
+#
+# CONFIG_W1 is not set
+
+#
+# Hardware Monitoring support
+#
+CONFIG_HWMON=y
+# CONFIG_HWMON_VID is not set
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ADM9240 is not set
+# CONFIG_SENSORS_ASB100 is not set
+# CONFIG_SENSORS_ATXP1 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_FSCHER is not set
+# CONFIG_SENSORS_FSCPOS is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_LM63 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM87 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_LM92 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_SIS5595 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_VIA686A is not set
+# CONFIG_SENSORS_VT8231 is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83792D is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+# CONFIG_HWMON_DEBUG_CHIP is not set
+
+#
+# Misc devices
+#
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# Digital Video Broadcasting Devices
+#
+# CONFIG_DVB is not set
+
+#
+# Graphics support
+#
+# CONFIG_FB is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+CONFIG_USB_ARCH_HAS_EHCI=y
+# CONFIG_USB is not set
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+
+#
+# USB Gadget Support
+#
+# CONFIG_USB_GADGET is not set
+
+#
+# MMC/SD Card support
+#
+# CONFIG_MMC is not set
+
+#
+# LED devices
+#
+# CONFIG_NEW_LEDS is not set
+
+#
+# LED drivers
+#
+
+#
+# LED Triggers
+#
+
+#
+# InfiniBand support
+#
+# CONFIG_INFINIBAND is not set
+
+#
+# EDAC - error detection and reporting (RAS) (EXPERIMENTAL)
+#
+
+#
+# Real Time Clock
+#
+# CONFIG_RTC_CLASS is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_XATTR=y
+# CONFIG_EXT3_FS_POSIX_ACL is not set
+# CONFIG_EXT3_FS_SECURITY is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_INOTIFY=y
+# CONFIG_QUOTA is not set
+CONFIG_DNOTIFY=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_RAMFS=y
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+
+#
+# Network File Systems
+#
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+CONFIG_NFS_V4=y
+# CONFIG_NFS_DIRECTIO is not set
+# CONFIG_NFSD is not set
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+CONFIG_SUNRPC_GSS=y
+CONFIG_RPCSEC_GSS_KRB5=y
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+# CONFIG_9P_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+# CONFIG_MSDOS_PARTITION is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+
+#
+# Native Language Support
+#
+# CONFIG_NLS is not set
+
+#
+# QE Options
+#
+CONFIG_UCC1=y
+# CONFIG_UCC1_SLOW is not set
+CONFIG_UCC1_FAST=y
+
+#
+# UCC1 Protocols options
+#
+CONFIG_UCC1_GETH=y
+# CONFIG_UCC2 is not set
+# CONFIG_UCC3 is not set
+# CONFIG_UCC4 is not set
+# CONFIG_UCC5 is not set
+# CONFIG_UCC6 is not set
+# CONFIG_UCC7 is not set
+# CONFIG_UCC8 is not set
+CONFIG_UCC=y
+CONFIG_UCC_FAST=y
+CONFIG_UCC_GETH_CONF=y
+
+#
+# Library routines
+#
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+CONFIG_CRC32=y
+# CONFIG_LIBCRC32C is not set
+
+#
+# Instrumentation Support
+#
+# CONFIG_PROFILING is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_DEBUG_KERNEL is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_DEBUG_FS is not set
+# CONFIG_BOOTX_TEXT is not set
+CONFIG_SERIAL_TEXT_DEBUG=y
+# CONFIG_PPC_EARLY_DEBUG_LPAR is not set
+# CONFIG_PPC_EARLY_DEBUG_G5 is not set
+# CONFIG_PPC_EARLY_DEBUG_RTAS is not set
+# CONFIG_PPC_EARLY_DEBUG_MAPLE is not set
+# CONFIG_PPC_EARLY_DEBUG_ISERIES is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+
+#
+# Cryptographic options
+#
+CONFIG_CRYPTO=y
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_MD4 is not set
+CONFIG_CRYPTO_MD5=y
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_WP512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Hardware crypto devices
+#
^ permalink raw reply related
* Re: [PATCH 2/7] mtd: Add map file for mpc83xx boards
From: David Woodhouse @ 2006-06-28 14:27 UTC (permalink / raw)
To: Li Yang-r58472
Cc: Phillips Kim-R1AAHA, Yin Olivia-r63875,
'linux-kernel@vger.kernel.org', linuxppc-dev,
'linux-mtd@lists.infradead.org', Chu hanjin-r52514
In-Reply-To: <9FCDBA58F226D911B202000BDBAD467306E04FD3@zch01exm40.ap.freescale.net>
On Wed, 2006-06-28 at 22:23 +0800, Li Yang-r58472 wrote:
> Flash mapping file for MPC83xx MDS platforms.
I'm not accepting any more individual map drivers unless they're
absolutely necessary, which this one isn't.
Use a platform device and physmap. Or better still, extend physmap to
handle of_devices too and just stick the flash information in the device
tree.
--
dwmw2
^ permalink raw reply
* Re: backlight control broken in current Linus' and Paulus' trees
From: Michael Hanselmann @ 2006-06-28 14:21 UTC (permalink / raw)
To: Aristeu Sergio Rozanski Filho; +Cc: linuxppc-dev
In-Reply-To: <20060628133453.GA14876@cathedrallabs.org>
Hello
On Wed, Jun 28, 2006 at 10:34:53AM -0300, Aristeu Sergio Rozanski Filho wro=
te:
> the backlight control is broken in my PowerBook6,8 in latest git
> trees, both for pbbuttonsd (yes, I have CONFIG_PMAC_BACKLIGHT_LEGACY
> enabled) and for fblevel. the last one also allows values be set
> at least to 1000 and according to new code, it should be able to
> reach 127.
Legacy will stay 0-15, because that's what legacy is about. To use the
new interface, you have to use the sysfs interface.
I've submitted another patch for legacy support last night which is now
waiting for Linus to include it. Do you want me to send it to you
directly or do you want to wait until it's in the git kernels?
Greets,
Michael
--=20
Gentoo Linux developer, http://hansmi.ch/, http://forkbomb.ch/
< doogie> asuffield: how do you think dpkg was originally written? :|
< asuffield> by letting iwj get dangerously near a computer
-- in #debian-devel
^ permalink raw reply
* Re: 2.6.17-mm2
From: Martin J. Bligh @ 2006-06-28 14:43 UTC (permalink / raw)
To: Andrew Morton; +Cc: jeremy, drfickle, linux-kernel, mbligh, linuxppc64-dev
In-Reply-To: <20060628034748.018eecac.akpm@osdl.org>
Andrew Morton wrote:
> On Wed, 28 Jun 2006 03:42:15 -0700
> Andrew Morton <akpm@osdl.org> wrote:
>
>
>>his is caused by the vsprintf() changes. Right now, if you do
>>
>> snprintf(buf, 4, "1111111111111");
>>
>>the memory at `buf' gets [31 31 31 31 00], which is not good.
>>
>>This'll plug it, but I didn't check very hard whether it still has any
>>off-by-ones, or if breaks the intent of Jeremy's patch. I think it's OK..
Aha, you're a genius! How the hell did you figure that one out?
Andy / Steve ... any chance one of you could kick this through the
harness? Against -git10 or so, I'd think
Thanks,
M.
> That diff was against an older kernel and doesn't apply. This is against
> mainline:
>
> --- a/lib/vsprintf.c~vsnprintf-fix
> +++ a/lib/vsprintf.c
> @@ -259,7 +259,9 @@ int vsnprintf(char *buf, size_t size, co
> int len;
> unsigned long long num;
> int i, base;
> - char *str, *end, c;
> + char *str; /* Where we're writing to */
> + char *end; /* The last byte we can write to */
> + char c;
> const char *s;
>
> int flags; /* flags to number() */
> @@ -283,12 +285,12 @@ int vsnprintf(char *buf, size_t size, co
> }
>
> str = buf;
> - end = buf + size;
> + end = buf + size - 1;
>
> /* Make sure end is always >= buf */
> - if (end < buf) {
> + if (end < buf - 1) {
> end = ((void *)-1);
> - size = end - buf;
> + size = end - buf + 1;
> }
>
> for (; *fmt ; ++fmt) {
> @@ -494,7 +496,6 @@ int vsnprintf(char *buf, size_t size, co
> /* the trailing null byte doesn't count towards the total */
> return str-buf;
> }
> -
> EXPORT_SYMBOL(vsnprintf);
>
> /**
> _
>
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