* Re: no login prompt with ml403 + uartlite-->major numbers?
From: Grant Likely @ 2006-06-28 15:06 UTC (permalink / raw)
To: Robert Zach; +Cc: linuxppc-embedded
In-Reply-To: <200606281214.k5SCEQEf039728@webmail.so-logic.net>
On 6/28/06, Robert Zach <rza1@so-logic.co.at> wrote:
> Hello!
>
> I use the "Standart" ml403 Design with the uartlite instead of the
> uart16550...
>
> my kernel parameters are:
> "console=ttl0 ip=off root=/dev/xsysace/disc0/part3 rw"
>
> It boots correctly, but i got no login prompt!!
> getty is started with init.
> my inittab looks like:
> ...
> ::respawn:/sbin/getty 9600 ttl0
Looks ok. busybox I assume. You might try:
ttl0::respawn:/sbin/getty 9600 ttl0
You could try just launching a shell on the console. Then you can
look around and see what's there:
::respace:/bin/sh
> ...
>
> I use devfs.
Ugh. You should turn off devfs and build a static /dev folder for the
time being. Otherwise you've got no idea if devfs is putting the
right things into /dev. If you *really* want to, you can go back to
devfs later (but I don't recommend it).
> Is the inittab entry correct?
I think so
> Which device is the uartlite in devfs?
I don't know; read the source. Look for where it registers with devfs
to get the expected name. Does the uartlite driver you're using even
support devfs?
>
> Which major numbers uses the uartlite?
I don't know; it should be easy to find in the driver source
Cheers,
g.
--
Grant Likely, B.Sc. P.Eng.
Secret Lab Technologies Ltd.
grant.likely@secretlab.ca
(403) 399-0195
^ permalink raw reply
* Re: 2.6.17-mm2
From: Jeremy Fitzhardinge @ 2006-06-28 15:43 UTC (permalink / raw)
To: Andrew Morton; +Cc: linuxppc64-dev, linux-kernel, mbligh, Martin J. Bligh
In-Reply-To: <20060628034215.c3008299.akpm@osdl.org>
Andrew Morton wrote:
> This is caused by the vsprintf() changes. Right now, if you do
>
> snprintf(buf, 4, "1111111111111");
>
> the memory at `buf' gets [31 31 31 31 00], which is not good.
>
> This'll plug it, but I didn't check very hard whether it still has any
> off-by-ones, or if breaks the intent of Jeremy's patch. I think it's OK..
>
Damn. This patch doesn't look right; the intent is that 'end' point to
just beyond the formatted string. I'm pretty sure I tested this, since
its the most obvious test. Clearly not enough. I'll look into it.
J
^ permalink raw reply
* Re: how to get individual patches
From: David H. Lynch Jr. @ 2006-06-28 16:18 UTC (permalink / raw)
To: linuxppc-embedded
In-Reply-To: <528646bc0606280209m4ce91cb0wc3cab2f2d3aec1a7@mail.gmail.com>
Grant Likely wrote:
> On 6/28/06, David H. Lynch Jr. <dhlii@dlasys.net> wrote:
>>
>> The bsp I am working on works with 2.6.16.21 but fails with 2.6.17.
>>
>> How can I find the individual patches that make up the transition
>> from 2.6.16.21 to 2.6.17 ?
>
> Unfortunately, there isn't a direct line between .16.21 and .17 which
> makes it complicated. Does your bsp work with .16? If so; you can
> use the 'git bisect' command to figure out exactly where the
> regression occured.
>
> If it doesn't work on .16; you can do a bisect between .16 and .16.21
> to figure out what patch is missing between .16 and .17.
>
> $ git bisect good v2.6.16
> $ git bisect bad # the head of the tree
> compile, test, etc.
> $ git bisect good|bad # depends on whether it works or not
> compile, test, etc
> $ git bisect good|bad # you get the idea... repeat until it's
> narrowed down
> $ git log # see where you are in the git tree.
Thanks,
At the moment I am not working out of a git tree - but I was
previously.
What I have works with everything from 2.6.15 through 2.6.16.21 -
or atleast the 15+ odd interim steps I tried.
It fails if I go from 2.6.16 to 2.6.17.
I can probably actually check into why it is not working - looks
alot like an ml403 mmu hang posted earlier (I am working with a Xilinx V4).
But I was hoping I could get away with brute force/divide and
conquer and isolate it to a single patch before actually trying to
figure out the problem.
I am going to have to get better at git.
>
> Cheers,
> g.
>
--
Dave Lynch DLA Systems
Software Development: Embedded Linux
717.627.3770 dhlii@dlasys.net http://www.dlasys.net
fax: 1.253.369.9244 Cell: 1.717.587.7774
Over 25 years' experience in platforms, languages, and technologies too numerous to list.
"Any intelligent fool can make things bigger and more complex... It takes a touch of genius - and a lot of courage to move in the opposite direction."
Albert Einstein
^ permalink raw reply
* Re: how to get individual patches
From: David H. Lynch Jr. @ 2006-06-28 16:22 UTC (permalink / raw)
To: linuxppc-embedded
In-Reply-To: <44A23E9A.50004@cambridgebroadband.com>
Alex Zeffertt wrote:
>
> For diffs of individual files between official kernel releases you can
> use
>
> http://www.linuxhq.com/kernel/
>
> It's really good!
They appear to be updating or something at the moment. I can not get
to most pages.
>
> Alex
>
--
Dave Lynch DLA Systems
Software Development: Embedded Linux
717.627.3770 dhlii@dlasys.net http://www.dlasys.net
fax: 1.253.369.9244 Cell: 1.717.587.7774
Over 25 years' experience in platforms, languages, and technologies too numerous to list.
"Any intelligent fool can make things bigger and more complex... It takes a touch of genius - and a lot of courage to move in the opposite direction."
Albert Einstein
^ permalink raw reply
* Re: [PATCH 1/7] powerpc: Add mpc8360epb platform support
From: Vitaly Bordug @ 2006-06-28 16:58 UTC (permalink / raw)
To: Li Yang-r58472
Cc: Kim-R1AAHA, Yin Olivia-r63875, Phillips,
'linux-kernel@vger.kernel.org', linuxppc-dev,
'Paul Mackerras', Chu hanjin-r52514
In-Reply-To: <9FCDBA58F226D911B202000BDBAD467306E04FD2@zch01exm40.ap.freescale.net>
On Wed, 28 Jun 2006 22:23:03 +0800
Li Yang-r58472 <LeoLi@freescale.com> wrote:
> The patch adds mpc8360e MDS Processor Board support.
Far too short comment I guess.. There should be some information at least, what u-boot modifications are required, what family being introduced, etc.
>
> Signed-off-by: Li Yang <leoli@freescale.com>
> Signed-off-by: Yin Olivia <hong-hua.yin@freescale.com>
> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
>
> ---
> arch/powerpc/platforms/83xx/Kconfig | 13 ++
> arch/powerpc/platforms/83xx/Makefile | 1
> arch/powerpc/platforms/83xx/mpc8360e_pb.c | 213 +++++++++++++++++++++++++++++
> arch/powerpc/platforms/83xx/mpc8360e_pb.h | 31 ++++
> 4 files changed, 258 insertions(+), 0 deletions(-)
>
> diff --git a/arch/powerpc/platforms/83xx/Kconfig b/arch/powerpc/platforms/83xx/Kconfig
> index 7675e67..04c4508 100644
> --- a/arch/powerpc/platforms/83xx/Kconfig
> +++ b/arch/powerpc/platforms/83xx/Kconfig
> @@ -16,6 +16,13 @@ config MPC834x_SYS
> 3 PCI slots. The PIBs PCI initialization is the bootloader's
> responsiblilty.
>
> +config MPC8360E_PB
> + bool "Freescale MPC8360E PB"
> + select DEFAULT_UIMAGE
> + select QUICC_ENGINE
> + help
> + This option enables support for the MPC836x EMDS Processor Board.
> +
> endchoice
I don't think this is really required option. I guess 836x + QUICC_ENGINE should be enough (with a proviso that 8360 won't boot without qe.
>
> config MPC834x
> @@ -24,4 +31,10 @@ config MPC834x
> select PPC_INDIRECT_PCI
> default y if MPC834x_SYS
>
> +config MPC836x
> + bool
> + select PPC_UDBG_16550
debug option made default?
> + select PPC_INDIRECT_PCI
> + default y if MPC8360E_PB
> +
> endmenu
> diff --git a/arch/powerpc/platforms/83xx/Makefile b/arch/powerpc/platforms/83xx/Makefile
> index 5c72367..0c9ea5c 100644
> --- a/arch/powerpc/platforms/83xx/Makefile
> +++ b/arch/powerpc/platforms/83xx/Makefile
> @@ -4,3 +4,4 @@ #
> obj-y := misc.o
> obj-$(CONFIG_PCI) += pci.o
> obj-$(CONFIG_MPC834x_SYS) += mpc834x_sys.o
> +obj-$(CONFIG_MPC8360E_PB) += mpc8360e_pb.o
> diff --git a/arch/powerpc/platforms/83xx/mpc8360e_pb.c b/arch/powerpc/platforms/83xx/mpc8360e_pb.c
> new file mode 100644
> index 0000000..b4ddb0a
> --- /dev/null
> +++ b/arch/powerpc/platforms/83xx/mpc8360e_pb.c
> @@ -0,0 +1,213 @@
> +/*
> + * Copyright (C) Freescale Semicondutor, Inc. 2006. All rights reserved.
> + *
> + * Author: Li Yang <LeoLi@freescale.com>
> + * Yin Olivia <Hong-hua.Yin@freescale.com>
> + *
> + * Description:
> + * MPC8360E MDS PB board specific routines.
> + *
> + * Changelog:
> + * Jun 21, 2006 Initial version
> + *
No changelog entries for new files please... git tracks it good enough.
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License as published by the
> + * Free Software Foundation; either version 2 of the License, or (at your
> + * option) any later version.
> + */
> +
> +#include <linux/config.h>
> +#include <linux/stddef.h>
> +#include <linux/kernel.h>
> +#include <linux/init.h>
> +#include <linux/errno.h>
> +#include <linux/reboot.h>
> +#include <linux/pci.h>
> +#include <linux/kdev_t.h>
> +#include <linux/major.h>
> +#include <linux/console.h>
> +#include <linux/delay.h>
> +#include <linux/seq_file.h>
> +#include <linux/root_dev.h>
> +#include <linux/initrd.h>
> +
> +#include <asm/system.h>
> +#include <asm/atomic.h>
> +#include <asm/time.h>
> +#include <asm/io.h>
> +#include <asm/machdep.h>
> +#include <asm/ipic.h>
> +#include <asm/bootinfo.h>
> +#include <asm/irq.h>
> +#include <asm/prom.h>
> +#include <asm/udbg.h>
> +#include <sysdev/fsl_soc.h>
> +#ifdef CONFIG_QUICC_ENGINE
> +#include <asm/immap_qe.h>
> +#include <asm/qe_ic.h>
> +#endif /* CONFIG_QUICC_ENGINE */
> +#include "mpc83xx.h"
> +#include "mpc8360e_pb.h"
> +
> +#undef DEBUG
> +
hmmm? Does it relate nicely with below ?
> +#ifdef DEBUG
> +#define DBG(fmt...) udbg_printf(fmt)
> +#else
> +#define DBG(fmt...)
> +#endif
> +
> +
> +#ifndef CONFIG_PCI
> +unsigned long isa_io_base = 0;
> +unsigned long isa_mem_base = 0;
> +#endif
> +
> +#ifdef CONFIG_QUICC_ENGINE
> +extern void qe_reset(void);
> +extern int par_io_of_config(struct device_node *np);
> +#endif /* CONFIG_QUICC_ENGINE */
I bet this should go to the .h file...
> +
> +/* ************************************************************************
> + *
> + * Setup the architecture
> + *
> + */
> +static void __init mpc8360_sys_setup_arch(void)
> +{
> + struct device_node *np;
> +
> +#ifdef CONFIG_QUICC_ENGINE
> + u8 *bcsr_regs;
> +#endif
> +
> + if (ppc_md.progress)
> + ppc_md.progress("mpc8360_sys_setup_arch()", 0);
> +
> + np = of_find_node_by_type(NULL, "cpu");
> + if (np != 0) {
> + unsigned int *fp =
> + (int *)get_property(np, "clock-frequency", NULL);
> + if (fp != 0)
> + loops_per_jiffy = *fp / HZ;
> + else
> + loops_per_jiffy = 50000000 / HZ;
> + of_node_put(np);
> + }
> +#ifdef CONFIG_PCI
> + for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;)
> + add_bridge(np);
> +
> + ppc_md.pci_swizzle = common_swizzle;
> + ppc_md.pci_exclude_device = mpc83xx_exclude_device;
> +#endif
> +
> +#ifdef CONFIG_QUICC_ENGINE
> + qe_reset();
> +
> + for (np = NULL; (np = of_find_node_by_name(np, "ucc")) != NULL;)
> + par_io_of_config(np);
> +
> + /* Reset the Ethernet PHY */
> + bcsr_regs = (u8 *) ioremap(BCSR_PHYS_ADDR, BCSR_SIZE);
> + bcsr_regs[9] &= ~0x20;
> + udelay(1000);
> + bcsr_regs[9] |= 0x20;
> + iounmap(bcsr_regs);
> +
And if we have a design, which do not contain real ethernet UCC usage? Or UCC geth is disabled somehow explicitly? Stuff like that normally goes to the callback that is going to be triggered upon Etherbet init.
> +#endif /* CONFIG_QUICC_ENGINE */
> +
> +#ifdef CONFIG_BLK_DEV_INITRD
> + if (initrd_start)
> + ROOT_DEV = Root_RAM0;
> + else
> +#endif
> +#ifdef CONFIG_ROOT_NFS
> + ROOT_DEV = Root_NFS;
> +#else
> + ROOT_DEV = Root_HDA1;
> +#endif
> +}
> +
> +void __init mpc8360_sys_init_IRQ(void)
> +{
> + u8 senses[8] = {
> + 0, /* EXT 0 */
> + IRQ_SENSE_LEVEL, /* EXT 1 */
> + IRQ_SENSE_LEVEL, /* EXT 2 */
> + 0, /* EXT 3 */
> +#ifdef CONFIG_PCI
> + IRQ_SENSE_LEVEL, /* EXT 4 */
> + IRQ_SENSE_LEVEL, /* EXT 5 */
> + IRQ_SENSE_LEVEL, /* EXT 6 */
> + IRQ_SENSE_LEVEL, /* EXT 7 */
> +#else
> + 0, /* EXT 4 */
> + 0, /* EXT 5 */
> + 0, /* EXT 6 */
> + 0, /* EXT 7 */
> +#endif
> + };
> +
> + ipic_init(get_immrbase() + 0x00700, 0, 0, senses, 8);
> +
> + /* Initialize the default interrupt mapping priorities,
> + * in case the boot rom changed something on us.
> + */
> + ipic_set_default_priority();
> +
> +#ifdef CONFIG_QUICC_ENGINE
> + qe_ic_init(get_qe_base() + 0x00000080,
> + (QE_IC_LOW_SIGNAL | QE_IC_HIGH_SIGNAL), QE_IRQ_OFFSET);
> +#endif /* CONFIG_QUICC_ENGINE */
> +}
> +
> +#if defined(CONFIG_I2C_MPC) && defined(CONFIG_SENSORS_DS1374)
> +extern ulong ds1374_get_rtc_time(void);
> +extern int ds1374_set_rtc_time(ulong);
> +
> +static int __init mpc8360_rtc_hookup(void)
> +{
> + struct timespec tv;
> +
> + ppc_md.get_rtc_time = ds1374_get_rtc_time;
> + ppc_md.set_rtc_time = ds1374_set_rtc_time;
> +
> + tv.tv_nsec = 0;
> + tv.tv_sec = (ppc_md.get_rtc_time) ();
> + do_settimeofday(&tv);
> +
> + return 0;
> +}
> +
> +late_initcall(mpc8360_rtc_hookup);
> +#endif
> +
> +/*
> + * Called very early, MMU is off, device-tree isn't unflattened
> + */
> +static int __init mpc8360_sys_probe(void)
> +{
> + char *model = of_get_flat_dt_prop(of_get_flat_dt_root(),
> + "model", NULL);
> + if (model == NULL)
> + return 0;
> + if (strcmp(model, "MPC8360EPB"))
> + return 0;
> +
> + DBG("MPC8360EMDS-PB found\n");
> +
> + return 1;
> +}
> +
> +define_machine(mpc8360_sys) {
> + .name = "MPC8360E PB",
> + .probe = mpc8360_sys_probe,
> + .setup_arch = mpc8360_sys_setup_arch,
> + .init_IRQ = mpc8360_sys_init_IRQ,
> + .get_irq = ipic_get_irq,
> + .restart = mpc83xx_restart,
> + .time_init = mpc83xx_time_init,
> + .calibrate_decr = generic_calibrate_decr,
> + .progress = udbg_progress,
> +};
> diff --git a/arch/powerpc/platforms/83xx/mpc8360e_pb.h b/arch/powerpc/platforms/83xx/mpc8360e_pb.h
> new file mode 100644
> index 0000000..4243f4a
> --- /dev/null
> +++ b/arch/powerpc/platforms/83xx/mpc8360e_pb.h
> @@ -0,0 +1,31 @@
> +/*
> + * Copyright (C) Freescale Semicondutor, Inc. 2006. All rights reserved.
> + *
> + * Author: Li Yang <LeoLi@freescale.com>
> + * Yin Olivia <Hong-hua.Yin@freescale.com>
> + *
> + * Description:
> + * MPC8360E MDS PB board specific header.
> + *
> + * Changelog:
> + * Jun 21, 2006 Initial version
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License as published by the
> + * Free Software Foundation; either version 2 of the License, or (at your
> + * option) any later version.
> + *
> + */
> +
> +#ifndef __MACH_MPC83XX_SYS_H__
> +#define __MACH_MPC83XX_SYS_H__
> +
> +#define BCSR_PHYS_ADDR ((uint)0xf8000000)
> +#define BCSR_SIZE ((uint)(32 * 1024))
> +
> +#define PIRQA MPC83xx_IRQ_EXT4
> +#define PIRQB MPC83xx_IRQ_EXT5
> +#define PIRQC MPC83xx_IRQ_EXT6
> +#define PIRQD MPC83xx_IRQ_EXT7
> +
Hrm, isn't PCI irq stuff encoded to the dts? Upper pci-related defines seem redundant...
> +#endif /* __MACH_MPC83XX_SYS_H__ */
>
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-dev
>
>
--
Sincerely,
Vitaly
^ permalink raw reply
* Re: [PATCH 3/7] powerpc: Add QE library qe_lib--common files
From: Christoph Hellwig @ 2006-06-28 17:09 UTC (permalink / raw)
To: Li Yang-r58472
Cc: Phillips Kim-R1AAHA, 'linux-kernel@vger.kernel.org',
linuxppc-dev, 'Paul Mackerras', Gridish Shlomi-RM96313,
Chu hanjin-r52514
In-Reply-To: <9FCDBA58F226D911B202000BDBAD467306E04FD4@zch01exm40.ap.freescale.net>
All these config options to descibe hardware variants are not acceptable.
Please describe the hardware layout in the device tree.
^ permalink raw reply
* Re: [PATCH 4/7] powerpc: Add QE library qe_lib--ucc support
From: Christoph Hellwig @ 2006-06-28 17:10 UTC (permalink / raw)
To: Li Yang-r58472
Cc: Phillips Kim-R1AAHA, 'linux-kernel@vger.kernel.org',
linuxppc-dev, 'Paul Mackerras', Gridish Shlomi-RM96313,
Chu hanjin-r52514
In-Reply-To: <9FCDBA58F226D911B202000BDBAD467306E04FD5@zch01exm40.ap.freescale.net>
> +int ucc_set_qe_mux_mii_mng(int ucc_num)
> +{
> + unsigned long flags;
> +
> + local_irq_save(flags);
> + out_be32(&qe_immr->qmx.cmxgcr,
> + ((in_be32(&qe_immr->qmx.cmxgcr) &
> + ~QE_CMXGCR_MII_ENET_MNG) |
> + (ucc_num << QE_CMXGCR_MII_ENET_MNG_SHIFT)));
> + local_irq_restore(flags);
Using local_irq_save to protect hardware access is wrong. Please use
spinlocks.
^ permalink raw reply
* CROSS_COMPILE - namespace collision
From: Lee Revell @ 2006-06-28 17:28 UTC (permalink / raw)
To: linuxppc-embedded
I have not been able to get readline 5.1 to compile with the ELDK - it
places the value of CROSS_COMPILE in the gcc command line and thus fails
with "No such file or directory". I emailed the readline maintainer and
got this response:
"The bash Makefiles expect CROSS_COMPILE
to expand to a preprocessor option, and will fail otherwise."
I can make it work with a hack, but I thought this might be interesting
info.
Any comments?
Lee
^ permalink raw reply
* Re: block after "io scheduler noop registered"
From: Vitaly Bordug @ 2006-06-28 17:48 UTC (permalink / raw)
To: linuxppc-embedded
In-Reply-To: <J1KRSY$2A22F25EF5BB111FA515FFA9A4DCCD71@libero.it>
On Wed, 28 Jun 2006 16:48:34 +0200
"morelli.gab" <morelli.gab@libero.it> wrote:
> Hi All,
>
> i,m upgrading the linux kernel 2.4 from 2.6, during the phase of restart on my card the system blocks on message "io scheduler noop registered".
> the board mount MPC875 processor
>
>
> ...
> Serial: CPM driver $Revision: 0.01 $
> ttyCPM0 at MMIO 0xf0000a80 (irq = 20) is a CPM UART
> ttyCPM1 at MMIO 0xf0000a90 (irq = 19) is a CPM UART
> io scheduler noop registered
You should add the proper cpm uart initialization bits to the board-specific code, as say 885ads does (ppc/platforms/mpc885ads_setup.c).
What experienced is uart misconfiguration which alters pins in a way the console doesn't like very much.
--
Sincerely,
Vitaly
^ permalink raw reply
* vm_region_alloc failing
From: Owen Stampflee @ 2006-06-28 17:21 UTC (permalink / raw)
To: linuxppc-dev
I am currently working on getting OFED (an Infiniband stack) working on
an Extreme Engineering Xpdite4000
( http://xes-inc.com/Products/XPedite4000/XPedite4000.html ) with 2.6.11
(the vendor supplied kernel).
The IB code calls dma_alloc_consistant 1024 times which then calls
vm_region_alloc. On the 501st iteration vm_region_alloc fails because
addr is greater than end (nospc).
With that known, I am curious as to what would cause that type failure
and what potential fixes there are for it.
Thanks,
Owen
^ permalink raw reply
* 2.6 kernel on XUPV2pro / ML300 board!
From: Ameet Patil @ 2006-06-28 17:50 UTC (permalink / raw)
To: linuxppc-embedded
Hi,
I have a XUPV2Pro Xilinx Embedded PPC405 board which is similar in
many respects to the ML3XX series. With good support in the kernel
source tree, I was easily able to compile the 2.4.26 linux kernel to run
on it.
However, I wanted 2.6 kernel to run on it. For some reason, the Xilinx
drivers and the OCP code went missing in the 2.6 kernel tree.
Does anyone know why did 2.6 kernel drop the Xilinx ML300 board
drivers (SysACE, Ethernet, Frame Buffer) which were present in the 2.4
kernel code tree? It is because of porting issues?
Anyway, I have ported the old 2.4 Xilinx drivers (Sysace and Ethernet)
to 2.6.17.1 kernel. If anyone is interested to test them, please let me
know. I shall put out a patch soon...
Thanks,
-Ameet
^ permalink raw reply
* Re: Xilinx SystemACE driver for 2.6
From: Ameet Patil @ 2006-06-28 18:17 UTC (permalink / raw)
To: linuxppc-embedded
Hi,
I have ported System Ace driver from 2.4 to 2.6. Please post the
patch soon.
-Ameet
^ permalink raw reply
* Re: 2.6.17-mm2
From: Andrew Morton @ 2006-06-28 19:11 UTC (permalink / raw)
To: Martin J. Bligh; +Cc: jeremy, drfickle, linux-kernel, mbligh, linuxppc64-dev
In-Reply-To: <44A29582.7050403@google.com>
On Wed, 28 Jun 2006 07:43:14 -0700
"Martin J. Bligh" <mbligh@google.com> wrote:
> Andrew Morton wrote:
> > On Wed, 28 Jun 2006 03:42:15 -0700
> > Andrew Morton <akpm@osdl.org> wrote:
> >
> >
> >>his is caused by the vsprintf() changes. Right now, if you do
> >>
> >> snprintf(buf, 4, "1111111111111");
> >>
> >>the memory at `buf' gets [31 31 31 31 00], which is not good.
> >>
> >>This'll plug it, but I didn't check very hard whether it still has any
> >>off-by-ones, or if breaks the intent of Jeremy's patch. I think it's OK..
>
> Aha, you're a genius!
That's not what my kids say.
> How the hell did you figure that one out?
Found a way to reproduce it - do `cat /proc/slabinfo > /dev/null' in a
tight loop. With that happening, a little two-way wasn't able to make
it through `dbench 4' without soiling the upholstery. Then bisection-searching.
^ permalink raw reply
* RE: 2.6 kernel on XUPV2pro / ML300 board!
From: Rick Moleres @ 2006-06-28 18:42 UTC (permalink / raw)
To: Ameet Patil, linuxppc-embedded
Ameet,
Xilinx is working with MontaVista to create an ML40x LSP (for the Xilinx
ML403/ML405 boards) and port the ML300 LSP to the MV Linux 2.6
distribution, and once it's ready MontaVista plans to push the ported
drivers to the Linux 2.6 tree. I don't have an exact timeframe, but I
hope this is very soon.
-Rick
-----Original Message-----
From: linuxppc-embedded-bounces+moleres=3Dxilinx.com@ozlabs.org
[mailto:linuxppc-embedded-bounces+moleres=3Dxilinx.com@ozlabs.org] On
Behalf Of Ameet Patil
Sent: Wednesday, June 28, 2006 11:50 AM
To: linuxppc-embedded@ozlabs.org
Subject: 2.6 kernel on XUPV2pro / ML300 board!
Hi,
I have a XUPV2Pro Xilinx Embedded PPC405 board which is similar in=20
many respects to the ML3XX series. With good support in the kernel=20
source tree, I was easily able to compile the 2.4.26 linux kernel to run
on it.
However, I wanted 2.6 kernel to run on it. For some reason, the Xilinx=20
drivers and the OCP code went missing in the 2.6 kernel tree.
Does anyone know why did 2.6 kernel drop the Xilinx ML300 board
drivers (SysACE, Ethernet, Frame Buffer) which were present in the 2.4
kernel code tree? It is because of porting issues?
Anyway, I have ported the old 2.4 Xilinx drivers (Sysace and Ethernet)=20
to 2.6.17.1 kernel. If anyone is interested to test them, please let me=20
know. I shall put out a patch soon...
Thanks,
-Ameet
_______________________________________________
Linuxppc-embedded mailing list
Linuxppc-embedded@ozlabs.org
https://ozlabs.org/mailman/listinfo/linuxppc-embedded
^ permalink raw reply
* Re: [PATCH 3/7] powerpc: Add QE library qe_lib--common files
From: Kumar Gala @ 2006-06-28 19:19 UTC (permalink / raw)
To: Li Yang-r58472
Cc: Phillips Kim-R1AAHA, 'linux-kernel@vger.kernel.org',
linuxppc-dev, 'Paul Mackerras', Gridish Shlomi-RM96313,
Chu hanjin-r52514
In-Reply-To: <9FCDBA58F226D911B202000BDBAD467306E04FD4@zch01exm40.ap.freescale.net>
Nack, remove the mm allocation code and just use rheap.
- k
On Jun 28, 2006, at 9:23 AM, Li Yang-r58472 wrote:
>
> Signed-off-by: Shlomi Gridish <gridish@freescale.com>
> Signed-off-by: Li Yang <leoli@freescale.com>
> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
>
> ---
> arch/powerpc/Kconfig | 12
> arch/powerpc/sysdev/Makefile | 1
> arch/powerpc/sysdev/ipic.c | 2
> arch/powerpc/sysdev/qe_lib/Kconfig | 315 +++++++++++++
> arch/powerpc/sysdev/qe_lib/Makefile | 8
> arch/powerpc/sysdev/qe_lib/mm.c | 770 +++++++++++++++++++++
> +++++++++++
> arch/powerpc/sysdev/qe_lib/mm.h | 6
> arch/powerpc/sysdev/qe_lib/qe.c | 181 ++++++++
> arch/powerpc/sysdev/qe_lib/qe_common.c | 401 +++++++++++++++++
> arch/powerpc/sysdev/qe_lib/qe_ic.c | 487 ++++++++++++++++++++
> arch/powerpc/sysdev/qe_lib/qe_ic.h | 83 +++
> arch/powerpc/sysdev/qe_lib/qe_io.c | 275 +++++++++++
> 12 files changed, 2541 insertions(+), 0 deletions(-)
>
> diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
> index 6729c98..6d4fc0b 100644
> --- a/arch/powerpc/Kconfig
> +++ b/arch/powerpc/Kconfig
> @@ -334,6 +334,16 @@ config APUS
> <http://linux-apus.sourceforge.net/>.
> endchoice
>
> +config QUICC_ENGINE
> + bool
> + depends on MPC836x
> + default y
> + help
> + The QE(QUICC Engine) is a new generation of coprocessor on
> + Freescale embedded CPUs(like CPM in older chips). Selecting
> + this option means that you wish to build a kernel for a machine
> + with QE coprocessor on it.
> +
> config PPC_PSERIES
> depends on PPC_MULTIPLATFORM && PPC64
> bool " IBM pSeries & new (POWER5-based) iSeries"
> @@ -993,6 +1003,8 @@ # XXX source "arch/ppc/8xx_io/Kconfig"
>
> # XXX source "arch/ppc/8260_io/Kconfig"
>
> +source "arch/powerpc/sysdev/qe_lib/Kconfig"
> +
> source "arch/powerpc/platforms/iseries/Kconfig"
>
> source "lib/Kconfig"
> diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/
> Makefile
> index 4c2b356..cd1d5cc 100644
> --- a/arch/powerpc/sysdev/Makefile
> +++ b/arch/powerpc/sysdev/Makefile
> @@ -8,3 +8,4 @@ obj-$(CONFIG_U3_DART) += dart_iommu.o
> obj-$(CONFIG_MMIO_NVRAM) += mmio_nvram.o
> obj-$(CONFIG_PPC_83xx) += ipic.o
> obj-$(CONFIG_FSL_SOC) += fsl_soc.o
> +obj-$(CONFIG_QUICC_ENGINE) += qe_lib/
> diff --git a/arch/powerpc/sysdev/ipic.c b/arch/powerpc/sysdev/ipic.c
> index 8f01e0f..dbeccba 100644
> --- a/arch/powerpc/sysdev/ipic.c
> +++ b/arch/powerpc/sysdev/ipic.c
> @@ -537,12 +537,14 @@ void ipic_set_highest_priority(unsigned
>
> void ipic_set_default_priority(void)
> {
> +#ifdef CONFIG_MPC834x
> ipic_set_priority(MPC83xx_IRQ_TSEC1_TX, 0);
> ipic_set_priority(MPC83xx_IRQ_TSEC1_RX, 1);
> ipic_set_priority(MPC83xx_IRQ_TSEC1_ERROR, 2);
> ipic_set_priority(MPC83xx_IRQ_TSEC2_TX, 3);
> ipic_set_priority(MPC83xx_IRQ_TSEC2_RX, 4);
> ipic_set_priority(MPC83xx_IRQ_TSEC2_ERROR, 5);
> +#endif
> ipic_set_priority(MPC83xx_IRQ_USB2_DR, 6);
> ipic_set_priority(MPC83xx_IRQ_USB2_MPH, 7);
>
> diff --git a/arch/powerpc/sysdev/qe_lib/Kconfig b/arch/powerpc/
> sysdev/qe_lib/Kconfig
> new file mode 100644
> index 0000000..6105237
> --- /dev/null
> +++ b/arch/powerpc/sysdev/qe_lib/Kconfig
> @@ -0,0 +1,315 @@
> +#
> +# QE Communication options
> +#
> +
> +menu "QE Options"
> + depends on QUICC_ENGINE
> +
> +config UCC1
> + bool "Enable QE UCC1"
> +
> +choice
> + prompt "UCC1 speed selection"
> + depends on UCC1
> + default UCC1_SLOW
> +
> + config UCC1_SLOW
> + bool "UCC1 is slow"
> + config UCC1_FAST
> + bool "UCC1 is fast"
> +endchoice
> +
> +menu "UCC1 Protocols options"
> + depends on UCC1
> +
> + choice
> + prompt "UCC1 Slow Protocols selection"
> + depends on UCC1_SLOW
> + default UCC1_UART
> +
> + config UCC1_UART
> + bool "UCC1 is UART"
> + endchoice
> +
> + choice
> + prompt "UCC1 Fast Protocols selection"
> + depends on UCC1_FAST
> + default UCC1_GETH
> +
> + config UCC1_GETH
> + bool "UCC1 is GETH"
> + endchoice
> +endmenu
> +
> +config UCC2
> + bool "Enable QE UCC2"
> +
> +choice
> + prompt "UCC2 speed selection"
> + depends on UCC2
> + default UCC2_SLOW
> +
> + config UCC2_SLOW
> + bool "UCC2 is slow"
> + config UCC2_FAST
> + bool "UCC2 is fast"
> +endchoice
> +
> +menu "UCC2 Protocols options"
> + depends on UCC2
> +
> + choice
> + prompt "UCC2 Slow Protocols selection"
> + depends on UCC2_SLOW
> + default UCC2_UART
> +
> + config UCC2_UART
> + bool "UCC2 is UART"
> + endchoice
> +
> + choice
> + prompt "UCC2 Fast Protocols selection"
> + depends on UCC2_FAST
> + default UCC2_GETH
> +
> + config UCC2_GETH
> + bool "UCC2 is GETH"
> + endchoice
> +endmenu
> +
> +config UCC3
> + bool "Enable QE UCC3"
> +
> +choice
> + prompt "UCC3 speed selection"
> + depends on UCC3
> + default UCC3_SLOW
> +
> + config UCC3_SLOW
> + bool "UCC3 is slow"
> + config UCC3_FAST
> + bool "UCC3 is fast"
> +endchoice
> +
> +menu "UCC3 Protocols options"
> + depends on UCC3
> +
> + choice
> + prompt "UCC3 Slow Protocols selection"
> + depends on UCC3_SLOW
> + default UCC3_UART
> +
> + config UCC3_UART
> + bool "UCC3 is UART"
> + endchoice
> +
> + config UCC3_GETH
> + depends on UCC3_FAST
> + bool "UCC3 is GETH"
> +
> + config UCC3_ATM
> + depends on UCC3_FAST && !UCC3_GETH
> + tristate "UCC3 is ATM"
> +endmenu
> +
> +config UCC4
> + bool "Enable QE UCC4"
> +
> +choice
> + prompt "UCC4 speed selection"
> + depends on UCC4
> + default UCC4_SLOW
> +
> + config UCC4_SLOW
> + bool "UCC4 is slow"
> + config UCC4_FAST
> + bool "UCC4 is fast"
> +endchoice
> +
> +menu "UCC4 Protocols options"
> + depends on UCC4
> +
> + choice
> + prompt "UCC4 Slow Protocols selection"
> + depends on UCC4_SLOW
> + default UCC4_UART
> +
> + config UCC4_UART
> + bool "UCC4 is UART"
> + endchoice
> +
> + choice
> + prompt "UCC4 Fast Protocols selection"
> + depends on UCC4_FAST
> + default UCC4_GETH
> +
> + config UCC4_GETH
> + bool "UCC4 is GETH"
> + endchoice
> +endmenu
> +
> +config UCC5
> + bool "Enable QE UCC5"
> +
> +choice
> + prompt "UCC5 speed selection"
> + depends on UCC5
> + default UCC5_SLOW
> +
> + config UCC5_SLOW
> + bool "UCC5 is slow"
> + config UCC5_FAST
> + bool "UCC5 is fast"
> +endchoice
> +
> +menu "UCC5 Protocols options"
> + depends on UCC5
> +
> + choice
> + prompt "UCC5 Slow Protocols selection"
> + depends on UCC5_SLOW
> + default UCC5_UART
> +
> + config UCC5_UART
> + bool "UCC5 is UART"
> + endchoice
> +
> + choice
> + prompt "UCC5 Fast Protocols selection"
> + depends on UCC5_FAST
> + default UCC5_GETH
> +
> + config UCC5_GETH
> + bool "UCC5 is GETH"
> + endchoice
> +endmenu
> +
> +config UCC6
> + bool "Enable QE UCC6"
> +
> +choice
> + prompt "UCC6 speed selection"
> + depends on UCC6
> + default UCC6_SLOW
> +
> + config UCC6_SLOW
> + bool "UCC6 is slow"
> + config UCC6_FAST
> + bool "UCC6 is fast"
> +endchoice
> +
> +menu "UCC6 Protocols options"
> + depends on UCC6
> +
> + choice
> + prompt "UCC6 Slow Protocols selection"
> + depends on UCC6_SLOW
> + default UCC6_UART
> +
> + config UCC6_UART
> + bool "UCC6 is UART"
> + endchoice
> +
> + choice
> + prompt "UCC6 Fast Protocols selection"
> + depends on UCC6_FAST
> + default UCC6_GETH
> +
> + config UCC6_GETH
> + bool "UCC6 is GETH"
> + endchoice
> +endmenu
> +
> +config UCC7
> + bool "Enable QE UCC7"
> +
> +choice
> + prompt "UCC7 speed selection"
> + depends on UCC7
> + default UCC7_SLOW
> +
> + config UCC7_SLOW
> + bool "UCC7 is slow"
> + config UCC7_FAST
> + bool "UCC7 is fast"
> +endchoice
> +
> +menu "UCC7 Protocols options"
> + depends on UCC7
> +
> + choice
> + prompt "UCC7 Slow Protocols selection"
> + depends on UCC7_SLOW
> + default UCC7_UART
> +
> + config UCC7_UART
> + bool "UCC7 is UART"
> + endchoice
> +
> + choice
> + prompt "UCC7 Fast Protocols selection"
> + depends on UCC7_FAST
> + default UCC7_GETH
> +
> + config UCC7_GETH
> + bool "UCC7 is GETH"
> + endchoice
> +endmenu
> +
> +config UCC8
> + bool "Enable QE UCC8"
> +
> +choice
> + prompt "UCC8 speed selection"
> + depends on UCC8
> + default UCC8_SLOW
> +
> + config UCC8_SLOW
> + bool "UCC8 is slow"
> + config UCC8_FAST
> + bool "UCC8 is fast"
> +endchoice
> +
> +menu "UCC8 Protocols options"
> + depends on UCC8
> +
> + choice
> + prompt "UCC8 Slow Protocols selection"
> + depends on UCC8_SLOW
> + default UCC8_UART
> +
> + config UCC8_UART
> + bool "UCC8 is UART"
> + endchoice
> +
> + choice
> + prompt "UCC8 Fast Protocols selection"
> + depends on UCC8_FAST
> + default UCC8_GETH
> +
> + config UCC8_GETH
> + bool "UCC8 is GETH"
> + endchoice
> +endmenu
> +
> +config UCC
> + depends on UCC1 || UCC2 || UCC3 || UCC4 || UCC5 || UCC6 || UCC7
> || UCC8
> + default y
> + bool
> +
> +config UCC_SLOW
> + depends on UCC1_SLOW || UCC2_SLOW || UCC3_SLOW || UCC4_SLOW ||
> UCC5_SLOW || UCC6_SLOW || UCC7_SLOW || UCC8_SLOW
> + default y
> + bool
> +
> +config UCC_FAST
> + depends on UCC1_FAST || UCC2_FAST || UCC3_FAST || UCC4_FAST ||
> UCC5_FAST || UCC6_FAST || UCC7_FAST || UCC8_FAST
> + default y
> + bool
> +
> +config UCC_GETH_CONF
> + depends on UCC1_GETH || UCC2_GETH || UCC3_GETH || UCC4_GETH ||
> UCC5_GETH || UCC6_GETH || UCC7_GETH || UCC8_GETH
> + default y
> + bool
> +endmenu
> +
> diff --git a/arch/powerpc/sysdev/qe_lib/Makefile b/arch/powerpc/
> sysdev/qe_lib/Makefile
> new file mode 100644
> index 0000000..c04a70c
> --- /dev/null
> +++ b/arch/powerpc/sysdev/qe_lib/Makefile
> @@ -0,0 +1,8 @@
> +#
> +# Makefile for the linux ppc-specific parts of QE
> +#
> +obj-$(CONFIG_QUICC_ENGINE)+= qe_common.o mm.o qe.o qe_ic.o qe_io.o
> +
> +obj-$(CONFIG_UCC) += ucc.o
> +obj-$(CONFIG_UCC_SLOW) += ucc_slow.o
> +obj-$(CONFIG_UCC_FAST) += ucc_fast.o ucc_slow.o
> diff --git a/arch/powerpc/sysdev/qe_lib/mm.c b/arch/powerpc/sysdev/
> qe_lib/mm.c
> new file mode 100644
> index 0000000..58984ba
> --- /dev/null
> +++ b/arch/powerpc/sysdev/qe_lib/mm.c
> @@ -0,0 +1,770 @@
> +/*
> + * Copyright (C) Freescale Semicondutor, Inc. 2006. All rights
> reserved.
> + *
> + * Author: Shlomi Gridish <gridish@freescale.com>
> + *
> + * Description:
> + * QE Memory Manager.
> + *
> + * Changelog:
> + * Jun 28, 2006 Li Yang <LeoLi@freescale.com>
> + * - Reorganized as qe_lib
> + * - Merged to powerpc arch; add device tree support
> + * - Style fixes
> + *
> + * This program is free software; you can redistribute it and/or
> modify it
> + * under the terms of the GNU General Public License as
> published by the
> + * Free Software Foundation; either version 2 of the License, or
> (at your
> + * option) any later version.
> + */
> +#include <linux/errno.h>
> +#include <linux/sched.h>
> +#include <linux/kernel.h>
> +#include <linux/param.h>
> +#include <linux/string.h>
> +#include <linux/mm.h>
> +#include <linux/interrupt.h>
> +#include <linux/bootmem.h>
> +#include <linux/module.h>
> +#include <asm/irq.h>
> +#include <asm/page.h>
> +#include <asm/pgtable.h>
> +
> +#include "mm.h"
> +
> +#define MAX_ALIGNMENT 20
> +#define MAX_NAME_LEN 50
> +
> +#define MAKE_ALIGNED(adr, align) ( ((u32)adr + (align - 1)) & (~
> (align - 1)) )
> +
> +/* mem_block_t data stucutre defines parameters of the Memory
> Block */
> +typedef struct mem_block {
> + struct mem_block *next; /* Pointer to the next memory block */
> +
> + u32 base; /* base address of the memory block */
> + u32 end; /* end address of the memory block */
> +} mem_block_t;
> +
> +/* free_block_t data stucutre defines parameters of the Free Block */
> +typedef struct free_block {
> + struct free_block *next; /* Pointer to the next free block */
> +
> + u32 base; /* base address of the block */
> + u32 end; /* end address of the block */
> +} free_block_t;
> +
> +/* busy_block_t data stucutre defines parameters of the Busy
> Block */
> +typedef struct busy_block {
> + struct busy_block *next; /* Pointer to the next free block */
> +
> + u32 base; /* base address of the block */
> + u32 end; /* end address of the block */
> + char name[MAX_NAME_LEN];
> +} busy_block_t;
> +
> +/* mm_t data structure defines parameters of the MM object */
> +typedef struct mm {
> + mem_block_t *mem_blocks; /* List of memory blocks (Memory
> list) */
> + busy_block_t *busy_blocks; /* List of busy blocks (Busy list) */
> + free_block_t *free_blocks[MAX_ALIGNMENT + 1];/* align lists of free
> + blocks (Free lists) */
> +} mm_t;
> +
> +/
> **********************************************************************
> + * MM internal routines
> set *
> +
> **********************************************************************
> /
> +
> +/****************************************************************
> + * Routine: mem_block_init
> + *
> + * Description:
> + * Initializes a new memory block of "size" bytes and started
> + * from "base" address.
> + *
> + * Arguments:
> + * mem_blk- handle to the mem_blk object
> + * base - base address of the memory block
> + * size - size of the memory block
> + *
> + * Return value:
> + * 0 is returned on success. E_NOMEMORY is returned
> + * if can't allocate memory for mem_blk object.
> + ****************************************************************/
> +static int mem_block_init(void **mem_blk, u32 base, u32 size)
> +{
> + mem_block_t *p_mem_blk;
> +
> + p_mem_blk = (mem_block_t *) kmalloc(sizeof(mem_block_t),
> GFP_KERNEL);
> + if (!p_mem_blk)
> + return -ENOMEM;
> +
> + p_mem_blk->base = base;
> + p_mem_blk->end = base + size;
> + p_mem_blk->next = 0;
> +
> + *mem_blk = p_mem_blk;
> +
> + return (0);
> +}
> +
> +/****************************************************************
> + * Routine: free_block_init
> + *
> + * Description:
> + * Initializes a new free block of of "size" bytes and
> + * started from "base" address.
> + *
> + * Arguments:
> + * FreeBlock - handle to the FreeBlock object
> + * base - base address of the free block
> + * size - size of the free block
> + *
> + * Return value:
> + * 0 is returned on success. E_NOMEMORY is returned
> + * if can't allocate memory for a free block.
> + ****************************************************************/
> +static int free_block_init(void **FreeBlock, u32 base, u32 size)
> +{
> + free_block_t *p_free_blk;
> +
> + p_free_blk = (free_block_t *) kmalloc(sizeof(free_block_t),
> GFP_KERNEL);
> + if (!p_free_blk)
> + return -ENOMEM;
> +
> + p_free_blk->base = base;
> + p_free_blk->end = base + size;
> + p_free_blk->next = 0;
> +
> + *FreeBlock = p_free_blk;
> +
> + return (0);
> +}
> +
> +/****************************************************************
> + * Routine: busy_block_init
> + *
> + * Description:
> + * Initializes a new busy block of "size" bytes and started
> + * rom "base" address. Each busy block has a name that
> + * specified the purpose of the memory allocation.
> + *
> + * Arguments:
> + * BusyBlock - handle to the BusyBlock object
> + * base - base address of the busy block
> + * size - size of the busy block
> + * name - name that specified the busy block
> + *
> + * Return value:
> + * 0 is returned on success. E_NOMEMORY is returned
> + * if can't allocate memory for busy block.
> + ****************************************************************/
> +static int busy_block_init(void **BusyBlock, u32 base, u32 size,
> char *name)
> +{
> + busy_block_t *p_busy_blk;
> + int n, NameLen;
> +
> + p_busy_blk = (busy_block_t *) kmalloc(sizeof(busy_block_t),
> GFP_KERNEL);
> + if (!p_busy_blk)
> + return -ENOMEM;
> +
> + p_busy_blk->base = base;
> + p_busy_blk->end = base + size;
> + NameLen = (int)strlen(name);
> + n = (NameLen > MAX_NAME_LEN - 1) ? MAX_NAME_LEN - 1 : NameLen;
> + strncpy(p_busy_blk->name, name, (u32) n);
> + p_busy_blk->name[n] = '\0';
> + p_busy_blk->next = 0;
> +
> + *BusyBlock = p_busy_blk;
> +
> + return (0);
> +}
> +
> +/****************************************************************
> + * Routine: add_free
> + *
> + * Description:
> + * Adds a new free block to the free lists. It updates each
> + * free list to include a new free block.
> + * Note, that all free block in each free list are ordered
> + * by their base address.
> + *
> + * Arguments:
> + * p_mm - pointer to the MM object
> + * base - base address of a given free block
> + * end - end address of a given free block
> + *
> + * Return value:
> + *
> + *
> + ****************************************************************/
> +static int add_free(mm_t * p_mm, u32 base, u32 end)
> +{
> + free_block_t *p_prev_blk, *p_curr_blk, *p_new_blk;
> + u32 align;
> + int i;
> + u32 align_base;
> +
> + /* Updates free lists to include a just released block */
> + for (i = 0; i <= MAX_ALIGNMENT; i++) {
> + p_prev_blk = p_new_blk = 0;
> + p_curr_blk = p_mm->free_blocks[i];
> +
> + align = (u32) (0x1 << i);
> + align_base = MAKE_ALIGNED(base, align);
> +
> + /* Goes to the next free list if there is no block to free */
> + if (align_base >= end)
> + continue;
> +
> + /* Looks for a free block that should be updated */
> + while (p_curr_blk) {
> + if (align_base <= p_curr_blk->end) {
> + if (end > p_curr_blk->end) {
> + free_block_t *p_NextB;
> + while (p_curr_blk->next
> + && end > p_curr_blk->next->end) {
> + p_NextB = p_curr_blk->next;
> + p_curr_blk->next =
> + p_curr_blk->next->next;
> + kfree(p_NextB);
> + }
> +
> + p_NextB = p_curr_blk->next;
> + if (!p_NextB
> + || (p_NextB
> + && end < p_NextB->base)) {
> + p_curr_blk->end = end;
> + } else {
> + p_curr_blk->end = p_NextB->end;
> + p_curr_blk->next =
> + p_NextB->next;
> + kfree(p_NextB);
> + }
> + } else if (end < p_curr_blk->base
> + && ((end - align_base) >= align)) {
> + if (free_block_init
> + ((void *)&p_new_blk, align_base,
> + end - align_base) != 0)
> + return -ENOMEM;
> + p_new_blk->next = p_curr_blk;
> + if (p_prev_blk)
> + p_prev_blk->next = p_new_blk;
> + else
> + p_mm->free_blocks[i] =
> + p_new_blk;
> + break;
> + }
> +
> + if (align_base < p_curr_blk->base
> + && end >= p_curr_blk->base)
> + p_curr_blk->base = align_base;
> +
> + /* if size of the free block is less then
> + * alignment deletes that free block from
> + * the free list. */
> + if ((p_curr_blk->end - p_curr_blk->base) <
> + align) {
> + if (p_prev_blk)
> + p_prev_blk->next =
> + p_curr_blk->next;
> + else
> + p_mm->free_blocks[i] =
> + p_curr_blk->next;
> + kfree(p_curr_blk);
> + }
> + break;
> + } else {
> + p_prev_blk = p_curr_blk;
> + p_curr_blk = p_curr_blk->next;
> + }
> + }
> +
> + /* If no free block found to be updated, insert a new free block
> + * to the end of the free list. */
> + if (!p_curr_blk && ((end - base) % align == 0)) {
> + if (free_block_init
> + ((void *)&p_new_blk, align_base, end - base) != 0)
> + return -ENOMEM;
> + if (p_prev_blk)
> + p_prev_blk->next = p_new_blk;
> + else
> + p_mm->free_blocks[i] = p_new_blk;
> + }
> +
> + /* Update boundaries of the new free block */
> + if (align == 1 && !p_new_blk) {
> + if (p_curr_blk && base > p_curr_blk->base)
> + base = p_curr_blk->base;
> + if (p_curr_blk && end < p_curr_blk->end)
> + end = p_curr_blk->end;
> + }
> + }
> +
> + return (0);
> +}
> +
> +/****************************************************************
> + * Routine: cut_free
> + *
> + * Description:
> + * Cuts a free block from hold_base to hold_end from the free
> lists.
> + * That is, it updates all free lists of the MM object do
> + * not include a block of memory from hold_base to hold_end.
> + * For each free lists it seek for a free block that holds
> + * either hold_base or hold_end. If such block is found it
> updates it.
> + *
> + * Arguments:
> + * p_mm - pointer to the MM object
> + * hold_base - base address of the allocated block
> + * hold_end - end address of the allocated block
> + *
> + * Return value:
> + * 0 is returned on success,
> + * otherwise returns an error code.
> + *
> + ****************************************************************/
> +static int cut_free(mm_t * p_mm, u32 hold_base, u32 hold_end)
> +{
> + free_block_t *p_prev_blk, *p_curr_blk, *p_new_blk;
> + u32 align_base, base, end, align;
> + int i;
> +
> + for (i = 0; i <= MAX_ALIGNMENT; i++) {
> + p_prev_blk = p_new_blk = 0;
> + p_curr_blk = p_mm->free_blocks[i];
> +
> + align = (u32) 0x1 << i;
> + align_base = MAKE_ALIGNED(hold_end, align);
> +
> + while (p_curr_blk) {
> + base = p_curr_blk->base;
> + end = p_curr_blk->end;
> +
> + if (hold_base <= base && hold_end <= end
> + && hold_end > base) {
> + if (align_base >= end
> + || (align_base < end
> + && (end - align_base) < align)) {
> + if (p_prev_blk)
> + p_prev_blk->next =
> + p_curr_blk->next;
> + else
> + p_mm->free_blocks[i] =
> + p_curr_blk->next;
> + kfree(p_curr_blk);
> + } else {
> + p_curr_blk->base = align_base;
> + }
> + break;
> + } else if (hold_base > base && hold_end <= end) {
> + if ((hold_base - base) >= align) {
> + if (align_base < end
> + && (end - align_base) >= align) {
> + if (free_block_init
> + ((void *)&p_new_blk,
> + align_base,
> + (end - align_base)) != 0)
> + return -ENOMEM;
> + p_new_blk->next =
> + p_curr_blk->next;
> + p_curr_blk->next = p_new_blk;
> + }
> + p_curr_blk->end = hold_base;
> + } else if (align_base < end
> + && (end - align_base) >= align) {
> + p_curr_blk->base = align_base;
> + } else {
> + if (p_prev_blk)
> + p_prev_blk->next =
> + p_curr_blk->next;
> + else
> + p_mm->free_blocks[i] =
> + p_curr_blk->next;
> + kfree(p_curr_blk);
> + }
> + break;
> + } else {
> + p_prev_blk = p_curr_blk;
> + p_curr_blk = p_curr_blk->next;
> + }
> + }
> + }
> +
> + return (0);
> +}
> +
> +/****************************************************************
> + * Routine: add_busy
> + *
> + * Description:
> + * Adds a new busy block to the list of busy blocks. Note,
> + * that all busy blocks are ordered by their base address in
> + * the busy list.
> + *
> + * Arguments:
> + * MM - handler to the MM object
> + * p_new_busy_blk - pointer to the a busy block
> + *
> + * Return value:
> + * None.
> + *
> + ****************************************************************/
> +static void add_busy(mm_t * p_mm, busy_block_t * p_new_busy_blk)
> +{
> + busy_block_t *p_cur_busy_blk, *p_prev_busy_blk;
> +
> + /* finds a place of a new busy block in the list of busy blocks */
> + p_prev_busy_blk = 0;
> + p_cur_busy_blk = p_mm->busy_blocks;
> +
> + while (p_cur_busy_blk && p_new_busy_blk->base > p_cur_busy_blk-
> >base) {
> + p_prev_busy_blk = p_cur_busy_blk;
> + p_cur_busy_blk = p_cur_busy_blk->next;
> + }
> +
> + /* insert the new busy block into the list of busy blocks */
> + if (p_cur_busy_blk)
> + p_new_busy_blk->next = p_cur_busy_blk;
> + if (p_prev_busy_blk)
> + p_prev_busy_blk->next = p_new_busy_blk;
> + else
> + p_mm->busy_blocks = p_new_busy_blk;
> +
> +}
> +
> +/****************************************************************
> + * Routine: get_greater_align
> + *
> + * Description:
> + * Allocates a block of memory according to the given size
> + * and the alignment. That routine is called from the mm_get
> + * routine if the required alignment is grater then
> MAX_ALIGNMENT.
> + * In that case, it goes over free blocks of 64 byte align list
> + * and checks if it has the required size of bytes of the
> required
> + * alignment. If no blocks found returns ILLEGAL_BASE.
> + * After the block is found and data is allocated, it calls
> + * the internal cut_free routine to update all free lists
> + * do not include a just allocated block. Of course, each
> + * free list contains a free blocks with the same alignment.
> + * It is also creates a busy block that holds
> + * information about an allocated block.
> + *
> + * Arguments:
> + * MM - handle to the MM object
> + * size - size of the MM
> + * align - index as a power of two defines
> + * a required alignment that is grater then
> 64.
> + * name - the name that specifies an allocated block.
> + *
> + * Return value:
> + * base address of an allocated block.
> + * ILLEGAL_BASE if can't allocate a block
> + *
> + ****************************************************************/
> +static int get_greater_align(void *MM, u32 size, int align, char
> *name)
> +{
> + mm_t *p_mm = (mm_t *) MM;
> + free_block_t *p_free_blk;
> + busy_block_t *p_new_busy_blk;
> + u32 hold_base, hold_end, align_base = 0;
> + u32 ret;
> +
> + /* goes over free blocks of the 64 byte alignment list
> + * and look for a block of the suitable size and
> + * base address according to the alignment.
> + */
> + p_free_blk = p_mm->free_blocks[MAX_ALIGNMENT];
> +
> + while (p_free_blk) {
> + align_base = MAKE_ALIGNED(p_free_blk->base, align);
> +
> + /* the block is found if the aligned base inside the block
> + * and has the anough size.
> + */
> + if (align_base >= p_free_blk->base &&
> + align_base < p_free_blk->end &&
> + size <= (p_free_blk->end - align_base))
> + break;
> + else
> + p_free_blk = p_free_blk->next;
> + }
> +
> + /* If such block isn't found */
> + if (!p_free_blk)
> + return -EBUSY;
> +
> + hold_base = align_base;
> + hold_end = align_base + size;
> +
> + /* init a new busy block */
> + if ((ret =
> + busy_block_init((void *)&p_new_busy_blk, hold_base, size,
> + name)) != 0)
> + return ret;
> +
> + /* calls Update routine to update a lists of free blocks */
> + if ((ret = cut_free(MM, hold_base, hold_end)) != 0)
> + return ret;
> +
> + /* insert the new busy block into the list of busy blocks */
> + add_busy(p_mm, p_new_busy_blk);
> +
> + return (hold_base);
> +}
> +
> +/
> **********************************************************************
> + * MM API routines
> set *
> +
> **********************************************************************
> /
> +int mm_init(void **MM, u32 base, u32 size)
> +{
> + mm_t *p_mm;
> + int i;
> + u32 new_base, new_size;
> +
> + /* Initializes a new MM object */
> + p_mm = (mm_t *) kmalloc(sizeof(mm_t), GFP_KERNEL);
> + if (p_mm == 0)
> + return -ENOMEM;
> +
> + /* initializes a new memory block */
> + if (mem_block_init((void *)&p_mm->mem_blocks, base, size) != 0)
> + return -ENOMEM;
> +
> + /* A busy list is empty */
> + p_mm->busy_blocks = 0;
> +
> + /*Initializes a new free block for each free list */
> + for (i = 0; i <= MAX_ALIGNMENT; i++) {
> + new_base = MAKE_ALIGNED(base, (0x1 << i));
> + new_size = size - (new_base - base);
> + if (free_block_init((void *)&p_mm->free_blocks[i],
> + new_base, new_size) != 0)
> + return -ENOMEM;
> + }
> +
> + *MM = p_mm;
> +
> + return (0);
> +}
> +
> +EXPORT_SYMBOL(mm_init);
> +
> +void mm_free(void *MM)
> +{
> + mm_t *p_mm = (mm_t *) MM;
> + mem_block_t *p_mem_blk;
> + busy_block_t *p_busy_blk;
> + free_block_t *p_free_blk;
> + void *p_blk;
> + int i;
> +
> + if (!p_mm)
> + return;
> +
> + /* release memory allocated for busy blocks */
> + p_busy_blk = p_mm->busy_blocks;
> + while (p_busy_blk) {
> + p_blk = p_busy_blk;
> + p_busy_blk = p_busy_blk->next;
> + kfree(p_blk);
> + }
> +
> + /* release memory allocated for free blocks */
> + for (i = 0; i <= MAX_ALIGNMENT; i++) {
> + p_free_blk = p_mm->free_blocks[i];
> + while (p_free_blk) {
> + p_blk = p_free_blk;
> + p_free_blk = p_free_blk->next;
> + kfree(p_blk);
> + }
> + }
> +
> + /* release memory allocated for memory blocks */
> + p_mem_blk = p_mm->mem_blocks;
> + while (p_mem_blk) {
> + p_blk = p_mem_blk;
> + p_mem_blk = p_mem_blk->next;
> + kfree(p_blk);
> + }
> +
> + /* release memory allocated for MM object itself */
> + kfree(p_mm);
> +}
> +
> +EXPORT_SYMBOL(mm_free);
> +
> +void *mm_get(void *MM, u32 size, int align, char *name)
> +{
> + mm_t *p_mm = (mm_t *) MM;
> + free_block_t *p_free_blk;
> + busy_block_t *p_new_busy_blk;
> + u32 hold_base, hold_end;
> + u32 i = 0, j = (u32) align;
> + u32 ret;
> +
> + if (!p_mm)
> + return ERR_PTR(-EINVAL);
> +
> + /* checks that align value is grater then zero */
> + if (align == 0)
> + return ERR_PTR(-EINVAL);
> +
> + /* checks if alignment is a power of two,
> + * if it correct and if the required size
> + * is multiple of the given alignment.
> + */
> + while ((j & 0x1) == 0) {
> + i++;
> + j = j >> 1;
> + }
> +
> + /* if the given alignment isn't power of two, returns an error */
> + if (j != 1)
> + return ERR_PTR(-EINVAL);
> +
> + if (i > MAX_ALIGNMENT)
> + return ERR_PTR(get_greater_align(MM, size, align, name));
> +
> + /* look for a block of the size grater or equal to the
> + * required size.
> + */
> + p_free_blk = p_mm->free_blocks[i];
> + while (p_free_blk && (p_free_blk->end - p_free_blk->base) < size)
> + p_free_blk = p_free_blk->next;
> +
> + /* If such block is found */
> + if (!p_free_blk)
> + return ERR_PTR(-ENOMEM);
> +
> + hold_base = p_free_blk->base;
> + hold_end = hold_base + size;
> +
> + /* init a new busy block */
> + if ((ret =
> + busy_block_init((void *)&p_new_busy_blk, hold_base, size,
> + name)) != 0)
> + return ERR_PTR(ret);
> +
> + /* calls Update routine to update a lists of free blocks */
> + if ((ret = cut_free(MM, hold_base, hold_end)) != 0)
> + return ERR_PTR(ret);
> +
> + /* insert the new busy block into the list of busy blocks */
> + add_busy(p_mm, p_new_busy_blk);
> +
> + return (void *)(hold_base);
> +}
> +
> +EXPORT_SYMBOL(mm_get);
> +
> +void *mm_get_force(void *MM, u32 base, u32 size, char *name)
> +{
> + mm_t *p_mm = (mm_t *) MM;
> + free_block_t *p_free_blk;
> + busy_block_t *p_new_busy_blk;
> + int blk_is_free = 0;
> + u32 ret;
> +
> + p_free_blk = p_mm->free_blocks[0];/* The biggest free blocks are in
> + the free list with alignment 1 */
> + while (p_free_blk) {
> + if (base >= p_free_blk->base
> + && (base + size) <= p_free_blk->end) {
> + blk_is_free = 1;
> + break;
> + } else
> + p_free_blk = p_free_blk->next;
> + }
> +
> + if (!blk_is_free)
> + return ERR_PTR(-ENOMEM);
> +
> + /* init a new busy block */
> + if ((ret =
> + busy_block_init((void *)&p_new_busy_blk, base, size, name)) !
> = 0)
> + return ERR_PTR(ret);
> +
> + /* calls Update routine to update a lists of free blocks */
> + if ((ret = cut_free(MM, base, base + size)) != 0)
> + return ERR_PTR(ret);
> +
> + /* insert the new busy block into the list of busy blocks */
> + add_busy(p_mm, p_new_busy_blk);
> + return (void *)(base);
> +}
> +
> +EXPORT_SYMBOL(mm_get_force);
> +
> +int mm_put(void *MM, u32 base)
> +{
> + mm_t *p_mm = (mm_t *) MM;
> + busy_block_t *p_busy_blk, *p_prev_busy_blk;
> + u32 size;
> + u32 ret;
> +
> + if (!p_mm)
> + return -EINVAL;
> +
> + /* Look for a busy block that have the given base value.
> + * That block will be returned back to the memory.
> + */
> + p_prev_busy_blk = 0;
> + p_busy_blk = p_mm->busy_blocks;
> + while (p_busy_blk && base != p_busy_blk->base) {
> + p_prev_busy_blk = p_busy_blk;
> + p_busy_blk = p_busy_blk->next;
> + }
> +
> + if (!p_busy_blk)
> + return -EINVAL;
> +
> + if ((ret = add_free(p_mm, p_busy_blk->base, p_busy_blk->end)) != 0)
> + return ret;
> +
> + /* removes a busy block form the list of busy blocks */
> + if (p_prev_busy_blk)
> + p_prev_busy_blk->next = p_busy_blk->next;
> + else
> + p_mm->busy_blocks = p_busy_blk->next;
> +
> + size = p_busy_blk->end - p_busy_blk->base;
> +
> + kfree(p_busy_blk);
> +
> + return (0);
> +}
> +
> +EXPORT_SYMBOL(mm_put);
> +
> +void mm_dump(void *MM)
> +{
> + mm_t *p_mm = (mm_t *) MM;
> + free_block_t *p_free_blk;
> + busy_block_t *p_busy_blk;
> + int i;
> +
> + p_busy_blk = p_mm->busy_blocks;
> + printk(KERN_INFO "List of busy blocks:\n");
> + while (p_busy_blk) {
> + printk(KERN_INFO "\t0x%08x: (%s: b=0x%08x, e=0x%08x)\n",
> + (u32) p_busy_blk, p_busy_blk->name, p_busy_blk->base,
> + p_busy_blk->end);
> + p_busy_blk = p_busy_blk->next;
> + }
> +
> + printk(KERN_INFO "Lists of free blocks according to alignment:\n");
> + for (i = 0; i <= MAX_ALIGNMENT; i++) {
> + printk(KERN_INFO "%d alignment:\n", (0x1 << i));
> + p_free_blk = p_mm->free_blocks[i];
> + while (p_free_blk) {
> + printk(KERN_INFO "\t0x%08x: (b=0x%08x, e=0x%08x)\n",
> + (u32) p_free_blk, p_free_blk->base,
> + p_free_blk->end);
> + p_free_blk = p_free_blk->next;
> + }
> + printk(KERN_INFO "\n");
> + }
> +}
> +
> +EXPORT_SYMBOL(mm_dump);
> diff --git a/arch/powerpc/sysdev/qe_lib/mm.h b/arch/powerpc/sysdev/
> qe_lib/mm.h
> new file mode 100644
> index 0000000..ab30080
> --- /dev/null
> +++ b/arch/powerpc/sysdev/qe_lib/mm.h
> @@ -0,0 +1,6 @@
> +int mm_init ( void **MM, u32 base, u32 size );
> +void mm_free (void * MM);
> +void *mm_get ( void * MM, u32 size, int align, char* name );
> +void *mm_get_force ( void * MM, u32 base, u32 size, char* name );
> +int mm_put ( void * MM, u32 base );
> +void mm_dump ( void * MM );
> diff --git a/arch/powerpc/sysdev/qe_lib/qe.c b/arch/powerpc/sysdev/
> qe_lib/qe.c
> new file mode 100644
> index 0000000..0fbb54c
> --- /dev/null
> +++ b/arch/powerpc/sysdev/qe_lib/qe.c
> @@ -0,0 +1,181 @@
> +/*
> + * Copyright (C) Freescale Semicondutor, Inc. 2006. All rights
> reserved.
> + *
> + * Author: Li Yang <LeoLi@freescale.com>
> + *
> + * Description:
> + * FSL QE SOC setup.
> + *
> + * Changelog:
> + * Jun 21, 2006 Initial version
> + *
> + * This program is free software; you can redistribute it and/or
> modify it
> + * under the terms of the GNU General Public License as
> published by the
> + * Free Software Foundation; either version 2 of the License, or
> (at your
> + * option) any later version.
> + */
> +
> +#include <linux/config.h>
> +#include <linux/stddef.h>
> +#include <linux/kernel.h>
> +#include <linux/init.h>
> +#include <linux/errno.h>
> +#include <linux/major.h>
> +#include <linux/delay.h>
> +#include <linux/irq.h>
> +#include <linux/module.h>
> +#include <linux/device.h>
> +#include <linux/platform_device.h>
> +#include <linux/fsl_devices.h>
> +
> +#include <asm/system.h>
> +#include <asm/atomic.h>
> +#include <asm/io.h>
> +#include <asm/irq.h>
> +#include <asm/prom.h>
> +#include <sysdev/fsl_soc.h>
> +#include <mm/mmu_decl.h>
> +
> +static phys_addr_t qebase = -1;
> +
> +phys_addr_t get_qe_base(void)
> +{
> + struct device_node *qe;
> +
> + if (qebase != -1)
> + return qebase;
> +
> + qe = of_find_node_by_type(NULL, "qe");
> + if (qe) {
> + unsigned int size;
> + void *prop = get_property(qe, "reg", &size);
> + qebase = of_translate_address(qe, prop);
> + of_node_put(qe);
> + };
> +
> + return qebase;
> +}
> +
> +EXPORT_SYMBOL(get_qe_base);
> +
> +static int __init ucc_geth_of_init(void)
> +{
> + struct device_node *np;
> + unsigned int i, ucc_num;
> + struct platform_device *ugeth_dev;
> + struct resource res;
> + int ret;
> +
> + for (np = NULL, i = 0;
> + (np = of_find_compatible_node(np, "network", "ucc_geth")) !=
> NULL;
> + i++) {
> + struct resource r[2];
> + struct device_node *phy, *mdio;
> + struct ucc_geth_platform_data ugeth_data;
> + unsigned int *id;
> + char *model;
> + void *mac_addr;
> + phandle *ph;
> +
> + memset(r, 0, sizeof(r));
> + memset(&ugeth_data, 0, sizeof(ugeth_data));
> +
> + ret = of_address_to_resource(np, 0, &r[0]);
> + if (ret)
> + goto err;
> +
> + ugeth_data.phy_reg_addr = r[0].start;
> + r[1].start = np->intrs[0].line;
> + r[1].end = np->intrs[0].line;
> + r[1].flags = IORESOURCE_IRQ;
> +
> + model = get_property(np, "model", NULL);
> + ucc_num = *((u32 *) get_property(np, "device-id", NULL));
> + if ((strstr(model, "UCC") == NULL) ||
> + (ucc_num < 1) || (ucc_num > 8)) {
> + ret = -ENODEV;
> + goto err;
> + }
> +
> + ugeth_dev =
> + platform_device_register_simple("ucc_geth", ucc_num - 1,
> + &r[0], np->n_intrs + 1);
> +
> + if (IS_ERR(ugeth_dev)) {
> + ret = PTR_ERR(ugeth_dev);
> + goto err;
> + }
> +
> + mac_addr = get_property(np, "mac-address", NULL);
> +
> + memcpy(ugeth_data.mac_addr, mac_addr, 6);
> +
> + ugeth_data.rx_clock = *((u32 *) get_property(np, "rx-clock",
> + NULL));
> + ugeth_data.tx_clock = *((u32 *) get_property(np, "tx-clock",
> + NULL));
> +
> + ph = (phandle *) get_property(np, "phy-handle", NULL);
> + phy = of_find_node_by_phandle(*ph);
> +
> + if (phy == NULL) {
> + ret = -ENODEV;
> + goto unreg;
> + }
> +
> + mdio = of_get_parent(phy);
> +
> + id = (u32 *) get_property(phy, "reg", NULL);
> + ret = of_address_to_resource(mdio, 0, &res);
> + if (ret) {
> + of_node_put(phy);
> + of_node_put(mdio);
> + goto unreg;
> + }
> +
> + ugeth_data.phy_id = *id;
> + ugeth_data.phy_interrupt = phy->intrs[0].line;
> + ugeth_data.phy_interface = *((u32 *) get_property(phy,
> + "interface", NULL));
> +
> + /* FIXME: Work around for early chip rev. */
> + /* There's a bug in initial chip rev(s) in the RGMII ac */
> + /* timing. */
> + /* The following compensates by writing to the reserved */
> + /* QE Port Output Hold Registers (CPOH1?). */
> + if ((ugeth_data.phy_interface == ENET_1000_RGMII) ||
> + (ugeth_data.phy_interface == ENET_100_RGMII) ||
> + (ugeth_data.phy_interface == ENET_10_RGMII)) {
> + u32 *tmp_reg = (u32 *) ioremap(get_immrbase()
> + + 0x14A8, 0x4);
> + u32 tmp_val = in_be32(tmp_reg);
> + if (ucc_num == 1)
> + out_be32(tmp_reg, tmp_val | 0x00003000);
> + else if (ucc_num == 2)
> + out_be32(tmp_reg, tmp_val | 0x0c000000);
> + iounmap(tmp_reg);
> + }
> +
> + if (phy->intrs[0].line != 0)
> + ugeth_data.board_flags |= FSL_UGETH_BRD_HAS_PHY_INTR;
> +
> + of_node_put(phy);
> + of_node_put(mdio);
> +
> + ret =
> + platform_device_add_data(ugeth_dev, &ugeth_data,
> + sizeof(struct
> + ucc_geth_platform_data));
> + if (ret)
> + goto unreg;
> + }
> +
> + return 0;
> +
> +unreg:
> + platform_device_unregister(ugeth_dev);
> +err:
> + return ret;
> +}
> +
> +arch_initcall(ucc_geth_of_init);
> diff --git a/arch/powerpc/sysdev/qe_lib/qe_common.c b/arch/powerpc/
> sysdev/qe_lib/qe_common.c
> new file mode 100644
> index 0000000..cd0aca9
> --- /dev/null
> +++ b/arch/powerpc/sysdev/qe_lib/qe_common.c
> @@ -0,0 +1,401 @@
> +/*
> + * Copyright (C) Freescale Semicondutor, Inc. 2006. All rights
> reserved.
> + *
> + * Author: Shlomi Gridish <gridish@freescale.com>
> + *
> + * Description:
> + * General Purpose functions for the global management of the
> + * QUICC Engine (QE).
> + *
> + * Changelog:
> + * Jun 28, 2006 Li Yang <LeoLi@freescale.com>
> + * - Reorganized as qe_lib
> + * - Merged to powerpc arch; add device tree support
> + * - Style fixes
> + *
> + * This program is free software; you can redistribute it and/or
> modify it
> + * under the terms of the GNU General Public License as
> published by the
> + * Free Software Foundation; either version 2 of the License, or
> (at your
> + * option) any later version.
> + */
> +#undef USE_RHEAP
> +#include <linux/errno.h>
> +#include <linux/sched.h>
> +#include <linux/kernel.h>
> +#include <linux/param.h>
> +#include <linux/string.h>
> +#include <linux/mm.h>
> +#include <linux/interrupt.h>
> +#include <linux/bootmem.h>
> +#include <linux/module.h>
> +#include <linux/delay.h>
> +#include <asm/irq.h>
> +#include <asm/page.h>
> +#include <asm/pgtable.h>
> +#include <asm/immap_qe.h>
> +#include <asm/qe.h>
> +#include <asm/prom.h>
> +#ifdef USE_RHEAP
> +#include <asm/rheap.h>
> +#else
> +#include "mm.h"
> +#endif /* USE_RHEAP */
> +
> +/* QE snum state
> +*/
> +typedef enum qe_snum_state {
> + QE_SNUM_STATE_USED, /* used */
> + QE_SNUM_STATE_FREE /* free */
> +} qe_snum_state_e;
> +
> +/* QE snum
> +*/
> +typedef struct qe_snum {
> + u8 num; /* snum */
> + qe_snum_state_e state; /* state */
> +} qe_snum_t;
> +
> +/* We allocate this here because it is used almost exclusively for
> + * the communication processor devices.
> + */
> +EXPORT_SYMBOL(qe_immr);
> +qe_map_t *qe_immr = NULL;
> +static qe_snum_t snums[QE_NUM_OF_SNUM]; /* Dynamically allocated
> SNUMs */
> +
> +static void qe_snums_init(void);
> +static void qe_muram_init(void);
> +static int qe_sdma_init(void);
> +
> +void qe_reset(void)
> +{
> + if (qe_immr == NULL)
> + qe_immr = (qe_map_t *) ioremap(get_qe_base(), QE_IMMAP_SIZE);
> +
> + qe_snums_init();
> +
> + qe_issue_cmd(QE_RESET, QE_CR_SUBBLOCK_INVALID,
> + (u8) QE_CR_PROTOCOL_UNSPECIFIED, 0);
> +
> + /* Reclaim the MURAM memory for our use. */
> + qe_muram_init();
> +
> +#ifdef USE_RHEAP
> + if (qe_sdma_init())
> + panic("sdma init failed!");
> +#endif /* USE_RHEAP */
> +}
> +
> +EXPORT_SYMBOL(qe_issue_cmd);
> +int qe_issue_cmd(uint cmd, uint device, u8 mcn_protocol, u32
> cmd_input)
> +{
> + unsigned long flags;
> + u32 cecr;
> + u8 mcn_shift = 0, dev_shift = 0;
> +
> + local_irq_save(flags);
> + if (cmd == QE_RESET) {
> + out_be32(&qe_immr->cp.cecr, (u32) (cmd | QE_CR_FLG));
> + } else {
> + if (cmd == QE_ASSIGN_PAGE) {
> + /* Here device is the SNUM, not sub-block */
> + dev_shift = QE_CR_SNUM_SHIFT;
> + } else if (cmd == QE_ASSIGN_RISC) {
> + /* Here device is the SNUM, and mcnProtocol is
> + * e_QeCmdRiscAssignment value */
> + dev_shift = QE_CR_SNUM_SHIFT;
> + mcn_shift = QE_CR_MCN_RISC_ASSIGN_SHIFT;
> + } else {
> + if (device == QE_CR_SUBBLOCK_USB)
> + mcn_shift = QE_CR_MCN_USB_SHIFT;
> + else
> + mcn_shift = QE_CR_MCN_NORMAL_SHIFT;
> + }
> +
> + out_be32(&qe_immr->cp.cecdr,
> + immrbar_virt_to_phys((void *)cmd_input));
> + out_be32(&qe_immr->cp.cecr,
> + (cmd | QE_CR_FLG | ((u32) device << dev_shift) | (u32)
> + mcn_protocol << mcn_shift));
> + }
> +
> + /* wait for the QE_CR_FLG to clear */
> + do {
> + cecr = in_be32(&qe_immr->cp.cecr);
> + } while (cecr & QE_CR_FLG);
> + local_irq_restore(flags);
> +
> + return 0;
> +}
> +
> +/* Set a baud rate generator. This needs lots of work. There are
> + * 16 BRGs, which can be connected to the QE channels or output
> + * as clocks. The BRGs are in two different block of internal
> + * memory mapped space.
> + * The baud rate clock is the system clock divided by something.
> + * It was set up long ago during the initial boot phase and is
> + * is given to us.
> + * Baud rate clocks are zero-based in the driver code (as that maps
> + * to port numbers). Documentation uses 1-based numbering.
> + */
> +static unsigned int brg_clk = 0;
> +
> +unsigned int get_brg_clk(void)
> +{
> + struct device_node *qe;
> + if (brg_clk)
> + return brg_clk;
> +
> + qe = of_find_node_by_type(NULL, "qe");
> + if (qe) {
> + unsigned int size;
> + u32 *prop = (u32 *) get_property(qe, "brg-frequency", &size);
> + brg_clk = *prop;
> + of_node_put(qe);
> + };
> + return brg_clk;
> +}
> +
> +/* This function is used by UARTS, or anything else that uses a 16x
> + * oversampled clock.
> + */
> +void qe_setbrg(uint brg, uint rate)
> +{
> + volatile uint *bp;
> + u32 divisor;
> + int div16 = 0;
> +
> + bp = (uint *) & qe_immr->brg.brgc1;
> + bp += brg;
> +
> + divisor = (get_brg_clk() / rate);
> + if (divisor > QE_BRGC_DIVISOR_MAX + 1) {
> + div16 = 1;
> + divisor /= 16;
> + }
> +
> + *bp = ((divisor - 1) << QE_BRGC_DIVISOR_SHIFT) | QE_BRGC_ENABLE;
> + if (div16)
> + *bp |= QE_BRGC_DIV16;
> +}
> +
> +static void qe_snums_init(void)
> +{
> + int i;
> +
> + /* Initialize the SNUMs array. */
> + for (i = 0; i < QE_NUM_OF_SNUM; i++)
> + snums[i].state = QE_SNUM_STATE_FREE;
> +
> + /* Initialize SNUMs (thread serial numbers) according to QE
> + * spec chapter 4, SNUM table */
> + i = 0;
> + snums[i++].num = 0x04;
> + snums[i++].num = 0x05;
> + snums[i++].num = 0x0C;
> + snums[i++].num = 0x0D;
> + snums[i++].num = 0x14;
> + snums[i++].num = 0x15;
> + snums[i++].num = 0x1C;
> + snums[i++].num = 0x1D;
> + snums[i++].num = 0x24;
> + snums[i++].num = 0x25;
> + snums[i++].num = 0x2C;
> + snums[i++].num = 0x2D;
> + snums[i++].num = 0x34;
> + snums[i++].num = 0x35;
> + snums[i++].num = 0x88;
> + snums[i++].num = 0x89;
> + snums[i++].num = 0x98;
> + snums[i++].num = 0x99;
> + snums[i++].num = 0xA8;
> + snums[i++].num = 0xA9;
> + snums[i++].num = 0xB8;
> + snums[i++].num = 0xB9;
> + snums[i++].num = 0xC8;
> + snums[i++].num = 0xC9;
> + snums[i++].num = 0xD8;
> + snums[i++].num = 0xD9;
> + snums[i++].num = 0xE8;
> + snums[i++].num = 0xE9;
> +}
> +
> +int qe_get_snum(void)
> +{
> + unsigned long flags;
> + int snum = -EBUSY;
> + int i;
> +
> + local_irq_save(flags);
> + for (i = 0; i < QE_NUM_OF_SNUM; i++) {
> + if (snums[i].state == QE_SNUM_STATE_FREE) {
> + snums[i].state = QE_SNUM_STATE_USED;
> + snum = snums[i].num;
> + break;
> + }
> + }
> + local_irq_restore(flags);
> +
> + return snum;
> +}
> +
> +EXPORT_SYMBOL(qe_get_snum);
> +
> +void qe_put_snum(u8 snum)
> +{
> + int i;
> +
> + for (i = 0; i < QE_NUM_OF_SNUM; i++) {
> + if (snums[i].num == snum) {
> + snums[i].state = QE_SNUM_STATE_FREE;
> + break;
> + }
> + }
> +}
> +
> +EXPORT_SYMBOL(qe_put_snum);
> +
> +static int qe_sdma_init(void)
> +{
> + sdma_t *sdma = &qe_immr->sdma;
> + uint sdma_buf_offset;
> +
> + if (!sdma)
> + return -ENODEV;
> +
> + /* allocate 2 internal temporary buffers (512 bytes size each) for
> + * the SDMA */
> + sdma_buf_offset = qe_muram_alloc(512 * 2, 64);
> + if (IS_MURAM_ERR(sdma_buf_offset))
> + return -ENOMEM;
> +
> + out_be32(&sdma->sdebcr, sdma_buf_offset & QE_SDEBCR_BA_MASK);
> + out_be32(&sdma->sdmr, (QE_SDMR_GLB_1_MSK | (0x1 >>
> + QE_SDMR_CEN_SHIFT)));
> +
> + return 0;
> +}
> +
> +/*
> + * muram_alloc / muram_free bits.
> + */
> +static spinlock_t qe_muram_lock;
> +#ifdef USE_RHEAP
> +/* 16 blocks should be enough to satisfy all requests
> + * until the memory subsystem goes up... */
> +static rh_block_t qe_boot_muram_rh_block[16];
> +static rh_info_t qe_muram_info;
> +#else
> +static void *mm = NULL;
> +#endif /* USE_RHEAP */
> +
> +static void qe_muram_init(void)
> +{
> + spin_lock_init(&qe_muram_lock);
> +
> +#ifdef USE_RHEAP
> + /* initialize the info header */
> + rh_init(&qe_muram_info, 1,
> + sizeof(qe_boot_muram_rh_block) /
> + sizeof(qe_boot_muram_rh_block[0]), qe_boot_muram_rh_block);
> +
> + /* Attach the usable muram area */
> + /* XXX: This is actually crap. QE_DATAONLY_BASE and
> + * QE_DATAONLY_SIZE is only a subset of the available muram. It
> + * varies with the processor and the microcode patches activated.
> + * But the following should be at least safe.
> + */
> + rh_attach_region(&qe_muram_info,
> + (void *)QE_MURAM_DATAONLY_BASE,
> + QE_MURAM_DATAONLY_SIZE);
> +#else
> +#endif /* USE_RHEAP */
> +}
> +
> +/* This function returns an index into the MURAM area.
> + */
> +uint qe_muram_alloc(uint size, uint align)
> +{
> + void *start;
> + unsigned long flags;
> +
> + spin_lock_irqsave(&qe_muram_lock, flags);
> +#ifdef USE_RHEAP
> + qe_muram_info.alignment = align;
> + start = rh_alloc(&qe_muram_info, size, "QE");
> +#else
> + if (!mm) {
> + mm_init(&mm, (u32) qe_muram_addr(QE_MURAM_DATAONLY_BASE),
> + QE_MURAM_DATAONLY_SIZE);
> + if (qe_sdma_init())
> + panic("sdma init failed!");
> +
> + }
> + start = mm_get(mm, (u32) size, (int)align, "QE");
> + if (!IS_MURAM_ERR((u32) start))
> + start = (void *)((u32) start - (u32) qe_immr->muram);
> +#endif /* USE_RHEAP */
> + spin_unlock_irqrestore(&qe_muram_lock, flags);
> +
> + return (uint) start;
> +}
> +
> +EXPORT_SYMBOL(qe_muram_alloc);
> +
> +int qe_muram_free(uint offset)
> +{
> + int ret;
> + unsigned long flags;
> +
> + spin_lock_irqsave(&qe_muram_lock, flags);
> +#ifdef USE_RHEAP
> + ret = rh_free(&qe_muram_info, (void *)offset);
> +#else
> + ret = mm_put(mm, (u32) qe_muram_addr(offset));
> +#endif /* USE_RHEAP */
> + spin_unlock_irqrestore(&qe_muram_lock, flags);
> +
> + return ret;
> +}
> +
> +EXPORT_SYMBOL(qe_muram_free);
> +
> +/* not sure if this is ever needed */
> +uint qe_muram_alloc_fixed(uint offset, uint size, uint align)
> +{
> + void *start;
> + unsigned long flags;
> +
> + spin_lock_irqsave(&qe_muram_lock, flags);
> +#ifdef USE_RHEAP
> + qe_muram_info.alignment = align;
> + start =
> + rh_alloc_fixed(&qe_muram_info, (void *)offset, size,
> "commproc");
> +#else
> + start = mm_get_force(mm, (u32) offset, (u32) size, "QE");
> + if (!IS_MURAM_ERR((u32) start))
> + start = (void *)((u32) start - (u32) qe_immr->muram);
> +#endif /* USE_RHEAP */
> + spin_unlock_irqrestore(&qe_muram_lock, flags);
> +
> + return (uint) start;
> +}
> +
> +EXPORT_SYMBOL(qe_muram_alloc_fixed);
> +
> +void qe_muram_dump(void)
> +{
> +#ifdef USE_RHEAP
> + rh_dump(&qe_muram_info);
> +#else
> + mm_dump(mm);
> +#endif /* USE_RHEAP */
> +}
> +
> +EXPORT_SYMBOL(qe_muram_dump);
> +
> +void *qe_muram_addr(uint offset)
> +{
> + return (void *)&qe_immr->muram[offset];
> +}
> +
> +EXPORT_SYMBOL(qe_muram_addr);
> diff --git a/arch/powerpc/sysdev/qe_lib/qe_ic.c b/arch/powerpc/
> sysdev/qe_lib/qe_ic.c
> new file mode 100644
> index 0000000..465630e
> --- /dev/null
> +++ b/arch/powerpc/sysdev/qe_lib/qe_ic.c
> @@ -0,0 +1,487 @@
> +/*
> + * Copyright (C) Freescale Semicondutor, Inc. 2006. All rights
> reserved.
> + *
> + * Author: Shlomi Gridish <gridish@freescale.com>
> + *
> + * Description:
> + * QE Interrupt Controller routines implementations.
> + *
> + * Changelog:
> + * Jun 28, 2006 Li Yang <LeoLi@freescale.com>
> + * - Reorganized as qe_lib
> + * - Merged to powerpc arch; add device tree support
> + * - Style fixes
> + *
> + * This program is free software; you can redistribute it and/or
> modify it
> + * under the terms of the GNU General Public License as
> published by the
> + * Free Software Foundation; either version 2 of the License, or
> (at your
> + * option) any later version.
> + */
> +#include <linux/kernel.h>
> +#include <linux/init.h>
> +#include <linux/errno.h>
> +#include <linux/reboot.h>
> +#include <linux/slab.h>
> +#include <linux/stddef.h>
> +#include <linux/sched.h>
> +#include <linux/signal.h>
> +#include <linux/sysdev.h>
> +#include <linux/interrupt.h>
> +
> +#include <asm/irq.h>
> +#include <asm/io.h>
> +#include <asm/qe_ic.h>
> +
> +#include "qe_ic.h"
> +
> +static struct qe_ic_private p_qe_ic;
> +static struct qe_ic_private *primary_qe_ic;
> +
> +static struct qe_ic_info qe_ic_info[] = {
> + [1] = {
> + .mask = 0x00008000,
> + .qimr = 1,
> + .pri_code = 0},
> + [2] = {
> + .mask = 0x00004000,
> + .qimr = 1,
> + .pri_code = 1},
> + [3] = {
> + .mask = 0x00002000,
> + .qimr = 1,
> + .pri_code = 2},
> + [10] = {
> + .mask = 0x00000040,
> + .qimr = 1,
> + .pri_code = 1},
> + [11] = {
> + .mask = 0x00000020,
> + .qimr = 1,
> + .pri_code = 2},
> + [12] = {
> + .mask = 0x00000010,
> + .qimr = 1,
> + .pri_code = 3},
> + [13] = {
> + .mask = 0x00000008,
> + .qimr = 1,
> + .pri_code = 4},
> + [14] = {
> + .mask = 0x00000004,
> + .qimr = 1,
> + .pri_code = 5},
> + [15] = {
> + .mask = 0x00000002,
> + .qimr = 1,
> + .pri_code = 6},
> + [20] = {
> + .mask = 0x10000000,
> + .qimr = 0,
> + .pri_code = 3},
> + [25] = {
> + .mask = 0x00800000,
> + .qimr = 0,
> + .pri_code = 0},
> + [26] = {
> + .mask = 0x00400000,
> + .qimr = 0,
> + .pri_code = 1},
> + [27] = {
> + .mask = 0x00200000,
> + .qimr = 0,
> + .pri_code = 2},
> + [28] = {
> + .mask = 0x00100000,
> + .qimr = 0,
> + .pri_code = 3},
> + [32] = {
> + .mask = 0x80000000,
> + .qimr = 1,
> + .pri_code = 0},
> + [33] = {
> + .mask = 0x40000000,
> + .qimr = 1,
> + .pri_code = 1},
> + [34] = {
> + .mask = 0x20000000,
> + .qimr = 1,
> + .pri_code = 2},
> + [35] = {
> + .mask = 0x10000000,
> + .qimr = 1,
> + .pri_code = 3},
> + [36] = {
> + .mask = 0x08000000,
> + .qimr = 1,
> + .pri_code = 4},
> + [40] = {
> + .mask = 0x00800000,
> + .qimr = 1,
> + .pri_code = 0},
> + [41] = {
> + .mask = 0x00400000,
> + .qimr = 1,
> + .pri_code = 1},
> + [42] = {
> + .mask = 0x00200000,
> + .qimr = 1,
> + .pri_code = 2},
> + [43] = {
> + .mask = 0x00100000,
> + .qimr = 1,
> + .pri_code = 3},
> +};
> +
> +struct hw_interrupt_type qe_ic = {
> + .typename = "QE IC",
> + .enable = qe_ic_enable_irq,
> + .disable = qe_ic_disable_irq,
> + .ack = qe_ic_disable_irq_and_ack,
> + .end = qe_ic_end_irq,
> +};
> +
> +static int qe_ic_get_low_irq(struct pt_regs *regs)
> +{
> + struct qe_ic_private *p_qe_ic = primary_qe_ic;
> + int irq = -1;
> +
> + /* get the low byte of SIVEC to get the interrupt source vector. */
> + irq = (in_be32(&p_qe_ic->regs->qivec) >> 24) >> 2;
> +
> + if (irq == 0) /* 0 --> no irq is pending */
> + return -1;
> +
> + return irq + p_qe_ic->irq_offset;
> +}
> +
> +static int qe_ic_get_high_irq(struct pt_regs *regs)
> +{
> + struct qe_ic_private *p_qe_ic = primary_qe_ic;
> + int irq = -1;
> +
> + /* get the high byte of SIVEC to get the interrupt source vector. */
> + irq = (in_be32(&p_qe_ic->regs->qhivec) >> 24) >> 2;
> +
> + if (irq == 0) /* 0 --> no irq is pending */
> + return -1;
> +
> + return irq + p_qe_ic->irq_offset;
> +}
> +
> +static irqreturn_t qe_ic_cascade_low(int irq, void *dev_id,
> + struct pt_regs *regs)
> +{
> + while ((irq = qe_ic_get_low_irq(regs)) >= 0)
> + __do_IRQ(irq, regs);
> + return IRQ_HANDLED;
> +}
> +
> +static irqreturn_t qe_ic_cascade_high(int irq, void *dev_id,
> + struct pt_regs *regs)
> +{
> + while ((irq = qe_ic_get_high_irq(regs)) >= 0)
> + __do_IRQ(irq, regs);
> + return IRQ_HANDLED;
> +}
> +
> +static struct irqaction qe_ic_low_irqaction = {
> + .handler = qe_ic_cascade_low,
> + .flags = SA_INTERRUPT,
> + .mask = CPU_MASK_NONE,
> + .name = "qe_ic_cascade_low",
> +};
> +
> +static struct irqaction qe_ic_high_irqaction = {
> + .handler = qe_ic_cascade_high,
> + .flags = SA_INTERRUPT,
> + .mask = CPU_MASK_NONE,
> + .name = "qe_ic_cascade_high",
> +};
> +
> +int qe_ic_init(phys_addr_t phys_addr,
> + unsigned int flags, unsigned int irq_offset)
> +{
> + struct qe_ic_map *regs;
> + u8 grp, pri, shift = 0;
> + u32 tmp_qicr = 0, tmp_qricr = 0, tmp_qicnr = 0, tmp_mask;
> + int i, high_hctive = 0;
> + const u32 high_signal = 2;
> +
> + primary_qe_ic = &p_qe_ic;
> + memset(primary_qe_ic, 0, sizeof(struct qe_ic_private));
> +
> + /* initialize QE interrupt controller registers */
> + primary_qe_ic->regs = regs =
> + (struct qe_ic_map *)ioremap(phys_addr, QE_IC_SIZE);
> + primary_qe_ic->irq_offset = irq_offset;
> +
> + /* default priority scheme is grouped. If spread mode is */
> + /* required, configure sicr accordingly. */
> + if (flags & QE_IC_SPREADMODE_GRP_W)
> + tmp_qicr |= QICR_GWCC;
> + if (flags & QE_IC_SPREADMODE_GRP_X)
> + tmp_qicr |= QICR_GXCC;
> + if (flags & QE_IC_SPREADMODE_GRP_Y)
> + tmp_qicr |= QICR_GYCC;
> + if (flags & QE_IC_SPREADMODE_GRP_Z)
> + tmp_qicr |= QICR_GZCC;
> + if (flags & QE_IC_SPREADMODE_GRP_RISCA)
> + tmp_qicr |= QICR_GRTA;
> + if (flags & QE_IC_SPREADMODE_GRP_RISCB)
> + tmp_qicr |= QICR_GRTB;
> +
> + /* choose destination signal for highest priority interrupt */
> + if (flags & QE_IC_HIGH_SIGNAL) {
> + tmp_qicr |= (high_signal << QICR_HPIT_SHIFT);
> + high_hctive = 1;
> + }
> +
> + out_be32(®s->qicr, tmp_qicr);
> +
> + tmp_mask = (1 << QE_IC_GRP_W_DEST_SIGNAL_SHIFT);
> + /* choose destination signal for highest priority interrupt in each
> + * group */
> + for (grp = 0; grp < NUM_OF_QE_IC_GROUPS; grp++) {
> + /* the first 2 priorities in each group have a choice of
> + * destination signal */
> + for (pri = 0; pri <= 1; pri++) {
> + if (flags & ((tmp_mask << (grp << 1)) << pri)) {
> + /* indicate whether QE High signal is
> + * required */
> + if (!high_hctive)
> + high_hctive = 1;
> +
> + /* The location of the bits relevant to
> + * priority 0 in the */
> + /* registers is always 2 bits left comparing
> + * to priority 1. */
> + if (pri == 0)
> + shift = 2;
> +
> + switch (grp) {
> + case (QE_IC_GRP_W):
> + shift += QICNR_WCC1T_SHIFT;
> + tmp_qicnr |= high_signal << shift;
> + break;
> + case (QE_IC_GRP_X):
> + shift += QICNR_XCC1T_SHIFT;
> + tmp_qicnr |= high_signal << shift;
> + break;
> + case (QE_IC_GRP_Y):
> + shift += QICNR_YCC1T_SHIFT;
> + tmp_qicnr |= high_signal << shift;
> + break;
> + case (QE_IC_GRP_Z):
> + shift += QICNR_ZCC1T_SHIFT;
> + tmp_qicnr |= high_signal << shift;
> + break;
> + case (QE_IC_GRP_RISCA):
> + shift += QRICR_RTA1T_SHIFT;
> + tmp_qricr |= high_signal << shift;
> + break;
> + case (QE_IC_GRP_RISCB):
> + shift += QRICR_RTB1T_SHIFT;
> + tmp_qricr |= high_signal << shift;
> + break;
> + default:
> + break;
> + }
> + }
> + }
> + }
> +
> + if (tmp_qicnr)
> + out_be32(®s->qicnr, tmp_qicnr);
> + if (tmp_qricr)
> + out_be32(®s->qricr, tmp_qricr);
> +
> + for (i = primary_qe_ic->irq_offset;
> + i < (NR_QE_IC_INTS + primary_qe_ic->irq_offset); i++) {
> + irq_desc[i].handler = &qe_ic;
> + irq_desc[i].status = IRQ_LEVEL;
> + }
> +
> + /* register QE_IC interrupt controller in the a higher hirarchy
> + * controller */
> + setup_irq(IRQ_QE_LOW, &qe_ic_low_irqaction);
> +
> + if (high_hctive)
> + /* register QE_IC high interrupt source in the higher
> + * hirarchy controller */
> + setup_irq(IRQ_QE_HIGH, &qe_ic_high_irqaction);
> +
> + printk("QE IC (%d IRQ sources) at %p\n", NR_QE_IC_INTS,
> + primary_qe_ic->regs);
> + return 0;
> +}
> +
> +void qe_ic_free(void)
> +{
> +}
> +
> +void qe_ic_enable_irq(unsigned int irq)
> +{
> + struct qe_ic_private *p_qe_ic = primary_qe_ic;
> + unsigned int src = irq - p_qe_ic->irq_offset;
> + u32 qimr;
> +
> + if (qe_ic_info[src].qimr) {
> + qimr = in_be32(&((struct qe_ic_private *)p_qe_ic)->regs->qimr);
> + out_be32(&((struct qe_ic_private *)p_qe_ic)->regs->qimr,
> + qimr | (qe_ic_info[src].mask));
> + } else {
> + qimr = in_be32(&((struct qe_ic_private *)p_qe_ic)->regs->qrimr);
> + out_be32(&((struct qe_ic_private *)p_qe_ic)->regs->qrimr,
> + qimr | (qe_ic_info[src].mask));
> + }
> +}
> +
> +void qe_ic_disable_irq(unsigned int irq)
> +{
> + struct qe_ic_private *p_qe_ic = primary_qe_ic;
> + unsigned int src = irq - p_qe_ic->irq_offset;
> + u32 qimr;
> +
> + if (qe_ic_info[src].qimr) {
> + qimr = in_be32(&((struct qe_ic_private *)p_qe_ic)->regs->qimr);
> + out_be32(&((struct qe_ic_private *)p_qe_ic)->regs->qimr,
> + qimr & ~(qe_ic_info[src].mask));
> + } else {
> + qimr = in_be32(&((struct qe_ic_private *)p_qe_ic)->regs->qrimr);
> + out_be32(&((struct qe_ic_private *)p_qe_ic)->regs->qrimr,
> + qimr & ~(qe_ic_info[src].mask));
> + }
> +}
> +
> +void qe_ic_disable_irq_and_ack(unsigned int irq)
> +{
> + qe_ic_disable_irq(irq);
> +}
> +
> +void qe_ic_end_irq(unsigned int irq)
> +{
> +
> + if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))
> + && irq_desc[irq].action)
> + qe_ic_enable_irq(irq);
> +}
> +
> +void qe_ic_modify_highest_priority(unsigned int irq)
> +{
> + struct qe_ic_private *p_qe_ic = primary_qe_ic;
> + unsigned int src = irq - p_qe_ic->irq_offset;
> + u32 tmp_qicr = 0;
> +
> + tmp_qicr = in_be32(&p_qe_ic->regs->qicr);
> + out_be32(&p_qe_ic->regs->qicr, (u32) (tmp_qicr | ((u8) src << 24)));
> +}
> +
> +void qe_ic_modify_priority(enum qe_ic_grp_id grp,
> + unsigned int pri0,
> + unsigned int pri1,
> + unsigned int pri2,
> + unsigned int pri3,
> + unsigned int pri4,
> + unsigned int pri5,
> + unsigned int pri6, unsigned int pri7)
> +{
> + struct qe_ic_private *p_qe_ic = primary_qe_ic;
> + volatile u32 *p_qip = 0;
> + u32 tmp_qip = 0;
> + u8 tmp_array[8] = { 0, 0, 0, 0, 0, 0, 0, 0 };
> + signed char code_array[8], i = 0, j = 0;
> +
> + code_array[0] = (signed char)(pri0 ? qe_ic_info[pri0].pri_code :
> -1);
> + code_array[1] = (signed char)(pri1 ? qe_ic_info[pri1].pri_code :
> -1);
> + code_array[2] = (signed char)(pri2 ? qe_ic_info[pri2].pri_code :
> -1);
> + code_array[3] = (signed char)(pri3 ? qe_ic_info[pri3].pri_code :
> -1);
> + code_array[4] = (signed char)(pri4 ? qe_ic_info[pri4].pri_code :
> -1);
> + code_array[5] = (signed char)(pri5 ? qe_ic_info[pri5].pri_code :
> -1);
> + code_array[6] = (signed char)(pri6 ? qe_ic_info[pri6].pri_code :
> -1);
> + code_array[7] = (signed char)(pri7 ? qe_ic_info[pri7].pri_code :
> -1);
> +
> + for (i = 0; i < 8; i++) {
> + if (code_array[i] == -1)
> + break;
> + tmp_array[code_array[i]] = 1;
> + }
> +
> + for (; i < 8; i++) {
> + while (tmp_array[j] && j < 8)
> + j++;
> + code_array[i] = j;
> + tmp_array[j] = 1;
> + }
> +
> + tmp_qip = (u32) (code_array[0] << QIPCC_SHIFT_PRI0 |
> + code_array[1] << QIPCC_SHIFT_PRI1 |
> + code_array[2] << QIPCC_SHIFT_PRI2 |
> + code_array[3] << QIPCC_SHIFT_PRI3 |
> + code_array[4] << QIPCC_SHIFT_PRI4 |
> + code_array[5] << QIPCC_SHIFT_PRI5 |
> + code_array[6] << QIPCC_SHIFT_PRI6 |
> + code_array[7] << QIPCC_SHIFT_PRI7);
> +
> + switch (grp) {
> + case (QE_IC_GRP_W):
> + p_qip = &(p_qe_ic->regs->qipwcc);
> + break;
> + case (QE_IC_GRP_X):
> + p_qip = &(p_qe_ic->regs->qipxcc);
> + break;
> + case (QE_IC_GRP_Y):
> + p_qip = &(p_qe_ic->regs->qipycc);
> + break;
> + case (QE_IC_GRP_Z):
> + p_qip = &(p_qe_ic->regs->qipzcc);
> + break;
> + case (QE_IC_GRP_RISCA):
> + p_qip = &(p_qe_ic->regs->qiprta);
> + break;
> + case (QE_IC_GRP_RISCB):
> + p_qip = &(p_qe_ic->regs->qiprtb);
> + break;
> + default:
> + break;
> + }
> +
> + out_be32(p_qip, tmp_qip);
> +}
> +
> +void qe_ic_dump_regs(void)
> +{
> + struct qe_ic_private *p_qe_ic = primary_qe_ic;
> +
> + printk(KERN_INFO "QE IC registars:\n");
> + printk(KERN_INFO "Base address: 0x%08x\n", (u32) p_qe_ic->regs);
> + printk(KERN_INFO "qicr : addr - 0x%08x, val - 0x%08x\n",
> + (u32) & p_qe_ic->regs->qicr, in_be32(&p_qe_ic->regs->qicr));
> + printk(KERN_INFO "qivec : addr - 0x%08x, val - 0x%08x\n",
> + (u32) & p_qe_ic->regs->qivec, in_be32(&p_qe_ic->regs-
> >qivec));
> + printk(KERN_INFO "qripnr: addr - 0x%08x, val - 0x%08x\n",
> + (u32) & p_qe_ic->regs->qripnr, in_be32(&p_qe_ic->regs-
> >qripnr));
> + printk(KERN_INFO "qipnr : addr - 0x%08x, val - 0x%08x\n",
> + (u32) & p_qe_ic->regs->qipnr, in_be32(&p_qe_ic->regs-
> >qipnr));
> + printk(KERN_INFO "qipxcc: addr - 0x%08x, val - 0x%08x\n",
> + (u32) & p_qe_ic->regs->qipxcc, in_be32(&p_qe_ic->regs-
> >qipxcc));
> + printk(KERN_INFO "qipycc: addr - 0x%08x, val - 0x%08x\n",
> + (u32) & p_qe_ic->regs->qipycc, in_be32(&p_qe_ic->regs-
> >qipycc));
> + printk(KERN_INFO "qipwcc: addr - 0x%08x, val - 0x%08x\n",
> + (u32) & p_qe_ic->regs->qipwcc, in_be32(&p_qe_ic->regs-
> >qipwcc));
> + printk(KERN_INFO "qipzcc: addr - 0x%08x, val - 0x%08x\n",
> + (u32) & p_qe_ic->regs->qipzcc, in_be32(&p_qe_ic->regs-
> >qipzcc));
> + printk(KERN_INFO "qimr : addr - 0x%08x, val - 0x%08x\n",
> + (u32) & p_qe_ic->regs->qimr, in_be32(&p_qe_ic->regs->qimr));
> + printk(KERN_INFO "qrimr : addr - 0x%08x, val - 0x%08x\n",
> + (u32) & p_qe_ic->regs->qrimr, in_be32(&p_qe_ic->regs-
> >qrimr));
> + printk(KERN_INFO "qicnr : addr - 0x%08x, val - 0x%08x\n",
> + (u32) & p_qe_ic->regs->qicnr, in_be32(&p_qe_ic->regs-
> >qicnr));
> + printk(KERN_INFO "qiprta: addr - 0x%08x, val - 0x%08x\n",
> + (u32) & p_qe_ic->regs->qiprta, in_be32(&p_qe_ic->regs-
> >qiprta));
> + printk(KERN_INFO "qiprtb: addr - 0x%08x, val - 0x%08x\n",
> + (u32) & p_qe_ic->regs->qiprtb, in_be32(&p_qe_ic->regs-
> >qiprtb));
> + printk(KERN_INFO "qricr : addr - 0x%08x, val - 0x%08x\n",
> + (u32) & p_qe_ic->regs->qricr, in_be32(&p_qe_ic->regs-
> >qricr));
> + printk(KERN_INFO "qhivec: addr - 0x%08x, val - 0x%08x\n",
> + (u32) & p_qe_ic->regs->qhivec, in_be32(&p_qe_ic->regs-
> >qhivec));
> +}
> diff --git a/arch/powerpc/sysdev/qe_lib/qe_ic.h b/arch/powerpc/
> sysdev/qe_lib/qe_ic.h
> new file mode 100644
> index 0000000..6662ad2
> --- /dev/null
> +++ b/arch/powerpc/sysdev/qe_lib/qe_ic.h
> @@ -0,0 +1,83 @@
> +/*
> + * Copyright (C) Freescale Semicondutor, Inc. 2006. All rights
> reserved.
> + *
> + * Author: Shlomi Gridish <gridish@freescale.com>
> + *
> + * Description:
> + * QE IC private definitions and structure.
> + *
> + * Changelog:
> + * Jun 21, 2006 Li Yang <LeoLi@freescale.com>
> + * - Style fix; port to powerpc arch
> + *
> + * This program is free software; you can redistribute it and/or
> modify it
> + * under the terms of the GNU General Public License as
> published by the
> + * Free Software Foundation; either version 2 of the License, or
> (at your
> + * option) any later version.
> + */
> +#ifndef __QE_IC_H__
> +#define __QE_IC_H__
> +
> +typedef struct qe_ic_map {
> + volatile u32 qicr;
> + volatile u32 qivec;
> + volatile u32 qripnr;
> + volatile u32 qipnr;
> + volatile u32 qipxcc;
> + volatile u32 qipycc;
> + volatile u32 qipwcc;
> + volatile u32 qipzcc;
> + volatile u32 qimr;
> + volatile u32 qrimr;
> + volatile u32 qicnr;
> + volatile u8 res0[0x4];
> + volatile u32 qiprta;
> + volatile u32 qiprtb;
> + volatile u8 res1[0x4];
> + volatile u32 qricr;
> + volatile u8 res2[0x20];
> + volatile u32 qhivec;
> + volatile u8 res3[0x1C];
> +} __attribute__ ((packed)) qe_ic_map_t;
> +
> +
> +#define QE_IC_SIZE sizeof(struct qe_ic_map)
> +
> +/* Interrupt priority registers */
> +#define QIPCC_SHIFT_PRI0 29
> +#define QIPCC_SHIFT_PRI1 26
> +#define QIPCC_SHIFT_PRI2 23
> +#define QIPCC_SHIFT_PRI3 20
> +#define QIPCC_SHIFT_PRI4 13
> +#define QIPCC_SHIFT_PRI5 10
> +#define QIPCC_SHIFT_PRI6 7
> +#define QIPCC_SHIFT_PRI7 4
> +
> +/* QICR priority modes */
> +#define QICR_GWCC 0x00040000
> +#define QICR_GXCC 0x00020000
> +#define QICR_GYCC 0x00010000
> +#define QICR_GZCC 0x00080000
> +#define QICR_GRTA 0x00200000
> +#define QICR_GRTB 0x00400000
> +#define QICR_HPIT_SHIFT 8
> +
> +/* QICNR */
> +#define QICNR_WCC1T_SHIFT 20
> +#define QICNR_ZCC1T_SHIFT 28
> +#define QICNR_YCC1T_SHIFT 12
> +#define QICNR_XCC1T_SHIFT 4
> +
> +/* QRICR */
> +#define QRICR_RTA1T_SHIFT 20
> +#define QRICR_RTB1T_SHIFT 28
> +
> +struct qe_ic_private {
> + struct qe_ic_map *regs;
> + unsigned int irq_offset;
> +} qe_ic_private_t;
> +
> +extern struct hw_interrupt_type qe_ic;
> +extern int qe_ic_get_irq(struct pt_regs *regs);
> +
> +#endif /* __QE_IC_H__ */
> diff --git a/arch/powerpc/sysdev/qe_lib/qe_io.c b/arch/powerpc/
> sysdev/qe_lib/qe_io.c
> new file mode 100644
> index 0000000..a943c27
> --- /dev/null
> +++ b/arch/powerpc/sysdev/qe_lib/qe_io.c
> @@ -0,0 +1,275 @@
> +/*
> + * Copyright (C) Freescale Semicondutor, Inc. 2006. All rights
> reserved.
> + *
> + * Author: Li Yang <LeoLi@freescale.com>
> + *
> + * Description:
> + * QE Parallel I/O ports configuration routines. Based on code from
> + * Shlomi Gridish <gridish@freescale.com>
> + *
> + * Changelog:
> + * Jun 21, 2006 Initial version
> + *
> + * This program is free software; you can redistribute it and/or
> modify it
> + * under the terms of the GNU General Public License as
> published by the
> + * Free Software Foundation; either version 2 of the License, or
> (at your
> + * option) any later version.
> + */
> +
> +#include <linux/config.h>
> +#include <linux/stddef.h>
> +#include <linux/kernel.h>
> +#include <linux/init.h>
> +#include <linux/errno.h>
> +#include <linux/module.h>
> +
> +#include <asm/io.h>
> +#include <asm/prom.h>
> +#include <sysdev/fsl_soc.h>
> +#undef DEBUG
> +
> +#define NUM_OF_PINS 32
> +#define NUM_OF_PAR_IOS 7
> +
> +typedef struct par_io {
> + struct {
> + u32 cpodr; /* Open drain register */
> + u32 cpdata; /* Data register */
> + u32 cpdir1; /* Direction register */
> + u32 cpdir2; /* Direction register */
> + u32 cppar1; /* Pin assignment register */
> + u32 cppar2; /* Pin assignment register */
> + } io_regs[NUM_OF_PAR_IOS];
> +} par_io_t;
> +
> +typedef struct qe_par_io {
> + u8 res[0xc];
> + u32 cepier; /* QE ports interrupt event register */
> + u32 cepimr; /* QE ports mask event register */
> + u32 cepicr; /* QE ports control event register */
> +} qe_par_io_t;
> +
> +static int qe_irq_ports[NUM_OF_PAR_IOS][NUM_OF_PINS] = {
> + /* 0-7 */ /* 8-15 */ /* 16 - 23 */ /* 24 - 31 */
> + {0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,1, 1,0,0,0,0,0,0,0,
> 0,0,0,0,0,1,1,0},
> + {0,0,0,1,0,1,0,0, 0,0,0,0,1,1,0,0, 0,0,0,0,0,0,0,0,
> 0,0,1,1,0,0,0,0},
> + {0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0,
> 0,0,0,1,1,1,0,0},
> + {0,0,0,0,0,0,0,0, 0,0,0,0,1,1,0,0, 1,1,0,0,0,0,0,0,
> 0,0,1,1,0,0,0,0},
> + {0,0,0,0,0,0,0,0, 0,0,0,0,1,1,0,0, 0,0,0,0,0,0,0,0,
> 1,1,1,1,0,0,0,1},
> + {0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0, 0,0,0,0,1,0,0,0,
> 0,0,0,0,0,0,0,0},
> + {0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,1}
> +};
> +
> +
> +static u8 get_irq_num(u8 port, u8 pin)
> +{
> + int i, j;
> + u8 num = 0;
> +
> + if (qe_irq_ports[port][pin] == 0)
> + return -1;
> + for (j = 0; j <= port; j++)
> + for (i = 0; i < pin; i++)
> + if (qe_irq_ports[j][i])
> + num++;
> + return num;
> +}
> +
> +static par_io_t *par_io = NULL;
> +static qe_par_io_t *qe_par_io = NULL;
> +
> +int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain,
> + int assignment, int has_irq)
> +{
> + u32 pinMask1bit, pinMask2bits, newMask2bits, tmp_val;
> +
> + if (!par_io) {
> + par_io = (par_io_t *) ioremap(get_immrbase() + 0x1400,
> + sizeof(par_io_t));
> + qe_par_io = (qe_par_io_t *) ioremap(get_immrbase() + 0xC00,
> + sizeof(qe_par_io_t));
> +
> + /* clear event bits in the event register of the QE ports */
> + out_be32(&qe_par_io->cepier, 0xFFFFFFFF);
> + }
> +
> + /* calculate pin location for single and 2 bits information */
> + pinMask1bit = (u32) (1 << (NUM_OF_PINS - (pin + 1)));
> +
> + /* Set open drain, if required */
> + tmp_val = in_be32(&par_io->io_regs[port].cpodr);
> + if (open_drain)
> + out_be32(&par_io->io_regs[port].cpodr, pinMask1bit | tmp_val);
> + else
> + out_be32(&par_io->io_regs[port].cpodr, ~pinMask1bit & tmp_val);
> +
> + /* define direction */
> + tmp_val = (pin > (NUM_OF_PINS / 2) - 1) ?
> + in_be32(&par_io->io_regs[port].cpdir2) :
> + in_be32(&par_io->io_regs[port].cpdir1);
> +
> + /* get all bits mask for 2 bit per port */
> + pinMask2bits = (u32) (0x3 <<
> + (NUM_OF_PINS -
> + (pin % (NUM_OF_PINS / 2) + 1) * 2));
> +
> + /* Get the final mask we need for the right definition */
> + newMask2bits = (u32) (dir <<
> + (NUM_OF_PINS -
> + (pin % (NUM_OF_PINS / 2) + 1) * 2));
> +
> + /* clear and set 2 bits mask */
> + if (pin > (NUM_OF_PINS / 2) - 1) {
> + out_be32(&par_io->io_regs[port].cpdir2,
> + ~pinMask2bits & tmp_val);
> + tmp_val &= ~pinMask2bits;
> + out_be32(&par_io->io_regs[port].cpdir2, newMask2bits | tmp_val);
> + } else {
> + out_be32(&par_io->io_regs[port].cpdir1,
> + ~pinMask2bits & tmp_val);
> + tmp_val &= ~pinMask2bits;
> + out_be32(&par_io->io_regs[port].cpdir1, newMask2bits | tmp_val);
> + }
> + /* define pin assignment */
> + tmp_val = (pin > (NUM_OF_PINS / 2) - 1) ?
> + in_be32(&par_io->io_regs[port].cppar2) :
> + in_be32(&par_io->io_regs[port].cppar1);
> +
> + newMask2bits = (u32) (assignment << (NUM_OF_PINS -
> + (pin % (NUM_OF_PINS / 2) + 1) * 2));
> + /* clear and set 2 bits mask */
> + if (pin > (NUM_OF_PINS / 2) - 1) {
> + out_be32(&par_io->io_regs[port].cppar2,
> + ~pinMask2bits & tmp_val);
> + tmp_val &= ~pinMask2bits;
> + out_be32(&par_io->io_regs[port].cppar2, newMask2bits | tmp_val);
> + } else {
> + out_be32(&par_io->io_regs[port].cppar1,
> + ~pinMask2bits & tmp_val);
> + tmp_val &= ~pinMask2bits;
> + out_be32(&par_io->io_regs[port].cppar1, newMask2bits | tmp_val);
> + }
> +
> + /* Set interrupt mask if the pin generates interrupt */
> + if (has_irq) {
> + int irq = get_irq_num(port, pin);
> + u32 mask = 0;
> +
> + if (irq == -1) {
> + printk(KERN_WARNING "Port %d, pin %d is can't be "
> + "interrupt\n", port, pin);
> + return -EINVAL;
> + }
> + mask = 0x80000000 >> irq;
> +
> + tmp_val = in_be32(&qe_par_io->cepimr);
> + out_be32(&qe_par_io->cepimr, mask | tmp_val);
> + }
> +
> + return 0;
> +}
> +
> +EXPORT_SYMBOL(par_io_config_pin);
> +
> +int par_io_data_set(u8 port, u8 pin, u8 val)
> +{
> + u32 pin_mask, tmp_val;
> +
> + if (port >= NUM_OF_PAR_IOS)
> + return -EINVAL;
> + if (pin >= NUM_OF_PINS)
> + return -EINVAL;
> + /* calculate pin location */
> + pin_mask = (u32) (1 << (NUM_OF_PINS - 1 - pin));
> +
> + tmp_val = in_be32(&par_io->io_regs[port].cpdata);
> +
> + if (val == 0) /* clear */
> + out_be32(&par_io->io_regs[port].cpdata, ~pin_mask & tmp_val);
> + else /* set */
> + out_be32(&par_io->io_regs[port].cpdata, pin_mask | tmp_val);
> +
> + return 0;
> +}
> +
> +EXPORT_SYMBOL(par_io_data_set);
> +
> +int par_io_of_config(struct device_node *np)
> +{
> + struct device_node *pio;
> + phandle *ph;
> + int pio_map_len;
> + unsigned int *pio_map;
> +
> + ph = (phandle *) get_property(np, "pio-handle", NULL);
> + if (ph == 0) {
> + printk(KERN_ERR "pio-handle not available \n");
> + return -1;
> + }
> +
> + pio = of_find_node_by_phandle(*ph);
> +
> + pio_map = (unsigned int *)
> + get_property(pio, "pio-map", &pio_map_len);
> + if (pio_map == NULL) {
> + printk(KERN_ERR "pio-map is not set! \n");
> + return -1;
> + }
> + pio_map_len /= sizeof(unsigned int);
> + if ((pio_map_len % 6) != 0) {
> + printk(KERN_ERR "pio-map format wrong! \n");
> + return -1;
> + }
> +
> + while (pio_map_len > 0) {
> + par_io_config_pin((u8) pio_map[0], (u8) pio_map[1],
> + (int) pio_map[2], (int) pio_map[3],
> + (int) pio_map[4], (int) pio_map[5]);
> + pio_map += 6;
> + pio_map_len -= 6;
> + }
> + of_node_put(pio);
> + return 0;
> +}
> +EXPORT_SYMBOL(par_io_of_config);
> +
> +#ifdef DEBUG
> +static void dump_par_io(void)
> +{
> + int i;
> +
> + printk(KERN_INFO "PAR IO registars:\n");
> + printk(KERN_INFO "Base address: 0x%08x\n", (u32) par_io);
> + for (i = 0; i < NUM_OF_PAR_IOS; i++) {
> + printk(KERN_INFO "cpodr[%d] : addr - 0x%08x, val - 0x%08x\n",
> + i, (u32) & par_io->io_regs[i].cpodr,
> + in_be32(&par_io->io_regs[i].cpodr));
> + printk(KERN_INFO "cpdata[%d]: addr - 0x%08x, val - 0x%08x\n",
> + i, (u32) & par_io->io_regs[i].cpdata,
> + in_be32(&par_io->io_regs[i].cpdata));
> + printk(KERN_INFO "cpdir1[%d]: addr - 0x%08x, val - 0x%08x\n",
> + i, (u32) & par_io->io_regs[i].cpdir1,
> + in_be32(&par_io->io_regs[i].cpdir1));
> + printk(KERN_INFO "cpdir2[%d]: addr - 0x%08x, val - 0x%08x\n",
> + i, (u32) & par_io->io_regs[i].cpdir2,
> + in_be32(&par_io->io_regs[i].cpdir2));
> + printk(KERN_INFO "cppar1[%d]: addr - 0x%08x, val - 0x%08x\n",
> + i, (u32) & par_io->io_regs[i].cppar1,
> + in_be32(&par_io->io_regs[i].cppar1));
> + printk(KERN_INFO "cppar2[%d]: addr - 0x%08x, val - 0x%08x\n",
> + i, (u32) & par_io->io_regs[i].cppar2,
> + in_be32(&par_io->io_regs[i].cppar2));
> + }
> +
> + printk(KERN_INFO "QE PAR IO registars:\n");
> + printk(KERN_INFO "Base address: 0x%08x\n", (u32) qe_par_io);
> + printk(KERN_INFO "cepier : addr - 0x%08x, val - 0x%08x\n",
> + (u32) & qe_par_io->cepier, in_be32(&qe_par_io->cepier));
> + printk(KERN_INFO "cepimr : addr - 0x%08x, val - 0x%08x\n",
> + (u32) & qe_par_io->cepimr, in_be32(&qe_par_io->cepimr));
> + printk(KERN_INFO "cepicr : addr - 0x%08x, val - 0x%08x\n",
> + (u32) & qe_par_io->cepicr, in_be32(&qe_par_io->cepicr));
> +}
> +
> +EXPORT_SYMBOL(dump_par_io);
> +#endif
> -
> To unsubscribe from this list: send the line "unsubscribe linux-
> kernel" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
> Please read the FAQ at http://www.tux.org/lkml/
^ permalink raw reply
* Re: 2.6.17-mm2
From: Jeremy Fitzhardinge @ 2006-06-28 19:22 UTC (permalink / raw)
To: Andrew Morton
Cc: drfickle, linux-kernel, mbligh, Martin J. Bligh, linuxppc64-dev
In-Reply-To: <20060628121102.638f08d9.akpm@osdl.org>
Andrew Morton wrote:
> Found a way to reproduce it - do `cat /proc/slabinfo > /dev/null' in a
> tight loop. With that happening, a little two-way wasn't able to make
> it through `dbench 4' without soiling the upholstery. Then bisection-searching.
>
It's surprising it was so subtle. I'd been running with that code for a
month or so without a peep of problem...
J
^ permalink raw reply
* Re: 2.6.17-mm2
From: Martin Bligh @ 2006-06-28 19:36 UTC (permalink / raw)
To: Andrew Morton; +Cc: jeremy, drfickle, linux-kernel, mbligh, linuxppc64-dev
In-Reply-To: <20060628121102.638f08d9.akpm@osdl.org>
>>How the hell did you figure that one out?
>
> Found a way to reproduce it - do `cat /proc/slabinfo > /dev/null' in a
> tight loop. With that happening, a little two-way wasn't able to make
> it through `dbench 4' without soiling the upholstery. Then bisection-searching.
Aha. we probably trigger it because the automated test harness dumps a
bunch of crap out of /proc before and after running dbench then ;-)
Thanks!
M.
^ permalink raw reply
* Re: 2.6.17-mm2
From: Andrew Morton @ 2006-06-28 19:49 UTC (permalink / raw)
To: Jeremy Fitzhardinge
Cc: drfickle, linux-kernel, mbligh, mbligh, linuxppc64-dev
In-Reply-To: <44A2D6DA.1050607@goop.org>
On Wed, 28 Jun 2006 12:22:02 -0700
Jeremy Fitzhardinge <jeremy@goop.org> wrote:
> Andrew Morton wrote:
> > Found a way to reproduce it - do `cat /proc/slabinfo > /dev/null' in a
> > tight loop. With that happening, a little two-way wasn't able to make
> > it through `dbench 4' without soiling the upholstery. Then bisection-searching.
> >
> It's surprising it was so subtle. I'd been running with that code for a
> month or so without a peep of problem...
>
It'll only bite if someone does snprintf() into a too-short buffer. That's
rare (it's usually a bug). But it looks like the seq_file() code does it
when someone is trying to generate more than PAGE_SIZE's worth of data.
Like /proc/slabinfo.
^ permalink raw reply
* linux reboots when a process asks for all memory !?!
From: Antonio Di Bacco @ 2006-06-28 20:01 UTC (permalink / raw)
To: linuxppc-embedded
I have two different boards with same kernel version but different
configurations of this kernel. I wrote a little program that continuosly
malloc memory, on one board when the memory is not more available the test
program gets killed, on the other the board reboots, and something like "out
of memory" message from the kernel is printed.
Does this depend on the configuration of the kernel?
Bye,
Antonio.
^ permalink raw reply
* Re: CROSS_COMPILE - namespace collision
From: Wolfgang Denk @ 2006-06-28 20:14 UTC (permalink / raw)
To: Lee Revell; +Cc: linuxppc-embedded
In-Reply-To: <1151515702.15513.40.camel@mindpipe>
Dear Lee,
in message <1151515702.15513.40.camel@mindpipe> you wrote:
> I have not been able to get readline 5.1 to compile with the ELDK - it
Did you read the documentation?
> I can make it work with a hack, but I thought this might be interesting
> info.
Please see section "3.7.2. Rebuilding Target Packages" in the manual,
http://www.denx.de/wiki/view/DULG/ELDKRebuildingComponents#Section_3.7.2.
It describes clearly what needs to be done to build target packages.
Also note that readline already comes as part of the ELDK, so you
probably might just use the existing code.
Please RTFM.
Best regards,
Wolfgang Denk
--
Software Engineering: Embedded and Realtime Systems, Embedded Linux
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de
Sometimes a feeling is all we humans have to go on.
-- Kirk, "A Taste of Armageddon", stardate 3193.9
^ permalink raw reply
* Re: no login prompt with ml403 + uartlite-->major numbers?
From: T Ziomek @ 2006-06-28 20:14 UTC (permalink / raw)
To: linuxppc-embedded
In-Reply-To: <mailman.1193.1151524639.11183.linuxppc-embedded@ozlabs.org>
> On 6/28/06, Robert Zach <rza1@so-logic.co.at> wrote:
>> Hello!
>>
>> I use the "Standart" ml403 Design with the uartlite instead of the
>> uart16550...
>>
>> my kernel parameters are:
>> "console=ttl0 ip=off root=/dev/xsysace/disc0/part3 rw"
>>
>> It boots correctly, but i got no login prompt!!
>> getty is started with init.
>> my inittab looks like:
>> ...
>> ::respawn:/sbin/getty 9600 ttl0
At a lower level...are you keeping in mind that the UART-Lite baud rate (and
probably parity, stop bits, # of data bits) is set in hardware? So any at-
tempt to specify settings in software (e.g. your 'getty' line above, or on
the kernel cmd line) have no effect. If your console isn't set to match the
UART-Lite's hardware settings you're going to see gibberish, or nothing.
Tom
--
/"\ ASCII Ribbon Campaign |
\ / | Email to user 'CTZ001'
X Against HTML | at 'email.mot.com'
/ \ in e-mail & news |
^ permalink raw reply
* Re: Re: [Alsa-devel] RFC: dma_mmap_coherent() for powerpc/ppc architecture and ALSA?
From: Gerhard Pircher @ 2006-06-28 20:27 UTC (permalink / raw)
To: Takashi Iwai; +Cc: linuxppc-dev, rlrevell, alsa-devel, linux-kernel
Hi,
It took a little bit longer to integrate the patch, as I didn't figure out first how to implement the __dma_mmap_coherent() function for PPC systems with CONFIG_NOT_COHERENT_CACHE defined. :)
Unfortunately my system still crashes within snd_pcm_mmap_data_nopage()
(sound/core/pcm_native.c), as you can see below. I guess it tries to remap
a DMA buffer allocated by the not cache coherent DMA memory allocation
function in arch/ppc/kernel/dma-mapping.c.
Jun 28 21:59:30 localhost kernel: [ 199.869609] Using dma_mmap_coherent for mmaping DMA buffer!
Jun 28 21:59:30 localhost kernel: [ 199.925075] Oops: kernel access of bad area, sig: 11 [#1]
Jun 28 21:59:30 localhost kernel: [ 199.925106] NIP: E226FF44 LR: E226FF94 CTR: E226FEA4
Jun 28 21:59:30 localhost kernel: [ 199.925116] REGS: d2577d30 TRAP: 0600 Not tainted (2.6.16.16-a1-2)
Jun 28 21:59:30 localhost kernel: [ 199.925121] MSR: 00009032 <EE,ME,IR,DR> CR: 44048444 XER: 00000000
Jun 28 21:59:30 localhost kernel: [ 199.925134] DAR: 99A9999D, DSISR: 00000120
Jun 28 21:59:30 localhost kernel: [ 199.925140] TASK = d242cd10[4338] 'totem' THREAD: d2576000
Jun 28 21:59:30 localhost kernel: [ 199.925144] GPR00: 99A9999D D2577DE0 D242CD10 C0C826A0 00000000 D2577E08 D275F000 D36DC328
Jun 28 21:59:30 localhost kernel: [ 199.925158] GPR08: 02000000 00004000 00000000 99A99999 84048444 10054698 00000000 10196A58
Jun 28 21:59:30 localhost kernel: [ 199.925172] GPR16: 00000000 00000000 00000000 D36DC328 02000000 329FE000 00000000 00000000
Jun 28 21:59:30 localhost kernel: [ 199.925184] GPR24: DE5A6B20 DFA63C80 329FE000 DFA63C80 D20AD804 D275F7F8 D2576000 D2577E08
Jun 28 21:59:30 localhost kernel: [ 199.925199] NIP [E226FF44] snd_pcm_mmap_data_nopage+0xa0/0x12c [snd_pcm]
Jun 28 21:59:30 localhost kernel: [ 199.925300] LR [E226FF94] snd_pcm_mmap_data_nopage+0xf0/0x12c [snd_pcm]
Jun 28 21:59:30 localhost kernel: [ 199.925325] Call Trace:
Jun 28 21:59:30 localhost kernel: [ 199.925330] [D2577DE0] [C0010050] update_mmu_cache+0xe4/0xf4 (unreliable)
Jun 28 21:59:30 localhost kernel: [ 199.925361] [D2577E00] [C004F1D8] do_no_page+0xa4/0x6a4
Jun 28 21:59:30 localhost kernel: [ 199.925387] [D2577E60] [C004FA24] __handle_mm_fault+0x12c/0x328
Jun 28 21:59:30 localhost kernel: [ 199.925398] [D2577E90] [C000F740] do_page_fault+0x140/0x384
Jun 28 21:59:30 localhost kernel: [ 199.925407] [D2577F40] [C0004AC0] handle_page_fault+0xc/0x80
Jun 28 21:59:30 localhost kernel: [ 199.925423] Instruction dump:
Jun 28 21:59:30 localhost kernel: [ 199.925427] 812a0218 3d60c038 800b938c 7d292214 3d294000 5529c9f4 7c604a14 80030000
Jun 28 21:59:30 localhost kernel: [ 199.925441] 7c6b1b78 70094000 40820044 380b0004 <7d200028> 31290001 7d20012d 40a2fff4
Comments?
Thanks!
Gerhard
-------- Original-Nachricht --------
Datum: Wed, 14 Jun 2006 16:42:48 +0200
Von: Takashi Iwai <tiwai@suse.de>
An: Gerhard Pircher <gerhard_pircher@gmx.net>
Betreff: Re: [Alsa-devel] RFC: dma_mmap_coherent() for powerpc/ppc architecture and ALSA?
> At Mon, 12 Jun 2006 16:42:54 +0200,
> Gerhard Pircher wrote:
> >
> > > > But as far as I understand this would require a rewrite of all the
> > > > ALSA drivers (or at least a rewrite of the ALSA's DMA helper
> > > > functions).
> > >
> > > Yes. The change of ALSA side has been also on my tree. But it was
> > > still pending since I'm not satisfied with the design yet.
> > > If you're interested in it, let me know. I'll post the patch.
> >
> > Yes, please! Then I can test, if the dma_mmap_coherent() patch works on
> > my non cache coherent powerpc machine.
>
> For using dma_mmap_coherent(), the patch below should suffice.
> (Also you need to enable HAVE_DMA_MMAP_COHERENT there not only for
> ARM.)
>
> > Do you think the DMA Layer/ALSA patches will go upstream in one of
> > the next ALSA/Linux kernel versions?
>
> Definitely no 2.6.18 material yet.
>
>
> Takashi
--
Echte DSL-Flatrate dauerhaft für 0,- Euro*!
"Feel free" mit GMX DSL! http://www.gmx.net/de/go/dsl
^ permalink raw reply
* [PATCH] todc: add support for Time-Of-Day-Clock
From: Mark A. Greer @ 2006-06-28 21:13 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev
This is a resubmit with a proper subject and with all comments addressed.
Applies cleanly to powerpc.git 649e85797259162f7fdc696420e7492f20226f2d
Mark
--
The todc code from arch/ppc supports many todc/rtc chips and is needed
in arch/powerpc. This patch adds the todc code to arch/powerpc.
Signed-off-by: Mark A. Greer <mgreer@mvista.com>
--
arch/powerpc/Kconfig | 7
arch/powerpc/sysdev/Makefile | 1
arch/powerpc/sysdev/todc.c | 392 ++++++++++++++++++++++++++++++++++
include/asm-powerpc/todc.h | 487 +++++++++++++++++++++++++++++++++++++++++++
4 files changed, 887 insertions(+)
--
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index a4dad6e..b1dcdbd 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -562,6 +562,13 @@ config TAU_AVERAGE
/proc/cpuinfo.
If in doubt, say N here.
+
+config PPC_TODC
+ depends on EMBEDDED6xx
+ bool "Generic Time-of-day Clock (TODC) support"
+ ---help---
+ This adds support for many TODC/RTC chips.
+
endmenu
source arch/powerpc/platforms/embedded6xx/Kconfig
diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile
index cef95b0..8b0dd5f 100644
--- a/arch/powerpc/sysdev/Makefile
+++ b/arch/powerpc/sysdev/Makefile
@@ -12,3 +12,4 @@ obj-$(CONFIG_U3_DART) += dart_iommu.o
obj-$(CONFIG_MMIO_NVRAM) += mmio_nvram.o
obj-$(CONFIG_PPC_83xx) += ipic.o
obj-$(CONFIG_FSL_SOC) += fsl_soc.o
+obj-$(CONFIG_PPC_TODC) += todc.o
diff --git a/arch/powerpc/sysdev/todc.c b/arch/powerpc/sysdev/todc.c
new file mode 100644
index 0000000..0a65980
--- /dev/null
+++ b/arch/powerpc/sysdev/todc.c
@@ -0,0 +1,392 @@
+/*
+ * Time of Day Clock support for the M48T35, M48T37, M48T59, and MC146818
+ * Real Time Clocks/Timekeepers.
+ *
+ * Author: Mark A. Greer <mgreer@mvista.com>
+ *
+ * 2001-2004 (c) MontaVista, Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/time.h>
+#include <linux/timex.h>
+#include <linux/bcd.h>
+#include <linux/mc146818rtc.h>
+
+#include <asm/machdep.h>
+#include <asm/io.h>
+#include <asm/time.h>
+#include <asm/todc.h>
+
+/*
+ * Depending on the hardware on your board and your board design, the
+ * RTC/NVRAM may be accessed either directly (like normal memory) or via
+ * address/data registers. If your board uses the direct method, set
+ * 'nvram_data' to the base address of your nvram and leave 'nvram_as0' and
+ * 'nvram_as1' NULL. If your board uses address/data regs to access nvram,
+ * set 'nvram_as0' to the address of the lower byte, set 'nvram_as1' to the
+ * address of the upper byte (leave NULL if using mc146818), and set
+ * 'nvram_data' to the address of the 8-bit data register.
+ *
+ * Note: Even though the documentation for the various RTC chips say that it
+ * take up to a second before it starts updating once the 'R' bit is
+ * cleared, they always seem to update even though we bang on it many
+ * times a second. This is true, except for the Dallas Semi 1746/1747
+ * (possibly others). Those chips seem to have a real problem whenever
+ * we set the 'R' bit before reading them, they basically stop counting.
+ * --MAG
+ */
+
+/*
+ * 'todc_info' should be initialized in your *_setup.c file to
+ * point to a fully initialized 'todc_info_t' structure.
+ * This structure holds all the register offsets for your particular
+ * TODC/RTC chip.
+ * TODC_ALLOC()/TODC_INIT() will allocate and initialize this table for you.
+ */
+
+#ifdef RTC_FREQ_SELECT
+#undef RTC_FREQ_SELECT
+#define RTC_FREQ_SELECT control_b /* Register A */
+#endif
+
+#ifdef RTC_CONTROL
+#undef RTC_CONTROL
+#define RTC_CONTROL control_a /* Register B */
+#endif
+
+#ifdef RTC_INTR_FLAGS
+#undef RTC_INTR_FLAGS
+#define RTC_INTR_FLAGS watchdog /* Register C */
+#endif
+
+#ifdef RTC_VALID
+#undef RTC_VALID
+#define RTC_VALID interrupts /* Register D */
+#endif
+
+/* Access routines when RTC accessed directly (like normal memory) */
+u_char
+todc_direct_read_val(int addr)
+{
+ return readb((void __iomem *)(todc_info->nvram_data + addr));
+}
+
+void
+todc_direct_write_val(int addr, unsigned char val)
+{
+ writeb(val, (void __iomem *)(todc_info->nvram_data + addr));
+ return;
+}
+
+/* Access routines for accessing m48txx type chips via addr/data regs */
+u_char
+todc_m48txx_read_val(int addr)
+{
+ outb(addr, todc_info->nvram_as0);
+ outb(addr>>todc_info->as0_bits, todc_info->nvram_as1);
+ return inb(todc_info->nvram_data);
+}
+
+void
+todc_m48txx_write_val(int addr, unsigned char val)
+{
+ outb(addr, todc_info->nvram_as0);
+ outb(addr>>todc_info->as0_bits, todc_info->nvram_as1);
+ outb(val, todc_info->nvram_data);
+ return;
+}
+
+/* Access routines for accessing mc146818 type chips via addr/data regs */
+u_char
+todc_mc146818_read_val(int addr)
+{
+ outb_p(addr, todc_info->nvram_as0);
+ return inb_p(todc_info->nvram_data);
+}
+
+void
+todc_mc146818_write_val(int addr, unsigned char val)
+{
+ outb_p(addr, todc_info->nvram_as0);
+ outb_p(val, todc_info->nvram_data);
+}
+
+
+/*
+ * Routines to make RTC chips with NVRAM buried behind an addr/data pair
+ * have the NVRAM and clock regs appear at the same level.
+ * The NVRAM will appear to start at addr 0 and the clock regs will appear
+ * to start immediately after the NVRAM (actually, start at offset
+ * todc_info->nvram_size).
+ */
+static inline u_char
+todc_read_val(int addr)
+{
+ u_char val;
+
+ if (todc_info->sw_flags & TODC_FLAG_2_LEVEL_NVRAM) {
+ if (addr < todc_info->nvram_size) { /* NVRAM */
+ ppc_md.rtc_write_val(todc_info->nvram_addr_reg, addr);
+ val = ppc_md.rtc_read_val(todc_info->nvram_data_reg);
+ } else { /* Clock Reg */
+ addr -= todc_info->nvram_size;
+ val = ppc_md.rtc_read_val(addr);
+ }
+ } else
+ val = ppc_md.rtc_read_val(addr);
+
+ return val;
+}
+
+static inline void
+todc_write_val(int addr, u_char val)
+{
+ if (todc_info->sw_flags & TODC_FLAG_2_LEVEL_NVRAM) {
+ if (addr < todc_info->nvram_size) { /* NVRAM */
+ ppc_md.rtc_write_val(todc_info->nvram_addr_reg, addr);
+ ppc_md.rtc_write_val(todc_info->nvram_data_reg, val);
+ } else { /* Clock Reg */
+ addr -= todc_info->nvram_size;
+ ppc_md.rtc_write_val(addr, val);
+ }
+ } else
+ ppc_md.rtc_write_val(addr, val);
+}
+
+/*
+ * TODC routines
+ *
+ * There is some ugly stuff in that there are assumptions for the mc146818.
+ *
+ * Assumptions:
+ * - todc_info->control_a has the offset as mc146818 Register B reg
+ * - todc_info->control_b has the offset as mc146818 Register A reg
+ * - m48txx control reg's write enable or 'W' bit is same as
+ * mc146818 Register B 'SET' bit (i.e., 0x80)
+ *
+ * These assumptions were made to make the code simpler.
+ */
+long __init
+todc_time_init(void)
+{
+ u_char cntl_b;
+
+ if (!ppc_md.rtc_read_val)
+ ppc_md.rtc_read_val = ppc_md.nvram_read_val;
+ if (!ppc_md.rtc_write_val)
+ ppc_md.rtc_write_val = ppc_md.nvram_write_val;
+
+ cntl_b = todc_read_val(todc_info->control_b);
+
+ if (todc_info->rtc_type == TODC_TYPE_MC146818) {
+ if ((cntl_b & 0x70) != 0x20) {
+ printk(KERN_INFO "TODC real-time-clock was stopped."
+ " Now starting...");
+ cntl_b &= ~0x70;
+ cntl_b |= 0x20;
+ }
+
+ todc_write_val(todc_info->control_b, cntl_b);
+ } else if (todc_info->rtc_type == TODC_TYPE_DS17285) {
+ u_char mode;
+
+ mode = todc_read_val(TODC_TYPE_DS17285_CNTL_A);
+ /* Make sure countdown clear is not set */
+ mode &= ~0x40;
+ /* Enable oscillator, extended register set */
+ mode |= 0x30;
+ todc_write_val(TODC_TYPE_DS17285_CNTL_A, mode);
+
+ } else if (todc_info->rtc_type == TODC_TYPE_DS1501) {
+ u_char month;
+
+ todc_info->enable_read = TODC_DS1501_CNTL_B_TE;
+ todc_info->enable_write = TODC_DS1501_CNTL_B_TE;
+
+ month = todc_read_val(todc_info->month);
+
+ if ((month & 0x80) == 0x80) {
+ printk(KERN_INFO "TODC %s %s\n",
+ "real-time-clock was stopped.",
+ "Now starting...");
+ month &= ~0x80;
+ todc_write_val(todc_info->month, month);
+ }
+
+ cntl_b &= ~TODC_DS1501_CNTL_B_TE;
+ todc_write_val(todc_info->control_b, cntl_b);
+ } else { /* must be a m48txx type */
+ u_char cntl_a;
+
+ todc_info->enable_read = TODC_MK48TXX_CNTL_A_R;
+ todc_info->enable_write = TODC_MK48TXX_CNTL_A_W;
+
+ cntl_a = todc_read_val(todc_info->control_a);
+
+ /* Check & clear STOP bit in control B register */
+ if (cntl_b & TODC_MK48TXX_DAY_CB) {
+ printk(KERN_INFO "TODC %s %s\n",
+ "real-time-clock was stopped.",
+ "Now starting...");
+
+ cntl_a |= todc_info->enable_write;
+ cntl_b &= ~TODC_MK48TXX_DAY_CB;/* Start Oscil */
+
+ todc_write_val(todc_info->control_a, cntl_a);
+ todc_write_val(todc_info->control_b, cntl_b);
+ }
+
+ /* Make sure READ & WRITE bits are cleared. */
+ cntl_a &= ~(todc_info->enable_write | todc_info->enable_read);
+ todc_write_val(todc_info->control_a, cntl_a);
+ }
+
+ return 0;
+}
+
+/*
+ * There is some ugly stuff in that there are assumptions that for a mc146818,
+ * the todc_info->control_a has the offset of the mc146818 Register B reg and
+ * that the register'ss 'SET' bit is the same as the m48txx's write enable
+ * bit in the control register of the m48txx (i.e., 0x80).
+ *
+ * It was done to make the code look simpler.
+ */
+void
+todc_get_rtc_time(struct rtc_time *tm)
+{
+ uint year = 0, mon = 0, mday = 0, hour = 0, min = 0, sec = 0;
+ uint limit, i;
+ u_char save_control, uip = 0;
+ extern void GregorianDay(struct rtc_time *);
+
+ spin_lock(&rtc_lock);
+ save_control = todc_read_val(todc_info->control_a);
+
+ if (todc_info->rtc_type != TODC_TYPE_MC146818) {
+ limit = 1;
+
+ switch (todc_info->rtc_type) {
+ case TODC_TYPE_DS1553:
+ case TODC_TYPE_DS1557:
+ case TODC_TYPE_DS1743:
+ case TODC_TYPE_DS1746: /* XXXX BAD HACK -> FIX */
+ case TODC_TYPE_DS1747:
+ case TODC_TYPE_DS17285:
+ break;
+ default:
+ todc_write_val(todc_info->control_a,
+ (save_control | todc_info->enable_read));
+ }
+ } else
+ limit = 100000000;
+
+ for (i=0; i<limit; i++) {
+ if (todc_info->rtc_type == TODC_TYPE_MC146818)
+ uip = todc_read_val(todc_info->RTC_FREQ_SELECT);
+
+ sec = todc_read_val(todc_info->seconds) & 0x7f;
+ min = todc_read_val(todc_info->minutes) & 0x7f;
+ hour = todc_read_val(todc_info->hours) & 0x3f;
+ mday = todc_read_val(todc_info->day_of_month) & 0x3f;
+ mon = todc_read_val(todc_info->month) & 0x1f;
+ year = todc_read_val(todc_info->year) & 0xff;
+
+ if (todc_info->rtc_type == TODC_TYPE_MC146818) {
+ uip |= todc_read_val(todc_info->RTC_FREQ_SELECT);
+ if ((uip & RTC_UIP) == 0)
+ break;
+ }
+ }
+
+ if (todc_info->rtc_type != TODC_TYPE_MC146818) {
+ switch (todc_info->rtc_type) {
+ case TODC_TYPE_DS1553:
+ case TODC_TYPE_DS1557:
+ case TODC_TYPE_DS1743:
+ case TODC_TYPE_DS1746: /* XXXX BAD HACK -> FIX */
+ case TODC_TYPE_DS1747:
+ case TODC_TYPE_DS17285:
+ break;
+ default:
+ save_control &= ~(todc_info->enable_read);
+ todc_write_val(todc_info->control_a, save_control);
+ }
+ }
+ spin_unlock(&rtc_lock);
+
+ if ((todc_info->rtc_type != TODC_TYPE_MC146818)
+ || ((save_control & RTC_DM_BINARY) == 0)
+ || RTC_ALWAYS_BCD) {
+ BCD_TO_BIN(sec);
+ BCD_TO_BIN(min);
+ BCD_TO_BIN(hour);
+ BCD_TO_BIN(mday);
+ BCD_TO_BIN(mon);
+ BCD_TO_BIN(year);
+ }
+
+ if ((year + 1900) < 1970) {
+ year += 100;
+ }
+
+ tm->tm_sec = sec;
+ tm->tm_min = min;
+ tm->tm_hour = hour;
+ tm->tm_mday = mday;
+ tm->tm_mon = mon;
+ tm->tm_year = year;
+
+ GregorianDay(tm);
+}
+
+int
+todc_set_rtc_time(struct rtc_time *tm)
+{
+ u_char save_control, save_freq_select = 0;
+
+ spin_lock(&rtc_lock);
+ save_control = todc_read_val(todc_info->control_a);
+
+ /* Assuming MK48T59_RTC_CA_WRITE & RTC_SET are equal */
+ todc_write_val(todc_info->control_a,
+ (save_control | todc_info->enable_write));
+ save_control &= ~(todc_info->enable_write); /* in case it was set */
+
+ if (todc_info->rtc_type == TODC_TYPE_MC146818) {
+ save_freq_select = todc_read_val(todc_info->RTC_FREQ_SELECT);
+ todc_write_val(todc_info->RTC_FREQ_SELECT,
+ save_freq_select | RTC_DIV_RESET2);
+ }
+
+ if ((todc_info->rtc_type != TODC_TYPE_MC146818)
+ || ((save_control & RTC_DM_BINARY) == 0)
+ || RTC_ALWAYS_BCD) {
+ BIN_TO_BCD(tm->tm_sec);
+ BIN_TO_BCD(tm->tm_min);
+ BIN_TO_BCD(tm->tm_hour);
+ BIN_TO_BCD(tm->tm_mon);
+ BIN_TO_BCD(tm->tm_mday);
+ BIN_TO_BCD(tm->tm_year);
+ }
+
+ todc_write_val(todc_info->seconds, tm->tm_sec);
+ todc_write_val(todc_info->minutes, tm->tm_min);
+ todc_write_val(todc_info->hours, tm->tm_hour);
+ todc_write_val(todc_info->month, tm->tm_mon);
+ todc_write_val(todc_info->day_of_month, tm->tm_mday);
+ todc_write_val(todc_info->year, tm->tm_year);
+
+ todc_write_val(todc_info->control_a, save_control);
+
+ if (todc_info->rtc_type == TODC_TYPE_MC146818)
+ todc_write_val(todc_info->RTC_FREQ_SELECT, save_freq_select);
+
+ spin_unlock(&rtc_lock);
+ return 0;
+}
diff --git a/include/asm-powerpc/todc.h b/include/asm-powerpc/todc.h
new file mode 100644
index 0000000..60a8c39
--- /dev/null
+++ b/include/asm-powerpc/todc.h
@@ -0,0 +1,487 @@
+/*
+ * Definitions for the M48Txx and mc146818 series of Time of day/Real Time
+ * Clock chips.
+ *
+ * Author: Mark A. Greer <mgreer@mvista.com>
+ *
+ * 2001 (c) MontaVista, Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+
+/*
+ * Support for the M48T37/M48T59/.../mc146818 Real Time Clock chips.
+ * Purpose is to make one generic file that handles all of these chips instead
+ * of every platform implementing the same code over & over again.
+ */
+
+#ifndef __PPC_KERNEL_TODC_H
+#define __PPC_KERNEL_TODC_H
+
+typedef struct {
+ uint rtc_type; /* your particular chip */
+
+ /*
+ * Following are the addresses of the AS0, AS1, and DATA registers
+ * of these chips. Note that these are board-specific.
+ */
+ unsigned int nvram_as0;
+ unsigned int nvram_as1;
+ unsigned int nvram_data;
+
+ /*
+ * Define bits to stop external set of regs from changing so
+ * the chip can be read/written reliably.
+ */
+ unsigned char enable_read;
+ unsigned char enable_write;
+
+ /*
+ * Following is the number of AS0 address bits. This is normally
+ * 8 but some bad hardware routes address lines incorrectly.
+ */
+ int as0_bits;
+
+ int nvram_size; /* Size of NVRAM on chip */
+ int sw_flags; /* Software control flags */
+
+ /* Following are the register offsets for the particular chip */
+ int year;
+ int month;
+ int day_of_month;
+ int day_of_week;
+ int hours;
+ int minutes;
+ int seconds;
+ int control_b;
+ int control_a;
+ int watchdog;
+ int interrupts;
+ int alarm_date;
+ int alarm_hour;
+ int alarm_minutes;
+ int alarm_seconds;
+ int century;
+ int flags;
+
+ /*
+ * Some RTC chips have their NVRAM buried behind a addr/data pair of
+ * regs on the first level/clock registers. The following fields
+ * are the addresses for those addr/data regs.
+ */
+ int nvram_addr_reg;
+ int nvram_data_reg;
+} todc_info_t;
+
+/*
+ * Define the types of TODC/RTC variants that are supported in
+ * arch/ppc/kernel/todc_time.c
+ * Make a new one of these for any chip somehow differs from what's already
+ * defined. That way, if you ever need to put in code to touch those
+ * bits/registers in todc_time.c, you can put it inside an
+ * 'if (todc_info->rtc_type == TODC_TYPE_XXX)' so you won't break
+ * anyone else.
+ */
+#define TODC_TYPE_MK48T35 1
+#define TODC_TYPE_MK48T37 2
+#define TODC_TYPE_MK48T59 3
+#define TODC_TYPE_DS1693 4 /* Dallas DS1693 RTC */
+#define TODC_TYPE_DS1743 5 /* Dallas DS1743 RTC */
+#define TODC_TYPE_DS1746 6 /* Dallas DS1746 RTC */
+#define TODC_TYPE_DS1747 7 /* Dallas DS1747 RTC */
+#define TODC_TYPE_DS1501 8 /* Dallas DS1501 RTC */
+#define TODC_TYPE_DS1643 9 /* Dallas DS1643 RTC */
+#define TODC_TYPE_PC97307 10 /* PC97307 internal RTC */
+#define TODC_TYPE_DS1557 11 /* Dallas DS1557 RTC */
+#define TODC_TYPE_DS17285 12 /* Dallas DS17285 RTC */
+#define TODC_TYPE_DS1553 13 /* Dallas DS1553 RTC */
+#define TODC_TYPE_MC146818 100 /* Leave room for m48txx's */
+
+/*
+ * Bit to clear/set to enable reads/writes to the chip
+ */
+#define TODC_MK48TXX_CNTL_A_R 0x40
+#define TODC_MK48TXX_CNTL_A_W 0x80
+#define TODC_MK48TXX_DAY_CB 0x80
+
+#define TODC_DS1501_CNTL_B_TE 0x80
+
+/*
+ * Define flag bits used by todc routines.
+ */
+#define TODC_FLAG_2_LEVEL_NVRAM 0x00000001
+
+/*
+ * Define the values for the various RTC's that should to into the todc_info
+ * table.
+ * Note: The XXX_NVRAM_SIZE, XXX_NVRAM_ADDR_REG, and XXX_NVRAM_DATA_REG only
+ * matter if XXX_SW_FLAGS has TODC_FLAG_2_LEVEL_NVRAM set.
+ */
+#define TODC_TYPE_MK48T35_NVRAM_SIZE 0x7ff8
+#define TODC_TYPE_MK48T35_SW_FLAGS 0
+#define TODC_TYPE_MK48T35_YEAR 0x7fff
+#define TODC_TYPE_MK48T35_MONTH 0x7ffe
+#define TODC_TYPE_MK48T35_DOM 0x7ffd /* Day of Month */
+#define TODC_TYPE_MK48T35_DOW 0x7ffc /* Day of Week */
+#define TODC_TYPE_MK48T35_HOURS 0x7ffb
+#define TODC_TYPE_MK48T35_MINUTES 0x7ffa
+#define TODC_TYPE_MK48T35_SECONDS 0x7ff9
+#define TODC_TYPE_MK48T35_CNTL_B 0x7ff9
+#define TODC_TYPE_MK48T35_CNTL_A 0x7ff8
+#define TODC_TYPE_MK48T35_WATCHDOG 0x0000
+#define TODC_TYPE_MK48T35_INTERRUPTS 0x0000
+#define TODC_TYPE_MK48T35_ALARM_DATE 0x0000
+#define TODC_TYPE_MK48T35_ALARM_HOUR 0x0000
+#define TODC_TYPE_MK48T35_ALARM_MINUTES 0x0000
+#define TODC_TYPE_MK48T35_ALARM_SECONDS 0x0000
+#define TODC_TYPE_MK48T35_CENTURY 0x0000
+#define TODC_TYPE_MK48T35_FLAGS 0x0000
+#define TODC_TYPE_MK48T35_NVRAM_ADDR_REG 0
+#define TODC_TYPE_MK48T35_NVRAM_DATA_REG 0
+
+#define TODC_TYPE_MK48T37_NVRAM_SIZE 0x7ff0
+#define TODC_TYPE_MK48T37_SW_FLAGS 0
+#define TODC_TYPE_MK48T37_YEAR 0x7fff
+#define TODC_TYPE_MK48T37_MONTH 0x7ffe
+#define TODC_TYPE_MK48T37_DOM 0x7ffd /* Day of Month */
+#define TODC_TYPE_MK48T37_DOW 0x7ffc /* Day of Week */
+#define TODC_TYPE_MK48T37_HOURS 0x7ffb
+#define TODC_TYPE_MK48T37_MINUTES 0x7ffa
+#define TODC_TYPE_MK48T37_SECONDS 0x7ff9
+#define TODC_TYPE_MK48T37_CNTL_B 0x7ff9
+#define TODC_TYPE_MK48T37_CNTL_A 0x7ff8
+#define TODC_TYPE_MK48T37_WATCHDOG 0x7ff7
+#define TODC_TYPE_MK48T37_INTERRUPTS 0x7ff6
+#define TODC_TYPE_MK48T37_ALARM_DATE 0x7ff5
+#define TODC_TYPE_MK48T37_ALARM_HOUR 0x7ff4
+#define TODC_TYPE_MK48T37_ALARM_MINUTES 0x7ff3
+#define TODC_TYPE_MK48T37_ALARM_SECONDS 0x7ff2
+#define TODC_TYPE_MK48T37_CENTURY 0x7ff1
+#define TODC_TYPE_MK48T37_FLAGS 0x7ff0
+#define TODC_TYPE_MK48T37_NVRAM_ADDR_REG 0
+#define TODC_TYPE_MK48T37_NVRAM_DATA_REG 0
+
+#define TODC_TYPE_MK48T59_NVRAM_SIZE 0x1ff0
+#define TODC_TYPE_MK48T59_SW_FLAGS 0
+#define TODC_TYPE_MK48T59_YEAR 0x1fff
+#define TODC_TYPE_MK48T59_MONTH 0x1ffe
+#define TODC_TYPE_MK48T59_DOM 0x1ffd /* Day of Month */
+#define TODC_TYPE_MK48T59_DOW 0x1ffc /* Day of Week */
+#define TODC_TYPE_MK48T59_HOURS 0x1ffb
+#define TODC_TYPE_MK48T59_MINUTES 0x1ffa
+#define TODC_TYPE_MK48T59_SECONDS 0x1ff9
+#define TODC_TYPE_MK48T59_CNTL_B 0x1ff9
+#define TODC_TYPE_MK48T59_CNTL_A 0x1ff8
+#define TODC_TYPE_MK48T59_WATCHDOG 0x1fff
+#define TODC_TYPE_MK48T59_INTERRUPTS 0x1fff
+#define TODC_TYPE_MK48T59_ALARM_DATE 0x1fff
+#define TODC_TYPE_MK48T59_ALARM_HOUR 0x1fff
+#define TODC_TYPE_MK48T59_ALARM_MINUTES 0x1fff
+#define TODC_TYPE_MK48T59_ALARM_SECONDS 0x1fff
+#define TODC_TYPE_MK48T59_CENTURY 0x1fff
+#define TODC_TYPE_MK48T59_FLAGS 0x1fff
+#define TODC_TYPE_MK48T59_NVRAM_ADDR_REG 0
+#define TODC_TYPE_MK48T59_NVRAM_DATA_REG 0
+
+#define TODC_TYPE_DS1501_NVRAM_SIZE 0x100
+#define TODC_TYPE_DS1501_SW_FLAGS TODC_FLAG_2_LEVEL_NVRAM
+#define TODC_TYPE_DS1501_YEAR (TODC_TYPE_DS1501_NVRAM_SIZE + 0x06)
+#define TODC_TYPE_DS1501_MONTH (TODC_TYPE_DS1501_NVRAM_SIZE + 0x05)
+#define TODC_TYPE_DS1501_DOM (TODC_TYPE_DS1501_NVRAM_SIZE + 0x04)
+#define TODC_TYPE_DS1501_DOW (TODC_TYPE_DS1501_NVRAM_SIZE + 0x03)
+#define TODC_TYPE_DS1501_HOURS (TODC_TYPE_DS1501_NVRAM_SIZE + 0x02)
+#define TODC_TYPE_DS1501_MINUTES (TODC_TYPE_DS1501_NVRAM_SIZE + 0x01)
+#define TODC_TYPE_DS1501_SECONDS (TODC_TYPE_DS1501_NVRAM_SIZE + 0x00)
+#define TODC_TYPE_DS1501_CNTL_B (TODC_TYPE_DS1501_NVRAM_SIZE + 0x0f)
+#define TODC_TYPE_DS1501_CNTL_A (TODC_TYPE_DS1501_NVRAM_SIZE + 0x0f)
+#define TODC_TYPE_DS1501_WATCHDOG (TODC_TYPE_DS1501_NVRAM_SIZE + 0xff)
+#define TODC_TYPE_DS1501_INTERRUPTS (TODC_TYPE_DS1501_NVRAM_SIZE + 0xff)
+#define TODC_TYPE_DS1501_ALARM_DATE (TODC_TYPE_DS1501_NVRAM_SIZE + 0x0b)
+#define TODC_TYPE_DS1501_ALARM_HOUR (TODC_TYPE_DS1501_NVRAM_SIZE + 0x0a)
+#define TODC_TYPE_DS1501_ALARM_MINUTES (TODC_TYPE_DS1501_NVRAM_SIZE + 0x09)
+#define TODC_TYPE_DS1501_ALARM_SECONDS (TODC_TYPE_DS1501_NVRAM_SIZE + 0x08)
+#define TODC_TYPE_DS1501_CENTURY (TODC_TYPE_DS1501_NVRAM_SIZE + 0x07)
+#define TODC_TYPE_DS1501_FLAGS (TODC_TYPE_DS1501_NVRAM_SIZE + 0xff)
+#define TODC_TYPE_DS1501_NVRAM_ADDR_REG 0x10
+#define TODC_TYPE_DS1501_NVRAM_DATA_REG 0x13
+
+#define TODC_TYPE_DS1553_NVRAM_SIZE 0x1ff0
+#define TODC_TYPE_DS1553_SW_FLAGS 0
+#define TODC_TYPE_DS1553_YEAR 0x1fff
+#define TODC_TYPE_DS1553_MONTH 0x1ffe
+#define TODC_TYPE_DS1553_DOM 0x1ffd /* Day of Month */
+#define TODC_TYPE_DS1553_DOW 0x1ffc /* Day of Week */
+#define TODC_TYPE_DS1553_HOURS 0x1ffb
+#define TODC_TYPE_DS1553_MINUTES 0x1ffa
+#define TODC_TYPE_DS1553_SECONDS 0x1ff9
+#define TODC_TYPE_DS1553_CNTL_B 0x1ff9
+#define TODC_TYPE_DS1553_CNTL_A 0x1ff8 /* control_a R/W regs */
+#define TODC_TYPE_DS1553_WATCHDOG 0x1ff7
+#define TODC_TYPE_DS1553_INTERRUPTS 0x1ff6
+#define TODC_TYPE_DS1553_ALARM_DATE 0x1ff5
+#define TODC_TYPE_DS1553_ALARM_HOUR 0x1ff4
+#define TODC_TYPE_DS1553_ALARM_MINUTES 0x1ff3
+#define TODC_TYPE_DS1553_ALARM_SECONDS 0x1ff2
+#define TODC_TYPE_DS1553_CENTURY 0x1ff8
+#define TODC_TYPE_DS1553_FLAGS 0x1ff0
+#define TODC_TYPE_DS1553_NVRAM_ADDR_REG 0
+#define TODC_TYPE_DS1553_NVRAM_DATA_REG 0
+
+#define TODC_TYPE_DS1557_NVRAM_SIZE 0x7fff0
+#define TODC_TYPE_DS1557_SW_FLAGS 0
+#define TODC_TYPE_DS1557_YEAR 0x7ffff
+#define TODC_TYPE_DS1557_MONTH 0x7fffe
+#define TODC_TYPE_DS1557_DOM 0x7fffd /* Day of Month */
+#define TODC_TYPE_DS1557_DOW 0x7fffc /* Day of Week */
+#define TODC_TYPE_DS1557_HOURS 0x7fffb
+#define TODC_TYPE_DS1557_MINUTES 0x7fffa
+#define TODC_TYPE_DS1557_SECONDS 0x7fff9
+#define TODC_TYPE_DS1557_CNTL_B 0x7fff9
+#define TODC_TYPE_DS1557_CNTL_A 0x7fff8 /* control_a R/W regs */
+#define TODC_TYPE_DS1557_WATCHDOG 0x7fff7
+#define TODC_TYPE_DS1557_INTERRUPTS 0x7fff6
+#define TODC_TYPE_DS1557_ALARM_DATE 0x7fff5
+#define TODC_TYPE_DS1557_ALARM_HOUR 0x7fff4
+#define TODC_TYPE_DS1557_ALARM_MINUTES 0x7fff3
+#define TODC_TYPE_DS1557_ALARM_SECONDS 0x7fff2
+#define TODC_TYPE_DS1557_CENTURY 0x7fff8
+#define TODC_TYPE_DS1557_FLAGS 0x7fff0
+#define TODC_TYPE_DS1557_NVRAM_ADDR_REG 0
+#define TODC_TYPE_DS1557_NVRAM_DATA_REG 0
+
+#define TODC_TYPE_DS1643_NVRAM_SIZE 0x1ff8
+#define TODC_TYPE_DS1643_SW_FLAGS 0
+#define TODC_TYPE_DS1643_YEAR 0x1fff
+#define TODC_TYPE_DS1643_MONTH 0x1ffe
+#define TODC_TYPE_DS1643_DOM 0x1ffd /* Day of Month */
+#define TODC_TYPE_DS1643_DOW 0x1ffc /* Day of Week */
+#define TODC_TYPE_DS1643_HOURS 0x1ffb
+#define TODC_TYPE_DS1643_MINUTES 0x1ffa
+#define TODC_TYPE_DS1643_SECONDS 0x1ff9
+#define TODC_TYPE_DS1643_CNTL_B 0x1ff9
+#define TODC_TYPE_DS1643_CNTL_A 0x1ff8 /* control_a R/W regs */
+#define TODC_TYPE_DS1643_WATCHDOG 0x1fff
+#define TODC_TYPE_DS1643_INTERRUPTS 0x1fff
+#define TODC_TYPE_DS1643_ALARM_DATE 0x1fff
+#define TODC_TYPE_DS1643_ALARM_HOUR 0x1fff
+#define TODC_TYPE_DS1643_ALARM_MINUTES 0x1fff
+#define TODC_TYPE_DS1643_ALARM_SECONDS 0x1fff
+#define TODC_TYPE_DS1643_CENTURY 0x1ff8
+#define TODC_TYPE_DS1643_FLAGS 0x1fff
+#define TODC_TYPE_DS1643_NVRAM_ADDR_REG 0
+#define TODC_TYPE_DS1643_NVRAM_DATA_REG 0
+
+#define TODC_TYPE_DS1693_NVRAM_SIZE 0 /* Not handled yet */
+#define TODC_TYPE_DS1693_SW_FLAGS 0
+#define TODC_TYPE_DS1693_YEAR 0x09
+#define TODC_TYPE_DS1693_MONTH 0x08
+#define TODC_TYPE_DS1693_DOM 0x07 /* Day of Month */
+#define TODC_TYPE_DS1693_DOW 0x06 /* Day of Week */
+#define TODC_TYPE_DS1693_HOURS 0x04
+#define TODC_TYPE_DS1693_MINUTES 0x02
+#define TODC_TYPE_DS1693_SECONDS 0x00
+#define TODC_TYPE_DS1693_CNTL_B 0x0b
+#define TODC_TYPE_DS1693_CNTL_A 0x0a
+#define TODC_TYPE_DS1693_WATCHDOG 0xff
+#define TODC_TYPE_DS1693_INTERRUPTS 0xff
+#define TODC_TYPE_DS1693_ALARM_DATE 0x49
+#define TODC_TYPE_DS1693_ALARM_HOUR 0x05
+#define TODC_TYPE_DS1693_ALARM_MINUTES 0x03
+#define TODC_TYPE_DS1693_ALARM_SECONDS 0x01
+#define TODC_TYPE_DS1693_CENTURY 0x48
+#define TODC_TYPE_DS1693_FLAGS 0xff
+#define TODC_TYPE_DS1693_NVRAM_ADDR_REG 0
+#define TODC_TYPE_DS1693_NVRAM_DATA_REG 0
+
+#define TODC_TYPE_DS1743_NVRAM_SIZE 0x1ff8
+#define TODC_TYPE_DS1743_SW_FLAGS 0
+#define TODC_TYPE_DS1743_YEAR 0x1fff
+#define TODC_TYPE_DS1743_MONTH 0x1ffe
+#define TODC_TYPE_DS1743_DOM 0x1ffd /* Day of Month */
+#define TODC_TYPE_DS1743_DOW 0x1ffc /* Day of Week */
+#define TODC_TYPE_DS1743_HOURS 0x1ffb
+#define TODC_TYPE_DS1743_MINUTES 0x1ffa
+#define TODC_TYPE_DS1743_SECONDS 0x1ff9
+#define TODC_TYPE_DS1743_CNTL_B 0x1ff9
+#define TODC_TYPE_DS1743_CNTL_A 0x1ff8 /* control_a R/W regs */
+#define TODC_TYPE_DS1743_WATCHDOG 0x1fff
+#define TODC_TYPE_DS1743_INTERRUPTS 0x1fff
+#define TODC_TYPE_DS1743_ALARM_DATE 0x1fff
+#define TODC_TYPE_DS1743_ALARM_HOUR 0x1fff
+#define TODC_TYPE_DS1743_ALARM_MINUTES 0x1fff
+#define TODC_TYPE_DS1743_ALARM_SECONDS 0x1fff
+#define TODC_TYPE_DS1743_CENTURY 0x1ff8
+#define TODC_TYPE_DS1743_FLAGS 0x1fff
+#define TODC_TYPE_DS1743_NVRAM_ADDR_REG 0
+#define TODC_TYPE_DS1743_NVRAM_DATA_REG 0
+
+#define TODC_TYPE_DS1746_NVRAM_SIZE 0x1fff8
+#define TODC_TYPE_DS1746_SW_FLAGS 0
+#define TODC_TYPE_DS1746_YEAR 0x1ffff
+#define TODC_TYPE_DS1746_MONTH 0x1fffe
+#define TODC_TYPE_DS1746_DOM 0x1fffd /* Day of Month */
+#define TODC_TYPE_DS1746_DOW 0x1fffc /* Day of Week */
+#define TODC_TYPE_DS1746_HOURS 0x1fffb
+#define TODC_TYPE_DS1746_MINUTES 0x1fffa
+#define TODC_TYPE_DS1746_SECONDS 0x1fff9
+#define TODC_TYPE_DS1746_CNTL_B 0x1fff9
+#define TODC_TYPE_DS1746_CNTL_A 0x1fff8 /* control_a R/W regs */
+#define TODC_TYPE_DS1746_WATCHDOG 0x00000
+#define TODC_TYPE_DS1746_INTERRUPTS 0x00000
+#define TODC_TYPE_DS1746_ALARM_DATE 0x00000
+#define TODC_TYPE_DS1746_ALARM_HOUR 0x00000
+#define TODC_TYPE_DS1746_ALARM_MINUTES 0x00000
+#define TODC_TYPE_DS1746_ALARM_SECONDS 0x00000
+#define TODC_TYPE_DS1746_CENTURY 0x00000
+#define TODC_TYPE_DS1746_FLAGS 0x00000
+#define TODC_TYPE_DS1746_NVRAM_ADDR_REG 0
+#define TODC_TYPE_DS1746_NVRAM_DATA_REG 0
+
+#define TODC_TYPE_DS1747_NVRAM_SIZE 0x7fff8
+#define TODC_TYPE_DS1747_SW_FLAGS 0
+#define TODC_TYPE_DS1747_YEAR 0x7ffff
+#define TODC_TYPE_DS1747_MONTH 0x7fffe
+#define TODC_TYPE_DS1747_DOM 0x7fffd /* Day of Month */
+#define TODC_TYPE_DS1747_DOW 0x7fffc /* Day of Week */
+#define TODC_TYPE_DS1747_HOURS 0x7fffb
+#define TODC_TYPE_DS1747_MINUTES 0x7fffa
+#define TODC_TYPE_DS1747_SECONDS 0x7fff9
+#define TODC_TYPE_DS1747_CNTL_B 0x7fff9
+#define TODC_TYPE_DS1747_CNTL_A 0x7fff8 /* control_a R/W regs */
+#define TODC_TYPE_DS1747_WATCHDOG 0x00000
+#define TODC_TYPE_DS1747_INTERRUPTS 0x00000
+#define TODC_TYPE_DS1747_ALARM_DATE 0x00000
+#define TODC_TYPE_DS1747_ALARM_HOUR 0x00000
+#define TODC_TYPE_DS1747_ALARM_MINUTES 0x00000
+#define TODC_TYPE_DS1747_ALARM_SECONDS 0x00000
+#define TODC_TYPE_DS1747_CENTURY 0x00000
+#define TODC_TYPE_DS1747_FLAGS 0x00000
+#define TODC_TYPE_DS1747_NVRAM_ADDR_REG 0
+#define TODC_TYPE_DS1747_NVRAM_DATA_REG 0
+
+#define TODC_TYPE_DS17285_NVRAM_SIZE (0x1000-0x80) /* 4Kx8 NVRAM (minus RTC regs) */
+#define TODC_TYPE_DS17285_SW_FLAGS TODC_FLAG_2_LEVEL_NVRAM
+#define TODC_TYPE_DS17285_SECONDS (TODC_TYPE_DS17285_NVRAM_SIZE + 0x00)
+#define TODC_TYPE_DS17285_ALARM_SECONDS (TODC_TYPE_DS17285_NVRAM_SIZE + 0x01)
+#define TODC_TYPE_DS17285_MINUTES (TODC_TYPE_DS17285_NVRAM_SIZE + 0x02)
+#define TODC_TYPE_DS17285_ALARM_MINUTES (TODC_TYPE_DS17285_NVRAM_SIZE + 0x03)
+#define TODC_TYPE_DS17285_HOURS (TODC_TYPE_DS17285_NVRAM_SIZE + 0x04)
+#define TODC_TYPE_DS17285_ALARM_HOUR (TODC_TYPE_DS17285_NVRAM_SIZE + 0x05)
+#define TODC_TYPE_DS17285_DOW (TODC_TYPE_DS17285_NVRAM_SIZE + 0x06)
+#define TODC_TYPE_DS17285_DOM (TODC_TYPE_DS17285_NVRAM_SIZE + 0x07)
+#define TODC_TYPE_DS17285_MONTH (TODC_TYPE_DS17285_NVRAM_SIZE + 0x08)
+#define TODC_TYPE_DS17285_YEAR (TODC_TYPE_DS17285_NVRAM_SIZE + 0x09)
+#define TODC_TYPE_DS17285_CNTL_A (TODC_TYPE_DS17285_NVRAM_SIZE + 0x0A)
+#define TODC_TYPE_DS17285_CNTL_B (TODC_TYPE_DS17285_NVRAM_SIZE + 0x0B)
+#define TODC_TYPE_DS17285_CNTL_C (TODC_TYPE_DS17285_NVRAM_SIZE + 0x0C)
+#define TODC_TYPE_DS17285_CNTL_D (TODC_TYPE_DS17285_NVRAM_SIZE + 0x0D)
+#define TODC_TYPE_DS17285_WATCHDOG 0
+#define TODC_TYPE_DS17285_INTERRUPTS 0
+#define TODC_TYPE_DS17285_ALARM_DATE 0
+#define TODC_TYPE_DS17285_CENTURY 0
+#define TODC_TYPE_DS17285_FLAGS 0
+#define TODC_TYPE_DS17285_NVRAM_ADDR_REG 0x50
+#define TODC_TYPE_DS17285_NVRAM_DATA_REG 0x53
+
+#define TODC_TYPE_MC146818_NVRAM_SIZE 0 /* XXXX */
+#define TODC_TYPE_MC146818_SW_FLAGS 0
+#define TODC_TYPE_MC146818_YEAR 0x09
+#define TODC_TYPE_MC146818_MONTH 0x08
+#define TODC_TYPE_MC146818_DOM 0x07 /* Day of Month */
+#define TODC_TYPE_MC146818_DOW 0x06 /* Day of Week */
+#define TODC_TYPE_MC146818_HOURS 0x04
+#define TODC_TYPE_MC146818_MINUTES 0x02
+#define TODC_TYPE_MC146818_SECONDS 0x00
+#define TODC_TYPE_MC146818_CNTL_B 0x0a
+#define TODC_TYPE_MC146818_CNTL_A 0x0b /* control_a R/W regs */
+#define TODC_TYPE_MC146818_WATCHDOG 0
+#define TODC_TYPE_MC146818_INTERRUPTS 0x0c
+#define TODC_TYPE_MC146818_ALARM_DATE 0xff
+#define TODC_TYPE_MC146818_ALARM_HOUR 0x05
+#define TODC_TYPE_MC146818_ALARM_MINUTES 0x03
+#define TODC_TYPE_MC146818_ALARM_SECONDS 0x01
+#define TODC_TYPE_MC146818_CENTURY 0xff
+#define TODC_TYPE_MC146818_FLAGS 0xff
+#define TODC_TYPE_MC146818_NVRAM_ADDR_REG 0
+#define TODC_TYPE_MC146818_NVRAM_DATA_REG 0
+
+#define TODC_TYPE_PC97307_NVRAM_SIZE 0 /* No NVRAM? */
+#define TODC_TYPE_PC97307_SW_FLAGS 0
+#define TODC_TYPE_PC97307_YEAR 0x09
+#define TODC_TYPE_PC97307_MONTH 0x08
+#define TODC_TYPE_PC97307_DOM 0x07 /* Day of Month */
+#define TODC_TYPE_PC97307_DOW 0x06 /* Day of Week */
+#define TODC_TYPE_PC97307_HOURS 0x04
+#define TODC_TYPE_PC97307_MINUTES 0x02
+#define TODC_TYPE_PC97307_SECONDS 0x00
+#define TODC_TYPE_PC97307_CNTL_B 0x0a
+#define TODC_TYPE_PC97307_CNTL_A 0x0b /* control_a R/W regs */
+#define TODC_TYPE_PC97307_WATCHDOG 0x0c
+#define TODC_TYPE_PC97307_INTERRUPTS 0x0d
+#define TODC_TYPE_PC97307_ALARM_DATE 0xff
+#define TODC_TYPE_PC97307_ALARM_HOUR 0x05
+#define TODC_TYPE_PC97307_ALARM_MINUTES 0x03
+#define TODC_TYPE_PC97307_ALARM_SECONDS 0x01
+#define TODC_TYPE_PC97307_CENTURY 0xff
+#define TODC_TYPE_PC97307_FLAGS 0xff
+#define TODC_TYPE_PC97307_NVRAM_ADDR_REG 0
+#define TODC_TYPE_PC97307_NVRAM_DATA_REG 0
+
+/*
+ * Define macros to allocate and init the todc_info_t table that will
+ * be used by the todc_time.c routines.
+ */
+#define TODC_ALLOC() \
+ static todc_info_t todc_info_alloc; \
+ todc_info_t *todc_info = &todc_info_alloc;
+
+#define TODC_INIT(clock_type, as0, as1, data, bits) { \
+ todc_info->rtc_type = clock_type; \
+ \
+ todc_info->nvram_as0 = (unsigned int)(as0); \
+ todc_info->nvram_as1 = (unsigned int)(as1); \
+ todc_info->nvram_data = (unsigned int)(data); \
+ \
+ todc_info->as0_bits = (bits); \
+ \
+ todc_info->nvram_size = clock_type ##_NVRAM_SIZE; \
+ todc_info->sw_flags = clock_type ##_SW_FLAGS; \
+ \
+ todc_info->year = clock_type ##_YEAR; \
+ todc_info->month = clock_type ##_MONTH; \
+ todc_info->day_of_month = clock_type ##_DOM; \
+ todc_info->day_of_week = clock_type ##_DOW; \
+ todc_info->hours = clock_type ##_HOURS; \
+ todc_info->minutes = clock_type ##_MINUTES; \
+ todc_info->seconds = clock_type ##_SECONDS; \
+ todc_info->control_b = clock_type ##_CNTL_B; \
+ todc_info->control_a = clock_type ##_CNTL_A; \
+ todc_info->watchdog = clock_type ##_WATCHDOG; \
+ todc_info->interrupts = clock_type ##_INTERRUPTS; \
+ todc_info->alarm_date = clock_type ##_ALARM_DATE; \
+ todc_info->alarm_hour = clock_type ##_ALARM_HOUR; \
+ todc_info->alarm_minutes = clock_type ##_ALARM_MINUTES; \
+ todc_info->alarm_seconds = clock_type ##_ALARM_SECONDS; \
+ todc_info->century = clock_type ##_CENTURY; \
+ todc_info->flags = clock_type ##_FLAGS; \
+ \
+ todc_info->nvram_addr_reg = clock_type ##_NVRAM_ADDR_REG; \
+ todc_info->nvram_data_reg = clock_type ##_NVRAM_DATA_REG; \
+}
+
+extern todc_info_t *todc_info;
+
+unsigned char todc_direct_read_val(int addr);
+void todc_direct_write_val(int addr, unsigned char val);
+unsigned char todc_m48txx_read_val(int addr);
+void todc_m48txx_write_val(int addr, unsigned char val);
+unsigned char todc_mc146818_read_val(int addr);
+void todc_mc146818_write_val(int addr, unsigned char val);
+
+long todc_time_init(void);
+void todc_get_rtc_time(struct rtc_time *);
+int todc_set_rtc_time(struct rtc_time *);
+void todc_calibrate_decr(void);
+
+#endif /* __PPC_KERNEL_TODC_H */
^ permalink raw reply related
* Re: [linux-pm] release early... powermac g5 suspend to disk
From: Pavel Machek @ 2006-06-28 21:42 UTC (permalink / raw)
To: Johannes Berg; +Cc: linuxppc-dev list, linux-pm
In-Reply-To: <1151057810.7608.25.camel@localhost>
Hi!
> Wow. 2 days and a mostly destroyed XFS filesystem (it's still running
> but I better not touch some directories or it goes belly up, xfs_repair
> craps out too) I actually suspended my quad powermac a few times.
Congratulations! Hehe, you have nice testcase for xfs now :-).
[ext2 is the filesystem you proably want to use while hacking such code].
> Half of the time I'll be told by the softlockup watchdog that it locked
> up, but sometimes it actually works, that is, it suspends and resumes.
>
> Issues: I don't save MPIC state. Hence, anything that is compiled in as
> modules will no longer get IRQs after resume. Like USB on my system. So
> I only ohci_hcd and ehci_hcd before suspend, reload later (from a
> script) and I can still use the keyboard after ;)
>
> Same goes for tg3 even though it is built-in. Well, I held off looking
> at the MPIC because Ben said he was rewriting the whole interrupt stuff
> anyway.
>
> Other issues: yeah, this is extremely ugly. If you like your machine,
> don't take a look.
I like my machine. I'll take a look anyway ;-). It is not _that_
bad... at least it is short :).
Pavel
> --- linux-2.6-git.orig/kernel/power/snapshot.c 2006-06-23 11:37:23.433885225 +0200
> +++ linux-2.6-git/kernel/power/snapshot.c 2006-06-23 11:39:03.352985945 +0200
> @@ -177,7 +177,13 @@
> return 0;
>
> page = pfn_to_page(pfn);
> +/*
> + I currently mark the physical memory that we reserve
> + and _don't_ map for kernel access as Nosave so we won't
> + try to save it... Not sure what to do.
> +
> BUG_ON(PageReserved(page) && PageNosave(page));
> +*/
I believe this is gone in -git kernels for some other reasons.
Pavel
--
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
^ permalink raw reply
* Re: [PATCH 6/7] net: Add QE UCC Gigabit Ethernet driver
From: Andrew Morton @ 2006-06-28 21:51 UTC (permalink / raw)
To: Li Yang-r58472
Cc: netdev, linux-kernel, linuxppc-dev, gridish, jgarzik, Hanjin.Chu
In-Reply-To: <9FCDBA58F226D911B202000BDBAD467306E04FD7@zch01exm40.ap.freescale.net>
Li Yang-r58472 <LeoLi@freescale.com> wrote:
>
> This is a gigabit Ethernet driver for Freescale QE(QUICC ENGINE) SOC. QE can be found on PowerQUICC II pro family.
>
>
>
> diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
> index bdaaad8..ebbb218 100644
> --- a/drivers/net/Kconfig
> +++ b/drivers/net/Kconfig
> @@ -2189,6 +2189,33 @@ config GFAR_NAPI
> bool "NAPI Support"
> depends on GIANFAR
>
> +config UCC_GETH
> + tristate "Freescale QE UCC GETH"
> + depends on QUICC_ENGINE
Opinions vary, but it can be useful if drivers such as this are compilable
on common architectures (ie: x86). That way, lots of people end up
compiling it and problems (generally simple ones) can be fixed for you.
Plus it's much less likely that someone will break your driver by accident.
Then again, it'll cause people to build a driver which they cannot possibly
use..
> # link order important here
> #
> diff --git a/drivers/net/ucc_geth.c b/drivers/net/ucc_geth.c
> new file mode 100644
> index 0000000..a7be2eb
> --- /dev/null
> +++ b/drivers/net/ucc_geth.c
>
> ...
>
> +#include <asm/uaccess.h>
> +#include <asm/irq.h>
> +#include <asm/io.h>
> +#include <asm/immap_qe.h>
> +#include <asm/qe.h>
> +
> +#include <asm/ucc.h>
> +#include <asm/ucc_fast.h>
Well that rather rules out the x86 option.
> +
> +static ucc_geth_info_t ugeth_primary_info = {
> + .uf_info = {
> + .bd_mem_part = MEM_PART_SYSTEM,
> + .brkpt_support = 0,
> + .grant_support = 0,
> + .tsa = 0,
> + .cdp = 0,
> + .cds = 0,
> + .ctsp = 0,
> + .ctss = 0,
> + .tci = 0,
> + .txsy = 0,
> + .rtsm = UCC_FAST_SEND_IDLES_BETWEEN_FRAMES,
> + .revd = 0,
> + .rsyn = 0,
Note that all the `.foo = 0' lines aren't needed.
> + .l2qt = {0, 0, 0, 0, 0, 0, 0, 0},
> + .l3qt = {0, 0, 0, 0, 0, 0, 0, 0,
> + 0, 0, 0, 0, 0, 0, 0, 0,
> + 0, 0, 0, 0, 0, 0, 0, 0,
> + 0, 0, 0, 0, 0, 0, 0, 0,
> + 0, 0, 0, 0, 0, 0, 0, 0,
> + 0, 0, 0, 0, 0, 0, 0, 0,
> + 0, 0, 0, 0, 0, 0, 0, 0,
> + 0, 0, 0, 0, 0, 0, 0, 0},
> + .vtagtable = {0, 0, 0, 0, 0, 0, 0, 0},
> + .iphoffset = {0, 0, 0, 0, 0, 0, 0, 0},
In fact I'd be inclined to remove them - the chances of keeping this table
in sync with the actual struct definition seem low.
> +
> +#ifdef DEBUG
> +static void mem_disp(u8 * addr, int size)
> +{
> + u8 *i;
> + int size16Aling = (size >> 4) << 4;
> + int size4Aling = (size >> 2) << 2;
> + int notAlign = 0;
> + if (size % 16)
> + notAlign = 1;
> +
> + for (i = addr; (u32) i < (u32) addr + size16Aling; i += 16)
> + printk("0x%08x: %08x %08x %08x %08x\r\n",
> + (u32) i,
> + *((u32 *) (i)),
> + *((u32 *) (i + 4)),
> + *((u32 *) (i + 8)), *((u32 *) (i + 12)));
> + if (notAlign == 1)
> + printk("0x%08x: ", (u32) i);
> + for (; (u32) i < (u32) addr + size4Aling; i += 4)
> + printk("%08x ", *((u32 *) (i)));
> + for (; (u32) i < (u32) addr + size; i++)
> + printk("%02x", *((u8 *) (i)));
> + if (notAlign == 1)
> + printk("\r\n");
> +}
> +#endif /* DEBUG */
This is very non-64-bit.
> +#ifdef CONFIG_UGETH_FILTERING
> +static void enqueue(struct list_head *node, struct list_head *lh)
> +{
> + unsigned long flags;
> +
> + local_irq_save(flags);
> + list_add_tail(node, lh);
> + local_irq_restore(flags);
> +}
> +#endif /* CONFIG_UGETH_FILTERING */
And local_irq_save() is very non-SMP (isn't it?)
> +static struct list_head *dequeue(struct list_head *lh)
> +{
> + unsigned long flags;
> +
> + local_irq_save(flags);
> + if (!list_empty(lh)) {
> + struct list_head *node = lh->next;
> + list_del(node);
> + local_irq_restore(flags);
> + return node;
> + } else {
> + local_irq_restore(flags);
> + return NULL;
> + }
> +}
Unless this really really really never will run on SMP, it'd be better to
use spin_lock_irqsave() here. That's equivalent on !SMP.
> +static struct sk_buff *get_new_skb(ucc_geth_private_t * ugeth, u8 * bd)
Preferred coding style is
static struct sk_buff *get_new_skb(ucc_geth_private_t *ugeth, u8 *bd)
> +{
> + struct sk_buff *skb = NULL;
> + unsigned int timeout = SKB_ALLOC_TIMEOUT;
> +
> + /* We have to allocate the skb, so keep trying till we succeed */
> + while ((!skb) && timeout--)
> + skb =
> + dev_alloc_skb(ugeth->ug_info->uf_info.max_rx_buf_length +
> + UCC_GETH_RX_DATA_BUF_ALIGNMENT);
This is pretty pointless. If the first allocation attempt failed then
for-sure the rest of them will fail too. All it does is waste CPU.
> +
> +static int rx_bd_buffer_set(ucc_geth_private_t * ugeth, u8 rxQ)
> +{
> + u8 *bd;
> + u32 bd_status;
> + struct sk_buff *skb;
> + int i;
> +
> + if (!ugeth) {
> + ugeth_err("%s: No handle passed.", __FUNCTION__);
> + return -EINVAL;
> + }
Presumably, this can't happen. Suggest you remove this code and let the
thing oops if it does happen.
> +static int fill_init_enet_entries(ucc_geth_private_t * ugeth,
> + volatile u32 * p_start,
> + u8 num_entries,
> + u32 thread_size,
> + u32 thread_alignment,
> + qe_risc_allocation_e risc,
> + int skip_page_for_first_entry)
> +{
> + u32 init_enet_offset;
> + u8 i;
> + int snum;
> +
> + if (!ugeth || !ugeth->uccf) {
> + ugeth_err("%s: No handle passed.", __FUNCTION__);
> + return -EINVAL;
> + }
Ditto.
> +#ifdef CONFIG_UGETH_FILTERING
> +static enet_addr_container_t *get_enet_addr_container(void)
> +{
> + enet_addr_container_t *enet_addr_cont;
> +
> + /* allocate memory */
> + enet_addr_cont =
> + (enet_addr_container_t *) kmalloc(sizeof(enet_addr_container_t),
Unneeded typecast.
> +
> +static inline int compare_addr(enet_addr_t * addr1, enet_addr_t * addr2)
> +{
> + return strncmp((char *)addr1, (char *)addr2,
> + ENET_NUM_OCTETS_PER_ADDRESS);
> +}
Shouldn't this use memcmp()? strncmp() will stop at 0x00.
> + mem_disp((u8 *) & ugeth->p_thread_data_tx[i],
> + sizeof(ucc_geth_thread_data_tx_t));
We should have a kernel-wide printk-a-block-of-memory-out library function,
but we don't.
> +static int init_check_frame_length_mode(int length_check,
> + volatile u32 * maccfg2_register)
> +{
> + u32 value = 0;
Unneeded initialisation (lots of places).
> + value = in_be32(maccfg2_register);
> +/* Called every time the controller might need to be made
> + * aware of new link state. The PHY code conveys this
> + * information through variables in the ugeth structure, and this
> + * function converts those variables into the appropriate
> + * register values, and can bring down the device if needed.
> + */
> +#include <linux/mii.h>
This is a funny place to be including a header file. Better to put it at
the top of the .c file.
[remainder skipped - it's a big driver]
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