* Re: update: consolidated flat device tree code
From: Hollis Blanchard @ 2006-08-18 0:29 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Pantelis Antoniou, Sachin P. Sant, linuxppc-embedded
In-Reply-To: <1155860626.27466.126.camel@basalt.austin.ibm.com>
On Thu, 2006-08-17 at 19:23 -0500, Hollis Blanchard wrote:
> Changes:
> - converted some ints to "unsigned", since gcc was generating warnings
> and negative lengths don't make sense in the flat data structure.
> - added ft_set_prop(), which doesn't yet resize properties but will in
> the future.
> - added an explicit copyright statement.
>
> Still haven't looked to merge Matt's changes (because I'm busy, the
> current code works for me, and they haven't been accepted in u-boot
> yet).
>
> Current users: Xen
> Future users: Mark's Linux bootwrapper code
> Potential users: kexec, u-boot
Forgot to add that dtc itself is a potential user of this code.
--
Hollis Blanchard
IBM Linux Technology Center
^ permalink raw reply
* update: consolidated flat device tree code
From: Hollis Blanchard @ 2006-08-18 0:23 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Pantelis Antoniou, Sachin P. Sant, linuxppc-embedded
[-- Attachment #1: Type: text/plain, Size: 558 bytes --]
Changes:
- converted some ints to "unsigned", since gcc was generating warnings
and negative lengths don't make sense in the flat data structure.
- added ft_set_prop(), which doesn't yet resize properties but will in
the future.
- added an explicit copyright statement.
Still haven't looked to merge Matt's changes (because I'm busy, the
current code works for me, and they haven't been accepted in u-boot
yet).
Current users: Xen
Future users: Mark's Linux bootwrapper code
Potential users: kexec, u-boot
--
Hollis Blanchard
IBM Linux Technology Center
[-- Attachment #2: ft_build.c --]
[-- Type: text/x-csrc, Size: 12119 bytes --]
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
*
* Copyright Pantelis Antoniou 2006
* Copyright (C) IBM Corporation 2006
*
* Authors: Pantelis Antoniou <pantelis@embeddedalley.com>
* Hollis Blanchard <hollisb@us.ibm.com>
*/
#include <stddef.h>
#include <string.h>
#include <stdio.h>
#include <asm/errno.h>
#include "ft_build.h"
#define _ALIGN(addr,size) (((addr)+(size)-1)&(~((size)-1)))
static void ft_put_word(struct ft_cxt *cxt, u32 v)
{
if (cxt->overflow) /* do nothing */
return;
/* check for overflow */
if (cxt->p + 4 > cxt->pstr) {
cxt->overflow = 1;
return;
}
*(u32 *) cxt->p = cpu_to_be32(v);
cxt->p += 4;
}
static inline void ft_put_bin(struct ft_cxt *cxt, const void *data, int sz)
{
char *p;
if (cxt->overflow) /* do nothing */
return;
/* next pointer pos */
p = (char *) _ALIGN((unsigned long)cxt->p + sz, 4);
/* check for overflow */
if (p > cxt->pstr) {
cxt->overflow = 1;
return;
}
memcpy(cxt->p, data, sz);
if ((sz & 3) != 0)
memset(cxt->p + sz, 0, 4 - (sz & 3));
cxt->p = p;
}
void ft_begin_node(struct ft_cxt *cxt, const char *name)
{
ft_put_word(cxt, OF_DT_BEGIN_NODE);
ft_put_bin(cxt, name, strlen(name) + 1);
}
void ft_end_node(struct ft_cxt *cxt)
{
ft_put_word(cxt, OF_DT_END_NODE);
}
void ft_nop(struct ft_cxt *cxt)
{
ft_put_word(cxt, OF_DT_NOP);
}
static int lookup_string(struct ft_cxt *cxt, const char *name)
{
char *p;
p = cxt->pstr;
while (p < cxt->pstr_begin) {
if (strcmp(p, (char *)name) == 0)
return p - cxt->p_begin;
p += strlen(p) + 1;
}
return -1;
}
void ft_prop(struct ft_cxt *cxt, const char *name,
const void *data, unsigned int sz)
{
int len, off;
if (cxt->overflow)
return;
len = strlen(name) + 1;
off = lookup_string(cxt, name);
if (off == -1) {
/* check if we have space */
if (cxt->p + 12 + sz + len > cxt->pstr) {
cxt->overflow = 1;
return;
}
cxt->pstr -= len;
memcpy(cxt->pstr, name, len);
off = cxt->pstr - cxt->p_begin;
}
/* now put offset from beginning of *STRUCTURE* */
/* will be fixed up at the end */
ft_put_word(cxt, OF_DT_PROP);
ft_put_word(cxt, sz);
ft_put_word(cxt, off);
ft_put_bin(cxt, data, sz);
}
void ft_prop_str(struct ft_cxt *cxt, const char *name, const char *str)
{
ft_prop(cxt, name, str, strlen(str) + 1);
}
void ft_prop_int(struct ft_cxt *cxt, const char *name, unsigned int val)
{
u32 v = cpu_to_be32((u32) val);
ft_prop(cxt, name, &v, 4);
}
/* start construction of the flat OF tree */
void ft_begin(struct ft_cxt *cxt, void *blob, unsigned int max_size)
{
struct boot_param_header *bph = blob;
u32 off;
/* clear the cxt */
memset(cxt, 0, sizeof(*cxt));
cxt->bph = bph;
cxt->max_size = max_size;
/* zero everything in the header area */
memset(bph, 0, sizeof(*bph));
bph->magic = cpu_to_be32(OF_DT_HEADER);
bph->version = cpu_to_be32(0x10);
bph->last_comp_version = cpu_to_be32(0x10);
/* start pointers */
cxt->pres_begin = (char *) _ALIGN((unsigned long)(bph + 1), 8);
cxt->pres = cxt->pres_begin;
off = (unsigned long)cxt->pres_begin - (unsigned long)bph;
bph->off_mem_rsvmap = cpu_to_be32(off);
((u64 *) cxt->pres)[0] = 0; /* phys = 0, size = 0, terminate */
((u64 *) cxt->pres)[1] = 0;
cxt->p_anchor = cxt->pres + 16; /* over the terminator */
}
/* add a reserver physical area to the rsvmap */
void ft_add_rsvmap(struct ft_cxt *cxt, u64 physaddr, u64 size)
{
((u64 *) cxt->pres)[0] = cpu_to_be64(physaddr); /* phys = 0, size = 0, terminate */
((u64 *) cxt->pres)[1] = cpu_to_be64(size);
cxt->pres += 18; /* advance */
((u64 *) cxt->pres)[0] = 0; /* phys = 0, size = 0, terminate */
((u64 *) cxt->pres)[1] = 0;
/* keep track of size */
cxt->res_size = cxt->pres + 16 - cxt->pres_begin;
cxt->p_anchor = cxt->pres + 16; /* over the terminator */
}
void ft_begin_tree(struct ft_cxt *cxt)
{
cxt->p_begin = cxt->p_anchor;
cxt->pstr_begin = (char *)cxt->bph + cxt->max_size; /* point at the end */
cxt->p = cxt->p_begin;
cxt->pstr = cxt->pstr_begin;
}
int ft_end_tree(struct ft_cxt *cxt)
{
struct boot_param_header *bph = cxt->bph;
int off, sz, sz1;
u32 tag, v;
char *p;
ft_put_word(cxt, OF_DT_END);
if (cxt->overflow)
return -ENOMEM;
/* size of the areas */
cxt->struct_size = cxt->p - cxt->p_begin;
cxt->strings_size = cxt->pstr_begin - cxt->pstr;
/* the offset we must move */
off = (cxt->pstr_begin - cxt->p_begin) - cxt->strings_size;
/* the new strings start */
cxt->pstr_begin = cxt->p_begin + cxt->struct_size;
/* move the whole string area */
memmove(cxt->pstr_begin, cxt->pstr, cxt->strings_size);
/* now perform the fixup of the strings */
p = cxt->p_begin;
while ((tag = be32_to_cpu(*(u32 *) p)) != OF_DT_END) {
p += 4;
if (tag == OF_DT_BEGIN_NODE) {
p = (char *) _ALIGN((unsigned long)p + strlen(p) + 1, 4);
continue;
}
if (tag == OF_DT_END_NODE || tag == OF_DT_NOP)
continue;
if (tag != OF_DT_PROP)
return -EINVAL;
sz = be32_to_cpu(*(u32 *) p);
p += 4;
v = be32_to_cpu(*(u32 *) p);
v -= off;
*(u32 *) p = cpu_to_be32(v); /* move down */
p += 4;
p = (char *) _ALIGN((unsigned long)p + sz, 4);
}
/* fix sizes */
p = (char *)cxt->bph;
sz = (cxt->pstr_begin + cxt->strings_size) - p;
sz1 = _ALIGN(sz, 16); /* align at 16 bytes */
if (sz != sz1)
memset(p + sz, 0, sz1 - sz);
bph->totalsize = cpu_to_be32(sz1);
bph->off_dt_struct = cpu_to_be32(cxt->p_begin - p);
bph->off_dt_strings = cpu_to_be32(cxt->pstr_begin - p);
/* the new strings start */
cxt->pstr_begin = cxt->p_begin + cxt->struct_size;
cxt->pstr = cxt->pstr_begin + cxt->strings_size;
return 0;
}
/**********************************************************************/
static inline int isprint(int c)
{
return c >= 0x20 && c <= 0x7e;
}
static int is_printable_string(const void *data, int len)
{
const char *s = data;
const char *ss;
/* zero length is not */
if (len == 0)
return 0;
/* must terminate with zero */
if (s[len - 1] != '\0')
return 0;
ss = s;
while (*s && isprint(*s))
s++;
/* not zero, or not done yet */
if (*s != '\0' || (s + 1 - ss) < len)
return 0;
return 1;
}
static void print_data(const void *data, int len)
{
int i;
const char *s;
/* no data, don't print */
if (len == 0)
return;
if (is_printable_string(data, len)) {
printf(" = \"%s\"", (char *)data);
return;
}
switch (len) {
case 1: /* byte */
printf(" = <0x%02x>", (*(char *) data) & 0xff);
break;
case 2: /* half-word */
printf(" = <0x%04x>", be16_to_cpu(*(u16 *) data) & 0xffff);
break;
case 4: /* word */
printf(" = <0x%08x>", be32_to_cpu(*(u32 *) data) & 0xffffffffU);
break;
case 8: /* double-word */
printf(" = <0x%16llx>", be64_to_cpu(*(u64 *) data));
break;
default: /* anything else... hexdump */
printf(" = [");
for (i = 0, s = data; i < len; i++)
printf("%02x%s", s[i], i < len - 1 ? " " : "");
printf("]");
break;
}
}
void ft_dump_blob(const void *bphp)
{
const struct boot_param_header *bph = bphp;
const u64 *p_rsvmap = (const u64 *)
((const char *)bph + be32_to_cpu(bph->off_mem_rsvmap));
const u32 *p_struct = (const u32 *)
((const char *)bph + be32_to_cpu(bph->off_dt_struct));
const u32 *p_strings = (const u32 *)
((const char *)bph + be32_to_cpu(bph->off_dt_strings));
u32 tag;
const u32 *p;
const char *s, *t;
int depth, sz, shift;
int i;
u64 addr, size;
if (be32_to_cpu(bph->magic) != OF_DT_HEADER) {
/* not valid tree */
return;
}
depth = 0;
shift = 4;
for (i = 0;; i++) {
addr = be64_to_cpu(p_rsvmap[i * 2]);
size = be64_to_cpu(p_rsvmap[i * 2 + 1]);
if (addr == 0 && size == 0)
break;
printf("/memreserve/ 0x%llx 0x%llx;\n", addr, size);
}
p = p_struct;
while ((tag = be32_to_cpu(*p++)) != OF_DT_END) {
/* printf("tag: 0x%08x (%d)\n", tag, p - p_struct); */
if (tag == OF_DT_BEGIN_NODE) {
s = (const char *)p;
p = (u32 *) _ALIGN((unsigned long)p + strlen(s) + 1, 4);
printf("%*s%s {\n", depth * shift, "", s);
depth++;
continue;
}
if (tag == OF_DT_END_NODE) {
depth--;
printf("%*s};\n", depth * shift, "");
continue;
}
if (tag == OF_DT_NOP) {
printf("%*s[NOP]\n", depth * shift, "");
continue;
}
if (tag != OF_DT_PROP) {
fprintf(stderr, "%*s ** Unknown tag 0x%08x\n",
depth * shift, "", tag);
break;
}
sz = be32_to_cpu(*p++);
s = (const char *)p_strings + be32_to_cpu(*p++);
t = (const char *)p;
p = (const u32 *)_ALIGN((unsigned long)p + sz, 4);
printf("%*s%s", depth * shift, "", s);
print_data(t, sz);
printf(";\n");
}
}
void ft_backtrack_node(struct ft_cxt *cxt)
{
if (be32_to_cpu(*(u32 *) (cxt->p - 4)) != OF_DT_END_NODE)
return; /* XXX only for node */
cxt->p -= 4;
}
/* note that the root node of the blob is "peeled" off */
void ft_merge_blob(struct ft_cxt *cxt, void *blob)
{
struct boot_param_header *bph = (struct boot_param_header *)blob;
u32 *p_struct = (u32 *) ((char *)bph + be32_to_cpu(bph->off_dt_struct));
u32 *p_strings =
(u32 *) ((char *)bph + be32_to_cpu(bph->off_dt_strings));
u32 tag, *p;
char *s, *t;
int depth, sz;
if (be32_to_cpu(*(u32 *) (cxt->p - 4)) != OF_DT_END_NODE)
return; /* XXX only for node */
cxt->p -= 4;
depth = 0;
p = p_struct;
while ((tag = be32_to_cpu(*p++)) != OF_DT_END) {
/* printf("tag: 0x%08x (%d) - %d\n", tag, p - p_struct, depth); */
if (tag == OF_DT_BEGIN_NODE) {
s = (char *)p;
p = (u32 *) _ALIGN((unsigned long)p + strlen(s) + 1, 4);
if (depth++ > 0)
ft_begin_node(cxt, s);
continue;
}
if (tag == OF_DT_END_NODE) {
ft_end_node(cxt);
if (--depth == 0)
break;
continue;
}
if (tag == OF_DT_NOP)
continue;
if (tag != OF_DT_PROP)
break;
sz = be32_to_cpu(*p++);
s = (char *)p_strings + be32_to_cpu(*p++);
t = (char *)p;
p = (u32 *) _ALIGN((unsigned long)p + sz, 4);
ft_prop(cxt, s, t, sz);
}
}
void *ft_get_prop(void *bphp, const char *propname, unsigned int *szp)
{
struct boot_param_header *bph = bphp;
u32 *p_struct =
(u32 *) ((char *)bph + be32_to_cpu(bph->off_dt_struct));
u32 *p_strings =
(u32 *) ((char *)bph + be32_to_cpu(bph->off_dt_strings));
u32 version = be32_to_cpu(bph->version);
u32 tag;
u32 *p;
char *s, *t;
char *ss;
int sz;
static char path[256], prop[256];
path[0] = '\0';
p = p_struct;
while ((tag = be32_to_cpu(*p++)) != OF_DT_END) {
if (tag == OF_DT_BEGIN_NODE) {
s = (char *)p;
p = (u32 *) _ALIGN((unsigned long)p + strlen(s) +
1, 4);
strcat(path, s);
strcat(path, "/");
continue;
}
if (tag == OF_DT_END_NODE) {
path[strlen(path) - 1] = '\0';
ss = strrchr(path, '/');
if (ss != NULL)
ss[1] = '\0';
continue;
}
if (tag == OF_DT_NOP)
continue;
if (tag != OF_DT_PROP)
break;
sz = be32_to_cpu(*p++);
s = (char *)p_strings + be32_to_cpu(*p++);
if (version < 0x10 && sz >= 8)
p = (u32 *) _ALIGN((unsigned long)p, 8);
t = (char *)p;
p = (u32 *) _ALIGN((unsigned long)p + sz, 4);
strcpy(prop, path);
strcat(prop, s);
if (strcmp(prop, propname) == 0) {
*szp = sz;
return t;
}
}
return NULL;
}
int ft_set_prop(void *bphp, const char *propname, const void *val,
unsigned int len)
{
void *prop;
unsigned int proplen;
prop = ft_get_prop(bphp, propname, &proplen);
if (prop == NULL)
return -ENOENT;
if (proplen != len)
/* XXX to be removed when property resize is supported */
return -EINVAL;
memcpy(prop, val, len);
return 0;
}
[-- Attachment #3: ft_build.h --]
[-- Type: text/x-chdr, Size: 4373 bytes --]
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
*/
#ifndef FT_BUILD_H
#define FT_BUILD_H
#include <endian.h>
typedef unsigned short u16;
typedef unsigned int u32;
typedef unsigned long long u64;
static inline u16 swab16(u16 x)
{
return (((u16)(x) & (u16)0x00ffU) << 8) |
(((u16)(x) & (u16)0xff00U) >> 8);
}
static inline u32 swab32(u32 x)
{
return (((u32)(x) & (u32)0x000000ffUL) << 24) |
(((u32)(x) & (u32)0x0000ff00UL) << 8) |
(((u32)(x) & (u32)0x00ff0000UL) >> 8) |
(((u32)(x) & (u32)0xff000000UL) >> 24);
}
static inline u64 swab64(u64 x)
{
return (u64)(((u64)(x) & (u64)0x00000000000000ffULL) << 56) |
(u64)(((u64)(x) & (u64)0x000000000000ff00ULL) << 40) |
(u64)(((u64)(x) & (u64)0x0000000000ff0000ULL) << 24) |
(u64)(((u64)(x) & (u64)0x00000000ff000000ULL) << 8) |
(u64)(((u64)(x) & (u64)0x000000ff00000000ULL) >> 8) |
(u64)(((u64)(x) & (u64)0x0000ff0000000000ULL) >> 24) |
(u64)(((u64)(x) & (u64)0x00ff000000000000ULL) >> 40) |
(u64)(((u64)(x) & (u64)0xff00000000000000ULL) >> 56);
}
#if __BYTE_ORDER == __LITTLE_ENDIAN
#define cpu_to_be16(x) swab16(x)
#define be16_to_cpu(x) swab16(x)
#define cpu_to_be32(x) swab32(x)
#define be32_to_cpu(x) swab32(x)
#define cpu_to_be64(x) swab64(x)
#define be64_to_cpu(x) swab64(x)
#else
#define cpu_to_be16(x) (x)
#define be16_to_cpu(x) (x)
#define cpu_to_be32(x) (x)
#define be32_to_cpu(x) (x)
#define cpu_to_be64(x) (x)
#define be64_to_cpu(x) (x)
#endif
/* Definitions used by the flattened device tree */
#define OF_DT_HEADER 0xd00dfeed /* marker */
#define OF_DT_BEGIN_NODE 0x1 /* Start of node, full name */
#define OF_DT_END_NODE 0x2 /* End node */
#define OF_DT_PROP 0x3 /* Property: name off, size, content */
#define OF_DT_NOP 0x4 /* nop */
#define OF_DT_END 0x9
#define OF_DT_VERSION 0x10
struct boot_param_header {
u32 magic; /* magic word OF_DT_HEADER */
u32 totalsize; /* total size of DT block */
u32 off_dt_struct; /* offset to structure */
u32 off_dt_strings; /* offset to strings */
u32 off_mem_rsvmap; /* offset to memory reserve map */
u32 version; /* format version */
u32 last_comp_version; /* last compatible version */
/* version 2 fields below */
u32 boot_cpuid_phys; /* Physical CPU id we're booting on */
/* version 3 fields below */
u32 dt_strings_size; /* size of the DT strings block */
};
struct ft_cxt {
struct boot_param_header *bph;
int max_size; /* maximum size of tree */
int overflow; /* set when this happens */
char *p, *pstr, *pres; /* running pointers */
char *p_begin, *pstr_begin, *pres_begin; /* starting pointers */
char *p_anchor; /* start of constructed area */
int struct_size, strings_size, res_size;
};
void ft_begin_node(struct ft_cxt *cxt, const char *name);
void ft_end_node(struct ft_cxt *cxt);
void ft_begin_tree(struct ft_cxt *cxt);
int ft_end_tree(struct ft_cxt *cxt);
void ft_nop(struct ft_cxt *cxt);
void ft_prop(struct ft_cxt *cxt, const char *name,
const void *data, unsigned int sz);
void ft_prop_str(struct ft_cxt *cxt, const char *name, const char *str);
void ft_prop_int(struct ft_cxt *cxt, const char *name, unsigned int val);
void ft_begin(struct ft_cxt *cxt, void *blob, unsigned int max_size);
void ft_add_rsvmap(struct ft_cxt *cxt, u64 physaddr, u64 size);
void ft_dump_blob(const void *bphp);
void ft_merge_blob(struct ft_cxt *cxt, void *blob);
void *ft_get_prop(void *bphp, const char *propname, unsigned int *szp);
int ft_set_prop(void *bphp, const char *propname, const void *val,
unsigned int len);
#endif
^ permalink raw reply
* Re: [PATCH] Directly reference i8259@4d0 nodes in mpc8641_hpcn.dts.
From: Benjamin Herrenschmidt @ 2006-08-18 0:09 UTC (permalink / raw)
To: Jon Loeliger; +Cc: linuxppc-dev@ozlabs.org
In-Reply-To: <1155849609.10054.175.camel@cashmere.sps.mot.com>
On Thu, 2006-08-17 at 16:20 -0500, Jon Loeliger wrote:
> Rather than using some hand-coded linux,phandle
> node references, use DTC's direct node refs ability
> and let it manage the phandle names instead.
Not 100% sure here but can't we use a label and do &label rather than
having to copy the full path every time ? Would make things easier :) If
not, that's probably something to add to dtc...
Cheers,
Ben.
> Signed-off-by: Jon Loeliger <jdl@freescale.com>
> ---
>
> On Thu, 2006-08-17 at 13:51, Hollis Blanchard wrote:
> > Doesn't the device tree compiler add linux,phandle properties as needed?
> > In this case that would be when the node is referenced by a
> > "<&/foo/bar/i8259@4d0>" property.
> >
> > On Thu, 2006-08-17 at 12:24 -0500, Jon Loeliger wrote:
> > > Add 'linux,phandle' entry to i8259@4d0 node.
> > >
> > > Signed-off-by: Zhang Wei <wei.zhang@freescale.com>
> > > Signed-off-by: Jon Loeliger <jdl@freescale.com>
> > > ---
>
> Paul,
>
> If you think this is better, please apply this patch
> instead of my previous patch with the subject line:
>
> Patch] Fix the mpc8641_hpcn.dts file.
>
> Thanks,
> jdl
>
>
> arch/powerpc/boot/dts/mpc8641_hpcn.dts | 121 ++++++++++++++++----------------
> 1 files changed, 60 insertions(+), 61 deletions(-)
>
> diff --git a/arch/powerpc/boot/dts/mpc8641_hpcn.dts b/arch/powerpc/boot/dts/mpc8641_hpcn.dts
> index e832a88..49d85a5 100644
> --- a/arch/powerpc/boot/dts/mpc8641_hpcn.dts
> +++ b/arch/powerpc/boot/dts/mpc8641_hpcn.dts
> @@ -32,7 +32,6 @@
> bus-frequency = <0>; // From uboot
> clock-frequency = <0>; // From uboot
> 32-bit;
> - linux,boot-cpu;
> };
> PowerPC,8641@1 {
> device_type = "cpu";
> @@ -202,95 +201,95 @@
> interrupt-map-mask = <f800 0 0 7>;
> interrupt-map = <
> /* IDSEL 0x11 */
> - 8800 0 0 1 4d0 3 2
> - 8800 0 0 2 4d0 4 2
> - 8800 0 0 3 4d0 5 2
> - 8800 0 0 4 4d0 6 2
> + 8800 0 0 1 &/soc8641@f8000000/pci@8000/i8259@4d0 3 2
> + 8800 0 0 2 &/soc8641@f8000000/pci@8000/i8259@4d0 4 2
> + 8800 0 0 3 &/soc8641@f8000000/pci@8000/i8259@4d0 5 2
> + 8800 0 0 4 &/soc8641@f8000000/pci@8000/i8259@4d0 6 2
>
> /* IDSEL 0x12 */
> - 9000 0 0 1 4d0 4 2
> - 9000 0 0 2 4d0 5 2
> - 9000 0 0 3 4d0 6 2
> - 9000 0 0 4 4d0 3 2
> + 9000 0 0 1 &/soc8641@f8000000/pci@8000/i8259@4d0 4 2
> + 9000 0 0 2 &/soc8641@f8000000/pci@8000/i8259@4d0 5 2
> + 9000 0 0 3 &/soc8641@f8000000/pci@8000/i8259@4d0 6 2
> + 9000 0 0 4 &/soc8641@f8000000/pci@8000/i8259@4d0 3 2
>
> /* IDSEL 0x13 */
> - 9800 0 0 1 4d0 0 0
> - 9800 0 0 2 4d0 0 0
> - 9800 0 0 3 4d0 0 0
> - 9800 0 0 4 4d0 0 0
> + 9800 0 0 1 &/soc8641@f8000000/pci@8000/i8259@4d0 0 0
> + 9800 0 0 2 &/soc8641@f8000000/pci@8000/i8259@4d0 0 0
> + 9800 0 0 3 &/soc8641@f8000000/pci@8000/i8259@4d0 0 0
> + 9800 0 0 4 &/soc8641@f8000000/pci@8000/i8259@4d0 0 0
>
> /* IDSEL 0x14 */
> - a000 0 0 1 4d0 0 0
> - a000 0 0 2 4d0 0 0
> - a000 0 0 3 4d0 0 0
> - a000 0 0 4 4d0 0 0
> + a000 0 0 1 &/soc8641@f8000000/pci@8000/i8259@4d0 0 0
> + a000 0 0 2 &/soc8641@f8000000/pci@8000/i8259@4d0 0 0
> + a000 0 0 3 &/soc8641@f8000000/pci@8000/i8259@4d0 0 0
> + a000 0 0 4 &/soc8641@f8000000/pci@8000/i8259@4d0 0 0
>
> /* IDSEL 0x15 */
> - a800 0 0 1 4d0 0 0
> - a800 0 0 2 4d0 0 0
> - a800 0 0 3 4d0 0 0
> - a800 0 0 4 4d0 0 0
> + a800 0 0 1 &/soc8641@f8000000/pci@8000/i8259@4d0 0 0
> + a800 0 0 2 &/soc8641@f8000000/pci@8000/i8259@4d0 0 0
> + a800 0 0 3 &/soc8641@f8000000/pci@8000/i8259@4d0 0 0
> + a800 0 0 4 &/soc8641@f8000000/pci@8000/i8259@4d0 0 0
>
> /* IDSEL 0x16 */
> - b000 0 0 1 4d0 0 0
> - b000 0 0 2 4d0 0 0
> - b000 0 0 3 4d0 0 0
> - b000 0 0 4 4d0 0 0
> + b000 0 0 1 &/soc8641@f8000000/pci@8000/i8259@4d0 0 0
> + b000 0 0 2 &/soc8641@f8000000/pci@8000/i8259@4d0 0 0
> + b000 0 0 3 &/soc8641@f8000000/pci@8000/i8259@4d0 0 0
> + b000 0 0 4 &/soc8641@f8000000/pci@8000/i8259@4d0 0 0
>
> /* IDSEL 0x17 */
> - b800 0 0 1 4d0 0 0
> - b800 0 0 2 4d0 0 0
> - b800 0 0 3 4d0 0 0
> - b800 0 0 4 4d0 0 0
> + b800 0 0 1 &/soc8641@f8000000/pci@8000/i8259@4d0 0 0
> + b800 0 0 2 &/soc8641@f8000000/pci@8000/i8259@4d0 0 0
> + b800 0 0 3 &/soc8641@f8000000/pci@8000/i8259@4d0 0 0
> + b800 0 0 4 &/soc8641@f8000000/pci@8000/i8259@4d0 0 0
>
> /* IDSEL 0x18 */
> - c000 0 0 1 4d0 0 0
> - c000 0 0 2 4d0 0 0
> - c000 0 0 3 4d0 0 0
> - c000 0 0 4 4d0 0 0
> + c000 0 0 1 &/soc8641@f8000000/pci@8000/i8259@4d0 0 0
> + c000 0 0 2 &/soc8641@f8000000/pci@8000/i8259@4d0 0 0
> + c000 0 0 3 &/soc8641@f8000000/pci@8000/i8259@4d0 0 0
> + c000 0 0 4 &/soc8641@f8000000/pci@8000/i8259@4d0 0 0
>
> /* IDSEL 0x19 */
> - c800 0 0 1 4d0 0 0
> - c800 0 0 2 4d0 0 0
> - c800 0 0 3 4d0 0 0
> - c800 0 0 4 4d0 0 0
> + c800 0 0 1 &/soc8641@f8000000/pci@8000/i8259@4d0 0 0
> + c800 0 0 2 &/soc8641@f8000000/pci@8000/i8259@4d0 0 0
> + c800 0 0 3 &/soc8641@f8000000/pci@8000/i8259@4d0 0 0
> + c800 0 0 4 &/soc8641@f8000000/pci@8000/i8259@4d0 0 0
>
> /* IDSEL 0x1a */
> - d000 0 0 1 4d0 6 2
> - d000 0 0 2 4d0 3 2
> - d000 0 0 3 4d0 4 2
> - d000 0 0 4 4d0 5 2
> + d000 0 0 1 &/soc8641@f8000000/pci@8000/i8259@4d0 6 2
> + d000 0 0 2 &/soc8641@f8000000/pci@8000/i8259@4d0 3 2
> + d000 0 0 3 &/soc8641@f8000000/pci@8000/i8259@4d0 4 2
> + d000 0 0 4 &/soc8641@f8000000/pci@8000/i8259@4d0 5 2
>
>
> /* IDSEL 0x1b */
> - d800 0 0 1 4d0 5 2
> - d800 0 0 2 4d0 0 0
> - d800 0 0 3 4d0 0 0
> - d800 0 0 4 4d0 0 0
> + d800 0 0 1 &/soc8641@f8000000/pci@8000/i8259@4d0 5 2
> + d800 0 0 2 &/soc8641@f8000000/pci@8000/i8259@4d0 0 0
> + d800 0 0 3 &/soc8641@f8000000/pci@8000/i8259@4d0 0 0
> + d800 0 0 4 &/soc8641@f8000000/pci@8000/i8259@4d0 0 0
>
> /* IDSEL 0x1c */
> - e000 0 0 1 4d0 9 2
> - e000 0 0 2 4d0 a 2
> - e000 0 0 3 4d0 c 2
> - e000 0 0 4 4d0 7 2
> + e000 0 0 1 &/soc8641@f8000000/pci@8000/i8259@4d0 9 2
> + e000 0 0 2 &/soc8641@f8000000/pci@8000/i8259@4d0 a 2
> + e000 0 0 3 &/soc8641@f8000000/pci@8000/i8259@4d0 c 2
> + e000 0 0 4 &/soc8641@f8000000/pci@8000/i8259@4d0 7 2
>
> /* IDSEL 0x1d */
> - e800 0 0 1 4d0 9 2
> - e800 0 0 2 4d0 a 2
> - e800 0 0 3 4d0 b 2
> - e800 0 0 4 4d0 0 0
> + e800 0 0 1 &/soc8641@f8000000/pci@8000/i8259@4d0 9 2
> + e800 0 0 2 &/soc8641@f8000000/pci@8000/i8259@4d0 a 2
> + e800 0 0 3 &/soc8641@f8000000/pci@8000/i8259@4d0 b 2
> + e800 0 0 4 &/soc8641@f8000000/pci@8000/i8259@4d0 0 0
>
> /* IDSEL 0x1e */
> - f000 0 0 1 4d0 c 2
> - f000 0 0 2 4d0 0 0
> - f000 0 0 3 4d0 0 0
> - f000 0 0 4 4d0 0 0
> + f000 0 0 1 &/soc8641@f8000000/pci@8000/i8259@4d0 c 2
> + f000 0 0 2 &/soc8641@f8000000/pci@8000/i8259@4d0 0 0
> + f000 0 0 3 &/soc8641@f8000000/pci@8000/i8259@4d0 0 0
> + f000 0 0 4 &/soc8641@f8000000/pci@8000/i8259@4d0 0 0
>
> /* IDSEL 0x1f */
> - f800 0 0 1 4d0 6 2
> - f800 0 0 2 4d0 0 0
> - f800 0 0 3 4d0 0 0
> - f800 0 0 4 4d0 0 0
> + f800 0 0 1 &/soc8641@f8000000/pci@8000/i8259@4d0 6 2
> + f800 0 0 2 &/soc8641@f8000000/pci@8000/i8259@4d0 0 0
> + f800 0 0 3 &/soc8641@f8000000/pci@8000/i8259@4d0 0 0
> + f800 0 0 4 &/soc8641@f8000000/pci@8000/i8259@4d0 0 0
> >;
> i8259@4d0 {
> clock-frequency = <0>;
^ permalink raw reply
* Re: Outstanding Patches Ping
From: Paul Mackerras @ 2006-08-18 0:07 UTC (permalink / raw)
To: Jon Loeliger; +Cc: linuxppc-dev@ozlabs.org
In-Reply-To: <E1GDhtO-0002Mk-2j@jdl.com>
Jon Loeliger writes:
> > > - 08/09 Offer PCI as a CONFIG choice for PPC_86xx
> >
> > I'll push it to powerpc.git (to go in 2.6.19) shortly, unless you
> > particularly want it and your "Allow MPC8641 HPCN to build with
> > CONFIG_PCI disabled too" patches in 2.6.18.
>
> My preference would be to have them both in 18 if possible.
The "Allow MPC8641 HPCN to build with CONFIG_PCI disabled too" patch
depends on your "Rewrite the PPC 86xx IRQ handling to use Flat Device
Tree" which isn't in the queue for 2.6.18, and doesn't apply for
2.6.18 since it depends on the constifying of get_property.
Paul.
^ permalink raw reply
* Re: latest git: compile error: arch/powerpc/kernel/built-in.o
From: Michael Ellerman @ 2006-08-18 0:01 UTC (permalink / raw)
To: Wolfgang Pfeiffer; +Cc: linux-ppc, Michael Ellerman, Paul Mackerras
In-Reply-To: <20060817120653.GA3440@localhost>
On Thu, 2006-08-17 at 14:06 +0200, Wolfgang Pfeiffer wrote:
> On Thu, Aug 17, 2006 at 04:41:58PM +1000, Paul Mackerras wrote:
> > Wolfgang Pfeiffer writes:
> >
> > > Strange tho' - for me at least - that these patches from about 5 weeks (!)
> > > ago still don't seem to have made it into the current git tree ...
> >
> > 5 weeks ago was a particularly bad time for patches trying to get into
> > the git tree, since I was on vacation and then travelling to OLS. :)
>
> [ ... ]
>
> Michael, Paul, and everyone else being involved:
>
> My apologies for my perhaps too strong wording when I was complaining
> about the delay ... I didn't mean the words as ugly as they actually
> might read ...
No worries, thanks for catching the error and reporting it.
cheers
--
Michael Ellerman
IBM OzLabs
email: michaele@au.ibm.com
stime: ellerman@au1.ibm.com
notes: Michael Ellerman/Australia/IBM
phone: +61 2 6212 1183 (tie line 70 21183)
We do not inherit the earth from our ancestors,
we borrow it from our children. - S.M.A.R.T Person
^ permalink raw reply
* Re: [PATCH 02/13] IB/ehca: includes
From: Arnd Bergmann @ 2006-08-17 23:44 UTC (permalink / raw)
To: linuxppc-dev; +Cc: linux-kernel, openib-general, RAISCH, HNGUYEN, MEDER
In-Reply-To: <20068171311.X1v1Q4Gk1v3wd7qJ@cisco.com>
T24gVGh1cnNkYXkgMTcgQXVndXN0IDIwMDYgMjI6MTEsIFJvbGFuZCBEcmVpZXIgd3JvdGU6Cj4g
KyAqIElTX0VERUJfT04gLSBDaGVja3MgaWYgZGVidWcgaXMgb24gZm9yIHRoZSBnaXZlbiBsZXZl
bC4KPiArICovCj4gKyNkZWZpbmUgSVNfRURFQl9PTihsZXZlbCkgXAo+ICsoKGVoY2FfZWRlYl9m
aWx0ZXIobGV2ZWwsIEVERUJfSURfVE9fVTMyKERFQl9QUkVGSVgpLCBfX0xJTkVfXykgJiBcCj4g
KyCgMHgxMDAwMDAwMDBMKSA9PSAwKQo+ICsKPiArI2RlZmluZSBFREVCX1BfR0VORVJJQyhsZXZl
bCxpZHN0cmluZyxmb3JtYXQsYXJncy4uLikgXAo+ICtkbyB7IFwKPiAroKCgoKCgoHU2NCBlaGNh
X2VkZWJfZmlsdGVycmVzdWx0ID2goKCgoKCgoKCgoKCgoKCgoKCgoKCgoKCgoKCgoKCgoKCgoKBc
Cj4gK6CgoKCgoKCgoKCgoKCgoGVoY2FfZWRlYl9maWx0ZXIobGV2ZWwsIEVERUJfSURfVE9fVTMy
KERFQl9QUkVGSVgpLCBfX0xJTkVfXyk7XAo+ICugoKCgoKCgaWYgKChlaGNhX2VkZWJfZmlsdGVy
cmVzdWx0ICYgMHgxMDAwMDAwMDBMKSA9PSAwKaCgoKCgoKCgoKCgoKCgoFwKPiAroKCgoKCgoKCg
oKCgoKCgcHJpbnRrKCJQVSUwNHggJTA4eDolcyAiIGlkc3RyaW5nICIgImZvcm1hdCAiXG4iLKCg
oKCgoKBcCj4gK6CgoKCgoKCgoKCgoKCgoCCgIKAgoCBnZXRfcGFjYSgpLT5wYWNhX2luZGV4LCAo
dTMyKShlaGNhX2VkZWJfZmlsdGVycmVzdWx0KSwgXAo+ICugoKCgoKCgoKCgoKCgoKAgoCCgIKAg
X19mdW5jX18sIKAjI2FyZ3MpO6CgoKCgoKCgoKCgoKCgoKCgoKCgoKCgoKCgoKCgoFwKPiArfSB3
aGlsZSAoMSA9PSAwKQoKVGhlc2UgbWFjcm9zIGFyZSByZXNwb25zaWJsZSBmb3IgNjElIG9mIHRo
ZSBvYmplY3QgY29kZSBzaXplIG9mIHlvdXIgbW9kdWxlLgpUaGlzIGlzIGNvbXBsZXRlbHkgaW5z
YW5lLiBQbGVhc2UgZ2V0IHJpZCBvZiB0aGF0IGNyYXAgZW50aXJlbHkgYW5kIHJlcGxhY2UKaXQg
d2l0aCBkZXZfaW5mby9kZXZfZGJnL2Rldl93YXJuIGNhbGxzIHdoZXJlIGFwcHJvcHJpYXRlIQoK
CUFybmQgPD48Cg==
^ permalink raw reply
* Re: [PATCH 13/13] IB/ehca: makefiles/kconfig
From: Arnd Bergmann @ 2006-08-17 23:34 UTC (permalink / raw)
To: linuxppc-dev; +Cc: linux-kernel, openib-general, RAISCH, HNGUYEN, MEDER
In-Reply-To: <20068171311.WDFBWw0F6z9B3Qes@cisco.com>
On Thursday 17 August 2006 22:11, Roland Dreier wrote:
> +
> +CFLAGS += -DEHCA_USE_HCALL -DEHCA_USE_HCALL_KERNEL
This seems really pointless, since you're always defining these
macros to the same value.
Just drop the CFLAGS and remove the code that depends on them
being different.
Arnd <><
^ permalink raw reply
* Re: [PATCH 6/6] bootwrapper: Add support for the sandpoint platform
From: Guennadi Liakhovetski @ 2006-08-17 23:19 UTC (permalink / raw)
To: Mark A. Greer; +Cc: linuxppc-dev
In-Reply-To: <Pine.LNX.4.60.0608172352220.8228@poirot.grange>
On Fri, 18 Aug 2006, Guennadi Liakhovetski wrote:
> On Thu, 17 Aug 2006, Mark A. Greer wrote:
>
> > Depends on what you mean by "__boot__". This is the code needed to
> > prepare things--the flat dev tree in this case--so that the kernel
> > can boot when running the DINK firmware on a sandpoint.
>
> ...after getting some vitamins on irc and re-reading some emails, I
> finally realised what the stuff under boot is for. Expect more confusion
> from me:-)
Ok, I think, now I have an idea what all these wrappers are about:
we want to be able to boot linux from a number of different environments:
OF
various firmwares / boot ROMs / bootloaders with very different
capabilities of running foreign code and different calling conventions
"native" Linux bootloaders like u-Boot, etc.
kexec
...
and the chosen approach is to have a kernel proper common to all these
possibilities, and "wrappers". These wrappers are boot-method and board
specific, are distributed with the kernel, located under
arch/powerpc/boot, get linked with the kernel proper, fdt, with various
compression possibilities...
Have I got it right now? One of the reasons of me having problems to
understand this is that on ARM we just say "to boot kernel you have to
have MMU switched off, registers must contain this and that, you have to
prepare a list of ATAGs, copy the kernel to a certain address, and jump to
it. If you don't do that you cannot run Linux on your system":-)
Thanks
Guennadi
---
Guennadi Liakhovetski
^ permalink raw reply
* Broken Firewire 400/SCSI on ppc Powerbook5,8
From: Wolfgang Pfeiffer @ 2006-08-17 23:03 UTC (permalink / raw)
To: linux1394-devel; +Cc: linuxppc-dev, Stefan Richter
Hi All
Short version first:
The SCSI/FW routines seem to work like a charm with a LSILogic Model/
SYM13FW500-Disk on my old Macintosh titanium-IV laptop, with exactly
the same relatively fresh git-kernel that does not work on the
PowerBook5,8. That is I compiled the kernel on the Apple Powerbook5,8
and installed it on both machines.
SCSI/FW didn't work ever on the new PowerBook5,8.
I'll give you first some error messages for the failing FW disk,
and at the end of this mail you'll find links to technical
documentation for the 2 failng machines (Powerbook5,8 and FW board/disk)
First I load the drivers with this little script:
------------------------------------------
#!/bin/sh -x
/bin/sh -n /home/shorty/scripts/scsi.start.sh && \
modprobe raw1394 && \
modprobe ieee1394 disable_irm=0 disable_nodemgr=1 && \
modprobe ohci1394 && \
modprobe eth1394 && \
modprobe sbp2 max_speed=3 workarounds=0x1 serialize_io=0 && \
sleep 4 && \
chown root.shorty /dev/raw1394
-------------------------------------------
After doing the latter:
-------------------------------
$ sh kernel-factory/git.08102006/linux-2.6/scripts/ver_linux
If some fields are empty or look unusual you may have an old version.
Compare to the current minimal requirements in Documentation/Changes.
Linux debby1-6 2.6.18-rc4-060811-dirty #1 Fri Aug 11 00:16:22 CEST 2006 ppc GNU/
Linux
Gnu C 4.1.2
Gnu make 3.81
binutils 2.17
util-linux 2.12r
mount 2.12r
module-init-tools 3.2.2
e2fsprogs 1.39
pcmcia-cs 3.2.8
Linux C Library 2.3.6
Dynamic linker (ldd) 2.3.6
Procps 3.2.7
Net-tools 1.60
Console-tools 0.2.3
Sh-utils 5.97
udev 093
Modules Loaded sbp2 eth1394 ohci1394 raw1394 ieee1394 bluetooth radeon d
rm nfs nfsd exportfs lockd nfs_acl sunrpc ipv6 therm_adt746x sr_mod cpufreq_powe
rsave cpufreq_performance scsi_mod apm_emu joydev usblp appletouch usbhid snd_ao
a_codec_onyx snd_aoa_fabric_layout snd_aoa pcmcia firmware_class evdev snd_aoa_i
2sbus snd_pcm_oss snd_mixer_oss snd_pcm snd_timer snd_page_alloc snd ide_cd ohci
_hcd yenta_socket sungem sungem_phy cdrom ehci_hcd usbcore rsrc_nonstatic pcmcia
_core pmac_zilog serial_core soundcore snd_aoa_soundbus uninorth_agp agpgart i2c
_powermac
------------------------------
After loading the drivers above the failing kernel says this about the
via FW attached disk:
-----------------------------------
Aug 18 00:24:03 debby1-6 kernel: [38907.611119] ieee1394: Initialized config rom entry `ip1394'
Aug 18 00:24:03 debby1-6 kernel: [38907.628475] ieee1394: raw1394: /dev/raw1394 device initialized
Aug 18 00:24:03 debby1-6 kernel: [38907.692766] PM: Adding info for ieee1394:fw-host0
Aug 18 00:24:03 debby1-6 kernel: [38907.764726] ohci1394: fw-host0: OHCI-1394 1.0 (PCI): IRQ=[40] MMIO=[f5000000-f50007ff] Max Packet=[4096] IR/IT contexts=[8/8]
Aug 18 00:24:03 debby1-6 kernel: [38907.912614] eth1394: eth2: IEEE-1394 IPv4 over 1394 Ethernet (fw-host0)
Aug 18 00:24:04 debby1-6 kernel: [38909.170610] ieee1394: The root node is not cycle master capable; selecting a new root node and resetting...
Aug 18 00:24:05 debby1-6 kernel: [38910.425599] ieee1394: Error parsing configrom for node 0-00:1023
Aug 18 00:24:05 debby1-6 kernel: [38910.425992] PM: Adding info for ieee1394:001451fffe3148be
Aug 18 00:24:05 debby1-6 kernel: [38910.426064] ieee1394: Host added: ID:BUS[0-02:1023] GUID[001451fffe3148be]
Aug 18 00:24:05 debby1-6 kernel: [38910.426209] PM: Adding info for ieee1394:001451fffe3148be-0
-----------------------------------
And gscanbus says this for:
"Unknown
Linux - ohci1394":
--------------------------
SelfID Info
-----------
Physical ID: 2
Link active: Yes
Gap Count: 63
PHY Speed: Unknown
PHY Delay: <=144ns
IRM Capable: Yes
Power Class: -1W
Port 0: Not connected
Port 1: Connected to child node
Port 2: Not connected
Init. reset: Yes
CSR ROM Info
------------
GUID: 0x001451FFFE3148BE
Node Capabilities: 0x000083C0
Vendor ID: 0x00001451
Unit Spec ID: 0x0000005E
Unit SW Version: 0x00000001
Model ID: 0x00000000
Nr. Textual Leafes: 1
Vendor: Unknown
Textual Leafes:
Linux - ohci1394
AV/C Subunits
-------------
N/A
-------------------------
And this for "S400 unknown":
---------------------------------
SelfID Info
-----------
Physical ID: 1
Link active: No
Gap Count: 63
PHY Speed: S400
PHY Delay: <=144ns
IRM Capable: No
Power Class: -1W
Port 0: Connected to parent node
Port 1: Not connected
Port 2: Connected to child node
Init. reset: No
CSR ROM Info
------------
GUID: 0x0000000000000000
Node Capabilities: 0x00000000
Vendor ID: 0x00000000
Unit Spec ID: 0x00000000
Unit SW Version: 0x00000000
Model ID: 0x00000000
Nr. Textual Leafes: 0
Vendor: (null)
Textual Leafes:
AV/C Subunits
-------------
N/A
-----------------------------------
I haven't enabled for the current kernel IEEE1394_VERBOSEDEBUG. I
could recompile it and enable this option if necessary, to provide
more verbose kernel logs.
As to the documentation for the 2 machines, where all this is
happening, first the computer, then the FW board/disk:
*** 1:
The computer:
$ cat /proc/cpuinfo
processor : 0
cpu : 7447A, altivec supported
clock : 1666.666000MHz
revision : 0.5 (pvr 8003 0105)
bogomips : 33.15
timebase : 8320000
platform : PowerMac
machine : PowerBook5,8
motherboard : PowerBook5,8 MacRISC3 Power Macintosh
detected as : 287 (PowerBook G4 15")
pmac flags : 00000019
L2 cache : 512K unified
pmac-generation : NewWorld
Some Apple technical documentation for the Firewire 400/800 ports is here:
http://developer.apple.com/documentation/Hardware/Developer_Notes/Macintosh_CPUs-G4/15inchPowerBookG4/3Input-Output/chapter_4_section_3.html#//apple_ref/doc/uid/TP40003165-CH207-TPXREF105
Start page - if the link above is only a temporary one - seems being
here:
http://developer.apple.com/documentation/Hardware/Developer_Notes/Macintosh_CPUs-G4/15inchPowerBookG4/index.html
*** 2:
The Firewire disk/board:
I don't have reasonable technical docs for the FW board. Here's a
picture of the package for the disk enclosure, with some technical data:
http://www.geocities.com/wolfgangpfeiffer/scsi.case.specs.jpg
This seems to be the board for the disk, inside the enclosure:
Vendor: LSILogic Model: SYM13FW500-Disk Rev: 1.00
I have pictures for the board here:
Disk on the board, top side:
http://wolfgangpfeiffer.com/scsi.top.jpg
Bottomside, with wirings:
http://wolfgangpfeiffer.com/scsi.focussed.flash.jpg
[444 KB]
Similar:
http://www.wolfgangpfeiffer.com/scsi.disk.2.scaled.jpg
[276 KB]
Wirings side again:
http://www.wolfgangpfeiffer.com/scsi.focussed.flash.jpg
[444 KB]
Please let me know if you need more information
Thanks for your time.
Wolfgang
--
Wolfgang Pfeiffer: /ICQ: 286585973/ + + + /AIM: crashinglinux/
http://profiles.yahoo.com/wolfgangpfeiffer
Key ID: E3037113
http://keyserver.mine.nu/pks/lookup?search=0xE3037113&fingerprint=on
^ permalink raw reply
* Re: [PATCH 6/6] bootwrapper: Add support for the sandpoint platform
From: Guennadi Liakhovetski @ 2006-08-17 22:39 UTC (permalink / raw)
To: Mark A. Greer; +Cc: linuxppc-dev
In-Reply-To: <20060817211353.GA1402@mag.az.mvista.com>
On Thu, 17 Aug 2006, Mark A. Greer wrote:
> Depends on what you mean by "__boot__". This is the code needed to
> prepare things--the flat dev tree in this case--so that the kernel
> can boot when running the DINK firmware on a sandpoint.
...after getting some vitamins on irc and re-reading some emails, I
finally realised what the stuff under boot is for. Expect more confusion
from me:-)
Thanks
Guennadi
---
Guennadi Liakhovetski
^ permalink raw reply
* [PATCH] Directly reference i8259@4d0 nodes in mpc8641_hpcn.dts.
From: Jon Loeliger @ 2006-08-17 21:20 UTC (permalink / raw)
To: Hollis Blanchard; +Cc: linuxppc-dev@ozlabs.org
In-Reply-To: <1155840700.27466.64.camel@basalt.austin.ibm.com>
Rather than using some hand-coded linux,phandle
node references, use DTC's direct node refs ability
and let it manage the phandle names instead.
Signed-off-by: Jon Loeliger <jdl@freescale.com>
---
On Thu, 2006-08-17 at 13:51, Hollis Blanchard wrote:
> Doesn't the device tree compiler add linux,phandle properties as needed?
> In this case that would be when the node is referenced by a
> "<&/foo/bar/i8259@4d0>" property.
>
> On Thu, 2006-08-17 at 12:24 -0500, Jon Loeliger wrote:
> > Add 'linux,phandle' entry to i8259@4d0 node.
> >
> > Signed-off-by: Zhang Wei <wei.zhang@freescale.com>
> > Signed-off-by: Jon Loeliger <jdl@freescale.com>
> > ---
Paul,
If you think this is better, please apply this patch
instead of my previous patch with the subject line:
Patch] Fix the mpc8641_hpcn.dts file.
Thanks,
jdl
arch/powerpc/boot/dts/mpc8641_hpcn.dts | 121 ++++++++++++++++----------------
1 files changed, 60 insertions(+), 61 deletions(-)
diff --git a/arch/powerpc/boot/dts/mpc8641_hpcn.dts b/arch/powerpc/boot/dts/mpc8641_hpcn.dts
index e832a88..49d85a5 100644
--- a/arch/powerpc/boot/dts/mpc8641_hpcn.dts
+++ b/arch/powerpc/boot/dts/mpc8641_hpcn.dts
@@ -32,7 +32,6 @@
bus-frequency = <0>; // From uboot
clock-frequency = <0>; // From uboot
32-bit;
- linux,boot-cpu;
};
PowerPC,8641@1 {
device_type = "cpu";
@@ -202,95 +201,95 @@
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
/* IDSEL 0x11 */
- 8800 0 0 1 4d0 3 2
- 8800 0 0 2 4d0 4 2
- 8800 0 0 3 4d0 5 2
- 8800 0 0 4 4d0 6 2
+ 8800 0 0 1 &/soc8641@f8000000/pci@8000/i8259@4d0 3 2
+ 8800 0 0 2 &/soc8641@f8000000/pci@8000/i8259@4d0 4 2
+ 8800 0 0 3 &/soc8641@f8000000/pci@8000/i8259@4d0 5 2
+ 8800 0 0 4 &/soc8641@f8000000/pci@8000/i8259@4d0 6 2
/* IDSEL 0x12 */
- 9000 0 0 1 4d0 4 2
- 9000 0 0 2 4d0 5 2
- 9000 0 0 3 4d0 6 2
- 9000 0 0 4 4d0 3 2
+ 9000 0 0 1 &/soc8641@f8000000/pci@8000/i8259@4d0 4 2
+ 9000 0 0 2 &/soc8641@f8000000/pci@8000/i8259@4d0 5 2
+ 9000 0 0 3 &/soc8641@f8000000/pci@8000/i8259@4d0 6 2
+ 9000 0 0 4 &/soc8641@f8000000/pci@8000/i8259@4d0 3 2
/* IDSEL 0x13 */
- 9800 0 0 1 4d0 0 0
- 9800 0 0 2 4d0 0 0
- 9800 0 0 3 4d0 0 0
- 9800 0 0 4 4d0 0 0
+ 9800 0 0 1 &/soc8641@f8000000/pci@8000/i8259@4d0 0 0
+ 9800 0 0 2 &/soc8641@f8000000/pci@8000/i8259@4d0 0 0
+ 9800 0 0 3 &/soc8641@f8000000/pci@8000/i8259@4d0 0 0
+ 9800 0 0 4 &/soc8641@f8000000/pci@8000/i8259@4d0 0 0
/* IDSEL 0x14 */
- a000 0 0 1 4d0 0 0
- a000 0 0 2 4d0 0 0
- a000 0 0 3 4d0 0 0
- a000 0 0 4 4d0 0 0
+ a000 0 0 1 &/soc8641@f8000000/pci@8000/i8259@4d0 0 0
+ a000 0 0 2 &/soc8641@f8000000/pci@8000/i8259@4d0 0 0
+ a000 0 0 3 &/soc8641@f8000000/pci@8000/i8259@4d0 0 0
+ a000 0 0 4 &/soc8641@f8000000/pci@8000/i8259@4d0 0 0
/* IDSEL 0x15 */
- a800 0 0 1 4d0 0 0
- a800 0 0 2 4d0 0 0
- a800 0 0 3 4d0 0 0
- a800 0 0 4 4d0 0 0
+ a800 0 0 1 &/soc8641@f8000000/pci@8000/i8259@4d0 0 0
+ a800 0 0 2 &/soc8641@f8000000/pci@8000/i8259@4d0 0 0
+ a800 0 0 3 &/soc8641@f8000000/pci@8000/i8259@4d0 0 0
+ a800 0 0 4 &/soc8641@f8000000/pci@8000/i8259@4d0 0 0
/* IDSEL 0x16 */
- b000 0 0 1 4d0 0 0
- b000 0 0 2 4d0 0 0
- b000 0 0 3 4d0 0 0
- b000 0 0 4 4d0 0 0
+ b000 0 0 1 &/soc8641@f8000000/pci@8000/i8259@4d0 0 0
+ b000 0 0 2 &/soc8641@f8000000/pci@8000/i8259@4d0 0 0
+ b000 0 0 3 &/soc8641@f8000000/pci@8000/i8259@4d0 0 0
+ b000 0 0 4 &/soc8641@f8000000/pci@8000/i8259@4d0 0 0
/* IDSEL 0x17 */
- b800 0 0 1 4d0 0 0
- b800 0 0 2 4d0 0 0
- b800 0 0 3 4d0 0 0
- b800 0 0 4 4d0 0 0
+ b800 0 0 1 &/soc8641@f8000000/pci@8000/i8259@4d0 0 0
+ b800 0 0 2 &/soc8641@f8000000/pci@8000/i8259@4d0 0 0
+ b800 0 0 3 &/soc8641@f8000000/pci@8000/i8259@4d0 0 0
+ b800 0 0 4 &/soc8641@f8000000/pci@8000/i8259@4d0 0 0
/* IDSEL 0x18 */
- c000 0 0 1 4d0 0 0
- c000 0 0 2 4d0 0 0
- c000 0 0 3 4d0 0 0
- c000 0 0 4 4d0 0 0
+ c000 0 0 1 &/soc8641@f8000000/pci@8000/i8259@4d0 0 0
+ c000 0 0 2 &/soc8641@f8000000/pci@8000/i8259@4d0 0 0
+ c000 0 0 3 &/soc8641@f8000000/pci@8000/i8259@4d0 0 0
+ c000 0 0 4 &/soc8641@f8000000/pci@8000/i8259@4d0 0 0
/* IDSEL 0x19 */
- c800 0 0 1 4d0 0 0
- c800 0 0 2 4d0 0 0
- c800 0 0 3 4d0 0 0
- c800 0 0 4 4d0 0 0
+ c800 0 0 1 &/soc8641@f8000000/pci@8000/i8259@4d0 0 0
+ c800 0 0 2 &/soc8641@f8000000/pci@8000/i8259@4d0 0 0
+ c800 0 0 3 &/soc8641@f8000000/pci@8000/i8259@4d0 0 0
+ c800 0 0 4 &/soc8641@f8000000/pci@8000/i8259@4d0 0 0
/* IDSEL 0x1a */
- d000 0 0 1 4d0 6 2
- d000 0 0 2 4d0 3 2
- d000 0 0 3 4d0 4 2
- d000 0 0 4 4d0 5 2
+ d000 0 0 1 &/soc8641@f8000000/pci@8000/i8259@4d0 6 2
+ d000 0 0 2 &/soc8641@f8000000/pci@8000/i8259@4d0 3 2
+ d000 0 0 3 &/soc8641@f8000000/pci@8000/i8259@4d0 4 2
+ d000 0 0 4 &/soc8641@f8000000/pci@8000/i8259@4d0 5 2
/* IDSEL 0x1b */
- d800 0 0 1 4d0 5 2
- d800 0 0 2 4d0 0 0
- d800 0 0 3 4d0 0 0
- d800 0 0 4 4d0 0 0
+ d800 0 0 1 &/soc8641@f8000000/pci@8000/i8259@4d0 5 2
+ d800 0 0 2 &/soc8641@f8000000/pci@8000/i8259@4d0 0 0
+ d800 0 0 3 &/soc8641@f8000000/pci@8000/i8259@4d0 0 0
+ d800 0 0 4 &/soc8641@f8000000/pci@8000/i8259@4d0 0 0
/* IDSEL 0x1c */
- e000 0 0 1 4d0 9 2
- e000 0 0 2 4d0 a 2
- e000 0 0 3 4d0 c 2
- e000 0 0 4 4d0 7 2
+ e000 0 0 1 &/soc8641@f8000000/pci@8000/i8259@4d0 9 2
+ e000 0 0 2 &/soc8641@f8000000/pci@8000/i8259@4d0 a 2
+ e000 0 0 3 &/soc8641@f8000000/pci@8000/i8259@4d0 c 2
+ e000 0 0 4 &/soc8641@f8000000/pci@8000/i8259@4d0 7 2
/* IDSEL 0x1d */
- e800 0 0 1 4d0 9 2
- e800 0 0 2 4d0 a 2
- e800 0 0 3 4d0 b 2
- e800 0 0 4 4d0 0 0
+ e800 0 0 1 &/soc8641@f8000000/pci@8000/i8259@4d0 9 2
+ e800 0 0 2 &/soc8641@f8000000/pci@8000/i8259@4d0 a 2
+ e800 0 0 3 &/soc8641@f8000000/pci@8000/i8259@4d0 b 2
+ e800 0 0 4 &/soc8641@f8000000/pci@8000/i8259@4d0 0 0
/* IDSEL 0x1e */
- f000 0 0 1 4d0 c 2
- f000 0 0 2 4d0 0 0
- f000 0 0 3 4d0 0 0
- f000 0 0 4 4d0 0 0
+ f000 0 0 1 &/soc8641@f8000000/pci@8000/i8259@4d0 c 2
+ f000 0 0 2 &/soc8641@f8000000/pci@8000/i8259@4d0 0 0
+ f000 0 0 3 &/soc8641@f8000000/pci@8000/i8259@4d0 0 0
+ f000 0 0 4 &/soc8641@f8000000/pci@8000/i8259@4d0 0 0
/* IDSEL 0x1f */
- f800 0 0 1 4d0 6 2
- f800 0 0 2 4d0 0 0
- f800 0 0 3 4d0 0 0
- f800 0 0 4 4d0 0 0
+ f800 0 0 1 &/soc8641@f8000000/pci@8000/i8259@4d0 6 2
+ f800 0 0 2 &/soc8641@f8000000/pci@8000/i8259@4d0 0 0
+ f800 0 0 3 &/soc8641@f8000000/pci@8000/i8259@4d0 0 0
+ f800 0 0 4 &/soc8641@f8000000/pci@8000/i8259@4d0 0 0
>;
i8259@4d0 {
clock-frequency = <0>;
--
2006_06_07.01.gittree_pull-dirty
^ permalink raw reply related
* Re: [PATCH 6/6] bootwrapper: Add support for the sandpoint platform
From: Mark A. Greer @ 2006-08-17 21:18 UTC (permalink / raw)
To: Mark A. Greer; +Cc: linuxppc-dev, Guennadi Liakhovetski
In-Reply-To: <20060817211353.GA1402@mag.az.mvista.com>
On Thu, Aug 17, 2006 at 02:13:53PM -0700, Mark A. Greer wrote:
> prepare things--the flat dev tree in this case--so that the kernel
> can boot when running the DINK firmware on a sandpoint.
I should rephrase this to, "so that the kernel will boot on a system
that has DINK as its firmware."
Mark
^ permalink raw reply
* Re: [PATCH 6/6] bootwrapper: Add support for the sandpoint platform
From: Mark A. Greer @ 2006-08-17 21:13 UTC (permalink / raw)
To: Guennadi Liakhovetski; +Cc: linuxppc-dev
In-Reply-To: <Pine.LNX.4.60.0608172200080.8228@poirot.grange>
On Thu, Aug 17, 2006 at 10:16:16PM +0200, Guennadi Liakhovetski wrote:
> On Wed, 19 Jul 2006, Mark A. Greer wrote:
>
> > This patch adds support for the Freescale Sandpoint platform
> > to the bootwrapper.
Hi Guennadi.
> Mark,
>
> you put sandpoint.c and mpc10x.c under boot... I don't quite understand
> your concept now: you mean this is the code needed to __boot__ sandpoint.
Depends on what you mean by "__boot__". This is the code needed to
prepare things--the flat dev tree in this case--so that the kernel
can boot when running the DINK firmware on a sandpoint.
> Ok. I can also imagine that as soon as the system is up you don't need any
> further specific code - only .init* sections. But - does this mean that
> every platform will now put its support flat under boot?
You need to read <file:Documentation/powerpc/booting-without-of.txt>.
> Or is it a
> special case? Or are there also run-time fixups that you didn't include
> with this patch-series? Also <board>_reset doesn't quite fit under boot,
Yes it does. Follow exit().
> or am I misunderstanding something?
Yes, you're missing the whole point of the patch series...
Did you read "[PATCH 0/6] bootwrapper: arch/powerpc/boot code reorg
patches"?
The intent was not to add kernel support for the sanpoint. The intent
was to solicit comments on a reorg of the bootwrapper code.
Mark
^ permalink raw reply
* Re: [PATCH 4/6] POWERPC: add support of mpc8560 eval board
From: Segher Boessenkool @ 2006-08-17 20:55 UTC (permalink / raw)
To: Andy Fleming; +Cc: linuxppc-dev, Paul Mackerras
In-Reply-To: <6A1F08CA-2FAE-4BE6-82BF-30F35053483C@freescale.com>
>> + pic@40000 {
>> + linux,phandle = <40000>;
>> + interrupt-controller;
>> + #address-cells = <0>;
>> + #interrupt-cells = <2>;
>> + reg = <40000 20100>;
>> + built-in;
>> + device_type = "mpic";
>
> This is wrong. It should be "open-pic";
Not necessarily; if not, it should have "open-pic" somewhere
in the "compatible" property though.
Best might be to have device_type = interrupt-controller,
and put "mpic,open-pic" in the "compatible" property (no
comma but a zero byte...)
Or prefix it with the name of your _exact_ interrupt controller,
even.
Segher
^ permalink raw reply
* Re: [PATCH] fix gettimeofday vs. update_gtod race
From: Nathan Lynch @ 2006-08-17 20:47 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev, Paul Mackerras
In-Reply-To: <1155774477.11312.137.camel@localhost.localdomain>
Benjamin Herrenschmidt wrote:
> On Wed, 2006-08-16 at 19:18 -0500, Nathan Lynch wrote:
>
> > No? I didn't find anything about mftb having synchronizing
> > behavior. How should we ensure that temp_varp is assigned before
> > reading the timebase?
>
> I sync an isync would be enough.
I see, thanks.
> > > I need to think about it a bit more closely but what about instead
> > > just check if tb_ticks goes negative, and if yes, just do get_tb()
> > > again ? That might be faster than having a sync in there and should
> > > still be correct.
> >
> > I did try something like that but found that a loop (i.e. multiple
> > get_tb's to "catch up") was necessary.
>
> Hrm... even with an isync ?
No, sorry, I was confusing this with a different bug (cpu
hotplug-related, separate patch for that forthcoming).
^ permalink raw reply
* Re: [openib-general] [PATCH 00/16] IB/ehca: introduction
From: Roland Dreier @ 2006-08-17 20:31 UTC (permalink / raw)
To: openib-general, linux-kernel, linuxppc-dev, RAISCH, HNGUYEN,
MEDER
In-Reply-To: <2006817139.43eVtRoa2IK8yOPl@cisco.com>
Sorry-- my patchbombing script blew up in the middle, and I didn't
restart quite correctly. But I'm pretty sure all 16 patches did make
it out, although the numbering is screwy. The correct series is:
01/16, 02/16, 00/13, 01/13, ..., 13/13
I'm not going to spam everybody and resend to all the lists, but I'm
happy to resend privately to anyone who asks, or you can clone the
git tree to get the series
git://git.kernel.org/pub/scm/linux/kernel/git/roland/infiniband.git ehca
Thanks,
Roland
^ permalink raw reply
* InfiniBand merge plans for 2.6.19
From: Roland Dreier @ 2006-08-17 20:13 UTC (permalink / raw)
To: linux-kernel, netdev, linuxppc-dev, openib-general
Here's a short summary of what I plan to merge for 2.6.19. Some of
this is already in infiniband.git[1], while some still needs to be
merged up. Highlights:
o iWARP core support[2]. This updates drivers/infiniband to work
with devices that do RDMA over IP/ethernet in addition to
InfiniBand devices. As a first user of this support, I also
plan to merge the amso1100[3] driver for Ammasso RNIC.
I will post this for review one more time after I pull it into
my git tree for last minute cleanups. But if you feel this
iWARP support should not be merged, please let me know why now.
o IBM eHCA driver, which supports IBM pSeries-specific InfiniBand
hardware. This is in the ehca branch of infiniband.git, and I
will post it for review one more time. My feeling is that more
cleanups are certainly possible, but this driver is "good
enough to merge" now and has languished out of tree for long
enough. I'm certainly happy to merge cleanup patches, though.
o mmap()ed userspace work queues for ipath. This is a
performance enhancement for QLogic/PathScale HCAs but it does
touch core stuff in minor ways. Should not be controversial.
o I also have the following minor changes queued in the
for-2.6.19 branch of infiniband.git:
Ishai Rabinovitz:
IB/srp: Add port/device attributes
James Lentini:
IB/mthca: Include the header we really want
Michael S. Tsirkin:
IB/mthca: Don't use privileged UAR for kernel access
IB/ipoib: Fix flush/start xmit race (from code review)
Roland Dreier:
IB/uverbs: Use idr_read_cq() where appropriate
IB/uverbs: Fix lockdep warning when QP is created with 2 CQs
[1] git://git.kernel.org/pub/scm/linux/kernel/git/roland/infiniband.git
[2] http://thread.gmane.org/gmane.linux.network/40903
[3] http://thread.gmane.org/gmane.linux.drivers.openib/28657
^ permalink raw reply
* [PATCH 13/13] IB/ehca: makefiles/kconfig
From: Roland Dreier @ 2006-08-17 20:11 UTC (permalink / raw)
To: openib-general, linux-kernel, linuxppc-dev; +Cc: RAISCH, HNGUYEN, MEDER
In-Reply-To: <20068171311.P1OwgyzMAlKlrkeW@cisco.com>
drivers/infiniband/Kconfig | 1 +
drivers/infiniband/Makefile | 1 +
drivers/infiniband/hw/ehca/Kconfig | 12 ++++++++++++
drivers/infiniband/hw/ehca/Makefile | 18 ++++++++++++++++++
4 files changed, 32 insertions(+), 0 deletions(-)
diff --git a/drivers/infiniband/Kconfig b/drivers/infiniband/Kconfig
index 69a53d4..fd2d528 100644
--- a/drivers/infiniband/Kconfig
+++ b/drivers/infiniband/Kconfig
@@ -36,6 +36,7 @@ config INFINIBAND_ADDR_TRANS
source "drivers/infiniband/hw/mthca/Kconfig"
source "drivers/infiniband/hw/ipath/Kconfig"
+source "drivers/infiniband/hw/ehca/Kconfig"
source "drivers/infiniband/ulp/ipoib/Kconfig"
diff --git a/drivers/infiniband/Makefile b/drivers/infiniband/Makefile
index c7ff58c..893bee0 100644
--- a/drivers/infiniband/Makefile
+++ b/drivers/infiniband/Makefile
@@ -1,6 +1,7 @@
obj-$(CONFIG_INFINIBAND) += core/
obj-$(CONFIG_INFINIBAND_MTHCA) += hw/mthca/
obj-$(CONFIG_IPATH_CORE) += hw/ipath/
+obj-$(CONFIG_INFINIBAND_EHCA) += hw/ehca/
obj-$(CONFIG_INFINIBAND_IPOIB) += ulp/ipoib/
obj-$(CONFIG_INFINIBAND_SRP) += ulp/srp/
obj-$(CONFIG_INFINIBAND_ISER) += ulp/iser/
diff --git a/drivers/infiniband/hw/ehca/Kconfig b/drivers/infiniband/hw/ehca/Kconfig
new file mode 100644
index 0000000..12285d0
--- /dev/null
+++ b/drivers/infiniband/hw/ehca/Kconfig
@@ -0,0 +1,12 @@
+config INFINIBAND_EHCA
+ tristate "eHCA support"
+ depends on IBMEBUS && INFINIBAND
+ ---help---
+ This is a low level device driver for the IBM GX based Host channel
+ adapters (HCAs).
+
+config INFINIBAND_EHCA_SCALING
+ bool "Scaling support (EXPERIMENTAL)"
+ depends on IBMEBUS && INFINIBAND_EHCA && HOTPLUG_CPU && EXPERIMENTAL
+ ---help---
+ eHCA scaling support schedules the CQ callbacks to different CPUs.
diff --git a/drivers/infiniband/hw/ehca/Makefile b/drivers/infiniband/hw/ehca/Makefile
new file mode 100644
index 0000000..70032cf
--- /dev/null
+++ b/drivers/infiniband/hw/ehca/Makefile
@@ -0,0 +1,18 @@
+# Authors: Heiko J Schick <schickhj@de.ibm.com>
+# Christoph Raisch <raisch@de.ibm.com>
+# Joachim Fenkes <fenkes@de.ibm.com>
+#
+# Copyright (c) 2005 IBM Corporation
+#
+# All rights reserved.
+#
+# This source code is distributed under a dual license of GPL v2.0 and OpenIB BSD.
+
+obj-$(CONFIG_INFINIBAND_EHCA) += hcad_mod.o
+
+
+hcad_mod-objs = ehca_main.o ehca_hca.o ehca_mcast.o ehca_pd.o ehca_av.o ehca_eq.o \
+ ehca_cq.o ehca_qp.o ehca_sqp.o ehca_mrmw.o ehca_reqs.o ehca_irq.o \
+ ehca_uverbs.o ipz_pt_fn.o hcp_if.o hcp_phyp.o
+
+CFLAGS += -DEHCA_USE_HCALL -DEHCA_USE_HCALL_KERNEL
--
1.4.1
^ permalink raw reply related
* [PATCH 02/13] IB/ehca: includes
From: Roland Dreier @ 2006-08-17 20:11 UTC (permalink / raw)
To: openib-general, linux-kernel, linuxppc-dev; +Cc: RAISCH, HNGUYEN, MEDER
In-Reply-To: <20068171311.qHSUlh5t6lpV4BeW@cisco.com>
drivers/infiniband/hw/ehca/ehca_iverbs.h | 181 +++++++++++++
drivers/infiniband/hw/ehca/ehca_tools.h | 417 ++++++++++++++++++++++++++++++
2 files changed, 598 insertions(+), 0 deletions(-)
diff --git a/drivers/infiniband/hw/ehca/ehca_iverbs.h b/drivers/infiniband/hw/ehca/ehca_iverbs.h
new file mode 100644
index 0000000..bbdc437
--- /dev/null
+++ b/drivers/infiniband/hw/ehca/ehca_iverbs.h
@@ -0,0 +1,181 @@
+/*
+ * IBM eServer eHCA Infiniband device driver for Linux on POWER
+ *
+ * Function definitions for internal functions
+ *
+ * Authors: Heiko J Schick <schickhj@de.ibm.com>
+ * Dietmar Decker <ddecker@de.ibm.com>
+ *
+ * Copyright (c) 2005 IBM Corporation
+ *
+ * All rights reserved.
+ *
+ * This source code is distributed under a dual license of GPL v2.0 and OpenIB
+ * BSD.
+ *
+ * OpenIB BSD License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials
+ * provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
+ * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __EHCA_IVERBS_H__
+#define __EHCA_IVERBS_H__
+
+#include "ehca_classes.h"
+
+int ehca_query_device(struct ib_device *ibdev, struct ib_device_attr *props);
+
+int ehca_query_port(struct ib_device *ibdev, u8 port,
+ struct ib_port_attr *props);
+
+int ehca_query_pkey(struct ib_device *ibdev, u8 port, u16 index, u16 * pkey);
+
+int ehca_query_gid(struct ib_device *ibdev, u8 port, int index,
+ union ib_gid *gid);
+
+int ehca_modify_port(struct ib_device *ibdev, u8 port, int port_modify_mask,
+ struct ib_port_modify *props);
+
+struct ib_pd *ehca_alloc_pd(struct ib_device *device,
+ struct ib_ucontext *context,
+ struct ib_udata *udata);
+
+int ehca_dealloc_pd(struct ib_pd *pd);
+
+struct ib_ah *ehca_create_ah(struct ib_pd *pd, struct ib_ah_attr *ah_attr);
+
+int ehca_modify_ah(struct ib_ah *ah, struct ib_ah_attr *ah_attr);
+
+int ehca_query_ah(struct ib_ah *ah, struct ib_ah_attr *ah_attr);
+
+int ehca_destroy_ah(struct ib_ah *ah);
+
+struct ib_mr *ehca_get_dma_mr(struct ib_pd *pd, int mr_access_flags);
+
+struct ib_mr *ehca_reg_phys_mr(struct ib_pd *pd,
+ struct ib_phys_buf *phys_buf_array,
+ int num_phys_buf,
+ int mr_access_flags, u64 *iova_start);
+
+struct ib_mr *ehca_reg_user_mr(struct ib_pd *pd,
+ struct ib_umem *region,
+ int mr_access_flags, struct ib_udata *udata);
+
+int ehca_rereg_phys_mr(struct ib_mr *mr,
+ int mr_rereg_mask,
+ struct ib_pd *pd,
+ struct ib_phys_buf *phys_buf_array,
+ int num_phys_buf, int mr_access_flags, u64 *iova_start);
+
+int ehca_query_mr(struct ib_mr *mr, struct ib_mr_attr *mr_attr);
+
+int ehca_dereg_mr(struct ib_mr *mr);
+
+struct ib_mw *ehca_alloc_mw(struct ib_pd *pd);
+
+int ehca_bind_mw(struct ib_qp *qp, struct ib_mw *mw,
+ struct ib_mw_bind *mw_bind);
+
+int ehca_dealloc_mw(struct ib_mw *mw);
+
+struct ib_fmr *ehca_alloc_fmr(struct ib_pd *pd,
+ int mr_access_flags,
+ struct ib_fmr_attr *fmr_attr);
+
+int ehca_map_phys_fmr(struct ib_fmr *fmr,
+ u64 *page_list, int list_len, u64 iova);
+
+int ehca_unmap_fmr(struct list_head *fmr_list);
+
+int ehca_dealloc_fmr(struct ib_fmr *fmr);
+
+enum ehca_eq_type {
+ EHCA_EQ = 0, /* Event Queue */
+ EHCA_NEQ /* Notification Event Queue */
+};
+
+int ehca_create_eq(struct ehca_shca *shca, struct ehca_eq *eq,
+ enum ehca_eq_type type, const u32 length);
+
+int ehca_destroy_eq(struct ehca_shca *shca, struct ehca_eq *eq);
+
+void *ehca_poll_eq(struct ehca_shca *shca, struct ehca_eq *eq);
+
+
+struct ib_cq *ehca_create_cq(struct ib_device *device, int cqe,
+ struct ib_ucontext *context,
+ struct ib_udata *udata);
+
+int ehca_destroy_cq(struct ib_cq *cq);
+
+int ehca_resize_cq(struct ib_cq *cq, int cqe, struct ib_udata *udata);
+
+int ehca_poll_cq(struct ib_cq *cq, int num_entries, struct ib_wc *wc);
+
+int ehca_peek_cq(struct ib_cq *cq, int wc_cnt);
+
+int ehca_req_notify_cq(struct ib_cq *cq, enum ib_cq_notify cq_notify);
+
+struct ib_qp *ehca_create_qp(struct ib_pd *pd,
+ struct ib_qp_init_attr *init_attr,
+ struct ib_udata *udata);
+
+int ehca_destroy_qp(struct ib_qp *qp);
+
+int ehca_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, int attr_mask);
+
+int ehca_query_qp(struct ib_qp *qp, struct ib_qp_attr *qp_attr,
+ int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr);
+
+int ehca_post_send(struct ib_qp *qp, struct ib_send_wr *send_wr,
+ struct ib_send_wr **bad_send_wr);
+
+int ehca_post_recv(struct ib_qp *qp, struct ib_recv_wr *recv_wr,
+ struct ib_recv_wr **bad_recv_wr);
+
+u64 ehca_define_sqp(struct ehca_shca *shca, struct ehca_qp *ibqp,
+ struct ib_qp_init_attr *qp_init_attr);
+
+int ehca_attach_mcast(struct ib_qp *qp, union ib_gid *gid, u16 lid);
+
+int ehca_detach_mcast(struct ib_qp *qp, union ib_gid *gid, u16 lid);
+
+struct ib_ucontext *ehca_alloc_ucontext(struct ib_device *device,
+ struct ib_udata *udata);
+
+int ehca_dealloc_ucontext(struct ib_ucontext *context);
+
+int ehca_mmap(struct ib_ucontext *context, struct vm_area_struct *vma);
+
+void ehca_poll_eqs(unsigned long data);
+
+int ehca_mmap_nopage(u64 foffset,u64 length,void **mapped,
+ struct vm_area_struct **vma);
+
+int ehca_mmap_register(u64 physical,void **mapped,
+ struct vm_area_struct **vma);
+
+int ehca_munmap(unsigned long addr, size_t len);
+
+#endif
diff --git a/drivers/infiniband/hw/ehca/ehca_tools.h b/drivers/infiniband/hw/ehca/ehca_tools.h
new file mode 100644
index 0000000..783fbb3
--- /dev/null
+++ b/drivers/infiniband/hw/ehca/ehca_tools.h
@@ -0,0 +1,417 @@
+/*
+ * IBM eServer eHCA Infiniband device driver for Linux on POWER
+ *
+ * auxiliary functions
+ *
+ * Authors: Christoph Raisch <raisch@de.ibm.com>
+ * Hoang-Nam Nguyen <hnguyen@de.ibm.com>
+ * Khadija Souissi <souissik@de.ibm.com>
+ * Waleri Fomin <fomin@de.ibm.com>
+ * Heiko J Schick <schickhj@de.ibm.com>
+ *
+ * Copyright (c) 2005 IBM Corporation
+ *
+ * This source code is distributed under a dual license of GPL v2.0 and OpenIB
+ * BSD.
+ *
+ * OpenIB BSD License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials
+ * provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
+ * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+#ifndef EHCA_TOOLS_H
+#define EHCA_TOOLS_H
+
+#include <linux/kernel.h>
+#include <linux/spinlock.h>
+#include <linux/delay.h>
+#include <linux/idr.h>
+#include <linux/kthread.h>
+#include <linux/mm.h>
+#include <linux/mman.h>
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/vmalloc.h>
+#include <linux/version.h>
+#include <linux/notifier.h>
+#include <linux/cpu.h>
+
+#include <asm/abs_addr.h>
+#include <asm/ibmebus.h>
+#include <asm/io.h>
+#include <asm/pgtable.h>
+
+#define EHCA_EDEB_TRACE_MASK_SIZE 32
+extern u8 ehca_edeb_mask[EHCA_EDEB_TRACE_MASK_SIZE];
+#define EDEB_ID_TO_U32(str4) (str4[3] | (str4[2] << 8) | (str4[1] << 16) | \
+ (str4[0] << 24))
+
+static inline u64 ehca_edeb_filter(const u32 level,
+ const u32 id, const u32 line)
+{
+ u64 ret = 0;
+ u32 filenr = 0;
+ u32 filter_level = 9;
+ u32 dynamic_level = 0;
+
+ /*
+ * This is code written for the gcc -O2 optimizer
+ * which should collapse to two single ints.
+ * Filter_level is the first level kicked out by
+ * compiler and means trace everything below 6.
+ */
+
+ if (id == EDEB_ID_TO_U32("ehav")) {
+ filenr = 0x01;
+ filter_level = 8;
+ }
+ if (id == EDEB_ID_TO_U32("clas")) {
+ filenr = 0x02;
+ filter_level = 8;
+ }
+ if (id == EDEB_ID_TO_U32("cqeq")) {
+ filenr = 0x03;
+ filter_level = 8;
+ }
+ if (id == EDEB_ID_TO_U32("shca")) {
+ filenr = 0x05;
+ filter_level = 8;
+ }
+ if (id == EDEB_ID_TO_U32("eirq")) {
+ filenr = 0x06;
+ filter_level = 8;
+ }
+ if (id == EDEB_ID_TO_U32("lMad")) {
+ filenr = 0x07;
+ filter_level = 8;
+ }
+ if (id == EDEB_ID_TO_U32("mcas")) {
+ filenr = 0x08;
+ filter_level = 8;
+ }
+ if (id == EDEB_ID_TO_U32("mrmw")) {
+ filenr = 0x09;
+ filter_level = 8;
+ }
+ if (id == EDEB_ID_TO_U32("vpd ")) {
+ filenr = 0x0a;
+ filter_level = 8;
+ }
+ if (id == EDEB_ID_TO_U32("e_qp")) {
+ filenr = 0x0b;
+ filter_level = 8;
+ }
+ if (id == EDEB_ID_TO_U32("uqes")) {
+ filenr = 0x0c;
+ filter_level = 8;
+ }
+ if (id == EDEB_ID_TO_U32("PHYP")) {
+ filenr = 0x0d;
+ filter_level = 8;
+ }
+ if (id == EDEB_ID_TO_U32("hcpi")) {
+ filenr = 0x0e;
+ filter_level = 8;
+ }
+ if (id == EDEB_ID_TO_U32("iptz")) {
+ filenr = 0x0f;
+ filter_level = 8;
+ }
+ if (id == EDEB_ID_TO_U32("spta")) {
+ filenr = 0x10;
+ filter_level = 8;
+ }
+ if (id == EDEB_ID_TO_U32("simp")) {
+ filenr = 0x11;
+ filter_level = 8;
+ }
+ if (id == EDEB_ID_TO_U32("reqs")) {
+ filenr = 0x12;
+ filter_level = 8;
+ }
+
+ if ((filenr - 1) > sizeof(ehca_edeb_mask)) {
+ filenr = 0;
+ }
+
+ if (filenr == 0) {
+ filter_level = 9;
+ } /* default */
+ ret = filenr * 0x10000 + line;
+ if (filter_level <= level) {
+ return ret | 0x100000000L; /* this is the flag to not trace */
+ }
+ dynamic_level = ehca_edeb_mask[filenr];
+ if (likely(dynamic_level <= level)) {
+ ret = ret | 0x100000000L;
+ };
+ return ret;
+}
+
+#ifdef EHCA_USE_HCALL_KERNEL
+#ifdef CONFIG_PPC_PSERIES
+
+#include <asm/paca.h>
+
+/*
+ * IS_EDEB_ON - Checks if debug is on for the given level.
+ */
+#define IS_EDEB_ON(level) \
+((ehca_edeb_filter(level, EDEB_ID_TO_U32(DEB_PREFIX), __LINE__) & \
+ 0x100000000L) == 0)
+
+#define EDEB_P_GENERIC(level,idstring,format,args...) \
+do { \
+ u64 ehca_edeb_filterresult = \
+ ehca_edeb_filter(level, EDEB_ID_TO_U32(DEB_PREFIX), __LINE__);\
+ if ((ehca_edeb_filterresult & 0x100000000L) == 0) \
+ printk("PU%04x %08x:%s " idstring " "format "\n", \
+ get_paca()->paca_index, (u32)(ehca_edeb_filterresult), \
+ __func__, ##args); \
+} while (1 == 0)
+
+#elif REAL_HCALL
+
+#define EDEB_P_GENERIC(level,idstring,format,args...) \
+do { \
+ u64 ehca_edeb_filterresult = \
+ ehca_edeb_filter(level, EDEB_ID_TO_U32(DEB_PREFIX), __LINE__); \
+ if ((ehca_edeb_filterresult & 0x100000000L) == 0) \
+ printk("%08x:%s " idstring " "format "\n", \
+ (u32)(ehca_edeb_filterresult), \
+ __func__, ##args); \
+} while (1 == 0)
+
+#endif
+#else
+
+#define IS_EDEB_ON(level) (1)
+
+#define EDEB_P_GENERIC(level,idstring,format,args...) \
+do { \
+ printk("%s " idstring " "format "\n", \
+ __func__, ##args); \
+} while (1 == 0)
+
+#endif
+
+/**
+ * EDEB - Trace output macro.
+ * @level: tracelevel
+ * @format: optional format string, use "" if not desired
+ * @args: printf like arguments for trace
+ */
+#define EDEB(level,format,args...) \
+ EDEB_P_GENERIC(level,"",format,##args)
+#define EDEB_ERR(level,format,args...) \
+ EDEB_P_GENERIC(level,"HCAD_ERROR ",format,##args)
+#define EDEB_EN(level,format,args...) \
+ EDEB_P_GENERIC(level,">>>",format,##args)
+#define EDEB_EX(level,format,args...) \
+ EDEB_P_GENERIC(level,"<<<",format,##args)
+
+/**
+ * EDEB_DMP - macro to dump a memory block, whose length is n*8 bytes.
+ * Each line has the following layout:
+ * <format string> adr=X ofs=Y <8 bytes hex> <8 bytes hex>
+ */
+#define EDEB_DMP(level,adr,len,format,args...) \
+ do { \
+ unsigned int x; \
+ unsigned int l = (unsigned int)(len); \
+ unsigned char *deb = (unsigned char*)(adr); \
+ for (x = 0; x < l; x += 16) { \
+ EDEB(level, format " adr=%p ofs=%04x %016lx %016lx", \
+ ##args, deb, x, \
+ *((u64 *)&deb[0]), *((u64 *)&deb[8])); \
+ deb += 16; \
+ } \
+ } while (0)
+
+/* define a bitmask, little endian version */
+#define EHCA_BMASK(pos,length) (((pos)<<16)+(length))
+
+/* define a bitmask, the ibm way... */
+#define EHCA_BMASK_IBM(from,to) (((63-to)<<16)+((to)-(from)+1))
+
+/* internal function, don't use */
+#define EHCA_BMASK_SHIFTPOS(mask) (((mask)>>16)&0xffff)
+
+/* internal function, don't use */
+#define EHCA_BMASK_MASK(mask) (0xffffffffffffffffULL >> ((64-(mask))&0xffff))
+
+/**
+ * EHCA_BMASK_SET - return value shifted and masked by mask
+ * variable|=EHCA_BMASK_SET(MY_MASK,0x4711) ORs the bits in variable
+ * variable&=~EHCA_BMASK_SET(MY_MASK,-1) clears the bits from the mask
+ * in variable
+ */
+#define EHCA_BMASK_SET(mask,value) \
+ ((EHCA_BMASK_MASK(mask) & ((u64)(value)))<<EHCA_BMASK_SHIFTPOS(mask))
+
+/**
+ * EHCA_BMASK_GET - extract a parameter from value by mask
+ */
+#define EHCA_BMASK_GET(mask,value) \
+ ( EHCA_BMASK_MASK(mask)& (((u64)(value))>>EHCA_BMASK_SHIFTPOS(mask)))
+
+#define PARANOIA_MODE
+#ifdef PARANOIA_MODE
+
+#define EHCA_CHECK_ADR_P(adr) \
+ if (unlikely(adr == 0)) { \
+ EDEB_ERR(4, "adr=%p check failed line %i", adr, \
+ __LINE__); \
+ return ERR_PTR(-EFAULT); }
+
+#define EHCA_CHECK_ADR(adr) \
+ if (unlikely(adr == 0)) { \
+ EDEB_ERR(4, "adr=%p check failed line %i", adr, \
+ __LINE__); \
+ return -EFAULT; }
+
+#define EHCA_CHECK_DEVICE_P(device) \
+ if (unlikely(device == 0)) { \
+ EDEB_ERR(4, "device=%p check failed", device); \
+ return ERR_PTR(-EFAULT); }
+
+#define EHCA_CHECK_DEVICE(device) \
+ if (unlikely(device == 0)) { \
+ EDEB_ERR(4, "device=%p check failed", device); \
+ return -EFAULT; }
+
+#define EHCA_CHECK_PD(pd) \
+ if (unlikely(pd == 0)) { \
+ EDEB_ERR(4, "pd=%p check failed", pd); \
+ return -EFAULT; }
+
+#define EHCA_CHECK_PD_P(pd) \
+ if (unlikely(pd == 0)) { \
+ EDEB_ERR(4, "pd=%p check failed", pd); \
+ return ERR_PTR(-EFAULT); }
+
+#define EHCA_CHECK_AV(av) \
+ if (unlikely(av == 0)) { \
+ EDEB_ERR(4, "av=%p check failed", av); \
+ return -EFAULT; }
+
+#define EHCA_CHECK_AV_P(av) \
+ if (unlikely(av == 0)) { \
+ EDEB_ERR(4, "av=%p check failed", av); \
+ return ERR_PTR(-EFAULT); }
+
+#define EHCA_CHECK_CQ(cq) \
+ if (unlikely(cq == 0)) { \
+ EDEB_ERR(4, "cq=%p check failed", cq); \
+ return -EFAULT; }
+
+#define EHCA_CHECK_CQ_P(cq) \
+ if (unlikely(cq == 0)) { \
+ EDEB_ERR(4, "cq=%p check failed", cq); \
+ return ERR_PTR(-EFAULT); }
+
+#define EHCA_CHECK_EQ(eq) \
+ if (unlikely(eq == 0)) { \
+ EDEB_ERR(4, "eq=%p check failed", eq); \
+ return -EFAULT; }
+
+#define EHCA_CHECK_EQ_P(eq) \
+ if (unlikely(eq == 0)) { \
+ EDEB_ERR(4, "eq=%p check failed", eq); \
+ return ERR_PTR(-EFAULT); }
+
+#define EHCA_CHECK_QP(qp) \
+ if (unlikely(qp == 0)) { \
+ EDEB_ERR(4, "qp=%p check failed", qp); \
+ return -EFAULT; }
+
+#define EHCA_CHECK_QP_P(qp) \
+ if (unlikely(qp == 0)) { \
+ EDEB_ERR(4, "qp=%p check failed", qp); \
+ return ERR_PTR(-EFAULT); }
+
+#define EHCA_CHECK_MR(mr) \
+ if (unlikely(mr == 0)) { \
+ EDEB_ERR(4, "mr=%p check failed", mr); \
+ return -EFAULT; }
+
+#define EHCA_CHECK_MR_P(mr) \
+ if (unlikely(mr == 0)) { \
+ EDEB_ERR(4, "mr=%p check failed", mr); \
+ return ERR_PTR(-EFAULT); }
+
+#define EHCA_CHECK_MW(mw) \
+ if (unlikely(mw == 0)) { \
+ EDEB_ERR(4, "mw=%p check failed", mw); \
+ return -EFAULT; }
+
+#define EHCA_CHECK_MW_P(mw) \
+ if (unlikely(mw == 0)) { \
+ EDEB_ERR(4, "mw=%p check failed", mw); \
+ return ERR_PTR(-EFAULT); }
+
+#define EHCA_CHECK_FMR(fmr) \
+ if (unlikely(fmr == 0)) { \
+ EDEB_ERR(4, "fmr=%p check failed", fmr); \
+ return -EFAULT; }
+
+#define EHCA_CHECK_FMR_P(fmr) \
+ if (unlikely(fmr == 0)) { \
+ EDEB_ERR(4, "fmr=%p check failed", fmr); \
+ return ERR_PTR(-EFAULT); }
+
+#define EHCA_REGISTER_PD(device,pd)
+#define EHCA_REGISTER_AV(pd,av)
+#define EHCA_DEREGISTER_PD(PD)
+#define EHCA_DEREGISTER_AV(av)
+#else
+#define EHCA_CHECK_DEVICE_P(device)
+
+#define EHCA_CHECK_PD(pd)
+#define EHCA_REGISTER_PD(device,pd)
+#define EHCA_DEREGISTER_PD(PD)
+#endif
+
+static inline int ehca_adr_bad(void *adr)
+{
+ return !adr;
+}
+
+/* Converts ehca to ib return code */
+static inline int ehca2ib_return_code(u64 ehca_rc)
+{
+ switch (ehca_rc) {
+ case H_SUCCESS:
+ return 0;
+ case H_BUSY:
+ return -EBUSY;
+ case H_NO_MEM:
+ return -ENOMEM;
+ default:
+ return -EINVAL;
+ }
+}
+
+#endif /* EHCA_TOOLS_H */
--
1.4.1
^ permalink raw reply related
* [PATCH 10/13] IB/ehca: hipz
From: Roland Dreier @ 2006-08-17 20:11 UTC (permalink / raw)
To: openib-general, linux-kernel, linuxppc-dev; +Cc: RAISCH, HNGUYEN, MEDER
In-Reply-To: <20068171311.sHGelL4wOwoc17UG@cisco.com>
drivers/infiniband/hw/ehca/hipz_fns.h | 68 +++++
drivers/infiniband/hw/ehca/hipz_fns_core.h | 122 +++++++++
drivers/infiniband/hw/ehca/hipz_hw.h | 390 ++++++++++++++++++++++++++++
3 files changed, 580 insertions(+), 0 deletions(-)
diff --git a/drivers/infiniband/hw/ehca/hipz_fns.h b/drivers/infiniband/hw/ehca/hipz_fns.h
new file mode 100644
index 0000000..9dac93d
--- /dev/null
+++ b/drivers/infiniband/hw/ehca/hipz_fns.h
@@ -0,0 +1,68 @@
+/*
+ * IBM eServer eHCA Infiniband device driver for Linux on POWER
+ *
+ * HW abstraction register functions
+ *
+ * Authors: Christoph Raisch <raisch@de.ibm.com>
+ * Reinhard Ernst <rernst@de.ibm.com>
+ *
+ * Copyright (c) 2005 IBM Corporation
+ *
+ * All rights reserved.
+ *
+ * This source code is distributed under a dual license of GPL v2.0 and OpenIB
+ * BSD.
+ *
+ * OpenIB BSD License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials
+ * provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
+ * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __HIPZ_FNS_H__
+#define __HIPZ_FNS_H__
+
+#include "ehca_classes.h"
+#include "hipz_hw.h"
+
+#include "hipz_fns_core.h"
+
+#define hipz_galpa_store_eq(gal, offset, value) \
+ hipz_galpa_store(gal, EQTEMM_OFFSET(offset), value)
+
+#define hipz_galpa_load_eq(gal, offset) \
+ hipz_galpa_load(gal, EQTEMM_OFFSET(offset))
+
+#define hipz_galpa_store_qped(gal, offset, value) \
+ hipz_galpa_store(gal, QPEDMM_OFFSET(offset), value)
+
+#define hipz_galpa_load_qped(gal, offset) \
+ hipz_galpa_load(gal, QPEDMM_OFFSET(offset))
+
+#define hipz_galpa_store_mrmw(gal, offset, value) \
+ hipz_galpa_store(gal, MRMWMM_OFFSET(offset), value)
+
+#define hipz_galpa_load_mrmw(gal, offset) \
+ hipz_galpa_load(gal, MRMWMM_OFFSET(offset))
+
+#endif
diff --git a/drivers/infiniband/hw/ehca/hipz_fns_core.h b/drivers/infiniband/hw/ehca/hipz_fns_core.h
new file mode 100644
index 0000000..ff8d7ed
--- /dev/null
+++ b/drivers/infiniband/hw/ehca/hipz_fns_core.h
@@ -0,0 +1,122 @@
+/*
+ * IBM eServer eHCA Infiniband device driver for Linux on POWER
+ *
+ * HW abstraction register functions
+ *
+ * Authors: Christoph Raisch <raisch@de.ibm.com>
+ * Heiko J Schick <schickhj@de.ibm.com>
+ * Hoang-Nam Nguyen <hnguyen@de.ibm.com>
+ * Reinhard Ernst <rernst@de.ibm.com>
+ *
+ * Copyright (c) 2005 IBM Corporation
+ *
+ * All rights reserved.
+ *
+ * This source code is distributed under a dual license of GPL v2.0 and OpenIB
+ * BSD.
+ *
+ * OpenIB BSD License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials
+ * provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
+ * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __HIPZ_FNS_CORE_H__
+#define __HIPZ_FNS_CORE_H__
+
+#include "hcp_phyp.h"
+#include "hipz_hw.h"
+
+#define hipz_galpa_store_cq(gal, offset, value) \
+ hipz_galpa_store(gal, CQTEMM_OFFSET(offset), value)
+
+#define hipz_galpa_load_cq(gal, offset) \
+ hipz_galpa_load(gal, CQTEMM_OFFSET(offset))
+
+#define hipz_galpa_store_qp(gal,offset, value) \
+ hipz_galpa_store(gal, QPTEMM_OFFSET(offset), value)
+#define hipz_galpa_load_qp(gal, offset) \
+ hipz_galpa_load(gal,QPTEMM_OFFSET(offset))
+
+static inline void hipz_update_sqa(struct ehca_qp *qp, u16 nr_wqes)
+{
+ struct h_galpa gal;
+
+ EDEB_EN(7, "qp=%p", qp);
+ gal = qp->galpas.kernel;
+ /* ringing doorbell :-) */
+ hipz_galpa_store_qp(gal, qpx_sqa, EHCA_BMASK_SET(QPX_SQADDER, nr_wqes));
+ EDEB_EX(7, "qp=%p QPx_SQA = %i", qp, nr_wqes);
+}
+
+static inline void hipz_update_rqa(struct ehca_qp *qp, u16 nr_wqes)
+{
+ struct h_galpa gal;
+
+ EDEB_EN(7, "qp=%p", qp);
+ gal = qp->galpas.kernel;
+ /* ringing doorbell :-) */
+ hipz_galpa_store_qp(gal, qpx_rqa, EHCA_BMASK_SET(QPX_RQADDER, nr_wqes));
+ EDEB_EX(7, "qp=%p QPx_RQA = %i", qp, nr_wqes);
+}
+
+static inline void hipz_update_feca(struct ehca_cq *cq, u32 nr_cqes)
+{
+ struct h_galpa gal;
+
+ EDEB_EN(7, "cq=%p", cq);
+ gal = cq->galpas.kernel;
+ hipz_galpa_store_cq(gal, cqx_feca,
+ EHCA_BMASK_SET(CQX_FECADDER, nr_cqes));
+ EDEB_EX(7, "cq=%p CQx_FECA = %i", cq, nr_cqes);
+}
+
+static inline void hipz_set_cqx_n0(struct ehca_cq *cq, u32 value)
+{
+ struct h_galpa gal;
+ u64 CQx_N0_reg = 0;
+
+ EDEB_EN(7, "cq=%p event on solicited completion -- write CQx_N0", cq);
+ gal = cq->galpas.kernel;
+ hipz_galpa_store_cq(gal, cqx_n0,
+ EHCA_BMASK_SET(CQX_N0_GENERATE_SOLICITED_COMP_EVENT,
+ value));
+ CQx_N0_reg = hipz_galpa_load_cq(gal, cqx_n0);
+ EDEB_EX(7, "cq=%p loaded CQx_N0=%lx", cq, (unsigned long)CQx_N0_reg);
+}
+
+static inline void hipz_set_cqx_n1(struct ehca_cq *cq, u32 value)
+{
+ struct h_galpa gal;
+ u64 CQx_N1_reg = 0;
+
+ EDEB_EN(7, "cq=%p event on completion -- write CQx_N1",
+ cq);
+ gal = cq->galpas.kernel;
+ hipz_galpa_store_cq(gal, cqx_n1,
+ EHCA_BMASK_SET(CQX_N1_GENERATE_COMP_EVENT, value));
+ CQx_N1_reg = hipz_galpa_load_cq(gal, cqx_n1);
+ EDEB_EX(7, "cq=%p loaded CQx_N1=%lx", cq, (unsigned long)CQx_N1_reg);
+}
+
+#endif /* __HIPZ_FNC_CORE_H__ */
diff --git a/drivers/infiniband/hw/ehca/hipz_hw.h b/drivers/infiniband/hw/ehca/hipz_hw.h
new file mode 100644
index 0000000..f5f4871
--- /dev/null
+++ b/drivers/infiniband/hw/ehca/hipz_hw.h
@@ -0,0 +1,390 @@
+/*
+ * IBM eServer eHCA Infiniband device driver for Linux on POWER
+ *
+ * eHCA register definitions
+ *
+ * Authors: Waleri Fomin <fomin@de.ibm.com>
+ * Christoph Raisch <raisch@de.ibm.com>
+ * Reinhard Ernst <rernst@de.ibm.com>
+ *
+ * Copyright (c) 2005 IBM Corporation
+ *
+ * All rights reserved.
+ *
+ * This source code is distributed under a dual license of GPL v2.0 and OpenIB
+ * BSD.
+ *
+ * OpenIB BSD License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials
+ * provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
+ * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __HIPZ_HW_H__
+#define __HIPZ_HW_H__
+
+#include "ehca_tools.h"
+
+/* QP Table Entry Memory Map */
+struct hipz_qptemm {
+ u64 qpx_hcr;
+ u64 qpx_c;
+ u64 qpx_herr;
+ u64 qpx_aer;
+/* 0x20*/
+ u64 qpx_sqa;
+ u64 qpx_sqc;
+ u64 qpx_rqa;
+ u64 qpx_rqc;
+/* 0x40*/
+ u64 qpx_st;
+ u64 qpx_pmstate;
+ u64 qpx_pmfa;
+ u64 qpx_pkey;
+/* 0x60*/
+ u64 qpx_pkeya;
+ u64 qpx_pkeyb;
+ u64 qpx_pkeyc;
+ u64 qpx_pkeyd;
+/* 0x80*/
+ u64 qpx_qkey;
+ u64 qpx_dqp;
+ u64 qpx_dlidp;
+ u64 qpx_portp;
+/* 0xa0*/
+ u64 qpx_slidp;
+ u64 qpx_slidpp;
+ u64 qpx_dlida;
+ u64 qpx_porta;
+/* 0xc0*/
+ u64 qpx_slida;
+ u64 qpx_slidpa;
+ u64 qpx_slvl;
+ u64 qpx_ipd;
+/* 0xe0*/
+ u64 qpx_mtu;
+ u64 qpx_lato;
+ u64 qpx_rlimit;
+ u64 qpx_rnrlimit;
+/* 0x100*/
+ u64 qpx_t;
+ u64 qpx_sqhp;
+ u64 qpx_sqptp;
+ u64 qpx_nspsn;
+/* 0x120*/
+ u64 qpx_nspsnhwm;
+ u64 reserved1;
+ u64 qpx_sdsi;
+ u64 qpx_sdsbc;
+/* 0x140*/
+ u64 qpx_sqwsize;
+ u64 qpx_sqwts;
+ u64 qpx_lsn;
+ u64 qpx_nssn;
+/* 0x160 */
+ u64 qpx_mor;
+ u64 qpx_cor;
+ u64 qpx_sqsize;
+ u64 qpx_erc;
+/* 0x180*/
+ u64 qpx_rnrrc;
+ u64 qpx_ernrwt;
+ u64 qpx_rnrresp;
+ u64 qpx_lmsna;
+/* 0x1a0 */
+ u64 qpx_sqhpc;
+ u64 qpx_sqcptp;
+ u64 qpx_sigt;
+ u64 qpx_wqecnt;
+/* 0x1c0*/
+ u64 qpx_rqhp;
+ u64 qpx_rqptp;
+ u64 qpx_rqsize;
+ u64 qpx_nrr;
+/* 0x1e0*/
+ u64 qpx_rdmac;
+ u64 qpx_nrpsn;
+ u64 qpx_lapsn;
+ u64 qpx_lcr;
+/* 0x200*/
+ u64 qpx_rwc;
+ u64 qpx_rwva;
+ u64 qpx_rdsi;
+ u64 qpx_rdsbc;
+/* 0x220*/
+ u64 qpx_rqwsize;
+ u64 qpx_crmsn;
+ u64 qpx_rdd;
+ u64 qpx_larpsn;
+/* 0x240*/
+ u64 qpx_pd;
+ u64 qpx_scqn;
+ u64 qpx_rcqn;
+ u64 qpx_aeqn;
+/* 0x260*/
+ u64 qpx_aaelog;
+ u64 qpx_ram;
+ u64 qpx_rdmaqe0;
+ u64 qpx_rdmaqe1;
+/* 0x280*/
+ u64 qpx_rdmaqe2;
+ u64 qpx_rdmaqe3;
+ u64 qpx_nrpsnhwm;
+/* 0x298*/
+ u64 reserved[(0x400 - 0x298) / 8];
+/* 0x400 extended data */
+ u64 reserved_ext[(0x500 - 0x400) / 8];
+/* 0x500 */
+ u64 reserved2[(0x1000 - 0x500) / 8];
+/* 0x1000 */
+};
+
+#define QPX_SQADDER EHCA_BMASK_IBM(48,63)
+#define QPX_RQADDER EHCA_BMASK_IBM(48,63)
+
+#define QPTEMM_OFFSET(x) offsetof(struct hipz_qptemm,x)
+
+/* MRMWPT Entry Memory Map */
+struct hipz_mrmwmm {
+ /* 0x00 */
+ u64 mrx_hcr;
+
+ u64 mrx_c;
+ u64 mrx_herr;
+ u64 mrx_aer;
+ /* 0x20 */
+ u64 mrx_pp;
+ u64 reserved1;
+ u64 reserved2;
+ u64 reserved3;
+ /* 0x40 */
+ u64 reserved4[(0x200 - 0x40) / 8];
+ /* 0x200 */
+ u64 mrx_ctl[64];
+
+};
+
+#define MRX_HCR_LPARID_VALID EHCA_BMASK_IBM(0,0)
+
+#define MRMWMM_OFFSET(x) offsetof(struct hipz_mrmwmm,x)
+
+struct hipz_qpedmm {
+ /* 0x00 */
+ u64 reserved0[(0x400) / 8];
+ /* 0x400 */
+ u64 qpedx_phh;
+ u64 qpedx_ppsgp;
+ /* 0x410 */
+ u64 qpedx_ppsgu;
+ u64 qpedx_ppdgp;
+ /* 0x420 */
+ u64 qpedx_ppdgu;
+ u64 qpedx_aph;
+ /* 0x430 */
+ u64 qpedx_apsgp;
+ u64 qpedx_apsgu;
+ /* 0x440 */
+ u64 qpedx_apdgp;
+ u64 qpedx_apdgu;
+ /* 0x450 */
+ u64 qpedx_apav;
+ u64 qpedx_apsav;
+ /* 0x460 */
+ u64 qpedx_hcr;
+ u64 reserved1[4];
+ /* 0x488 */
+ u64 qpedx_rrl0;
+ /* 0x490 */
+ u64 qpedx_rrrkey0;
+ u64 qpedx_rrva0;
+ /* 0x4a0 */
+ u64 reserved2;
+ u64 qpedx_rrl1;
+ /* 0x4b0 */
+ u64 qpedx_rrrkey1;
+ u64 qpedx_rrva1;
+ /* 0x4c0 */
+ u64 reserved3;
+ u64 qpedx_rrl2;
+ /* 0x4d0 */
+ u64 qpedx_rrrkey2;
+ u64 qpedx_rrva2;
+ /* 0x4e0 */
+ u64 reserved4;
+ u64 qpedx_rrl3;
+ /* 0x4f0 */
+ u64 qpedx_rrrkey3;
+ u64 qpedx_rrva3;
+};
+
+#define QPEDMM_OFFSET(x) offsetof(struct hipz_qpedmm,x)
+
+/* CQ Table Entry Memory Map */
+struct hipz_cqtemm {
+ u64 cqx_hcr;
+ u64 cqx_c;
+ u64 cqx_herr;
+ u64 cqx_aer;
+/* 0x20 */
+ u64 cqx_ptp;
+ u64 cqx_tp;
+ u64 cqx_fec;
+ u64 cqx_feca;
+/* 0x40 */
+ u64 cqx_ep;
+ u64 cqx_eq;
+/* 0x50 */
+ u64 reserved1;
+ u64 cqx_n0;
+/* 0x60 */
+ u64 cqx_n1;
+ u64 reserved2[(0x1000 - 0x60) / 8];
+/* 0x1000 */
+};
+
+#define CQX_FEC_CQE_CNT EHCA_BMASK_IBM(32,63)
+#define CQX_FECADDER EHCA_BMASK_IBM(32,63)
+#define CQX_N0_GENERATE_SOLICITED_COMP_EVENT EHCA_BMASK_IBM(0,0)
+#define CQX_N1_GENERATE_COMP_EVENT EHCA_BMASK_IBM(0,0)
+
+#define CQTEMM_OFFSET(x) offsetof(struct hipz_cqtemm,x)
+
+/* EQ Table Entry Memory Map */
+struct hipz_eqtemm {
+ u64 eqx_hcr;
+ u64 eqx_c;
+
+ u64 eqx_herr;
+ u64 eqx_aer;
+/* 0x20 */
+ u64 eqx_ptp;
+ u64 eqx_tp;
+ u64 eqx_ssba;
+ u64 eqx_psba;
+
+/* 0x40 */
+ u64 eqx_cec;
+ u64 eqx_meql;
+ u64 eqx_xisbi;
+ u64 eqx_xisc;
+/* 0x60 */
+ u64 eqx_it;
+
+};
+
+#define EQTEMM_OFFSET(x) offsetof(struct hipz_eqtemm,x)
+
+/* access control defines for MR/MW */
+#define HIPZ_ACCESSCTRL_L_WRITE 0x00800000
+#define HIPZ_ACCESSCTRL_R_WRITE 0x00400000
+#define HIPZ_ACCESSCTRL_R_READ 0x00200000
+#define HIPZ_ACCESSCTRL_R_ATOMIC 0x00100000
+#define HIPZ_ACCESSCTRL_MW_BIND 0x00080000
+
+/* query hca response block */
+struct hipz_query_hca {
+ u32 cur_reliable_dg;
+ u32 cur_qp;
+ u32 cur_cq;
+ u32 cur_eq;
+ u32 cur_mr;
+ u32 cur_mw;
+ u32 cur_ee_context;
+ u32 cur_mcast_grp;
+ u32 cur_qp_attached_mcast_grp;
+ u32 reserved1;
+ u32 cur_ipv6_qp;
+ u32 cur_eth_qp;
+ u32 cur_hp_mr;
+ u32 reserved2[3];
+ u32 max_rd_domain;
+ u32 max_qp;
+ u32 max_cq;
+ u32 max_eq;
+ u32 max_mr;
+ u32 max_hp_mr;
+ u32 max_mw;
+ u32 max_mrwpte;
+ u32 max_special_mrwpte;
+ u32 max_rd_ee_context;
+ u32 max_mcast_grp;
+ u32 max_total_mcast_qp_attach;
+ u32 max_mcast_qp_attach;
+ u32 max_raw_ipv6_qp;
+ u32 max_raw_ethy_qp;
+ u32 internal_clock_frequency;
+ u32 max_pd;
+ u32 max_ah;
+ u32 max_cqe;
+ u32 max_wqes_wq;
+ u32 max_partitions;
+ u32 max_rr_ee_context;
+ u32 max_rr_qp;
+ u32 max_rr_hca;
+ u32 max_act_wqs_ee_context;
+ u32 max_act_wqs_qp;
+ u32 max_sge;
+ u32 max_sge_rd;
+ u32 memory_page_size_supported;
+ u64 max_mr_size;
+ u32 local_ca_ack_delay;
+ u32 num_ports;
+ u32 vendor_id;
+ u32 vendor_part_id;
+ u32 hw_ver;
+ u64 node_guid;
+ u64 hca_cap_indicators;
+ u32 data_counter_register_size;
+ u32 max_shared_rq;
+ u32 max_isns_eq;
+ u32 max_neq;
+} __attribute__ ((packed));
+
+/* query port response block */
+struct hipz_query_port {
+ u32 state;
+ u32 bad_pkey_cntr;
+ u32 lmc;
+ u32 lid;
+ u32 subnet_timeout;
+ u32 qkey_viol_cntr;
+ u32 sm_sl;
+ u32 sm_lid;
+ u32 capability_mask;
+ u32 init_type_reply;
+ u32 pkey_tbl_len;
+ u32 gid_tbl_len;
+ u64 gid_prefix;
+ u32 port_nr;
+ u16 pkey_entries[16];
+ u8 reserved1[32];
+ u32 trent_size;
+ u32 trbuf_size;
+ u64 max_msg_sz;
+ u32 max_mtu;
+ u32 vl_cap;
+ u8 reserved2[1900];
+ u64 guid_entries[255];
+} __attribute__ ((packed));
+
+#endif
--
1.4.1
^ permalink raw reply related
* [PATCH 11/13] IB/ehca: ipz
From: Roland Dreier @ 2006-08-17 20:11 UTC (permalink / raw)
To: openib-general, linux-kernel, linuxppc-dev; +Cc: RAISCH, HNGUYEN, MEDER
In-Reply-To: <20068171311.jebQ3TFd5jvynHCW@cisco.com>
drivers/infiniband/hw/ehca/ipz_pt_fn.c | 166 +++++++++++++++++++++
drivers/infiniband/hw/ehca/ipz_pt_fn.h | 253 ++++++++++++++++++++++++++++++++
2 files changed, 419 insertions(+), 0 deletions(-)
diff --git a/drivers/infiniband/hw/ehca/ipz_pt_fn.c b/drivers/infiniband/hw/ehca/ipz_pt_fn.c
new file mode 100644
index 0000000..a14f957
--- /dev/null
+++ b/drivers/infiniband/hw/ehca/ipz_pt_fn.c
@@ -0,0 +1,166 @@
+/*
+ * IBM eServer eHCA Infiniband device driver for Linux on POWER
+ *
+ * internal queue handling
+ *
+ * Authors: Waleri Fomin <fomin@de.ibm.com>
+ * Reinhard Ernst <rernst@de.ibm.com>
+ * Christoph Raisch <raisch@de.ibm.com>
+ *
+ * Copyright (c) 2005 IBM Corporation
+ *
+ * This source code is distributed under a dual license of GPL v2.0 and OpenIB
+ * BSD.
+ *
+ * OpenIB BSD License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials
+ * provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
+ * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#define DEB_PREFIX "iptz"
+
+#include "ehca_tools.h"
+#include "ipz_pt_fn.h"
+
+extern int ehca_hwlevel;
+
+void *ipz_qpageit_get_inc(struct ipz_queue *queue)
+{
+ void *ret = ipz_qeit_get(queue);
+ queue->current_q_offset += queue->pagesize;
+ if (queue->current_q_offset > queue->queue_length) {
+ queue->current_q_offset -= queue->pagesize;
+ ret = NULL;
+ }
+ if (((u64)ret) % EHCA_PAGESIZE) {
+ EDEB(4, "ERROR!! not at PAGE-Boundary");
+ return NULL;
+ }
+ EDEB(7, "queue=%p ret=%p", queue, ret);
+ return ret;
+}
+
+void *ipz_qeit_eq_get_inc(struct ipz_queue *queue)
+{
+ void *ret = ipz_qeit_get(queue);
+ u64 last_entry_in_q = queue->queue_length - queue->qe_size;
+ queue->current_q_offset += queue->qe_size;
+ if (queue->current_q_offset > last_entry_in_q) {
+ queue->current_q_offset = 0;
+ queue->toggle_state = (~queue->toggle_state) & 1;
+ }
+
+ EDEB(7, "queue=%p ret=%p new current_q_offset=%lx qe_size=%x",
+ queue, ret, queue->current_q_offset, queue->qe_size);
+
+ return ret;
+}
+
+int ipz_queue_ctor(struct ipz_queue *queue,
+ const u32 nr_of_pages,
+ const u32 pagesize, const u32 qe_size, const u32 nr_of_sg)
+{
+ int pages_per_kpage = PAGE_SIZE >> EHCA_PAGESHIFT;
+ int f;
+
+ EDEB_EN(7, "nr_of_pages=%x pagesize=%x qe_size=%x pages_per_kpage=%x",
+ nr_of_pages, pagesize, qe_size, pages_per_kpage);
+ if (pagesize > PAGE_SIZE) {
+ EDEB_ERR(4, "FATAL ERROR: pagesize=%x is greater than "
+ "kernel page size", pagesize);
+ return 0;
+ }
+ if (!pages_per_kpage) {
+ EDEB_ERR(4, "FATAL ERROR: invalid kernel page size. "
+ "pages_per_kpage=%x", pages_per_kpage);
+ return 0;
+ }
+ queue->queue_length = nr_of_pages * pagesize;
+ queue->queue_pages = vmalloc(nr_of_pages * sizeof(void *));
+ if (!queue->queue_pages) {
+ EDEB(4, "ERROR!! didn't get the memory");
+ return 0;
+ }
+ memset(queue->queue_pages, 0, nr_of_pages * sizeof(void *));
+ /*
+ * allocate pages for queue:
+ * outer loop allocates whole kernel pages (page aligned) and
+ * inner loop divides a kernel page into smaller hca queue pages
+ */
+ f = 0;
+ while (f < nr_of_pages) {
+ u8 *kpage = (u8*)get_zeroed_page(GFP_KERNEL);
+ int k;
+ if (!kpage)
+ goto ipz_queue_ctor_exit0; /*NOMEM*/
+ for (k = 0; k < pages_per_kpage && f < nr_of_pages; k++) {
+ (queue->queue_pages)[f] = (struct ipz_page *)kpage;
+ kpage += EHCA_PAGESIZE;
+ f++;
+ }
+ }
+
+ queue->current_q_offset = 0;
+ queue->qe_size = qe_size;
+ queue->act_nr_of_sg = nr_of_sg;
+ queue->pagesize = pagesize;
+ queue->toggle_state = 1;
+ EDEB_EX(7, "queue_length=%x queue_pages=%p qe_size=%x"
+ " act_nr_of_sg=%x", queue->queue_length, queue->queue_pages,
+ queue->qe_size, queue->act_nr_of_sg);
+ return 1;
+
+ ipz_queue_ctor_exit0:
+ EDEB_ERR(4, "Couldn't get alloc pages queue=%p f=%x nr_of_pages=%x",
+ queue, f, nr_of_pages);
+ for (f = 0; f < nr_of_pages; f += pages_per_kpage) {
+ if (!(queue->queue_pages)[f])
+ break;
+ free_page((unsigned long)(queue->queue_pages)[f]);
+ }
+ return 0;
+}
+
+int ipz_queue_dtor(struct ipz_queue *queue)
+{
+ int pages_per_kpage = PAGE_SIZE >> EHCA_PAGESHIFT;
+ int g;
+ int nr_pages;
+
+ EDEB_EN(7, "ipz_queue pointer=%p", queue);
+ if (!queue || !queue->queue_pages) {
+ EDEB_ERR(4, "queue or queue_pages is NULL");
+ return 0;
+ }
+ EDEB(7, "destructing a queue with the following "
+ "properties:\n nr_of_pages=%x pagesize=%x qe_size=%x",
+ queue->act_nr_of_sg, queue->pagesize, queue->qe_size);
+ nr_pages = queue->queue_length / queue->pagesize;
+ for (g = 0; g < nr_pages; g += pages_per_kpage)
+ free_page((unsigned long)(queue->queue_pages)[g]);
+ vfree(queue->queue_pages);
+
+ EDEB_EX(7, "queue freed!");
+ return 1;
+}
diff --git a/drivers/infiniband/hw/ehca/ipz_pt_fn.h b/drivers/infiniband/hw/ehca/ipz_pt_fn.h
new file mode 100644
index 0000000..fdd139b
--- /dev/null
+++ b/drivers/infiniband/hw/ehca/ipz_pt_fn.h
@@ -0,0 +1,253 @@
+/*
+ * IBM eServer eHCA Infiniband device driver for Linux on POWER
+ *
+ * internal queue handling
+ *
+ * Authors: Waleri Fomin <fomin@de.ibm.com>
+ * Reinhard Ernst <rernst@de.ibm.com>
+ * Christoph Raisch <raisch@de.ibm.com>
+ *
+ * Copyright (c) 2005 IBM Corporation
+ *
+ * All rights reserved.
+ *
+ * This source code is distributed under a dual license of GPL v2.0 and OpenIB
+ * BSD.
+ *
+ * OpenIB BSD License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials
+ * provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
+ * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __IPZ_PT_FN_H__
+#define __IPZ_PT_FN_H__
+
+#include "ehca_qes.h"
+#define EHCA_PAGESHIFT 12
+#define EHCA_PAGESIZE 4096UL
+#define EHCA_PAGEMASK (~(EHCA_PAGESIZE-1))
+#define EHCA_PT_ENTRIES 512UL
+
+#include "ehca_tools.h"
+#include "ehca_qes.h"
+
+/* struct generic ehca page */
+struct ipz_page {
+ u8 entries[EHCA_PAGESIZE];
+};
+
+/* struct generic queue in linux kernel virtual memory (kv) */
+struct ipz_queue {
+ u64 current_q_offset; /* current queue entry */
+
+ struct ipz_page **queue_pages; /* array of pages belonging to queue */
+ u32 qe_size; /* queue entry size */
+ u32 act_nr_of_sg;
+ u32 queue_length; /* queue length allocated in bytes */
+ u32 pagesize;
+ u32 toggle_state; /* toggle flag - per page */
+ u32 dummy3; /* 64 bit alignment */
+};
+
+/*
+ * return current Queue Entry for a certain q_offset
+ * returns address (kv) of Queue Entry
+ */
+static inline void *ipz_qeit_calc(struct ipz_queue *queue, u64 q_offset)
+{
+ struct ipz_page *current_page = NULL;
+ if (q_offset >= queue->queue_length)
+ return NULL;
+ current_page = (queue->queue_pages)[q_offset >> EHCA_PAGESHIFT];
+ return ¤t_page->entries[q_offset & (EHCA_PAGESIZE - 1)];
+}
+
+/*
+ * return current Queue Entry
+ * returns address (kv) of Queue Entry
+ */
+static inline void *ipz_qeit_get(struct ipz_queue *queue)
+{
+ return ipz_qeit_calc(queue, queue->current_q_offset);
+}
+
+/*
+ * return current Queue Page , increment Queue Page iterator from
+ * page to page in struct ipz_queue, last increment will return 0! and
+ * NOT wrap
+ * returns address (kv) of Queue Page
+ * warning don't use in parallel with ipz_QE_get_inc()
+ */
+void *ipz_qpageit_get_inc(struct ipz_queue *queue);
+
+/*
+ * return current Queue Entry, increment Queue Entry iterator by one
+ * step in struct ipz_queue, will wrap in ringbuffer
+ * returns address (kv) of Queue Entry BEFORE increment
+ * warning don't use in parallel with ipz_qpageit_get_inc()
+ * warning unpredictable results may occur if steps>act_nr_of_queue_entries
+ */
+static inline void *ipz_qeit_get_inc(struct ipz_queue *queue)
+{
+ void *ret = ipz_qeit_get(queue);
+ queue->current_q_offset += queue->qe_size;
+ if (queue->current_q_offset >= queue->queue_length) {
+ queue->current_q_offset = 0;
+ /* toggle the valid flag */
+ queue->toggle_state = (~queue->toggle_state) & 1;
+ }
+
+ EDEB(7, "queue=%p ret=%p new current_q_addr=%lx qe_size=%x",
+ queue, ret, queue->current_q_offset, queue->qe_size);
+
+ return ret;
+}
+
+/*
+ * return current Queue Entry, increment Queue Entry iterator by one
+ * step in struct ipz_queue, will wrap in ringbuffer
+ * returns address (kv) of Queue Entry BEFORE increment
+ * returns 0 and does not increment, if wrong valid state
+ * warning don't use in parallel with ipz_qpageit_get_inc()
+ * warning unpredictable results may occur if steps>act_nr_of_queue_entries
+ */
+static inline void *ipz_qeit_get_inc_valid(struct ipz_queue *queue)
+{
+ struct ehca_cqe *cqe = ipz_qeit_get(queue);
+ u32 cqe_flags = cqe->cqe_flags;
+
+ if ((cqe_flags >> 7) != (queue->toggle_state & 1))
+ return NULL;
+
+ ipz_qeit_get_inc(queue);
+ return cqe;
+}
+
+/*
+ * returns and resets Queue Entry iterator
+ * returns address (kv) of first Queue Entry
+ */
+static inline void *ipz_qeit_reset(struct ipz_queue *queue)
+{
+ queue->current_q_offset = 0;
+ return ipz_qeit_get(queue);
+}
+
+/* struct generic page table */
+struct ipz_pt {
+ u64 entries[EHCA_PT_ENTRIES];
+};
+
+/* struct page table for a queue, only to be used in pf */
+struct ipz_qpt {
+ /* queue page tables (kv), use u64 because we know the element length */
+ u64 *qpts;
+ u32 n_qpts;
+ u32 n_ptes; /* number of page table entries */
+ u64 *current_pte_addr;
+};
+
+/*
+ * constructor for a ipz_queue_t, placement new for ipz_queue_t,
+ * new for all dependent datastructors
+ * all QP Tables are the same
+ * flow:
+ * allocate+pin queue
+ * see ipz_qpt_ctor()
+ * returns true if ok, false if out of memory
+ */
+int ipz_queue_ctor(struct ipz_queue *queue, const u32 nr_of_pages,
+ const u32 pagesize, const u32 qe_size,
+ const u32 nr_of_sg);
+
+/*
+ * destructor for a ipz_queue_t
+ * -# free queue
+ * see ipz_queue_ctor()
+ * returns true if ok, false if queue was NULL-ptr of free failed
+ */
+int ipz_queue_dtor(struct ipz_queue *queue);
+
+/*
+ * constructor for a ipz_qpt_t,
+ * placement new for struct ipz_queue, new for all dependent datastructors
+ * all QP Tables are the same,
+ * flow:
+ * -# allocate+pin queue
+ * -# initialise ptcb
+ * -# allocate+pin PTs
+ * -# link PTs to a ring, according to HCA Arch, set bit62 id needed
+ * -# the ring must have room for exactly nr_of_PTEs
+ * see ipz_qpt_ctor()
+ */
+void ipz_qpt_ctor(struct ipz_qpt *qpt,
+ const u32 nr_of_qes,
+ const u32 pagesize,
+ const u32 qe_size,
+ const u8 lowbyte, const u8 toggle,
+ u32 * act_nr_of_QEs, u32 * act_nr_of_pages);
+
+/*
+ * return current Queue Entry, increment Queue Entry iterator by one
+ * step in struct ipz_queue, will wrap in ringbuffer
+ * returns address (kv) of Queue Entry BEFORE increment
+ * warning don't use in parallel with ipz_qpageit_get_inc()
+ * warning unpredictable results may occur if steps>act_nr_of_queue_entries
+ * fix EQ page problems
+ */
+void *ipz_qeit_eq_get_inc(struct ipz_queue *queue);
+
+/*
+ * return current Event Queue Entry, increment Queue Entry iterator
+ * by one step in struct ipz_queue if valid, will wrap in ringbuffer
+ * returns address (kv) of Queue Entry BEFORE increment
+ * returns 0 and does not increment, if wrong valid state
+ * warning don't use in parallel with ipz_queue_QPageit_get_inc()
+ * warning unpredictable results may occur if steps>act_nr_of_queue_entries
+ */
+static inline void *ipz_eqit_eq_get_inc_valid(struct ipz_queue *queue)
+{
+ void *ret = ipz_qeit_get(queue);
+ u32 qe = *(u8 *) ret;
+ EDEB(7, "ipz_QEit_EQ_get_inc_valid qe=%x", qe);
+ if ((qe >> 7) == (queue->toggle_state & 1))
+ ipz_qeit_eq_get_inc(queue); /* this is a good one */
+ else
+ ret = NULL;
+ return ret;
+}
+
+/* returns address (GX) of first queue entry */
+static inline u64 ipz_qpt_get_firstpage(struct ipz_qpt *qpt)
+{
+ return be64_to_cpu(qpt->qpts[0]);
+}
+
+/* returns address (kv) of first page of queue page table */
+static inline void *ipz_qpt_get_qpt(struct ipz_qpt *qpt)
+{
+ return qpt->qpts;
+}
+
+#endif /* __IPZ_PT_FN_H__ */
--
1.4.1
^ permalink raw reply related
* [PATCH 05/13] IB/ehca: avpd
From: Roland Dreier @ 2006-08-17 20:11 UTC (permalink / raw)
To: openib-general, linux-kernel, linuxppc-dev; +Cc: RAISCH, HNGUYEN, MEDER
In-Reply-To: <20068171311.Erm4R4ERt5Mpsgua@cisco.com>
drivers/infiniband/hw/ehca/ehca_av.c | 303 ++++++++++++++++++++++++++++++++++
drivers/infiniband/hw/ehca/ehca_pd.c | 120 +++++++++++++
2 files changed, 423 insertions(+), 0 deletions(-)
diff --git a/drivers/infiniband/hw/ehca/ehca_av.c b/drivers/infiniband/hw/ehca/ehca_av.c
new file mode 100644
index 0000000..fd9fc6d
--- /dev/null
+++ b/drivers/infiniband/hw/ehca/ehca_av.c
@@ -0,0 +1,303 @@
+/*
+ * IBM eServer eHCA Infiniband device driver for Linux on POWER
+ *
+ * adress vector functions
+ *
+ * Authors: Hoang-Nam Nguyen <hnguyen@de.ibm.com>
+ * Khadija Souissi <souissik@de.ibm.com>
+ * Reinhard Ernst <rernst@de.ibm.com>
+ * Christoph Raisch <raisch@de.ibm.com>
+ *
+ * Copyright (c) 2005 IBM Corporation
+ *
+ * All rights reserved.
+ *
+ * This source code is distributed under a dual license of GPL v2.0 and OpenIB
+ * BSD.
+ *
+ * OpenIB BSD License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials
+ * provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
+ * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+#define DEB_PREFIX "ehav"
+
+#include <asm/current.h>
+
+#include "ehca_tools.h"
+#include "ehca_iverbs.h"
+#include "hcp_if.h"
+
+struct ib_ah *ehca_create_ah(struct ib_pd *pd, struct ib_ah_attr *ah_attr)
+{
+ extern struct ehca_module ehca_module;
+ extern int ehca_static_rate;
+ int ret = 0;
+ struct ehca_av *av = NULL;
+ struct ehca_shca *shca = NULL;
+
+ EHCA_CHECK_PD_P(pd);
+ EHCA_CHECK_ADR_P(ah_attr);
+
+ shca = container_of(pd->device, struct ehca_shca, ib_device);
+
+ EDEB_EN(7, "pd=%p ah_attr=%p", pd, ah_attr);
+
+ av = kmem_cache_alloc(ehca_module.cache_av, SLAB_KERNEL);
+ if (!av) {
+ EDEB_ERR(4, "Out of memory pd=%p ah_attr=%p", pd, ah_attr);
+ ret = -ENOMEM;
+ goto create_ah_exit0;
+ }
+
+ av->av.sl = ah_attr->sl;
+ av->av.dlid = ah_attr->dlid;
+ av->av.slid_path_bits = ah_attr->src_path_bits;
+
+ if (ehca_static_rate < 0) {
+ int ah_mult = ib_rate_to_mult(ah_attr->static_rate);
+ int ehca_mult =
+ ib_rate_to_mult(shca->sport[ah_attr->port_num].rate );
+
+ if (ah_mult >= ehca_mult)
+ av->av.ipd = 0;
+ else
+ av->av.ipd = (ah_mult > 0) ?
+ ((ehca_mult - 1) / ah_mult) : 0;
+ } else
+ av->av.ipd = ehca_static_rate;
+
+ EDEB(7, "IPD av->av.ipd set =%x ah_attr->static_rate=%x "
+ "shca_ib_rate=%x ",av->av.ipd, ah_attr->static_rate,
+ shca->sport[ah_attr->port_num].rate);
+
+ av->av.lnh = ah_attr->ah_flags;
+ av->av.grh.word_0 = EHCA_BMASK_SET(GRH_IPVERSION_MASK, 6);
+ av->av.grh.word_0 |= EHCA_BMASK_SET(GRH_TCLASS_MASK,
+ ah_attr->grh.traffic_class);
+ av->av.grh.word_0 |= EHCA_BMASK_SET(GRH_FLOWLABEL_MASK,
+ ah_attr->grh.flow_label);
+ av->av.grh.word_0 |= EHCA_BMASK_SET(GRH_HOPLIMIT_MASK,
+ ah_attr->grh.hop_limit);
+ av->av.grh.word_0 |= EHCA_BMASK_SET(GRH_NEXTHEADER_MASK, 0x1B);
+ /* set sgid in grh.word_1 */
+ if (ah_attr->ah_flags & IB_AH_GRH) {
+ int rc = 0;
+ struct ib_port_attr port_attr;
+ union ib_gid gid;
+ memset(&port_attr, 0, sizeof(port_attr));
+ rc = ehca_query_port(pd->device, ah_attr->port_num,
+ &port_attr);
+ if (rc) { /* invalid port number */
+ ret = -EINVAL;
+ EDEB_ERR(4, "Invalid port number "
+ "ehca_query_port() returned %x "
+ "pd=%p ah_attr=%p", rc, pd, ah_attr);
+ goto create_ah_exit1;
+ }
+ memset(&gid, 0, sizeof(gid));
+ rc = ehca_query_gid(pd->device,
+ ah_attr->port_num,
+ ah_attr->grh.sgid_index, &gid);
+ if (rc) {
+ ret = -EINVAL;
+ EDEB_ERR(4, "Failed to retrieve sgid "
+ "ehca_query_gid() returned %x "
+ "pd=%p ah_attr=%p", rc, pd, ah_attr);
+ goto create_ah_exit1;
+ }
+ memcpy(&av->av.grh.word_1, &gid, sizeof(gid));
+ }
+ /* for the time being we use a hard coded PMTU of 2048 Bytes */
+ av->av.pmtu = 4;
+
+ /* dgid comes in grh.word_3 */
+ memcpy(&av->av.grh.word_3, &ah_attr->grh.dgid,
+ sizeof(ah_attr->grh.dgid));
+
+ EHCA_REGISTER_AV(device, pd);
+
+ EDEB_EX(7, "pd=%p ah_attr=%p av=%p", pd, ah_attr, av);
+ return &av->ib_ah;
+
+create_ah_exit1:
+ kmem_cache_free(ehca_module.cache_av, av);
+
+create_ah_exit0:
+ EDEB_EX(7, "ret=%x pd=%p ah_attr=%p", ret, pd, ah_attr);
+
+ return ERR_PTR(ret);
+}
+
+int ehca_modify_ah(struct ib_ah *ah, struct ib_ah_attr *ah_attr)
+{
+ struct ehca_av *av = NULL;
+ struct ehca_ud_av new_ehca_av;
+ struct ehca_pd *my_pd = NULL;
+ u32 cur_pid = current->tgid;
+ int ret = 0;
+
+ EHCA_CHECK_AV(ah);
+ EHCA_CHECK_ADR(ah_attr);
+
+ EDEB_EN(7, "ah=%p ah_attr=%p", ah, ah_attr);
+
+ my_pd = container_of(ah->pd, struct ehca_pd, ib_pd);
+ if (my_pd->ib_pd.uobject && my_pd->ib_pd.uobject->context &&
+ my_pd->ownpid != cur_pid) {
+ EDEB_ERR(4, "Invalid caller pid=%x ownpid=%x",
+ cur_pid, my_pd->ownpid);
+ return -EINVAL;
+ }
+
+ memset(&new_ehca_av, 0, sizeof(new_ehca_av));
+ new_ehca_av.sl = ah_attr->sl;
+ new_ehca_av.dlid = ah_attr->dlid;
+ new_ehca_av.slid_path_bits = ah_attr->src_path_bits;
+ new_ehca_av.ipd = ah_attr->static_rate;
+ new_ehca_av.lnh = EHCA_BMASK_SET(GRH_FLAG_MASK,
+ (ah_attr->ah_flags & IB_AH_GRH) > 0);
+ new_ehca_av.grh.word_0 = EHCA_BMASK_SET(GRH_TCLASS_MASK,
+ ah_attr->grh.traffic_class);
+ new_ehca_av.grh.word_0 |= EHCA_BMASK_SET(GRH_FLOWLABEL_MASK,
+ ah_attr->grh.flow_label);
+ new_ehca_av.grh.word_0 |= EHCA_BMASK_SET(GRH_HOPLIMIT_MASK,
+ ah_attr->grh.hop_limit);
+ new_ehca_av.grh.word_0 |= EHCA_BMASK_SET(GRH_NEXTHEADER_MASK, 0x1b);
+
+ /* set sgid in grh.word_1 */
+ if (ah_attr->ah_flags & IB_AH_GRH) {
+ int rc = 0;
+ struct ib_port_attr port_attr;
+ union ib_gid gid;
+ memset(&port_attr, 0, sizeof(port_attr));
+ rc = ehca_query_port(ah->device, ah_attr->port_num,
+ &port_attr);
+ if (rc) { /* invalid port number */
+ ret = -EINVAL;
+ EDEB_ERR(4, "Invalid port number "
+ "ehca_query_port() returned %x "
+ "ah=%p ah_attr=%p port_num=%x",
+ rc, ah, ah_attr, ah_attr->port_num);
+ goto modify_ah_exit1;
+ }
+ memset(&gid, 0, sizeof(gid));
+ rc = ehca_query_gid(ah->device,
+ ah_attr->port_num,
+ ah_attr->grh.sgid_index, &gid);
+ if (rc) {
+ ret = -EINVAL;
+ EDEB_ERR(4, "Failed to retrieve sgid "
+ "ehca_query_gid() returned %x "
+ "ah=%p ah_attr=%p port_num=%x "
+ "sgid_index=%x",
+ rc, ah, ah_attr, ah_attr->port_num,
+ ah_attr->grh.sgid_index);
+ goto modify_ah_exit1;
+ }
+ memcpy(&new_ehca_av.grh.word_1, &gid, sizeof(gid));
+ }
+
+ new_ehca_av.pmtu = 4; /* see also comment in create_ah() */
+
+ memcpy(&new_ehca_av.grh.word_3, &ah_attr->grh.dgid,
+ sizeof(ah_attr->grh.dgid));
+
+ av = container_of(ah, struct ehca_av, ib_ah);
+ av->av = new_ehca_av;
+
+modify_ah_exit1:
+ EDEB_EX(7, "ret=%x ah=%p ah_attr=%p", ret, ah, ah_attr);
+
+ return ret;
+}
+
+int ehca_query_ah(struct ib_ah *ah, struct ib_ah_attr *ah_attr)
+{
+ int ret = 0;
+ struct ehca_av *av = NULL;
+ struct ehca_pd *my_pd = NULL;
+ u32 cur_pid = current->tgid;
+
+ EHCA_CHECK_AV(ah);
+ EHCA_CHECK_ADR(ah_attr);
+
+ EDEB_EN(7, "ah=%p ah_attr=%p", ah, ah_attr);
+
+ my_pd = container_of(ah->pd, struct ehca_pd, ib_pd);
+ if (my_pd->ib_pd.uobject && my_pd->ib_pd.uobject->context &&
+ my_pd->ownpid != cur_pid) {
+ EDEB_ERR(4, "Invalid caller pid=%x ownpid=%x",
+ cur_pid, my_pd->ownpid);
+ return -EINVAL;
+ }
+
+ av = container_of(ah, struct ehca_av, ib_ah);
+ memcpy(&ah_attr->grh.dgid, &av->av.grh.word_3,
+ sizeof(ah_attr->grh.dgid));
+ ah_attr->sl = av->av.sl;
+
+ ah_attr->dlid = av->av.dlid;
+
+ ah_attr->src_path_bits = av->av.slid_path_bits;
+ ah_attr->static_rate = av->av.ipd;
+ ah_attr->ah_flags = EHCA_BMASK_GET(GRH_FLAG_MASK, av->av.lnh);
+ ah_attr->grh.traffic_class = EHCA_BMASK_GET(GRH_TCLASS_MASK,
+ av->av.grh.word_0);
+ ah_attr->grh.hop_limit = EHCA_BMASK_GET(GRH_HOPLIMIT_MASK,
+ av->av.grh.word_0);
+ ah_attr->grh.flow_label = EHCA_BMASK_GET(GRH_FLOWLABEL_MASK,
+ av->av.grh.word_0);
+
+ EDEB_EX(7, "ah=%p ah_attr=%p ret=%x", ah, ah_attr, ret);
+ return ret;
+}
+
+int ehca_destroy_ah(struct ib_ah *ah)
+{
+ extern struct ehca_module ehca_module;
+ struct ehca_pd *my_pd = NULL;
+ u32 cur_pid = current->tgid;
+ int ret = 0;
+
+ EHCA_CHECK_AV(ah);
+ EHCA_DEREGISTER_AV(ah);
+
+ EDEB_EN(7, "ah=%p", ah);
+
+ my_pd = container_of(ah->pd, struct ehca_pd, ib_pd);
+ if (my_pd->ib_pd.uobject && my_pd->ib_pd.uobject->context &&
+ my_pd->ownpid != cur_pid) {
+ EDEB_ERR(4, "Invalid caller pid=%x ownpid=%x",
+ cur_pid, my_pd->ownpid);
+ return -EINVAL;
+ }
+
+ kmem_cache_free(ehca_module.cache_av,
+ container_of(ah, struct ehca_av, ib_ah));
+
+ EDEB_EX(7, "ret=%x ah=%p", ret, ah);
+ return ret;
+}
diff --git a/drivers/infiniband/hw/ehca/ehca_pd.c b/drivers/infiniband/hw/ehca/ehca_pd.c
new file mode 100644
index 0000000..afcbe59
--- /dev/null
+++ b/drivers/infiniband/hw/ehca/ehca_pd.c
@@ -0,0 +1,120 @@
+/*
+ * IBM eServer eHCA Infiniband device driver for Linux on POWER
+ *
+ * PD functions
+ *
+ * Authors: Christoph Raisch <raisch@de.ibm.com>
+ *
+ * Copyright (c) 2005 IBM Corporation
+ *
+ * All rights reserved.
+ *
+ * This source code is distributed under a dual license of GPL v2.0 and OpenIB
+ * BSD.
+ *
+ * OpenIB BSD License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials
+ * provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
+ * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+#define DEB_PREFIX "vpd "
+
+#include <asm/current.h>
+
+#include "ehca_tools.h"
+#include "ehca_iverbs.h"
+
+struct ib_pd *ehca_alloc_pd(struct ib_device *device,
+ struct ib_ucontext *context, struct ib_udata *udata)
+{
+ extern struct ehca_module ehca_module;
+ struct ib_pd *mypd = NULL;
+ struct ehca_pd *pd = NULL;
+
+ EDEB_EN(7, "device=%p context=%p udata=%p", device, context, udata);
+
+ EHCA_CHECK_DEVICE_P(device);
+
+ pd = kmem_cache_alloc(ehca_module.cache_pd, SLAB_KERNEL);
+ if (!pd) {
+ EDEB_ERR(4, "ERROR device=%p context=%p pd=%p"
+ " out of memory", device, context, mypd);
+ return ERR_PTR(-ENOMEM);
+ }
+
+ memset(pd, 0, sizeof(struct ehca_pd));
+ pd->ownpid = current->tgid;
+
+ /*
+ * Kernel PD: when device = -1, 0
+ * User PD: when context != -1
+ */
+ if (!context) {
+ /*
+ * Kernel PDs after init reuses always
+ * the one created in ehca_shca_reopen()
+ */
+ struct ehca_shca *shca = container_of(device, struct ehca_shca,
+ ib_device);
+ pd->fw_pd.value = shca->pd->fw_pd.value;
+ } else
+ pd->fw_pd.value = (u64)pd;
+
+ mypd = &pd->ib_pd;
+
+ EHCA_REGISTER_PD(device, pd);
+
+ EDEB_EX(7, "device=%p context=%p pd=%p", device, context, mypd);
+
+ return mypd;
+}
+
+int ehca_dealloc_pd(struct ib_pd *pd)
+{
+ extern struct ehca_module ehca_module;
+ int ret = 0;
+ u32 cur_pid = current->tgid;
+ struct ehca_pd *my_pd = NULL;
+
+ EDEB_EN(7, "pd=%p", pd);
+
+ EHCA_CHECK_PD(pd);
+ my_pd = container_of(pd, struct ehca_pd, ib_pd);
+ if (my_pd->ib_pd.uobject && my_pd->ib_pd.uobject->context &&
+ my_pd->ownpid != cur_pid) {
+ EDEB_ERR(4, "Invalid caller pid=%x ownpid=%x",
+ cur_pid, my_pd->ownpid);
+ return -EINVAL;
+ }
+
+ EHCA_DEREGISTER_PD(pd);
+
+ kmem_cache_free(ehca_module.cache_pd,
+ container_of(pd, struct ehca_pd, ib_pd));
+
+ EDEB_EX(7, "pd=%p", pd);
+
+ return ret;
+}
--
1.4.1
^ permalink raw reply related
* [PATCH 06/13] IB/ehca: eq
From: Roland Dreier @ 2006-08-17 20:11 UTC (permalink / raw)
To: openib-general, linux-kernel, linuxppc-dev; +Cc: RAISCH, HNGUYEN, MEDER
In-Reply-To: <20068171311.8D49tRUe7xsVtB0H@cisco.com>
drivers/infiniband/hw/ehca/ehca_eq.c | 222 ++++++++++++++++++++++++++++++++++
1 files changed, 222 insertions(+), 0 deletions(-)
diff --git a/drivers/infiniband/hw/ehca/ehca_eq.c b/drivers/infiniband/hw/ehca/ehca_eq.c
new file mode 100644
index 0000000..080ed02
--- /dev/null
+++ b/drivers/infiniband/hw/ehca/ehca_eq.c
@@ -0,0 +1,222 @@
+/*
+ * IBM eServer eHCA Infiniband device driver for Linux on POWER
+ *
+ * Event queue handling
+ *
+ * Authors: Waleri Fomin <fomin@de.ibm.com>
+ * Khadija Souissi <souissi@de.ibm.com>
+ * Reinhard Ernst <rernst@de.ibm.com>
+ * Heiko J Schick <schickhj@de.ibm.com>
+ * Hoang-Nam Nguyen <hnguyen@de.ibm.com>
+ *
+ *
+ * Copyright (c) 2005 IBM Corporation
+ *
+ * All rights reserved.
+ *
+ * This source code is distributed under a dual license of GPL v2.0 and OpenIB
+ * BSD.
+ *
+ * OpenIB BSD License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials
+ * provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
+ * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#define DEB_PREFIX "e_eq"
+
+#include "ehca_classes.h"
+#include "ehca_irq.h"
+#include "ehca_iverbs.h"
+#include "ehca_qes.h"
+#include "hcp_if.h"
+#include "ipz_pt_fn.h"
+
+int ehca_create_eq(struct ehca_shca *shca,
+ struct ehca_eq *eq,
+ const enum ehca_eq_type type, const u32 length)
+{
+ u64 ret = H_SUCCESS;
+ u32 nr_pages = 0;
+ u32 i;
+ void *vpage = NULL;
+
+ EDEB_EN(7, "shca=%p eq=%p length=%x", shca, eq, length);
+ EHCA_CHECK_ADR(shca);
+ EHCA_CHECK_ADR(eq);
+
+ spin_lock_init(&eq->spinlock);
+ eq->is_initialized = 0;
+
+ if (type != EHCA_EQ && type != EHCA_NEQ) {
+ EDEB_ERR(4, "Invalid EQ type %x. eq=%p", type, eq);
+ return -EINVAL;
+ }
+ if (length == 0) {
+ EDEB_ERR(4, "EQ length must not be zero. eq=%p", eq);
+ return -EINVAL;
+ }
+
+ ret = hipz_h_alloc_resource_eq(shca->ipz_hca_handle,
+ &eq->pf,
+ type,
+ length,
+ &eq->ipz_eq_handle,
+ &eq->length,
+ &nr_pages, &eq->ist);
+
+ if (ret != H_SUCCESS) {
+ EDEB_ERR(4, "Can't allocate EQ / NEQ. eq=%p", eq);
+ return -EINVAL;
+ }
+
+ ret = ipz_queue_ctor(&eq->ipz_queue, nr_pages,
+ EHCA_PAGESIZE, sizeof(struct ehca_eqe), 0);
+ if (!ret) {
+ EDEB_ERR(4, "Can't allocate EQ pages. eq=%p", eq);
+ goto create_eq_exit1;
+ }
+
+ for (i = 0; i < nr_pages; i++) {
+ u64 rpage;
+
+ if (!(vpage = ipz_qpageit_get_inc(&eq->ipz_queue))) {
+ ret = H_RESOURCE;
+ goto create_eq_exit2;
+ }
+
+ rpage = virt_to_abs(vpage);
+ ret = hipz_h_register_rpage_eq(shca->ipz_hca_handle,
+ eq->ipz_eq_handle,
+ &eq->pf,
+ 0, 0, rpage, 1);
+
+ if (i == (nr_pages - 1)) {
+ /* last page */
+ vpage = ipz_qpageit_get_inc(&eq->ipz_queue);
+ if (ret != H_SUCCESS || vpage)
+ goto create_eq_exit2;
+ } else {
+ if (ret != H_PAGE_REGISTERED || !vpage)
+ goto create_eq_exit2;
+ }
+ }
+
+ ipz_qeit_reset(&eq->ipz_queue);
+
+ /* register interrupt handlers and initialize work queues */
+ if (type == EHCA_EQ) {
+ ret = ibmebus_request_irq(NULL, eq->ist, ehca_interrupt_eq,
+ SA_INTERRUPT, "ehca_eq",
+ (void *)shca);
+ if (ret < 0)
+ EDEB_ERR(4, "Can't map interrupt handler.");
+
+ tasklet_init(&eq->interrupt_task, ehca_tasklet_eq, (long)shca);
+ } else if (type == EHCA_NEQ) {
+ ret = ibmebus_request_irq(NULL, eq->ist, ehca_interrupt_neq,
+ SA_INTERRUPT, "ehca_neq",
+ (void *)shca);
+ if (ret < 0)
+ EDEB_ERR(4, "Can't map interrupt handler.");
+
+ tasklet_init(&eq->interrupt_task, ehca_tasklet_neq, (long)shca);
+ }
+
+ eq->is_initialized = 1;
+
+ EDEB_EX(7, "ret=%lx", ret);
+
+ return 0;
+
+create_eq_exit2:
+ ipz_queue_dtor(&eq->ipz_queue);
+
+create_eq_exit1:
+ hipz_h_destroy_eq(shca->ipz_hca_handle, eq);
+
+ EDEB_EX(7, "ret=%lx", ret);
+
+ return -EINVAL;
+}
+
+void *ehca_poll_eq(struct ehca_shca *shca, struct ehca_eq *eq)
+{
+ unsigned long flags = 0;
+ void *eqe = NULL;
+
+ EDEB_EN(7, "shca=%p eq=%p", shca, eq);
+ EHCA_CHECK_ADR_P(shca);
+ EHCA_CHECK_EQ_P(eq);
+
+ spin_lock_irqsave(&eq->spinlock, flags);
+ eqe = ipz_eqit_eq_get_inc_valid(&eq->ipz_queue);
+ spin_unlock_irqrestore(&eq->spinlock, flags);
+
+ EDEB_EX(7, "eq=%p eqe=%p", eq, eqe);
+
+ return eqe;
+}
+
+void ehca_poll_eqs(unsigned long data)
+{
+ struct ehca_shca *shca;
+ struct ehca_module *module = (struct ehca_module*)data;
+
+ spin_lock(&module->shca_lock);
+ list_for_each_entry(shca, &module->shca_list, shca_list) {
+ if (shca->eq.is_initialized)
+ ehca_tasklet_eq((unsigned long)(void*)shca);
+ }
+ mod_timer(&module->timer, jiffies + HZ);
+ spin_unlock(&module->shca_lock);
+
+ return;
+}
+
+int ehca_destroy_eq(struct ehca_shca *shca, struct ehca_eq *eq)
+{
+ unsigned long flags = 0;
+ u64 h_ret = H_SUCCESS;
+
+ EDEB_EN(7, "shca=%p eq=%p", shca, eq);
+ EHCA_CHECK_ADR(shca);
+ EHCA_CHECK_EQ(eq);
+
+ spin_lock_irqsave(&eq->spinlock, flags);
+ ibmebus_free_irq(NULL, eq->ist, (void *)shca);
+
+ h_ret = hipz_h_destroy_eq(shca->ipz_hca_handle, eq);
+
+ spin_unlock_irqrestore(&eq->spinlock, flags);
+
+ if (h_ret != H_SUCCESS) {
+ EDEB_ERR(4, "Can't free EQ resources.");
+ return -EINVAL;
+ }
+ ipz_queue_dtor(&eq->ipz_queue);
+
+ EDEB_EX(7, "h_ret=%lx", h_ret);
+
+ return h_ret;
+}
--
1.4.1
^ permalink raw reply related
* [PATCH 12/13] IB/ehca: phyp
From: Roland Dreier @ 2006-08-17 20:11 UTC (permalink / raw)
To: openib-general, linux-kernel, linuxppc-dev; +Cc: RAISCH, HNGUYEN, MEDER
In-Reply-To: <20068171311.NYGfAW00YTmK6YKh@cisco.com>
drivers/infiniband/hw/ehca/hcp_phyp.c | 92 ++++++++++++++++++++++++++++++++
drivers/infiniband/hw/ehca/hcp_phyp.h | 96 +++++++++++++++++++++++++++++++++
2 files changed, 188 insertions(+), 0 deletions(-)
diff --git a/drivers/infiniband/hw/ehca/hcp_phyp.c b/drivers/infiniband/hw/ehca/hcp_phyp.c
new file mode 100644
index 0000000..d522d50
--- /dev/null
+++ b/drivers/infiniband/hw/ehca/hcp_phyp.c
@@ -0,0 +1,92 @@
+/*
+ * IBM eServer eHCA Infiniband device driver for Linux on POWER
+ *
+ * load store abstraction for ehca register access with tracing
+ *
+ * Authors: Christoph Raisch <raisch@de.ibm.com>
+ * Hoang-Nam Nguyen <hnguyen@de.ibm.com>
+ *
+ * Copyright (c) 2005 IBM Corporation
+ *
+ * All rights reserved.
+ *
+ * This source code is distributed under a dual license of GPL v2.0 and OpenIB
+ * BSD.
+ *
+ * OpenIB BSD License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials
+ * provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
+ * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#define DEB_PREFIX "PHYP"
+
+#include "ehca_classes.h"
+#include "hipz_hw.h"
+
+int hcall_map_page(u64 physaddr, u64 *mapaddr)
+{
+ *mapaddr = (u64)(ioremap(physaddr, EHCA_PAGESIZE));
+
+ EDEB(7, "ioremap physaddr=%lx mapaddr=%lx", physaddr, *mapaddr);
+ return 0;
+}
+
+int hcall_unmap_page(u64 mapaddr)
+{
+ EDEB(7, "mapaddr=%lx", mapaddr);
+ iounmap((volatile void __iomem*)mapaddr);
+ return 0;
+}
+
+int hcp_galpas_ctor(struct h_galpas *galpas,
+ u64 paddr_kernel, u64 paddr_user)
+{
+ int ret = hcall_map_page(paddr_kernel, &galpas->kernel.fw_handle);
+ if (ret)
+ return ret;
+
+ galpas->user.fw_handle = paddr_user;
+
+ EDEB(7, "paddr_kernel=%lx paddr_user=%lx galpas->kernel=%lx"
+ " galpas->user=%lx",
+ paddr_kernel, paddr_user, galpas->kernel.fw_handle,
+ galpas->user.fw_handle);
+
+ return ret;
+}
+
+int hcp_galpas_dtor(struct h_galpas *galpas)
+{
+ int ret = 0;
+
+ if (galpas->kernel.fw_handle)
+ ret = hcall_unmap_page(galpas->kernel.fw_handle);
+
+ if (ret)
+ return ret;
+
+ galpas->user.fw_handle = galpas->kernel.fw_handle = 0;
+
+ return ret;
+}
diff --git a/drivers/infiniband/hw/ehca/hcp_phyp.h b/drivers/infiniband/hw/ehca/hcp_phyp.h
new file mode 100644
index 0000000..ecb1117
--- /dev/null
+++ b/drivers/infiniband/hw/ehca/hcp_phyp.h
@@ -0,0 +1,96 @@
+/*
+ * IBM eServer eHCA Infiniband device driver for Linux on POWER
+ *
+ * Firmware calls
+ *
+ * Authors: Christoph Raisch <raisch@de.ibm.com>
+ * Hoang-Nam Nguyen <hnguyen@de.ibm.com>
+ * Waleri Fomin <fomin@de.ibm.com>
+ * Gerd Bayer <gerd.bayer@de.ibm.com>
+ *
+ * Copyright (c) 2005 IBM Corporation
+ *
+ * All rights reserved.
+ *
+ * This source code is distributed under a dual license of GPL v2.0 and OpenIB
+ * BSD.
+ *
+ * OpenIB BSD License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials
+ * provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
+ * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __HCP_PHYP_H__
+#define __HCP_PHYP_H__
+
+
+/*
+ * eHCA page (mapped into memory)
+ * resource to access eHCA register pages in CPU address space
+*/
+struct h_galpa {
+ u64 fw_handle;
+ /* for pSeries this is a 64bit memory address where
+ I/O memory is mapped into CPU address space (kv) */
+};
+
+/*
+ * resource to access eHCA address space registers, all types
+ */
+struct h_galpas {
+ u32 pid; /*PID of userspace galpa checking */
+ struct h_galpa user; /* user space accessible resource,
+ set to 0 if unused */
+ struct h_galpa kernel; /* kernel space accessible resource,
+ set to 0 if unused */
+};
+
+static inline u64 hipz_galpa_load(struct h_galpa galpa, u32 offset)
+{
+ u64 addr = galpa.fw_handle + offset;
+ u64 out;
+ EDEB_EN(7, "addr=%lx offset=%x ", addr, offset);
+ out = *(u64 *) addr;
+ EDEB_EX(7, "addr=%lx value=%lx", addr, out);
+ return out;
+}
+
+static inline void hipz_galpa_store(struct h_galpa galpa, u32 offset, u64 value)
+{
+ u64 addr = galpa.fw_handle + offset;
+ EDEB(7, "addr=%lx offset=%x value=%lx", addr,
+ offset, value);
+ *(u64 *) addr = value;
+}
+
+int hcp_galpas_ctor(struct h_galpas *galpas,
+ u64 paddr_kernel, u64 paddr_user);
+
+int hcp_galpas_dtor(struct h_galpas *galpas);
+
+int hcall_map_page(u64 physaddr, u64 * mapaddr);
+
+int hcall_unmap_page(u64 mapaddr);
+
+#endif
--
1.4.1
^ permalink raw reply related
* [PATCH 08/13] IB/ehca: qp
From: Roland Dreier @ 2006-08-17 20:11 UTC (permalink / raw)
To: openib-general, linux-kernel, linuxppc-dev; +Cc: RAISCH, HNGUYEN, MEDER
In-Reply-To: <20068171311.4HUmviC1Ip8J2EpE@cisco.com>
drivers/infiniband/hw/ehca/ehca_qes.h | 259 +++++
drivers/infiniband/hw/ehca/ehca_qp.c | 1594 ++++++++++++++++++++++++++++++++
drivers/infiniband/hw/ehca/ehca_reqs.c | 694 ++++++++++++++
drivers/infiniband/hw/ehca/ehca_sqp.c | 123 ++
4 files changed, 2670 insertions(+), 0 deletions(-)
diff --git a/drivers/infiniband/hw/ehca/ehca_qes.h b/drivers/infiniband/hw/ehca/ehca_qes.h
new file mode 100644
index 0000000..8707d29
--- /dev/null
+++ b/drivers/infiniband/hw/ehca/ehca_qes.h
@@ -0,0 +1,259 @@
+/*
+ * IBM eServer eHCA Infiniband device driver for Linux on POWER
+ *
+ * Hardware request structures
+ *
+ * Authors: Waleri Fomin <fomin@de.ibm.com>
+ * Reinhard Ernst <rernst@de.ibm.com>
+ * Christoph Raisch <raisch@de.ibm.com>
+ *
+ * Copyright (c) 2005 IBM Corporation
+ *
+ * All rights reserved.
+ *
+ * This source code is distributed under a dual license of GPL v2.0 and OpenIB
+ * BSD.
+ *
+ * OpenIB BSD License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials
+ * provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
+ * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+#ifndef _EHCA_QES_H_
+#define _EHCA_QES_H_
+
+#include "ehca_tools.h"
+
+/* virtual scatter gather entry to specify remote adresses with length */
+struct ehca_vsgentry {
+ u64 vaddr;
+ u32 lkey;
+ u32 length;
+};
+
+#define GRH_FLAG_MASK EHCA_BMASK_IBM(7,7)
+#define GRH_IPVERSION_MASK EHCA_BMASK_IBM(0,3)
+#define GRH_TCLASS_MASK EHCA_BMASK_IBM(4,12)
+#define GRH_FLOWLABEL_MASK EHCA_BMASK_IBM(13,31)
+#define GRH_PAYLEN_MASK EHCA_BMASK_IBM(32,47)
+#define GRH_NEXTHEADER_MASK EHCA_BMASK_IBM(48,55)
+#define GRH_HOPLIMIT_MASK EHCA_BMASK_IBM(56,63)
+
+/*
+ * Unreliable Datagram Address Vector Format
+ * see IBTA Vol1 chapter 8.3 Global Routing Header
+ */
+struct ehca_ud_av {
+ u8 sl;
+ u8 lnh;
+ u16 dlid;
+ u8 reserved1;
+ u8 reserved2;
+ u8 reserved3;
+ u8 slid_path_bits;
+ u8 reserved4;
+ u8 ipd;
+ u8 reserved5;
+ u8 pmtu;
+ u32 reserved6;
+ u64 reserved7;
+ union {
+ struct {
+ u64 word_0; /* always set to 6 */
+ /*should be 0x1B for IB transport */
+ u64 word_1;
+ u64 word_2;
+ u64 word_3;
+ u64 word_4;
+ } grh;
+ struct {
+ u32 wd_0;
+ u32 wd_1;
+ /* DWord_1 --> SGID */
+
+ u32 sgid_wd3;
+ u32 sgid_wd2;
+
+ u32 sgid_wd1;
+ u32 sgid_wd0;
+ /* DWord_3 --> DGID */
+
+ u32 dgid_wd3;
+ u32 dgid_wd2;
+
+ u32 dgid_wd1;
+ u32 dgid_wd0;
+ } grh_l;
+ };
+};
+
+/* maximum number of sg entries allowed in a WQE */
+#define MAX_WQE_SG_ENTRIES 252
+
+#define WQE_OPTYPE_SEND 0x80
+#define WQE_OPTYPE_RDMAREAD 0x40
+#define WQE_OPTYPE_RDMAWRITE 0x20
+#define WQE_OPTYPE_CMPSWAP 0x10
+#define WQE_OPTYPE_FETCHADD 0x08
+#define WQE_OPTYPE_BIND 0x04
+
+#define WQE_WRFLAG_REQ_SIGNAL_COM 0x80
+#define WQE_WRFLAG_FENCE 0x40
+#define WQE_WRFLAG_IMM_DATA_PRESENT 0x20
+#define WQE_WRFLAG_SOLIC_EVENT 0x10
+
+#define WQEF_CACHE_HINT 0x80
+#define WQEF_CACHE_HINT_RD_WR 0x40
+#define WQEF_TIMED_WQE 0x20
+#define WQEF_PURGE 0x08
+#define WQEF_HIGH_NIBBLE 0xF0
+
+#define MW_BIND_ACCESSCTRL_R_WRITE 0x40
+#define MW_BIND_ACCESSCTRL_R_READ 0x20
+#define MW_BIND_ACCESSCTRL_R_ATOMIC 0x10
+
+struct ehca_wqe {
+ u64 work_request_id;
+ u8 optype;
+ u8 wr_flag;
+ u16 pkeyi;
+ u8 wqef;
+ u8 nr_of_data_seg;
+ u16 wqe_provided_slid;
+ u32 destination_qp_number;
+ u32 resync_psn_sqp;
+ u32 local_ee_context_qkey;
+ u32 immediate_data;
+ union {
+ struct {
+ u64 remote_virtual_adress;
+ u32 rkey;
+ u32 reserved;
+ u64 atomic_1st_op_dma_len;
+ u64 atomic_2nd_op;
+ struct ehca_vsgentry sg_list[MAX_WQE_SG_ENTRIES];
+
+ } nud;
+ struct {
+ u64 ehca_ud_av_ptr;
+ u64 reserved1;
+ u64 reserved2;
+ u64 reserved3;
+ struct ehca_vsgentry sg_list[MAX_WQE_SG_ENTRIES];
+ } ud_avp;
+ struct {
+ struct ehca_ud_av ud_av;
+ struct ehca_vsgentry sg_list[MAX_WQE_SG_ENTRIES -
+ 2];
+ } ud_av;
+ struct {
+ u64 reserved0;
+ u64 reserved1;
+ u64 reserved2;
+ u64 reserved3;
+ struct ehca_vsgentry sg_list[MAX_WQE_SG_ENTRIES];
+ } all_rcv;
+
+ struct {
+ u64 reserved;
+ u32 rkey;
+ u32 old_rkey;
+ u64 reserved1;
+ u64 reserved2;
+ u64 virtual_address;
+ u32 reserved3;
+ u32 length;
+ u32 reserved4;
+ u16 reserved5;
+ u8 reserved6;
+ u8 lr_ctl;
+ u32 lkey;
+ u32 reserved7;
+ u64 reserved8;
+ u64 reserved9;
+ u64 reserved10;
+ u64 reserved11;
+ } bind;
+ struct {
+ u64 reserved12;
+ u64 reserved13;
+ u32 size;
+ u32 start;
+ } inline_data;
+ } u;
+
+};
+
+#define WC_SEND_RECEIVE EHCA_BMASK_IBM(0,0)
+#define WC_IMM_DATA EHCA_BMASK_IBM(1,1)
+#define WC_GRH_PRESENT EHCA_BMASK_IBM(2,2)
+#define WC_SE_BIT EHCA_BMASK_IBM(3,3)
+#define WC_STATUS_ERROR_BIT 0x80000000
+#define WC_STATUS_REMOTE_ERROR_FLAGS 0x0000F800
+#define WC_STATUS_PURGE_BIT 0x10
+
+struct ehca_cqe {
+ u64 work_request_id;
+ u8 optype;
+ u8 w_completion_flags;
+ u16 reserved1;
+ u32 nr_bytes_transferred;
+ u32 immediate_data;
+ u32 local_qp_number;
+ u8 freed_resource_count;
+ u8 service_level;
+ u16 wqe_count;
+ u32 qp_token;
+ u32 qkey_ee_token;
+ u32 remote_qp_number;
+ u16 dlid;
+ u16 rlid;
+ u16 reserved2;
+ u16 pkey_index;
+ u32 cqe_timestamp;
+ u32 wqe_timestamp;
+ u8 wqe_timestamp_valid;
+ u8 reserved3;
+ u8 reserved4;
+ u8 cqe_flags;
+ u32 status;
+};
+
+struct ehca_eqe {
+ u64 entry;
+};
+
+struct ehca_mrte {
+ u64 starting_va;
+ u64 length; /* length of memory region in bytes*/
+ u32 pd;
+ u8 key_instance;
+ u8 pagesize;
+ u8 mr_control;
+ u8 local_remote_access_ctrl;
+ u8 reserved[0x20 - 0x18];
+ u64 at_pointer[4];
+};
+#endif /*_EHCA_QES_H_*/
diff --git a/drivers/infiniband/hw/ehca/ehca_qp.c b/drivers/infiniband/hw/ehca/ehca_qp.c
new file mode 100644
index 0000000..011afa6
--- /dev/null
+++ b/drivers/infiniband/hw/ehca/ehca_qp.c
@@ -0,0 +1,1594 @@
+/*
+ * IBM eServer eHCA Infiniband device driver for Linux on POWER
+ *
+ * QP functions
+ *
+ * Authors: Waleri Fomin <fomin@de.ibm.com>
+ * Hoang-Nam Nguyen <hnguyen@de.ibm.com>
+ * Reinhard Ernst <rernst@de.ibm.com>
+ * Heiko J Schick <schickhj@de.ibm.com>
+ *
+ * Copyright (c) 2005 IBM Corporation
+ *
+ * All rights reserved.
+ *
+ * This source code is distributed under a dual license of GPL v2.0 and OpenIB
+ * BSD.
+ *
+ * OpenIB BSD License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials
+ * provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
+ * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+#define DEB_PREFIX "e_qp"
+
+#include <asm/current.h>
+
+#include "ehca_classes.h"
+#include "ehca_tools.h"
+#include "ehca_qes.h"
+#include "ehca_iverbs.h"
+#include "hcp_if.h"
+#include "hipz_fns.h"
+
+/*
+ * attributes not supported by query qp
+ */
+#define QP_ATTR_QUERY_NOT_SUPPORTED (IB_QP_MAX_DEST_RD_ATOMIC | \
+ IB_QP_MAX_QP_RD_ATOMIC | \
+ IB_QP_ACCESS_FLAGS | \
+ IB_QP_EN_SQD_ASYNC_NOTIFY)
+
+/*
+ * ehca (internal) qp state values
+ */
+enum ehca_qp_state {
+ EHCA_QPS_RESET = 1,
+ EHCA_QPS_INIT = 2,
+ EHCA_QPS_RTR = 3,
+ EHCA_QPS_RTS = 5,
+ EHCA_QPS_SQD = 6,
+ EHCA_QPS_SQE = 8,
+ EHCA_QPS_ERR = 128
+};
+
+/*
+ * qp state transitions as defined by IB Arch Rel 1.1 page 431
+ */
+enum ib_qp_statetrans {
+ IB_QPST_ANY2RESET,
+ IB_QPST_ANY2ERR,
+ IB_QPST_RESET2INIT,
+ IB_QPST_INIT2RTR,
+ IB_QPST_INIT2INIT,
+ IB_QPST_RTR2RTS,
+ IB_QPST_RTS2SQD,
+ IB_QPST_RTS2RTS,
+ IB_QPST_SQD2RTS,
+ IB_QPST_SQE2RTS,
+ IB_QPST_SQD2SQD,
+ IB_QPST_MAX /* nr of transitions, this must be last!!! */
+};
+
+/*
+ * ib2ehca_qp_state maps IB to ehca qp_state
+ * returns ehca qp state corresponding to given ib qp state
+ */
+static inline enum ehca_qp_state ib2ehca_qp_state(enum ib_qp_state ib_qp_state)
+{
+ switch (ib_qp_state) {
+ case IB_QPS_RESET:
+ return EHCA_QPS_RESET;
+ case IB_QPS_INIT:
+ return EHCA_QPS_INIT;
+ case IB_QPS_RTR:
+ return EHCA_QPS_RTR;
+ case IB_QPS_RTS:
+ return EHCA_QPS_RTS;
+ case IB_QPS_SQD:
+ return EHCA_QPS_SQD;
+ case IB_QPS_SQE:
+ return EHCA_QPS_SQE;
+ case IB_QPS_ERR:
+ return EHCA_QPS_ERR;
+ default:
+ EDEB_ERR(4, "invalid ib_qp_state=%x", ib_qp_state);
+ return -EINVAL;
+ }
+}
+
+/*
+ * ehca2ib_qp_state maps ehca to IB qp_state
+ * returns ib qp state corresponding to given ehca qp state
+ */
+static inline enum ib_qp_state ehca2ib_qp_state(enum ehca_qp_state
+ ehca_qp_state)
+{
+ switch (ehca_qp_state) {
+ case EHCA_QPS_RESET:
+ return IB_QPS_RESET;
+ case EHCA_QPS_INIT:
+ return IB_QPS_INIT;
+ case EHCA_QPS_RTR:
+ return IB_QPS_RTR;
+ case EHCA_QPS_RTS:
+ return IB_QPS_RTS;
+ case EHCA_QPS_SQD:
+ return IB_QPS_SQD;
+ case EHCA_QPS_SQE:
+ return IB_QPS_SQE;
+ case EHCA_QPS_ERR:
+ return IB_QPS_ERR;
+ default:
+ EDEB_ERR(4,"invalid ehca_qp_state=%x",ehca_qp_state);
+ return -EINVAL;
+ }
+}
+
+/*
+ * ehca_qp_type used as index for req_attr and opt_attr of
+ * struct ehca_modqp_statetrans
+ */
+enum ehca_qp_type {
+ QPT_RC = 0,
+ QPT_UC = 1,
+ QPT_UD = 2,
+ QPT_SQP = 3,
+ QPT_MAX
+};
+
+/*
+ * ib2ehcaqptype maps Ib to ehca qp_type
+ * returns ehca qp type corresponding to ib qp type
+ */
+static inline enum ehca_qp_type ib2ehcaqptype(enum ib_qp_type ibqptype)
+{
+ switch (ibqptype) {
+ case IB_QPT_SMI:
+ case IB_QPT_GSI:
+ return QPT_SQP;
+ case IB_QPT_RC:
+ return QPT_RC;
+ case IB_QPT_UC:
+ return QPT_UC;
+ case IB_QPT_UD:
+ return QPT_UD;
+ default:
+ EDEB_ERR(4,"Invalid ibqptype=%x", ibqptype);
+ return -EINVAL;
+ }
+}
+
+static inline enum ib_qp_statetrans get_modqp_statetrans(int ib_fromstate,
+ int ib_tostate)
+{
+ int index = -EINVAL;
+ switch (ib_tostate) {
+ case IB_QPS_RESET:
+ index = IB_QPST_ANY2RESET;
+ break;
+ case IB_QPS_INIT:
+ if (ib_fromstate == IB_QPS_RESET)
+ index = IB_QPST_RESET2INIT;
+ else if (ib_fromstate == IB_QPS_INIT)
+ index = IB_QPST_INIT2INIT;
+ break;
+ case IB_QPS_RTR:
+ if (ib_fromstate == IB_QPS_INIT)
+ index = IB_QPST_INIT2RTR;
+ break;
+ case IB_QPS_RTS:
+ if (ib_fromstate == IB_QPS_RTR)
+ index = IB_QPST_RTR2RTS;
+ else if (ib_fromstate == IB_QPS_RTS)
+ index = IB_QPST_RTS2RTS;
+ else if (ib_fromstate == IB_QPS_SQD)
+ index = IB_QPST_SQD2RTS;
+ else if (ib_fromstate == IB_QPS_SQE)
+ index = IB_QPST_SQE2RTS;
+ break;
+ case IB_QPS_SQD:
+ if (ib_fromstate == IB_QPS_RTS)
+ index = IB_QPST_RTS2SQD;
+ break;
+ case IB_QPS_SQE:
+ break;
+ case IB_QPS_ERR:
+ index = IB_QPST_ANY2ERR;
+ break;
+ default:
+ break;
+ }
+ return index;
+}
+
+enum ehca_service_type {
+ ST_RC = 0,
+ ST_UC = 1,
+ ST_RD = 2,
+ ST_UD = 3
+};
+
+/*
+ * ibqptype2servicetype returns hcp service type corresponding to given
+ * ib qp type used by create_qp()
+ */
+static inline int ibqptype2servicetype(enum ib_qp_type ibqptype)
+{
+ switch (ibqptype) {
+ case IB_QPT_SMI:
+ case IB_QPT_GSI:
+ return ST_UD;
+ case IB_QPT_RC:
+ return ST_RC;
+ case IB_QPT_UC:
+ return ST_UC;
+ case IB_QPT_UD:
+ return ST_UD;
+ case IB_QPT_RAW_IPV6:
+ return -EINVAL;
+ case IB_QPT_RAW_ETY:
+ return -EINVAL;
+ default:
+ EDEB_ERR(4, "Invalid ibqptype=%x", ibqptype);
+ return -EINVAL;
+ }
+}
+
+/*
+ * init_qp_queues initializes/constructs r/squeue and registers queue pages.
+ */
+static inline int init_qp_queues(struct ipz_adapter_handle ipz_hca_handle,
+ struct ehca_qp *my_qp,
+ int nr_sq_pages,
+ int nr_rq_pages,
+ int swqe_size,
+ int rwqe_size,
+ int nr_send_sges, int nr_receive_sges)
+{
+ int ret = -EINVAL;
+ int cnt = 0;
+ void *vpage = NULL;
+ u64 rpage = 0;
+ int ipz_rc = -1;
+ u64 h_ret = H_PARAMETER;
+
+ ipz_rc = ipz_queue_ctor(&my_qp->ipz_squeue,
+ nr_sq_pages,
+ EHCA_PAGESIZE, swqe_size, nr_send_sges);
+ if (!ipz_rc) {
+ EDEB_ERR(4, "Cannot allocate page for squeue. ipz_rc=%x",
+ ipz_rc);
+ ret = -EBUSY;
+ return ret;
+ }
+
+ ipz_rc = ipz_queue_ctor(&my_qp->ipz_rqueue,
+ nr_rq_pages,
+ EHCA_PAGESIZE, rwqe_size, nr_receive_sges);
+ if (!ipz_rc) {
+ EDEB_ERR(4, "Cannot allocate page for rqueue. ipz_rc=%x",
+ ipz_rc);
+ ret = -EBUSY;
+ goto init_qp_queues0;
+ }
+ /* register SQ pages */
+ for (cnt = 0; cnt < nr_sq_pages; cnt++) {
+ vpage = ipz_qpageit_get_inc(&my_qp->ipz_squeue);
+ if (!vpage) {
+ EDEB_ERR(4, "SQ ipz_qpageit_get_inc() "
+ "failed p_vpage= %p", vpage);
+ ret = -EINVAL;
+ goto init_qp_queues1;
+ }
+ rpage = virt_to_abs(vpage);
+
+ h_ret = hipz_h_register_rpage_qp(ipz_hca_handle,
+ my_qp->ipz_qp_handle,
+ &my_qp->pf, 0, 0,
+ rpage, 1,
+ my_qp->galpas.kernel);
+ if (h_ret < H_SUCCESS) {
+ EDEB_ERR(4,"SQ hipz_qp_register_rpage() faield "
+ "rc=%lx", h_ret);
+ ret = ehca2ib_return_code(h_ret);
+ goto init_qp_queues1;
+ }
+ }
+
+ ipz_qeit_reset(&my_qp->ipz_squeue);
+
+ /* register RQ pages */
+ for (cnt = 0; cnt < nr_rq_pages; cnt++) {
+ vpage = ipz_qpageit_get_inc(&my_qp->ipz_rqueue);
+ if (!vpage) {
+ EDEB_ERR(4,"RQ ipz_qpageit_get_inc() "
+ "failed p_vpage = %p", vpage);
+ h_ret = H_RESOURCE;
+ ret = -EINVAL;
+ goto init_qp_queues1;
+ }
+
+ rpage = virt_to_abs(vpage);
+
+ h_ret = hipz_h_register_rpage_qp(ipz_hca_handle,
+ my_qp->ipz_qp_handle,
+ &my_qp->pf, 0, 1,
+ rpage, 1,my_qp->galpas.kernel);
+ if (h_ret < H_SUCCESS) {
+ EDEB_ERR(4, "RQ hipz_qp_register_rpage() failed "
+ "rc=%lx", h_ret);
+ ret = ehca2ib_return_code(h_ret);
+ goto init_qp_queues1;
+ }
+ if (cnt == (nr_rq_pages - 1)) { /* last page! */
+ if (h_ret != H_SUCCESS) {
+ EDEB_ERR(4,"RQ hipz_qp_register_rpage() "
+ "h_ret= %lx ", h_ret);
+ ret = ehca2ib_return_code(h_ret);
+ goto init_qp_queues1;
+ }
+ vpage = ipz_qpageit_get_inc(&my_qp->ipz_rqueue);
+ if (vpage) {
+ EDEB_ERR(4,"ipz_qpageit_get_inc() "
+ "should not succeed vpage=%p",
+ vpage);
+ ret = -EINVAL;
+ goto init_qp_queues1;
+ }
+ } else {
+ if (h_ret != H_PAGE_REGISTERED) {
+ EDEB_ERR(4,"RQ hipz_qp_register_rpage() "
+ "h_ret= %lx ", h_ret);
+ ret = ehca2ib_return_code(h_ret);
+ goto init_qp_queues1;
+ }
+ }
+ }
+
+ ipz_qeit_reset(&my_qp->ipz_rqueue);
+
+ return 0;
+
+init_qp_queues1:
+ ipz_queue_dtor(&my_qp->ipz_rqueue);
+init_qp_queues0:
+ ipz_queue_dtor(&my_qp->ipz_squeue);
+ return ret;
+}
+
+
+struct ib_qp *ehca_create_qp(struct ib_pd *pd,
+ struct ib_qp_init_attr *init_attr,
+ struct ib_udata *udata)
+{
+ extern struct ehca_module ehca_module;
+ static int da_msg_size[]={ 128, 256, 512, 1024, 2048, 4096 };
+ int ret = -EINVAL;
+
+ struct ehca_qp *my_qp = NULL;
+ struct ehca_pd *my_pd = NULL;
+ struct ehca_shca *shca = NULL;
+ struct ib_ucontext *context = NULL;
+ u64 h_ret = H_PARAMETER;
+ int max_send_sge;
+ int max_recv_sge;
+
+ /* h_call's out parameters */
+ struct ehca_alloc_qp_parms parms;
+ u32 qp_nr = 0, swqe_size = 0, rwqe_size = 0;
+ u8 daqp_completion, isdaqp;
+ unsigned long flags;
+
+ EDEB_EN(7,"pd=%p init_attr=%p", pd, init_attr);
+ EHCA_CHECK_PD_P(pd);
+ EHCA_CHECK_ADR_P(init_attr);
+
+ if (init_attr->sq_sig_type != IB_SIGNAL_REQ_WR &&
+ init_attr->sq_sig_type != IB_SIGNAL_ALL_WR) {
+ EDEB_ERR(4, "init_attr->sg_sig_type=%x not allowed",
+ init_attr->sq_sig_type);
+ return ERR_PTR(-EINVAL);
+ }
+
+ /* save daqp completion bits */
+ daqp_completion = init_attr->qp_type & 0x60;
+ /* save daqp bit */
+ isdaqp = (init_attr->qp_type & 0x80) ? 1 : 0;
+ init_attr->qp_type = init_attr->qp_type & 0x1F;
+
+ if (init_attr->qp_type != IB_QPT_UD &&
+ init_attr->qp_type != IB_QPT_SMI &&
+ init_attr->qp_type != IB_QPT_GSI &&
+ init_attr->qp_type != IB_QPT_UC &&
+ init_attr->qp_type != IB_QPT_RC) {
+ EDEB_ERR(4,"wrong QP Type=%x",init_attr->qp_type);
+ return ERR_PTR(-EINVAL);
+ }
+ if (init_attr->qp_type != IB_QPT_RC && isdaqp != 0) {
+ EDEB_ERR(4,"unsupported LL QP Type=%x",init_attr->qp_type);
+ return ERR_PTR(-EINVAL);
+ }
+
+ if (pd->uobject && udata)
+ context = pd->uobject->context;
+
+ my_qp = kmem_cache_alloc(ehca_module.cache_qp, SLAB_KERNEL);
+ if (!my_qp) {
+ EDEB_ERR(4, "pd=%p not enough memory to alloc qp", pd);
+ return ERR_PTR(-ENOMEM);
+ }
+
+ memset(my_qp, 0, sizeof(struct ehca_qp));
+ memset (&parms, 0, sizeof(struct ehca_alloc_qp_parms));
+ spin_lock_init(&my_qp->spinlock_s);
+ spin_lock_init(&my_qp->spinlock_r);
+
+ my_pd = container_of(pd, struct ehca_pd, ib_pd);
+
+ shca = container_of(pd->device, struct ehca_shca, ib_device);
+ my_qp->recv_cq =
+ container_of(init_attr->recv_cq, struct ehca_cq, ib_cq);
+ my_qp->send_cq =
+ container_of(init_attr->send_cq, struct ehca_cq, ib_cq);
+
+ my_qp->init_attr = *init_attr;
+
+ do {
+ if (!idr_pre_get(&ehca_qp_idr, GFP_KERNEL)) {
+ ret = -ENOMEM;
+ EDEB_ERR(4, "Can't reserve idr resources.");
+ goto create_qp_exit0;
+ }
+
+ spin_lock_irqsave(&ehca_qp_idr_lock, flags);
+ ret = idr_get_new(&ehca_qp_idr, my_qp, &my_qp->token);
+ spin_unlock_irqrestore(&ehca_qp_idr_lock, flags);
+
+ } while (ret == -EAGAIN);
+
+ if (ret) {
+ ret = -ENOMEM;
+ EDEB_ERR(4, "Can't allocate new idr entry.");
+ goto create_qp_exit0;
+ }
+
+ parms.servicetype = ibqptype2servicetype(init_attr->qp_type);
+ if (parms.servicetype < 0) {
+ ret = -EINVAL;
+ EDEB_ERR(4, "Invalid qp_type=%x", init_attr->qp_type);
+ goto create_qp_exit0;
+ }
+
+ if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
+ parms.sigtype = HCALL_SIGT_EVERY;
+ else
+ parms.sigtype = HCALL_SIGT_BY_WQE;
+
+ /* UD_AV CIRCUMVENTION */
+ max_send_sge = init_attr->cap.max_send_sge;
+ max_recv_sge = init_attr->cap.max_recv_sge;
+ if (IB_QPT_UD == init_attr->qp_type ||
+ IB_QPT_GSI == init_attr->qp_type ||
+ IB_QPT_SMI == init_attr->qp_type) {
+ max_send_sge += 2;
+ max_recv_sge += 2;
+ }
+
+ EDEB(7, "isdaqp=%x daqp_completion=%x", isdaqp, daqp_completion);
+
+ parms.ipz_eq_handle = shca->eq.ipz_eq_handle;
+ parms.daqp_ctrl = isdaqp | daqp_completion;
+ parms.pd = my_pd->fw_pd;
+ parms.max_recv_sge = max_recv_sge;
+ parms.max_send_sge = max_send_sge;
+
+ h_ret = hipz_h_alloc_resource_qp(shca->ipz_hca_handle, my_qp, &parms);
+
+ if (h_ret != H_SUCCESS) {
+ EDEB_ERR(4, "h_alloc_resource_qp() failed h_ret=%lx", h_ret);
+ ret = ehca2ib_return_code(h_ret);
+ goto create_qp_exit1;
+ }
+
+ switch (init_attr->qp_type) {
+ case IB_QPT_RC:
+ if (isdaqp == 0) {
+ swqe_size = offsetof(struct ehca_wqe, u.nud.sg_list[
+ (parms.act_nr_send_sges)]);
+ rwqe_size = offsetof(struct ehca_wqe, u.nud.sg_list[
+ (parms.act_nr_recv_sges)]);
+ } else { /* for daqp we need to use msg size, not wqe size */
+ swqe_size = da_msg_size[max_send_sge];
+ rwqe_size = da_msg_size[max_recv_sge];
+ parms.act_nr_send_sges = 1;
+ parms.act_nr_recv_sges = 1;
+ }
+ break;
+ case IB_QPT_UC:
+ swqe_size = offsetof(struct ehca_wqe,
+ u.nud.sg_list[parms.act_nr_send_sges]);
+ rwqe_size = offsetof(struct ehca_wqe,
+ u.nud.sg_list[parms.act_nr_recv_sges]);
+ break;
+
+ case IB_QPT_UD:
+ case IB_QPT_GSI:
+ case IB_QPT_SMI:
+ /* UD circumvention */
+ parms.act_nr_recv_sges -= 2;
+ parms.act_nr_send_sges -= 2;
+ swqe_size = offsetof(struct ehca_wqe,
+ u.ud_av.sg_list[parms.act_nr_send_sges]);
+ rwqe_size = offsetof(struct ehca_wqe,
+ u.ud_av.sg_list[parms.act_nr_recv_sges]);
+
+ if (IB_QPT_GSI == init_attr->qp_type ||
+ IB_QPT_SMI == init_attr->qp_type) {
+ parms.act_nr_send_wqes = init_attr->cap.max_send_wr;
+ parms.act_nr_recv_wqes = init_attr->cap.max_recv_wr;
+ parms.act_nr_send_sges = init_attr->cap.max_send_sge;
+ parms.act_nr_recv_sges = init_attr->cap.max_recv_sge;
+ my_qp->real_qp_num =
+ (init_attr->qp_type == IB_QPT_SMI) ? 0 : 1;
+ }
+
+ break;
+
+ default:
+ break;
+ }
+
+ /* initializes r/squeue and registers queue pages */
+ ret = init_qp_queues(shca->ipz_hca_handle, my_qp,
+ parms.nr_sq_pages, parms.nr_rq_pages,
+ swqe_size, rwqe_size,
+ parms.act_nr_send_sges, parms.act_nr_recv_sges);
+ if (ret) {
+ EDEB_ERR(4,"Couldn't initialize r/squeue and pages ret=%x",
+ ret);
+ goto create_qp_exit2;
+ }
+
+ my_qp->ib_qp.pd = &my_pd->ib_pd;
+ my_qp->ib_qp.device = my_pd->ib_pd.device;
+
+ my_qp->ib_qp.recv_cq = init_attr->recv_cq;
+ my_qp->ib_qp.send_cq = init_attr->send_cq;
+
+ my_qp->ib_qp.qp_num = my_qp->real_qp_num;
+ my_qp->ib_qp.qp_type = init_attr->qp_type;
+
+ my_qp->qp_type = init_attr->qp_type;
+ my_qp->ib_qp.srq = init_attr->srq;
+
+ my_qp->ib_qp.qp_context = init_attr->qp_context;
+ my_qp->ib_qp.event_handler = init_attr->event_handler;
+
+ init_attr->cap.max_inline_data = 0; /* not supported yet */
+ init_attr->cap.max_recv_sge = parms.act_nr_recv_sges;
+ init_attr->cap.max_recv_wr = parms.act_nr_recv_wqes;
+ init_attr->cap.max_send_sge = parms.act_nr_send_sges;
+ init_attr->cap.max_send_wr = parms.act_nr_send_wqes;
+
+ /* NOTE: define_apq0() not supported yet */
+ if (init_attr->qp_type == IB_QPT_GSI) {
+ h_ret = ehca_define_sqp(shca, my_qp, init_attr);
+ if (h_ret != H_SUCCESS) {
+ EDEB_ERR(4, "ehca_define_sqp() failed rc=%lx",h_ret);
+ ret = ehca2ib_return_code(h_ret);
+ goto create_qp_exit3;
+ }
+ }
+ if (init_attr->send_cq) {
+ struct ehca_cq *cq = container_of(init_attr->send_cq,
+ struct ehca_cq, ib_cq);
+ ret = ehca_cq_assign_qp(cq, my_qp);
+ if (ret) {
+ EDEB_ERR(4, "Couldn't assign qp to send_cq ret=%x",
+ ret);
+ goto create_qp_exit3;
+ }
+ my_qp->send_cq = cq;
+ }
+ /* copy queues, galpa data to user space */
+ if (context && udata) {
+ struct ipz_queue *ipz_rqueue = &my_qp->ipz_rqueue;
+ struct ipz_queue *ipz_squeue = &my_qp->ipz_squeue;
+ struct ehca_create_qp_resp resp;
+ struct vm_area_struct * vma;
+ memset(&resp, 0, sizeof(resp));
+
+ resp.qp_num = my_qp->real_qp_num;
+ resp.token = my_qp->token;
+ resp.qp_type = my_qp->qp_type;
+ resp.qkey = my_qp->qkey;
+ resp.real_qp_num = my_qp->real_qp_num;
+ /* rqueue properties */
+ resp.ipz_rqueue.qe_size = ipz_rqueue->qe_size;
+ resp.ipz_rqueue.act_nr_of_sg = ipz_rqueue->act_nr_of_sg;
+ resp.ipz_rqueue.queue_length = ipz_rqueue->queue_length;
+ resp.ipz_rqueue.pagesize = ipz_rqueue->pagesize;
+ resp.ipz_rqueue.toggle_state = ipz_rqueue->toggle_state;
+ ret = ehca_mmap_nopage(((u64)(my_qp->token) << 32) | 0x22000000,
+ ipz_rqueue->queue_length,
+ (void**)&resp.ipz_rqueue.queue,
+ &vma);
+ if (ret) {
+ EDEB_ERR(4, "Could not mmap rqueue pages");
+ goto create_qp_exit3;
+ }
+ my_qp->uspace_rqueue = resp.ipz_rqueue.queue;
+ /* squeue properties */
+ resp.ipz_squeue.qe_size = ipz_squeue->qe_size;
+ resp.ipz_squeue.act_nr_of_sg = ipz_squeue->act_nr_of_sg;
+ resp.ipz_squeue.queue_length = ipz_squeue->queue_length;
+ resp.ipz_squeue.pagesize = ipz_squeue->pagesize;
+ resp.ipz_squeue.toggle_state = ipz_squeue->toggle_state;
+ ret = ehca_mmap_nopage(((u64)(my_qp->token) << 32) | 0x23000000,
+ ipz_squeue->queue_length,
+ (void**)&resp.ipz_squeue.queue,
+ &vma);
+ if (ret) {
+ EDEB_ERR(4, "Could not mmap squeue pages");
+ goto create_qp_exit4;
+ }
+ my_qp->uspace_squeue = resp.ipz_squeue.queue;
+ /* fw_handle */
+ resp.galpas = my_qp->galpas;
+ ret = ehca_mmap_register(my_qp->galpas.user.fw_handle,
+ (void**)&resp.galpas.kernel.fw_handle,
+ &vma);
+ if (ret) {
+ EDEB_ERR(4, "Could not mmap fw_handle");
+ goto create_qp_exit5;
+ }
+ my_qp->uspace_fwh = (u64)resp.galpas.kernel.fw_handle;
+
+ if (ib_copy_to_udata(udata, &resp, sizeof resp)) {
+ EDEB_ERR(4, "Copy to udata failed");
+ ret = -EINVAL;
+ goto create_qp_exit6;
+ }
+ }
+
+ EDEB_EX(7, "ehca_qp=%p qp_num=%x, token=%x",
+ my_qp, qp_nr, my_qp->token);
+ return &my_qp->ib_qp;
+
+create_qp_exit6:
+ ehca_munmap(my_qp->uspace_fwh, EHCA_PAGESIZE);
+
+create_qp_exit5:
+ ehca_munmap(my_qp->uspace_squeue, my_qp->ipz_squeue.queue_length);
+
+create_qp_exit4:
+ ehca_munmap(my_qp->uspace_rqueue, my_qp->ipz_rqueue.queue_length);
+
+create_qp_exit3:
+ ipz_queue_dtor(&my_qp->ipz_rqueue);
+ ipz_queue_dtor(&my_qp->ipz_squeue);
+
+create_qp_exit2:
+ hipz_h_destroy_qp(shca->ipz_hca_handle, my_qp);
+
+create_qp_exit1:
+ spin_lock_irqsave(&ehca_qp_idr_lock, flags);
+ idr_remove(&ehca_qp_idr, my_qp->token);
+ spin_unlock_irqrestore(&ehca_qp_idr_lock, flags);
+
+create_qp_exit0:
+ kmem_cache_free(ehca_module.cache_qp, my_qp);
+ EDEB_EX(4, "failed ret=%x", ret);
+ return ERR_PTR(ret);
+
+}
+
+/*
+ * prepare_sqe_rts called by internal_modify_qp() at trans sqe -> rts
+ * set purge bit of bad wqe and subsequent wqes to avoid reentering sqe
+ * returns total number of bad wqes in bad_wqe_cnt
+ */
+static int prepare_sqe_rts(struct ehca_qp *my_qp, struct ehca_shca *shca,
+ int *bad_wqe_cnt)
+{
+ int ret = 0;
+ u64 h_ret = H_SUCCESS;
+ struct ipz_queue *squeue = NULL;
+ void *bad_send_wqe_p = NULL;
+ void *bad_send_wqe_v = NULL;
+ void *squeue_start_p = NULL;
+ void *squeue_end_p = NULL;
+ void *squeue_start_v = NULL;
+ void *squeue_end_v = NULL;
+ struct ehca_wqe *wqe = NULL;
+ int qp_num = my_qp->ib_qp.qp_num;
+
+ EDEB_EN(7, "ehca_qp=%p qp_num=%x ", my_qp, qp_num);
+
+ /* get send wqe pointer */
+ h_ret = hipz_h_disable_and_get_wqe(shca->ipz_hca_handle,
+ my_qp->ipz_qp_handle, &my_qp->pf,
+ &bad_send_wqe_p, NULL, 2);
+ if (h_ret != H_SUCCESS) {
+ EDEB_ERR(4, "hipz_h_disable_and_get_wqe() failed "
+ "ehca_qp=%p qp_num=%x h_ret=%lx",my_qp, qp_num, h_ret);
+ ret = ehca2ib_return_code(h_ret);
+ goto prepare_sqe_rts_exit1;
+ }
+ bad_send_wqe_p = (void*)((u64)bad_send_wqe_p & (~(1L<<63)));
+ EDEB(7, "qp_num=%x bad_send_wqe_p=%p", qp_num, bad_send_wqe_p);
+ /* convert wqe pointer to vadr */
+ bad_send_wqe_v = abs_to_virt((u64)bad_send_wqe_p);
+ EDEB_DMP(6, bad_send_wqe_v, 32, "qp_num=%x bad_wqe", qp_num);
+ squeue = &my_qp->ipz_squeue;
+ squeue_start_p = (void*)virt_to_abs(ipz_qeit_calc(squeue, 0L));
+ squeue_end_p = squeue_start_p+squeue->queue_length;
+ squeue_start_v = abs_to_virt((u64)squeue_start_p);
+ squeue_end_v = abs_to_virt((u64)squeue_end_p);
+ EDEB(6, "qp_num=%x squeue_start_v=%p squeue_end_v=%p",
+ qp_num, squeue_start_v, squeue_end_v);
+
+ /* loop sets wqe's purge bit */
+ wqe = (struct ehca_wqe*)bad_send_wqe_v;
+ *bad_wqe_cnt = 0;
+ while (wqe->optype != 0xff && wqe->wqef != 0xff) {
+ EDEB_DMP(6, wqe, 32, "qp_num=%x wqe", qp_num);
+ wqe->nr_of_data_seg = 0; /* suppress data access */
+ wqe->wqef = WQEF_PURGE; /* WQE to be purged */
+ wqe = (struct ehca_wqe*)((u8*)wqe+squeue->qe_size);
+ *bad_wqe_cnt = (*bad_wqe_cnt)+1;
+ if ((void*)wqe >= squeue_end_v) {
+ wqe = squeue_start_v;
+ }
+ }
+ /*
+ * bad wqe will be reprocessed and ignored when pol_cq() is called,
+ * i.e. nr of wqes with flush error status is one less
+ */
+ EDEB(6, "qp_num=%x flusherr_wqe_cnt=%x", qp_num, (*bad_wqe_cnt)-1);
+ wqe->wqef = 0;
+
+prepare_sqe_rts_exit1:
+
+ EDEB_EX(7, "ehca_qp=%p qp_num=%x ret=%x", my_qp, qp_num, ret);
+ return ret;
+}
+
+/*
+ * internal_modify_qp with circumvention to handle aqp0 properly
+ * smi_reset2init indicates if this is an internal reset-to-init-call for
+ * smi. This flag must always be zero if called from ehca_modify_qp()!
+ * This internal func was intorduced to avoid recursion of ehca_modify_qp()!
+ */
+static int internal_modify_qp(struct ib_qp *ibqp,
+ struct ib_qp_attr *attr,
+ int attr_mask, int smi_reset2init)
+{
+ enum ib_qp_state qp_cur_state = 0, qp_new_state = 0;
+ int cnt = 0, qp_attr_idx = 0, ret = 0;
+
+ enum ib_qp_statetrans statetrans;
+ struct hcp_modify_qp_control_block *mqpcb = NULL;
+ struct ehca_qp *my_qp = NULL;
+ struct ehca_shca *shca = NULL;
+ u64 update_mask = 0;
+ u64 h_ret = H_SUCCESS;
+ int bad_wqe_cnt = 0;
+ int squeue_locked = 0;
+ unsigned long spl_flags = 0;
+
+ my_qp = container_of(ibqp, struct ehca_qp, ib_qp);
+ shca = container_of(ibqp->pd->device, struct ehca_shca, ib_device);
+
+ EDEB_EN(7, "ehca_qp=%p qp_num=%x ibqp_type=%x "
+ "new qp_state=%x attribute_mask=%x",
+ my_qp, ibqp->qp_num, ibqp->qp_type,
+ attr->qp_state, attr_mask);
+
+ /* do query_qp to obtain current attr values */
+ mqpcb = kzalloc(H_CB_ALIGNMENT, GFP_KERNEL);
+ if (mqpcb == NULL) {
+ ret = -ENOMEM;
+ EDEB_ERR(4, "Could not get zeroed page for mqpcb "
+ "ehca_qp=%p qp_num=%x ", my_qp, ibqp->qp_num);
+ goto modify_qp_exit0;
+ }
+
+ h_ret = hipz_h_query_qp(shca->ipz_hca_handle,
+ my_qp->ipz_qp_handle,
+ &my_qp->pf,
+ mqpcb, my_qp->galpas.kernel);
+ if (h_ret != H_SUCCESS) {
+ EDEB_ERR(4, "hipz_h_query_qp() failed "
+ "ehca_qp=%p qp_num=%x h_ret=%lx",
+ my_qp, ibqp->qp_num, h_ret);
+ ret = ehca2ib_return_code(h_ret);
+ goto modify_qp_exit1;
+ }
+ EDEB(7, "ehca_qp=%p qp_num=%x ehca_qp_state=%x",
+ my_qp, ibqp->qp_num, mqpcb->qp_state);
+
+ qp_cur_state = ehca2ib_qp_state(mqpcb->qp_state);
+
+ if (qp_cur_state == -EINVAL) { /* invalid qp state */
+ ret = -EINVAL;
+ EDEB_ERR(4, "Invalid current ehca_qp_state=%x "
+ "ehca_qp=%p qp_num=%x",
+ mqpcb->qp_state, my_qp, ibqp->qp_num);
+ goto modify_qp_exit1;
+ }
+ /*
+ * circumvention to set aqp0 initial state to init
+ * as expected by IB spec
+ */
+ if (smi_reset2init == 0 &&
+ ibqp->qp_type == IB_QPT_SMI &&
+ qp_cur_state == IB_QPS_RESET &&
+ (attr_mask & IB_QP_STATE) &&
+ attr->qp_state == IB_QPS_INIT) { /* RESET -> INIT */
+ struct ib_qp_attr smiqp_attr = {
+ .qp_state = IB_QPS_INIT,
+ .port_num = my_qp->init_attr.port_num,
+ .pkey_index = 0,
+ .qkey = 0
+ };
+ int smiqp_attr_mask = IB_QP_STATE | IB_QP_PORT |
+ IB_QP_PKEY_INDEX | IB_QP_QKEY;
+ int smirc = internal_modify_qp(
+ ibqp, &smiqp_attr, smiqp_attr_mask, 1);
+ if (smirc) {
+ EDEB_ERR(4, "SMI RESET -> INIT failed. "
+ "ehca_modify_qp() rc=%x", smirc);
+ ret = H_PARAMETER;
+ goto modify_qp_exit1;
+ }
+ qp_cur_state = IB_QPS_INIT;
+ EDEB(7, "SMI RESET -> INIT succeeded");
+ }
+ /* is transmitted current state equal to "real" current state */
+ if ((attr_mask & IB_QP_CUR_STATE) &&
+ qp_cur_state != attr->cur_qp_state) {
+ ret = -EINVAL;
+ EDEB_ERR(4, "Invalid IB_QP_CUR_STATE attr->curr_qp_state=%x <>"
+ " actual cur_qp_state=%x. ehca_qp=%p qp_num=%x",
+ attr->cur_qp_state, qp_cur_state, my_qp, ibqp->qp_num);
+ goto modify_qp_exit1;
+ }
+
+ EDEB(7, "ehca_qp=%p qp_num=%x current qp_state=%x "
+ "new qp_state=%x attribute_mask=%x",
+ my_qp, ibqp->qp_num, qp_cur_state, attr->qp_state, attr_mask);
+
+ qp_new_state = attr_mask & IB_QP_STATE ? attr->qp_state : qp_cur_state;
+ if (!smi_reset2init &&
+ !ib_modify_qp_is_ok(qp_cur_state, qp_new_state, ibqp->qp_type,
+ attr_mask)) {
+ ret = -EINVAL;
+ EDEB_ERR(4, "Invalid qp transition new_state=%x cur_state=%x "
+ "ehca_qp=%p qp_num=%x attr_mask=%x",
+ qp_new_state, qp_cur_state, my_qp, ibqp->qp_num,
+ attr_mask);
+ goto modify_qp_exit1;
+ }
+
+ if ((mqpcb->qp_state = ib2ehca_qp_state(qp_new_state)))
+ update_mask = EHCA_BMASK_SET(MQPCB_MASK_QP_STATE, 1);
+ else {
+ ret = -EINVAL;
+ EDEB_ERR(4, "Invalid new qp state=%x "
+ "ehca_qp=%p qp_num=%x",
+ qp_new_state, my_qp, ibqp->qp_num);
+ goto modify_qp_exit1;
+ }
+
+ /* retrieve state transition struct to get req and opt attrs */
+ statetrans = get_modqp_statetrans(qp_cur_state, qp_new_state);
+ if (statetrans < 0) {
+ ret = -EINVAL;
+ EDEB_ERR(4, "<INVALID STATE CHANGE> qp_cur_state=%x "
+ "new_qp_state=%x State_xsition=%x "
+ "ehca_qp=%p qp_num=%x",
+ qp_cur_state, qp_new_state,
+ statetrans, my_qp, ibqp->qp_num);
+ goto modify_qp_exit1;
+ }
+
+ qp_attr_idx = ib2ehcaqptype(ibqp->qp_type);
+
+ if (qp_attr_idx < 0) {
+ ret = qp_attr_idx;
+ EDEB_ERR(4, "Invalid QP type=%x ehca_qp=%p qp_num=%x",
+ ibqp->qp_type, my_qp, ibqp->qp_num);
+ goto modify_qp_exit1;
+ }
+
+ EDEB(7, "ehca_qp=%p qp_num=%x <VALID STATE CHANGE> qp_state_xsit=%x",
+ my_qp, ibqp->qp_num, statetrans);
+
+ /* sqe -> rts: set purge bit of bad wqe before actual trans */
+ if ((my_qp->qp_type == IB_QPT_UD ||
+ my_qp->qp_type == IB_QPT_GSI ||
+ my_qp->qp_type == IB_QPT_SMI) &&
+ statetrans == IB_QPST_SQE2RTS) {
+ /* mark next free wqe if kernel */
+ if (my_qp->uspace_squeue == 0) {
+ struct ehca_wqe *wqe = NULL;
+ /* lock send queue */
+ spin_lock_irqsave(&my_qp->spinlock_s, spl_flags);
+ squeue_locked = 1;
+ /* mark next free wqe */
+ wqe = (struct ehca_wqe*)
+ ipz_qeit_get(&my_qp->ipz_squeue);
+ wqe->optype = wqe->wqef = 0xff;
+ EDEB(7, "qp_num=%x next_free_wqe=%p",
+ ibqp->qp_num, wqe);
+ }
+ ret = prepare_sqe_rts(my_qp, shca, &bad_wqe_cnt);
+ if (ret) {
+ EDEB_ERR(4, "prepare_sqe_rts() failed "
+ "ehca_qp=%p qp_num=%x ret=%x",
+ my_qp, ibqp->qp_num, ret);
+ goto modify_qp_exit2;
+ }
+ }
+
+ /*
+ * enable RDMA_Atomic_Control if reset->init und reliable con
+ * this is necessary since gen2 does not provide that flag,
+ * but pHyp requires it
+ */
+ if (statetrans == IB_QPST_RESET2INIT &&
+ (ibqp->qp_type == IB_QPT_RC || ibqp->qp_type == IB_QPT_UC)) {
+ mqpcb->rdma_atomic_ctrl = 3;
+ update_mask |= EHCA_BMASK_SET(MQPCB_MASK_RDMA_ATOMIC_CTRL, 1);
+ }
+ /* circ. pHyp requires #RDMA/Atomic Resp Res for UC INIT -> RTR */
+ if (statetrans == IB_QPST_INIT2RTR &&
+ (ibqp->qp_type == IB_QPT_UC) &&
+ !(attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)) {
+ mqpcb->rdma_nr_atomic_resp_res = 1; /* default to 1 */
+ update_mask |=
+ EHCA_BMASK_SET(MQPCB_MASK_RDMA_NR_ATOMIC_RESP_RES, 1);
+ }
+
+ if (attr_mask & IB_QP_PKEY_INDEX) {
+ mqpcb->prim_p_key_idx = attr->pkey_index;
+ update_mask |= EHCA_BMASK_SET(MQPCB_MASK_PRIM_P_KEY_IDX, 1);
+ EDEB(7, "ehca_qp=%p qp_num=%x "
+ "IB_QP_PKEY_INDEX update_mask=%lx",
+ my_qp, ibqp->qp_num, update_mask);
+ }
+ if (attr_mask & IB_QP_PORT) {
+ if (attr->port_num < 1 || attr->port_num > shca->num_ports) {
+ ret = -EINVAL;
+ EDEB_ERR(4, "Invalid port=%x. "
+ "ehca_qp=%p qp_num=%x num_ports=%x",
+ attr->port_num, my_qp, ibqp->qp_num,
+ shca->num_ports);
+ goto modify_qp_exit2;
+ }
+ mqpcb->prim_phys_port = attr->port_num;
+ update_mask |= EHCA_BMASK_SET(MQPCB_MASK_PRIM_PHYS_PORT, 1);
+ EDEB(7, "ehca_qp=%p qp_num=%x IB_QP_PORT update_mask=%lx",
+ my_qp, ibqp->qp_num, update_mask);
+ }
+ if (attr_mask & IB_QP_QKEY) {
+ mqpcb->qkey = attr->qkey;
+ update_mask |= EHCA_BMASK_SET(MQPCB_MASK_QKEY, 1);
+ EDEB(7, "ehca_qp=%p qp_num=%x IB_QP_QKEY update_mask=%lx",
+ my_qp, ibqp->qp_num, update_mask);
+ }
+ if (attr_mask & IB_QP_AV) {
+ int ah_mult = ib_rate_to_mult(attr->ah_attr.static_rate);
+ int ehca_mult = ib_rate_to_mult(shca->sport[my_qp->
+ init_attr.port_num].rate);
+
+ mqpcb->dlid = attr->ah_attr.dlid;
+ update_mask |= EHCA_BMASK_SET(MQPCB_MASK_DLID, 1);
+ mqpcb->source_path_bits = attr->ah_attr.src_path_bits;
+ update_mask |= EHCA_BMASK_SET(MQPCB_MASK_SOURCE_PATH_BITS, 1);
+ mqpcb->service_level = attr->ah_attr.sl;
+ update_mask |= EHCA_BMASK_SET(MQPCB_MASK_SERVICE_LEVEL, 1);
+
+ if (ah_mult < ehca_mult)
+ mqpcb->max_static_rate = (ah_mult > 0) ?
+ ((ehca_mult - 1) / ah_mult) : 0;
+ else
+ mqpcb->max_static_rate = 0;
+
+ EDEB(7, " ipd=mqpcb->max_static_rate set %x "
+ " ah_mult=%x ehca_mult=%x "
+ " attr->ah_attr.static_rate=%x",
+ mqpcb->max_static_rate,ah_mult,ehca_mult,
+ attr->ah_attr.static_rate);
+
+ update_mask |= EHCA_BMASK_SET(MQPCB_MASK_MAX_STATIC_RATE, 1);
+
+ /*
+ * only if GRH is TRUE we might consider SOURCE_GID_IDX
+ * and DEST_GID otherwise phype will return H_ATTR_PARM!!!
+ */
+ if (attr->ah_attr.ah_flags == IB_AH_GRH) {
+ mqpcb->send_grh_flag = 1 << 31;
+ update_mask |=
+ EHCA_BMASK_SET(MQPCB_MASK_SEND_GRH_FLAG, 1);
+ mqpcb->source_gid_idx = attr->ah_attr.grh.sgid_index;
+ update_mask |=
+ EHCA_BMASK_SET(MQPCB_MASK_SOURCE_GID_IDX, 1);
+
+ for (cnt = 0; cnt < 16; cnt++)
+ mqpcb->dest_gid.byte[cnt] =
+ attr->ah_attr.grh.dgid.raw[cnt];
+
+ update_mask |= EHCA_BMASK_SET(MQPCB_MASK_DEST_GID, 1);
+ mqpcb->flow_label = attr->ah_attr.grh.flow_label;
+ update_mask |= EHCA_BMASK_SET(MQPCB_MASK_FLOW_LABEL, 1);
+ mqpcb->hop_limit = attr->ah_attr.grh.hop_limit;
+ update_mask |= EHCA_BMASK_SET(MQPCB_MASK_HOP_LIMIT, 1);
+ mqpcb->traffic_class = attr->ah_attr.grh.traffic_class;
+ update_mask |=
+ EHCA_BMASK_SET(MQPCB_MASK_TRAFFIC_CLASS, 1);
+ }
+
+ EDEB(7, "ehca_qp=%p qp_num=%x IB_QP_AV update_mask=%lx",
+ my_qp, ibqp->qp_num, update_mask);
+ }
+
+ if (attr_mask & IB_QP_PATH_MTU) {
+ mqpcb->path_mtu = attr->path_mtu;
+ update_mask |= EHCA_BMASK_SET(MQPCB_MASK_PATH_MTU, 1);
+ EDEB(7, "ehca_qp=%p qp_num=%x IB_QP_PATH_MTU update_mask=%lx",
+ my_qp, ibqp->qp_num, update_mask);
+ }
+ if (attr_mask & IB_QP_TIMEOUT) {
+ mqpcb->timeout = attr->timeout;
+ update_mask |= EHCA_BMASK_SET(MQPCB_MASK_TIMEOUT, 1);
+ EDEB(7, "ehca_qp=%p qp_num=%x IB_QP_TIMEOUT update_mask=%lx",
+ my_qp, ibqp->qp_num, update_mask);
+ }
+ if (attr_mask & IB_QP_RETRY_CNT) {
+ mqpcb->retry_count = attr->retry_cnt;
+ update_mask |= EHCA_BMASK_SET(MQPCB_MASK_RETRY_COUNT, 1);
+ EDEB(7, "ehca_qp=%p qp_num=%x IB_QP_RETRY_CNT update_mask=%lx",
+ my_qp, ibqp->qp_num, update_mask);
+ }
+ if (attr_mask & IB_QP_RNR_RETRY) {
+ mqpcb->rnr_retry_count = attr->rnr_retry;
+ update_mask |= EHCA_BMASK_SET(MQPCB_MASK_RNR_RETRY_COUNT, 1);
+ EDEB(7, "ehca_qp=%p qp_num=%x IB_QP_RNR_RETRY update_mask=%lx",
+ my_qp, ibqp->qp_num, update_mask);
+ }
+ if (attr_mask & IB_QP_RQ_PSN) {
+ mqpcb->receive_psn = attr->rq_psn;
+ update_mask |= EHCA_BMASK_SET(MQPCB_MASK_RECEIVE_PSN, 1);
+ EDEB(7, "ehca_qp=%p qp_num=%x IB_QP_RQ_PSN update_mask=%lx",
+ my_qp, ibqp->qp_num, update_mask);
+ }
+ if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
+ mqpcb->rdma_nr_atomic_resp_res = attr->max_dest_rd_atomic < 3 ?
+ attr->max_dest_rd_atomic : 2; /* max is 2 */
+ update_mask |=
+ EHCA_BMASK_SET(MQPCB_MASK_RDMA_NR_ATOMIC_RESP_RES, 1);
+ EDEB(7, "ehca_qp=%p qp_num=%x IB_QP_MAX_DEST_RD_ATOMIC "
+ "update_mask=%lx", my_qp, ibqp->qp_num, update_mask);
+ }
+ if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
+ mqpcb->rdma_atomic_outst_dest_qp = attr->max_rd_atomic < 3 ?
+ attr->max_rd_atomic : 2;
+ update_mask |=
+ EHCA_BMASK_SET
+ (MQPCB_MASK_RDMA_ATOMIC_OUTST_DEST_QP, 1);
+ EDEB(7, "ehca_qp=%p qp_num=%x IB_QP_MAX_QP_RD_ATOMIC "
+ "update_mask=%lx", my_qp, ibqp->qp_num, update_mask);
+ }
+ if (attr_mask & IB_QP_ALT_PATH) {
+ int ah_mult = ib_rate_to_mult(attr->alt_ah_attr.static_rate);
+ int ehca_mult = ib_rate_to_mult(
+ shca->sport[my_qp->init_attr.port_num].rate);
+
+ mqpcb->dlid_al = attr->alt_ah_attr.dlid;
+ update_mask |= EHCA_BMASK_SET(MQPCB_MASK_DLID_AL, 1);
+ mqpcb->source_path_bits_al = attr->alt_ah_attr.src_path_bits;
+ update_mask |=
+ EHCA_BMASK_SET(MQPCB_MASK_SOURCE_PATH_BITS_AL, 1);
+ mqpcb->service_level_al = attr->alt_ah_attr.sl;
+ update_mask |= EHCA_BMASK_SET(MQPCB_MASK_SERVICE_LEVEL_AL, 1);
+
+ if (ah_mult < ehca_mult)
+ mqpcb->max_static_rate = (ah_mult > 0) ?
+ ((ehca_mult - 1) / ah_mult) : 0;
+ else
+ mqpcb->max_static_rate_al = 0;
+
+ EDEB(7, " ipd=mqpcb->max_static_rate set %x,"
+ " ah_mult=%x ehca_mult=%x",
+ mqpcb->max_static_rate,ah_mult,ehca_mult);
+
+ update_mask |= EHCA_BMASK_SET(MQPCB_MASK_MAX_STATIC_RATE_AL, 1);
+
+ /*
+ * only if GRH is TRUE we might consider SOURCE_GID_IDX
+ * and DEST_GID otherwise phype will return H_ATTR_PARM!!!
+ */
+ if (attr->alt_ah_attr.ah_flags == IB_AH_GRH) {
+ mqpcb->send_grh_flag_al = 1 << 31;
+ update_mask |=
+ EHCA_BMASK_SET(MQPCB_MASK_SEND_GRH_FLAG_AL, 1);
+ mqpcb->source_gid_idx_al =
+ attr->alt_ah_attr.grh.sgid_index;
+ update_mask |=
+ EHCA_BMASK_SET(MQPCB_MASK_SOURCE_GID_IDX_AL, 1);
+
+ for (cnt = 0; cnt < 16; cnt++)
+ mqpcb->dest_gid_al.byte[cnt] =
+ attr->alt_ah_attr.grh.dgid.raw[cnt];
+
+ update_mask |=
+ EHCA_BMASK_SET(MQPCB_MASK_DEST_GID_AL, 1);
+ mqpcb->flow_label_al = attr->alt_ah_attr.grh.flow_label;
+ update_mask |=
+ EHCA_BMASK_SET(MQPCB_MASK_FLOW_LABEL_AL, 1);
+ mqpcb->hop_limit_al = attr->alt_ah_attr.grh.hop_limit;
+ update_mask |=
+ EHCA_BMASK_SET(MQPCB_MASK_HOP_LIMIT_AL, 1);
+ mqpcb->traffic_class_al =
+ attr->alt_ah_attr.grh.traffic_class;
+ update_mask |=
+ EHCA_BMASK_SET(MQPCB_MASK_TRAFFIC_CLASS_AL, 1);
+ }
+
+ EDEB(7, "ehca_qp=%p qp_num=%x IB_QP_ALT_PATH update_mask=%lx",
+ my_qp, ibqp->qp_num, update_mask);
+ }
+
+ if (attr_mask & IB_QP_MIN_RNR_TIMER) {
+ mqpcb->min_rnr_nak_timer_field = attr->min_rnr_timer;
+ update_mask |=
+ EHCA_BMASK_SET(MQPCB_MASK_MIN_RNR_NAK_TIMER_FIELD, 1);
+ EDEB(7, "ehca_qp=%p qp_num=%x "
+ "IB_QP_MIN_RNR_TIMER update_mask=%lx",
+ my_qp, ibqp->qp_num, update_mask);
+ }
+
+ if (attr_mask & IB_QP_SQ_PSN) {
+ mqpcb->send_psn = attr->sq_psn;
+ update_mask |= EHCA_BMASK_SET(MQPCB_MASK_SEND_PSN, 1);
+ EDEB(7, "ehca_qp=%p qp_num=%x "
+ "IB_QP_SQ_PSN update_mask=%lx",
+ my_qp, ibqp->qp_num, update_mask);
+ }
+
+ if (attr_mask & IB_QP_DEST_QPN) {
+ mqpcb->dest_qp_nr = attr->dest_qp_num;
+ update_mask |= EHCA_BMASK_SET(MQPCB_MASK_DEST_QP_NR, 1);
+ EDEB(7, "ehca_qp=%p qp_num=%x "
+ "IB_QP_DEST_QPN update_mask=%lx",
+ my_qp, ibqp->qp_num, update_mask);
+ }
+
+ if (attr_mask & IB_QP_PATH_MIG_STATE) {
+ mqpcb->path_migration_state = attr->path_mig_state;
+ update_mask |=
+ EHCA_BMASK_SET(MQPCB_MASK_PATH_MIGRATION_STATE, 1);
+ EDEB(7, "ehca_qp=%p qp_num=%x "
+ "IB_QP_PATH_MIG_STATE update_mask=%lx", my_qp,
+ ibqp->qp_num, update_mask);
+ }
+
+ if (attr_mask & IB_QP_CAP) {
+ mqpcb->max_nr_outst_send_wr = attr->cap.max_send_wr+1;
+ update_mask |=
+ EHCA_BMASK_SET(MQPCB_MASK_MAX_NR_OUTST_SEND_WR, 1);
+ mqpcb->max_nr_outst_recv_wr = attr->cap.max_recv_wr+1;
+ update_mask |=
+ EHCA_BMASK_SET(MQPCB_MASK_MAX_NR_OUTST_RECV_WR, 1);
+ EDEB(7, "ehca_qp=%p qp_num=%x "
+ "IB_QP_CAP update_mask=%lx",
+ my_qp, ibqp->qp_num, update_mask);
+ /* no support for max_send/recv_sge yet */
+ }
+
+ EDEB_DMP(7, mqpcb, 4*70, "ehca_qp=%p qp_num=%x", my_qp, ibqp->qp_num);
+
+ h_ret = hipz_h_modify_qp(shca->ipz_hca_handle,
+ my_qp->ipz_qp_handle,
+ &my_qp->pf,
+ update_mask,
+ mqpcb, my_qp->galpas.kernel);
+
+ if (h_ret != H_SUCCESS) {
+ ret = ehca2ib_return_code(h_ret);
+ EDEB_ERR(4, "hipz_h_modify_qp() failed rc=%lx "
+ "ehca_qp=%p qp_num=%x",
+ h_ret, my_qp, ibqp->qp_num);
+ goto modify_qp_exit2;
+ }
+
+ if ((my_qp->qp_type == IB_QPT_UD ||
+ my_qp->qp_type == IB_QPT_GSI ||
+ my_qp->qp_type == IB_QPT_SMI) &&
+ statetrans == IB_QPST_SQE2RTS) {
+ /* doorbell to reprocessing wqes */
+ iosync(); /* serialize GAL register access */
+ hipz_update_sqa(my_qp, bad_wqe_cnt-1);
+ EDEB(6, "doorbell for %x wqes", bad_wqe_cnt);
+ }
+
+ if (statetrans == IB_QPST_RESET2INIT ||
+ statetrans == IB_QPST_INIT2INIT) {
+ mqpcb->qp_enable = 1;
+ mqpcb->qp_state = EHCA_QPS_INIT;
+ update_mask = 0;
+ update_mask = EHCA_BMASK_SET(MQPCB_MASK_QP_ENABLE, 1);
+
+ EDEB(7, "ehca_qp=%p qp_num=%x "
+ "RESET_2_INIT needs an additional enable "
+ "-> update_mask=%lx", my_qp, ibqp->qp_num, update_mask);
+
+ h_ret = hipz_h_modify_qp(shca->ipz_hca_handle,
+ my_qp->ipz_qp_handle,
+ &my_qp->pf,
+ update_mask,
+ mqpcb,
+ my_qp->galpas.kernel);
+
+ if (h_ret != H_SUCCESS) {
+ ret = ehca2ib_return_code(h_ret);
+ EDEB_ERR(4, "ENABLE in context of "
+ "RESET_2_INIT failed! "
+ "Maybe you didn't get a LID"
+ "h_ret=%lx ehca_qp=%p qp_num=%x",
+ h_ret, my_qp, ibqp->qp_num);
+ goto modify_qp_exit2;
+ }
+ }
+
+ if (statetrans == IB_QPST_ANY2RESET) {
+ ipz_qeit_reset(&my_qp->ipz_rqueue);
+ ipz_qeit_reset(&my_qp->ipz_squeue);
+ }
+
+ if (attr_mask & IB_QP_QKEY)
+ my_qp->qkey = attr->qkey;
+
+modify_qp_exit2:
+ if (squeue_locked) { /* this means: sqe -> rts */
+ spin_unlock_irqrestore(&my_qp->spinlock_s, spl_flags);
+ my_qp->sqerr_purgeflag = 1;
+ }
+
+modify_qp_exit1:
+ kfree(mqpcb);
+
+modify_qp_exit0:
+ EDEB_EX(7, "ehca_qp=%p qp_num=%x ibqp_type=%x ret=%x",
+ my_qp, ibqp->qp_num, ibqp->qp_type, ret);
+ return ret;
+}
+
+int ehca_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, int attr_mask)
+{
+ int ret = 0;
+ struct ehca_qp *my_qp = NULL;
+ struct ehca_pd *my_pd = NULL;
+ u32 cur_pid = current->tgid;
+
+ EHCA_CHECK_ADR(ibqp);
+ EHCA_CHECK_ADR(attr);
+ EHCA_CHECK_ADR(ibqp->device);
+
+ my_qp = container_of(ibqp, struct ehca_qp, ib_qp);
+
+ EDEB_EN(7, "ehca_qp=%p qp_num=%x ibqp_type=%x attr_mask=%x",
+ my_qp, ibqp->qp_num, ibqp->qp_type, attr_mask);
+
+ my_pd = container_of(my_qp->ib_qp.pd, struct ehca_pd, ib_pd);
+ if (my_pd->ib_pd.uobject && my_pd->ib_pd.uobject->context &&
+ my_pd->ownpid != cur_pid) {
+ EDEB_ERR(4, "Invalid caller pid=%x ownpid=%x",
+ cur_pid, my_pd->ownpid);
+ ret = -EINVAL;
+ } else
+ ret = internal_modify_qp(ibqp, attr, attr_mask, 0);
+
+ EDEB_EX(7, "ehca_qp=%p qp_num=%x ibqp_type=%x ret=%x",
+ my_qp, ibqp->qp_num, ibqp->qp_type, ret);
+ return ret;
+}
+
+int ehca_query_qp(struct ib_qp *qp,
+ struct ib_qp_attr *qp_attr,
+ int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
+{
+ struct ehca_qp *my_qp = NULL;
+ struct ehca_shca *shca = NULL;
+ struct hcp_modify_qp_control_block *qpcb = NULL;
+ struct ipz_adapter_handle adapter_handle;
+ struct ehca_pd *my_pd = NULL;
+ u32 cur_pid = current->tgid;
+ int cnt = 0, ret = 0;
+ u64 h_ret = H_SUCCESS;
+
+ EHCA_CHECK_ADR(qp);
+ EHCA_CHECK_ADR(qp_attr);
+ EHCA_CHECK_DEVICE(qp->device);
+
+ my_qp = container_of(qp, struct ehca_qp, ib_qp);
+
+ EDEB_EN(7, "ehca_qp=%p qp_num=%x "
+ "qp_attr=%p qp_attr_mask=%x qp_init_attr=%p",
+ my_qp, qp->qp_num, qp_attr, qp_attr_mask, qp_init_attr);
+
+ my_pd = container_of(my_qp->ib_qp.pd, struct ehca_pd, ib_pd);
+ if (my_pd->ib_pd.uobject && my_pd->ib_pd.uobject->context &&
+ my_pd->ownpid != cur_pid) {
+ EDEB_ERR(4, "Invalid caller pid=%x ownpid=%x",
+ cur_pid, my_pd->ownpid);
+ ret = -EINVAL;
+ goto query_qp_exit0;
+ }
+
+ shca = container_of(qp->device, struct ehca_shca, ib_device);
+ adapter_handle = shca->ipz_hca_handle;
+
+ if (qp_attr_mask & QP_ATTR_QUERY_NOT_SUPPORTED) {
+ ret = -EINVAL;
+ EDEB_ERR(4,"Invalid attribute mask "
+ "ehca_qp=%p qp_num=%x qp_attr_mask=%x ",
+ my_qp, qp->qp_num, qp_attr_mask);
+ goto query_qp_exit0;
+ }
+
+ qpcb = kzalloc(H_CB_ALIGNMENT, GFP_KERNEL );
+ if (!qpcb) {
+ ret = -ENOMEM;
+ EDEB_ERR(4,"Out of memory for qpcb "
+ "ehca_qp=%p qp_num=%x", my_qp, qp->qp_num);
+ goto query_qp_exit0;
+ }
+
+ h_ret = hipz_h_query_qp(adapter_handle,
+ my_qp->ipz_qp_handle,
+ &my_qp->pf,
+ qpcb, my_qp->galpas.kernel);
+
+ if (h_ret != H_SUCCESS) {
+ ret = ehca2ib_return_code(h_ret);
+ EDEB_ERR(4,"hipz_h_query_qp() failed "
+ "ehca_qp=%p qp_num=%x h_ret=%lx",
+ my_qp, qp->qp_num, h_ret);
+ goto query_qp_exit1;
+ }
+
+ qp_attr->cur_qp_state = ehca2ib_qp_state(qpcb->qp_state);
+ qp_attr->qp_state = qp_attr->cur_qp_state;
+ if (qp_attr->cur_qp_state == -EINVAL) {
+ ret = -EINVAL;
+ EDEB_ERR(4,"Got invalid ehca_qp_state=%x "
+ "ehca_qp=%p qp_num=%x",
+ qpcb->qp_state, my_qp, qp->qp_num);
+ goto query_qp_exit1;
+ }
+
+ if (qp_attr->qp_state == IB_QPS_SQD)
+ qp_attr->sq_draining = 1;
+
+ qp_attr->qkey = qpcb->qkey;
+ qp_attr->path_mtu = qpcb->path_mtu;
+ qp_attr->path_mig_state = qpcb->path_migration_state;
+ qp_attr->rq_psn = qpcb->receive_psn;
+ qp_attr->sq_psn = qpcb->send_psn;
+ qp_attr->min_rnr_timer = qpcb->min_rnr_nak_timer_field;
+ qp_attr->cap.max_send_wr = qpcb->max_nr_outst_send_wr-1;
+ qp_attr->cap.max_recv_wr = qpcb->max_nr_outst_recv_wr-1;
+ /* UD_AV CIRCUMVENTION */
+ if (my_qp->qp_type == IB_QPT_UD) {
+ qp_attr->cap.max_send_sge =
+ qpcb->actual_nr_sges_in_sq_wqe - 2;
+ qp_attr->cap.max_recv_sge =
+ qpcb->actual_nr_sges_in_rq_wqe - 2;
+ } else {
+ qp_attr->cap.max_send_sge =
+ qpcb->actual_nr_sges_in_sq_wqe;
+ qp_attr->cap.max_recv_sge =
+ qpcb->actual_nr_sges_in_rq_wqe;
+ }
+
+ qp_attr->cap.max_inline_data = my_qp->sq_max_inline_data_size;
+ qp_attr->dest_qp_num = qpcb->dest_qp_nr;
+
+ qp_attr->pkey_index =
+ EHCA_BMASK_GET(MQPCB_PRIM_P_KEY_IDX, qpcb->prim_p_key_idx);
+
+ qp_attr->port_num =
+ EHCA_BMASK_GET(MQPCB_PRIM_PHYS_PORT, qpcb->prim_phys_port);
+
+ qp_attr->timeout = qpcb->timeout;
+ qp_attr->retry_cnt = qpcb->retry_count;
+ qp_attr->rnr_retry = qpcb->rnr_retry_count;
+
+ qp_attr->alt_pkey_index =
+ EHCA_BMASK_GET(MQPCB_PRIM_P_KEY_IDX, qpcb->alt_p_key_idx);
+
+ qp_attr->alt_port_num = qpcb->alt_phys_port;
+ qp_attr->alt_timeout = qpcb->timeout_al;
+
+ /* primary av */
+ qp_attr->ah_attr.sl = qpcb->service_level;
+
+ if (qpcb->send_grh_flag) {
+ qp_attr->ah_attr.ah_flags = IB_AH_GRH;
+ }
+
+ qp_attr->ah_attr.static_rate = qpcb->max_static_rate;
+ qp_attr->ah_attr.dlid = qpcb->dlid;
+ qp_attr->ah_attr.src_path_bits = qpcb->source_path_bits;
+ qp_attr->ah_attr.port_num = qp_attr->port_num;
+
+ /* primary GRH */
+ qp_attr->ah_attr.grh.traffic_class = qpcb->traffic_class;
+ qp_attr->ah_attr.grh.hop_limit = qpcb->hop_limit;
+ qp_attr->ah_attr.grh.sgid_index = qpcb->source_gid_idx;
+ qp_attr->ah_attr.grh.flow_label = qpcb->flow_label;
+
+ for (cnt = 0; cnt < 16; cnt++)
+ qp_attr->ah_attr.grh.dgid.raw[cnt] =
+ qpcb->dest_gid.byte[cnt];
+
+ /* alternate AV */
+ qp_attr->alt_ah_attr.sl = qpcb->service_level_al;
+ if (qpcb->send_grh_flag_al) {
+ qp_attr->alt_ah_attr.ah_flags = IB_AH_GRH;
+ }
+
+ qp_attr->alt_ah_attr.static_rate = qpcb->max_static_rate_al;
+ qp_attr->alt_ah_attr.dlid = qpcb->dlid_al;
+ qp_attr->alt_ah_attr.src_path_bits = qpcb->source_path_bits_al;
+
+ /* alternate GRH */
+ qp_attr->alt_ah_attr.grh.traffic_class = qpcb->traffic_class_al;
+ qp_attr->alt_ah_attr.grh.hop_limit = qpcb->hop_limit_al;
+ qp_attr->alt_ah_attr.grh.sgid_index = qpcb->source_gid_idx_al;
+ qp_attr->alt_ah_attr.grh.flow_label = qpcb->flow_label_al;
+
+ for (cnt = 0; cnt < 16; cnt++)
+ qp_attr->alt_ah_attr.grh.dgid.raw[cnt] =
+ qpcb->dest_gid_al.byte[cnt];
+
+ /* return init attributes given in ehca_create_qp */
+ if (qp_init_attr)
+ *qp_init_attr = my_qp->init_attr;
+
+ EDEB(7, "ehca_qp=%p qp_number=%x dest_qp_number=%x "
+ "dlid=%x path_mtu=%x dest_gid=%lx_%lx "
+ "service_level=%x qp_state=%x",
+ my_qp, qpcb->qp_number, qpcb->dest_qp_nr,
+ qpcb->dlid, qpcb->path_mtu,
+ qpcb->dest_gid.dw[0], qpcb->dest_gid.dw[1],
+ qpcb->service_level, qpcb->qp_state);
+
+ EDEB_DMP(7, qpcb, 4*70, "ehca_qp=%p qp_num=%x", my_qp, qp->qp_num);
+
+query_qp_exit1:
+ kfree(qpcb);
+
+query_qp_exit0:
+ EDEB_EX(7, "ehca_qp=%p qp_num=%x ret=%x",
+ my_qp, qp->qp_num, ret);
+ return ret;
+}
+
+int ehca_destroy_qp(struct ib_qp *ibqp)
+{
+ extern struct ehca_module ehca_module;
+ struct ehca_qp *my_qp = NULL;
+ struct ehca_shca *shca = NULL;
+ struct ehca_pfqp *qp_pf = NULL;
+ struct ehca_pd *my_pd = NULL;
+ u32 cur_pid = current->tgid;
+ u32 qp_num = 0;
+ int ret = 0;
+ u64 h_ret = H_SUCCESS;
+ u8 port_num = 0;
+ enum ib_qp_type qp_type;
+ unsigned long flags;
+
+ EHCA_CHECK_ADR(ibqp);
+
+ my_qp = container_of(ibqp, struct ehca_qp, ib_qp);
+ qp_num = ibqp->qp_num;
+ qp_pf = &my_qp->pf;
+
+ shca = container_of(ibqp->device, struct ehca_shca, ib_device);
+
+ EDEB_EN(7, "ehca_qp=%p qp_num=%x", my_qp, ibqp->qp_num);
+
+ my_pd = container_of(my_qp->ib_qp.pd, struct ehca_pd, ib_pd);
+ if (my_pd->ib_pd.uobject && my_pd->ib_pd.uobject->context &&
+ my_pd->ownpid != cur_pid) {
+ EDEB_ERR(4, "Invalid caller pid=%x ownpid=%x",
+ cur_pid, my_pd->ownpid);
+ return -EINVAL;
+ }
+
+ if (my_qp->send_cq) {
+ ret = ehca_cq_unassign_qp(my_qp->send_cq,
+ my_qp->real_qp_num);
+ if (ret) {
+ EDEB_ERR(4, "Couldn't unassign qp from send_cq "
+ "ret=%x qp_num=%x cq_num=%x",
+ ret, my_qp->ib_qp.qp_num,
+ my_qp->send_cq->cq_number);
+ goto destroy_qp_exit0;
+ }
+ }
+
+ spin_lock_irqsave(&ehca_qp_idr_lock, flags);
+ idr_remove(&ehca_qp_idr, my_qp->token);
+ spin_unlock_irqrestore(&ehca_qp_idr_lock, flags);
+
+ /* un-mmap if vma alloc */
+ if (my_qp->uspace_rqueue) {
+ ret = ehca_munmap(my_qp->uspace_rqueue,
+ my_qp->ipz_rqueue.queue_length);
+ ret = ehca_munmap(my_qp->uspace_squeue,
+ my_qp->ipz_squeue.queue_length);
+ ret = ehca_munmap(my_qp->uspace_fwh, EHCA_PAGESIZE);
+ }
+
+ h_ret = hipz_h_destroy_qp(shca->ipz_hca_handle, my_qp);
+ if (h_ret != H_SUCCESS) {
+ EDEB_ERR(4, "hipz_h_destroy_qp() failed "
+ "rc=%lx ehca_qp=%p qp_num=%x",
+ h_ret, qp_pf, qp_num);
+ goto destroy_qp_exit0;
+ }
+
+ port_num = my_qp->init_attr.port_num;
+ qp_type = my_qp->init_attr.qp_type;
+
+ /* no support for IB_QPT_SMI yet */
+ if (qp_type == IB_QPT_GSI) {
+ struct ib_event event;
+
+ EDEB(4, "device %s: port %x is inactive.",
+ shca->ib_device.name, port_num);
+ event.device = &shca->ib_device;
+ event.event = IB_EVENT_PORT_ERR;
+ event.element.port_num = port_num;
+ shca->sport[port_num - 1].port_state = IB_PORT_DOWN;
+ ib_dispatch_event(&event);
+ }
+
+ ipz_queue_dtor(&my_qp->ipz_rqueue);
+ ipz_queue_dtor(&my_qp->ipz_squeue);
+ kmem_cache_free(ehca_module.cache_qp, my_qp);
+
+destroy_qp_exit0:
+ ret = ehca2ib_return_code(h_ret);
+ EDEB_EX(7,"ret=%x", ret);
+ return ret;
+}
diff --git a/drivers/infiniband/hw/ehca/ehca_reqs.c b/drivers/infiniband/hw/ehca/ehca_reqs.c
new file mode 100644
index 0000000..f1afb94
--- /dev/null
+++ b/drivers/infiniband/hw/ehca/ehca_reqs.c
@@ -0,0 +1,694 @@
+/*
+ * IBM eServer eHCA Infiniband device driver for Linux on POWER
+ *
+ * post_send/recv, poll_cq, req_notify
+ *
+ * Authors: Waleri Fomin <fomin@de.ibm.com>
+ * Hoang-Nam Nguyen <hnguyen@de.ibm.com>
+ * Reinhard Ernst <rernst@de.ibm.com>
+ *
+ * Copyright (c) 2005 IBM Corporation
+ *
+ * All rights reserved.
+ *
+ * This source code is distributed under a dual license of GPL v2.0 and OpenIB
+ * BSD.
+ *
+ * OpenIB BSD License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials
+ * provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
+ * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+#define DEB_PREFIX "reqs"
+
+#include <asm-powerpc/system.h>
+#include "ehca_classes.h"
+#include "ehca_tools.h"
+#include "ehca_qes.h"
+#include "ehca_iverbs.h"
+#include "hcp_if.h"
+#include "hipz_fns.h"
+
+static inline int ehca_write_rwqe(struct ipz_queue *ipz_rqueue,
+ struct ehca_wqe *wqe_p,
+ struct ib_recv_wr *recv_wr)
+{
+ u8 cnt_ds;
+ if (unlikely((recv_wr->num_sge < 0) ||
+ (recv_wr->num_sge > ipz_rqueue->act_nr_of_sg))) {
+ EDEB_ERR(4, "Invalid number of WQE SGE. "
+ "num_sqe=%x max_nr_of_sg=%x",
+ recv_wr->num_sge, ipz_rqueue->act_nr_of_sg);
+ return -EINVAL; /* invalid SG list length */
+ }
+
+ /* clear wqe header until sglist */
+ memset(wqe_p, 0, offsetof(struct ehca_wqe, u.ud_av.sg_list));
+
+ wqe_p->work_request_id = recv_wr->wr_id;
+ wqe_p->nr_of_data_seg = recv_wr->num_sge;
+
+ for (cnt_ds = 0; cnt_ds < recv_wr->num_sge; cnt_ds++) {
+ wqe_p->u.all_rcv.sg_list[cnt_ds].vaddr =
+ recv_wr->sg_list[cnt_ds].addr;
+ wqe_p->u.all_rcv.sg_list[cnt_ds].lkey =
+ recv_wr->sg_list[cnt_ds].lkey;
+ wqe_p->u.all_rcv.sg_list[cnt_ds].length =
+ recv_wr->sg_list[cnt_ds].length;
+ }
+
+ if (IS_EDEB_ON(7)) {
+ EDEB(7, "RECEIVE WQE written into ipz_rqueue=%p", ipz_rqueue);
+ EDEB_DMP(7, wqe_p, 16*(6 + wqe_p->nr_of_data_seg), "recv wqe");
+ }
+
+ return 0;
+}
+
+#if defined(DEBUG_GSI_SEND_WR)
+
+/* need ib_mad struct */
+#include <rdma/ib_mad.h>
+
+static void trace_send_wr_ud(const struct ib_send_wr *send_wr)
+{
+ int idx = 0;
+ int j = 0;
+ while (send_wr) {
+ struct ib_mad_hdr *mad_hdr = send_wr->wr.ud.mad_hdr;
+ struct ib_sge *sge = send_wr->sg_list;
+ EDEB(4, "send_wr#%x wr_id=%lx num_sge=%x "
+ "send_flags=%x opcode=%x",idx, send_wr->wr_id,
+ send_wr->num_sge, send_wr->send_flags, send_wr->opcode);
+ if (mad_hdr) {
+ EDEB(4, "send_wr#%x mad_hdr base_version=%x "
+ "mgmt_class=%x class_version=%x method=%x "
+ "status=%x class_specific=%x tid=%lx attr_id=%x "
+ "resv=%x attr_mod=%x",
+ idx, mad_hdr->base_version, mad_hdr->mgmt_class,
+ mad_hdr->class_version, mad_hdr->method,
+ mad_hdr->status, mad_hdr->class_specific,
+ mad_hdr->tid, mad_hdr->attr_id, mad_hdr->resv,
+ mad_hdr->attr_mod);
+ }
+ for (j = 0; j < send_wr->num_sge; j++) {
+ u8 *data = (u8 *) abs_to_virt(sge->addr);
+ EDEB(4, "send_wr#%x sge#%x addr=%p length=%x lkey=%x",
+ idx, j, data, sge->length, sge->lkey);
+ /* assume length is n*16 */
+ EDEB_DMP(4, data, sge->length, "send_wr#%x sge#%x",
+ idx, j);
+ sge++;
+ } /* eof for j */
+ idx++;
+ send_wr = send_wr->next;
+ } /* eof while send_wr */
+}
+
+#endif /* DEBUG_GSI_SEND_WR */
+
+static inline int ehca_write_swqe(struct ehca_qp *qp,
+ struct ehca_wqe *wqe_p,
+ const struct ib_send_wr *send_wr)
+{
+ u32 idx;
+ u64 dma_length;
+ struct ehca_av *my_av;
+ u32 remote_qkey = send_wr->wr.ud.remote_qkey;
+
+ if (unlikely((send_wr->num_sge < 0) ||
+ (send_wr->num_sge > qp->ipz_squeue.act_nr_of_sg))) {
+ EDEB_ERR(4, "Invalid number of WQE SGE. "
+ "num_sqe=%x max_nr_of_sg=%x",
+ send_wr->num_sge, qp->ipz_squeue.act_nr_of_sg);
+ return -EINVAL; /* invalid SG list length */
+ }
+
+ /* clear wqe header until sglist */
+ memset(wqe_p, 0, offsetof(struct ehca_wqe, u.ud_av.sg_list));
+
+ wqe_p->work_request_id = send_wr->wr_id;
+
+ switch (send_wr->opcode) {
+ case IB_WR_SEND:
+ case IB_WR_SEND_WITH_IMM:
+ wqe_p->optype = WQE_OPTYPE_SEND;
+ break;
+ case IB_WR_RDMA_WRITE:
+ case IB_WR_RDMA_WRITE_WITH_IMM:
+ wqe_p->optype = WQE_OPTYPE_RDMAWRITE;
+ break;
+ case IB_WR_RDMA_READ:
+ wqe_p->optype = WQE_OPTYPE_RDMAREAD;
+ break;
+ default:
+ EDEB_ERR(4, "Invalid opcode=%x", send_wr->opcode);
+ return -EINVAL; /* invalid opcode */
+ }
+
+ wqe_p->wqef = (send_wr->opcode) & WQEF_HIGH_NIBBLE;
+
+ wqe_p->wr_flag = 0;
+
+ if (send_wr->send_flags & IB_SEND_SIGNALED)
+ wqe_p->wr_flag |= WQE_WRFLAG_REQ_SIGNAL_COM;
+
+ if (send_wr->opcode == IB_WR_SEND_WITH_IMM ||
+ send_wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM) {
+ /* this might not work as long as HW does not support it */
+ wqe_p->immediate_data = be32_to_cpu(send_wr->imm_data);
+ wqe_p->wr_flag |= WQE_WRFLAG_IMM_DATA_PRESENT;
+ }
+
+ wqe_p->nr_of_data_seg = send_wr->num_sge;
+
+ switch (qp->qp_type) {
+ case IB_QPT_SMI:
+ case IB_QPT_GSI:
+ /* no break is intential here */
+ case IB_QPT_UD:
+ /* IB 1.2 spec C10-15 compliance */
+ if (send_wr->wr.ud.remote_qkey & 0x80000000)
+ remote_qkey = qp->qkey;
+
+ wqe_p->destination_qp_number = send_wr->wr.ud.remote_qpn << 8;
+ wqe_p->local_ee_context_qkey = remote_qkey;
+ if (!send_wr->wr.ud.ah) {
+ EDEB_ERR(4, "wr.ud.ah is NULL. qp=%p", qp);
+ return -EINVAL;
+ }
+ my_av = container_of(send_wr->wr.ud.ah, struct ehca_av, ib_ah);
+ wqe_p->u.ud_av.ud_av = my_av->av;
+
+ /*
+ * omitted check of IB_SEND_INLINE
+ * since HW does not support it
+ */
+ for (idx = 0; idx < send_wr->num_sge; idx++) {
+ wqe_p->u.ud_av.sg_list[idx].vaddr =
+ send_wr->sg_list[idx].addr;
+ wqe_p->u.ud_av.sg_list[idx].lkey =
+ send_wr->sg_list[idx].lkey;
+ wqe_p->u.ud_av.sg_list[idx].length =
+ send_wr->sg_list[idx].length;
+ } /* eof for idx */
+ if (qp->qp_type == IB_QPT_SMI ||
+ qp->qp_type == IB_QPT_GSI)
+ wqe_p->u.ud_av.ud_av.pmtu = 1;
+ if (qp->qp_type == IB_QPT_GSI) {
+ wqe_p->pkeyi = send_wr->wr.ud.pkey_index;
+#ifdef DEBUG_GSI_SEND_WR
+ trace_send_wr_ud(send_wr);
+#endif /* DEBUG_GSI_SEND_WR */
+ }
+ break;
+
+ case IB_QPT_UC:
+ if (send_wr->send_flags & IB_SEND_FENCE)
+ wqe_p->wr_flag |= WQE_WRFLAG_FENCE;
+ /* no break is intentional here */
+ case IB_QPT_RC:
+ /* TODO: atomic not implemented */
+ wqe_p->u.nud.remote_virtual_adress =
+ send_wr->wr.rdma.remote_addr;
+ wqe_p->u.nud.rkey = send_wr->wr.rdma.rkey;
+
+ /*
+ * omitted checking of IB_SEND_INLINE
+ * since HW does not support it
+ */
+ dma_length = 0;
+ for (idx = 0; idx < send_wr->num_sge; idx++) {
+ wqe_p->u.nud.sg_list[idx].vaddr =
+ send_wr->sg_list[idx].addr;
+ wqe_p->u.nud.sg_list[idx].lkey =
+ send_wr->sg_list[idx].lkey;
+ wqe_p->u.nud.sg_list[idx].length =
+ send_wr->sg_list[idx].length;
+ dma_length += send_wr->sg_list[idx].length;
+ } /* eof idx */
+ wqe_p->u.nud.atomic_1st_op_dma_len = dma_length;
+
+ break;
+
+ default:
+ EDEB_ERR(4, "Invalid qptype=%x", qp->qp_type);
+ return -EINVAL;
+ }
+
+ if (IS_EDEB_ON(7)) {
+ EDEB(7, "SEND WQE written into queue qp=%p ", qp);
+ EDEB_DMP(7, wqe_p, 16*(6 + wqe_p->nr_of_data_seg), "send wqe");
+ }
+ return 0;
+}
+
+/* map_ib_wc_status converts raw cqe_status to ib_wc_status */
+static inline void map_ib_wc_status(u32 cqe_status,
+ enum ib_wc_status *wc_status)
+{
+ if (unlikely(cqe_status & WC_STATUS_ERROR_BIT)) {
+ switch (cqe_status & 0x3F) {
+ case 0x01:
+ case 0x21:
+ *wc_status = IB_WC_LOC_LEN_ERR;
+ break;
+ case 0x02:
+ case 0x22:
+ *wc_status = IB_WC_LOC_QP_OP_ERR;
+ break;
+ case 0x03:
+ case 0x23:
+ *wc_status = IB_WC_LOC_EEC_OP_ERR;
+ break;
+ case 0x04:
+ case 0x24:
+ *wc_status = IB_WC_LOC_PROT_ERR;
+ break;
+ case 0x05:
+ case 0x25:
+ *wc_status = IB_WC_WR_FLUSH_ERR;
+ break;
+ case 0x06:
+ *wc_status = IB_WC_MW_BIND_ERR;
+ break;
+ case 0x07: /* remote error - look into bits 20:24 */
+ switch ((cqe_status
+ & WC_STATUS_REMOTE_ERROR_FLAGS) >> 11) {
+ case 0x0:
+ /*
+ * PSN Sequence Error!
+ * couldn't find a matching status!
+ */
+ *wc_status = IB_WC_GENERAL_ERR;
+ break;
+ case 0x1:
+ *wc_status = IB_WC_REM_INV_REQ_ERR;
+ break;
+ case 0x2:
+ *wc_status = IB_WC_REM_ACCESS_ERR;
+ break;
+ case 0x3:
+ *wc_status = IB_WC_REM_OP_ERR;
+ break;
+ case 0x4:
+ *wc_status = IB_WC_REM_INV_RD_REQ_ERR;
+ break;
+ }
+ break;
+ case 0x08:
+ *wc_status = IB_WC_RETRY_EXC_ERR;
+ break;
+ case 0x09:
+ *wc_status = IB_WC_RNR_RETRY_EXC_ERR;
+ break;
+ case 0x0A:
+ case 0x2D:
+ *wc_status = IB_WC_REM_ABORT_ERR;
+ break;
+ case 0x0B:
+ case 0x2E:
+ *wc_status = IB_WC_INV_EECN_ERR;
+ break;
+ case 0x0C:
+ case 0x2F:
+ *wc_status = IB_WC_INV_EEC_STATE_ERR;
+ break;
+ case 0x0D:
+ *wc_status = IB_WC_BAD_RESP_ERR;
+ break;
+ case 0x10:
+ /* WQE purged */
+ *wc_status = IB_WC_WR_FLUSH_ERR;
+ break;
+ default:
+ *wc_status = IB_WC_FATAL_ERR;
+
+ }
+ } else
+ *wc_status = IB_WC_SUCCESS;
+}
+
+int ehca_post_send(struct ib_qp *qp,
+ struct ib_send_wr *send_wr,
+ struct ib_send_wr **bad_send_wr)
+{
+ struct ehca_qp *my_qp = NULL;
+ struct ib_send_wr *cur_send_wr = NULL;
+ struct ehca_wqe *wqe_p = NULL;
+ int wqe_cnt = 0;
+ int ret = 0;
+ unsigned long spl_flags = 0;
+
+ EHCA_CHECK_ADR(qp);
+ my_qp = container_of(qp, struct ehca_qp, ib_qp);
+ EHCA_CHECK_QP(my_qp);
+ EHCA_CHECK_ADR(send_wr);
+ EDEB_EN(7, "ehca_qp=%p qp_num=%x send_wr=%p bad_send_wr=%p",
+ my_qp, qp->qp_num, send_wr, bad_send_wr);
+
+ /* LOCK the QUEUE */
+ spin_lock_irqsave(&my_qp->spinlock_s, spl_flags);
+
+ /* loop processes list of send reqs */
+ for (cur_send_wr = send_wr; cur_send_wr != NULL;
+ cur_send_wr = cur_send_wr->next) {
+ u64 start_offset = my_qp->ipz_squeue.current_q_offset;
+ /* get pointer next to free WQE */
+ wqe_p = ipz_qeit_get_inc(&my_qp->ipz_squeue);
+ if (unlikely(!wqe_p)) {
+ /* too many posted work requests: queue overflow */
+ if (bad_send_wr)
+ *bad_send_wr = cur_send_wr;
+ if (wqe_cnt == 0) {
+ ret = -ENOMEM;
+ EDEB_ERR(4, "Too many posted WQEs qp_num=%x",
+ qp->qp_num);
+ }
+ goto post_send_exit0;
+ }
+ /* write a SEND WQE into the QUEUE */
+ ret = ehca_write_swqe(my_qp, wqe_p, cur_send_wr);
+ /*
+ * if something failed,
+ * reset the free entry pointer to the start value
+ */
+ if (unlikely(ret)) {
+ my_qp->ipz_squeue.current_q_offset = start_offset;
+ *bad_send_wr = cur_send_wr;
+ if (wqe_cnt == 0) {
+ ret = -EINVAL;
+ EDEB_ERR(4, "Could not write WQE qp_num=%x",
+ qp->qp_num);
+ }
+ goto post_send_exit0;
+ }
+ wqe_cnt++;
+ EDEB(7, "ehca_qp=%p qp_num=%x wqe_cnt=%d",
+ my_qp, qp->qp_num, wqe_cnt);
+ } /* eof for cur_send_wr */
+
+post_send_exit0:
+ /* UNLOCK the QUEUE */
+ spin_unlock_irqrestore(&my_qp->spinlock_s, spl_flags);
+ iosync(); /* serialize GAL register access */
+ hipz_update_sqa(my_qp, wqe_cnt);
+ EDEB_EX(7, "ehca_qp=%p qp_num=%x ret=%x wqe_cnt=%d",
+ my_qp, qp->qp_num, ret, wqe_cnt);
+ return ret;
+}
+
+int ehca_post_recv(struct ib_qp *qp,
+ struct ib_recv_wr *recv_wr,
+ struct ib_recv_wr **bad_recv_wr)
+{
+ struct ehca_qp *my_qp = NULL;
+ struct ib_recv_wr *cur_recv_wr = NULL;
+ struct ehca_wqe *wqe_p = NULL;
+ int wqe_cnt = 0;
+ int ret = 0;
+ unsigned long spl_flags = 0;
+
+ EHCA_CHECK_ADR(qp);
+ my_qp = container_of(qp, struct ehca_qp, ib_qp);
+ EHCA_CHECK_QP(my_qp);
+ EHCA_CHECK_ADR(recv_wr);
+ EDEB_EN(7, "ehca_qp=%p qp_num=%x recv_wr=%p bad_recv_wr=%p",
+ my_qp, qp->qp_num, recv_wr, bad_recv_wr);
+
+ /* LOCK the QUEUE */
+ spin_lock_irqsave(&my_qp->spinlock_r, spl_flags);
+
+ /* loop processes list of send reqs */
+ for (cur_recv_wr = recv_wr; cur_recv_wr != NULL;
+ cur_recv_wr = cur_recv_wr->next) {
+ u64 start_offset = my_qp->ipz_rqueue.current_q_offset;
+ /* get pointer next to free WQE */
+ wqe_p = ipz_qeit_get_inc(&my_qp->ipz_rqueue);
+ if (unlikely(!wqe_p)) {
+ /* too many posted work requests: queue overflow */
+ if (bad_recv_wr)
+ *bad_recv_wr = cur_recv_wr;
+ if (wqe_cnt == 0) {
+ ret = -ENOMEM;
+ EDEB_ERR(4, "Too many posted WQEs qp_num=%x",
+ qp->qp_num);
+ }
+ goto post_recv_exit0;
+ }
+ /* write a RECV WQE into the QUEUE */
+ ret = ehca_write_rwqe(&my_qp->ipz_rqueue, wqe_p,
+ cur_recv_wr);
+ /*
+ * if something failed,
+ * reset the free entry pointer to the start value
+ */
+ if (unlikely(ret)) {
+ my_qp->ipz_rqueue.current_q_offset = start_offset;
+ *bad_recv_wr = cur_recv_wr;
+ if (wqe_cnt == 0) {
+ ret = -EINVAL;
+ EDEB_ERR(4, "Could not write WQE qp_num=%x",
+ qp->qp_num);
+ }
+ goto post_recv_exit0;
+ }
+ wqe_cnt++;
+ EDEB(7, "ehca_qp=%p qp_num=%x wqe_cnt=%d",
+ my_qp, qp->qp_num, wqe_cnt);
+ } /* eof for cur_recv_wr */
+
+post_recv_exit0:
+ spin_unlock_irqrestore(&my_qp->spinlock_r, spl_flags);
+ iosync(); /* serialize GAL register access */
+ hipz_update_rqa(my_qp, wqe_cnt);
+ EDEB_EX(7, "ehca_qp=%p qp_num=%x ret=%x wqe_cnt=%d",
+ my_qp, qp->qp_num, ret, wqe_cnt);
+ return ret;
+}
+
+/*
+ * ib_wc_opcode table converts ehca wc opcode to ib
+ * Since we use zero to indicate invalid opcode, the actual ib opcode must
+ * be decremented!!!
+ */
+static const u8 ib_wc_opcode[255] = {
+ [0x01] = IB_WC_RECV+1,
+ [0x02] = IB_WC_RECV_RDMA_WITH_IMM+1,
+ [0x04] = IB_WC_BIND_MW+1,
+ [0x08] = IB_WC_FETCH_ADD+1,
+ [0x10] = IB_WC_COMP_SWAP+1,
+ [0x20] = IB_WC_RDMA_WRITE+1,
+ [0x40] = IB_WC_RDMA_READ+1,
+ [0x80] = IB_WC_SEND+1
+};
+
+/* internal function to poll one entry of cq */
+static inline int ehca_poll_cq_one(struct ib_cq *cq, struct ib_wc *wc)
+{
+ int ret = 0;
+ struct ehca_cq *my_cq = container_of(cq, struct ehca_cq, ib_cq);
+ struct ehca_cqe *cqe = NULL;
+ int cqe_count = 0;
+
+ EDEB_EN(7, "ehca_cq=%p cq_num=%x wc=%p", my_cq, my_cq->cq_number, wc);
+
+poll_cq_one_read_cqe:
+ cqe = (struct ehca_cqe *)
+ ipz_qeit_get_inc_valid(&my_cq->ipz_queue);
+ if (!cqe) {
+ ret = -EAGAIN;
+ EDEB(7, "Completion queue is empty ehca_cq=%p cq_num=%x "
+ "ret=%x", my_cq, my_cq->cq_number, ret);
+ goto poll_cq_one_exit0;
+ }
+
+ /* prevents loads being reordered across this point */
+ rmb();
+
+ cqe_count++;
+ if (unlikely(cqe->status & WC_STATUS_PURGE_BIT)) {
+ struct ehca_qp *qp=ehca_cq_get_qp(my_cq, cqe->local_qp_number);
+ int purgeflag = 0;
+ unsigned long spl_flags = 0;
+ if (!qp) {
+ EDEB_ERR(4, "cq_num=%x qp_num=%x "
+ "could not find qp -> ignore cqe",
+ my_cq->cq_number, cqe->local_qp_number);
+ EDEB_DMP(4, cqe, 64, "cq_num=%x qp_num=%x",
+ my_cq->cq_number, cqe->local_qp_number);
+ /* ignore this purged cqe */
+ goto poll_cq_one_read_cqe;
+ }
+ spin_lock_irqsave(&qp->spinlock_s, spl_flags);
+ purgeflag = qp->sqerr_purgeflag;
+ spin_unlock_irqrestore(&qp->spinlock_s, spl_flags);
+
+ if (purgeflag) {
+ EDEB(6, "Got CQE with purged bit qp_num=%x src_qp=%x",
+ cqe->local_qp_number, cqe->remote_qp_number);
+ EDEB_DMP(6, cqe, 64, "qp_num=%x src_qp=%x",
+ cqe->local_qp_number, cqe->remote_qp_number);
+ /*
+ * ignore this to avoid double cqes of bad wqe
+ * that caused sqe and turn off purge flag
+ */
+ qp->sqerr_purgeflag = 0;
+ goto poll_cq_one_read_cqe;
+ }
+ }
+
+ /* tracing cqe */
+ if (IS_EDEB_ON(7)) {
+ EDEB(7, "Received COMPLETION ehca_cq=%p cq_num=%x -----",
+ my_cq, my_cq->cq_number);
+ EDEB_DMP(7, cqe, 64, "ehca_cq=%p cq_num=%x",
+ my_cq, my_cq->cq_number);
+ EDEB(7, "ehca_cq=%p cq_num=%x -------------------------",
+ my_cq, my_cq->cq_number);
+ }
+
+ /* we got a completion! */
+ wc->wr_id = cqe->work_request_id;
+
+ /* eval ib_wc_opcode */
+ wc->opcode = ib_wc_opcode[cqe->optype]-1;
+ if (unlikely(wc->opcode == -1)) {
+ EDEB_ERR(4, "Invalid cqe->OPType=%x cqe->status=%x "
+ "ehca_cq=%p cq_num=%x",
+ cqe->optype, cqe->status, my_cq, my_cq->cq_number);
+ /* dump cqe for other infos */
+ EDEB_DMP(4, cqe, 64, "ehca_cq=%p cq_num=%x",
+ my_cq, my_cq->cq_number);
+ /* update also queue adder to throw away this entry!!! */
+ goto poll_cq_one_exit0;
+ }
+ /* eval ib_wc_status */
+ if (unlikely(cqe->status & WC_STATUS_ERROR_BIT)) {
+ /* complete with errors */
+ map_ib_wc_status(cqe->status, &wc->status);
+ wc->vendor_err = wc->status;
+ } else
+ wc->status = IB_WC_SUCCESS;
+
+ wc->qp_num = cqe->local_qp_number;
+ wc->byte_len = cqe->nr_bytes_transferred;
+ wc->pkey_index = cqe->pkey_index;
+ wc->slid = cqe->rlid;
+ wc->dlid_path_bits = cqe->dlid;
+ wc->src_qp = cqe->remote_qp_number;
+ wc->wc_flags = cqe->w_completion_flags;
+ wc->imm_data = cpu_to_be32(cqe->immediate_data);
+ wc->sl = cqe->service_level;
+
+ if (wc->status != IB_WC_SUCCESS)
+ EDEB(6, "ehca_cq=%p cq_num=%x WARNING unsuccessful cqe "
+ "OPType=%x status=%x qp_num=%x src_qp=%x wr_id=%lx cqe=%p",
+ my_cq, my_cq->cq_number, cqe->optype, cqe->status,
+ cqe->local_qp_number, cqe->remote_qp_number,
+ cqe->work_request_id, cqe);
+
+poll_cq_one_exit0:
+ if (cqe_count > 0)
+ hipz_update_feca(my_cq, cqe_count);
+
+ EDEB_EX(7, "ret=%x ehca_cq=%p cq_number=%x wc=%p "
+ "status=%x opcode=%x qp_num=%x byte_len=%x",
+ ret, my_cq, my_cq->cq_number, wc, wc->status,
+ wc->opcode, wc->qp_num, wc->byte_len);
+
+ return ret;
+}
+
+int ehca_poll_cq(struct ib_cq *cq, int num_entries, struct ib_wc *wc)
+{
+ struct ehca_cq *my_cq = NULL;
+ int nr = 0;
+ struct ib_wc *current_wc = NULL;
+ int ret = 0;
+ unsigned long spl_flags = 0;
+
+ EHCA_CHECK_CQ(cq);
+ EHCA_CHECK_ADR(wc);
+
+ my_cq = container_of(cq, struct ehca_cq, ib_cq);
+ EHCA_CHECK_CQ(my_cq);
+
+ EDEB_EN(7, "ehca_cq=%p cq_num=%x num_entries=%d wc=%p",
+ my_cq, my_cq->cq_number, num_entries, wc);
+
+ if (num_entries < 1) {
+ EDEB_ERR(4, "Invalid num_entries=%d ehca_cq=%p cq_num=%x",
+ num_entries, my_cq, my_cq->cq_number);
+ ret = -EINVAL;
+ goto poll_cq_exit0;
+ }
+
+ current_wc = wc;
+ spin_lock_irqsave(&my_cq->spinlock, spl_flags);
+ for (nr = 0; nr < num_entries; nr++) {
+ ret = ehca_poll_cq_one(cq, current_wc);
+ if (ret)
+ break;
+ current_wc++;
+ } /* eof for nr */
+ spin_unlock_irqrestore(&my_cq->spinlock, spl_flags);
+ if (ret == -EAGAIN || !ret)
+ ret = nr;
+
+poll_cq_exit0:
+ EDEB_EX(7, "ehca_cq=%p cq_num=%x ret=%x wc=%p nr_entries=%d",
+ my_cq, my_cq->cq_number, ret, wc, nr);
+
+ return ret;
+}
+
+int ehca_req_notify_cq(struct ib_cq *cq, enum ib_cq_notify cq_notify)
+{
+ struct ehca_cq *my_cq = NULL;
+ int ret = 0;
+
+ EHCA_CHECK_CQ(cq);
+ my_cq = container_of(cq, struct ehca_cq, ib_cq);
+ EHCA_CHECK_CQ(my_cq);
+ EDEB_EN(7, "ehca_cq=%p cq_num=%x cq_notif=%x",
+ my_cq, my_cq->cq_number, cq_notify);
+
+ switch (cq_notify) {
+ case IB_CQ_SOLICITED:
+ hipz_set_cqx_n0(my_cq, 1);
+ break;
+ case IB_CQ_NEXT_COMP:
+ hipz_set_cqx_n1(my_cq, 1);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ EDEB_EX(7, "ehca_cq=%p cq_num=%x ret=%x",
+ my_cq, my_cq->cq_number, ret);
+
+ return ret;
+}
diff --git a/drivers/infiniband/hw/ehca/ehca_sqp.c b/drivers/infiniband/hw/ehca/ehca_sqp.c
new file mode 100644
index 0000000..d2c5552
--- /dev/null
+++ b/drivers/infiniband/hw/ehca/ehca_sqp.c
@@ -0,0 +1,123 @@
+/*
+ * IBM eServer eHCA Infiniband device driver for Linux on POWER
+ *
+ * SQP functions
+ *
+ * Authors: Khadija Souissi <souissi@de.ibm.com>
+ * Heiko J Schick <schickhj@de.ibm.com>
+ *
+ * Copyright (c) 2005 IBM Corporation
+ *
+ * All rights reserved.
+ *
+ * This source code is distributed under a dual license of GPL v2.0 and OpenIB
+ * BSD.
+ *
+ * OpenIB BSD License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials
+ * provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
+ * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+#define DEB_PREFIX "e_qp"
+
+#include <linux/module.h>
+#include <linux/err.h>
+#include "ehca_classes.h"
+#include "ehca_tools.h"
+#include "ehca_qes.h"
+#include "ehca_iverbs.h"
+#include "hcp_if.h"
+
+
+extern int ehca_create_aqp1(struct ehca_shca *shca, struct ehca_sport *sport);
+extern int ehca_destroy_aqp1(struct ehca_sport *sport);
+
+extern int ehca_port_act_time;
+
+/**
+ * ehca_define_sqp - Defines special queue pair 1 (GSI QP). When special queue
+ * pair is created successfully, the corresponding port gets active.
+ *
+ * Define Special Queue pair 0 (SMI QP) is still not supported.
+ *
+ * @qp_init_attr: Queue pair init attributes with port and queue pair type
+ */
+
+u64 ehca_define_sqp(struct ehca_shca *shca,
+ struct ehca_qp *ehca_qp,
+ struct ib_qp_init_attr *qp_init_attr)
+{
+
+ u32 pma_qp_nr = 0;
+ u32 bma_qp_nr = 0;
+ u64 ret = H_SUCCESS;
+ u8 port = qp_init_attr->port_num;
+ int counter = 0;
+
+ EDEB_EN(7, "port=%x qp_type=%x",
+ port, qp_init_attr->qp_type);
+
+ shca->sport[port - 1].port_state = IB_PORT_DOWN;
+
+ switch (qp_init_attr->qp_type) {
+ case IB_QPT_SMI:
+ /* function not supported yet */
+ break;
+ case IB_QPT_GSI:
+ ret = hipz_h_define_aqp1(shca->ipz_hca_handle,
+ ehca_qp->ipz_qp_handle,
+ ehca_qp->galpas.kernel,
+ (u32) qp_init_attr->port_num,
+ &pma_qp_nr, &bma_qp_nr);
+
+ if (ret != H_SUCCESS) {
+ EDEB_ERR(4, "Can't define AQP1 for port %x. rc=%lx",
+ port, ret);
+ goto ehca_define_aqp1;
+ }
+ break;
+ default:
+ ret = H_PARAMETER;
+ goto ehca_define_aqp1;
+ }
+
+ while ((shca->sport[port - 1].port_state != IB_PORT_ACTIVE) &&
+ (counter < ehca_port_act_time)) {
+ EDEB(6, "... wait until port %x is active",
+ port);
+ msleep_interruptible(1000);
+ counter++;
+ }
+
+ if (counter == ehca_port_act_time) {
+ EDEB_ERR(4, "Port %x is not active.", port);
+ ret = H_HARDWARE;
+ }
+
+ehca_define_aqp1:
+ EDEB_EX(7, "ret=%lx", ret);
+
+ return ret;
+}
--
1.4.1
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