* Re: [PATCH ] powerpc: Add tsi108/9 and non standard mpic support
From: Benjamin Herrenschmidt @ 2006-08-24 5:54 UTC (permalink / raw)
To: Zang Roy-r61911; +Cc: linuxppc-dev list, Paul Mackerras, Yang Xin-Xin-r48390
In-Reply-To: <1156398135.5913.43.camel@localhost.localdomain>
On Thu, 2006-08-24 at 13:42 +0800, Zang Roy-r61911 wrote:
> On Tue, 2006-08-22 at 18:07, Zang Roy-r61911 wrote:
> > The patch adds new hardware information table for mpic. This
> > enables mpic code to deal with mpic controller with
> > hardware behavior difference.
> >
> > CONFIG_MPIC_WEIRD is introduced in the code.
> > If a board with non standard mpic controller, it can select the
> > CONFIG_MPIC_WEIRD with board and add its hardware information
> > in the array mpic_infos.
> >
> > TSI108/109 PIC takes the first index of weird hardware information
> > table:) . The table can be extended. The Tsi108/109 PIC looks like
> > standard OpenPIC but, in fact, is different in registers mapping and
> > behavior.
The table should still contain the entries for a normal MPIC. One can
build a kernel that will boot both machines with the "weird" one and
with the normal one. Thus CONFIG_MPIC_WEIRD shall not exclude normal
MPICs, though not having it does exclude weird ones. I thus would
suggest to keep the table as it was in your earlier patches, that is
with the normal MPIC mapping at 0.
I intend to re-use that to handle another weird MPIC from some other
project :)
Cheers,
Ben.
> > The patch does not affect the behavior of standard mpic.
> > CONFIG_MPIC_WEIRD
> > excludes the weird mpic code when building standard mpic.
> >
> > Signed-off-by: Alexandre Bounine <alexandreb@tundra.com>
> > Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
> >
> Repost the patch. Fix the word wrap.
>
> ---
> arch/powerpc/Kconfig | 8 +-
> arch/powerpc/sysdev/Makefile | 1
> arch/powerpc/sysdev/mpic.c | 187 +++++++++++++++++++++++++++++-------------
> include/asm-powerpc/mpic.h | 114 ++++++++++++++++++++++++++
> 4 files changed, 252 insertions(+), 58 deletions(-)
>
> diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
> index abb325e..c88b647 100644
> --- a/arch/powerpc/Kconfig
> +++ b/arch/powerpc/Kconfig
> @@ -440,11 +440,15 @@ config U3_DART
> default n
>
> config MPIC
> - depends on PPC_PSERIES || PPC_PMAC || PPC_MAPLE || PPC_CHRP \
> - || MPC7448HPC2
> + depends on PPC_PSERIES || PPC_PMAC || PPC_MAPLE || PPC_CHRP
> bool
> default y
>
> +config MPIC_WEIRD
> + depends on MPC7448HPC2
> + bool
> + default y
> +
> config PPC_RTAS
> bool
> default n
> diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile
> index cebfae2..8ae887b 100644
> --- a/arch/powerpc/sysdev/Makefile
> +++ b/arch/powerpc/sysdev/Makefile
> @@ -3,6 +3,7 @@ EXTRA_CFLAGS += -mno-minimal-toc
> endif
>
> obj-$(CONFIG_MPIC) += mpic.o
> +obj-$(CONFIG_MPIC_WEIRD) += mpic.o
> obj-$(CONFIG_PPC_INDIRECT_PCI) += indirect_pci.o
> obj-$(CONFIG_PPC_MPC106) += grackle.o
> obj-$(CONFIG_BOOKE) += dcr.o
> diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c
> index 6e0281a..78e0515 100644
> --- a/arch/powerpc/sysdev/mpic.c
> +++ b/arch/powerpc/sysdev/mpic.c
> @@ -54,6 +54,55 @@ #define distribute_irqs (0)
> #endif
> #endif
>
> +#ifdef CONFIG_MPIC_WEIRD
> +static u32 mpic_infos[][INDEX_MPIC_WEIRD_END] = {
> + [0] = { /* Tsi108/109 PIC */
> + TSI108_GREG_BASE,
> + TSI108_GREG_FEATURE_0,
> + TSI108_GREG_GLOBAL_CONF_0,
> + TSI108_GREG_VENDOR_ID,
> + TSI108_GREG_IPI_VECTOR_PRI_0,
> + TSI108_GREG_IPI_STRIDE,
> + TSI108_GREG_SPURIOUS,
> + TSI108_GREG_TIMER_FREQ,
> +
> + TSI108_TIMER_BASE,
> + TSI108_TIMER_STRIDE,
> + TSI108_TIMER_CURRENT_CNT,
> + TSI108_TIMER_BASE_CNT,
> + TSI108_TIMER_VECTOR_PRI,
> + TSI108_TIMER_DESTINATION,
> +
> + TSI108_CPU_BASE,
> + TSI108_CPU_STRIDE,
> + TSI108_CPU_IPI_DISPATCH_0,
> + TSI108_CPU_IPI_DISPATCH_STRIDE,
> + TSI108_CPU_CURRENT_TASK_PRI,
> + TSI108_CPU_WHOAMI,
> + TSI108_CPU_INTACK,
> + TSI108_CPU_EOI,
> +
> + TSI108_IRQ_BASE,
> + TSI108_IRQ_STRIDE,
> + TSI108_IRQ_VECTOR_PRI,
> + TSI108_VECPRI_VECTOR_MASK,
> + TSI108_VECPRI_POLARITY_POSITIVE,
> + TSI108_VECPRI_POLARITY_NEGATIVE,
> + TSI108_VECPRI_SENSE_LEVEL,
> + TSI108_VECPRI_SENSE_EDGE,
> + TSI108_VECPRI_POLARITY_MASK,
> + TSI108_VECPRI_SENSE_MASK,
> + TSI108_IRQ_DESTINATION
> + },
> +};
> +#endif
> +
> +#ifdef CONFIG_MPIC_WEIRD
> +#define MPIC_INFO(name) mpic->hw_set[INDEX_##name]
> +#else
> +#define MPIC_INFO(name) MPIC_##name
> +#endif
> +
> /*
> * Register accessor functions
> */
> @@ -80,7 +129,8 @@ static inline void _mpic_write(unsigned
> static inline u32 _mpic_ipi_read(struct mpic *mpic, unsigned int ipi)
> {
> unsigned int be = (mpic->flags & MPIC_BIG_ENDIAN) != 0;
> - unsigned int offset = MPIC_GREG_IPI_VECTOR_PRI_0 + (ipi * 0x10);
> + unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +
> + (ipi * MPIC_INFO(GREG_IPI_STRIDE));
>
> if (mpic->flags & MPIC_BROKEN_IPI)
> be = !be;
> @@ -89,7 +139,8 @@ static inline u32 _mpic_ipi_read(struct
>
> static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 value)
> {
> - unsigned int offset = MPIC_GREG_IPI_VECTOR_PRI_0 + (ipi * 0x10);
> + unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +
> + (ipi * MPIC_INFO(GREG_IPI_STRIDE));
>
> _mpic_write(mpic->flags & MPIC_BIG_ENDIAN, mpic->gregs, offset, value);
> }
> @@ -120,7 +171,7 @@ static inline u32 _mpic_irq_read(struct
> unsigned int idx = src_no & mpic->isu_mask;
>
> return _mpic_read(mpic->flags & MPIC_BIG_ENDIAN, mpic->isus[isu],
> - reg + (idx * MPIC_IRQ_STRIDE));
> + reg + (idx * MPIC_INFO(IRQ_STRIDE)));
> }
>
> static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no,
> @@ -130,7 +181,7 @@ static inline void _mpic_irq_write(struc
> unsigned int idx = src_no & mpic->isu_mask;
>
> _mpic_write(mpic->flags & MPIC_BIG_ENDIAN, mpic->isus[isu],
> - reg + (idx * MPIC_IRQ_STRIDE), value);
> + reg + (idx * MPIC_INFO(IRQ_STRIDE)), value);
> }
>
> #define mpic_read(b,r) _mpic_read(mpic->flags & MPIC_BIG_ENDIAN,(b),(r))
> @@ -156,8 +207,8 @@ static void __init mpic_test_broken_ipi(
> {
> u32 r;
>
> - mpic_write(mpic->gregs, MPIC_GREG_IPI_VECTOR_PRI_0, MPIC_VECPRI_MASK);
> - r = mpic_read(mpic->gregs, MPIC_GREG_IPI_VECTOR_PRI_0);
> + mpic_write(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0), MPIC_VECPRI_MASK);
> + r = mpic_read(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0));
>
> if (r == le32_to_cpu(MPIC_VECPRI_MASK)) {
> printk(KERN_INFO "mpic: Detected reversed IPI registers\n");
> @@ -394,8 +445,8 @@ static inline struct mpic * mpic_from_ir
> /* Send an EOI */
> static inline void mpic_eoi(struct mpic *mpic)
> {
> - mpic_cpu_write(MPIC_CPU_EOI, 0);
> - (void)mpic_cpu_read(MPIC_CPU_WHOAMI);
> + mpic_cpu_write(MPIC_INFO(CPU_EOI), 0);
> + (void)mpic_cpu_read(MPIC_INFO(CPU_WHOAMI));
> }
>
> #ifdef CONFIG_SMP
> @@ -419,8 +470,8 @@ static void mpic_unmask_irq(unsigned int
>
> DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, irq, src);
>
> - mpic_irq_write(src, MPIC_IRQ_VECTOR_PRI,
> - mpic_irq_read(src, MPIC_IRQ_VECTOR_PRI) &
> + mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
> + mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) &
> ~MPIC_VECPRI_MASK);
> /* make sure mask gets to controller before we return to user */
> do {
> @@ -428,7 +479,7 @@ static void mpic_unmask_irq(unsigned int
> printk(KERN_ERR "mpic_enable_irq timeout\n");
> break;
> }
> - } while(mpic_irq_read(src, MPIC_IRQ_VECTOR_PRI) & MPIC_VECPRI_MASK);
> + } while(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK);
> }
>
> static void mpic_mask_irq(unsigned int irq)
> @@ -439,8 +490,8 @@ static void mpic_mask_irq(unsigned int i
>
> DBG("%s: disable_irq: %d (src %d)\n", mpic->name, irq, src);
>
> - mpic_irq_write(src, MPIC_IRQ_VECTOR_PRI,
> - mpic_irq_read(src, MPIC_IRQ_VECTOR_PRI) |
> + mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
> + mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) |
> MPIC_VECPRI_MASK);
>
> /* make sure mask gets to controller before we return to user */
> @@ -449,7 +500,7 @@ static void mpic_mask_irq(unsigned int i
> printk(KERN_ERR "mpic_enable_irq timeout\n");
> break;
> }
> - } while(!(mpic_irq_read(src, MPIC_IRQ_VECTOR_PRI) & MPIC_VECPRI_MASK));
> + } while(!(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK));
> }
>
> static void mpic_end_irq(unsigned int irq)
> @@ -560,24 +611,32 @@ static void mpic_set_affinity(unsigned i
>
> cpus_and(tmp, cpumask, cpu_online_map);
>
> - mpic_irq_write(src, MPIC_IRQ_DESTINATION,
> + mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION),
> mpic_physmask(cpus_addr(tmp)[0]));
> }
>
> +#ifdef CONFIG_MPIC_WEIRD
> +static unsigned int mpic_type_to_vecpri(struct mpic *mpic, unsigned int type)
> +#else
> static unsigned int mpic_type_to_vecpri(unsigned int type)
> +#endif
> {
> /* Now convert sense value */
> switch(type & IRQ_TYPE_SENSE_MASK) {
> case IRQ_TYPE_EDGE_RISING:
> - return MPIC_VECPRI_SENSE_EDGE | MPIC_VECPRI_POLARITY_POSITIVE;
> + return MPIC_INFO(VECPRI_SENSE_EDGE) |
> + MPIC_INFO(VECPRI_POLARITY_POSITIVE);
> case IRQ_TYPE_EDGE_FALLING:
> case IRQ_TYPE_EDGE_BOTH:
> - return MPIC_VECPRI_SENSE_EDGE | MPIC_VECPRI_POLARITY_NEGATIVE;
> + return MPIC_INFO(VECPRI_SENSE_EDGE) |
> + MPIC_INFO(VECPRI_POLARITY_NEGATIVE);
> case IRQ_TYPE_LEVEL_HIGH:
> - return MPIC_VECPRI_SENSE_LEVEL | MPIC_VECPRI_POLARITY_POSITIVE;
> + return MPIC_INFO(VECPRI_SENSE_LEVEL) |
> + MPIC_INFO(VECPRI_POLARITY_POSITIVE);
> case IRQ_TYPE_LEVEL_LOW:
> default:
> - return MPIC_VECPRI_SENSE_LEVEL | MPIC_VECPRI_POLARITY_NEGATIVE;
> + return MPIC_INFO(VECPRI_SENSE_LEVEL) |
> + MPIC_INFO(VECPRI_POLARITY_NEGATIVE);
> }
> }
>
> @@ -609,13 +668,18 @@ static int mpic_set_irq_type(unsigned in
> vecpri = MPIC_VECPRI_POLARITY_POSITIVE |
> MPIC_VECPRI_SENSE_EDGE;
> else
> +#ifdef CONFIG_MPIC_WEIRD
> + vecpri = mpic_type_to_vecpri(mpic, flow_type);
> +#else
> vecpri = mpic_type_to_vecpri(flow_type);
> +#endif
>
> - vold = mpic_irq_read(src, MPIC_IRQ_VECTOR_PRI);
> - vnew = vold & ~(MPIC_VECPRI_POLARITY_MASK | MPIC_VECPRI_SENSE_MASK);
> + vold = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
> + vnew = vold & ~(MPIC_INFO(VECPRI_POLARITY_MASK) |
> + MPIC_INFO(VECPRI_SENSE_MASK));
> vnew |= vecpri;
> if (vold != vnew)
> - mpic_irq_write(src, MPIC_IRQ_VECTOR_PRI, vnew);
> + mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vnew);
>
> return 0;
> }
> @@ -797,18 +861,23 @@ #endif /* CONFIG_SMP */
> mpic->isu_size = isu_size;
> mpic->irq_count = irq_count;
> mpic->num_sources = 0; /* so far */
> +
> +#ifdef CONFIG_MPIC_WEIRD
> + mpic->hw_set = mpic_infos[MPIC_GET_MOD_ID(flags)];
> +#endif
>
> /* Map the global registers */
> - mpic->gregs = ioremap(phys_addr + MPIC_GREG_BASE, 0x1000);
> - mpic->tmregs = mpic->gregs + ((MPIC_TIMER_BASE - MPIC_GREG_BASE) >> 2);
> + mpic->gregs = ioremap(phys_addr + MPIC_INFO(GREG_BASE), 0x1000);
> + mpic->tmregs = mpic->gregs +
> + ((MPIC_INFO(TIMER_BASE) - MPIC_INFO(GREG_BASE)) >> 2);
> BUG_ON(mpic->gregs == NULL);
>
> /* Reset */
> if (flags & MPIC_WANTS_RESET) {
> - mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_0,
> - mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_0)
> + mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
> + mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
> | MPIC_GREG_GCONF_RESET);
> - while( mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_0)
> + while( mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
> & MPIC_GREG_GCONF_RESET)
> mb();
> }
> @@ -817,7 +886,7 @@ #endif /* CONFIG_SMP */
> * MPICs, num sources as well. On ISU MPICs, sources are counted
> * as ISUs are added
> */
> - reg = mpic_read(mpic->gregs, MPIC_GREG_FEATURE_0);
> + reg = mpic_read(mpic->gregs, MPIC_INFO(GREG_FEATURE_0));
> mpic->num_cpus = ((reg & MPIC_GREG_FEATURE_LAST_CPU_MASK)
> >> MPIC_GREG_FEATURE_LAST_CPU_SHIFT) + 1;
> if (isu_size == 0)
> @@ -826,16 +895,16 @@ #endif /* CONFIG_SMP */
>
> /* Map the per-CPU registers */
> for (i = 0; i < mpic->num_cpus; i++) {
> - mpic->cpuregs[i] = ioremap(phys_addr + MPIC_CPU_BASE +
> - i * MPIC_CPU_STRIDE, 0x1000);
> + mpic->cpuregs[i] = ioremap(phys_addr + MPIC_INFO(CPU_BASE) +
> + i * MPIC_INFO(CPU_STRIDE), 0x1000);
> BUG_ON(mpic->cpuregs[i] == NULL);
> }
>
> /* Initialize main ISU if none provided */
> if (mpic->isu_size == 0) {
> mpic->isu_size = mpic->num_sources;
> - mpic->isus[0] = ioremap(phys_addr + MPIC_IRQ_BASE,
> - MPIC_IRQ_STRIDE * mpic->isu_size);
> + mpic->isus[0] = ioremap(phys_addr + MPIC_INFO(IRQ_BASE),
> + MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);
> BUG_ON(mpic->isus[0] == NULL);
> }
> mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1);
> @@ -879,7 +948,8 @@ void __init mpic_assign_isu(struct mpic
>
> BUG_ON(isu_num >= MPIC_MAX_ISU);
>
> - mpic->isus[isu_num] = ioremap(phys_addr, MPIC_IRQ_STRIDE * mpic->isu_size);
> + mpic->isus[isu_num] = ioremap(phys_addr,
> + MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);
> if ((isu_first + mpic->isu_size) > mpic->num_sources)
> mpic->num_sources = isu_first + mpic->isu_size;
> }
> @@ -904,14 +974,16 @@ void __init mpic_init(struct mpic *mpic)
> printk(KERN_INFO "mpic: Initializing for %d sources\n", mpic->num_sources);
>
> /* Set current processor priority to max */
> - mpic_cpu_write(MPIC_CPU_CURRENT_TASK_PRI, 0xf);
> + mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
>
> /* Initialize timers: just disable them all */
> for (i = 0; i < 4; i++) {
> mpic_write(mpic->tmregs,
> - i * MPIC_TIMER_STRIDE + MPIC_TIMER_DESTINATION, 0);
> + i * MPIC_INFO(TIMER_STRIDE) +
> + MPIC_INFO(TIMER_DESTINATION), 0);
> mpic_write(mpic->tmregs,
> - i * MPIC_TIMER_STRIDE + MPIC_TIMER_VECTOR_PRI,
> + i * MPIC_INFO(TIMER_STRIDE) +
> + MPIC_INFO(TIMER_VECTOR_PRI),
> MPIC_VECPRI_MASK |
> (MPIC_VEC_TIMER_0 + i));
> }
> @@ -940,21 +1012,23 @@ void __init mpic_init(struct mpic *mpic)
> (8 << MPIC_VECPRI_PRIORITY_SHIFT);
>
> /* init hw */
> - mpic_irq_write(i, MPIC_IRQ_VECTOR_PRI, vecpri);
> - mpic_irq_write(i, MPIC_IRQ_DESTINATION,
> + mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);
> + mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
> 1 << hard_smp_processor_id());
> }
>
> /* Init spurrious vector */
> - mpic_write(mpic->gregs, MPIC_GREG_SPURIOUS, MPIC_VEC_SPURRIOUS);
> + mpic_write(mpic->gregs, MPIC_INFO(GREG_SPURIOUS), MPIC_VEC_SPURRIOUS);
>
> - /* Disable 8259 passthrough */
> - mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_0,
> - mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_0)
> + /* Disable 8259 passthrough, if supported */
> +#ifndef CONFIG_MPIC_WEIRD
> + mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
> + mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
> | MPIC_GREG_GCONF_8259_PTHROU_DIS);
> +#endif
>
> /* Set current processor priority to 0 */
> - mpic_cpu_write(MPIC_CPU_CURRENT_TASK_PRI, 0);
> + mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);
> }
>
> void __init mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio)
> @@ -997,9 +1071,9 @@ void mpic_irq_set_priority(unsigned int
> mpic_ipi_write(src - MPIC_VEC_IPI_0,
> reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
> } else {
> - reg = mpic_irq_read(src, MPIC_IRQ_VECTOR_PRI)
> + reg = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI))
> & ~MPIC_VECPRI_PRIORITY_MASK;
> - mpic_irq_write(src, MPIC_IRQ_VECTOR_PRI,
> + mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
> reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
> }
> spin_unlock_irqrestore(&mpic_lock, flags);
> @@ -1017,7 +1091,7 @@ unsigned int mpic_irq_get_priority(unsig
> if (is_ipi)
> reg = mpic_ipi_read(src = MPIC_VEC_IPI_0);
> else
> - reg = mpic_irq_read(src, MPIC_IRQ_VECTOR_PRI);
> + reg = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
> spin_unlock_irqrestore(&mpic_lock, flags);
> return (reg & MPIC_VECPRI_PRIORITY_MASK) >> MPIC_VECPRI_PRIORITY_SHIFT;
> }
> @@ -1043,12 +1117,12 @@ #ifdef CONFIG_SMP
> */
> if (distribute_irqs) {
> for (i = 0; i < mpic->num_sources ; i++)
> - mpic_irq_write(i, MPIC_IRQ_DESTINATION,
> - mpic_irq_read(i, MPIC_IRQ_DESTINATION) | msk);
> + mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
> + mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) | msk);
> }
>
> /* Set current processor priority to 0 */
> - mpic_cpu_write(MPIC_CPU_CURRENT_TASK_PRI, 0);
> + mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);
>
> spin_unlock_irqrestore(&mpic_lock, flags);
> #endif /* CONFIG_SMP */
> @@ -1058,7 +1132,7 @@ int mpic_cpu_get_priority(void)
> {
> struct mpic *mpic = mpic_primary;
>
> - return mpic_cpu_read(MPIC_CPU_CURRENT_TASK_PRI);
> + return mpic_cpu_read(MPIC_INFO(CPU_CURRENT_TASK_PRI));
> }
>
> void mpic_cpu_set_priority(int prio)
> @@ -1066,7 +1140,7 @@ void mpic_cpu_set_priority(int prio)
> struct mpic *mpic = mpic_primary;
>
> prio &= MPIC_CPU_TASKPRI_MASK;
> - mpic_cpu_write(MPIC_CPU_CURRENT_TASK_PRI, prio);
> + mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), prio);
> }
>
> /*
> @@ -1088,11 +1162,11 @@ void mpic_teardown_this_cpu(int secondar
>
> /* let the mpic know we don't want intrs. */
> for (i = 0; i < mpic->num_sources ; i++)
> - mpic_irq_write(i, MPIC_IRQ_DESTINATION,
> - mpic_irq_read(i, MPIC_IRQ_DESTINATION) & ~msk);
> + mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
> + mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) & ~msk);
>
> /* Set current processor priority to max */
> - mpic_cpu_write(MPIC_CPU_CURRENT_TASK_PRI, 0xf);
> + mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
>
> spin_unlock_irqrestore(&mpic_lock, flags);
> }
> @@ -1108,7 +1182,8 @@ #ifdef DEBUG_IPI
> DBG("%s: send_ipi(ipi_no: %d)\n", mpic->name, ipi_no);
> #endif
>
> - mpic_cpu_write(MPIC_CPU_IPI_DISPATCH_0 + ipi_no * 0x10,
> + mpic_cpu_write(MPIC_INFO(CPU_IPI_DISPATCH_0) +
> + ipi_no * MPIC_INFO(CPU_IPI_DISPATCH_STRIDE),
> mpic_physmask(cpu_mask & cpus_addr(cpu_online_map)[0]));
> }
>
> @@ -1116,7 +1191,7 @@ unsigned int mpic_get_one_irq(struct mpi
> {
> u32 src;
>
> - src = mpic_cpu_read(MPIC_CPU_INTACK) & MPIC_VECPRI_VECTOR_MASK;
> + src = mpic_cpu_read(MPIC_INFO(CPU_INTACK)) & MPIC_INFO(VECPRI_VECTOR_MASK);
> #ifdef DEBUG_LOW
> DBG("%s: get_one_irq(): %d\n", mpic->name, src);
> #endif
> diff --git a/include/asm-powerpc/mpic.h b/include/asm-powerpc/mpic.h
> index eb241c9..faebdf2 100644
> --- a/include/asm-powerpc/mpic.h
> +++ b/include/asm-powerpc/mpic.h
> @@ -41,6 +41,7 @@ #define MPIC_GREG_IPI_VECTOR_PRI_0 0x000
> #define MPIC_GREG_IPI_VECTOR_PRI_1 0x000b0
> #define MPIC_GREG_IPI_VECTOR_PRI_2 0x000c0
> #define MPIC_GREG_IPI_VECTOR_PRI_3 0x000d0
> +#define MPIC_GREG_IPI_STRIDE 0x10
> #define MPIC_GREG_SPURIOUS 0x000e0
> #define MPIC_GREG_TIMER_FREQ 0x000f0
>
> @@ -68,6 +69,7 @@ #define MPIC_CPU_IPI_DISPATCH_0 0x00040
> #define MPIC_CPU_IPI_DISPATCH_1 0x00050
> #define MPIC_CPU_IPI_DISPATCH_2 0x00060
> #define MPIC_CPU_IPI_DISPATCH_3 0x00070
> +#define MPIC_CPU_IPI_DISPATCH_STRIDE 0x00010
> #define MPIC_CPU_CURRENT_TASK_PRI 0x00080
> #define MPIC_CPU_TASKPRI_MASK 0x0000000f
> #define MPIC_CPU_WHOAMI 0x00090
> @@ -114,6 +116,103 @@ #define MPIC_VEC_TIMER_2 249
> #define MPIC_VEC_TIMER_1 248
> #define MPIC_VEC_TIMER_0 247
>
> +#ifdef CONFIG_MPIC_WEIRD
> +/*
> + * Tsi108 implementation of MPIC has many differences from the original one
> + */
> +
> +/*
> + * Global registers
> + */
> +
> +#define TSI108_GREG_BASE 0x00000
> +#define TSI108_GREG_FEATURE_0 0x00000
> +#define TSI108_GREG_GLOBAL_CONF_0 0x00004
> +#define TSI108_GREG_VENDOR_ID 0x0000c
> +#define TSI108_GREG_IPI_VECTOR_PRI_0 0x00204 /* Doorbell 0 */
> +#define TSI108_GREG_IPI_STRIDE 0x0c
> +#define TSI108_GREG_SPURIOUS 0x00010
> +#define TSI108_GREG_TIMER_FREQ 0x00014
> +
> +/*
> + * Timer registers
> + */
> +#define TSI108_TIMER_BASE 0x0030
> +#define TSI108_TIMER_STRIDE 0x10
> +#define TSI108_TIMER_CURRENT_CNT 0x00000
> +#define TSI108_TIMER_BASE_CNT 0x00004
> +#define TSI108_TIMER_VECTOR_PRI 0x00008
> +#define TSI108_TIMER_DESTINATION 0x0000c
> +
> +/*
> + * Per-Processor registers
> + */
> +#define TSI108_CPU_BASE 0x00300
> +#define TSI108_CPU_STRIDE 0x00040
> +#define TSI108_CPU_IPI_DISPATCH_0 0x00200
> +#define TSI108_CPU_IPI_DISPATCH_STRIDE 0x00000
> +#define TSI108_CPU_CURRENT_TASK_PRI 0x00000
> +#define TSI108_CPU_WHOAMI 0xffffffff
> +#define TSI108_CPU_INTACK 0x00004
> +#define TSI108_CPU_EOI 0x00008
> +
> +/*
> + * Per-source registers
> + */
> +#define TSI108_IRQ_BASE 0x00100
> +#define TSI108_IRQ_STRIDE 0x00008
> +#define TSI108_IRQ_VECTOR_PRI 0x00000
> +#define TSI108_VECPRI_VECTOR_MASK 0x000000ff
> +#define TSI108_VECPRI_POLARITY_POSITIVE 0x01000000
> +#define TSI108_VECPRI_POLARITY_NEGATIVE 0x00000000
> +#define TSI108_VECPRI_SENSE_LEVEL 0x02000000
> +#define TSI108_VECPRI_SENSE_EDGE 0x00000000
> +#define TSI108_VECPRI_POLARITY_MASK 0x01000000
> +#define TSI108_VECPRI_SENSE_MASK 0x02000000
> +#define TSI108_IRQ_DESTINATION 0x00004
> +
> +/* weird mpic variable index in the HW info array */
> +enum MPIC_WEIRD_INDEX {
> + INDEX_GREG_BASE = 0, /* Offset of global registers from MPIC base */
> + INDEX_GREG_FEATURE_0, /* FRR0 offset from base */
> + INDEX_GREG_GLOBAL_CONF_0, /* Global Config register offset from base */
> + INDEX_GREG_VENDOR_ID, /* VID register offset from base */
> + INDEX_GREG_IPI_VECTOR_PRI_0, /* IPI Vector/Priority Registers */
> + INDEX_GREG_IPI_STRIDE, /* IPI Vector/Priority Registers spacing */
> + INDEX_GREG_SPURIOUS, /* Spurious Vector Register */
> + INDEX_GREG_TIMER_FREQ, /* Global Timer Frequency Reporting Register */
> +
> + INDEX_TIMER_BASE, /* Global Timer Registers base */
> + INDEX_TIMER_STRIDE, /* Global Timer Registers spacing */
> + INDEX_TIMER_CURRENT_CNT, /* Global Timer Current Count Register */
> + INDEX_TIMER_BASE_CNT, /* Global Timer Base Count Register */
> + INDEX_TIMER_VECTOR_PRI, /* Global Timer Vector/Priority Register */
> + INDEX_TIMER_DESTINATION, /* Global Timer Destination Register */
> +
> + INDEX_CPU_BASE, /* Offset of cpu base */
> + INDEX_CPU_STRIDE, /* Cpu register spacing*/
> + INDEX_CPU_IPI_DISPATCH_0, /* IPI 0 Dispatch Command Register */
> + INDEX_CPU_IPI_DISPATCH_STRIDE, /* IPI Dispatch spacing */
> + INDEX_CPU_CURRENT_TASK_PRI,/* Processor Current Task Priority Register */
> + INDEX_CPU_WHOAMI, /* Who Am I Register */
> + INDEX_CPU_INTACK, /* Interrupt Acknowledge Register */
> + INDEX_CPU_EOI, /* End of Interrupt Register */
> +
> + INDEX_IRQ_BASE, /* Interrupt registers base */
> + INDEX_IRQ_STRIDE, /* Interrupt registers spacing */
> + INDEX_IRQ_VECTOR_PRI, /* Interrupt Vector/Priority Register */
> + INDEX_VECPRI_VECTOR_MASK, /* Interrupt Vector Mask */
> + INDEX_VECPRI_POLARITY_POSITIVE, /* Interrupt Positive Polarity bit */
> + INDEX_VECPRI_POLARITY_NEGATIVE, /* Interrupt Negative Polarity bit */
> + INDEX_VECPRI_SENSE_LEVEL, /* Interrupt Level Sense bit */
> + INDEX_VECPRI_SENSE_EDGE, /* Interrupt edge Sense bit */
> + INDEX_VECPRI_POLARITY_MASK, /* Interrupt Polarity mask */
> + INDEX_VECPRI_SENSE_MASK, /* Interrupt sense mask */
> + INDEX_IRQ_DESTINATION, /* Interrupt Destination Register */
> + INDEX_MPIC_WEIRD_END /* Size of the hw info array */
> +};
> +#endif
> +
> #ifdef CONFIG_MPIC_BROKEN_U3
> /* Fixup table entry */
> struct mpic_irq_fixup
> @@ -170,6 +269,11 @@ #endif
> volatile u32 __iomem *tmregs;
> volatile u32 __iomem *cpuregs[MPIC_MAX_CPUS];
> volatile u32 __iomem *isus[MPIC_MAX_ISU];
> +
> +#ifdef CONFIG_MPIC_WEIRD
> + /* Pointer to HW info array */
> + u32 *hw_set;
> +#endif
>
> /* link */
> struct mpic *next;
> @@ -189,6 +293,16 @@ #define MPIC_BROKEN_IPI 0x00000008
> /* MPIC wants a reset */
> #define MPIC_WANTS_RESET 0x00000010
>
> +#ifdef CONFIG_MPIC_WEIRD
> +/* Spurious vector requires EOI */
> +#define MPIC_SPV_EOI 0x00000020
> +/* MPIC HW modification ID */
> +#define MPIC_MOD_ID_MASK 0x00000f00
> +#define MPIC_MOD_ID(val) (((val) << 8) & MPIC_MOD_ID_MASK)
> +#define MPIC_GET_MOD_ID(flags) (((flags) & MPIC_MOD_ID_MASK) >> 8)
> +#define MPIC_ID_TSI108 0 /* Tsi108/109 PIC */
> +#endif
> +
> /* Allocate the controller structure and setup the linux irq descs
> * for the range if interrupts passed in. No HW initialization is
> * actually performed.
^ permalink raw reply
* RE: [PATCH ] powerpc: pass UPIO_TSI flag to 8259 serial driver
From: Zang Roy-r61911 @ 2006-08-24 5:54 UTC (permalink / raw)
To: Li Yang-r58472, Benjamin Herrenschmidt
Cc: linuxppc-dev list, Paul Mackerras, Yang Xin-Xin-r48390
In-Reply-To: <4879B0C6C249214CBE7AB04453F84E4D0FC2F6@zch01exm20.fsl.freescale.net>
> > On Thu, 2006-08-24 at 13:17, Benjamin Herrenschmidt wrote:
> > > > Evolution 1.2.2. I had found the reason and tested on my side.
> > > > Paul, if you do not modify it by hand, please select=20
> the following
> > > :-).
> > > > I will repost the mpic and mpc7448hph2 irq update=20
> patch.Very sorry
> > > for that.
> > >
> > > Ok, the trick with evolution is to use the "preformat" style.
> > >
> > > Typically, when posting a patch, I write my description, put the=20
> > > caret where I want to insert the patch itself, set the style to=20
> > > "Preformat" (from the pop-up menu just above the text=20
> editing zone),=20
> > > and do Insert->Text File from the menu.
> > >
> > > You can also select a bit of text/patch and change the style to=20
> > > "Preformat" afterward if you missed it before doing the import.
> > >
> > You words are principle to post patch with evolution :-).
>=20
> Why did no one ever add a mail client guide to the kernel=20
> documentation? It seems such problem happens a lot.
>=20
I think there should be one in other place. But we do not know where it
is.
I have tried Thunderbird, but failed.
Roy
^ permalink raw reply
* RE: [PATCH 1/3] Adapt ipic driver to new host_ops interface, addset_irq_type to set IRQ sense
From: Benjamin Herrenschmidt @ 2006-08-24 5:56 UTC (permalink / raw)
To: Li Yang-r58472; +Cc: linuxppc-dev, Phillips Kim-R1AAHA
In-Reply-To: <4879B0C6C249214CBE7AB04453F84E4D0FC2F3@zch01exm20.fsl.freescale.net>
> But for IRQ with a specified type, set_irq_type() will be called two
> times continuously. Why not call the set_irq_type() in any case in
> irq_create_of_mapping()?
well... it would still not be called by irq_create_mapping() (the non-OF
one). You need to make sure your stuff is properly initialized in the
case there it's not called. That is that you have a proper default irq
type, handler, and HW setup after host_map() returns.
It's not terribly harmful to have set_irq_type() called twice. Another
option is to have host_map re-do what your set_type() does, or move the
common code into a low level __set_type() that gets called by both
set_irq_type() and your host_map ...
Ben.
^ permalink raw reply
* Re: [PATCH] powerpc: emulate power5 popcntb instruction
From: Paul Mackerras @ 2006-08-24 6:36 UTC (permalink / raw)
To: will_schmidt; +Cc: linuxppc-dev, arnd, segher
In-Reply-To: <1156190965.9659.41.camel@farscape.rchland.ibm.com>
Will Schmidt writes:
> I'm not Arnd :-) , but since I'm poking at it anyways,.. how about
> this?
I just did a patch to fix the existing masks. Could you do a new
version of this patch that doesn't include the unrelated mask fixes
please? Also it would be really nice if you could figure out a way to
avoid doing the unnecessary 64-bit logical operations on 32-bit
machines - i.e. using an unsigned long for tmp, but then the constants
become problematic. Maybe you need something like
#define LCONST(x) ((unsigned long)(x##ULL))
Thanks,
Paul.
^ permalink raw reply
* [PATCH] Split out vpa unregister logic from pseries_kexec_cpu_down_xics()
From: Michael Ellerman @ 2006-08-24 6:54 UTC (permalink / raw)
To: Paul Mackerras; +Cc: Michael Neuling, linuxppc-dev
As part of the new irq code pseries_kexec_cpu_down() was split into a
xics and mpic version. The vpa unregister logic is now only done in the
xics routine, and although that's ok in practice (we don't have SPLPAR
machines with mpic), I'd rather have the two concepts stay separate.
So move the vpa unregister into pseries_kexec_cpu_down(), which gets called
by both the xics and mpic routines. This also gives us an obvious place to
put any new kexec-down logic needed in future.
Signed-off-by: Michael Ellerman <michael@ellerman.id.au>
---
arch/powerpc/platforms/pseries/setup.c | 18 ++++++++++++------
1 file changed, 12 insertions(+), 6 deletions(-)
Index: to-merge/arch/powerpc/platforms/pseries/setup.c
===================================================================
--- to-merge.orig/arch/powerpc/platforms/pseries/setup.c
+++ to-merge/arch/powerpc/platforms/pseries/setup.c
@@ -223,12 +223,7 @@ static void pseries_lpar_enable_pmcs(voi
}
#ifdef CONFIG_KEXEC
-static void pseries_kexec_cpu_down_mpic(int crash_shutdown, int secondary)
-{
- mpic_teardown_this_cpu(secondary);
-}
-
-static void pseries_kexec_cpu_down_xics(int crash_shutdown, int secondary)
+static void pseries_kexec_cpu_down(int crash_shutdown, int secondary)
{
/* Don't risk a hypervisor call if we're crashing */
if (firmware_has_feature(FW_FEATURE_SPLPAR) && !crash_shutdown) {
@@ -248,6 +243,17 @@ static void pseries_kexec_cpu_down_xics(
hard_smp_processor_id());
}
}
+}
+
+static void pseries_kexec_cpu_down_mpic(int crash_shutdown, int secondary)
+{
+ pseries_kexec_cpu_down(crash_shutdown, secondary);
+ mpic_teardown_this_cpu(secondary);
+}
+
+static void pseries_kexec_cpu_down_xics(int crash_shutdown, int secondary)
+{
+ pseries_kexec_cpu_down(crash_shutdown, secondary);
xics_teardown_cpu(secondary);
}
#endif /* CONFIG_KEXEC */
^ permalink raw reply
* Re: [PATCH] powerpc: Instrument Hypervisor Calls
From: Paul Mackerras @ 2006-08-24 6:55 UTC (permalink / raw)
To: Mike Kravetz; +Cc: linuxppc-dev
In-Reply-To: <20060816160456.GA4170@w-mikek2.ibm.com>
Mike Kravetz writes:
> Add instrumentation for hypervisor calls on pseries. Call statistics
> include number of calls, wall time and cpu cycles (if available) and
> are made available via debugfs. Instrumentation code is behind the
> HCALL_STATS config option and has no impact if not enabled.
Starting to look really good, just a few minor comments below...
> +/*
> + * precall must preserve all registers. use unused STK_PARM()
> + * areas to save snapshots and opcode.
> + */
> +#define HCALL_INST_PRECALL \
> + std r3,STK_PARM(r3)(r1); /* save opcode */ \
> + mftb r3; /* get timebase and */ \
> + std r3,STK_PARM(r5)(r1); /* save for later */ \
> +BEGIN_FTR_SECTION; \
> + mfspr r3,SPRN_PURR; /* get PURR and */ \
> + std r3,STK_PARM(r6)(r1); /* save for later */ \
> +END_FTR_SECTION_IFSET(CPU_FTR_PURR); \
> + ld r3,STK_PARM(r3)(r1); /* opcode back in r3 */
You can use r0 here; maybe you could use it instead of having to
restore r3 (I see that you still need to save r3 for later).
> + * postcall is performed immediately before function return which
> + * allows liberal use of volital registers.
"volatile"
> + /* calculate address of stat structure */ \
> + ld r4,STK_PARM(r3)(r1); /* use opcode as */ \
> + rldicl r4,r4,62,2; /* index into array */ \
> + mulli r4,r4,HCALL_STAT_SIZE; \
It's a pity our multiplies are slow (6 cycles). The rldicl would I
think be more clearly expressed as srdi r4,r4,2. We could use a shift
and add instead of the multiply if we put a big fat comment in the
header that defines the structure warning people to adjust the
assembly if they change the structure. Might not be worth it though.
> + LOAD_REG_ADDR(r7, per_cpu__hcall_stats); \
We could use a load from the TOC here rather than the 5 instructions
that LOAD_REG_ADDR turns into. Look at some gcc -S output to see how
it's done.
BTW are we going to die horribly if someone uses an hcall greater than
MAX_HCALL_OPCODES? The hcall functions are available to modules, so
it would be quite possible for a module to come along and try to use
some new hcalls that weren't known about when the kernel was built.
Paul.
^ permalink raw reply
* Re: [PATCH] Split out vpa unregister logic from pseries_kexec_cpu_down_xics()
From: Benjamin Herrenschmidt @ 2006-08-24 7:33 UTC (permalink / raw)
To: Michael Ellerman; +Cc: linuxppc-dev, Michael Neuling, Paul Mackerras
In-Reply-To: <20060824065409.645DD67C42@ozlabs.org>
On Thu, 2006-08-24 at 16:54 +1000, Michael Ellerman wrote:
> As part of the new irq code pseries_kexec_cpu_down() was split into a
> xics and mpic version. The vpa unregister logic is now only done in the
> xics routine, and although that's ok in practice (we don't have SPLPAR
> machines with mpic), I'd rather have the two concepts stay separate.
>
> So move the vpa unregister into pseries_kexec_cpu_down(), which gets called
> by both the xics and mpic routines. This also gives us an obvious place to
> put any new kexec-down logic needed in future.
>
> Signed-off-by: Michael Ellerman <michael@ellerman.id.au>
Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
^ permalink raw reply
* RE: [PATCH 1/3] Adapt ipic driver to new host_ops interface, addset_irq_type to set IRQ sense
From: Li Yang-r58472 @ 2006-08-24 7:39 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev, Phillips Kim-R1AAHA
In-Reply-To: <1156398982.8433.200.camel@localhost.localdomain>
> -----Original Message-----
> From: Benjamin Herrenschmidt [mailto:benh@kernel.crashing.org]
> Sent: Thursday, August 24, 2006 1:56 PM
> To: Li Yang-r58472
> Cc: Phillips Kim-R1AAHA; linuxppc-dev@ozlabs.org
> Subject: RE: [PATCH 1/3] Adapt ipic driver to new host_ops
> interface,addset_irq_type to set IRQ sense
>=20
>=20
> > But for IRQ with a specified type, set_irq_type() will be called two
> > times continuously. Why not call the set_irq_type() in any case in
> > irq_create_of_mapping()?
>=20
> well... it would still not be called by irq_create_mapping() (the
non-OF
> one). You need to make sure your stuff is properly initialized in the
> case there it's not called. That is that you have a proper default irq
> type, handler, and HW setup after host_map() returns.
>=20
> It's not terribly harmful to have set_irq_type() called twice. Another
> option is to have host_map re-do what your set_type() does, or move
the
> common code into a low level __set_type() that gets called by both
> set_irq_type() and your host_map ...
Currently, it's difficult to get the irq type in host_map() before it is
set in set_type(). Shall we add flow_type to the host_map() parameters?
^ permalink raw reply
* RE: [PATCH 1/3] Adapt ipic driver to new host_ops interface,addset_irq_type to set IRQ sense
From: Benjamin Herrenschmidt @ 2006-08-24 7:58 UTC (permalink / raw)
To: Li Yang-r58472; +Cc: linuxppc-dev, Phillips Kim-R1AAHA
In-Reply-To: <4879B0C6C249214CBE7AB04453F84E4D0FC344@zch01exm20.fsl.freescale.net>
> Currently, it's difficult to get the irq type in host_map() before it is
> set in set_type(). Shall we add flow_type to the host_map() parameters?
I had that and decided to remove it for various reasons. host_map() can
set it to the default, it doesn't really matter if you end up with
multiple calls.
Ben.
^ permalink raw reply
* I2C driver for SAA7121 on MPC855 and linux-2.4.25
From: Xu, Li (GE, Research) @ 2006-08-24 8:02 UTC (permalink / raw)
To: linuxppc-embedded
Hi,
I am trying to setup i2c driver for saa7121 on my mpc855 based board
normally the address for saa7121 is 0x88, but when I enable i2c bus
scan, the driver detect it's address is 0x34, so I just stick to 0x34.
Anyway, I can write to saa7121via i2c bus successfully, but I can't =
enable
color bar, so I don't know whether the driver is working properly or =
not?
BTW, I setup I2C driver for SAA7113 and it works fine.
Tim
^ permalink raw reply
* Re: [PATCH] powerpc: update mpc7448hpc2 board irq supportusingdevice tree
From: Zang Roy-r61911 @ 2006-08-24 8:36 UTC (permalink / raw)
To: Benjamin Herrenschmidt
Cc: linuxppc-dev list, Paul Mackerras, Alexandre.Bounine,
Yang Xin-Xin-r48390
In-Reply-To: <1156398659.8433.193.camel@localhost.localdomain>
On Thu, 2006-08-24 at 13:50, Benjamin Herrenschmidt wrote:
> > -struct hw_interrupt_type tsi108_pci_irq = {
> > +static struct irq_chip tsi108_pci_irq = {
> > .typename = "tsi108_PCI_int",
> > - .enable = tsi108_pci_irq_enable,
> > - .disable = tsi108_pci_irq_disable,
> > + .mask = tsi108_pci_irq_disable,
> > .ack = tsi108_pci_irq_ack,
> > .end = tsi108_pci_irq_end,
> > + .unmask = tsi108_pci_irq_enable,
> > };
> >
> > /*
>
> While the patch as-is looks ok, it also looks like you could take
> advantage of the new genirq code to clean up your TSI irq handling a
> bit. You probably don't need a end() handler anymore provided that you
> properly set your main handler to be either level, edge or fasteoi (in
> which case, you need an eoi handler).
I need the end() handler. The main handler can not proper process the
case.
Roy
^ permalink raw reply
* Re: [PATCH] powerpc: update mpc7448hpc2 board irq supportusingdevice tree
From: Benjamin Herrenschmidt @ 2006-08-24 8:53 UTC (permalink / raw)
To: Zang Roy-r61911
Cc: linuxppc-dev list, Paul Mackerras, Alexandre.Bounine,
Yang Xin-Xin-r48390
In-Reply-To: <1156408565.6591.2.camel@localhost.localdomain>
On Thu, 2006-08-24 at 16:36 +0800, Zang Roy-r61911 wrote:
> On Thu, 2006-08-24 at 13:50, Benjamin Herrenschmidt wrote:
> > > -struct hw_interrupt_type tsi108_pci_irq = {
> > > +static struct irq_chip tsi108_pci_irq = {
> > > .typename = "tsi108_PCI_int",
> > > - .enable = tsi108_pci_irq_enable,
> > > - .disable = tsi108_pci_irq_disable,
> > > + .mask = tsi108_pci_irq_disable,
> > > .ack = tsi108_pci_irq_ack,
> > > .end = tsi108_pci_irq_end,
> > > + .unmask = tsi108_pci_irq_enable,
> > > };
> > >
> > > /*
> >
> > While the patch as-is looks ok, it also looks like you could take
> > advantage of the new genirq code to clean up your TSI irq handling a
> > bit. You probably don't need a end() handler anymore provided that you
> > properly set your main handler to be either level, edge or fasteoi (in
> > which case, you need an eoi handler).
> I need the end() handler. The main handler can not proper process the
> case.
None of the 3 main handlers in kernel/irq/chip.c (You can set them at
host_map time with set_irq_chip_and_handler, if you don't do it, you end
up with the old-style main handler, but one of the 3 new ones might be
more suitable to your flow) ? Strange... I would need to look in more
details, but it's not urgent, the current stuff should work.
Ben
^ permalink raw reply
* Re: [PATCH ] powerpc: Add tsi108/9 and non standard mpic support
From: Zang Roy-r61911 @ 2006-08-24 9:52 UTC (permalink / raw)
To: Benjamin Herrenschmidt
Cc: linuxppc-dev list, Paul Mackerras, Yang Xin-Xin-r48390
In-Reply-To: <1156398861.8433.197.camel@localhost.localdomain>
On Thu, 2006-08-24 at 13:54, Benjamin Herrenschmidt wrote:
> On Thu, 2006-08-24 at 13:42 +0800, Zang Roy-r61911 wrote:
> > On Tue, 2006-08-22 at 18:07, Zang Roy-r61911 wrote:
> > > The patch adds new hardware information table for mpic. This
> > > enables mpic code to deal with mpic controller with
> > > hardware behavior difference.
> > >
> > > CONFIG_MPIC_WEIRD is introduced in the code.
> > > If a board with non standard mpic controller, it can select the
> > > CONFIG_MPIC_WEIRD with board and add its hardware information
> > > in the array mpic_infos.
> > >
> > > TSI108/109 PIC takes the first index of weird hardware
> information
> > > table:) . The table can be extended. The Tsi108/109 PIC looks
> like
> > > standard OpenPIC but, in fact, is different in registers mapping
> and
> > > behavior.
>
> The table should still contain the entries for a normal MPIC. One can
> build a kernel that will boot both machines with the "weird" one and
> with the normal one. Thus CONFIG_MPIC_WEIRD shall not exclude normal
> MPICs, though not having it does exclude weird ones. I thus would
> suggest to keep the table as it was in your earlier patches, that is
> with the normal MPIC mapping at 0.
>
> I intend to re-use that to handle another weird MPIC from some other
> project :)
That is also my target. I hope the imported mpic_info table can support
more non-standard mpic structure.
The following patch adds the standard MPIC entry to the table.
I post it here.
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
---
arch/powerpc/Kconfig | 8 +
arch/powerpc/sysdev/Makefile | 1
arch/powerpc/sysdev/mpic.c | 225 ++++++++++++++++++++++++++++++++----------
include/asm-powerpc/mpic.h | 115 +++++++++++++++++++++
4 files changed, 291 insertions(+), 58 deletions(-)
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index abb325e..c88b647 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -440,11 +440,15 @@ config U3_DART
default n
config MPIC
- depends on PPC_PSERIES || PPC_PMAC || PPC_MAPLE || PPC_CHRP \
- || MPC7448HPC2
+ depends on PPC_PSERIES || PPC_PMAC || PPC_MAPLE || PPC_CHRP
bool
default y
+config MPIC_WEIRD
+ depends on MPC7448HPC2
+ bool
+ default y
+
config PPC_RTAS
bool
default n
diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile
index cebfae2..8ae887b 100644
--- a/arch/powerpc/sysdev/Makefile
+++ b/arch/powerpc/sysdev/Makefile
@@ -3,6 +3,7 @@ EXTRA_CFLAGS += -mno-minimal-toc
endif
obj-$(CONFIG_MPIC) += mpic.o
+obj-$(CONFIG_MPIC_WEIRD) += mpic.o
obj-$(CONFIG_PPC_INDIRECT_PCI) += indirect_pci.o
obj-$(CONFIG_PPC_MPC106) += grackle.o
obj-$(CONFIG_BOOKE) += dcr.o
diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c
index 6e0281a..9a2ad1f 100644
--- a/arch/powerpc/sysdev/mpic.c
+++ b/arch/powerpc/sysdev/mpic.c
@@ -54,6 +54,93 @@ #define distribute_irqs (0)
#endif
#endif
+#ifdef CONFIG_MPIC_WEIRD
+static u32 mpic_infos[][INDEX_MPIC_WEIRD_END] = {
+ [0] = { /* Original OpenPIC compatible MPIC */
+ MPIC_GREG_BASE,
+ MPIC_GREG_FEATURE_0,
+ MPIC_GREG_GLOBAL_CONF_0,
+ MPIC_GREG_VENDOR_ID,
+ MPIC_GREG_IPI_VECTOR_PRI_0,
+ MPIC_GREG_IPI_STRIDE,
+ MPIC_GREG_SPURIOUS,
+ MPIC_GREG_TIMER_FREQ,
+
+ MPIC_TIMER_BASE,
+ MPIC_TIMER_STRIDE,
+ MPIC_TIMER_CURRENT_CNT,
+ MPIC_TIMER_BASE_CNT,
+ MPIC_TIMER_VECTOR_PRI,
+ MPIC_TIMER_DESTINATION,
+
+ MPIC_CPU_BASE,
+ MPIC_CPU_STRIDE,
+ MPIC_CPU_IPI_DISPATCH_0,
+ MPIC_CPU_IPI_DISPATCH_STRIDE,
+ MPIC_CPU_CURRENT_TASK_PRI,
+ MPIC_CPU_WHOAMI,
+ MPIC_CPU_INTACK,
+ MPIC_CPU_EOI,
+
+ MPIC_IRQ_BASE,
+ MPIC_IRQ_STRIDE,
+ MPIC_IRQ_VECTOR_PRI,
+ MPIC_VECPRI_VECTOR_MASK,
+ MPIC_VECPRI_POLARITY_POSITIVE,
+ MPIC_VECPRI_POLARITY_NEGATIVE,
+ MPIC_VECPRI_SENSE_LEVEL,
+ MPIC_VECPRI_SENSE_EDGE,
+ MPIC_VECPRI_POLARITY_MASK,
+ MPIC_VECPRI_SENSE_MASK,
+ MPIC_IRQ_DESTINATION
+ },
+ [1] = { /* Tsi108/109 PIC */
+ TSI108_GREG_BASE,
+ TSI108_GREG_FEATURE_0,
+ TSI108_GREG_GLOBAL_CONF_0,
+ TSI108_GREG_VENDOR_ID,
+ TSI108_GREG_IPI_VECTOR_PRI_0,
+ TSI108_GREG_IPI_STRIDE,
+ TSI108_GREG_SPURIOUS,
+ TSI108_GREG_TIMER_FREQ,
+
+ TSI108_TIMER_BASE,
+ TSI108_TIMER_STRIDE,
+ TSI108_TIMER_CURRENT_CNT,
+ TSI108_TIMER_BASE_CNT,
+ TSI108_TIMER_VECTOR_PRI,
+ TSI108_TIMER_DESTINATION,
+
+ TSI108_CPU_BASE,
+ TSI108_CPU_STRIDE,
+ TSI108_CPU_IPI_DISPATCH_0,
+ TSI108_CPU_IPI_DISPATCH_STRIDE,
+ TSI108_CPU_CURRENT_TASK_PRI,
+ TSI108_CPU_WHOAMI,
+ TSI108_CPU_INTACK,
+ TSI108_CPU_EOI,
+
+ TSI108_IRQ_BASE,
+ TSI108_IRQ_STRIDE,
+ TSI108_IRQ_VECTOR_PRI,
+ TSI108_VECPRI_VECTOR_MASK,
+ TSI108_VECPRI_POLARITY_POSITIVE,
+ TSI108_VECPRI_POLARITY_NEGATIVE,
+ TSI108_VECPRI_SENSE_LEVEL,
+ TSI108_VECPRI_SENSE_EDGE,
+ TSI108_VECPRI_POLARITY_MASK,
+ TSI108_VECPRI_SENSE_MASK,
+ TSI108_IRQ_DESTINATION
+ },
+};
+#endif
+
+#ifdef CONFIG_MPIC_WEIRD
+#define MPIC_INFO(name) mpic->hw_set[INDEX_##name]
+#else
+#define MPIC_INFO(name) MPIC_##name
+#endif
+
/*
* Register accessor functions
*/
@@ -80,7 +167,8 @@ static inline void _mpic_write(unsigned
static inline u32 _mpic_ipi_read(struct mpic *mpic, unsigned int ipi)
{
unsigned int be = (mpic->flags & MPIC_BIG_ENDIAN) != 0;
- unsigned int offset = MPIC_GREG_IPI_VECTOR_PRI_0 + (ipi * 0x10);
+ unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +
+ (ipi * MPIC_INFO(GREG_IPI_STRIDE));
if (mpic->flags & MPIC_BROKEN_IPI)
be = !be;
@@ -89,7 +177,8 @@ static inline u32 _mpic_ipi_read(struct
static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 value)
{
- unsigned int offset = MPIC_GREG_IPI_VECTOR_PRI_0 + (ipi * 0x10);
+ unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +
+ (ipi * MPIC_INFO(GREG_IPI_STRIDE));
_mpic_write(mpic->flags & MPIC_BIG_ENDIAN, mpic->gregs, offset, value);
}
@@ -120,7 +209,7 @@ static inline u32 _mpic_irq_read(struct
unsigned int idx = src_no & mpic->isu_mask;
return _mpic_read(mpic->flags & MPIC_BIG_ENDIAN, mpic->isus[isu],
- reg + (idx * MPIC_IRQ_STRIDE));
+ reg + (idx * MPIC_INFO(IRQ_STRIDE)));
}
static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no,
@@ -130,7 +219,7 @@ static inline void _mpic_irq_write(struc
unsigned int idx = src_no & mpic->isu_mask;
_mpic_write(mpic->flags & MPIC_BIG_ENDIAN, mpic->isus[isu],
- reg + (idx * MPIC_IRQ_STRIDE), value);
+ reg + (idx * MPIC_INFO(IRQ_STRIDE)), value);
}
#define mpic_read(b,r) _mpic_read(mpic->flags & MPIC_BIG_ENDIAN,(b),(r))
@@ -156,8 +245,8 @@ static void __init mpic_test_broken_ipi(
{
u32 r;
- mpic_write(mpic->gregs, MPIC_GREG_IPI_VECTOR_PRI_0, MPIC_VECPRI_MASK);
- r = mpic_read(mpic->gregs, MPIC_GREG_IPI_VECTOR_PRI_0);
+ mpic_write(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0), MPIC_VECPRI_MASK);
+ r = mpic_read(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0));
if (r == le32_to_cpu(MPIC_VECPRI_MASK)) {
printk(KERN_INFO "mpic: Detected reversed IPI registers\n");
@@ -394,8 +483,8 @@ static inline struct mpic * mpic_from_ir
/* Send an EOI */
static inline void mpic_eoi(struct mpic *mpic)
{
- mpic_cpu_write(MPIC_CPU_EOI, 0);
- (void)mpic_cpu_read(MPIC_CPU_WHOAMI);
+ mpic_cpu_write(MPIC_INFO(CPU_EOI), 0);
+ (void)mpic_cpu_read(MPIC_INFO(CPU_WHOAMI));
}
#ifdef CONFIG_SMP
@@ -419,8 +508,8 @@ static void mpic_unmask_irq(unsigned int
DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, irq, src);
- mpic_irq_write(src, MPIC_IRQ_VECTOR_PRI,
- mpic_irq_read(src, MPIC_IRQ_VECTOR_PRI) &
+ mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
+ mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) &
~MPIC_VECPRI_MASK);
/* make sure mask gets to controller before we return to user */
do {
@@ -428,7 +517,7 @@ static void mpic_unmask_irq(unsigned int
printk(KERN_ERR "mpic_enable_irq timeout\n");
break;
}
- } while(mpic_irq_read(src, MPIC_IRQ_VECTOR_PRI) & MPIC_VECPRI_MASK);
+ } while(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK);
}
static void mpic_mask_irq(unsigned int irq)
@@ -439,8 +528,8 @@ static void mpic_mask_irq(unsigned int i
DBG("%s: disable_irq: %d (src %d)\n", mpic->name, irq, src);
- mpic_irq_write(src, MPIC_IRQ_VECTOR_PRI,
- mpic_irq_read(src, MPIC_IRQ_VECTOR_PRI) |
+ mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
+ mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) |
MPIC_VECPRI_MASK);
/* make sure mask gets to controller before we return to user */
@@ -449,7 +538,7 @@ static void mpic_mask_irq(unsigned int i
printk(KERN_ERR "mpic_enable_irq timeout\n");
break;
}
- } while(!(mpic_irq_read(src, MPIC_IRQ_VECTOR_PRI) & MPIC_VECPRI_MASK));
+ } while(!(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK));
}
static void mpic_end_irq(unsigned int irq)
@@ -560,24 +649,32 @@ static void mpic_set_affinity(unsigned i
cpus_and(tmp, cpumask, cpu_online_map);
- mpic_irq_write(src, MPIC_IRQ_DESTINATION,
+ mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION),
mpic_physmask(cpus_addr(tmp)[0]));
}
+#ifdef CONFIG_MPIC_WEIRD
+static unsigned int mpic_type_to_vecpri(struct mpic *mpic, unsigned int type)
+#else
static unsigned int mpic_type_to_vecpri(unsigned int type)
+#endif
{
/* Now convert sense value */
switch(type & IRQ_TYPE_SENSE_MASK) {
case IRQ_TYPE_EDGE_RISING:
- return MPIC_VECPRI_SENSE_EDGE | MPIC_VECPRI_POLARITY_POSITIVE;
+ return MPIC_INFO(VECPRI_SENSE_EDGE) |
+ MPIC_INFO(VECPRI_POLARITY_POSITIVE);
case IRQ_TYPE_EDGE_FALLING:
case IRQ_TYPE_EDGE_BOTH:
- return MPIC_VECPRI_SENSE_EDGE | MPIC_VECPRI_POLARITY_NEGATIVE;
+ return MPIC_INFO(VECPRI_SENSE_EDGE) |
+ MPIC_INFO(VECPRI_POLARITY_NEGATIVE);
case IRQ_TYPE_LEVEL_HIGH:
- return MPIC_VECPRI_SENSE_LEVEL | MPIC_VECPRI_POLARITY_POSITIVE;
+ return MPIC_INFO(VECPRI_SENSE_LEVEL) |
+ MPIC_INFO(VECPRI_POLARITY_POSITIVE);
case IRQ_TYPE_LEVEL_LOW:
default:
- return MPIC_VECPRI_SENSE_LEVEL | MPIC_VECPRI_POLARITY_NEGATIVE;
+ return MPIC_INFO(VECPRI_SENSE_LEVEL) |
+ MPIC_INFO(VECPRI_POLARITY_NEGATIVE);
}
}
@@ -609,13 +706,18 @@ static int mpic_set_irq_type(unsigned in
vecpri = MPIC_VECPRI_POLARITY_POSITIVE |
MPIC_VECPRI_SENSE_EDGE;
else
+#ifdef CONFIG_MPIC_WEIRD
+ vecpri = mpic_type_to_vecpri(mpic, flow_type);
+#else
vecpri = mpic_type_to_vecpri(flow_type);
+#endif
- vold = mpic_irq_read(src, MPIC_IRQ_VECTOR_PRI);
- vnew = vold & ~(MPIC_VECPRI_POLARITY_MASK | MPIC_VECPRI_SENSE_MASK);
+ vold = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
+ vnew = vold & ~(MPIC_INFO(VECPRI_POLARITY_MASK) |
+ MPIC_INFO(VECPRI_SENSE_MASK));
vnew |= vecpri;
if (vold != vnew)
- mpic_irq_write(src, MPIC_IRQ_VECTOR_PRI, vnew);
+ mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vnew);
return 0;
}
@@ -797,18 +899,23 @@ #endif /* CONFIG_SMP */
mpic->isu_size = isu_size;
mpic->irq_count = irq_count;
mpic->num_sources = 0; /* so far */
+
+#ifdef CONFIG_MPIC_WEIRD
+ mpic->hw_set = mpic_infos[MPIC_GET_MOD_ID(flags)];
+#endif
/* Map the global registers */
- mpic->gregs = ioremap(phys_addr + MPIC_GREG_BASE, 0x1000);
- mpic->tmregs = mpic->gregs + ((MPIC_TIMER_BASE - MPIC_GREG_BASE) >> 2);
+ mpic->gregs = ioremap(phys_addr + MPIC_INFO(GREG_BASE), 0x1000);
+ mpic->tmregs = mpic->gregs +
+ ((MPIC_INFO(TIMER_BASE) - MPIC_INFO(GREG_BASE)) >> 2);
BUG_ON(mpic->gregs == NULL);
/* Reset */
if (flags & MPIC_WANTS_RESET) {
- mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_0,
- mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_0)
+ mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
+ mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
| MPIC_GREG_GCONF_RESET);
- while( mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_0)
+ while( mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
& MPIC_GREG_GCONF_RESET)
mb();
}
@@ -817,7 +924,7 @@ #endif /* CONFIG_SMP */
* MPICs, num sources as well. On ISU MPICs, sources are counted
* as ISUs are added
*/
- reg = mpic_read(mpic->gregs, MPIC_GREG_FEATURE_0);
+ reg = mpic_read(mpic->gregs, MPIC_INFO(GREG_FEATURE_0));
mpic->num_cpus = ((reg & MPIC_GREG_FEATURE_LAST_CPU_MASK)
>> MPIC_GREG_FEATURE_LAST_CPU_SHIFT) + 1;
if (isu_size == 0)
@@ -826,16 +933,16 @@ #endif /* CONFIG_SMP */
/* Map the per-CPU registers */
for (i = 0; i < mpic->num_cpus; i++) {
- mpic->cpuregs[i] = ioremap(phys_addr + MPIC_CPU_BASE +
- i * MPIC_CPU_STRIDE, 0x1000);
+ mpic->cpuregs[i] = ioremap(phys_addr + MPIC_INFO(CPU_BASE) +
+ i * MPIC_INFO(CPU_STRIDE), 0x1000);
BUG_ON(mpic->cpuregs[i] == NULL);
}
/* Initialize main ISU if none provided */
if (mpic->isu_size == 0) {
mpic->isu_size = mpic->num_sources;
- mpic->isus[0] = ioremap(phys_addr + MPIC_IRQ_BASE,
- MPIC_IRQ_STRIDE * mpic->isu_size);
+ mpic->isus[0] = ioremap(phys_addr + MPIC_INFO(IRQ_BASE),
+ MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);
BUG_ON(mpic->isus[0] == NULL);
}
mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1);
@@ -879,7 +986,8 @@ void __init mpic_assign_isu(struct mpic
BUG_ON(isu_num >= MPIC_MAX_ISU);
- mpic->isus[isu_num] = ioremap(phys_addr, MPIC_IRQ_STRIDE * mpic->isu_size);
+ mpic->isus[isu_num] = ioremap(phys_addr,
+ MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);
if ((isu_first + mpic->isu_size) > mpic->num_sources)
mpic->num_sources = isu_first + mpic->isu_size;
}
@@ -904,14 +1012,16 @@ void __init mpic_init(struct mpic *mpic)
printk(KERN_INFO "mpic: Initializing for %d sources\n", mpic->num_sources);
/* Set current processor priority to max */
- mpic_cpu_write(MPIC_CPU_CURRENT_TASK_PRI, 0xf);
+ mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
/* Initialize timers: just disable them all */
for (i = 0; i < 4; i++) {
mpic_write(mpic->tmregs,
- i * MPIC_TIMER_STRIDE + MPIC_TIMER_DESTINATION, 0);
+ i * MPIC_INFO(TIMER_STRIDE) +
+ MPIC_INFO(TIMER_DESTINATION), 0);
mpic_write(mpic->tmregs,
- i * MPIC_TIMER_STRIDE + MPIC_TIMER_VECTOR_PRI,
+ i * MPIC_INFO(TIMER_STRIDE) +
+ MPIC_INFO(TIMER_VECTOR_PRI),
MPIC_VECPRI_MASK |
(MPIC_VEC_TIMER_0 + i));
}
@@ -940,21 +1050,23 @@ void __init mpic_init(struct mpic *mpic)
(8 << MPIC_VECPRI_PRIORITY_SHIFT);
/* init hw */
- mpic_irq_write(i, MPIC_IRQ_VECTOR_PRI, vecpri);
- mpic_irq_write(i, MPIC_IRQ_DESTINATION,
+ mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);
+ mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1 << hard_smp_processor_id());
}
/* Init spurrious vector */
- mpic_write(mpic->gregs, MPIC_GREG_SPURIOUS, MPIC_VEC_SPURRIOUS);
+ mpic_write(mpic->gregs, MPIC_INFO(GREG_SPURIOUS), MPIC_VEC_SPURRIOUS);
- /* Disable 8259 passthrough */
- mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_0,
- mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_0)
+ /* Disable 8259 passthrough, if supported */
+#ifndef CONFIG_MPIC_WEIRD
+ mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
+ mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
| MPIC_GREG_GCONF_8259_PTHROU_DIS);
+#endif
/* Set current processor priority to 0 */
- mpic_cpu_write(MPIC_CPU_CURRENT_TASK_PRI, 0);
+ mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);
}
void __init mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio)
@@ -997,9 +1109,9 @@ void mpic_irq_set_priority(unsigned int
mpic_ipi_write(src - MPIC_VEC_IPI_0,
reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
} else {
- reg = mpic_irq_read(src, MPIC_IRQ_VECTOR_PRI)
+ reg = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI))
& ~MPIC_VECPRI_PRIORITY_MASK;
- mpic_irq_write(src, MPIC_IRQ_VECTOR_PRI,
+ mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
}
spin_unlock_irqrestore(&mpic_lock, flags);
@@ -1017,7 +1129,7 @@ unsigned int mpic_irq_get_priority(unsig
if (is_ipi)
reg = mpic_ipi_read(src = MPIC_VEC_IPI_0);
else
- reg = mpic_irq_read(src, MPIC_IRQ_VECTOR_PRI);
+ reg = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
spin_unlock_irqrestore(&mpic_lock, flags);
return (reg & MPIC_VECPRI_PRIORITY_MASK) >> MPIC_VECPRI_PRIORITY_SHIFT;
}
@@ -1043,12 +1155,12 @@ #ifdef CONFIG_SMP
*/
if (distribute_irqs) {
for (i = 0; i < mpic->num_sources ; i++)
- mpic_irq_write(i, MPIC_IRQ_DESTINATION,
- mpic_irq_read(i, MPIC_IRQ_DESTINATION) | msk);
+ mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
+ mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) | msk);
}
/* Set current processor priority to 0 */
- mpic_cpu_write(MPIC_CPU_CURRENT_TASK_PRI, 0);
+ mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);
spin_unlock_irqrestore(&mpic_lock, flags);
#endif /* CONFIG_SMP */
@@ -1058,7 +1170,7 @@ int mpic_cpu_get_priority(void)
{
struct mpic *mpic = mpic_primary;
- return mpic_cpu_read(MPIC_CPU_CURRENT_TASK_PRI);
+ return mpic_cpu_read(MPIC_INFO(CPU_CURRENT_TASK_PRI));
}
void mpic_cpu_set_priority(int prio)
@@ -1066,7 +1178,7 @@ void mpic_cpu_set_priority(int prio)
struct mpic *mpic = mpic_primary;
prio &= MPIC_CPU_TASKPRI_MASK;
- mpic_cpu_write(MPIC_CPU_CURRENT_TASK_PRI, prio);
+ mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), prio);
}
/*
@@ -1088,11 +1200,11 @@ void mpic_teardown_this_cpu(int secondar
/* let the mpic know we don't want intrs. */
for (i = 0; i < mpic->num_sources ; i++)
- mpic_irq_write(i, MPIC_IRQ_DESTINATION,
- mpic_irq_read(i, MPIC_IRQ_DESTINATION) & ~msk);
+ mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
+ mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) & ~msk);
/* Set current processor priority to max */
- mpic_cpu_write(MPIC_CPU_CURRENT_TASK_PRI, 0xf);
+ mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
spin_unlock_irqrestore(&mpic_lock, flags);
}
@@ -1108,7 +1220,8 @@ #ifdef DEBUG_IPI
DBG("%s: send_ipi(ipi_no: %d)\n", mpic->name, ipi_no);
#endif
- mpic_cpu_write(MPIC_CPU_IPI_DISPATCH_0 + ipi_no * 0x10,
+ mpic_cpu_write(MPIC_INFO(CPU_IPI_DISPATCH_0) +
+ ipi_no * MPIC_INFO(CPU_IPI_DISPATCH_STRIDE),
mpic_physmask(cpu_mask & cpus_addr(cpu_online_map)[0]));
}
@@ -1116,7 +1229,7 @@ unsigned int mpic_get_one_irq(struct mpi
{
u32 src;
- src = mpic_cpu_read(MPIC_CPU_INTACK) & MPIC_VECPRI_VECTOR_MASK;
+ src = mpic_cpu_read(MPIC_INFO(CPU_INTACK)) & MPIC_INFO(VECPRI_VECTOR_MASK);
#ifdef DEBUG_LOW
DBG("%s: get_one_irq(): %d\n", mpic->name, src);
#endif
diff --git a/include/asm-powerpc/mpic.h b/include/asm-powerpc/mpic.h
index eb241c9..a70ef57 100644
--- a/include/asm-powerpc/mpic.h
+++ b/include/asm-powerpc/mpic.h
@@ -41,6 +41,7 @@ #define MPIC_GREG_IPI_VECTOR_PRI_0 0x000
#define MPIC_GREG_IPI_VECTOR_PRI_1 0x000b0
#define MPIC_GREG_IPI_VECTOR_PRI_2 0x000c0
#define MPIC_GREG_IPI_VECTOR_PRI_3 0x000d0
+#define MPIC_GREG_IPI_STRIDE 0x10
#define MPIC_GREG_SPURIOUS 0x000e0
#define MPIC_GREG_TIMER_FREQ 0x000f0
@@ -68,6 +69,7 @@ #define MPIC_CPU_IPI_DISPATCH_0 0x00040
#define MPIC_CPU_IPI_DISPATCH_1 0x00050
#define MPIC_CPU_IPI_DISPATCH_2 0x00060
#define MPIC_CPU_IPI_DISPATCH_3 0x00070
+#define MPIC_CPU_IPI_DISPATCH_STRIDE 0x00010
#define MPIC_CPU_CURRENT_TASK_PRI 0x00080
#define MPIC_CPU_TASKPRI_MASK 0x0000000f
#define MPIC_CPU_WHOAMI 0x00090
@@ -114,6 +116,103 @@ #define MPIC_VEC_TIMER_2 249
#define MPIC_VEC_TIMER_1 248
#define MPIC_VEC_TIMER_0 247
+#ifdef CONFIG_MPIC_WEIRD
+/*
+ * Tsi108 implementation of MPIC has many differences from the original one
+ */
+
+/*
+ * Global registers
+ */
+
+#define TSI108_GREG_BASE 0x00000
+#define TSI108_GREG_FEATURE_0 0x00000
+#define TSI108_GREG_GLOBAL_CONF_0 0x00004
+#define TSI108_GREG_VENDOR_ID 0x0000c
+#define TSI108_GREG_IPI_VECTOR_PRI_0 0x00204 /* Doorbell 0 */
+#define TSI108_GREG_IPI_STRIDE 0x0c
+#define TSI108_GREG_SPURIOUS 0x00010
+#define TSI108_GREG_TIMER_FREQ 0x00014
+
+/*
+ * Timer registers
+ */
+#define TSI108_TIMER_BASE 0x0030
+#define TSI108_TIMER_STRIDE 0x10
+#define TSI108_TIMER_CURRENT_CNT 0x00000
+#define TSI108_TIMER_BASE_CNT 0x00004
+#define TSI108_TIMER_VECTOR_PRI 0x00008
+#define TSI108_TIMER_DESTINATION 0x0000c
+
+/*
+ * Per-Processor registers
+ */
+#define TSI108_CPU_BASE 0x00300
+#define TSI108_CPU_STRIDE 0x00040
+#define TSI108_CPU_IPI_DISPATCH_0 0x00200
+#define TSI108_CPU_IPI_DISPATCH_STRIDE 0x00000
+#define TSI108_CPU_CURRENT_TASK_PRI 0x00000
+#define TSI108_CPU_WHOAMI 0xffffffff
+#define TSI108_CPU_INTACK 0x00004
+#define TSI108_CPU_EOI 0x00008
+
+/*
+ * Per-source registers
+ */
+#define TSI108_IRQ_BASE 0x00100
+#define TSI108_IRQ_STRIDE 0x00008
+#define TSI108_IRQ_VECTOR_PRI 0x00000
+#define TSI108_VECPRI_VECTOR_MASK 0x000000ff
+#define TSI108_VECPRI_POLARITY_POSITIVE 0x01000000
+#define TSI108_VECPRI_POLARITY_NEGATIVE 0x00000000
+#define TSI108_VECPRI_SENSE_LEVEL 0x02000000
+#define TSI108_VECPRI_SENSE_EDGE 0x00000000
+#define TSI108_VECPRI_POLARITY_MASK 0x01000000
+#define TSI108_VECPRI_SENSE_MASK 0x02000000
+#define TSI108_IRQ_DESTINATION 0x00004
+
+/* weird mpic variable index in the HW info array */
+enum MPIC_WEIRD_INDEX {
+ INDEX_GREG_BASE = 0, /* Offset of global registers from MPIC base */
+ INDEX_GREG_FEATURE_0, /* FRR0 offset from base */
+ INDEX_GREG_GLOBAL_CONF_0, /* Global Config register offset from base */
+ INDEX_GREG_VENDOR_ID, /* VID register offset from base */
+ INDEX_GREG_IPI_VECTOR_PRI_0, /* IPI Vector/Priority Registers */
+ INDEX_GREG_IPI_STRIDE, /* IPI Vector/Priority Registers spacing */
+ INDEX_GREG_SPURIOUS, /* Spurious Vector Register */
+ INDEX_GREG_TIMER_FREQ, /* Global Timer Frequency Reporting Register */
+
+ INDEX_TIMER_BASE, /* Global Timer Registers base */
+ INDEX_TIMER_STRIDE, /* Global Timer Registers spacing */
+ INDEX_TIMER_CURRENT_CNT, /* Global Timer Current Count Register */
+ INDEX_TIMER_BASE_CNT, /* Global Timer Base Count Register */
+ INDEX_TIMER_VECTOR_PRI, /* Global Timer Vector/Priority Register */
+ INDEX_TIMER_DESTINATION, /* Global Timer Destination Register */
+
+ INDEX_CPU_BASE, /* Offset of cpu base */
+ INDEX_CPU_STRIDE, /* Cpu register spacing*/
+ INDEX_CPU_IPI_DISPATCH_0, /* IPI 0 Dispatch Command Register */
+ INDEX_CPU_IPI_DISPATCH_STRIDE, /* IPI Dispatch spacing */
+ INDEX_CPU_CURRENT_TASK_PRI,/* Processor Current Task Priority Register */
+ INDEX_CPU_WHOAMI, /* Who Am I Register */
+ INDEX_CPU_INTACK, /* Interrupt Acknowledge Register */
+ INDEX_CPU_EOI, /* End of Interrupt Register */
+
+ INDEX_IRQ_BASE, /* Interrupt registers base */
+ INDEX_IRQ_STRIDE, /* Interrupt registers spacing */
+ INDEX_IRQ_VECTOR_PRI, /* Interrupt Vector/Priority Register */
+ INDEX_VECPRI_VECTOR_MASK, /* Interrupt Vector Mask */
+ INDEX_VECPRI_POLARITY_POSITIVE, /* Interrupt Positive Polarity bit */
+ INDEX_VECPRI_POLARITY_NEGATIVE, /* Interrupt Negative Polarity bit */
+ INDEX_VECPRI_SENSE_LEVEL, /* Interrupt Level Sense bit */
+ INDEX_VECPRI_SENSE_EDGE, /* Interrupt edge Sense bit */
+ INDEX_VECPRI_POLARITY_MASK, /* Interrupt Polarity mask */
+ INDEX_VECPRI_SENSE_MASK, /* Interrupt sense mask */
+ INDEX_IRQ_DESTINATION, /* Interrupt Destination Register */
+ INDEX_MPIC_WEIRD_END /* Size of the hw info array */
+};
+#endif
+
#ifdef CONFIG_MPIC_BROKEN_U3
/* Fixup table entry */
struct mpic_irq_fixup
@@ -170,6 +269,11 @@ #endif
volatile u32 __iomem *tmregs;
volatile u32 __iomem *cpuregs[MPIC_MAX_CPUS];
volatile u32 __iomem *isus[MPIC_MAX_ISU];
+
+#ifdef CONFIG_MPIC_WEIRD
+ /* Pointer to HW info array */
+ u32 *hw_set;
+#endif
/* link */
struct mpic *next;
@@ -189,6 +293,17 @@ #define MPIC_BROKEN_IPI 0x00000008
/* MPIC wants a reset */
#define MPIC_WANTS_RESET 0x00000010
+#ifdef CONFIG_MPIC_WEIRD
+/* Spurious vector requires EOI */
+#define MPIC_SPV_EOI 0x00000020
+/* MPIC HW modification ID */
+#define MPIC_MOD_ID_MASK 0x00000f00
+#define MPIC_MOD_ID(val) (((val) << 8) & MPIC_MOD_ID_MASK)
+#define MPIC_GET_MOD_ID(flags) (((flags) & MPIC_MOD_ID_MASK) >> 8)
+#define MPIC_ID_MPIC 0 /* Original MPIC */
+#define MPIC_ID_TSI108 1 /* Tsi108/109 PIC */
+#endif
+
/* Allocate the controller structure and setup the linux irq descs
* for the range if interrupts passed in. No HW initialization is
* actually performed.
--
1.4.0
^ permalink raw reply related
* RE: atomic operations in user space
From: Li Yang-r58472 @ 2006-08-24 10:39 UTC (permalink / raw)
To: Terry Liang, linuxppc-embedded
In-Reply-To: <82557754AC6C0448A2218FD1C7D50E2AC6FE9F@hq-exch-1.corp.brocade.com>
Why do you need atomic operations in user land? IPC will be sufficient
to deal with race conditions between processes.=20
Best Regards,
Leo
> -----Original Message-----
> From: linuxppc-embedded-bounces+leoli=3Dfreescale.com@ozlabs.org
> [mailto:linuxppc-embedded-bounces+leoli=3Dfreescale.com@ozlabs.org] On
Behalf Of
> Terry Liang
> Sent: Thursday, August 24, 2006 3:04 AM
> To: linuxppc-embedded@ozlabs.org
> Subject: atomic operations in user space
>=20
> Thanks. Arnd. My main concern is whether the operations are really
atomic as they
> are in the kernel space. I have read some discussion in another forum
that on other
> platforms, even if you are able to compile the atomic_add(),
atomic_set(), etc.
> from an user space application, they don't guarantee to be atomic.
Thanks.
>=20
> Regards,
>=20
> Terry Liang
^ permalink raw reply
* RE: I2C driver for SAA7121 on MPC855 and linux-2.4.25
From: Li Yang-r58472 @ 2006-08-24 10:49 UTC (permalink / raw)
To: Xu, Li (GE, Research), linuxppc-embedded
In-Reply-To: <84681EC46E2C6347953892915BA5DAB1038FE72F@SHAMLVEM01.e2k.ad.ge.com>
> -----Original Message-----
> From: linuxppc-embedded-bounces+leoli=3Dfreescale.com@ozlabs.org
> [mailto:linuxppc-embedded-bounces+leoli=3Dfreescale.com@ozlabs.org] On
Behalf Of
> Xu, Li (GE, Research)
> Sent: Thursday, August 24, 2006 4:02 PM
> To: linuxppc-embedded@ozlabs.org
> Subject: I2C driver for SAA7121 on MPC855 and linux-2.4.25
>=20
> Hi,
>=20
> I am trying to setup i2c driver for saa7121 on my mpc855 based board
> normally the address for saa7121 is 0x88, but when I enable i2c bus
> scan, the driver detect it's address is 0x34, so I just stick to 0x34.
Is it the only device on i2c bus?=20
>=20
> Anyway, I can write to saa7121via i2c bus successfully, but I can't
enable
> color bar, so I don't know whether the driver is working properly or
not?
Are you sure you are operating on the correct device? What operation
can you do successfully on the device? Can you read from the i2c bus?
>=20
> BTW, I setup I2C driver for SAA7113 and it works fine.
>=20
> Tim
^ permalink raw reply
* Re: [PATCH ] powerpc: Add tsi108/9 and non standard mpic support
From: Benjamin Herrenschmidt @ 2006-08-24 10:54 UTC (permalink / raw)
To: Zang Roy-r61911; +Cc: linuxppc-dev list, Paul Mackerras, Yang Xin-Xin-r48390
In-Reply-To: <1156413135.6591.14.camel@localhost.localdomain>
> > The table should still contain the entries for a normal MPIC. One can
> > build a kernel that will boot both machines with the "weird" one and
> > with the normal one. Thus CONFIG_MPIC_WEIRD shall not exclude normal
> > MPICs, though not having it does exclude weird ones. I thus would
> > suggest to keep the table as it was in your earlier patches, that is
> > with the normal MPIC mapping at 0.
> >
> > I intend to re-use that to handle another weird MPIC from some other
> > project :)
>
> That is also my target. I hope the imported mpic_info table can support
> more non-standard mpic structure.
> The following patch adds the standard MPIC entry to the table.
> I post it here.
Looks good. I still need to test it, hopefully tomorrow, then it can go
in though I'm not sure it can get into 2.6.18, we'll see.
Ben.
^ permalink raw reply
* Re: [PATCH ] powerpc: Add tsi108/9 and non standard mpic support
From: Zang Roy-r61911 @ 2006-08-24 11:04 UTC (permalink / raw)
To: Benjamin Herrenschmidt
Cc: linuxppc-dev list, Paul Mackerras, Yang Xin-Xin-r48390
In-Reply-To: <1156416857.8433.244.camel@localhost.localdomain>
On Thu, 2006-08-24 at 18:54, Benjamin Herrenschmidt wrote:
> > > The table should still contain the entries for a normal MPIC. One
> can
> > > build a kernel that will boot both machines with the "weird" one
> and
> > > with the normal one. Thus CONFIG_MPIC_WEIRD shall not exclude
> normal
> > > MPICs, though not having it does exclude weird ones. I thus would
> > > suggest to keep the table as it was in your earlier patches, that
> is
> > > with the normal MPIC mapping at 0.
> > >
> > > I intend to re-use that to handle another weird MPIC from some
> other
> > > project :)
> >
> > That is also my target. I hope the imported mpic_info table can
> support
> > more non-standard mpic structure.
> > The following patch adds the standard MPIC entry to the table.
> > I post it here.
>
> Looks good. I still need to test it, hopefully tomorrow, then it can
> go
> in though I'm not sure it can get into 2.6.18, we'll see.
>
I have tested on mpc8641hpcn board with CONFIG_MPIC.
Hope to see it in 2.6.18.
Roy
^ permalink raw reply
* ARCH=ppc or ARCH=powerpc
From: Benjamin Delagoutte @ 2006-08-24 10:28 UTC (permalink / raw)
To: linuxppc-embedded
Hello,
I'm new to Linux PowerPC platform, and I'm wondering what ARCH we should
use to build the kernel. There seems to be 'ppc' and 'powerpc'. What's
the difference between the two ?
Thank you !
Benjamin
^ permalink raw reply
* Re: [PATCH ] powerpc: Add tsi108/9 and non standard mpic support
From: Benjamin Herrenschmidt @ 2006-08-24 11:13 UTC (permalink / raw)
To: Zang Roy-r61911; +Cc: linuxppc-dev list, Paul Mackerras, Yang Xin-Xin-r48390
In-Reply-To: <1156417448.7107.1.camel@localhost.localdomain>
> I have tested on mpc8641hpcn board with CONFIG_MPIC.
I need to test it with normal MPIC machines and CONFIG_MPIC_WEIRD
enabled
> Hope to see it in 2.6.18.
This is not my call unfortunately though I reckon that it could go in
since it's been sitting around for a while. We'll see.
Ben.
^ permalink raw reply
* Re: ARCH=ppc or ARCH=powerpc
From: Parav Pandit @ 2006-08-24 12:38 UTC (permalink / raw)
To: BDE, linuxppc-embedded
In-Reply-To: <1156415289.19482.7.camel@localhost>
[-- Attachment #1: Type: text/plain, Size: 695 bytes --]
ppc = 32bit.
powerpc= 64bit.
Correct me if I am wrong.
I am not sure why community didn't adopt the name ppc and ppc64 just like ia-32 and ia64.
Parav
Benjamin Delagoutte <BDE@teamlog.com> wrote:
Hello,
I'm new to Linux PowerPC platform, and I'm wondering what ARCH we should
use to build the kernel. There seems to be 'ppc' and 'powerpc'. What's
the difference between the two ?
Thank you !
Benjamin
_______________________________________________
Linuxppc-embedded mailing list
Linuxppc-embedded@ozlabs.org
https://ozlabs.org/mailman/listinfo/linuxppc-embedded
---------------------------------
Do you Yahoo!?
Everyone is raving about the all-new Yahoo! Mail.
[-- Attachment #2: Type: text/html, Size: 1049 bytes --]
^ permalink raw reply
* Re: ARCH=ppc or ARCH=powerpc
From: Josh Boyer @ 2006-08-24 12:49 UTC (permalink / raw)
To: Parav Pandit; +Cc: BDE, linuxppc-embedded
In-Reply-To: <20060824123841.4756.qmail@web36601.mail.mud.yahoo.com>
On Thu, 2006-08-24 at 05:38 -0700, Parav Pandit wrote:
> ppc = 32bit.
> powerpc= 64bit.
> Correct me if I am wrong.
Yes, you're wrong. Some 32 bit boards are also under arch/powerpc now.
>
> I am not sure why community didn't adopt the name ppc and ppc64 just
> like ia-32 and ia64.
They did originally.
The new direction is to have everything under arch/powerpc, both 32 and
64 bit. The reason arch/ppc still exists is because some 32 bit
platforms have not been fully migrated to the requirements to be merged
into arch/powerpc. Namely, the code has to boot from an OpenFirmware
like flattened device tree. The PPC 4xx family of processors, as an
example, does not do this yet though there is work going on to adapt it.
Eventually, arch/ppc will go away and all of PowerPC will be under
arch/powerpc. That's the goal anyway.
josh
^ permalink raw reply
* MPC8555 PCI interrupts are not coming
From: Parav Pandit @ 2006-08-24 12:52 UTC (permalink / raw)
To: linuxppc-embedded
[-- Attachment #1: Type: text/plain, Size: 1024 bytes --]
Hi,
Can someone give light on PCI interrupts routing to the OS from the openPIC?
Basically I am able to talk to PCI end device connected on MPC8555 board in 2.6.13 but not getting interrupts reported by my device.
When I read the INTERRUPT_LINE byte, it comes as 0. pdev->irq is also reporting 0.
Due to that request_irq() fails. But now I request for IRQ line 8 + openPIC offset.
Handler gets registered but still not getting the interrupts. (PCI interrupt line is 8,9 in case of MPC8555).
Can anyone please guide me, what are the different things need be configure in the platform code to receive the PCI interrupts in the driver?
I don't understand the pci_irq_table, and what it should represent?
Currrently no one is writing the INTERRUPT LINE value in the config space.
In which function I should configure that value? pcibios_fixup??
Regards,
Parav Pandit
---------------------------------
Do you Yahoo!?
Get on board. You're invited to try the new Yahoo! Mail.
[-- Attachment #2: Type: text/html, Size: 1338 bytes --]
^ permalink raw reply
* Re: ARCH=ppc or ARCH=powerpc
From: Benjamin Delagoutte @ 2006-08-24 12:58 UTC (permalink / raw)
To: Josh Boyer; +Cc: linuxppc-embedded
In-Reply-To: <1156423796.5640.23.camel@zod.rchland.ibm.com>
Le jeudi 24 août 2006 à 07:49 -0500, Josh Boyer a écrit :
> On Thu, 2006-08-24 at 05:38 -0700, Parav Pandit wrote:
> > ppc = 32bit.
> > powerpc= 64bit.
> > Correct me if I am wrong.
>
> Yes, you're wrong. Some 32 bit boards are also under arch/powerpc now.
>
> >
> > I am not sure why community didn't adopt the name ppc and ppc64 just
> > like ia-32 and ia64.
>
> They did originally.
>
> The new direction is to have everything under arch/powerpc, both 32 and
> 64 bit. The reason arch/ppc still exists is because some 32 bit
> platforms have not been fully migrated to the requirements to be merged
> into arch/powerpc. Namely, the code has to boot from an OpenFirmware
> like flattened device tree. The PPC 4xx family of processors, as an
> example, does not do this yet though there is work going on to adapt it.
I'm currently working on a PPC 405 based developement card. Does it mean
I have to work using the arch/ppc tree ?
What about the includes ? Do I have to use only include/asm-ppc or are
include/asm-powerpc necessary as well ?
> Eventually, arch/ppc will go away and all of PowerPC will be under
> arch/powerpc. That's the goal anyway.
>
> josh
> _______________________________________________
> Linuxppc-embedded mailing list
> Linuxppc-embedded@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-embedded
^ permalink raw reply
* Re: ARCH=ppc or ARCH=powerpc
From: Parav Pandit @ 2006-08-24 12:58 UTC (permalink / raw)
To: Josh Boyer; +Cc: BDE, linuxppc-embedded
In-Reply-To: <1156423796.5640.23.camel@zod.rchland.ibm.com>
[-- Attachment #1: Type: text/plain, Size: 1115 bytes --]
Thanks for correcting my understanding.
We would also move our code to powerpc from ppc next release onwards.
Parav
Josh Boyer <jdub@us.ibm.com> wrote:
On Thu, 2006-08-24 at 05:38 -0700, Parav Pandit wrote:
> ppc = 32bit.
> powerpc= 64bit.
> Correct me if I am wrong.
Yes, you're wrong. Some 32 bit boards are also under arch/powerpc now.
>
> I am not sure why community didn't adopt the name ppc and ppc64 just
> like ia-32 and ia64.
They did originally.
The new direction is to have everything under arch/powerpc, both 32 and
64 bit. The reason arch/ppc still exists is because some 32 bit
platforms have not been fully migrated to the requirements to be merged
into arch/powerpc. Namely, the code has to boot from an OpenFirmware
like flattened device tree. The PPC 4xx family of processors, as an
example, does not do this yet though there is work going on to adapt it.
Eventually, arch/ppc will go away and all of PowerPC will be under
arch/powerpc. That's the goal anyway.
josh
---------------------------------
Stay in the know. Pulse on the new Yahoo.com. Check it out.
[-- Attachment #2: Type: text/html, Size: 1498 bytes --]
^ permalink raw reply
* Re: ARCH=ppc or ARCH=powerpc
From: Josh Boyer @ 2006-08-24 13:07 UTC (permalink / raw)
To: BDE; +Cc: linuxppc-embedded
In-Reply-To: <1156424295.19482.11.camel@localhost>
On Thu, 2006-08-24 at 14:58 +0200, Benjamin Delagoutte wrote:
>
> I'm currently working on a PPC 405 based developement card. Does it mean
> I have to work using the arch/ppc tree ?
For now, yes. Set ARCH=ppc when you compile the kernel.
> What about the includes ? Do I have to use only include/asm-ppc or are
> include/asm-powerpc necessary as well ?
I believe there are some hacks in the makefiles to pull common asm files
from include/asm-powerpc when needed. Basically, you should be able to
just do:
#include <asm/foo.h>
and it should work. If you're adding new .h files, I suppose asm-ppc is
the place to add them for now. That's just my opinion though :)
josh
^ permalink raw reply
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox