* Re: status of mpc52xx with arch=powerpc?
From: John Rigby @ 2006-10-26 20:07 UTC (permalink / raw)
To: Grant Likely; +Cc: linuxppc-embedded
In-Reply-To: <528646bc0610242325m45fa610egb47f118f5f4f6f5e@mail.gmail.com>
Does Bestcomm dma belong in here somewhere?
On 10/25/06, Grant Likely <grant.likely@secretlab.ca> wrote:
> On 10/24/06, Benjamin Herrenschmidt <benh@kernel.crashing.org> wrote:
> > Can you send me your .dts ?
>
> Here you go; for discussion purposes only! :)
>
> This is pretty rough stuff, and it haven't even got to the point of
> using it to boot a kernel. But if it's a starting point to figure out
> what the 52xx device tree should look like then go to it!
>
> g.
>
>
> --
> Grant Likely, B.Sc. P.Eng.
> Secret Lab Technologies Ltd.
> grant.likely@secretlab.ca
> (403) 399-0195
>
>
> _______________________________________________
> Linuxppc-embedded mailing list
> Linuxppc-embedded@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-embedded
>
>
>
^ permalink raw reply
* Re: [PATCH] General CHRP/MPC5K2 platform support patch
From: Grant Likely @ 2006-10-26 20:00 UTC (permalink / raw)
To: Nicolas DET; +Cc: akpm, sl, linuxppc-dev, linuxppc-embedded, sha
In-Reply-To: <4541118F.60002@bplan-gmbh.de>
My comments are satisfied
Acked-by: Grant Likely <grant.likely@secretlab.ca>
On 10/26/06, Nicolas DET <nd@bplan-gmbh.de> wrote:
> Grant Likely wrote:
>
> >> +
> >> +struct device_node *find_mpc52xx_pic(void)
> >> +{
> >> + struct device_node *dev;
> >> + const char *piccompatible_list[] =
> >> + {
> >> + "mpc5200-interrupt-controller",
> >> + "mpc52xx-interrupt-controller",
> >> + "mpc52xx-pic",
> >> + "mpc5200-pic",
> >> + "5200-interrupt-controller",
> >> + "52xx-interrupt-controller",
> >> + "52xx-pic",
> >> + "5200-pic",
> >> + NULL
> >> + };
> >
> > Considering Efika is the *only* CHRP 52xx board out there at the
> > moment, and only a handful of embedded folks trying to move it to
> > arch/powerpc, surely we can come to an agreement now on what this
> > thing is named. :)
> >
> >
>
> Done
>
>
>
>
> --- a/arch/powerpc/sysdev/Makefile 2006-10-25 19:07:24.000000000 +0200
> +++ b/arch/powerpc/sysdev/Makefile 2006-10-26 11:38:02.000000000 +0200
> @@ -13,6 +13,7 @@ obj-$(CONFIG_FSL_SOC) += fsl_soc.o
> obj-$(CONFIG_PPC_TODC) += todc.o
> obj-$(CONFIG_TSI108_BRIDGE) += tsi108_pci.o tsi108_dev.o
> obj-$(CONFIG_QUICC_ENGINE) += qe_lib/
> +obj-$(CONFIG_PPC_MPC52xx_PIC) += mpc52xx_pic.o
>
> ifeq ($(CONFIG_PPC_MERGE),y)
> obj-$(CONFIG_PPC_I8259) += i8259.o
> --- a/arch/powerpc/sysdev/mpc52xx_pic.c 1970-01-01 01:00:00.000000000 +0100
> +++ b/arch/powerpc/sysdev/mpc52xx_pic.c 2006-10-26 21:32:05.000000000 +0200
> @@ -0,0 +1,363 @@
> +/*
> + * arch/powerpc/sysdev/mpc52xx_pic.c
> + *
> + * Programmable Interrupt Controller functions for the Freescale MPC52xx
> + * embedded CPU.
> + * Modified for CHRP Efika 5K2
> + *
> + * Maintainer : Sylvain Munaut <tnt@246tNt.com>
> + *
> + * Based on (well, mostly copied from) the code from the 2.4 kernel by
> + * Dale Farnsworth <dfarnsworth@mvista.com> and Kent Borg.
> + *
> + * Copyright (C) 2004 Sylvain Munaut <tnt@246tNt.com>
> + * Copyright (C) 2003 Montavista Software, Inc
> + *
> + * This file is licensed under the terms of the GNU General Public License
> + * version 2. This program is licensed "as is" without any warranty of any
> + * kind, whether express or implied.
> + */
> +
> +#include <linux/stddef.h>
> +#include <linux/init.h>
> +#include <linux/sched.h>
> +#include <linux/signal.h>
> +#include <linux/stddef.h>
> +#include <linux/delay.h>
> +#include <linux/irq.h>
> +
> +#include <asm/io.h>
> +#include <asm/processor.h>
> +#include <asm/system.h>
> +#include <asm/irq.h>
> +#include <asm/prom.h>
> +
> +#include <asm/mpc52xx.h>
> +
> +static struct mpc52xx_intr __iomem *intr;
> +static struct mpc52xx_sdma __iomem *sdma;
> +
> +static struct irq_host *mpc52xx_irqhost = NULL;
> +
> +static void mpc52xx_ic_disable(unsigned int virq)
> +{
> + u32 val;
> + int irq;
> +
> + irq = irq_map[virq].hwirq;
> +
> + pr_debug("%s: irq=%d\n", __func__, irq);
> +
> + if (irq == MPC52xx_IRQ0) {
> + val = in_be32(&intr->ctrl);
> + val &= ~(1 << 11);
> + out_be32(&intr->ctrl, val);
> + } else if (irq < MPC52xx_IRQ1) {
> + BUG();
> + } else if (irq <= MPC52xx_IRQ3) {
> + val = in_be32(&intr->ctrl);
> + val &= ~(1 << (10 - (irq - MPC52xx_IRQ1)));
> + out_be32(&intr->ctrl, val);
> + } else if (irq < MPC52xx_SDMA_IRQ_BASE) {
> + val = in_be32(&intr->main_mask);
> + val |= 1 << (16 - (irq - MPC52xx_MAIN_IRQ_BASE));
> + out_be32(&intr->main_mask, val);
> + } else if (irq < MPC52xx_PERP_IRQ_BASE) {
> + val = in_be32(&sdma->IntMask);
> + val |= 1 << (irq - MPC52xx_SDMA_IRQ_BASE);
> + out_be32(&sdma->IntMask, val);
> + } else {
> + val = in_be32(&intr->per_mask);
> + val |= 1 << (31 - (irq - MPC52xx_PERP_IRQ_BASE));
> + out_be32(&intr->per_mask, val);
> + }
> +}
> +
> +static void mpc52xx_ic_enable(unsigned int virq)
> +{
> + u32 val;
> + int irq;
> +
> + irq = irq_map[virq].hwirq;
> +
> + pr_debug("%s: irq=%d\n", __func__, irq);
> +
> + if (irq == MPC52xx_IRQ0) {
> + val = in_be32(&intr->ctrl);
> + val |= 1 << 11;
> + out_be32(&intr->ctrl, val);
> + } else if (irq < MPC52xx_IRQ1) {
> + BUG();
> + } else if (irq <= MPC52xx_IRQ3) {
> + val = in_be32(&intr->ctrl);
> + val |= 1 << (10 - (irq - MPC52xx_IRQ1));
> + out_be32(&intr->ctrl, val);
> + } else if (irq < MPC52xx_SDMA_IRQ_BASE) {
> + val = in_be32(&intr->main_mask);
> + val &= ~(1 << (16 - (irq - MPC52xx_MAIN_IRQ_BASE)));
> + out_be32(&intr->main_mask, val);
> + } else if (irq < MPC52xx_PERP_IRQ_BASE) {
> + val = in_be32(&sdma->IntMask);
> + val &= ~(1 << (irq - MPC52xx_SDMA_IRQ_BASE));
> + out_be32(&sdma->IntMask, val);
> + } else {
> + val = in_be32(&intr->per_mask);
> + val &= ~(1 << (31 - (irq - MPC52xx_PERP_IRQ_BASE)));
> + out_be32(&intr->per_mask, val);
> + }
> +}
> +
> +static void mpc52xx_ic_ack(unsigned int virq)
> +{
> + u32 val;
> + int irq;
> +
> + irq = irq_map[virq].hwirq;
> +
> + pr_debug("%s: irq=%d\n", __func__, irq);
> +
> + /*
> + * Only some irqs are reset here, others in interrupting hardware.
> + */
> +
> + switch (irq) {
> + case MPC52xx_IRQ0:
> + val = in_be32(&intr->ctrl);
> + val |= 0x08000000;
> + out_be32(&intr->ctrl, val);
> + break;
> + case MPC52xx_CCS_IRQ:
> + val = in_be32(&intr->enc_status);
> + val |= 0x00000400;
> + out_be32(&intr->enc_status, val);
> + break;
> + case MPC52xx_IRQ1:
> + val = in_be32(&intr->ctrl);
> + val |= 0x04000000;
> + out_be32(&intr->ctrl, val);
> + break;
> + case MPC52xx_IRQ2:
> + val = in_be32(&intr->ctrl);
> + val |= 0x02000000;
> + out_be32(&intr->ctrl, val);
> + break;
> + case MPC52xx_IRQ3:
> + val = in_be32(&intr->ctrl);
> + val |= 0x01000000;
> + out_be32(&intr->ctrl, val);
> + break;
> + default:
> + if (irq >= MPC52xx_SDMA_IRQ_BASE
> + && irq < (MPC52xx_SDMA_IRQ_BASE + MPC52xx_SDMA_IRQ_NUM)) {
> + out_be32(&sdma->IntPend,
> + 1 << (irq - MPC52xx_SDMA_IRQ_BASE));
> + }
> +
> + break;
> + }
> +
> +}
> +
> +static void mpc52xx_ic_disable_and_ack(unsigned int irq)
> +{
> + mpc52xx_ic_disable(irq);
> + mpc52xx_ic_ack(irq);
> +}
> +
> +static void mpc52xx_ic_end(unsigned int irq)
> +{
> + if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
> + mpc52xx_ic_enable(irq);
> +}
> +
> +static struct irq_chip mpc52xx_irqchip = {
> + .name = " MPC52xx ",
> + .enable = mpc52xx_ic_enable,
> + .disable = mpc52xx_ic_disable,
> + .ack = mpc52xx_ic_disable_and_ack,
> + .end = mpc52xx_ic_end,
> +};
> +
> +extern struct device_node *find_mpc52xx_pic(void);
> +static int mpc52xx_irqhost_match(struct irq_host *h, struct device_node *node)
> +{
> + pr_debug("%s: %p vs %p\n", __func__, find_mpc52xx_pic(), node);
> + return find_mpc52xx_pic() == node;
> +}
> +
> +static int mpc52xx_irqhost_xlate(struct irq_host *h, struct device_node *ct,
> + u32 * intspec, unsigned int intsize,
> + irq_hw_number_t * out_hwirq,
> + unsigned int *out_flags)
> +{
> + static unsigned char map_senses[4] = {
> + IRQ_TYPE_LEVEL_HIGH,
> + IRQ_TYPE_EDGE_FALLING,
> + IRQ_TYPE_EDGE_RISING,
> + IRQ_TYPE_LEVEL_LOW,
> + };
> +
> + int intrvect_l1;
> + int intrvect_l2;
> + int intrvect_type;
> + int intrvect_linux;
> +
> + pr_debug("%s:\n", __func__);
> +
> + if (intsize != 3)
> + return -1;
> +
> + intrvect_l1 = (int)intspec[0];
> + intrvect_l2 = (int)intspec[1];
> + intrvect_type = (int)intspec[2];
> +
> + pr_debug("l1=%d, l2=%d, type=%d\n", intrvect_l1, intrvect_l2,
> + intrvect_type);
> +
> + switch (intrvect_l1) {
> + case 0: /* Critical */
> + intrvect_linux = MPC52xx_CRIT_IRQ_BASE;
> + break;
> +
> + case 1: /* Main */
> + intrvect_linux = MPC52xx_MAIN_IRQ_BASE;
> + break;
> +
> + case 2: /* Periph */
> + intrvect_linux = MPC52xx_PERP_IRQ_BASE;
> + break;
> +
> + case 3: /* Bestcomm */
> + intrvect_linux = MPC52xx_SDMA_IRQ_BASE;
> + break;
> +
> + default:
> + if (printk_ratelimit())
> + printk(KERN_ERR "Wrong L1 interrupt vector (%d)\n",
> + intrvect_l1);
> +
> + return -1;
> + }
> +
> + intrvect_linux += intrvect_l2;
> +
> + pr_debug("return %d\n", intrvect_linux);
> +
> + *out_hwirq = intrvect_linux;
> + *out_flags = map_senses[intrvect_type];
> +
> + return 0;
> +
> +}
> +
> +int mpc52xx_irqhost_map(struct irq_host *h, unsigned int virq,
> + irq_hw_number_t hw)
> +{
> + pr_debug("%s: v=%d, hw=%d\n", __func__, virq, (int)hw);
> +
> + return 0;
> +}
> +
> +void mpc52xx_irqhost_unmap(struct irq_host *h, unsigned int virq)
> +{
> + pr_debug("%s: v=%d\n", __func__, virq);
> +}
> +
> +static struct irq_host_ops mpc52xx_irqhost_ops = {
> + .match = mpc52xx_irqhost_match,
> + .xlate = mpc52xx_irqhost_xlate,
> + .map = mpc52xx_irqhost_map,
> + .unmap = mpc52xx_irqhost_unmap,
> +};
> +
> +void __init mpc52xx_init_irq(void)
> +{
> + int i;
> + u32 intr_ctrl;
> +
> + /* Remap the necessary zones */
> + intr = ioremap(MPC52xx_PA(MPC52xx_INTR_OFFSET), MPC52xx_INTR_SIZE);
> + sdma = ioremap(MPC52xx_PA(MPC52xx_SDMA_OFFSET), MPC52xx_SDMA_SIZE);
> +
> + if ((intr == NULL) || (sdma == NULL))
> + panic("Can't ioremap PIC/SDMA register or init_irq !");
> +
> + /* Disable all interrupt sources. */
> + out_be32(&sdma->IntPend, 0xffffffff); /* 1 means clear pending */
> + out_be32(&sdma->IntMask, 0xffffffff); /* 1 means disabled */
> + out_be32(&intr->per_mask, 0x7ffffc00); /* 1 means disabled */
> + out_be32(&intr->main_mask, 0x00010fff); /* 1 means disabled */
> + intr_ctrl = in_be32(&intr->ctrl);
> + intr_ctrl &= 0x00ff0000; /* Keeps IRQ[0-3] config */
> + intr_ctrl |= 0x0f000000 | /* clear IRQ 0-3 */
> + 0x00001000 | /* MEE master external enable */
> + 0x00000000 | /* 0 means disable IRQ 0-3 */
> + 0x00000001; /* CEb route critical normally */
> + out_be32(&intr->ctrl, intr_ctrl);
> +
> + /* Zero a bunch of the priority settings. */
> + out_be32(&intr->per_pri1, 0);
> + out_be32(&intr->per_pri2, 0);
> + out_be32(&intr->per_pri3, 0);
> + out_be32(&intr->main_pri1, 0);
> + out_be32(&intr->main_pri2, 0);
> + /* Initialize irq_desc[i].handler's with mpc52xx_ic. */
> + for (i = 0; i < NR_IRQS; i++) {
> + irq_desc[i].chip = &mpc52xx_irqchip;
> + irq_desc[i].status = IRQ_LEVEL;
> +
> + }
> +
> +#define IRQn_MODE(intr_ctrl,irq) (((intr_ctrl) >> (22-(i<<1))) & 0x03)
> + for (i = 0; i < 4; i++) {
> + int mode;
> + mode = IRQn_MODE(intr_ctrl, i);
> + if ((mode == 0x1) || (mode == 0x2))
> + irq_desc[i ? MPC52xx_IRQ1 + i -
> + 1 : MPC52xx_IRQ0].status = 0;
> + }
> +
> + /*
> + * As last step, add an irq host to translate the real
> + * hw irq information provided by the ofw to linux virq
> + */
> +
> + mpc52xx_irqhost =
> + irq_alloc_host(IRQ_HOST_MAP_LINEAR, NR_IRQS, &mpc52xx_irqhost_ops,
> + -1);
> + pr_debug("%s: mpc52xx_irqhost =%p\n", __func__, mpc52xx_irqhost);
> +}
> +
> +unsigned int mpc52xx_get_irq(void)
> +{
> + u32 status;
> + int virq;
> + int irq = NO_IRQ_IGNORE;
> +
> + status = in_be32(&intr->enc_status);
> + if (status & 0x00000400) { /* critical */
> + irq = (status >> 8) & 0x3;
> + if (irq == 2) /* high priority peripheral */
> + goto peripheral;
> + irq += MPC52xx_CRIT_IRQ_BASE;
> + } else if (status & 0x00200000) { /* main */
> + irq = (status >> 16) & 0x1f;
> + if (irq == 4) /* low priority peripheral */
> + goto peripheral;
> + irq += MPC52xx_MAIN_IRQ_BASE;
> + } else if (status & 0x20000000) { /* peripheral */
> + peripheral:
> + irq = (status >> 24) & 0x1f;
> + if (irq == 0) { /* bestcomm */
> + status = in_be32(&sdma->IntPend);
> + irq = ffs(status) + MPC52xx_SDMA_IRQ_BASE - 1;
> + } else
> + irq += MPC52xx_PERP_IRQ_BASE;
> +
> + }
> +
> + virq = irq_linear_revmap(mpc52xx_irqhost, irq);
> + pr_debug("%s: irq=%d -> %d\n", __func__, irq, virq);
> +
> + return virq;
> +}
> --- a/arch/powerpc/Kconfig 2006-10-25 19:07:23.000000000 +0200
> +++ b/arch/powerpc/Kconfig 2006-10-26 18:55:58.000000000 +0200
> @@ -384,6 +384,11 @@ config PPC_CHRP
> select PPC_RTAS
> select PPC_MPC106
> select PPC_UDBG_16550
> + select PPC_MPC52xx_PIC
> + default y
> +
> +config PPC_MPC52xx_PIC
> + bool
> default y
>
> config PPC_PMAC
> --- a/arch/powerpc/platforms/chrp/setup.c 2006-10-25 19:07:23.000000000 +0200
> +++ b/arch/powerpc/platforms/chrp/setup.c 2006-10-26 21:47:29.000000000 +0200
> @@ -51,6 +51,7 @@
> #include <asm/mpic.h>
> #include <asm/rtas.h>
> #include <asm/xmon.h>
> +#include <asm/mpc52xx.h>
>
> #include "chrp.h"
>
> @@ -435,6 +436,44 @@ static struct irqaction xmon_irqaction =
> };
> #endif
>
> +
> +struct device_node *find_mpc52xx_pic(void)
> +{
> + struct device_node *dev;
> + const char *piccompatible_list[] =
> + {
> + "mpc5200-pic",
> + NULL
> + };
> +
> + /* Look for an MPC52xx interrupt controller */
> + for_each_node_by_type(dev, "interrupt-controller")
> + {
> + const char **piccompatible_entry = piccompatible_list;
> +
> + for(piccompatible_entry = piccompatible_list; *piccompatible_entry; piccompatible_entry++ )
> + {
> + if (device_is_compatible(dev, *piccompatible_entry ))
> + return dev;
> + }
> + }
> +
> + return NULL;
> +}
> +
> +static int __init chrp_find_mpc52xx_pic(void)
> +{
> + if (find_mpc52xx_pic())
> + {
> + printk(KERN_INFO "Found MPC52xx Interrupt Controller\n");
> + ppc_md.get_irq = mpc52xx_get_irq;
> + mpc52xx_init_irq();
> + return 0;
> + }
> +
> + return -ENODEV;
> +}
> +
> static void __init chrp_find_8259(void)
> {
> struct device_node *np, *pic = NULL;
> @@ -473,8 +512,11 @@ static void __init chrp_find_8259(void)
> break;
> }
> if (np == NULL)
> - printk(KERN_WARNING "Cannot find PCI interrupt acknowledge"
> - " address, polling\n");
> + {
> + printk(KERN_WARNING "Cannot find PCI/i8259 interrupt acknowledge"
> + " Fix your tree!\n");
> + return;
> + }
>
> i8259_init(pic, chrp_int_ack);
> if (ppc_md.get_irq == NULL)
> @@ -494,6 +536,8 @@ void __init chrp_init_IRQ(void)
> #if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(XMON)
> struct device_node *kbd;
> #endif
> +
> + chrp_find_mpc52xx_pic();
> chrp_find_openpic();
> chrp_find_8259();
>
>
>
>
>
--
Grant Likely, B.Sc. P.Eng.
Secret Lab Technologies Ltd.
grant.likely@secretlab.ca
(403) 399-0195
^ permalink raw reply
* Re: [PATCH] General CHRP/MPC5K2 platform support patch
From: Nicolas DET @ 2006-10-26 19:50 UTC (permalink / raw)
To: Grant Likely; +Cc: akpm, sl, linuxppc-dev, linuxppc-embedded, sha
In-Reply-To: <528646bc0610260902o4d4996a4i3dcf2a9b874037c7@mail.gmail.com>
[-- Attachment #1: Type: text/plain, Size: 781 bytes --]
Grant Likely wrote:
>> +
>> +struct device_node *find_mpc52xx_pic(void)
>> +{
>> + struct device_node *dev;
>> + const char *piccompatible_list[] =
>> + {
>> + "mpc5200-interrupt-controller",
>> + "mpc52xx-interrupt-controller",
>> + "mpc52xx-pic",
>> + "mpc5200-pic",
>> + "5200-interrupt-controller",
>> + "52xx-interrupt-controller",
>> + "52xx-pic",
>> + "5200-pic",
>> + NULL
>> + };
>
> Considering Efika is the *only* CHRP 52xx board out there at the
> moment, and only a handful of embedded folks trying to move it to
> arch/powerpc, surely we can come to an agreement now on what this
> thing is named. :)
>
>
Done
[-- Attachment #2: chrpmpc52xx_2.6.19-rc3.patch --]
[-- Type: text/plain, Size: 12164 bytes --]
--- a/arch/powerpc/sysdev/Makefile 2006-10-25 19:07:24.000000000 +0200
+++ b/arch/powerpc/sysdev/Makefile 2006-10-26 11:38:02.000000000 +0200
@@ -13,6 +13,7 @@ obj-$(CONFIG_FSL_SOC) += fsl_soc.o
obj-$(CONFIG_PPC_TODC) += todc.o
obj-$(CONFIG_TSI108_BRIDGE) += tsi108_pci.o tsi108_dev.o
obj-$(CONFIG_QUICC_ENGINE) += qe_lib/
+obj-$(CONFIG_PPC_MPC52xx_PIC) += mpc52xx_pic.o
ifeq ($(CONFIG_PPC_MERGE),y)
obj-$(CONFIG_PPC_I8259) += i8259.o
--- a/arch/powerpc/sysdev/mpc52xx_pic.c 1970-01-01 01:00:00.000000000 +0100
+++ b/arch/powerpc/sysdev/mpc52xx_pic.c 2006-10-26 21:32:05.000000000 +0200
@@ -0,0 +1,363 @@
+/*
+ * arch/powerpc/sysdev/mpc52xx_pic.c
+ *
+ * Programmable Interrupt Controller functions for the Freescale MPC52xx
+ * embedded CPU.
+ * Modified for CHRP Efika 5K2
+ *
+ * Maintainer : Sylvain Munaut <tnt@246tNt.com>
+ *
+ * Based on (well, mostly copied from) the code from the 2.4 kernel by
+ * Dale Farnsworth <dfarnsworth@mvista.com> and Kent Borg.
+ *
+ * Copyright (C) 2004 Sylvain Munaut <tnt@246tNt.com>
+ * Copyright (C) 2003 Montavista Software, Inc
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <linux/stddef.h>
+#include <linux/init.h>
+#include <linux/sched.h>
+#include <linux/signal.h>
+#include <linux/stddef.h>
+#include <linux/delay.h>
+#include <linux/irq.h>
+
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <asm/system.h>
+#include <asm/irq.h>
+#include <asm/prom.h>
+
+#include <asm/mpc52xx.h>
+
+static struct mpc52xx_intr __iomem *intr;
+static struct mpc52xx_sdma __iomem *sdma;
+
+static struct irq_host *mpc52xx_irqhost = NULL;
+
+static void mpc52xx_ic_disable(unsigned int virq)
+{
+ u32 val;
+ int irq;
+
+ irq = irq_map[virq].hwirq;
+
+ pr_debug("%s: irq=%d\n", __func__, irq);
+
+ if (irq == MPC52xx_IRQ0) {
+ val = in_be32(&intr->ctrl);
+ val &= ~(1 << 11);
+ out_be32(&intr->ctrl, val);
+ } else if (irq < MPC52xx_IRQ1) {
+ BUG();
+ } else if (irq <= MPC52xx_IRQ3) {
+ val = in_be32(&intr->ctrl);
+ val &= ~(1 << (10 - (irq - MPC52xx_IRQ1)));
+ out_be32(&intr->ctrl, val);
+ } else if (irq < MPC52xx_SDMA_IRQ_BASE) {
+ val = in_be32(&intr->main_mask);
+ val |= 1 << (16 - (irq - MPC52xx_MAIN_IRQ_BASE));
+ out_be32(&intr->main_mask, val);
+ } else if (irq < MPC52xx_PERP_IRQ_BASE) {
+ val = in_be32(&sdma->IntMask);
+ val |= 1 << (irq - MPC52xx_SDMA_IRQ_BASE);
+ out_be32(&sdma->IntMask, val);
+ } else {
+ val = in_be32(&intr->per_mask);
+ val |= 1 << (31 - (irq - MPC52xx_PERP_IRQ_BASE));
+ out_be32(&intr->per_mask, val);
+ }
+}
+
+static void mpc52xx_ic_enable(unsigned int virq)
+{
+ u32 val;
+ int irq;
+
+ irq = irq_map[virq].hwirq;
+
+ pr_debug("%s: irq=%d\n", __func__, irq);
+
+ if (irq == MPC52xx_IRQ0) {
+ val = in_be32(&intr->ctrl);
+ val |= 1 << 11;
+ out_be32(&intr->ctrl, val);
+ } else if (irq < MPC52xx_IRQ1) {
+ BUG();
+ } else if (irq <= MPC52xx_IRQ3) {
+ val = in_be32(&intr->ctrl);
+ val |= 1 << (10 - (irq - MPC52xx_IRQ1));
+ out_be32(&intr->ctrl, val);
+ } else if (irq < MPC52xx_SDMA_IRQ_BASE) {
+ val = in_be32(&intr->main_mask);
+ val &= ~(1 << (16 - (irq - MPC52xx_MAIN_IRQ_BASE)));
+ out_be32(&intr->main_mask, val);
+ } else if (irq < MPC52xx_PERP_IRQ_BASE) {
+ val = in_be32(&sdma->IntMask);
+ val &= ~(1 << (irq - MPC52xx_SDMA_IRQ_BASE));
+ out_be32(&sdma->IntMask, val);
+ } else {
+ val = in_be32(&intr->per_mask);
+ val &= ~(1 << (31 - (irq - MPC52xx_PERP_IRQ_BASE)));
+ out_be32(&intr->per_mask, val);
+ }
+}
+
+static void mpc52xx_ic_ack(unsigned int virq)
+{
+ u32 val;
+ int irq;
+
+ irq = irq_map[virq].hwirq;
+
+ pr_debug("%s: irq=%d\n", __func__, irq);
+
+ /*
+ * Only some irqs are reset here, others in interrupting hardware.
+ */
+
+ switch (irq) {
+ case MPC52xx_IRQ0:
+ val = in_be32(&intr->ctrl);
+ val |= 0x08000000;
+ out_be32(&intr->ctrl, val);
+ break;
+ case MPC52xx_CCS_IRQ:
+ val = in_be32(&intr->enc_status);
+ val |= 0x00000400;
+ out_be32(&intr->enc_status, val);
+ break;
+ case MPC52xx_IRQ1:
+ val = in_be32(&intr->ctrl);
+ val |= 0x04000000;
+ out_be32(&intr->ctrl, val);
+ break;
+ case MPC52xx_IRQ2:
+ val = in_be32(&intr->ctrl);
+ val |= 0x02000000;
+ out_be32(&intr->ctrl, val);
+ break;
+ case MPC52xx_IRQ3:
+ val = in_be32(&intr->ctrl);
+ val |= 0x01000000;
+ out_be32(&intr->ctrl, val);
+ break;
+ default:
+ if (irq >= MPC52xx_SDMA_IRQ_BASE
+ && irq < (MPC52xx_SDMA_IRQ_BASE + MPC52xx_SDMA_IRQ_NUM)) {
+ out_be32(&sdma->IntPend,
+ 1 << (irq - MPC52xx_SDMA_IRQ_BASE));
+ }
+
+ break;
+ }
+
+}
+
+static void mpc52xx_ic_disable_and_ack(unsigned int irq)
+{
+ mpc52xx_ic_disable(irq);
+ mpc52xx_ic_ack(irq);
+}
+
+static void mpc52xx_ic_end(unsigned int irq)
+{
+ if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
+ mpc52xx_ic_enable(irq);
+}
+
+static struct irq_chip mpc52xx_irqchip = {
+ .name = " MPC52xx ",
+ .enable = mpc52xx_ic_enable,
+ .disable = mpc52xx_ic_disable,
+ .ack = mpc52xx_ic_disable_and_ack,
+ .end = mpc52xx_ic_end,
+};
+
+extern struct device_node *find_mpc52xx_pic(void);
+static int mpc52xx_irqhost_match(struct irq_host *h, struct device_node *node)
+{
+ pr_debug("%s: %p vs %p\n", __func__, find_mpc52xx_pic(), node);
+ return find_mpc52xx_pic() == node;
+}
+
+static int mpc52xx_irqhost_xlate(struct irq_host *h, struct device_node *ct,
+ u32 * intspec, unsigned int intsize,
+ irq_hw_number_t * out_hwirq,
+ unsigned int *out_flags)
+{
+ static unsigned char map_senses[4] = {
+ IRQ_TYPE_LEVEL_HIGH,
+ IRQ_TYPE_EDGE_FALLING,
+ IRQ_TYPE_EDGE_RISING,
+ IRQ_TYPE_LEVEL_LOW,
+ };
+
+ int intrvect_l1;
+ int intrvect_l2;
+ int intrvect_type;
+ int intrvect_linux;
+
+ pr_debug("%s:\n", __func__);
+
+ if (intsize != 3)
+ return -1;
+
+ intrvect_l1 = (int)intspec[0];
+ intrvect_l2 = (int)intspec[1];
+ intrvect_type = (int)intspec[2];
+
+ pr_debug("l1=%d, l2=%d, type=%d\n", intrvect_l1, intrvect_l2,
+ intrvect_type);
+
+ switch (intrvect_l1) {
+ case 0: /* Critical */
+ intrvect_linux = MPC52xx_CRIT_IRQ_BASE;
+ break;
+
+ case 1: /* Main */
+ intrvect_linux = MPC52xx_MAIN_IRQ_BASE;
+ break;
+
+ case 2: /* Periph */
+ intrvect_linux = MPC52xx_PERP_IRQ_BASE;
+ break;
+
+ case 3: /* Bestcomm */
+ intrvect_linux = MPC52xx_SDMA_IRQ_BASE;
+ break;
+
+ default:
+ if (printk_ratelimit())
+ printk(KERN_ERR "Wrong L1 interrupt vector (%d)\n",
+ intrvect_l1);
+
+ return -1;
+ }
+
+ intrvect_linux += intrvect_l2;
+
+ pr_debug("return %d\n", intrvect_linux);
+
+ *out_hwirq = intrvect_linux;
+ *out_flags = map_senses[intrvect_type];
+
+ return 0;
+
+}
+
+int mpc52xx_irqhost_map(struct irq_host *h, unsigned int virq,
+ irq_hw_number_t hw)
+{
+ pr_debug("%s: v=%d, hw=%d\n", __func__, virq, (int)hw);
+
+ return 0;
+}
+
+void mpc52xx_irqhost_unmap(struct irq_host *h, unsigned int virq)
+{
+ pr_debug("%s: v=%d\n", __func__, virq);
+}
+
+static struct irq_host_ops mpc52xx_irqhost_ops = {
+ .match = mpc52xx_irqhost_match,
+ .xlate = mpc52xx_irqhost_xlate,
+ .map = mpc52xx_irqhost_map,
+ .unmap = mpc52xx_irqhost_unmap,
+};
+
+void __init mpc52xx_init_irq(void)
+{
+ int i;
+ u32 intr_ctrl;
+
+ /* Remap the necessary zones */
+ intr = ioremap(MPC52xx_PA(MPC52xx_INTR_OFFSET), MPC52xx_INTR_SIZE);
+ sdma = ioremap(MPC52xx_PA(MPC52xx_SDMA_OFFSET), MPC52xx_SDMA_SIZE);
+
+ if ((intr == NULL) || (sdma == NULL))
+ panic("Can't ioremap PIC/SDMA register or init_irq !");
+
+ /* Disable all interrupt sources. */
+ out_be32(&sdma->IntPend, 0xffffffff); /* 1 means clear pending */
+ out_be32(&sdma->IntMask, 0xffffffff); /* 1 means disabled */
+ out_be32(&intr->per_mask, 0x7ffffc00); /* 1 means disabled */
+ out_be32(&intr->main_mask, 0x00010fff); /* 1 means disabled */
+ intr_ctrl = in_be32(&intr->ctrl);
+ intr_ctrl &= 0x00ff0000; /* Keeps IRQ[0-3] config */
+ intr_ctrl |= 0x0f000000 | /* clear IRQ 0-3 */
+ 0x00001000 | /* MEE master external enable */
+ 0x00000000 | /* 0 means disable IRQ 0-3 */
+ 0x00000001; /* CEb route critical normally */
+ out_be32(&intr->ctrl, intr_ctrl);
+
+ /* Zero a bunch of the priority settings. */
+ out_be32(&intr->per_pri1, 0);
+ out_be32(&intr->per_pri2, 0);
+ out_be32(&intr->per_pri3, 0);
+ out_be32(&intr->main_pri1, 0);
+ out_be32(&intr->main_pri2, 0);
+ /* Initialize irq_desc[i].handler's with mpc52xx_ic. */
+ for (i = 0; i < NR_IRQS; i++) {
+ irq_desc[i].chip = &mpc52xx_irqchip;
+ irq_desc[i].status = IRQ_LEVEL;
+
+ }
+
+#define IRQn_MODE(intr_ctrl,irq) (((intr_ctrl) >> (22-(i<<1))) & 0x03)
+ for (i = 0; i < 4; i++) {
+ int mode;
+ mode = IRQn_MODE(intr_ctrl, i);
+ if ((mode == 0x1) || (mode == 0x2))
+ irq_desc[i ? MPC52xx_IRQ1 + i -
+ 1 : MPC52xx_IRQ0].status = 0;
+ }
+
+ /*
+ * As last step, add an irq host to translate the real
+ * hw irq information provided by the ofw to linux virq
+ */
+
+ mpc52xx_irqhost =
+ irq_alloc_host(IRQ_HOST_MAP_LINEAR, NR_IRQS, &mpc52xx_irqhost_ops,
+ -1);
+ pr_debug("%s: mpc52xx_irqhost =%p\n", __func__, mpc52xx_irqhost);
+}
+
+unsigned int mpc52xx_get_irq(void)
+{
+ u32 status;
+ int virq;
+ int irq = NO_IRQ_IGNORE;
+
+ status = in_be32(&intr->enc_status);
+ if (status & 0x00000400) { /* critical */
+ irq = (status >> 8) & 0x3;
+ if (irq == 2) /* high priority peripheral */
+ goto peripheral;
+ irq += MPC52xx_CRIT_IRQ_BASE;
+ } else if (status & 0x00200000) { /* main */
+ irq = (status >> 16) & 0x1f;
+ if (irq == 4) /* low priority peripheral */
+ goto peripheral;
+ irq += MPC52xx_MAIN_IRQ_BASE;
+ } else if (status & 0x20000000) { /* peripheral */
+ peripheral:
+ irq = (status >> 24) & 0x1f;
+ if (irq == 0) { /* bestcomm */
+ status = in_be32(&sdma->IntPend);
+ irq = ffs(status) + MPC52xx_SDMA_IRQ_BASE - 1;
+ } else
+ irq += MPC52xx_PERP_IRQ_BASE;
+
+ }
+
+ virq = irq_linear_revmap(mpc52xx_irqhost, irq);
+ pr_debug("%s: irq=%d -> %d\n", __func__, irq, virq);
+
+ return virq;
+}
--- a/arch/powerpc/Kconfig 2006-10-25 19:07:23.000000000 +0200
+++ b/arch/powerpc/Kconfig 2006-10-26 18:55:58.000000000 +0200
@@ -384,6 +384,11 @@ config PPC_CHRP
select PPC_RTAS
select PPC_MPC106
select PPC_UDBG_16550
+ select PPC_MPC52xx_PIC
+ default y
+
+config PPC_MPC52xx_PIC
+ bool
default y
config PPC_PMAC
--- a/arch/powerpc/platforms/chrp/setup.c 2006-10-25 19:07:23.000000000 +0200
+++ b/arch/powerpc/platforms/chrp/setup.c 2006-10-26 21:47:29.000000000 +0200
@@ -51,6 +51,7 @@
#include <asm/mpic.h>
#include <asm/rtas.h>
#include <asm/xmon.h>
+#include <asm/mpc52xx.h>
#include "chrp.h"
@@ -435,6 +436,44 @@ static struct irqaction xmon_irqaction =
};
#endif
+
+struct device_node *find_mpc52xx_pic(void)
+{
+ struct device_node *dev;
+ const char *piccompatible_list[] =
+ {
+ "mpc5200-pic",
+ NULL
+ };
+
+ /* Look for an MPC52xx interrupt controller */
+ for_each_node_by_type(dev, "interrupt-controller")
+ {
+ const char **piccompatible_entry = piccompatible_list;
+
+ for(piccompatible_entry = piccompatible_list; *piccompatible_entry; piccompatible_entry++ )
+ {
+ if (device_is_compatible(dev, *piccompatible_entry ))
+ return dev;
+ }
+ }
+
+ return NULL;
+}
+
+static int __init chrp_find_mpc52xx_pic(void)
+{
+ if (find_mpc52xx_pic())
+ {
+ printk(KERN_INFO "Found MPC52xx Interrupt Controller\n");
+ ppc_md.get_irq = mpc52xx_get_irq;
+ mpc52xx_init_irq();
+ return 0;
+ }
+
+ return -ENODEV;
+}
+
static void __init chrp_find_8259(void)
{
struct device_node *np, *pic = NULL;
@@ -473,8 +512,11 @@ static void __init chrp_find_8259(void)
break;
}
if (np == NULL)
- printk(KERN_WARNING "Cannot find PCI interrupt acknowledge"
- " address, polling\n");
+ {
+ printk(KERN_WARNING "Cannot find PCI/i8259 interrupt acknowledge"
+ " Fix your tree!\n");
+ return;
+ }
i8259_init(pic, chrp_int_ack);
if (ppc_md.get_irq == NULL)
@@ -494,6 +536,8 @@ void __init chrp_init_IRQ(void)
#if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(XMON)
struct device_node *kbd;
#endif
+
+ chrp_find_mpc52xx_pic();
chrp_find_openpic();
chrp_find_8259();
[-- Attachment #3: nd.vcf --]
[-- Type: text/x-vcard, Size: 249 bytes --]
begin:vcard
fn:Nicolas DET ( bplan GmbH )
n:DET;Nicolas
org:bplan GmbH
adr:;;;;;;Germany
email;internet:nd@bplan-gmbh.de
title:Software Entwicklung
tel;work:+49 6171 9187 - 31
x-mozilla-html:FALSE
url:http://www.bplan-gmbh.de
version:2.1
end:vcard
^ permalink raw reply
* Re: [PATCH] General CHRP/MPC5K2 platform support patch
From: Nicolas DET @ 2006-10-26 19:32 UTC (permalink / raw)
To: Nicolas DET; +Cc: akpm, sl, linuxppc-dev, linuxppc-embedded, sha
In-Reply-To: <45410ABA.9000902@bplan-gmbh.de>
[-- Attachment #1: Type: text/plain, Size: 659 bytes --]
Nicolas DET wrote:
> Grant Likely wrote:
>
>>>
>>> diff -uprN a/include/asm-ppc/mpc52xx.h b/include/asm-ppc/mpc52xx.h
>>> --- a/include/asm-ppc/mpc52xx.h 2006-10-25 19:07:48.000000000 +0200
>>> +++ b/include/asm-ppc/mpc52xx.h 2006-10-25 19:11:55.000000000 +0200
>>> @@ -119,7 +119,7 @@ enum ppc_sys_devices {
>>> #define MPC52xx_SDMA_IRQ_NUM 17
>>> #define MPC52xx_PERP_IRQ_NUM 23
>>>
>>> -#define MPC52xx_CRIT_IRQ_BASE 1
>>> +#define MPC52xx_CRIT_IRQ_BASE 0
>>
>> Is this *strictly* necessary for adding mpc52xx-pic support to
>> arch/powerpc? If not, then move it to a separate patch.
>
>
> Removed as it does not hurt ARCH=powerpc.
Lindent...
[-- Attachment #2: chrpmpc52xx_2.6.19-rc3.patch --]
[-- Type: text/plain, Size: 12346 bytes --]
--- a/arch/powerpc/sysdev/Makefile 2006-10-25 19:07:24.000000000 +0200
+++ b/arch/powerpc/sysdev/Makefile 2006-10-26 11:38:02.000000000 +0200
@@ -13,6 +13,7 @@ obj-$(CONFIG_FSL_SOC) += fsl_soc.o
obj-$(CONFIG_PPC_TODC) += todc.o
obj-$(CONFIG_TSI108_BRIDGE) += tsi108_pci.o tsi108_dev.o
obj-$(CONFIG_QUICC_ENGINE) += qe_lib/
+obj-$(CONFIG_PPC_MPC52xx_PIC) += mpc52xx_pic.o
ifeq ($(CONFIG_PPC_MERGE),y)
obj-$(CONFIG_PPC_I8259) += i8259.o
--- a/arch/powerpc/sysdev/mpc52xx_pic.c 1970-01-01 01:00:00.000000000 +0100
+++ b/arch/powerpc/sysdev/mpc52xx_pic.c 2006-10-26 21:32:05.000000000 +0200
@@ -0,0 +1,363 @@
+/*
+ * arch/powerpc/sysdev/mpc52xx_pic.c
+ *
+ * Programmable Interrupt Controller functions for the Freescale MPC52xx
+ * embedded CPU.
+ * Modified for CHRP Efika 5K2
+ *
+ * Maintainer : Sylvain Munaut <tnt@246tNt.com>
+ *
+ * Based on (well, mostly copied from) the code from the 2.4 kernel by
+ * Dale Farnsworth <dfarnsworth@mvista.com> and Kent Borg.
+ *
+ * Copyright (C) 2004 Sylvain Munaut <tnt@246tNt.com>
+ * Copyright (C) 2003 Montavista Software, Inc
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <linux/stddef.h>
+#include <linux/init.h>
+#include <linux/sched.h>
+#include <linux/signal.h>
+#include <linux/stddef.h>
+#include <linux/delay.h>
+#include <linux/irq.h>
+
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <asm/system.h>
+#include <asm/irq.h>
+#include <asm/prom.h>
+
+#include <asm/mpc52xx.h>
+
+static struct mpc52xx_intr __iomem *intr;
+static struct mpc52xx_sdma __iomem *sdma;
+
+static struct irq_host *mpc52xx_irqhost = NULL;
+
+static void mpc52xx_ic_disable(unsigned int virq)
+{
+ u32 val;
+ int irq;
+
+ irq = irq_map[virq].hwirq;
+
+ pr_debug("%s: irq=%d\n", __func__, irq);
+
+ if (irq == MPC52xx_IRQ0) {
+ val = in_be32(&intr->ctrl);
+ val &= ~(1 << 11);
+ out_be32(&intr->ctrl, val);
+ } else if (irq < MPC52xx_IRQ1) {
+ BUG();
+ } else if (irq <= MPC52xx_IRQ3) {
+ val = in_be32(&intr->ctrl);
+ val &= ~(1 << (10 - (irq - MPC52xx_IRQ1)));
+ out_be32(&intr->ctrl, val);
+ } else if (irq < MPC52xx_SDMA_IRQ_BASE) {
+ val = in_be32(&intr->main_mask);
+ val |= 1 << (16 - (irq - MPC52xx_MAIN_IRQ_BASE));
+ out_be32(&intr->main_mask, val);
+ } else if (irq < MPC52xx_PERP_IRQ_BASE) {
+ val = in_be32(&sdma->IntMask);
+ val |= 1 << (irq - MPC52xx_SDMA_IRQ_BASE);
+ out_be32(&sdma->IntMask, val);
+ } else {
+ val = in_be32(&intr->per_mask);
+ val |= 1 << (31 - (irq - MPC52xx_PERP_IRQ_BASE));
+ out_be32(&intr->per_mask, val);
+ }
+}
+
+static void mpc52xx_ic_enable(unsigned int virq)
+{
+ u32 val;
+ int irq;
+
+ irq = irq_map[virq].hwirq;
+
+ pr_debug("%s: irq=%d\n", __func__, irq);
+
+ if (irq == MPC52xx_IRQ0) {
+ val = in_be32(&intr->ctrl);
+ val |= 1 << 11;
+ out_be32(&intr->ctrl, val);
+ } else if (irq < MPC52xx_IRQ1) {
+ BUG();
+ } else if (irq <= MPC52xx_IRQ3) {
+ val = in_be32(&intr->ctrl);
+ val |= 1 << (10 - (irq - MPC52xx_IRQ1));
+ out_be32(&intr->ctrl, val);
+ } else if (irq < MPC52xx_SDMA_IRQ_BASE) {
+ val = in_be32(&intr->main_mask);
+ val &= ~(1 << (16 - (irq - MPC52xx_MAIN_IRQ_BASE)));
+ out_be32(&intr->main_mask, val);
+ } else if (irq < MPC52xx_PERP_IRQ_BASE) {
+ val = in_be32(&sdma->IntMask);
+ val &= ~(1 << (irq - MPC52xx_SDMA_IRQ_BASE));
+ out_be32(&sdma->IntMask, val);
+ } else {
+ val = in_be32(&intr->per_mask);
+ val &= ~(1 << (31 - (irq - MPC52xx_PERP_IRQ_BASE)));
+ out_be32(&intr->per_mask, val);
+ }
+}
+
+static void mpc52xx_ic_ack(unsigned int virq)
+{
+ u32 val;
+ int irq;
+
+ irq = irq_map[virq].hwirq;
+
+ pr_debug("%s: irq=%d\n", __func__, irq);
+
+ /*
+ * Only some irqs are reset here, others in interrupting hardware.
+ */
+
+ switch (irq) {
+ case MPC52xx_IRQ0:
+ val = in_be32(&intr->ctrl);
+ val |= 0x08000000;
+ out_be32(&intr->ctrl, val);
+ break;
+ case MPC52xx_CCS_IRQ:
+ val = in_be32(&intr->enc_status);
+ val |= 0x00000400;
+ out_be32(&intr->enc_status, val);
+ break;
+ case MPC52xx_IRQ1:
+ val = in_be32(&intr->ctrl);
+ val |= 0x04000000;
+ out_be32(&intr->ctrl, val);
+ break;
+ case MPC52xx_IRQ2:
+ val = in_be32(&intr->ctrl);
+ val |= 0x02000000;
+ out_be32(&intr->ctrl, val);
+ break;
+ case MPC52xx_IRQ3:
+ val = in_be32(&intr->ctrl);
+ val |= 0x01000000;
+ out_be32(&intr->ctrl, val);
+ break;
+ default:
+ if (irq >= MPC52xx_SDMA_IRQ_BASE
+ && irq < (MPC52xx_SDMA_IRQ_BASE + MPC52xx_SDMA_IRQ_NUM)) {
+ out_be32(&sdma->IntPend,
+ 1 << (irq - MPC52xx_SDMA_IRQ_BASE));
+ }
+
+ break;
+ }
+
+}
+
+static void mpc52xx_ic_disable_and_ack(unsigned int irq)
+{
+ mpc52xx_ic_disable(irq);
+ mpc52xx_ic_ack(irq);
+}
+
+static void mpc52xx_ic_end(unsigned int irq)
+{
+ if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
+ mpc52xx_ic_enable(irq);
+}
+
+static struct irq_chip mpc52xx_irqchip = {
+ .name = " MPC52xx ",
+ .enable = mpc52xx_ic_enable,
+ .disable = mpc52xx_ic_disable,
+ .ack = mpc52xx_ic_disable_and_ack,
+ .end = mpc52xx_ic_end,
+};
+
+extern struct device_node *find_mpc52xx_pic(void);
+static int mpc52xx_irqhost_match(struct irq_host *h, struct device_node *node)
+{
+ pr_debug("%s: %p vs %p\n", __func__, find_mpc52xx_pic(), node);
+ return find_mpc52xx_pic() == node;
+}
+
+static int mpc52xx_irqhost_xlate(struct irq_host *h, struct device_node *ct,
+ u32 * intspec, unsigned int intsize,
+ irq_hw_number_t * out_hwirq,
+ unsigned int *out_flags)
+{
+ static unsigned char map_senses[4] = {
+ IRQ_TYPE_LEVEL_HIGH,
+ IRQ_TYPE_EDGE_FALLING,
+ IRQ_TYPE_EDGE_RISING,
+ IRQ_TYPE_LEVEL_LOW,
+ };
+
+ int intrvect_l1;
+ int intrvect_l2;
+ int intrvect_type;
+ int intrvect_linux;
+
+ pr_debug("%s:\n", __func__);
+
+ if (intsize != 3)
+ return -1;
+
+ intrvect_l1 = (int)intspec[0];
+ intrvect_l2 = (int)intspec[1];
+ intrvect_type = (int)intspec[2];
+
+ pr_debug("l1=%d, l2=%d, type=%d\n", intrvect_l1, intrvect_l2,
+ intrvect_type);
+
+ switch (intrvect_l1) {
+ case 0: /* Critical */
+ intrvect_linux = MPC52xx_CRIT_IRQ_BASE;
+ break;
+
+ case 1: /* Main */
+ intrvect_linux = MPC52xx_MAIN_IRQ_BASE;
+ break;
+
+ case 2: /* Periph */
+ intrvect_linux = MPC52xx_PERP_IRQ_BASE;
+ break;
+
+ case 3: /* Bestcomm */
+ intrvect_linux = MPC52xx_SDMA_IRQ_BASE;
+ break;
+
+ default:
+ if (printk_ratelimit())
+ printk(KERN_ERR "Wrong L1 interrupt vector (%d)\n",
+ intrvect_l1);
+
+ return -1;
+ }
+
+ intrvect_linux += intrvect_l2;
+
+ pr_debug("return %d\n", intrvect_linux);
+
+ *out_hwirq = intrvect_linux;
+ *out_flags = map_senses[intrvect_type];
+
+ return 0;
+
+}
+
+int mpc52xx_irqhost_map(struct irq_host *h, unsigned int virq,
+ irq_hw_number_t hw)
+{
+ pr_debug("%s: v=%d, hw=%d\n", __func__, virq, (int)hw);
+
+ return 0;
+}
+
+void mpc52xx_irqhost_unmap(struct irq_host *h, unsigned int virq)
+{
+ pr_debug("%s: v=%d\n", __func__, virq);
+}
+
+static struct irq_host_ops mpc52xx_irqhost_ops = {
+ .match = mpc52xx_irqhost_match,
+ .xlate = mpc52xx_irqhost_xlate,
+ .map = mpc52xx_irqhost_map,
+ .unmap = mpc52xx_irqhost_unmap,
+};
+
+void __init mpc52xx_init_irq(void)
+{
+ int i;
+ u32 intr_ctrl;
+
+ /* Remap the necessary zones */
+ intr = ioremap(MPC52xx_PA(MPC52xx_INTR_OFFSET), MPC52xx_INTR_SIZE);
+ sdma = ioremap(MPC52xx_PA(MPC52xx_SDMA_OFFSET), MPC52xx_SDMA_SIZE);
+
+ if ((intr == NULL) || (sdma == NULL))
+ panic("Can't ioremap PIC/SDMA register or init_irq !");
+
+ /* Disable all interrupt sources. */
+ out_be32(&sdma->IntPend, 0xffffffff); /* 1 means clear pending */
+ out_be32(&sdma->IntMask, 0xffffffff); /* 1 means disabled */
+ out_be32(&intr->per_mask, 0x7ffffc00); /* 1 means disabled */
+ out_be32(&intr->main_mask, 0x00010fff); /* 1 means disabled */
+ intr_ctrl = in_be32(&intr->ctrl);
+ intr_ctrl &= 0x00ff0000; /* Keeps IRQ[0-3] config */
+ intr_ctrl |= 0x0f000000 | /* clear IRQ 0-3 */
+ 0x00001000 | /* MEE master external enable */
+ 0x00000000 | /* 0 means disable IRQ 0-3 */
+ 0x00000001; /* CEb route critical normally */
+ out_be32(&intr->ctrl, intr_ctrl);
+
+ /* Zero a bunch of the priority settings. */
+ out_be32(&intr->per_pri1, 0);
+ out_be32(&intr->per_pri2, 0);
+ out_be32(&intr->per_pri3, 0);
+ out_be32(&intr->main_pri1, 0);
+ out_be32(&intr->main_pri2, 0);
+ /* Initialize irq_desc[i].handler's with mpc52xx_ic. */
+ for (i = 0; i < NR_IRQS; i++) {
+ irq_desc[i].chip = &mpc52xx_irqchip;
+ irq_desc[i].status = IRQ_LEVEL;
+
+ }
+
+#define IRQn_MODE(intr_ctrl,irq) (((intr_ctrl) >> (22-(i<<1))) & 0x03)
+ for (i = 0; i < 4; i++) {
+ int mode;
+ mode = IRQn_MODE(intr_ctrl, i);
+ if ((mode == 0x1) || (mode == 0x2))
+ irq_desc[i ? MPC52xx_IRQ1 + i -
+ 1 : MPC52xx_IRQ0].status = 0;
+ }
+
+ /*
+ * As last step, add an irq host to translate the real
+ * hw irq information provided by the ofw to linux virq
+ */
+
+ mpc52xx_irqhost =
+ irq_alloc_host(IRQ_HOST_MAP_LINEAR, NR_IRQS, &mpc52xx_irqhost_ops,
+ -1);
+ pr_debug("%s: mpc52xx_irqhost =%p\n", __func__, mpc52xx_irqhost);
+}
+
+unsigned int mpc52xx_get_irq(void)
+{
+ u32 status;
+ int virq;
+ int irq = NO_IRQ_IGNORE;
+
+ status = in_be32(&intr->enc_status);
+ if (status & 0x00000400) { /* critical */
+ irq = (status >> 8) & 0x3;
+ if (irq == 2) /* high priority peripheral */
+ goto peripheral;
+ irq += MPC52xx_CRIT_IRQ_BASE;
+ } else if (status & 0x00200000) { /* main */
+ irq = (status >> 16) & 0x1f;
+ if (irq == 4) /* low priority peripheral */
+ goto peripheral;
+ irq += MPC52xx_MAIN_IRQ_BASE;
+ } else if (status & 0x20000000) { /* peripheral */
+ peripheral:
+ irq = (status >> 24) & 0x1f;
+ if (irq == 0) { /* bestcomm */
+ status = in_be32(&sdma->IntPend);
+ irq = ffs(status) + MPC52xx_SDMA_IRQ_BASE - 1;
+ } else
+ irq += MPC52xx_PERP_IRQ_BASE;
+
+ }
+
+ virq = irq_linear_revmap(mpc52xx_irqhost, irq);
+ pr_debug("%s: irq=%d -> %d\n", __func__, irq, virq);
+
+ return virq;
+}
--- a/arch/powerpc/Kconfig 2006-10-25 19:07:23.000000000 +0200
+++ b/arch/powerpc/Kconfig 2006-10-26 18:55:58.000000000 +0200
@@ -384,6 +384,11 @@ config PPC_CHRP
select PPC_RTAS
select PPC_MPC106
select PPC_UDBG_16550
+ select PPC_MPC52xx_PIC
+ default y
+
+config PPC_MPC52xx_PIC
+ bool
default y
config PPC_PMAC
--- a/arch/powerpc/platforms/chrp/setup.c 2006-10-25 19:07:23.000000000 +0200
+++ b/arch/powerpc/platforms/chrp/setup.c 2006-10-26 18:56:34.000000000 +0200
@@ -51,6 +51,7 @@
#include <asm/mpic.h>
#include <asm/rtas.h>
#include <asm/xmon.h>
+#include <asm/mpc52xx.h>
#include "chrp.h"
@@ -435,6 +436,51 @@ static struct irqaction xmon_irqaction =
};
#endif
+
+struct device_node *find_mpc52xx_pic(void)
+{
+ struct device_node *dev;
+ const char *piccompatible_list[] =
+ {
+ "mpc5200-interrupt-controller",
+ "mpc52xx-interrupt-controller",
+ "mpc52xx-pic",
+ "mpc5200-pic",
+ "5200-interrupt-controller",
+ "52xx-interrupt-controller",
+ "52xx-pic",
+ "5200-pic",
+ NULL
+ };
+
+ /* Look for an MPC52xx interrupt controller */
+ for_each_node_by_type(dev, "interrupt-controller")
+ {
+ const char **piccompatible_entry = piccompatible_list;
+
+ for(piccompatible_entry = piccompatible_list; *piccompatible_entry; piccompatible_entry++ )
+ {
+ if (device_is_compatible(dev, *piccompatible_entry ))
+ return dev;
+ }
+ }
+
+ return NULL;
+}
+
+static int __init chrp_find_mpc52xx_pic(void)
+{
+ if (find_mpc52xx_pic())
+ {
+ printk(KERN_INFO "Found MPC52xx Interrupt Controller\n");
+ ppc_md.get_irq = mpc52xx_get_irq;
+ mpc52xx_init_irq();
+ return 0;
+ }
+
+ return -ENODEV;
+}
+
static void __init chrp_find_8259(void)
{
struct device_node *np, *pic = NULL;
@@ -473,8 +519,11 @@ static void __init chrp_find_8259(void)
break;
}
if (np == NULL)
- printk(KERN_WARNING "Cannot find PCI interrupt acknowledge"
- " address, polling\n");
+ {
+ printk(KERN_WARNING "Cannot find PCI/i8259 interrupt acknowledge"
+ " Fix your tree!\n");
+ return;
+ }
i8259_init(pic, chrp_int_ack);
if (ppc_md.get_irq == NULL)
@@ -494,6 +543,8 @@ void __init chrp_init_IRQ(void)
#if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(XMON)
struct device_node *kbd;
#endif
+
+ chrp_find_mpc52xx_pic();
chrp_find_openpic();
chrp_find_8259();
[-- Attachment #3: nd.vcf --]
[-- Type: text/x-vcard, Size: 249 bytes --]
begin:vcard
fn:Nicolas DET ( bplan GmbH )
n:DET;Nicolas
org:bplan GmbH
adr:;;;;;;Germany
email;internet:nd@bplan-gmbh.de
title:Software Entwicklung
tel;work:+49 6171 9187 - 31
x-mozilla-html:FALSE
url:http://www.bplan-gmbh.de
version:2.1
end:vcard
^ permalink raw reply
* Re: [PATCH] General CHRP/MPC5K2 platform support patch
From: Nicolas DET @ 2006-10-26 19:21 UTC (permalink / raw)
To: Grant Likely; +Cc: akpm, sl, linuxppc-dev, linuxppc-embedded, sha
In-Reply-To: <528646bc0610261214i34351884reb3171413e4c105@mail.gmail.com>
[-- Attachment #1: Type: text/plain, Size: 611 bytes --]
Grant Likely wrote:
>>
>> diff -uprN a/include/asm-ppc/mpc52xx.h b/include/asm-ppc/mpc52xx.h
>> --- a/include/asm-ppc/mpc52xx.h 2006-10-25 19:07:48.000000000 +0200
>> +++ b/include/asm-ppc/mpc52xx.h 2006-10-25 19:11:55.000000000 +0200
>> @@ -119,7 +119,7 @@ enum ppc_sys_devices {
>> #define MPC52xx_SDMA_IRQ_NUM 17
>> #define MPC52xx_PERP_IRQ_NUM 23
>>
>> -#define MPC52xx_CRIT_IRQ_BASE 1
>> +#define MPC52xx_CRIT_IRQ_BASE 0
>
> Is this *strictly* necessary for adding mpc52xx-pic support to
> arch/powerpc? If not, then move it to a separate patch.
Removed as it does not hurt ARCH=powerpc.
Bye
[-- Attachment #2: chrpmpc52xx_2.6.19-rc3.patch --]
[-- Type: text/plain, Size: 14370 bytes --]
--- a/arch/powerpc/sysdev/Makefile 2006-10-25 19:07:24.000000000 +0200
+++ b/arch/powerpc/sysdev/Makefile 2006-10-26 11:38:02.000000000 +0200
@@ -13,6 +13,7 @@ obj-$(CONFIG_FSL_SOC) += fsl_soc.o
obj-$(CONFIG_PPC_TODC) += todc.o
obj-$(CONFIG_TSI108_BRIDGE) += tsi108_pci.o tsi108_dev.o
obj-$(CONFIG_QUICC_ENGINE) += qe_lib/
+obj-$(CONFIG_PPC_MPC52xx_PIC) += mpc52xx_pic.o
ifeq ($(CONFIG_PPC_MERGE),y)
obj-$(CONFIG_PPC_I8259) += i8259.o
--- a/arch/powerpc/sysdev/mpc52xx_pic.c 1970-01-01 01:00:00.000000000 +0100
+++ b/arch/powerpc/sysdev/mpc52xx_pic.c 2006-10-26 18:55:04.000000000 +0200
@@ -0,0 +1,368 @@
+/*
+ * arch/powerpc/sysdev/mpc52xx_pic.c
+ *
+ * Programmable Interrupt Controller functions for the Freescale MPC52xx
+ * embedded CPU.
+ *
+ * Maintainer : Sylvain Munaut <tnt@246tNt.com>
+ *
+ * Based on (well, mostly copied from) the code from the 2.4 kernel by
+ * Dale Farnsworth <dfarnsworth@mvista.com> and Kent Borg.
+ *
+ * Copyright (C) 2004 Sylvain Munaut <tnt@246tNt.com>
+ * Copyright (C) 2003 Montavista Software, Inc
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <linux/stddef.h>
+#include <linux/init.h>
+#include <linux/sched.h>
+#include <linux/signal.h>
+#include <linux/stddef.h>
+#include <linux/delay.h>
+#include <linux/irq.h>
+
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <asm/system.h>
+#include <asm/irq.h>
+#include <asm/prom.h>
+
+#include <asm/mpc52xx.h>
+
+static struct mpc52xx_intr __iomem *intr;
+static struct mpc52xx_sdma __iomem *sdma;
+
+static struct irq_host *mpc52xx_irqhost = NULL;
+
+static void
+mpc52xx_ic_disable(unsigned int virq)
+{
+ u32 val;
+ int irq;
+
+ irq = irq_map[virq].hwirq;
+
+ pr_debug("%s: irq=%d\n", __func__, irq);
+
+ if (irq == MPC52xx_IRQ0) {
+ val = in_be32(&intr->ctrl);
+ val &= ~(1 << 11);
+ out_be32(&intr->ctrl, val);
+ } else if (irq < MPC52xx_IRQ1) {
+ BUG();
+ } else if (irq <= MPC52xx_IRQ3) {
+ val = in_be32(&intr->ctrl);
+ val &= ~(1 << (10 - (irq - MPC52xx_IRQ1)));
+ out_be32(&intr->ctrl, val);
+ } else if (irq < MPC52xx_SDMA_IRQ_BASE) {
+ val = in_be32(&intr->main_mask);
+ val |= 1 << (16 - (irq - MPC52xx_MAIN_IRQ_BASE));
+ out_be32(&intr->main_mask, val);
+ } else if (irq < MPC52xx_PERP_IRQ_BASE) {
+ val = in_be32(&sdma->IntMask);
+ val |= 1 << (irq - MPC52xx_SDMA_IRQ_BASE);
+ out_be32(&sdma->IntMask, val);
+ } else {
+ val = in_be32(&intr->per_mask);
+ val |= 1 << (31 - (irq - MPC52xx_PERP_IRQ_BASE));
+ out_be32(&intr->per_mask, val);
+ }
+}
+
+static void
+mpc52xx_ic_enable(unsigned int virq)
+{
+ u32 val;
+ int irq;
+
+ irq = irq_map[virq].hwirq;
+
+ pr_debug("%s: irq=%d\n", __func__, irq);
+
+ if (irq == MPC52xx_IRQ0) {
+ val = in_be32(&intr->ctrl);
+ val |= 1 << 11;
+ out_be32(&intr->ctrl, val);
+ } else if (irq < MPC52xx_IRQ1) {
+ BUG();
+ } else if (irq <= MPC52xx_IRQ3) {
+ val = in_be32(&intr->ctrl);
+ val |= 1 << (10 - (irq - MPC52xx_IRQ1));
+ out_be32(&intr->ctrl, val);
+ } else if (irq < MPC52xx_SDMA_IRQ_BASE) {
+ val = in_be32(&intr->main_mask);
+ val &= ~(1 << (16 - (irq - MPC52xx_MAIN_IRQ_BASE)));
+ out_be32(&intr->main_mask, val);
+ } else if (irq < MPC52xx_PERP_IRQ_BASE) {
+ val = in_be32(&sdma->IntMask);
+ val &= ~(1 << (irq - MPC52xx_SDMA_IRQ_BASE));
+ out_be32(&sdma->IntMask, val);
+ } else {
+ val = in_be32(&intr->per_mask);
+ val &= ~(1 << (31 - (irq - MPC52xx_PERP_IRQ_BASE)));
+ out_be32(&intr->per_mask, val);
+ }
+}
+
+static void
+mpc52xx_ic_ack(unsigned int virq)
+{
+ u32 val;
+ int irq;
+
+ irq = irq_map[virq].hwirq;
+
+ pr_debug("%s: irq=%d\n", __func__, irq);
+
+ /*
+ * Only some irqs are reset here, others in interrupting hardware.
+ */
+
+ switch (irq) {
+ case MPC52xx_IRQ0:
+ val = in_be32(&intr->ctrl);
+ val |= 0x08000000;
+ out_be32(&intr->ctrl, val);
+ break;
+ case MPC52xx_CCS_IRQ:
+ val = in_be32(&intr->enc_status);
+ val |= 0x00000400;
+ out_be32(&intr->enc_status, val);
+ break;
+ case MPC52xx_IRQ1:
+ val = in_be32(&intr->ctrl);
+ val |= 0x04000000;
+ out_be32(&intr->ctrl, val);
+ break;
+ case MPC52xx_IRQ2:
+ val = in_be32(&intr->ctrl);
+ val |= 0x02000000;
+ out_be32(&intr->ctrl, val);
+ break;
+ case MPC52xx_IRQ3:
+ val = in_be32(&intr->ctrl);
+ val |= 0x01000000;
+ out_be32(&intr->ctrl, val);
+ break;
+ default:
+ if (irq >= MPC52xx_SDMA_IRQ_BASE
+ && irq < (MPC52xx_SDMA_IRQ_BASE + MPC52xx_SDMA_IRQ_NUM)) {
+ out_be32(&sdma->IntPend,
+ 1 << (irq - MPC52xx_SDMA_IRQ_BASE));
+ }
+
+ break;
+ }
+
+}
+
+static void
+mpc52xx_ic_disable_and_ack(unsigned int irq)
+{
+ mpc52xx_ic_disable(irq);
+ mpc52xx_ic_ack(irq);
+}
+
+static void
+mpc52xx_ic_end(unsigned int irq)
+{
+ if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
+ mpc52xx_ic_enable(irq);
+}
+
+static struct irq_chip mpc52xx_irqchip = {
+ .name = " MPC52xx ",
+ .enable = mpc52xx_ic_enable,
+ .disable = mpc52xx_ic_disable,
+ .ack = mpc52xx_ic_disable_and_ack,
+ .end = mpc52xx_ic_end,
+};
+
+
+extern struct device_node *find_mpc52xx_pic(void);
+static int mpc52xx_irqhost_match(struct irq_host *h, struct device_node *node)
+{
+ pr_debug("%s: %p vs %p\n", __func__, find_mpc52xx_pic(), node);
+ return find_mpc52xx_pic() == node;
+}
+
+static int mpc52xx_irqhost_xlate(struct irq_host *h, struct device_node *ct,
+ u32 *intspec, unsigned int intsize,
+ irq_hw_number_t *out_hwirq, unsigned int *out_flags)
+{
+ static unsigned char map_senses[4] = {
+ IRQ_TYPE_LEVEL_HIGH,
+ IRQ_TYPE_EDGE_FALLING,
+ IRQ_TYPE_EDGE_RISING,
+ IRQ_TYPE_LEVEL_LOW,
+ };
+
+ int intrvect_l1;
+ int intrvect_l2;
+ int intrvect_type;
+ int intrvect_linux;
+
+ pr_debug("%s:\n", __func__);
+
+ if (intsize!=3)
+ return -1;
+
+ intrvect_l1 = (int) intspec[0];
+ intrvect_l2 = (int) intspec[1];
+ intrvect_type = (int) intspec[2];
+
+ pr_debug("l1=%d, l2=%d, type=%d\n", intrvect_l1, intrvect_l2, intrvect_type );
+
+ switch(intrvect_l1) {
+ case 0: /* Critical */
+ intrvect_linux = MPC52xx_CRIT_IRQ_BASE;
+ break;
+
+ case 1: /* Main */
+ intrvect_linux = MPC52xx_MAIN_IRQ_BASE;
+ break;
+
+ case 2: /* Periph */
+ intrvect_linux = MPC52xx_PERP_IRQ_BASE;
+ break;
+
+ case 3: /* Bestcomm */
+ intrvect_linux = MPC52xx_SDMA_IRQ_BASE;
+ break;
+
+ default:
+ if ( printk_ratelimit() )
+ printk(KERN_ERR "Wrong L1 interrupt vector (%d)\n", intrvect_l1);
+
+ return -1;
+ }
+
+ intrvect_linux += intrvect_l2;
+
+ pr_debug("return %d\n", intrvect_linux);
+
+ *out_hwirq = intrvect_linux;
+ *out_flags = map_senses[intrvect_type];
+
+ return 0;
+
+}
+
+int mpc52xx_irqhost_map(struct irq_host *h, unsigned int virq, irq_hw_number_t hw)
+{
+ pr_debug("%s: v=%d, hw=%d\n", __func__, virq, (int) hw);
+
+ return 0;
+}
+
+void mpc52xx_irqhost_unmap(struct irq_host *h, unsigned int virq)
+{
+ pr_debug("%s: v=%d\n", __func__, virq);
+}
+
+static struct irq_host_ops mpc52xx_irqhost_ops = {
+ .match = mpc52xx_irqhost_match,
+ .xlate = mpc52xx_irqhost_xlate,
+ .map = mpc52xx_irqhost_map,
+ .unmap = mpc52xx_irqhost_unmap,
+};
+
+void __init
+mpc52xx_init_irq(void)
+{
+ int i;
+ u32 intr_ctrl;
+
+
+ /* Remap the necessary zones */
+ intr = ioremap(MPC52xx_PA(MPC52xx_INTR_OFFSET), MPC52xx_INTR_SIZE);
+ sdma = ioremap(MPC52xx_PA(MPC52xx_SDMA_OFFSET), MPC52xx_SDMA_SIZE);
+
+ if ((intr==NULL) || (sdma==NULL))
+ panic("Can't ioremap PIC/SDMA register or init_irq !");
+
+ /* Disable all interrupt sources. */
+ out_be32(&sdma->IntPend, 0xffffffff); /* 1 means clear pending */
+ out_be32(&sdma->IntMask, 0xffffffff); /* 1 means disabled */
+ out_be32(&intr->per_mask, 0x7ffffc00); /* 1 means disabled */
+ out_be32(&intr->main_mask, 0x00010fff); /* 1 means disabled */
+ intr_ctrl = in_be32(&intr->ctrl);
+ intr_ctrl &= 0x00ff0000; /* Keeps IRQ[0-3] config */
+ intr_ctrl |= 0x0f000000 | /* clear IRQ 0-3 */
+ 0x00001000 | /* MEE master external enable */
+ 0x00000000 | /* 0 means disable IRQ 0-3 */
+ 0x00000001; /* CEb route critical normally */
+ out_be32(&intr->ctrl, intr_ctrl);
+
+ /* Zero a bunch of the priority settings. */
+ out_be32(&intr->per_pri1, 0);
+ out_be32(&intr->per_pri2, 0);
+ out_be32(&intr->per_pri3, 0);
+ out_be32(&intr->main_pri1, 0);
+ out_be32(&intr->main_pri2, 0);
+ /* Initialize irq_desc[i].handler's with mpc52xx_ic. */
+ for (i = 0; i < NR_IRQS; i++) {
+ irq_desc[i].chip = &mpc52xx_irqchip;
+ irq_desc[i].status = IRQ_LEVEL;
+
+ }
+
+#define IRQn_MODE(intr_ctrl,irq) (((intr_ctrl) >> (22-(i<<1))) & 0x03)
+ for (i=0 ; i<4 ; i++) {
+ int mode;
+ mode = IRQn_MODE(intr_ctrl,i);
+ if ((mode == 0x1) || (mode == 0x2))
+ irq_desc[i?MPC52xx_IRQ1+i-1:MPC52xx_IRQ0].status = 0;
+ }
+
+ /*
+ * As last step, add an irq host to translate the real
+ * hw irq information provided by the ofw to linux virq
+ */
+
+ mpc52xx_irqhost = irq_alloc_host(IRQ_HOST_MAP_LINEAR, NR_IRQS, &mpc52xx_irqhost_ops, -1);
+ pr_debug("%s: mpc52xx_irqhost =%p\n", __func__, mpc52xx_irqhost );
+}
+
+unsigned int
+mpc52xx_get_irq(void)
+{
+ u32 status;
+ int virq;
+ int irq = NO_IRQ_IGNORE;
+
+ status = in_be32(&intr->enc_status);
+ if (status & 0x00000400)
+ { /* critical */
+ irq = (status >> 8) & 0x3;
+ if (irq == 2) /* high priority peripheral */
+ goto peripheral;
+ irq += MPC52xx_CRIT_IRQ_BASE;
+ } else if (status & 0x00200000)
+ { /* main */
+ irq = (status >> 16) & 0x1f;
+ if (irq == 4) /* low priority peripheral */
+ goto peripheral;
+ irq += MPC52xx_MAIN_IRQ_BASE;
+ } else if (status & 0x20000000)
+ { /* peripheral */
+peripheral:
+ irq = (status >> 24) & 0x1f;
+ if (irq == 0) { /* bestcomm */
+ status = in_be32(&sdma->IntPend);
+ irq = ffs(status) + MPC52xx_SDMA_IRQ_BASE-1;
+ } else
+ irq += MPC52xx_PERP_IRQ_BASE;
+
+ }
+
+ virq = irq_linear_revmap(mpc52xx_irqhost, irq);
+ pr_debug("%s: irq=%d -> %d\n", __func__, irq, virq);
+
+ return virq;
+}
+
--- a/arch/powerpc/Kconfig 2006-10-25 19:07:23.000000000 +0200
+++ b/arch/powerpc/Kconfig 2006-10-26 18:55:58.000000000 +0200
@@ -384,6 +384,11 @@ config PPC_CHRP
select PPC_RTAS
select PPC_MPC106
select PPC_UDBG_16550
+ select PPC_MPC52xx_PIC
+ default y
+
+config PPC_MPC52xx_PIC
+ bool
default y
config PPC_PMAC
--- a/arch/powerpc/platforms/chrp/setup.c 2006-10-25 19:07:23.000000000 +0200
+++ b/arch/powerpc/platforms/chrp/setup.c 2006-10-26 18:56:34.000000000 +0200
@@ -51,6 +51,7 @@
#include <asm/mpic.h>
#include <asm/rtas.h>
#include <asm/xmon.h>
+#include <asm/mpc52xx.h>
#include "chrp.h"
@@ -435,6 +436,51 @@ static struct irqaction xmon_irqaction =
};
#endif
+
+struct device_node *find_mpc52xx_pic(void)
+{
+ struct device_node *dev;
+ const char *piccompatible_list[] =
+ {
+ "mpc5200-interrupt-controller",
+ "mpc52xx-interrupt-controller",
+ "mpc52xx-pic",
+ "mpc5200-pic",
+ "5200-interrupt-controller",
+ "52xx-interrupt-controller",
+ "52xx-pic",
+ "5200-pic",
+ NULL
+ };
+
+ /* Look for an MPC52xx interrupt controller */
+ for_each_node_by_type(dev, "interrupt-controller")
+ {
+ const char **piccompatible_entry = piccompatible_list;
+
+ for(piccompatible_entry = piccompatible_list; *piccompatible_entry; piccompatible_entry++ )
+ {
+ if (device_is_compatible(dev, *piccompatible_entry ))
+ return dev;
+ }
+ }
+
+ return NULL;
+}
+
+static int __init chrp_find_mpc52xx_pic(void)
+{
+ if (find_mpc52xx_pic())
+ {
+ printk(KERN_INFO "Found MPC52xx Interrupt Controller\n");
+ ppc_md.get_irq = mpc52xx_get_irq;
+ mpc52xx_init_irq();
+ return 0;
+ }
+
+ return -ENODEV;
+}
+
static void __init chrp_find_8259(void)
{
struct device_node *np, *pic = NULL;
@@ -473,8 +519,11 @@ static void __init chrp_find_8259(void)
break;
}
if (np == NULL)
- printk(KERN_WARNING "Cannot find PCI interrupt acknowledge"
- " address, polling\n");
+ {
+ printk(KERN_WARNING "Cannot find PCI/i8259 interrupt acknowledge"
+ " Fix your tree!\n");
+ return;
+ }
i8259_init(pic, chrp_int_ack);
if (ppc_md.get_irq == NULL)
@@ -494,6 +543,8 @@ void __init chrp_init_IRQ(void)
#if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(XMON)
struct device_node *kbd;
#endif
+
+ chrp_find_mpc52xx_pic();
chrp_find_openpic();
chrp_find_8259();
[-- Attachment #3: nd.vcf --]
[-- Type: text/x-vcard, Size: 249 bytes --]
begin:vcard
fn:Nicolas DET ( bplan GmbH )
n:DET;Nicolas
org:bplan GmbH
adr:;;;;;;Germany
email;internet:nd@bplan-gmbh.de
title:Software Entwicklung
tel;work:+49 6171 9187 - 31
x-mozilla-html:FALSE
url:http://www.bplan-gmbh.de
version:2.1
end:vcard
^ permalink raw reply
* Re: [PATCH] General CHRP/MPC5K2 platform support patch
From: Grant Likely @ 2006-10-26 19:14 UTC (permalink / raw)
To: Nicolas DET; +Cc: akpm, sl, linuxppc-dev, linuxppc-embedded, sha
In-Reply-To: <4540EB0E.2090000@bplan-gmbh.de>
I've already made these comments on IRC; but I'll repeat them here for
posterity. :)
General:
- Run this code through Lindent; fixes up spacing and line endings
On 10/26/06, Nicolas DET <nd@bplan-gmbh.de> wrote:
> --- a/arch/powerpc/platforms/chrp/setup.c 2006-10-25 19:07:23.000000000 +0200
> +++ b/arch/powerpc/platforms/chrp/setup.c 2006-10-26 18:56:34.000000000 +0200
> @@ -51,6 +51,7 @@
> #include <asm/mpic.h>
> #include <asm/rtas.h>
> #include <asm/xmon.h>
> +#include <asm/mpc52xx.h>
>
> #include "chrp.h"
>
> @@ -435,6 +436,51 @@ static struct irqaction xmon_irqaction =
> };
> #endif
>
> +
> +struct device_node *find_mpc52xx_pic(void)
> +{
> + struct device_node *dev;
> + const char *piccompatible_list[] =
> + {
> + "mpc5200-interrupt-controller",
> + "mpc52xx-interrupt-controller",
> + "mpc52xx-pic",
> + "mpc5200-pic",
> + "5200-interrupt-controller",
> + "52xx-interrupt-controller",
> + "52xx-pic",
> + "5200-pic",
> + NULL
> + };
As you mentioned on IRC that benh suggested "mpc52xx-pic"; Just call
it mpc52xx-pic and be done with it. Don't need to loop over this
table. If incompatible variants appear in the future; this can
change.
> +
> + /* Look for an MPC52xx interrupt controller */
> + for_each_node_by_type(dev, "interrupt-controller")
> + {
> + const char **piccompatible_entry = piccompatible_list;
> +
> + for(piccompatible_entry = piccompatible_list; *piccompatible_entry; piccompatible_entry++ )
> + {
> + if (device_is_compatible(dev, *piccompatible_entry ))
> + return dev;
> + }
> + }
> +
> + return NULL;
> +}
> +
> +static int __init chrp_find_mpc52xx_pic(void)
> +{
> + if (find_mpc52xx_pic())
> + {
> + printk(KERN_INFO "Found MPC52xx Interrupt Controller\n");
> + ppc_md.get_irq = mpc52xx_get_irq;
> + mpc52xx_init_irq();
> + return 0;
> + }
> +
> + return -ENODEV;
> +}
> +
> static void __init chrp_find_8259(void)
> {
> struct device_node *np, *pic = NULL;
> @@ -473,8 +519,11 @@ static void __init chrp_find_8259(void)
> break;
> }
> if (np == NULL)
> - printk(KERN_WARNING "Cannot find PCI interrupt acknowledge"
> - " address, polling\n");
> + {
> + printk(KERN_WARNING "Cannot find PCI/i8259 interrupt acknowledge"
> + " Fix your tree!\n");
> + return;
> + }
>
> i8259_init(pic, chrp_int_ack);
> if (ppc_md.get_irq == NULL)
Missing the fixup to prevent i8258 from clobbering the 52xx-pic. You
do need to have that change in this patch; or have this patch
dependent on another patch that fixes it. Otherwise, as you know,
this patch is worthless! :)
And on the other side of this coin; I don't think that the message
change in chrp_find_8259 has anything to do with adding mpc52xx. :)
(Unfortunately, I have tendencies towards perfectionism)
And on the flip side, I would (*
> @@ -494,6 +543,8 @@ void __init chrp_init_IRQ(void)
> #if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(XMON)
> struct device_node *kbd;
> #endif
> +
> + chrp_find_mpc52xx_pic();
> chrp_find_openpic();
> chrp_find_8259();
>
> diff -uprN a/include/asm-ppc/mpc52xx.h b/include/asm-ppc/mpc52xx.h
> --- a/include/asm-ppc/mpc52xx.h 2006-10-25 19:07:48.000000000 +0200
> +++ b/include/asm-ppc/mpc52xx.h 2006-10-25 19:11:55.000000000 +0200
> @@ -119,7 +119,7 @@ enum ppc_sys_devices {
> #define MPC52xx_SDMA_IRQ_NUM 17
> #define MPC52xx_PERP_IRQ_NUM 23
>
> -#define MPC52xx_CRIT_IRQ_BASE 1
> +#define MPC52xx_CRIT_IRQ_BASE 0
Is this *strictly* necessary for adding mpc52xx-pic support to
arch/powerpc? If not, then move it to a separate patch.
> #define MPC52xx_MAIN_IRQ_BASE (MPC52xx_CRIT_IRQ_BASE + MPC52xx_CRIT_IRQ_NUM)
> #define MPC52xx_SDMA_IRQ_BASE (MPC52xx_MAIN_IRQ_BASE + MPC52xx_MAIN_IRQ_NUM)
> #define MPC52xx_PERP_IRQ_BASE (MPC52xx_SDMA_IRQ_BASE + MPC52xx_SDMA_IRQ_NUM)
> @@ -415,7 +415,7 @@ struct mpc52xx_cdm {
> #ifndef __ASSEMBLY__
>
> extern void mpc52xx_init_irq(void);
> -extern int mpc52xx_get_irq(void);
> +extern unsigned int mpc52xx_get_irq(void);
Yeah, you really shouldn't do this without fixing the arch/ppc side too.
g.
--
Grant Likely, B.Sc. P.Eng.
Secret Lab Technologies Ltd.
grant.likely@secretlab.ca
(403) 399-0195
^ permalink raw reply
* Re: [PATCH 2/3] Create compat_sys_migrate_pages
From: Christoph Lameter @ 2006-10-26 19:00 UTC (permalink / raw)
To: Stephen Rothwell; +Cc: linux-mm, ppc-dev, paulus, LKML, ak
In-Reply-To: <20061026133305.b0db54e6.sfr@canb.auug.org.au>
On Thu, 26 Oct 2006, Stephen Rothwell wrote:
> This is needed on bigendian 64bit architectures. The obvious way to do
> this (taking the other compat_ routines in this file as examples) is to
> use compat_alloc_user_space and copy the bitmasks back there, however you
> cannot call compat_alloc_user_space twice for a single system call and
> this method saves two copies of the bitmasks.
Well this means also that sys_mbind and sys_set_mempolicy are also
broken because these functions also use get_nodes().
Fixing get_nodes() to do the proper thing would fix all of these
without having to touch sys_migrate_pages or creating a compat_ function
(which usually is placed in kernel/compat.c)
^ permalink raw reply
* Re: Kernel hangs in console_init()
From: Scott Wood @ 2006-10-26 18:19 UTC (permalink / raw)
To: wei.li4; +Cc: linuxppc-embedded
In-Reply-To: <20061025173304.c57o9tf3go000wc0@webmail.mcgill.ca>
wei.li4@elf.mcgill.ca wrote:
> Hi All,
>
> I am working on linux 2.6.18-rc2 with my mpc875 demo board, I used
> Debugger LEDs to find that kernel stopped in:
> while (call < __con_initcall_end) {
> (*call)();
> call++;
> }
> which is in console_init() of tty_io.c, what kind of problem could be?
> What's the means of 'bctrl' instruction that I found in its assembler?
It's an indirect function call (i.e. the (*call)(); line) to the address
specified in the CTR register. You need to find out the value of *call
in order to figure out which function is failing. There are probably
only a small number of possibilities that are actually configured into
your kernel (look for console_initcall in files that get built for your
target).
-Scott
^ permalink raw reply
* Re: [PATCH] General CHRP/MPC5K2 platform support patch
From: Sylvain Munaut @ 2006-10-26 17:54 UTC (permalink / raw)
To: Nicolas DET; +Cc: akpm, sl, linuxppc-dev, linuxppc-embedded, sha
In-Reply-To: <4540EB0E.2090000@bplan-gmbh.de>
Hi Nicolas,
I don't have much to add to what's already been posted, so here's a
couple of details,
mainly compatibility concerns with the legacy arch/ppc tree.
>
> diff -uprN a/include/asm-ppc/mpc52xx.h b/include/asm-ppc/mpc52xx.h
> --- a/include/asm-ppc/mpc52xx.h 2006-10-25 19:07:48.000000000 +0200
> +++ b/include/asm-ppc/mpc52xx.h 2006-10-25 19:11:55.000000000 +0200
> @@ -119,7 +119,7 @@ enum ppc_sys_devices {
> #define MPC52xx_SDMA_IRQ_NUM 17
> #define MPC52xx_PERP_IRQ_NUM 23
>
> -#define MPC52xx_CRIT_IRQ_BASE 1
> +#define MPC52xx_CRIT_IRQ_BASE 0
As explained in IRC, I'm not sure about this.
I was previously talked into applying this to avoid using interrupt
number 0. In the LITE5200 IRQ0 is used for PCI. It's interrupt number
is equal to MPC52xx_CRIT_IRQ_BASE and if it's 0 some drivers just don't
work.
That's when using the arch/ppc code. Apparently this is no longer an
issue in arch/powerpc (someone to confirm and explain me why ? I would guess
the irq_linear_revmap thingie ), but can a "standard" lite5200 be booted
in a arch/powerpc kernel ?
So if no critical, I would postpone that change until it's confirmed
a lite5200 can boot ...
> -extern int mpc52xx_get_irq(void);
> +extern unsigned int mpc52xx_get_irq(void);
Mmmh, the one in arch/ppc is not unsigned but I guess the warning is fine.
Finally, some triviality : The patch adds some space on empty lines. Also,
the indentation is sometimes done with space and sometimes with space ...
Sylvain
^ permalink raw reply
* Re: [PATCH] General CHRP/MPC5K2 platform support patch
From: Sylvain Munaut @ 2006-10-26 17:33 UTC (permalink / raw)
To: John Rigby; +Cc: akpm, linuxppc-embedded, sl, linuxppc-dev, sha
In-Reply-To: <4b73d43f0610261017s38cdc78fn23ea07113bf8c0fc@mail.gmail.com>
John Rigby wrote:
>>
>> * mpc5k2_bestcomm.c (& helpers): I've been in contact with others people
>> using bestcomm and please to see the development was still active. I'm
>> already using latest code on my board but this is not include in this
>> patch. Indeed, it needs some changes for ARCH=powerpc. Moreover, we have
>> a different approach for the tasks. I'll be pleased to work with the
>> bestcomm folks.
>>
>
> So you preload the bestcomm task code in your boot loader? Do those
> of us using other bootloaders still have the option of loading the
> task code later in linux?
>
> What api are you using? Sylvain's proposed one based on Dale's with
> some additions from me? Or have you come up with your own?
>
Hi John,
I've sent him the latest API you describe.
As for task preloading, I'm not too sure what Nicolas' plan is. I'm
waiting to see
what he's proposing.
Since the bestcomm init is in a module, a different module could be
implemented,
(like bestcomm-chrp5k2.ko) that instead of clearing SRAM and doing
everything
from scrtch, would rely on the bootloader more. This would allow
"custom" tasks
to be marked as "don't touch". So if the bootloader want to load
something that
will not be altered by the linux driver (for whatever reason ...)
However, for the tasks like FEC and ATA and everything supported in the
kernel
natively, I would still recommend reload the task code (anyway the
driver is gonna
reset the task and everything ...) Trying to reuse the microcode loaded
by the
bootloader is not a great idea IMHO. (Imagine, the fec driver is changed
to use
the latest microcode, but the bootloader is not ... both have to be in
perfect sync ...)
We would still have to compare the internal FDT and the preloaded one
though since
they have to match ...
Sylvain
^ permalink raw reply
* Re: [PATCH] General CHRP/MPC5K2 platform support patch
From: Nicolas DET @ 2006-10-26 17:23 UTC (permalink / raw)
To: John Rigby; +Cc: akpm, sl, linuxppc-dev, linuxppc-embedded, sha
In-Reply-To: <4b73d43f0610261017s38cdc78fn23ea07113bf8c0fc@mail.gmail.com>
[-- Attachment #1: Type: text/plain, Size: 934 bytes --]
John Rigby wrote:
>>
>> * mpc5k2_bestcomm.c (& helpers): I've been in contact with others people
>> using bestcomm and please to see the development was still active. I'm
>> already using latest code on my board but this is not include in this
>> patch. Indeed, it needs some changes for ARCH=powerpc. Moreover, we have
>> a different approach for the tasks. I'll be pleased to work with the
>> bestcomm folks.
>>
>
> So you preload the bestcomm task code in your boot loader?
Yes.
>Do those
> of us using other bootloaders still have the option of loading the
> task code later in linux?
Well, just reading the phy address from 0xf008000 to 0xf00c0000 (if I
remenber correctly) should be enough to get the tasks code.
> What api are you using? Sylvain's proposed one based on Dale's with
> some additions from me? Or have you come up with your own?
>
We implemented our own yet. However, we could moved to any.
Regards,
[-- Attachment #2: nd.vcf --]
[-- Type: text/x-vcard, Size: 249 bytes --]
begin:vcard
fn:Nicolas DET ( bplan GmbH )
n:DET;Nicolas
org:bplan GmbH
adr:;;;;;;Germany
email;internet:nd@bplan-gmbh.de
title:Software Entwicklung
tel;work:+49 6171 9187 - 31
x-mozilla-html:FALSE
url:http://www.bplan-gmbh.de
version:2.1
end:vcard
^ permalink raw reply
* Re: [PATCH] General CHRP/MPC5K2 platform support patch
From: John Rigby @ 2006-10-26 17:17 UTC (permalink / raw)
To: Nicolas DET; +Cc: akpm, sl, linuxppc-dev, linuxppc-embedded, sha
In-Reply-To: <453FB582.20802@bplan-gmbh.de>
>
> * mpc5k2_bestcomm.c (& helpers): I've been in contact with others people
> using bestcomm and please to see the development was still active. I'm
> already using latest code on my board but this is not include in this
> patch. Indeed, it needs some changes for ARCH=powerpc. Moreover, we have
> a different approach for the tasks. I'll be pleased to work with the
> bestcomm folks.
>
So you preload the bestcomm task code in your boot loader? Do those
of us using other bootloaders still have the option of loading the
task code later in linux?
What api are you using? Sylvain's proposed one based on Dale's with
some additions from me? Or have you come up with your own?
^ permalink raw reply
* Re: Linux-2.6.x for TQM860L
From: Wolfgang Denk @ 2006-10-26 17:06 UTC (permalink / raw)
To: tran vanle; +Cc: linuxppc-embedded
In-Reply-To: <20061026095033.85887.qmail@web33012.mail.mud.yahoo.com>
Hello,
in message <20061026095033.85887.qmail@web33012.mail.mud.yahoo.com> you wrote:
>
> I have just read pages
> http://www.denx.de/wiki/Know/Linux24vs26 and i see you had build Linux-2.6.11.7 for TQM860L with instruction below
> Download Kernel Version 2.6.11.7 from kernel.org plus 8xx v2.6 TLB patch by Marcelo Tosatti (4 Apr 2005)
> Download config-2.6.11.7-TQM860L
> Build instruction
>
> -> export CROSS_COMPILE=ppc_8xx-
> -> cp ../config-2.6.11.7-TQM860L .config
> -> make ARCH=ppc CROSS_COMPILE=ppc_8xx- oldconfig
> -> time make -j8 ARCH=ppc CROSS_COMPILE=ppc_8xx- uImage
>
> I had done exactly these intruction but I received error
> Why? Had I missed another guide?
Did you use exact this kernel version, with Marcelo's patch applied,
with the provided configuration file?
Best regards,
Wolfgang Denk
--
Software Engineering: Embedded and Realtime Systems, Embedded Linux
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de
No one may kill a man. Not for any purpose. It cannot be condoned.
-- Kirk, "Spock's Brain", stardate 5431.6
^ permalink raw reply
* Re: [PATCH] General CHRP/MPC5K2 platform support patch
From: Nicolas DET @ 2006-10-26 17:06 UTC (permalink / raw)
To: Grant Likely; +Cc: akpm, sl, linuxppc-dev, linuxppc-embedded, sha
In-Reply-To: <528646bc0610260909x10c3b242i64387f576e625048@mail.gmail.com>
[-- Attachment #1: Type: text/plain, Size: 631 bytes --]
Grant Likely wrote:
> On 10/26/06, Grant Likely <grant.likely@secretlab.ca> wrote:
>> On 10/26/06, Nicolas DET <nd@bplan-gmbh.de> wrote:
>> > - chrp_find_openpic();
>> > - chrp_find_8259();
>> > +
>> > + if ( chrp_find_mpc52xx_pic() < 0)
>> > + {
>> > + chrp_find_openpic();
>> > + chrp_find_8259();
>> > + }
>>
>> Why? Why not just add the call to chrp_find_mpc52xx_pic() before or
>> after the other two chrp_find_ calls? Will calling them cause things
>> to break?
>>
As decided on the IRC channel. a patch which remove the check but fix
chrp_find_8259().
Regards,
[-- Attachment #2: chrpmpc52xx_2.6.19-rc3.patch --]
[-- Type: text/plain, Size: 15259 bytes --]
--- a/arch/powerpc/sysdev/Makefile 2006-10-25 19:07:24.000000000 +0200
+++ b/arch/powerpc/sysdev/Makefile 2006-10-26 11:38:02.000000000 +0200
@@ -13,6 +13,7 @@ obj-$(CONFIG_FSL_SOC) += fsl_soc.o
obj-$(CONFIG_PPC_TODC) += todc.o
obj-$(CONFIG_TSI108_BRIDGE) += tsi108_pci.o tsi108_dev.o
obj-$(CONFIG_QUICC_ENGINE) += qe_lib/
+obj-$(CONFIG_PPC_MPC52xx_PIC) += mpc52xx_pic.o
ifeq ($(CONFIG_PPC_MERGE),y)
obj-$(CONFIG_PPC_I8259) += i8259.o
--- a/arch/powerpc/sysdev/mpc52xx_pic.c 1970-01-01 01:00:00.000000000 +0100
+++ b/arch/powerpc/sysdev/mpc52xx_pic.c 2006-10-26 18:55:04.000000000 +0200
@@ -0,0 +1,368 @@
+/*
+ * arch/powerpc/sysdev/mpc52xx_pic.c
+ *
+ * Programmable Interrupt Controller functions for the Freescale MPC52xx
+ * embedded CPU.
+ *
+ * Maintainer : Sylvain Munaut <tnt@246tNt.com>
+ *
+ * Based on (well, mostly copied from) the code from the 2.4 kernel by
+ * Dale Farnsworth <dfarnsworth@mvista.com> and Kent Borg.
+ *
+ * Copyright (C) 2004 Sylvain Munaut <tnt@246tNt.com>
+ * Copyright (C) 2003 Montavista Software, Inc
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <linux/stddef.h>
+#include <linux/init.h>
+#include <linux/sched.h>
+#include <linux/signal.h>
+#include <linux/stddef.h>
+#include <linux/delay.h>
+#include <linux/irq.h>
+
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <asm/system.h>
+#include <asm/irq.h>
+#include <asm/prom.h>
+
+#include <asm/mpc52xx.h>
+
+static struct mpc52xx_intr __iomem *intr;
+static struct mpc52xx_sdma __iomem *sdma;
+
+static struct irq_host *mpc52xx_irqhost = NULL;
+
+static void
+mpc52xx_ic_disable(unsigned int virq)
+{
+ u32 val;
+ int irq;
+
+ irq = irq_map[virq].hwirq;
+
+ pr_debug("%s: irq=%d\n", __func__, irq);
+
+ if (irq == MPC52xx_IRQ0) {
+ val = in_be32(&intr->ctrl);
+ val &= ~(1 << 11);
+ out_be32(&intr->ctrl, val);
+ } else if (irq < MPC52xx_IRQ1) {
+ BUG();
+ } else if (irq <= MPC52xx_IRQ3) {
+ val = in_be32(&intr->ctrl);
+ val &= ~(1 << (10 - (irq - MPC52xx_IRQ1)));
+ out_be32(&intr->ctrl, val);
+ } else if (irq < MPC52xx_SDMA_IRQ_BASE) {
+ val = in_be32(&intr->main_mask);
+ val |= 1 << (16 - (irq - MPC52xx_MAIN_IRQ_BASE));
+ out_be32(&intr->main_mask, val);
+ } else if (irq < MPC52xx_PERP_IRQ_BASE) {
+ val = in_be32(&sdma->IntMask);
+ val |= 1 << (irq - MPC52xx_SDMA_IRQ_BASE);
+ out_be32(&sdma->IntMask, val);
+ } else {
+ val = in_be32(&intr->per_mask);
+ val |= 1 << (31 - (irq - MPC52xx_PERP_IRQ_BASE));
+ out_be32(&intr->per_mask, val);
+ }
+}
+
+static void
+mpc52xx_ic_enable(unsigned int virq)
+{
+ u32 val;
+ int irq;
+
+ irq = irq_map[virq].hwirq;
+
+ pr_debug("%s: irq=%d\n", __func__, irq);
+
+ if (irq == MPC52xx_IRQ0) {
+ val = in_be32(&intr->ctrl);
+ val |= 1 << 11;
+ out_be32(&intr->ctrl, val);
+ } else if (irq < MPC52xx_IRQ1) {
+ BUG();
+ } else if (irq <= MPC52xx_IRQ3) {
+ val = in_be32(&intr->ctrl);
+ val |= 1 << (10 - (irq - MPC52xx_IRQ1));
+ out_be32(&intr->ctrl, val);
+ } else if (irq < MPC52xx_SDMA_IRQ_BASE) {
+ val = in_be32(&intr->main_mask);
+ val &= ~(1 << (16 - (irq - MPC52xx_MAIN_IRQ_BASE)));
+ out_be32(&intr->main_mask, val);
+ } else if (irq < MPC52xx_PERP_IRQ_BASE) {
+ val = in_be32(&sdma->IntMask);
+ val &= ~(1 << (irq - MPC52xx_SDMA_IRQ_BASE));
+ out_be32(&sdma->IntMask, val);
+ } else {
+ val = in_be32(&intr->per_mask);
+ val &= ~(1 << (31 - (irq - MPC52xx_PERP_IRQ_BASE)));
+ out_be32(&intr->per_mask, val);
+ }
+}
+
+static void
+mpc52xx_ic_ack(unsigned int virq)
+{
+ u32 val;
+ int irq;
+
+ irq = irq_map[virq].hwirq;
+
+ pr_debug("%s: irq=%d\n", __func__, irq);
+
+ /*
+ * Only some irqs are reset here, others in interrupting hardware.
+ */
+
+ switch (irq) {
+ case MPC52xx_IRQ0:
+ val = in_be32(&intr->ctrl);
+ val |= 0x08000000;
+ out_be32(&intr->ctrl, val);
+ break;
+ case MPC52xx_CCS_IRQ:
+ val = in_be32(&intr->enc_status);
+ val |= 0x00000400;
+ out_be32(&intr->enc_status, val);
+ break;
+ case MPC52xx_IRQ1:
+ val = in_be32(&intr->ctrl);
+ val |= 0x04000000;
+ out_be32(&intr->ctrl, val);
+ break;
+ case MPC52xx_IRQ2:
+ val = in_be32(&intr->ctrl);
+ val |= 0x02000000;
+ out_be32(&intr->ctrl, val);
+ break;
+ case MPC52xx_IRQ3:
+ val = in_be32(&intr->ctrl);
+ val |= 0x01000000;
+ out_be32(&intr->ctrl, val);
+ break;
+ default:
+ if (irq >= MPC52xx_SDMA_IRQ_BASE
+ && irq < (MPC52xx_SDMA_IRQ_BASE + MPC52xx_SDMA_IRQ_NUM)) {
+ out_be32(&sdma->IntPend,
+ 1 << (irq - MPC52xx_SDMA_IRQ_BASE));
+ }
+
+ break;
+ }
+
+}
+
+static void
+mpc52xx_ic_disable_and_ack(unsigned int irq)
+{
+ mpc52xx_ic_disable(irq);
+ mpc52xx_ic_ack(irq);
+}
+
+static void
+mpc52xx_ic_end(unsigned int irq)
+{
+ if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
+ mpc52xx_ic_enable(irq);
+}
+
+static struct irq_chip mpc52xx_irqchip = {
+ .name = " MPC52xx ",
+ .enable = mpc52xx_ic_enable,
+ .disable = mpc52xx_ic_disable,
+ .ack = mpc52xx_ic_disable_and_ack,
+ .end = mpc52xx_ic_end,
+};
+
+
+extern struct device_node *find_mpc52xx_pic(void);
+static int mpc52xx_irqhost_match(struct irq_host *h, struct device_node *node)
+{
+ pr_debug("%s: %p vs %p\n", __func__, find_mpc52xx_pic(), node);
+ return find_mpc52xx_pic() == node;
+}
+
+static int mpc52xx_irqhost_xlate(struct irq_host *h, struct device_node *ct,
+ u32 *intspec, unsigned int intsize,
+ irq_hw_number_t *out_hwirq, unsigned int *out_flags)
+{
+ static unsigned char map_senses[4] = {
+ IRQ_TYPE_LEVEL_HIGH,
+ IRQ_TYPE_EDGE_FALLING,
+ IRQ_TYPE_EDGE_RISING,
+ IRQ_TYPE_LEVEL_LOW,
+ };
+
+ int intrvect_l1;
+ int intrvect_l2;
+ int intrvect_type;
+ int intrvect_linux;
+
+ pr_debug("%s:\n", __func__);
+
+ if (intsize!=3)
+ return -1;
+
+ intrvect_l1 = (int) intspec[0];
+ intrvect_l2 = (int) intspec[1];
+ intrvect_type = (int) intspec[2];
+
+ pr_debug("l1=%d, l2=%d, type=%d\n", intrvect_l1, intrvect_l2, intrvect_type );
+
+ switch(intrvect_l1) {
+ case 0: /* Critical */
+ intrvect_linux = MPC52xx_CRIT_IRQ_BASE;
+ break;
+
+ case 1: /* Main */
+ intrvect_linux = MPC52xx_MAIN_IRQ_BASE;
+ break;
+
+ case 2: /* Periph */
+ intrvect_linux = MPC52xx_PERP_IRQ_BASE;
+ break;
+
+ case 3: /* Bestcomm */
+ intrvect_linux = MPC52xx_SDMA_IRQ_BASE;
+ break;
+
+ default:
+ if ( printk_ratelimit() )
+ printk(KERN_ERR "Wrong L1 interrupt vector (%d)\n", intrvect_l1);
+
+ return -1;
+ }
+
+ intrvect_linux += intrvect_l2;
+
+ pr_debug("return %d\n", intrvect_linux);
+
+ *out_hwirq = intrvect_linux;
+ *out_flags = map_senses[intrvect_type];
+
+ return 0;
+
+}
+
+int mpc52xx_irqhost_map(struct irq_host *h, unsigned int virq, irq_hw_number_t hw)
+{
+ pr_debug("%s: v=%d, hw=%d\n", __func__, virq, (int) hw);
+
+ return 0;
+}
+
+void mpc52xx_irqhost_unmap(struct irq_host *h, unsigned int virq)
+{
+ pr_debug("%s: v=%d\n", __func__, virq);
+}
+
+static struct irq_host_ops mpc52xx_irqhost_ops = {
+ .match = mpc52xx_irqhost_match,
+ .xlate = mpc52xx_irqhost_xlate,
+ .map = mpc52xx_irqhost_map,
+ .unmap = mpc52xx_irqhost_unmap,
+};
+
+void __init
+mpc52xx_init_irq(void)
+{
+ int i;
+ u32 intr_ctrl;
+
+
+ /* Remap the necessary zones */
+ intr = ioremap(MPC52xx_PA(MPC52xx_INTR_OFFSET), MPC52xx_INTR_SIZE);
+ sdma = ioremap(MPC52xx_PA(MPC52xx_SDMA_OFFSET), MPC52xx_SDMA_SIZE);
+
+ if ((intr==NULL) || (sdma==NULL))
+ panic("Can't ioremap PIC/SDMA register or init_irq !");
+
+ /* Disable all interrupt sources. */
+ out_be32(&sdma->IntPend, 0xffffffff); /* 1 means clear pending */
+ out_be32(&sdma->IntMask, 0xffffffff); /* 1 means disabled */
+ out_be32(&intr->per_mask, 0x7ffffc00); /* 1 means disabled */
+ out_be32(&intr->main_mask, 0x00010fff); /* 1 means disabled */
+ intr_ctrl = in_be32(&intr->ctrl);
+ intr_ctrl &= 0x00ff0000; /* Keeps IRQ[0-3] config */
+ intr_ctrl |= 0x0f000000 | /* clear IRQ 0-3 */
+ 0x00001000 | /* MEE master external enable */
+ 0x00000000 | /* 0 means disable IRQ 0-3 */
+ 0x00000001; /* CEb route critical normally */
+ out_be32(&intr->ctrl, intr_ctrl);
+
+ /* Zero a bunch of the priority settings. */
+ out_be32(&intr->per_pri1, 0);
+ out_be32(&intr->per_pri2, 0);
+ out_be32(&intr->per_pri3, 0);
+ out_be32(&intr->main_pri1, 0);
+ out_be32(&intr->main_pri2, 0);
+ /* Initialize irq_desc[i].handler's with mpc52xx_ic. */
+ for (i = 0; i < NR_IRQS; i++) {
+ irq_desc[i].chip = &mpc52xx_irqchip;
+ irq_desc[i].status = IRQ_LEVEL;
+
+ }
+
+#define IRQn_MODE(intr_ctrl,irq) (((intr_ctrl) >> (22-(i<<1))) & 0x03)
+ for (i=0 ; i<4 ; i++) {
+ int mode;
+ mode = IRQn_MODE(intr_ctrl,i);
+ if ((mode == 0x1) || (mode == 0x2))
+ irq_desc[i?MPC52xx_IRQ1+i-1:MPC52xx_IRQ0].status = 0;
+ }
+
+ /*
+ * As last step, add an irq host to translate the real
+ * hw irq information provided by the ofw to linux virq
+ */
+
+ mpc52xx_irqhost = irq_alloc_host(IRQ_HOST_MAP_LINEAR, NR_IRQS, &mpc52xx_irqhost_ops, -1);
+ pr_debug("%s: mpc52xx_irqhost =%p\n", __func__, mpc52xx_irqhost );
+}
+
+unsigned int
+mpc52xx_get_irq(void)
+{
+ u32 status;
+ int virq;
+ int irq = NO_IRQ_IGNORE;
+
+ status = in_be32(&intr->enc_status);
+ if (status & 0x00000400)
+ { /* critical */
+ irq = (status >> 8) & 0x3;
+ if (irq == 2) /* high priority peripheral */
+ goto peripheral;
+ irq += MPC52xx_CRIT_IRQ_BASE;
+ } else if (status & 0x00200000)
+ { /* main */
+ irq = (status >> 16) & 0x1f;
+ if (irq == 4) /* low priority peripheral */
+ goto peripheral;
+ irq += MPC52xx_MAIN_IRQ_BASE;
+ } else if (status & 0x20000000)
+ { /* peripheral */
+peripheral:
+ irq = (status >> 24) & 0x1f;
+ if (irq == 0) { /* bestcomm */
+ status = in_be32(&sdma->IntPend);
+ irq = ffs(status) + MPC52xx_SDMA_IRQ_BASE-1;
+ } else
+ irq += MPC52xx_PERP_IRQ_BASE;
+
+ }
+
+ virq = irq_linear_revmap(mpc52xx_irqhost, irq);
+ pr_debug("%s: irq=%d -> %d\n", __func__, irq, virq);
+
+ return virq;
+}
+
--- a/arch/powerpc/Kconfig 2006-10-25 19:07:23.000000000 +0200
+++ b/arch/powerpc/Kconfig 2006-10-26 18:55:58.000000000 +0200
@@ -384,6 +384,11 @@ config PPC_CHRP
select PPC_RTAS
select PPC_MPC106
select PPC_UDBG_16550
+ select PPC_MPC52xx_PIC
+ default y
+
+config PPC_MPC52xx_PIC
+ bool
default y
config PPC_PMAC
--- a/arch/powerpc/platforms/chrp/setup.c 2006-10-25 19:07:23.000000000 +0200
+++ b/arch/powerpc/platforms/chrp/setup.c 2006-10-26 18:56:34.000000000 +0200
@@ -51,6 +51,7 @@
#include <asm/mpic.h>
#include <asm/rtas.h>
#include <asm/xmon.h>
+#include <asm/mpc52xx.h>
#include "chrp.h"
@@ -435,6 +436,51 @@ static struct irqaction xmon_irqaction =
};
#endif
+
+struct device_node *find_mpc52xx_pic(void)
+{
+ struct device_node *dev;
+ const char *piccompatible_list[] =
+ {
+ "mpc5200-interrupt-controller",
+ "mpc52xx-interrupt-controller",
+ "mpc52xx-pic",
+ "mpc5200-pic",
+ "5200-interrupt-controller",
+ "52xx-interrupt-controller",
+ "52xx-pic",
+ "5200-pic",
+ NULL
+ };
+
+ /* Look for an MPC52xx interrupt controller */
+ for_each_node_by_type(dev, "interrupt-controller")
+ {
+ const char **piccompatible_entry = piccompatible_list;
+
+ for(piccompatible_entry = piccompatible_list; *piccompatible_entry; piccompatible_entry++ )
+ {
+ if (device_is_compatible(dev, *piccompatible_entry ))
+ return dev;
+ }
+ }
+
+ return NULL;
+}
+
+static int __init chrp_find_mpc52xx_pic(void)
+{
+ if (find_mpc52xx_pic())
+ {
+ printk(KERN_INFO "Found MPC52xx Interrupt Controller\n");
+ ppc_md.get_irq = mpc52xx_get_irq;
+ mpc52xx_init_irq();
+ return 0;
+ }
+
+ return -ENODEV;
+}
+
static void __init chrp_find_8259(void)
{
struct device_node *np, *pic = NULL;
@@ -473,8 +519,11 @@ static void __init chrp_find_8259(void)
break;
}
if (np == NULL)
- printk(KERN_WARNING "Cannot find PCI interrupt acknowledge"
- " address, polling\n");
+ {
+ printk(KERN_WARNING "Cannot find PCI/i8259 interrupt acknowledge"
+ " Fix your tree!\n");
+ return;
+ }
i8259_init(pic, chrp_int_ack);
if (ppc_md.get_irq == NULL)
@@ -494,6 +543,8 @@ void __init chrp_init_IRQ(void)
#if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(XMON)
struct device_node *kbd;
#endif
+
+ chrp_find_mpc52xx_pic();
chrp_find_openpic();
chrp_find_8259();
diff -uprN a/include/asm-ppc/mpc52xx.h b/include/asm-ppc/mpc52xx.h
--- a/include/asm-ppc/mpc52xx.h 2006-10-25 19:07:48.000000000 +0200
+++ b/include/asm-ppc/mpc52xx.h 2006-10-25 19:11:55.000000000 +0200
@@ -119,7 +119,7 @@ enum ppc_sys_devices {
#define MPC52xx_SDMA_IRQ_NUM 17
#define MPC52xx_PERP_IRQ_NUM 23
-#define MPC52xx_CRIT_IRQ_BASE 1
+#define MPC52xx_CRIT_IRQ_BASE 0
#define MPC52xx_MAIN_IRQ_BASE (MPC52xx_CRIT_IRQ_BASE + MPC52xx_CRIT_IRQ_NUM)
#define MPC52xx_SDMA_IRQ_BASE (MPC52xx_MAIN_IRQ_BASE + MPC52xx_MAIN_IRQ_NUM)
#define MPC52xx_PERP_IRQ_BASE (MPC52xx_SDMA_IRQ_BASE + MPC52xx_SDMA_IRQ_NUM)
@@ -415,7 +415,7 @@ struct mpc52xx_cdm {
#ifndef __ASSEMBLY__
extern void mpc52xx_init_irq(void);
-extern int mpc52xx_get_irq(void);
+extern unsigned int mpc52xx_get_irq(void);
extern unsigned long mpc52xx_find_end_of_memory(void);
extern void mpc52xx_set_bat(void);
[-- Attachment #3: nd.vcf --]
[-- Type: text/x-vcard, Size: 249 bytes --]
begin:vcard
fn:Nicolas DET ( bplan GmbH )
n:DET;Nicolas
org:bplan GmbH
adr:;;;;;;Germany
email;internet:nd@bplan-gmbh.de
title:Software Entwicklung
tel;work:+49 6171 9187 - 31
x-mozilla-html:FALSE
url:http://www.bplan-gmbh.de
version:2.1
end:vcard
^ permalink raw reply
* Re: [PATCH] General CHRP/MPC5K2 platform support patch
From: Sven Luther @ 2006-10-26 16:45 UTC (permalink / raw)
To: Grant Likely; +Cc: akpm, linuxppc-embedded, sl, linuxppc-dev, sven, sha
In-Reply-To: <528646bc0610260902o4d4996a4i3dcf2a9b874037c7@mail.gmail.com>
On Thu, Oct 26, 2006 at 10:02:00AM -0600, Grant Likely wrote:
> >+config PPC_MPC52xx_PIC
> >+ bool
> >+ depends on PPC_CHRP
> > default y
>
> This isn't good for embedded 52xx boards. Anything u-boot based
> cannot be CHRP. Please drop the "depends on" line
This was a direct suggestion from benh, ppc_chrp should not be dropped, but
ored with whatever you are using, or somethiung like it.
Friendly,
Sven Luther
^ permalink raw reply
* Re: [PATCH] General CHRP/MPC5K2 platform support patch
From: Grant Likely @ 2006-10-26 16:09 UTC (permalink / raw)
To: Nicolas DET; +Cc: akpm, sl, linuxppc-dev, linuxppc-embedded, sha
In-Reply-To: <528646bc0610260902o4d4996a4i3dcf2a9b874037c7@mail.gmail.com>
On 10/26/06, Grant Likely <grant.likely@secretlab.ca> wrote:
> On 10/26/06, Nicolas DET <nd@bplan-gmbh.de> wrote:
> > - chrp_find_openpic();
> > - chrp_find_8259();
> > +
> > + if ( chrp_find_mpc52xx_pic() < 0)
> > + {
> > + chrp_find_openpic();
> > + chrp_find_8259();
> > + }
>
> Why? Why not just add the call to chrp_find_mpc52xx_pic() before or
> after the other two chrp_find_ calls? Will calling them cause things
> to break?
>
> Keep the code simple.
... as possible; but no simpler.
:)
g.
--
Grant Likely, B.Sc. P.Eng.
Secret Lab Technologies Ltd.
grant.likely@secretlab.ca
(403) 399-0195
^ permalink raw reply
* Re: [PATCH] General CHRP/MPC5K2 platform support patch
From: Grant Likely @ 2006-10-26 16:02 UTC (permalink / raw)
To: Nicolas DET; +Cc: akpm, sl, linuxppc-dev, linuxppc-embedded, sha
In-Reply-To: <4540B0A9.6070404@bplan-gmbh.de>
(minor) Whitespace is still inconsistent; mostly spaces used where
they should be tabs and a few lines longer than 80 chars. Running the
source through scripts/Lindent will help.
On 10/26/06, Nicolas DET <nd@bplan-gmbh.de> wrote:
> --- a/arch/powerpc/sysdev/mpc52xx_pic.c 2006-10-25 19:07:24.000000000 +0200
> +++ b/arch/powerpc/sysdev/mpc52xx_pic.c 2006-10-26 10:55:44.000000000 +0200
> @@ -0,0 +1,371 @@
> +/*
> + * arch/powerpc/sysdev/mpc52xx_pic.c
> + *
> + * Programmable Interrupt Controller functions for the Freescale MPC52xx
> + * embedded CPU.
> + * Modified for CHRP Efika 5K2
Don't really need to add the "Modified for.." line; That's what git is
for. Besides this code is modified for more than just the Efika now.
:)
> + *
> + * Maintainer : Sylvain Munaut <tnt@246tNt.com>
> + *
> + * Based on (well, mostly copied from) the code from the 2.4 kernel by
> + * Dale Farnsworth <dfarnsworth@mvista.com> and Kent Borg.
Ditto for this; but I know you didn't add it. :) Although this kind
of comment is more justified because it captures information not
maintained in git. (Namely where the original file came from.)
> + *
> + * Copyright (C) 2004 Sylvain Munaut <tnt@246tNt.com>
> + * Copyright (C) 2003 Montavista Software, Inc
You should add a bplan copyright line too.
> + *
> + * This file is licensed under the terms of the GNU General Public License
> + * version 2. This program is licensed "as is" without any warranty of any
> + * kind, whether express or implied.
> + */
> +
> +//#define DEBUG
C++ style comment bad. :)
> +
> +#include <linux/stddef.h>
> +#include <linux/init.h>
> +#include <linux/sched.h>
> +#include <linux/signal.h>
> +#include <linux/stddef.h>
> +#include <linux/delay.h>
> +#include <linux/irq.h>
> +
> +#include <asm/io.h>
> +#include <asm/processor.h>
> +#include <asm/system.h>
> +#include <asm/irq.h>
> +#include <asm/prom.h>
> +
> +#include <asm/mpc52xx.h>
> +
> +static struct mpc52xx_intr __iomem *intr;
> +static struct mpc52xx_sdma __iomem *sdma;
> +
> +static struct irq_host *mpc52xx_irqhost = NULL;
> +
(snip)
> --- a/arch/powerpc/Kconfig 2006-10-25 19:07:23.000000000 +0200
> +++ b/arch/powerpc/Kconfig 2006-10-26 11:32:54.000000000 +0200
> @@ -384,6 +384,12 @@ config PPC_CHRP
> select PPC_RTAS
> select PPC_MPC106
> select PPC_UDBG_16550
> + select PPC_MPC52xx_PIC
> + default y
> +
> +config PPC_MPC52xx_PIC
> + bool
> + depends on PPC_CHRP
> default y
This isn't good for embedded 52xx boards. Anything u-boot based
cannot be CHRP. Please drop the "depends on" line
> --- a/arch/powerpc/platforms/chrp/setup.c 2006-10-25 19:07:23.000000000 +0200
> +++ b/arch/powerpc/platforms/chrp/setup.c 2006-10-26 10:59:39.000000000 +0200
> @@ -51,6 +51,7 @@
> #include <asm/mpic.h>
> #include <asm/rtas.h>
> #include <asm/xmon.h>
> +#include <asm/mpc52xx.h>
>
> #include "chrp.h"
>
> @@ -435,6 +436,51 @@ static struct irqaction xmon_irqaction =
> };
> #endif
>
> +
> +struct device_node *find_mpc52xx_pic(void)
> +{
> + struct device_node *dev;
> + const char *piccompatible_list[] =
> + {
> + "mpc5200-interrupt-controller",
> + "mpc52xx-interrupt-controller",
> + "mpc52xx-pic",
> + "mpc5200-pic",
> + "5200-interrupt-controller",
> + "52xx-interrupt-controller",
> + "52xx-pic",
> + "5200-pic",
> + NULL
> + };
Considering Efika is the *only* CHRP 52xx board out there at the
moment, and only a handful of embedded folks trying to move it to
arch/powerpc, surely we can come to an agreement now on what this
thing is named. :)
Seriously, just recommend a name to use and everyone will use it.
Providing a list of names means that every name in your list will be
used.
> +
> + /* Look for an MPC52xx interrupt controller */
> + for_each_node_by_type(dev, "interrupt-controller")
> + {
> + const char **piccompatible_entry = piccompatible_list;
> +
> + for(piccompatible_entry = piccompatible_list; *piccompatible_entry; piccompatible_entry++ )
> + {
> + if (device_is_compatible(dev, *piccompatible_entry ))
> + return dev;
> + }
> + }
> +
> + return NULL;
> +}
> +
> +static int __init chrp_find_mpc52xx_pic(void)
> +{
> + if (find_mpc52xx_pic())
> + {
> + printk(KERN_INFO "Found MPC52xx Interrupt Controller\n");
> + ppc_md.get_irq = mpc52xx_get_irq;
> + mpc52xx_init_irq();
> + return 0;
> + }
> +
> + return -ENODEV;
> +}
> +
> static void __init chrp_find_8259(void)
> {
> struct device_node *np, *pic = NULL;
> @@ -494,8 +540,12 @@ void __init chrp_init_IRQ(void)
> #if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(XMON)
> struct device_node *kbd;
> #endif
> - chrp_find_openpic();
> - chrp_find_8259();
> +
> + if ( chrp_find_mpc52xx_pic() < 0)
> + {
> + chrp_find_openpic();
> + chrp_find_8259();
> + }
Why? Why not just add the call to chrp_find_mpc52xx_pic() before or
after the other two chrp_find_ calls? Will calling them cause things
to break?
Keep the code simple.
Cheers,
g.
--
Grant Likely, B.Sc. P.Eng.
Secret Lab Technologies Ltd.
grant.likely@secretlab.ca
(403) 399-0195
^ permalink raw reply
* xapp902 with 2.6.17 -- uartlite IRQ problems
From: robert corley @ 2006-10-26 14:51 UTC (permalink / raw)
To: David H. Lynch Jr.; +Cc: linux linuxppc-embedded
(original msg below)=0A=0ADavid;=0A=0AThe RS232 interrupt is currently usin=
g IRQ #1.=0A=0AI did a couple of things to verify interrupt generation and =
servicing:=0A1. Modified the uartlite isr to print a message every 128 i=
nterrupts (using the mod operator, etc.), and=0A2. Modified the xilinx d=
esign to push three signals out the ports for examination via an o-scope:=
=0A a. the RS232 interrupt to the PIC,=0A b. the PIC interrupt =
to the PPC405, and=0A c. the RS232 xmit output=0A=0AOn startup, I see=
a message from the uarlite ISR just once, as follows:=0A=0A---------------=
------------=0A[ 66.063011] ulite_startup: irq 1 allocated (int. counter =
=3D 0), resetting buffers...=0A[ 68.111531] ulite_startup: enabling inter=
rupts...=0A=0ABusyBox v1.00-pre9 (2004.04.18-19-[ 69.386364] Int. counter=
=3D 0=0A#=0A---------------------------=0A=0ABut no more after that...=0A=
=0AOddly enough, there weren't any interrupt signals from the PIC or UARTLI=
TE at any time.=0A=0AI will modify the isr to dump the PIC and UARTLITE reg=
isters. In addition, I will monitor =0Athe uartlite memory registers using=
XMD and see what I find.=0A=0AWhere is the code that enables the interrupt=
s on the Xilinx PIC?=0A=0A-cy=0A=0A----- Original Message ----=0AFrom: Davi=
d H. Lynch Jr. <dhlii@dlasys.net>=0ATo: robert corley <rdcorle@yahoo.com>=
=0ASent: Thursday, October 26, 2006 1:15:13 AM=0ASubject: Re: xapp902 with =
2.6.17 -- uartlite & ramdisk problems=0A=0Arobert corley wrote:=0A> David e=
t al;=0A>=0A> In my seemingly neverending effort to get linux up on the ML4=
03, I went the route David B. did and worked with the xapp902 reference des=
ing. I have met with a little success and appeal for some assistance...=0A=
>=0A> 1. The uart is dog slow. I suspect it has to do with interrupts =
(note the console dump below). I see this line:=0A>=0A> [ 2.637345]=
uartlite.0: ttyUL0 at MMIO 0xa0000000 (irq =3D =0A>=0A> and I think th=
at the interrupt isn't properly registered with the PIC. What do you think=
?=0A>=0A> 2. Can you look below and comment on the ram disk size? I am =
not sure what this value should be. My ramdisk=0A> image is 4658942 by=
tes. I recall reading somewhere that the value for the initrd ram disk sho=
uld be about 10k larger =0A> than the ramdisk size to allow for decompr=
ession. The # of pages and page size is throwing me off. Comments?=0A>=0A=
> -corley=0A> =0A I do not want to profess to be expert on the David B=
./Peter version =0Aof the UartLite driver. But I would guess UartLite inter=
rupts are not =0Aworking at all. What IRQ are you using ?=0A If it is IR=
Q 0 it is possible that it is being ignored =3D I had to =0Ajigger the code=
a bit because IRQ 0 is frequently used by Linux as no =0Airq, and on Xilin=
x (an possibly many ppc's) it is valid.=0A I made irq -1 the invalid irq=
and if you set the irq to -1 I use the =0Atimer.=0A=0A Adding timer dri=
ver I/O was fairly trivial - I am trying to put =0Atogether a patch for Dav=
id B./Peter's driver that does that.=0A The timer stuff is trivial. The =
problem is that Peters =0Atransmit/receive assume that they are only called=
when it is safe to =0Asend/receive - normal if driven by interrupts.=0A=0A=
But the advantage to polled serial ports is they pretty much always =0A=
work. I currently have some minor interrupt issues on my driver (of =0Acour=
se Peter's fails in the same way on my system), but=0A I do not have to =
sweat it because I can just ignore uartlite =0Ainterrupts and things work =
fine.=0A=0A Peter claims to be getting 1M xfers, that is probably not fe=
asible =0Awith polled IO.=0A=0A=0A =0A=0A=0A>=0A>=0A>=0A> =3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D console dump =3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=0A=
> [ 0.000000] Linux version 2.6.17.1 (rdcorle@athena) (gcc version 3.4.2=
) #2 Mon Oct 23 17:58:11 UTC 2006 =0A> [ 0.0000=
00] Xilinx ML403 Reference System (Virtex-4 FX) =
=0A> [ 0.000000] Built 1 zonelists =
=0A> [ 0.000000] Kernel command line: console=3D=
ttyUL0 single ip=3Doff root=3D/dev/ram rw =0A> [ 0.000000] Xilinx INTC #=
0 at 0xD1000FC0 mapped to 0xFDFFFFC0 =
=0A> [ 0.000000] PID hash table entries: 512 (o=
rder: 9, 2048 bytes) =
=0A> [ 0.000151] Console: colour dummy device 80x25 =
=0A> [ 0.000560] Dentry cache hash=
table entries: 8192 =0A=
> [ 0.001271] Inode-cache hash table entries: 4096 (order: 2, 16384 byte=
s) =
=0A> [ 0.013924] Memory: 58572k available (1348k kernel code, 344k dat=
a, 80k init, 0k highmem) =0A> [ 0.200435] Mount-cache hash ta=
ble entries: 512 =0A> [ =
0.203108] checking if image is initramfs...it isn't (no cpio magic); looks=
like an initrd =0A> [ 2.504612] Freeing initrd memory: 454=
9k freed =0A> [ 2.508719=
] NET: Registered protocol family 16 =
=0A> [ 2.518260] NET: Registered protocol family 2 =
=0A> [ 2.583989] IP route cache hash=
table entries: 51 =0A> [ =
2.584467] TCP established hash table entries: 2048 (order: 3, 32768 byte=
s) =
=0A> [ 2.584936] TCP bind hash table entries: 1024 (order: 2, 2048=
0 bytes) =
=0A> [ 2.585222] TCP: Hash tables configured (established 2048 bind=
1024) =
=0A> [ 2.585257] TCP reno registered =
=0A> [ 2.591657] io scheduler noop registered =
=0A> [ 2.591817] io scheduler anticipatory registered (d=
efault) =0A> [ =
2.591912] io scheduler deadline registered =
=0A> [ 2.592049] io scheduler cfq registered =
=0A> [ 2.637345] uartlite.0: ttyUL0 at MM=
IO 0xa0000000 (irq =3D =
=0A> [ 40.942337] RAMDISK driver initialized: 16 RAM disks of 4096K =
size 1024 block size =0A> [ 42.944862] eth%d: XTemac using sgDMA mode.=
=0A> [ 44.072738] eth%d: XT=
emac buffer_descriptor_space: phy: 0xbb8000, virt: 0xff1 00000, size: 0x500=
0 =0A> [ 46.424830] eth0: Xilinx TEMAC #0 at 0x60000000=
mapped to 0xC5008000, irq=3D0 =
=0A> [ 48.289878] mice: PS/2 mouse devic=
e common for all mice =
=0A> [ 49.694042] TCP bic registered =
=0A> [ 50.524157] RAMDISK: Compressed image found at block 0 =
=0A> [ 52.672304] RAMDISK: in=
complete write (-28 !=3D 3276 =
=0A> [ 56.000551] VFS: Mounted root (ext2 filesystem). =
=0A> [ 57.243671] Freeing unused ker=
nel memory: 80k init =
=0A> [ 58.579050] attempt to access beyond end of device =
=0A> [ 59.867968] ram0: rw=3D0, want=
=3D10018, limit=3D8192 =0A>=
[ 61.064912] Buffer I/O error on device ram0, logical block 5008 =
=0A> [ 62.65314=
9] attempt to access beyond end of device =
=0A> [ 63.942154] ram0: rw=3D0, want=3D10020, limit=3D=
8192 =0A> [ 65.139082] Bu=
ffer I/O error on device ram0, logical block 5009 =
=0A> [ 66.727305] attempt to acce=
ss beyond end of device =
=0A> [ 68.016306] ram0: rw=3D0, want=3D10022, limit=3D8192 =
=0A> [ 69.212688] BUG: soft lockup det=
ected on CPU#0! =0A> [ 6=
9.212711] Call Trace: =0A> [ 69.212733] [C024F78=
0] [C000906C] show_stack+0x48/0x194 (unreliable) =
=0A> [ 69.212808] [C024F7C0] =
[C0031874] softlockup_tick+0xb4/0xd0 =
=0A> [ 69.212853] [C024F7E0] [C001DDE8] run_local_=
timers+0x18/0x28 =
=0A> [ 69.212905] [C024F7F0] [C001DE70] update_process_times+0x78/0xb=
4 =0A> [ =
69.212956] [C024F810] [C00045B4] timer_interrupt+0xd4/0x204 =
=0A> [ 69.213000] [C024F=
850] [C000351C] ret_from_except+0x0/ =
=0A> [ 69.213043] [C024F910] [C0015A9C] release_console_=
sem+0xe0/0x284 =
=0A> [ 69.213105] [C024F950] [C0015DF4] vprintk+0x1b4/0x384 =
=0A> [ 69.213149] [C024F9=
F0] [C0016014] printk+0x50/0x60 =
=0A> [ 69.213189] [C024FA70] [C00B98DC] generic_make_request+0xc=
0/0x20c =
=0A> [ 69.213252] [C024FAB0] [C00B9AA8] submit_bio+0x80/0xd8 =
=0A> [ 69.213294] [C024FAF0] =
[C005602C] submit_bh+0x14c/0x1a0 =
=0A> [ 69.213342] [C024FB10] [C005854C] block_read_full_pa=
ge+0x310/0x328 =
=0A> [ 69.213391] [C024FB80] [C007D4FC] do_mpage_readpage+0x38c/0=
x538 =0A> =
[ 69.213437] [C024FC00] [C007D880] mpage_readpage+0x50/0x78 =
=0A> [ 69.213477] [C024FC5=
0] [C00B0120] ext2_readpage+0x1c/0x2c =
=0A> [ 69.213516] [C024FC60] [C0034824] read_cache_=
page+0xf8/0x208 =
=0A> [ 69.213562] [C024FC90] [C00AD490] ext2_get_page+0x24/0x308 =
=0A> [ 69.213623] =
[C024FCC0] [C00ADAE8] ext2_find_entry+0x7c/0x17c =0A> [ 6=
9.213663] [C024FD10] [C00ADC78] ext2_inode_by_name+0x18/0x58=0A> [ 69.213=
704] [C024FD30] [C00B191C] ext2_lookup+0x54/0xd8=0A> [ 69.213744] [C024FD=
50] [C0062E4C] do_lookup+0x138/0x19c=0A> [ 69.213793] [C024FD80] [C006391=
8] __link_path_walk+0x8f4/0x1014=0A> [ 69.213837] [C024FDD0] [C00640C0] l=
ink_path_walk+0x88/0x150=0A> [ 69.213879] [C024FE40] [C006432C] do_path_l=
ookup+0x1a4/0x2b8=0A> [ 69.213924] [C024FE70] [C006452C] __path_lookup_in=
tent_open+0x58/0xb8=0A> [ 69.213971] [C024FEA0] [C0064F14] open_namei+0x7=
0/0x6dc=0A> [ 69.214015] [C024FEE0] [C00519E4] do_filp_open+0x30/0x78=0A>=
[ 69.214056] [C024FF50] [C0051E04] do_sys_open+0x70/0x10c=0A> [ 69.214=
095] [C024FF80] [C0002618] init+0x274/0x2e0=0A> [ 69.214137] [C024FFF0] [=
C00051FC] kernel_thread+0x44/0x60=0A> [ 117.445261] Buffer I/O error on de=
vice ram0, logical block 5010=0A> [ 119.033233] attempt to access beyond e=
nd of device=0A> [ 120.322015] ram0: rw=3D0, want=3D10018, limit=3D8192=0A=
> [ 121.518738] Buffer I/O error on device ram0, logical block 5008=0A> [ =
123.106686] attempt to access beyond end of device=0A> [ 124.395468] ram0=
: rw=3D0, want=3D10020, limit=3D8192=0A> [ 125.592200] Buffer I/O error on=
device ram0, logical block 5009=0A> [ 127.180152] attempt to access beyon=
d end of device=0A> [ 128.468929] ram0: rw=3D0, want=3D10022, limit=3D8192=
=0A> [ 129.665650] Buffer I/O error on device ram0, logical block 5010=0A>=
[ 131.253675] attempt to access beyond end of device=0A> [ 132.542475] r=
am0: rw=3D0, want=3D100=0A>=0A>=0A> _______________________________________=
________=0A> Linuxppc-embedded mailing list=0A> Linuxppc-embedded@ozlabs.or=
g=0A> https://ozlabs.org/mailman/listinfo/linuxppc-embedded=0A> =0A=0A=0A=
-- =0ADave Lynch DLA Systems=0ASoftware Devel=
opment: Embedded Linux=0A717.627.3770 =
dhlii@dlasys.net http://www.dlasys.net=0Afax: 1.253.369.9244 =
Cell: 1.717.587.7774=0AOver 25 years' experience in platform=
s, languages, and technologies too numerous to list.=0A=0A"Any intelligent =
fool can make things bigger and more complex... It takes a touch of genius =
- and a lot of courage to move in the opposite direction."=0AAlbert Einstei=
n=0A=0A=0A=0A
^ permalink raw reply
* Re: [1/2] build failure for E500 CPUs w/ CONFIG_OPROFLE=y
From: Kumar Gala @ 2006-10-26 13:57 UTC (permalink / raw)
To: Vitaly Wool
Cc: linuxppc-dev list, oprofile-list,
linuxppc-embedded ((((E-Mail))))
In-Reply-To: <20061026104338.99e89782.vwool@ru.mvista.com>
On Oct 26, 2006, at 1:43 AM, Vitaly Wool wrote:
> Below is the patch for the problem described in "[0/2] build
> failure for 8540 w/ CONFIG_OPROFLE=y" letter representing the first
> approach. This approach is based on (pretty reasonable) assumption
> that op_model_7450.c is applicable only to 6XX, so let's compile it
> only when CONFIG_6XX==y. This results in more #ifdef's in arch/
> powerpc/oprofile/common.c, which doesn't look good to me. I'd
> rather "switch (cur_cpu_spec->oprofile_type) ..." to SoC-dependent
> header files arranging that one as static inline func...
>
> Anyway, here's the patch.
>
> arch/powerpc/oprofile/Makefile | 2 +-
> arch/powerpc/oprofile/common.c | 7 +++----
> 2 files changed, 4 insertions(+), 5 deletions(-)
>
> Signed-off-by: Vitaly Wool <vwool@ru.mvista.com>
This makes sense to me since we are just increasing kernel code size
for code we would never use for an FSL_BOOKE part if we do it the
other way. I dont think its that much more messy with the ifdef's.
If you want to do the other cleanup as well I've got no issue with
that, but we really should NOT build in support for 7450 into a
FSL_BOOKE kernel when reasonably avoidable.
- kumar
>
> Index: linux-2.6.18/arch/powerpc/oprofile/Makefile
> ===================================================================
> --- linux-2.6.18.orig/arch/powerpc/oprofile/Makefile
> +++ linux-2.6.18/arch/powerpc/oprofile/Makefile
> @@ -13,4 +13,4 @@ DRIVER_OBJS := $(addprefix ../../../driv
> oprofile-y := $(DRIVER_OBJS) common.o backtrace.o
> oprofile-$(CONFIG_PPC64) += op_model_rs64.o op_model_power4.o
> oprofile-$(CONFIG_FSL_BOOKE) += op_model_fsl_booke.o
> -oprofile-$(CONFIG_PPC32) += op_model_7450.o
> +oprofile-$(CONFIG_6XX) += op_model_7450.o
> Index: linux-2.6.18/arch/powerpc/oprofile/common.c
> ===================================================================
> --- linux-2.6.18.orig/arch/powerpc/oprofile/common.c
> +++ linux-2.6.18/arch/powerpc/oprofile/common.c
> @@ -135,19 +135,18 @@ int __init oprofile_arch_init(struct opr
> return -ENODEV;
>
> switch (cur_cpu_spec->oprofile_type) {
> -#ifdef CONFIG_PPC64
> +#if defined(CONFIG_PPC64)
> case PPC_OPROFILE_RS64:
> model = &op_model_rs64;
> break;
> case PPC_OPROFILE_POWER4:
> model = &op_model_power4;
> break;
> -#else
> +#elif defined (CONFIG_6XX)
> case PPC_OPROFILE_G4:
> model = &op_model_7450;
> break;
> -#endif
> -#ifdef CONFIG_FSL_BOOKE
> +#elif defined (CONFIG_FSL_BOOKE)
> case PPC_OPROFILE_BOOKE:
> model = &op_model_fsl_booke;
> break;
>
> _______________________________________________
> Linuxppc-embedded mailing list
> Linuxppc-embedded@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-embedded
^ permalink raw reply
* Re: [PATCH 2.6.19-rc3 2/2] ehea: 64K page support fix
From: Jan-Bernd Themann @ 2006-10-26 13:00 UTC (permalink / raw)
To: Anton Blanchard
Cc: Thomas Klein, Jeff Garzik, Jan-Bernd Themann, netdev,
linux-kernel, linux-ppc, Christoph Raisch, Marcus Eder
In-Reply-To: <20061025162126.GB25324@krispykreme>
Hi,
that is right, I'll send a new patch
Thanks,
Jan-Bernd
On Wednesday 25 October 2006 18:21, Anton Blanchard wrote:
>
> Hi,
>
> > +#ifdef CONFIG_PPC_64K_PAGES
> > + /* To support 64k pages we must round to 64k page boundary */
> > + epas->kernel.addr =
> > + ioremap((paddr_kernel & 0xFFFFFFFFFFFF0000), PAGE_SIZE) +
> > + (paddr_kernel & 0xFFFF);
> > +#else
> > epas->kernel.addr = ioremap(paddr_kernel, PAGE_SIZE);
> > +#endif
>
> Cant you just use PAGE_MASK, ~PAGE_MASK and remove the ifdefs
> completely?
>
> Anton
>
^ permalink raw reply
* [PATCH] 8xx: Fixed compile error
From: Kalle Pokki @ 2006-10-26 13:33 UTC (permalink / raw)
To: linuxppc-embedded, Paul Mackerras, Vitaly Bordug
Compilation fails in case of CONFIG_MTD_PARTITIONS && !CONFIG_MTD_PHYSMAP.
Also put board-specific definitions inside #ifdef.
Signed-off-by: Kalle Pokki <kalle.pokki@iki.fi>
---
arch/ppc/syslib/m8xx_setup.c | 6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/ppc/syslib/m8xx_setup.c b/arch/ppc/syslib/m8xx_setup.c
index 54303a7..7d3bf66 100644
--- a/arch/ppc/syslib/m8xx_setup.c
+++ b/arch/ppc/syslib/m8xx_setup.c
@@ -31,12 +31,10 @@ #include <linux/bootmem.h>
#include <linux/seq_file.h>
#include <linux/root_dev.h>
-#if defined(CONFIG_MTD) && defined(CONFIG_MTD_PHYSMAP)
#include <linux/mtd/partitions.h>
#include <linux/mtd/physmap.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/map.h>
-#endif
#include <asm/mmu.h>
#include <asm/reg.h>
@@ -53,6 +51,7 @@ #include <asm/ppc_sys.h>
#include "ppc8xx_pic.h"
+#if defined (CONFIG_MPC86XADS) || defined (CONFIG_MPC885ADS)
#ifdef CONFIG_MTD_PHYSMAP
#define MPC8xxADS_BANK_WIDTH 4
#endif
@@ -79,7 +78,8 @@ static struct mtd_partition mpc8xxads_pa
#define mpc8xxads_part_num (sizeof (mpc8xxads_partitions) / sizeof (mpc8xxads_partitions[0]))
-#endif
+#endif /* CONFIG_MTD_PARTITIONS */
+#endif /* CONFIG_MPC86XADS || CONFIG_MPC855ADS */
static int m8xx_set_rtc_time(unsigned long time);
static unsigned long m8xx_get_rtc_time(void);
--
1.4.1.1
^ permalink raw reply related
* Re: [PATCH] General CHRP/MPC5K2 platform support patch
From: Nicolas DET @ 2006-10-26 12:59 UTC (permalink / raw)
To: Benjamin Herrenschmidt
Cc: akpm, Sylvain Munaut, sl, linuxppc-dev, linuxppc-embedded, sha
In-Reply-To: <1161866964.27827.2.camel@localhost.localdomain>
[-- Attachment #1: Type: text/plain, Size: 364 bytes --]
Benjamin Herrenschmidt wrote:
>> rent patch, I know do:
>> mpc52xx_irqhost = irq_alloc_host(IRQ_HOST_MAP_LINEAR, NR_IRQS,
>> &mpc52xx_irqhost_ops, -1);
>>
>> Which should be ok.
>
> NR_IRQ, it's a bit violent :) It's also the max number of virtual IRQs
> and thus has nothing to do with your HW numbers. Use the max number of
> HW IRQs here.
>
> Ben.
>
>
>
[-- Attachment #2: chrpmpc52xx_2.6.19-rc3.patch --]
[-- Type: text/plain, Size: 15122 bytes --]
--- a/arch/powerpc/sysdev/Makefile 2006-10-25 19:07:24.000000000 +0200
+++ b/arch/powerpc/sysdev/Makefile 2006-10-26 11:38:02.000000000 +0200
@@ -13,6 +13,7 @@ obj-$(CONFIG_FSL_SOC) += fsl_soc.o
obj-$(CONFIG_PPC_TODC) += todc.o
obj-$(CONFIG_TSI108_BRIDGE) += tsi108_pci.o tsi108_dev.o
obj-$(CONFIG_QUICC_ENGINE) += qe_lib/
+obj-$(CONFIG_PPC_MPC52xx_PIC) += mpc52xx_pic.o
ifeq ($(CONFIG_PPC_MERGE),y)
obj-$(CONFIG_PPC_I8259) += i8259.o
--- a/arch/powerpc/sysdev/mpc52xx_pic.c 2006-10-25 19:07:24.000000000 +0200
+++ b/arch/powerpc/sysdev/mpc52xx_pic.c 2006-10-26 10:55:44.000000000 +0200
@@ -0,0 +1,371 @@
+/*
+ * arch/powerpc/sysdev/mpc52xx_pic.c
+ *
+ * Programmable Interrupt Controller functions for the Freescale MPC52xx
+ * embedded CPU.
+ * Modified for CHRP Efika 5K2
+ *
+ * Maintainer : Sylvain Munaut <tnt@246tNt.com>
+ *
+ * Based on (well, mostly copied from) the code from the 2.4 kernel by
+ * Dale Farnsworth <dfarnsworth@mvista.com> and Kent Borg.
+ *
+ * Copyright (C) 2004 Sylvain Munaut <tnt@246tNt.com>
+ * Copyright (C) 2003 Montavista Software, Inc
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+//#define DEBUG
+
+#include <linux/stddef.h>
+#include <linux/init.h>
+#include <linux/sched.h>
+#include <linux/signal.h>
+#include <linux/stddef.h>
+#include <linux/delay.h>
+#include <linux/irq.h>
+
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <asm/system.h>
+#include <asm/irq.h>
+#include <asm/prom.h>
+
+#include <asm/mpc52xx.h>
+
+static struct mpc52xx_intr __iomem *intr;
+static struct mpc52xx_sdma __iomem *sdma;
+
+static struct irq_host *mpc52xx_irqhost = NULL;
+
+static void
+mpc52xx_ic_disable(unsigned int virq)
+{
+ u32 val;
+ int irq;
+
+ irq = irq_map[virq].hwirq;
+
+ pr_debug("%s: irq=%d\n", __func__, irq);
+
+ if (irq == MPC52xx_IRQ0) {
+ val = in_be32(&intr->ctrl);
+ val &= ~(1 << 11);
+ out_be32(&intr->ctrl, val);
+ } else if (irq < MPC52xx_IRQ1) {
+ BUG();
+ } else if (irq <= MPC52xx_IRQ3) {
+ val = in_be32(&intr->ctrl);
+ val &= ~(1 << (10 - (irq - MPC52xx_IRQ1)));
+ out_be32(&intr->ctrl, val);
+ } else if (irq < MPC52xx_SDMA_IRQ_BASE) {
+ val = in_be32(&intr->main_mask);
+ val |= 1 << (16 - (irq - MPC52xx_MAIN_IRQ_BASE));
+ out_be32(&intr->main_mask, val);
+ } else if (irq < MPC52xx_PERP_IRQ_BASE) {
+ val = in_be32(&sdma->IntMask);
+ val |= 1 << (irq - MPC52xx_SDMA_IRQ_BASE);
+ out_be32(&sdma->IntMask, val);
+ } else {
+ val = in_be32(&intr->per_mask);
+ val |= 1 << (31 - (irq - MPC52xx_PERP_IRQ_BASE));
+ out_be32(&intr->per_mask, val);
+ }
+}
+
+static void
+mpc52xx_ic_enable(unsigned int virq)
+{
+ u32 val;
+ int irq;
+
+ irq = irq_map[virq].hwirq;
+
+ pr_debug("%s: irq=%d\n", __func__, irq);
+
+ if (irq == MPC52xx_IRQ0) {
+ val = in_be32(&intr->ctrl);
+ val |= 1 << 11;
+ out_be32(&intr->ctrl, val);
+ } else if (irq < MPC52xx_IRQ1) {
+ BUG();
+ } else if (irq <= MPC52xx_IRQ3) {
+ val = in_be32(&intr->ctrl);
+ val |= 1 << (10 - (irq - MPC52xx_IRQ1));
+ out_be32(&intr->ctrl, val);
+ } else if (irq < MPC52xx_SDMA_IRQ_BASE) {
+ val = in_be32(&intr->main_mask);
+ val &= ~(1 << (16 - (irq - MPC52xx_MAIN_IRQ_BASE)));
+ out_be32(&intr->main_mask, val);
+ } else if (irq < MPC52xx_PERP_IRQ_BASE) {
+ val = in_be32(&sdma->IntMask);
+ val &= ~(1 << (irq - MPC52xx_SDMA_IRQ_BASE));
+ out_be32(&sdma->IntMask, val);
+ } else {
+ val = in_be32(&intr->per_mask);
+ val &= ~(1 << (31 - (irq - MPC52xx_PERP_IRQ_BASE)));
+ out_be32(&intr->per_mask, val);
+ }
+}
+
+static void
+mpc52xx_ic_ack(unsigned int virq)
+{
+ u32 val;
+ int irq;
+
+ irq = irq_map[virq].hwirq;
+
+ pr_debug("%s: irq=%d\n", __func__, irq);
+
+ /*
+ * Only some irqs are reset here, others in interrupting hardware.
+ */
+
+ switch (irq) {
+ case MPC52xx_IRQ0:
+ val = in_be32(&intr->ctrl);
+ val |= 0x08000000;
+ out_be32(&intr->ctrl, val);
+ break;
+ case MPC52xx_CCS_IRQ:
+ val = in_be32(&intr->enc_status);
+ val |= 0x00000400;
+ out_be32(&intr->enc_status, val);
+ break;
+ case MPC52xx_IRQ1:
+ val = in_be32(&intr->ctrl);
+ val |= 0x04000000;
+ out_be32(&intr->ctrl, val);
+ break;
+ case MPC52xx_IRQ2:
+ val = in_be32(&intr->ctrl);
+ val |= 0x02000000;
+ out_be32(&intr->ctrl, val);
+ break;
+ case MPC52xx_IRQ3:
+ val = in_be32(&intr->ctrl);
+ val |= 0x01000000;
+ out_be32(&intr->ctrl, val);
+ break;
+ default:
+ if (irq >= MPC52xx_SDMA_IRQ_BASE
+ && irq < (MPC52xx_SDMA_IRQ_BASE + MPC52xx_SDMA_IRQ_NUM)) {
+ out_be32(&sdma->IntPend,
+ 1 << (irq - MPC52xx_SDMA_IRQ_BASE));
+ }
+
+ break;
+ }
+
+}
+
+static void
+mpc52xx_ic_disable_and_ack(unsigned int irq)
+{
+ mpc52xx_ic_disable(irq);
+ mpc52xx_ic_ack(irq);
+}
+
+static void
+mpc52xx_ic_end(unsigned int irq)
+{
+ if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
+ mpc52xx_ic_enable(irq);
+}
+
+static struct irq_chip mpc52xx_irqchip = {
+ .name = " MPC52xx ",
+ .enable = mpc52xx_ic_enable,
+ .disable = mpc52xx_ic_disable,
+ .ack = mpc52xx_ic_disable_and_ack,
+ .end = mpc52xx_ic_end,
+};
+
+
+extern struct device_node *find_mpc52xx_pic(void);
+static int mpc52xx_irqhost_match(struct irq_host *h, struct device_node *node)
+{
+ pr_debug("%s: %p vs %p\n", __func__, find_mpc52xx_pic(), node);
+ return find_mpc52xx_pic() == node;
+}
+
+static int mpc52xx_irqhost_xlate(struct irq_host *h, struct device_node *ct,
+ u32 *intspec, unsigned int intsize,
+ irq_hw_number_t *out_hwirq, unsigned int *out_flags)
+{
+ static unsigned char map_senses[4] = {
+ IRQ_TYPE_LEVEL_HIGH,
+ IRQ_TYPE_EDGE_FALLING,
+ IRQ_TYPE_EDGE_RISING,
+ IRQ_TYPE_LEVEL_LOW,
+ };
+
+ int intrvect_l1;
+ int intrvect_l2;
+ int intrvect_type;
+ int intrvect_linux;
+
+ pr_debug("%s:\n", __func__);
+
+ if (intsize!=3)
+ return -1;
+
+ intrvect_l1 = (int) intspec[0];
+ intrvect_l2 = (int) intspec[1];
+ intrvect_type = (int) intspec[2];
+
+ pr_debug("l1=%d, l2=%d, type=%d\n", intrvect_l1, intrvect_l2, intrvect_type );
+
+ switch(intrvect_l1) {
+ case 0: /* Critical */
+ intrvect_linux = MPC52xx_CRIT_IRQ_BASE;
+ break;
+
+ case 1: /* Main */
+ intrvect_linux = MPC52xx_MAIN_IRQ_BASE;
+ break;
+
+ case 2: /* Periph */
+ intrvect_linux = MPC52xx_PERP_IRQ_BASE;
+ break;
+
+ case 3: /* Bestcomm */
+ intrvect_linux = MPC52xx_SDMA_IRQ_BASE;
+ break;
+
+ default:
+ if ( printk_ratelimit() )
+ printk(KERN_ERR "Wrong L1 interrupt vector (%d)\n", intrvect_l1);
+
+ return -1;
+ }
+
+ intrvect_linux += intrvect_l2;
+
+ pr_debug("return %d\n", intrvect_linux);
+
+ *out_hwirq = intrvect_linux;
+ *out_flags = map_senses[intrvect_type];
+
+ return 0;
+
+}
+
+int mpc52xx_irqhost_map(struct irq_host *h, unsigned int virq, irq_hw_number_t hw)
+{
+ pr_debug("%s: v=%d, hw=%d\n", __func__, virq, (int) hw);
+
+ return 0;
+}
+
+void mpc52xx_irqhost_unmap(struct irq_host *h, unsigned int virq)
+{
+ pr_debug("%s: v=%d\n", __func__, virq);
+}
+
+static struct irq_host_ops mpc52xx_irqhost_ops = {
+ .match = mpc52xx_irqhost_match,
+ .xlate = mpc52xx_irqhost_xlate,
+ .map = mpc52xx_irqhost_map,
+ .unmap = mpc52xx_irqhost_unmap,
+};
+
+void __init
+mpc52xx_init_irq(void)
+{
+ int i;
+ u32 intr_ctrl;
+
+
+ /* Remap the necessary zones */
+ intr = ioremap(MPC52xx_PA(MPC52xx_INTR_OFFSET), MPC52xx_INTR_SIZE);
+ sdma = ioremap(MPC52xx_PA(MPC52xx_SDMA_OFFSET), MPC52xx_SDMA_SIZE);
+
+ if ((intr==NULL) || (sdma==NULL))
+ panic("Can't ioremap PIC/SDMA register or init_irq !");
+
+ /* Disable all interrupt sources. */
+ out_be32(&sdma->IntPend, 0xffffffff); /* 1 means clear pending */
+ out_be32(&sdma->IntMask, 0xffffffff); /* 1 means disabled */
+ out_be32(&intr->per_mask, 0x7ffffc00); /* 1 means disabled */
+ out_be32(&intr->main_mask, 0x00010fff); /* 1 means disabled */
+ intr_ctrl = in_be32(&intr->ctrl);
+ intr_ctrl &= 0x00ff0000; /* Keeps IRQ[0-3] config */
+ intr_ctrl |= 0x0f000000 | /* clear IRQ 0-3 */
+ 0x00001000 | /* MEE master external enable */
+ 0x00000000 | /* 0 means disable IRQ 0-3 */
+ 0x00000001; /* CEb route critical normally */
+ out_be32(&intr->ctrl, intr_ctrl);
+
+ /* Zero a bunch of the priority settings. */
+ out_be32(&intr->per_pri1, 0);
+ out_be32(&intr->per_pri2, 0);
+ out_be32(&intr->per_pri3, 0);
+ out_be32(&intr->main_pri1, 0);
+ out_be32(&intr->main_pri2, 0);
+ /* Initialize irq_desc[i].handler's with mpc52xx_ic. */
+ for (i = 0; i < NR_IRQS; i++) {
+ irq_desc[i].chip = &mpc52xx_irqchip;
+ irq_desc[i].status = IRQ_LEVEL;
+
+ }
+
+#define IRQn_MODE(intr_ctrl,irq) (((intr_ctrl) >> (22-(i<<1))) & 0x03)
+ for (i=0 ; i<4 ; i++) {
+ int mode;
+ mode = IRQn_MODE(intr_ctrl,i);
+ if ((mode == 0x1) || (mode == 0x2))
+ irq_desc[i?MPC52xx_IRQ1+i-1:MPC52xx_IRQ0].status = 0;
+ }
+
+ /*
+ * As last step, add an irq host to translate the real
+ * hw irq information provided by the ofw to linux virq
+ */
+
+ mpc52xx_irqhost = irq_alloc_host(IRQ_HOST_MAP_LINEAR, MPC52xx_BDLC_IRQ+1, &mpc52xx_irqhost_ops, -1);
+ pr_debug("%s: mpc52xx_irqhost =%p\n", __func__, mpc52xx_irqhost );
+}
+
+unsigned int
+mpc52xx_get_irq(void)
+{
+ u32 status;
+ int virq;
+ int irq = NO_IRQ_IGNORE;
+
+ status = in_be32(&intr->enc_status);
+ if (status & 0x00000400)
+ { /* critical */
+ irq = (status >> 8) & 0x3;
+ if (irq == 2) /* high priority peripheral */
+ goto peripheral;
+ irq += MPC52xx_CRIT_IRQ_BASE;
+ } else if (status & 0x00200000)
+ { /* main */
+ irq = (status >> 16) & 0x1f;
+ if (irq == 4) /* low priority peripheral */
+ goto peripheral;
+ irq += MPC52xx_MAIN_IRQ_BASE;
+ } else if (status & 0x20000000)
+ { /* peripheral */
+peripheral:
+ irq = (status >> 24) & 0x1f;
+ if (irq == 0) { /* bestcomm */
+ status = in_be32(&sdma->IntPend);
+ irq = ffs(status) + MPC52xx_SDMA_IRQ_BASE-1;
+ } else
+ irq += MPC52xx_PERP_IRQ_BASE;
+
+ }
+
+ virq = irq_linear_revmap(mpc52xx_irqhost, irq);
+ pr_debug("%s: irq=%d -> %d\n", __func__, irq, virq);
+
+ return virq;
+}
+
--- a/arch/powerpc/Kconfig 2006-10-25 19:07:23.000000000 +0200
+++ b/arch/powerpc/Kconfig 2006-10-26 11:32:54.000000000 +0200
@@ -384,6 +384,12 @@ config PPC_CHRP
select PPC_RTAS
select PPC_MPC106
select PPC_UDBG_16550
+ select PPC_MPC52xx_PIC
+ default y
+
+config PPC_MPC52xx_PIC
+ bool
+ depends on PPC_CHRP
default y
config PPC_PMAC
--- a/arch/powerpc/platforms/chrp/setup.c 2006-10-25 19:07:23.000000000 +0200
+++ b/arch/powerpc/platforms/chrp/setup.c 2006-10-26 10:59:39.000000000 +0200
@@ -51,6 +51,7 @@
#include <asm/mpic.h>
#include <asm/rtas.h>
#include <asm/xmon.h>
+#include <asm/mpc52xx.h>
#include "chrp.h"
@@ -435,6 +436,51 @@ static struct irqaction xmon_irqaction =
};
#endif
+
+struct device_node *find_mpc52xx_pic(void)
+{
+ struct device_node *dev;
+ const char *piccompatible_list[] =
+ {
+ "mpc5200-interrupt-controller",
+ "mpc52xx-interrupt-controller",
+ "mpc52xx-pic",
+ "mpc5200-pic",
+ "5200-interrupt-controller",
+ "52xx-interrupt-controller",
+ "52xx-pic",
+ "5200-pic",
+ NULL
+ };
+
+ /* Look for an MPC52xx interrupt controller */
+ for_each_node_by_type(dev, "interrupt-controller")
+ {
+ const char **piccompatible_entry = piccompatible_list;
+
+ for(piccompatible_entry = piccompatible_list; *piccompatible_entry; piccompatible_entry++ )
+ {
+ if (device_is_compatible(dev, *piccompatible_entry ))
+ return dev;
+ }
+ }
+
+ return NULL;
+}
+
+static int __init chrp_find_mpc52xx_pic(void)
+{
+ if (find_mpc52xx_pic())
+ {
+ printk(KERN_INFO "Found MPC52xx Interrupt Controller\n");
+ ppc_md.get_irq = mpc52xx_get_irq;
+ mpc52xx_init_irq();
+ return 0;
+ }
+
+ return -ENODEV;
+}
+
static void __init chrp_find_8259(void)
{
struct device_node *np, *pic = NULL;
@@ -494,8 +540,12 @@ void __init chrp_init_IRQ(void)
#if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(XMON)
struct device_node *kbd;
#endif
- chrp_find_openpic();
- chrp_find_8259();
+
+ if ( chrp_find_mpc52xx_pic() < 0)
+ {
+ chrp_find_openpic();
+ chrp_find_8259();
+ }
#ifdef CONFIG_SMP
/* Pegasos has no MPIC, those ops would make it crash. It might be an
diff -uprN a/include/asm-ppc/mpc52xx.h b/include/asm-ppc/mpc52xx.h
--- a/include/asm-ppc/mpc52xx.h 2006-10-25 19:07:48.000000000 +0200
+++ b/include/asm-ppc/mpc52xx.h 2006-10-25 19:11:55.000000000 +0200
@@ -119,7 +119,7 @@ enum ppc_sys_devices {
#define MPC52xx_SDMA_IRQ_NUM 17
#define MPC52xx_PERP_IRQ_NUM 23
-#define MPC52xx_CRIT_IRQ_BASE 1
+#define MPC52xx_CRIT_IRQ_BASE 0
#define MPC52xx_MAIN_IRQ_BASE (MPC52xx_CRIT_IRQ_BASE + MPC52xx_CRIT_IRQ_NUM)
#define MPC52xx_SDMA_IRQ_BASE (MPC52xx_MAIN_IRQ_BASE + MPC52xx_MAIN_IRQ_NUM)
#define MPC52xx_PERP_IRQ_BASE (MPC52xx_SDMA_IRQ_BASE + MPC52xx_SDMA_IRQ_NUM)
@@ -415,7 +415,7 @@ struct mpc52xx_cdm {
#ifndef __ASSEMBLY__
extern void mpc52xx_init_irq(void);
-extern int mpc52xx_get_irq(void);
+extern unsigned int mpc52xx_get_irq(void);
extern unsigned long mpc52xx_find_end_of_memory(void);
extern void mpc52xx_set_bat(void);
[-- Attachment #3: nd.vcf --]
[-- Type: text/x-vcard, Size: 249 bytes --]
begin:vcard
fn:Nicolas DET ( bplan GmbH )
n:DET;Nicolas
org:bplan GmbH
adr:;;;;;;Germany
email;internet:nd@bplan-gmbh.de
title:Software Entwicklung
tel;work:+49 6171 9187 - 31
x-mozilla-html:FALSE
url:http://www.bplan-gmbh.de
version:2.1
end:vcard
^ permalink raw reply
* Re: [PATCH] General CHRP/MPC5K2 platform support patch
From: Benjamin Herrenschmidt @ 2006-10-26 12:51 UTC (permalink / raw)
To: Nicolas DET; +Cc: akpm, sl, linuxppc-dev, linuxppc-embedded, sha
In-Reply-To: <4540A4EF.5030802@bplan-gmbh.de>
On Thu, 2006-10-26 at 14:09 +0200, Nicolas DET wrote:
> What do you mean exactly by 'the IPB freq should be in the device-tree'?
> It is as property.
Yeah, just that drivers should pick it up from there
Ben.
^ permalink raw reply
* Re: [PATCH] General CHRP/MPC5K2 platform support patch
From: Benjamin Herrenschmidt @ 2006-10-26 12:49 UTC (permalink / raw)
To: Nicolas DET
Cc: akpm, Sylvain Munaut, sl, linuxppc-dev, linuxppc-embedded, sha
In-Reply-To: <45409760.7030902@bplan-gmbh.de>
> rent patch, I know do:
> mpc52xx_irqhost = irq_alloc_host(IRQ_HOST_MAP_LINEAR, NR_IRQS,
> &mpc52xx_irqhost_ops, -1);
>
> Which should be ok.
NR_IRQ, it's a bit violent :) It's also the max number of virtual IRQs
and thus has nothing to do with your HW numbers. Use the max number of
HW IRQs here.
Ben.
^ permalink raw reply
* Re: [PATCH] General CHRP/MPC5K2 platform support patch
From: Nicolas DET @ 2006-10-26 12:09 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: akpm, sl, linuxppc-dev, linuxppc-embedded, sha
In-Reply-To: <1161817576.22582.142.camel@localhost.localdomain>
[-- Attachment #1: Type: text/plain, Size: 586 bytes --]
Benjamin Herrenschmidt wrote:
>>> * serial stuff / IBP Freq. As this frequency is MPC52xx specific. I
>>> think it would make sense to add a new func mpc52xx_getipbfreq(void).
>>> The way it would be implemented may depend of the architecture. Our
>>> firmware contains an 'ipb-freq' property in '/builtin/'.
>
> BTW. I forgot to comment on the above in my previous mail... As I said,
> there should be no such thing. Instead, the IPB freq should be in the
> device-tree.
>
>
>
What do you mean exactly by 'the IPB freq should be in the device-tree'?
It is as property.
Regards
[-- Attachment #2: nd.vcf --]
[-- Type: text/x-vcard, Size: 249 bytes --]
begin:vcard
fn:Nicolas DET ( bplan GmbH )
n:DET;Nicolas
org:bplan GmbH
adr:;;;;;;Germany
email;internet:nd@bplan-gmbh.de
title:Software Entwicklung
tel;work:+49 6171 9187 - 31
x-mozilla-html:FALSE
url:http://www.bplan-gmbh.de
version:2.1
end:vcard
^ permalink raw reply
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