* Re: [PATCH 1/2] Add MPC52xx Interrupt controller support for ARCH=powerpc
From: Benjamin Herrenschmidt @ 2006-10-31 9:07 UTC (permalink / raw)
To: Nicolas DET; +Cc: linuxppc-dev, sl, sha, linuxppc-embedded
In-Reply-To: <4547119C.3060208@bplan-gmbh.de>
On Tue, 2006-10-31 at 10:04 +0100, Nicolas DET wrote:
> Benjamin Herrenschmidt wrote:
> >> In my point of view, the Firmware main task is to init the HW. I do not
> >> think it's a good idea to overwrite firmware hw settings in the common
> >> code. In my mind, this should be done in platform specific area.
> >
> > The setting of interrupt polarity is a matter that is at the edge
> > between firmware and OS responsibility. Remember that a lot of embedded
> > platforms have close to no useful firmware too.
> >
>
> Ok. that's why I suggest to keep buggy (or none) firmware board in
> platform specific code.
Well, in that case, we have a well defined interface to set the sense
code, via the device-tree, and that's much better than having platform
code muck around the PIC hardware separately from the PIC driver don't
you think ?
Anyway, that's the way it works in Linux/powerpc so there is no need
debating that for ever. Just be aware that at one point, there will be a
set_type() implementation in this driver and that it will be called
based on the polarity information in the device-tree so make sure you
got it right.
> > Of course, if your device-tree has bugs, then adding that feature
> > afterward will suddenly break efika ...
> >
>
> Our OpenFirmware is, of course, bugfree ;-)
:)
Ben.
^ permalink raw reply
* Re: [PATCH 1/2] Add MPC52xx Interrupt controller support for ARCH=powerpc
From: Nicolas DET @ 2006-10-31 9:08 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev, sl, sha, linuxppc-embedded
In-Reply-To: <1162284176.25682.320.camel@localhost.localdomain>
[-- Attachment #1: Type: text/plain, Size: 1263 bytes --]
Benjamin Herrenschmidt wrote:
> On Tue, 2006-10-31 at 09:25 +0100, Nicolas DET wrote:
>
>> Ok. By the way, the mbar is include as property in our OpenFrimware.
>> Moreover, the G2CORE CPU has a new SPR 'MBAR' which is the MBAR ;-). It
>> would maybe make sense to create a new file
>> (arch/powerpc/sysdev/mpc52xx.c) which would contain chip specific code.
>>
>> Like mpc52xx_get_mbar(), mpc52xx_get_ipbfreq(), etc...
>>
>> I updated a bit the patches. I applied Dale requests.
>> My kernel still compiles and boots. ;-)
>>
>> Should I post the new patches?
>
> Sure.
>
Ok. Should be done this morning.
>> About the headers thingy. Should I split them directly in the patch, or
>> this should be done by others later on?
>
> Don't bother that much about splitting the headers. I personally don't
> mind.
>
Ok. so I keep everything in include/asm-powerpc/mpc52xx.h for now.
>> About the serials and USB part. Have anyone already do some work (moving
>> to of_platform, etc...)?
>
> I think Grant has.
>
Ok.
>> As far as I see, the Efika platform patch did not get any comment,
>> should I assume it is good enough for inclusion in the main stream kernel?
>
> It looked ok at a very very quick glance. I'll give a better look.
>
Ok.
Regards,
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^ permalink raw reply
* Re: [PATCH 1/2] Add MPC52xx Interrupt controller support for ARCH=powerpc
From: Nicolas DET @ 2006-10-31 9:46 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev, sl, sha, linuxppc-embedded
In-Reply-To: <1162285628.25682.326.camel@localhost.localdomain>
[-- Attachment #1: Type: text/plain, Size: 1000 bytes --]
Benjamin Herrenschmidt wrote:
>> Ok. that's why I suggest to keep buggy (or none) firmware board in
>> platform specific code.
>
> Well, in that case, we have a well defined interface to set the sense
> code, via the device-tree, and that's much better than having platform
> code muck around the PIC hardware separately from the PIC driver don't
> you think ?
>
> Anyway, that's the way it works in Linux/powerpc so there is no need
> debating that for ever. Just be aware that at one point, there will be a
> set_type() implementation in this driver and that it will be called
> based on the polarity information in the device-tree so make sure you
> got it right.
>
Ok. set_type() is scheduled for later on or should it be included right now?
What's next should be done to finally acked the driver?
>>> Of course, if your device-tree has bugs, then adding that feature
>>> afterward will suddenly break efika ...
>>>
>> Our OpenFirmware is, of course, bugfree ;-)
>
> :)
>
You doubt? ;-)
[-- Attachment #2: nd.vcf --]
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begin:vcard
fn:Nicolas DET ( bplan GmbH )
n:DET;Nicolas
org:bplan GmbH
adr:;;;;;;Germany
email;internet:nd@bplan-gmbh.de
title:Software Entwicklung
tel;work:+49 6171 9187 - 31
x-mozilla-html:FALSE
url:http://www.bplan-gmbh.de
version:2.1
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^ permalink raw reply
* Re: glibc-2.5 test suite hangs/crashes the machine
From: Fabio Massimo Di Nitto @ 2006-10-31 9:47 UTC (permalink / raw)
To: Benjamin Herrenschmidt
Cc: linuxppc-dev, Jeff Bailey, Paul Mackerras, Ben Collins
In-Reply-To: <1162240610.25682.182.camel@localhost.localdomain>
Benjamin Herrenschmidt wrote:
> On Mon, 2006-10-30 at 12:35 +0100, Fabio Massimo Di Nitto wrote:
>> Benjamin Herrenschmidt wrote:
>>> Does that patch fixes it ?
>>>
>> tested with kernel .17 and headers from .19 and the build hangs. Still tons of
>> Zl processes around.
>>
>> On the note building with kernel .19 and .19 headers it all goes smooth.
>
> Ok, so there's a different issue from what I've found. You haven't by
> chance noted what those processes are (which test case typically) ?
> Also, there's a sysrq to get a backtrace of all pending processes,
> though I don't remember which one off the top of my mind, might be
> useful to have a look though.
>
> Ben.
>
After discussing with Ben on IRC i applied 69588298188b40ed7f75c98a6fd328d82f23ca21
to kernel .17 and glibc does build without zombie processes and no hang whatsoever.
I suggest to push this patch back to the stable kernel trees.
Fabio
--
I'm going to make him an offer he can't refuse.
^ permalink raw reply
* [PATCH 1/2] qe_lib: qe_issue_cmd writes wrong value to CECDR
From: Li Yang @ 2006-10-31 9:53 UTC (permalink / raw)
To: Paul; +Cc: linuxppc-dev
From: Timur Tabi <timur@freescale.com>
Changed qe_issue_cmd() to write cmd_input to the CECDR unmodified. It
was treating cmd_input as a virtual address and tried to convert it to
a physical address.
Signed-off-by: Timur Tabi <timur@freescale.com>
---
diff --git a/arch/powerpc/sysdev/qe_lib/qe.c b/arch/powerpc/sysdev/qe_lib/qe.c
index 2bae632..e422322 100644
--- a/arch/powerpc/sysdev/qe_lib/qe.c
+++ b/arch/powerpc/sysdev/qe_lib/qe.c
@@ -122,8 +122,7 @@ int qe_issue_cmd(u32 cmd, u32 device, u8
mcn_shift = QE_CR_MCN_NORMAL_SHIFT;
}
- out_be32(&qe_immr->cp.cecdr,
- immrbar_virt_to_phys((void *)cmd_input));
+ out_be32(&qe_immr->cp.cecdr, cmd_input);
out_be32(&qe_immr->cp.cecr,
(cmd | QE_CR_FLG | ((u32) device << dev_shift) | (u32)
mcn_protocol << mcn_shift));
^ permalink raw reply related
* [PATCH 2/2] qe_lib: Remove immrbar_virt_to_phys() function
From: Li Yang @ 2006-10-31 9:53 UTC (permalink / raw)
To: Paul; +Cc: linuxppc-dev
Remove private address mapping function immrbar_virt_to_phys() as it can be
replaced by kernel generic API like iopa(). iopa() had problem dealing with
area mapped by io_block_mapping(). It's now working as all io spaces are mapped
by ioremap(). Users of this function should change to use generic functions.
Signed-off-by: Li Yang <leoli@freescale.com>
---
diff --git a/include/asm-powerpc/immap_qe.h b/include/asm-powerpc/immap_qe.h
index ce12f85..7cccd16 100644
--- a/include/asm-powerpc/immap_qe.h
+++ b/include/asm-powerpc/immap_qe.h
@@ -464,14 +464,5 @@ struct qe_immap {
extern struct qe_immap *qe_immr;
extern phys_addr_t get_qe_base(void);
-static inline unsigned long immrbar_virt_to_phys(volatile void * address)
-{
- if ( ((u32)address >= (u32)qe_immr) &&
- ((u32)address < ((u32)qe_immr + QE_IMMAP_SIZE)) )
- return (unsigned long)(address - (u32)qe_immr +
- (u32)get_qe_base());
- return (unsigned long)virt_to_phys(address);
-}
-
#endif /* __KERNEL__ */
#endif /* _ASM_POWERPC_IMMAP_QE_H */
^ permalink raw reply related
* Re: [PATCH] CPM_UART: Fix non-console transmit
From: Laurent Pinchart @ 2006-10-31 10:24 UTC (permalink / raw)
To: linuxppc-embedded; +Cc: Boris Shteinbock
In-Reply-To: <a425f86c0610191207i3a9977c9ree3f66cbfb52950e@mail.gmail.com>
> > After applying your patch,
> > the transmission doesn't take place at all..
> > just hanging in write...
> > at least it is possible to exit the program.
>
> That's strange. No matter how I test the driver it now works
> perfectly for me with my patches.
Ditto. Your patch fixed my problems. I'd like to see a fix (either this one or
another one, there are different solutions) pushed upstream soon, as the
problem is quite serious. I'm quite amazed nobody had ever reported it
before.
> Did you apply them both?
I only applied [PATCH] CPM_UART: Fix non-console transmit
> However, I cannot see why the length of the transmission would cause any
> difference.
>
> What is you baud rate on SMC2? How about the TX buffer count and TX
> FIFO size - have you changed them? I suspect that cpm_uart_tx_pump()
> could disable your TX interrupt when you have all characters queued in
> separate TX buffers. I'll test this theory tomorrow.
>
> You might want to strace your program and post the results here. Also put
>
> #define DEBUG
>
> in front of cpm_uart_core.c and cpm_uart_cpm2.c and recompile. You'll
> get a lot of debugging messages after
>
> echo 8 > /proc/sys/kernel/printk
>
> That should give us clues what goes wrong. The output of
>
> stty -F /dev/ttyCPM1 -a
>
> would also help.
Cheers,
Laurent Pinchart
^ permalink raw reply
* Re: [RFC] Fix for interrupt distribution
From: Mohan Kumar M @ 2006-10-31 11:05 UTC (permalink / raw)
To: Nathan Lynch; +Cc: linuxppc-dev, fastboot, anton
In-Reply-To: <20061030181751.GI17168@localdomain>
On Mon, Oct 30, 2006 at 12:17:51PM -0600, Nathan Lynch wrote:
> Mohan Kumar M wrote:
> > Hello,
> >
> > When kdump kernel is booted with the parameter "maxcpus=1" on a threaded
> > CPU, we faced some interrupt routing problems.
> >
> > In the xics initialization code, "reg" property in each cpu node
> > (device-tree/cpus/PowerPC,POWER5@x) is used to match the current boot
> > cpu id and based on that "default_server" and "default_distrib_server"
> > are calculated. This condition will always meet when OF chooses CPU0 as
> > boot cpu or crash happenes on any cpu whose id is any physical cpu id.
> >
> > The "reg" property in cpu node gives the id of the cpu and this cpu node
> > is created only for physical cpus (not for logical/threaded cpus). The
> > code compares the "reg" value to the current boot cpu id and if it
> > matches then only it reads "ibm,ppc-interrupt-gserver#s" and assigns the
> > last value of it (which is usually 0xff) to default_distrib_server. So
> > when a crash occurs on CPU 3, it will not be able to match the condition
> > and thus default_distrib_server is left as zero only. This makes all
> > interrupts routed to cpu 0 but cpu 0 is not up because of "maxcpus=1"
> > parameter.
> >
> > To overcome this, I have just added one more condition to check the
> > above condition. I have attached the patch also. Patch is generated over
> > 2.6.19-rc3.
> >
> > One more idea will be instead of using "reg" property in each cpu node,
> > can we use "ibm,ppc-interrupt-gserver#s" to determine the distribution
> > server? "ibm,ppc-interrupt-gserver#s" format is (please correct
> > if I am wrong)
> > phys_cpu_id distrib_server logical_cpu_id distrib_server
>
> Firmware has no notion of Linux's logical cpu numbering.
>
>
I have created a patch based on "ibm,ppc-interrupt-gserver#s" property.
Attached patch uses "ibm,ppc-interrupt-gserver#s" property to match the
boot cpu id with available cpu ids. The property
"ibm,ppc-interrupt-gserver#" is encoded as a list of server# and
gserver#s pairs. The first integer specifies a single processor server#
as presented in "ibm,ppc-interrupt-server#s" property and followed by
distribution server. So if a match is found, corresponding server# is
taken as default server and the corresponding gserver# is taken as
default distribution server.
In a Dual core SMT enabled system, "ibm,ppc-interrupt-gserver#s" for
PowerPC,POWER5@2 will be:
00000002 000000ff 00000003 000000ff
^ cpu id
^ distribution server
^ cpu id
^ distribution server
Tested on a POWER5 box.
Patch is generated over 2.6.19-rc3
Allow any cpu to become boot cpu.
Signed-off-by: Mohan Kumar M <mohan@in.ibm.com>
---
arch/powerpc/platforms/pseries/xics.c | 30 +++++++++++++++---------------
1 file changed, 15 insertions(+), 15 deletions(-)
Index: linux-2.6.19-rc3/arch/powerpc/platforms/pseries/xics.c
===================================================================
--- linux-2.6.19-rc3.orig/arch/powerpc/platforms/pseries/xics.c
+++ linux-2.6.19-rc3/arch/powerpc/platforms/pseries/xics.c
@@ -658,7 +658,7 @@ static void __init xics_setup_8259_casca
void __init xics_init_IRQ(void)
{
- int i;
+ int i, j;
struct device_node *np;
u32 ilen, indx = 0;
const u32 *ireg;
@@ -686,23 +686,23 @@ void __init xics_init_IRQ(void)
for (np = of_find_node_by_type(NULL, "cpu");
np;
np = of_find_node_by_type(np, "cpu")) {
- ireg = get_property(np, "reg", &ilen);
- if (ireg && ireg[0] == get_hard_smp_processor_id(boot_cpuid)) {
- ireg = get_property(np,
- "ibm,ppc-interrupt-gserver#s", &ilen);
- i = ilen / sizeof(int);
- if (ireg && i > 0) {
- default_server = ireg[0];
- /* take last element */
- default_distrib_server = ireg[i-1];
- }
- ireg = get_property(np,
+ ireg = get_property(np, "ibm,ppc-interrupt-gserver#s", &ilen);
+ i = ilen / sizeof(int);
+ for (j = 0; ireg[j] && j < i; j+=2) {
+ if (ireg[j] == get_hard_smp_processor_id(boot_cpuid)) {
+ if ( j + 1 < i) {
+ default_server = ireg[j];
+ default_distrib_server = ireg[j+1];
+ }
+ ireg = get_property(np,
"ibm,interrupt-server#-size", NULL);
- if (ireg)
- interrupt_server_size = *ireg;
- break;
+ if (ireg)
+ interrupt_server_size = *ireg;
+ goto out;
+ }
}
}
+out:
of_node_put(np);
if (firmware_has_feature(FW_FEATURE_LPAR))
^ permalink raw reply
* Re: [PATCH] CPM_UART: Fix non-console transmit
From: Kalle Pokki @ 2006-10-31 11:52 UTC (permalink / raw)
To: Laurent Pinchart; +Cc: Boris Shteinbock, linuxppc-embedded
In-Reply-To: <200610311124.46698.laurent.pinchart@tbox.biz>
On 10/31/06, Laurent Pinchart <laurent.pinchart@tbox.biz> wrote:
> Ditto. Your patch fixed my problems. I'd like to see a fix (either this one or
> another one, there are different solutions) pushed upstream soon, as the
> problem is quite serious. I'm quite amazed nobody had ever reported it
> before.
I think cpm_uart_startup() is the right place to enable both
transmitter and receiver, since they are disabled in the corresponding
shutdown() function. Or actually, one might be just fine with never
disabling the hardware at all. I can't see any reason other than power
consumption that they are disabled by the shutdown() function.
It seems the reason of not enabling the transmitter at startup() is
that the serial core specification only states that reception should
be enabled with that function call. However enabling also the
transmitter does not by itself initiate any transmissions, so it
should be just fine. It just makes the hardware ready to transmit.
^ permalink raw reply
* 8 MB D-TLB's break 8xx without CONFIG_8xx_CPU6
From: Kalle Pokki @ 2006-10-31 12:24 UTC (permalink / raw)
To: linuxppc-embedded, marcelo.tosatti
Hi,
Can you please review the 8 MB D-TLB change introduced by
8f069b1a90bd97bf6d59a02ecabf0173d9175609 again? Even though I also
have the two patches that fix this commit, I always get an oops when
the init process is supposed to start. The only way to run the board
is to have CONFIG_8xx_CPU6 enabled, and I'd rather avoid that since I
only have 860's with the D.4 mask that are not supposed to be affected
by CPU6.
^ permalink raw reply
* build problems with powerpc allmodconfig
From: Christoph Hellwig @ 2006-10-31 14:22 UTC (permalink / raw)
To: linuxppc-dev
When trying to build an allmodconfig kernel on powerpc I run into
three errors, all related to the integeration of iseries support
into the main kernel image:
- vicocons.c can't be compiled at the same time as CONFIG_VT, but
instead of expressing that in the Kconfig it errors out in that
case. This should at least be a Kconfig dependency, but long
term viocons must work at the same time as the normal vt code
to have a single ppc64 image
- vioscsi linkage fails because iseries_vscsi.c and rpa_vscsi.c.
This needs some trivial indirection via function vectors, but
how can we find out which one to use from the driver? Both
seem to look the same in the device tree
- arch/powerpc/platforms/iseries/setup.c references rd_size
when CONFIG_INITRD is set. But rd_size is defined drivers/block/rd.c
which can me modular (and is selected by CONFIG_BLK_DEV_RAM).
This same bug is repeated in the arm amd arm26 code, but except
for those no one outside of rd.c uses this symbol. I don't see
a point why arch code should modify this as it's already big enough.
^ permalink raw reply
* Re: [PATCH 1/2] Add MPC52xx Interrupt controller support for ARCH=powerpc
From: Kumar Gala @ 2006-10-31 14:34 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev, linuxppc-embedded, sl, sha
In-Reply-To: <1162284176.25682.320.camel@localhost.localdomain>
On Oct 31, 2006, at 2:42 AM, Benjamin Herrenschmidt wrote:
> On Tue, 2006-10-31 at 09:25 +0100, Nicolas DET wrote:
>
>> Ok. By the way, the mbar is include as property in our OpenFrimware.
>> Moreover, the G2CORE CPU has a new SPR 'MBAR' which is the
>> MBAR ;-). It
>> would maybe make sense to create a new file
>> (arch/powerpc/sysdev/mpc52xx.c) which would contain chip specific
>> code.
>>
>> Like mpc52xx_get_mbar(), mpc52xx_get_ipbfreq(), etc...
>>
>> I updated a bit the patches. I applied Dale requests.
>> My kernel still compiles and boots. ;-)
>>
>> Should I post the new patches?
>
> Sure.
>
>> About the headers thingy. Should I split them directly in the
>> patch, or
>> this should be done by others later on?
>
> Don't bother that much about splitting the headers. I personally don't
> mind.
I think we should at least split out the interrupt stuff into a arch/
powerpc/sysdev/mpc52xx_pic.h, but we can make the change in the future.
- k
^ permalink raw reply
* Re: [PATCH] CPM_UART: Fix non-console transmit
From: Vitaly Bordug @ 2006-10-31 15:08 UTC (permalink / raw)
To: Paul Mackerras; +Cc: Laurent, linuxppc-embedded
In-Reply-To: <Pine.OSF.4.61.0610191549130.318096@kosh.hut.fi>
On Thu, 19 Oct 2006 15:52:11 +0300 (EEST)
Kalle Pokki <kalle.pokki@iki.fi> wrote:
> The SMC and SCC hardware transmitter is enabled at the wrong
> place. Simply writing twice to the non-console port, like
>
> $ echo asdf > /dev/ttyCPM1
> $ echo asdf > /dev/ttyCPM1
>
> puts the shell into endless uninterruptible sleep, since the
> transmitter is stopped after the first write, and is not enabled
> before the shutdown function of the second write. Thus the transmit
> buffers are never emptied.
>
> Signed-off-by: Kalle Pokki <kalle.pokki@iki.fi>
Signed-off-by: Vitaly Bordug <vbordug@ru.mvista.com>
Paul: please apply.
I am recalling addressing something like the upper, but dunno why it haven't pushed
upstream. Something around re-use scc/smc did not feel good with this approach, but it is
much less important than the odd behavior expressed.
--
Sincerely,
Vitaly
^ permalink raw reply
* Re: build problems with powerpc allmodconfig
From: Stephen Rothwell @ 2006-10-31 15:22 UTC (permalink / raw)
To: Christoph Hellwig; +Cc: linuxppc-dev
In-Reply-To: <20061031142213.GA9275@lst.de>
[-- Attachment #1: Type: text/plain, Size: 1656 bytes --]
On Tue, 31 Oct 2006 15:22:13 +0100 Christoph Hellwig <hch@lst.de> wrote:
>
> - vicocons.c can't be compiled at the same time as CONFIG_VT, but
> instead of expressing that in the Kconfig it errors out in that
> case. This should at least be a Kconfig dependency, but long
> term viocons must work at the same time as the normal vt code
> to have a single ppc64 image
viocons is deprecated (in favour of hvc_iseries) so we just need Kconfig
to say to build it only CONFIG_VT is not defined.
> - vioscsi linkage fails because iseries_vscsi.c and rpa_vscsi.c.
> This needs some trivial indirection via function vectors, but
> how can we find out which one to use from the driver? Both
> seem to look the same in the device tree
The maintainer suggested that we just don't build vioscsi for iseries
if we are building the rpa version as it is not often used (in particular,
it is not used for installations). We could, however distinguish them
by changing the "compat" field in the iSeries device tree if we wished.
> - arch/powerpc/platforms/iseries/setup.c references rd_size
> when CONFIG_INITRD is set. But rd_size is defined drivers/block/rd.c
> which can me modular (and is selected by CONFIG_BLK_DEV_RAM).
> This same bug is repeated in the arm amd arm26 code, but except
> for those no one outside of rd.c uses this symbol. I don't see
> a point why arch code should modify this as it's already big enough.
A fix for this has already been posted
(http://patchwork.ozlabs.org/linuxppc/patch?id=7523).
--
Cheers,
Stephen Rothwell sfr@canb.auug.org.au
http://www.canb.auug.org.au/~sfr/
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^ permalink raw reply
* Re: build problems with powerpc allmodconfig
From: Stephen Rothwell @ 2006-10-31 15:24 UTC (permalink / raw)
To: Christoph Hellwig; +Cc: linuxppc-dev
In-Reply-To: <20061101022213.0b6bcaf9.sfr@canb.auug.org.au>
[-- Attachment #1: Type: text/plain, Size: 840 bytes --]
On Wed, 1 Nov 2006 02:22:13 +1100 Stephen Rothwell <sfr@canb.auug.org.au> wrote:
>
> On Tue, 31 Oct 2006 15:22:13 +0100 Christoph Hellwig <hch@lst.de> wrote:
> >
> > - arch/powerpc/platforms/iseries/setup.c references rd_size
> > when CONFIG_INITRD is set. But rd_size is defined drivers/block/rd.c
> > which can me modular (and is selected by CONFIG_BLK_DEV_RAM).
> > This same bug is repeated in the arm amd arm26 code, but except
> > for those no one outside of rd.c uses this symbol. I don't see
> > a point why arch code should modify this as it's already big enough.
>
> A fix for this has already been posted
> (http://patchwork.ozlabs.org/linuxppc/patch?id=7523).
This patch is already in the powerpc git tree.
--
Cheers,
Stephen Rothwell sfr@canb.auug.org.au
http://www.canb.auug.org.au/~sfr/
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^ permalink raw reply
* Re: [PATCH 1/2] Add MPC52xx Interrupt controller support for ARCH=powerpc
From: Grant Likely @ 2006-10-31 16:24 UTC (permalink / raw)
To: Nicolas DET; +Cc: linuxppc-dev, sl, sha, linuxppc-embedded
In-Reply-To: <4546F7DE.6070104@bplan-gmbh.de>
On 10/31/06, Nicolas DET <nd@bplan-gmbh.de> wrote:
> Kumar Gala wrote:
> > +/* MBAR position */
> > +#define MPC52xx_MBAR 0xf0000000 /* Phys address */
> > +#define MPC52xx_MBAR_VIRT 0xf0000000 /* Virt address */
> > +#define MPC52xx_MBAR_SIZE 0x00010000
> > +
> > +#define MPC52xx_PA(x) ((phys_addr_t)(MPC52xx_MBAR + (x)))
> > +#define MPC52xx_VA(x) ((void __iomem *)(MPC52xx_MBAR_VIRT + (x)))
> >
> > This should be handled dynamically (pulled from the device tree), I
> > doubt MBAR will be at the same location for all boards.
>
> Well, 0xf000000 seems some kind of 'standart' value. we could have a
> global variable 'mpc52xx_mbar' which would be default 0xf0000000 and
> modified by each platform.
In my lite5200 device tree; I've got an "soc5200@f0000000" node which
provides the MBAR base address.
--
Grant Likely, B.Sc. P.Eng.
Secret Lab Technologies Ltd.
grant.likely@secretlab.ca
(403) 399-0195
^ permalink raw reply
* Re: [PATCH] Xilinx UART Lite 2.6.18 driver
From: David H. Lynch Jr. @ 2006-10-31 17:26 UTC (permalink / raw)
To: Peter Korsgaard, linuxppc-embedded
In-Reply-To: <87pscap5zq.fsf@sleipner.barco.com>
[-- Attachment #1: Type: text/plain, Size: 7010 bytes --]
Peter Korsgaard wrote:
>>>>>> "David" == David H Lynch <dhlii@dlasys.net> writes:
>>>>>>
>
> David> There is a substantial time/code difference between the
> David> time ulite_console_setup() is called and the time the platform
> David> device is initiallized.
>
> Huh?
>
> (gdb) br ulite_probe
> Breakpoint 2 at 0xc00f7530: file drivers/serial/uartlite.c, line 397.
> (gdb) br ulite_console_setup
> Breakpoint 3 at 0xc00f7454: file drivers/serial/uartlite.c, line 342.
> (gdb) c
> Continuing.
>
> Breakpoint 2, ulite_probe (pdev=0xc00ddb50) at drivers/serial/uartlite.c:397
> 397 return -EINVAL;
> (gdb) c
> Continuing.
>
> Breakpoint 3, ulite_console_setup (co=0xc00e2f14, options=0xc00fe00f "115200")
> at drivers/serial/uartlite.c:342
> 342 if (co->index < 0 || co->index >= ULITE_NR_UARTS)
>
> _probe get's called before console_setup, so we have all the
> information to output console data right away.
I am not nearly as familiar with your driver and David B. Early
serial patches as I am with my own.
But I can assure you that the early serial init code occurs well
before the call to probe.
If that is not the case then there is no reason for the early serial
code to even exist.
Does David B.'s patch include support for early_serial_init(struct
uart_port *) ?
Look at other BSP's, most have early serial support.
One of the reasons I modeled my driver off the 8250 was because it
had boot to bash support.
If the 8250 did something in a particular way I did the same for the
uartlite - unless I really deeply understood why
I needed not to. I implimented every relevant 8250 feature every
step of the way.
I actually started with the early serial code long before I started
with the driver. It was fairly trivial. It gets you fairly far into the
boot process,
and you can call it directly for debugging.
> David> But for now, if you are not going to bother making
> David> console_settup() work you might as well not put the rest of the
> David> early serial code in at all.
>
> Not going to make it work? What doesn't work?
>
If you impliment early_serial_setup(struct uart_port *) then you
must initialize the driver at the time of that call using a uart_port
struct.
Unless you are going to redefine early_serial_setup() specifically
for the uartlite - maybe that is possible, I don't know, but it sounds
like a bad idea.
I have attached the boot text from a Pico E14 - this one using my
Keyhole port serial driver not the uartlite drive - but since I
patterned them both after the 8250
the sequence is the same.
The serial_init() call initializes the mini_driver in
arch/ppc/boot/simple - in the case of uartlite that would be uartlite_tty.c
keyhole_init() or uartlite_init() is in arch/ppc/syslib - in the
case of uartlite uartlite_dbg.c
that is followed immediately by early_serial_init() - basically
meaning unless you make heavy use of progress() calls - and with
early_serial_init() you can call printk and receive output immediately,
uartlite_dbg.c is probably unneeded but it is trivial and damn
near identical to uartlite_tty.c
early_serial_init() is followed nearly immediately with
keyhole_console_setup() or uartlite_console_setup()
Much late Linux starts initializing the serial drivers and calls probe.
If you do not impliment early_serial_setup, then you will be blind
from that point until the probe call occurs. If anything goes wrong you
will have to try to dump the printk buffer in memory to find out what
went wrong.
I do not know what hardware you are using or how your BSP is
constructed.
The whole early serial text system has little use for a system that
is working perfectly.
But it could be a life saver for somebody doing board bringup.
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
.
Loading zImage.elf.
[keyhole] serial_init()
loaded at: 00800000 00ABC13C
board data at: 0FFFFF60 0FFFFF7C
relocated to: 00804030 0080404C
zimage at: 00804E01 00AB9C2E
avail ram: 00ABD000 0FFFFFFF
Linux/PPC load: root=/dev/ram
Uncompressing Linux...done.
Now booting the kernel
id mach(): done
MMU:enter
MMU:hw init
MMU:mapin
MMU:setio
MMU:exit
setup_arch: enter
setup_arch: bootmem
keyhole_init()
keyhole:early_serial_setup()
arch: exit
keyhole_console_setup()
Linux version 2.6.19-rc2 (root@pico.dlasys.net) (gcc version 3.4.1) #2
Tue Oct 31 11:24:48 EST 2006
Pico Virtex-4 port
Port by DLA Systems (info@dlasys.net)
Zone PFN ranges:
DMA 0 -> 65535
Normal 65535 -> 65535
early_node_map[1] active PFN ranges
0: 0 -> 65535
Built 1 zonelists. Total pages: 65024
Kernel command line: root=/dev/ram
Xilinx INTC #0 at 0x41200000 mapped to 0xF5FFD000
PID hash table entries: 1024 (order: 10, 4096 bytes)
Dentry cache hash table entries: 32768 (order: 5, 131072 bytes)
Inode-cache hash table entries: 16384 (order: 4, 65536 bytes)
Memory: 255488k available (1272k kernel code, 724k data, 2052k init, 0k
highmem)
Mount-cache hash table entries: 512
NET: Registered protocol family 16
NET: Registered protocol family 2
IP route cache hash table entries: 2048 (order: 1, 8192 bytes)
TCP established hash table entries: 8192 (order: 3, 32768 bytes)
TCP bind hash table entries: 4096 (order: 2, 16384 bytes)
TCP: Hash tables configured (established 8192 bind 4096)
TCP reno registered
io scheduler noop registered (default)
Serial: Xilinx uartlite driver $Revision: 0.10 $ 1 ports
Serial: Pico keyhole driver $Revision: 0.20 $*
keyhole_device_probe()
ttyS0 at MMIO 0x70000000 (irq = -1) is a keyhole
RAMDISK driver initialized: 16 RAM disks of 8192K size 1024 blocksize
TCP cubic registered
NET: Registered protocol family 17
Freeing unused kernel memory: 2052k init
command='/bin/sh' action='2' terminal='/dev/ttyS0'
command='/etc/init.d/rcS' action='1' terminal='/dev/ttyS0'
command='/sbin/init' action='128' terminal='/dev/ttyS0'
command='/sbin/reboot' action='32' terminal='/dev/ttyS0'
command='/sbin/swapoff -a 2>/dev/null' action='64' terminal='/dev/ttyS0'
command='/bin/umount -a -r' action='64' terminal='/dev/ttyS0'
Starting DHCP client: udhcpc a
BusyBox v1.2.0 (2006.07.21-07:20+0000) Built-in shell (ash)
Enter 'help' for a list of built-in commands.
/ $
--
Dave Lynch DLA Systems
Software Development: Embedded Linux
717.627.3770 dhlii@dlasys.net http://www.dlasys.net
fax: 1.253.369.9244 Cell: 1.717.587.7774
Over 25 years' experience in platforms, languages, and technologies too numerous to list.
"Any intelligent fool can make things bigger and more complex... It takes a touch of genius - and a lot of courage to move in the opposite direction."
Albert Einstein
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^ permalink raw reply
* Re: Building ELDK 3.0/3.1 from SRPMS
From: John W @ 2006-10-31 18:05 UTC (permalink / raw)
To: Wolfgang Denk; +Cc: linuxppc-embedded
In-Reply-To: <20061030235315.7BC2B352658@atlas.denx.de>
Wolfgang,
> Out of curiosity: may I ask why you invest efforts
> in this old
> version?
There are a number of people on my team that have been
using ELDK 2.1.0 gcc toolchain to compile their kernel
modules, and userspace programs for a number of years.
I would love to use ELDK 3.x, but if there are
problems during kernel compilation, user space library
incompatability, etc., I would like to have ELDK 2.1.0
built from source as a "Plan B". I'm doing my very
best to convince people to upgrade to a newer version
of the gcc toolchain & kernel version. The only
problem is that I have to prove that ELDK 3.x will
satisfy all of their needs before making such a vast
upgrade. Unfortuantely I work in a place where
"change" does not happen very fast.
> Sorry, I don't have these old logs online any more.
> Please drop me a
> note if you really want to see these, so I can
> restore the files from
> tape.
Thanks. Let me try and recompile everything first,
and if that doesn't work, then I'll politely ask you
for those logs. It will take me a few days to track
down the right versions of software and complete this
task.
You have been tremendously helpful! Thank you very
much.
John M. Woo
--- Wolfgang Denk <wd@denx.de> wrote:
> Dear John,
>
> in message
> <20061030033846.1930.qmail@web50313.mail.yahoo.com>
> you wrote:
> > Thanks Wolfgang! Loading RH7.3 and updating
> > everything with YUM seemed to do the trick to
> building
> > ELDK 3.0!
>
> Out of curiosity: may I ask why you invest efforts
> in this old
> version?
>
> > On a another note, I am also trying to build ELDK
> > 2.1.0 from SRPMS on the same RH7.3 machine, and I
> am
> > comming across two problems:
> > 1. The SRPM for mount-2.11g-5a.src.rpm from the
> > Yellowdog 2.3 release seems to have "bad magic" in
> > that when trying to install the SRPM, there is
> some
> > sort of validation problem. In remeding this, I
> am
> > using mount-2.11g-5a.src.rpm from the Yellowdog
> 2.2
> > release. It probably isn't safe to to so, but I
> was
> > wondering how you over came this issue.
>
> Exactly the same way you did :-)
>
> > 2. I'm pretty sure that not all of my
> applications
> > are building in the ELDK2.1.0 release, for
> example
> ...
> > /bin/sh: gperf: command not found
> > make[1]: *** [keywords.c] Error 127
> > make[1]: Leaving directory
> >
>
`/opt/eldkv2.1.0/build/ppc-2006-10-27/work/usr/src/de
> > nx/BUILD/modutils-2.4.13/genksyms'
> > make: *** [all] Error 2
> > error: Bad exit status from
> >
> /opt/eldkv2.1.0/build/ppc-2006-10-27/work/var/tmp/rp
> > m-tmp.26616 (%build)
> >
> > Does mean that I need to go get gperf?
>
> Sorry, I don't have these old logs online any more.
> Please drop me a
> note if you really want to see these, so I can
> restore the files from
> tape.
>
> Best regards,
>
> Wolfgang Denk
>
> --
> Software Engineering: Embedded and Realtime
> Systems, Embedded Linux
> Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80
> Email: wd@denx.de
> How many Unix hacks does it take to change a light
> bulb? Let's see,
> can you use a shell script for that or does it
> need a C program?
>
____________________________________________________________________________________
Access over 1 million songs - Yahoo! Music Unlimited
(http://music.yahoo.com/unlimited)
^ permalink raw reply
* Re: [DTC][PATCH] increment default output blob version from 3 to 16
From: Jon Loeliger @ 2006-10-31 18:32 UTC (permalink / raw)
To: Kim Phillips; +Cc: linuxppc-dev list
In-Reply-To: <20061030104859.017cb613.kim.phillips@freescale.com>
So, like, the other day Kim Phillips mumbled:
> increment default output blob version from 3 to 16
>
> diff --git a/dtc.c b/dtc.c
> index 646b814..3cb94e6 100644
> --- a/dtc.c
> +++ b/dtc.c
> @@ -113,7 +113,7 @@ int main(int argc, char *argv[])
> int opt;
> FILE *inf = NULL;
> FILE *outf = NULL;
> - int outversion = 3;
> + int outversion = 0x10;
> int reservenum = 1;
> int boot_cpuid_phys = 0xfeedbeef;
So, I am inclined to accept this change since we all pretty
much really need version 16 for what we are doing.
Will changing this default really annoy anyone out there?
Thanks,
jdl
^ permalink raw reply
* [PATCH 4/5] ppc64: make soft_enabled irqs preempt safe
From: Hugh Dickins @ 2006-10-31 18:43 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev
In-Reply-To: <Pine.LNX.4.64.0610311834580.26470@blonde.wat.veritas.com>
Rewrite local_get_flags and local_irq_disable to use r13 explicitly,
to avoid the risk that gcc will split get_paca()->soft_enabled into
a sequence unsafe against preemption.
local_irq_restore be careful to access hard_enabled and lppaca before
setting soft_enabled, which may well permit preemption. Use local_paca
instead of get_paca() when setting hard_enabled: looking ahead to the
DEBUG_PREEMPT patch, which uses local_paca as the raw unchecked version.
Signed-off-by: Hugh Dickins <hugh@veritas.com>
---
As before, my powerpc and inline asm may be nonsense: please do fix it.
This patch is to powerpc git code, not intended for 2.6.19.
arch/powerpc/kernel/irq.c | 20 +++++++++++++++-----
include/asm-powerpc/hw_irq.h | 20 +++++++++++++++-----
2 files changed, 30 insertions(+), 10 deletions(-)
--- git-powerpc/arch/powerpc/kernel/irq.c 2006-10-30 19:30:57.000000000 +0000
+++ linux/arch/powerpc/kernel/irq.c 2006-10-30 19:32:38.000000000 +0000
@@ -99,20 +99,30 @@ int distribute_irqs = 1;
void local_irq_restore(unsigned long en)
{
- get_paca()->soft_enabled = en;
- if (!en)
+ unsigned long hard_enabled;
+
+ if (!en) {
+ get_paca()->soft_enabled = en;
return;
+ }
if (firmware_has_feature(FW_FEATURE_ISERIES)) {
- if (get_paca()->lppaca_ptr->int_dword.any_int)
+ unsigned long any_int;
+
+ any_int = get_lppaca()->int_dword.any_int;
+ get_paca()->soft_enabled = en;
+ if (any_int)
iseries_handle_interrupts();
return;
}
- if (get_paca()->hard_enabled)
+ hard_enabled = get_paca()->hard_enabled;
+ get_paca()->soft_enabled = en;
+ if (hard_enabled)
return;
+
/* need to hard-enable interrupts here */
- get_paca()->hard_enabled = en;
+ local_paca->hard_enabled = en;
if ((int)mfspr(SPRN_DEC) < 0)
mtspr(SPRN_DEC, 1);
hard_irq_enable();
--- git-powerpc/include/asm-powerpc/hw_irq.h 2006-10-30 19:30:57.000000000 +0000
+++ linux/include/asm-powerpc/hw_irq.h 2006-10-30 19:32:38.000000000 +0000
@@ -18,15 +18,25 @@ extern void timer_interrupt(struct pt_re
static inline unsigned long local_get_flags(void)
{
- return get_paca()->soft_enabled;
+ unsigned long flags;
+
+ __asm__ __volatile__("lbz %0,%1(13)"
+ : "=r" (flags)
+ : "i" (offsetof(struct paca_struct, soft_enabled)));
+
+ return flags;
}
static inline unsigned long local_irq_disable(void)
{
- unsigned long flag = get_paca()->soft_enabled;
- get_paca()->soft_enabled = 0;
- barrier();
- return flag;
+ unsigned long flags, zero;
+
+ __asm__ __volatile__("li %1,0; lbz %0,%2(13); stb %1,%2(13)"
+ : "=r" (flags), "=&r" (zero)
+ : "i" (offsetof(struct paca_struct, soft_enabled))
+ : "memory");
+
+ return flags;
}
extern void local_irq_restore(unsigned long);
^ permalink raw reply
* [PATCH 5/5] ppc64: support CONFIG_DEBUG_PREEMPT
From: Hugh Dickins @ 2006-10-31 18:44 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev
In-Reply-To: <Pine.LNX.4.64.0610311834580.26470@blonde.wat.veritas.com>
Add CONFIG_DEBUG_PREEMPT support to ppc64: it was useful for testing
get_paca() preemption. Cheat a little, just use debug_smp_processor_id()
in the debug version of get_paca(): it contains all the right checks and
reporting, though get_paca() doesn't really use smp_processor_id().
Use local_paca for what might have been called __raw_get_paca().
Silence harmless warnings from io.h and lparcfg.c with local_paca - I
assume it is okay for iseries_lparcfg_data to be referencing shared_proc
with preemption enabled: all cpus show the same value for shared_proc?
Why do other architectures need TRACE_IRQFLAGS_SUPPORT for DEBUG_PREEMPT?
I don't know, ppc64 appears to get along fine without it.
Signed-off-by: Hugh Dickins <hugh@veritas.com>
---
I've only tested this on one particular PowerMac G5 configuration:
it's quite likely that once integrated, defaulting to y when PREEMPT,
it'll show up a bunch of noisy warnings on other configurations:
not something to rush into mainline.
arch/powerpc/kernel/lparcfg.c | 2 +-
include/asm-powerpc/io.h | 14 +++++++-------
include/asm-powerpc/paca.h | 11 +++++++++++
include/asm-powerpc/percpu.h | 2 +-
include/asm-powerpc/smp.h | 2 +-
lib/Kconfig.debug | 2 +-
6 files changed, 22 insertions(+), 11 deletions(-)
--- git-powerpc/arch/powerpc/kernel/lparcfg.c 2006-10-24 04:34:08.000000000 +0100
+++ linux/arch/powerpc/kernel/lparcfg.c 2006-10-30 19:50:54.000000000 +0000
@@ -77,7 +77,7 @@ static int iseries_lparcfg_data(struct s
int processors, max_processors;
unsigned long purr = get_purr();
- shared = (int)(get_lppaca()->shared_proc);
+ shared = (int)(local_paca->lppaca_ptr->shared_proc);
seq_printf(m, "system_active_processors=%d\n",
(int)HvLpConfig_getSystemPhysicalProcessors());
--- git-powerpc/include/asm-powerpc/io.h 2006-10-24 04:34:33.000000000 +0100
+++ linux/include/asm-powerpc/io.h 2006-10-30 19:50:54.000000000 +0000
@@ -282,7 +282,7 @@ static inline void __out_8(volatile unsi
{
__asm__ __volatile__("sync; stb%U0%X0 %1,%0"
: "=m" (*addr) : "r" (val));
- get_paca()->io_sync = 1;
+ local_paca->io_sync = 1;
}
static inline int __in_le16(const volatile unsigned short __iomem *addr)
@@ -307,14 +307,14 @@ static inline void __out_le16(volatile u
{
__asm__ __volatile__("sync; sthbrx %1,0,%2"
: "=m" (*addr) : "r" (val), "r" (addr));
- get_paca()->io_sync = 1;
+ local_paca->io_sync = 1;
}
static inline void __out_be16(volatile unsigned short __iomem *addr, int val)
{
__asm__ __volatile__("sync; sth%U0%X0 %1,%0"
: "=m" (*addr) : "r" (val));
- get_paca()->io_sync = 1;
+ local_paca->io_sync = 1;
}
static inline unsigned __in_le32(const volatile unsigned __iomem *addr)
@@ -339,14 +339,14 @@ static inline void __out_le32(volatile u
{
__asm__ __volatile__("sync; stwbrx %1,0,%2" : "=m" (*addr)
: "r" (val), "r" (addr));
- get_paca()->io_sync = 1;
+ local_paca->io_sync = 1;
}
static inline void __out_be32(volatile unsigned __iomem *addr, int val)
{
__asm__ __volatile__("sync; stw%U0%X0 %1,%0"
: "=m" (*addr) : "r" (val));
- get_paca()->io_sync = 1;
+ local_paca->io_sync = 1;
}
static inline unsigned long __in_le64(const volatile unsigned long __iomem *addr)
@@ -393,13 +393,13 @@ static inline void __out_le64(volatile u
"sync\n"
"std %0,0(%3)"
: "=&r" (tmp) , "=&r" (val) : "1" (val) , "b" (addr) , "m" (*addr));
- get_paca()->io_sync = 1;
+ local_paca->io_sync = 1;
}
static inline void __out_be64(volatile unsigned long __iomem *addr, unsigned long val)
{
__asm__ __volatile__("sync; std%U0%X0 %1,%0" : "=m" (*addr) : "r" (val));
- get_paca()->io_sync = 1;
+ local_paca->io_sync = 1;
}
#include <asm/eeh.h>
--- git-powerpc/include/asm-powerpc/paca.h 2006-10-30 19:30:57.000000000 +0000
+++ linux/include/asm-powerpc/paca.h 2006-10-30 19:50:54.000000000 +0000
@@ -21,7 +21,18 @@
#include <asm/mmu.h>
register struct paca_struct *local_paca asm("r13");
+
+#if defined(CONFIG_DEBUG_PREEMPT) && defined(CONFIG_SMP)
+extern unsigned int debug_smp_processor_id(void); /* from linux/smp.h */
+/*
+ * Add standard checks that preemption cannot occur when using get_paca():
+ * otherwise the paca_struct it points to may be the wrong one just after.
+ */
+#define get_paca() ((void) debug_smp_processor_id(), local_paca)
+#else
#define get_paca() local_paca
+#endif
+
#define get_lppaca() (get_paca()->lppaca_ptr)
#define get_slb_shadow() (get_paca()->slb_shadow_ptr)
--- git-powerpc/include/asm-powerpc/percpu.h 2006-09-20 04:42:06.000000000 +0100
+++ linux/include/asm-powerpc/percpu.h 2006-10-30 19:50:54.000000000 +0000
@@ -23,7 +23,7 @@
/* var is in discarded region: offset to particular copy we want */
#define per_cpu(var, cpu) (*RELOC_HIDE(&per_cpu__##var, __per_cpu_offset(cpu)))
#define __get_cpu_var(var) (*RELOC_HIDE(&per_cpu__##var, __my_cpu_offset()))
-#define __raw_get_cpu_var(var) (*RELOC_HIDE(&per_cpu__##var, __my_cpu_offset()))
+#define __raw_get_cpu_var(var) (*RELOC_HIDE(&per_cpu__##var, local_paca->data_offset))
/* A macro to avoid #include hell... */
#define percpu_modcopy(pcpudst, src, size) \
--- git-powerpc/include/asm-powerpc/smp.h 2006-10-24 04:34:33.000000000 +0100
+++ linux/include/asm-powerpc/smp.h 2006-10-30 19:50:54.000000000 +0000
@@ -45,7 +45,7 @@ void generic_mach_cpu_die(void);
#endif
#ifdef CONFIG_PPC64
-#define raw_smp_processor_id() (get_paca()->paca_index)
+#define raw_smp_processor_id() (local_paca->paca_index)
#define hard_smp_processor_id() (get_paca()->hw_cpu_id)
#else
/* 32-bit */
--- git-powerpc/lib/Kconfig.debug 2006-10-30 19:15:49.000000000 +0000
+++ linux/lib/Kconfig.debug 2006-10-30 19:50:54.000000000 +0000
@@ -114,7 +114,7 @@ config DEBUG_SLAB_LEAK
config DEBUG_PREEMPT
bool "Debug preemptible kernel"
- depends on DEBUG_KERNEL && PREEMPT && TRACE_IRQFLAGS_SUPPORT
+ depends on DEBUG_KERNEL && PREEMPT && (TRACE_IRQFLAGS_SUPPORT || PPC64)
default y
help
If you say Y here then the kernel will use a debug variant of the
^ permalink raw reply
* [PATCH 2/5] ppc64: make high hugepage areas preempt safe
From: Hugh Dickins @ 2006-10-31 18:40 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev
In-Reply-To: <Pine.LNX.4.64.0610311834580.26470@blonde.wat.veritas.com>
Checking source for other get_paca()->field preemption dangers found that
open_high_hpage_areas does a structure copy into its paca while preemption
is enabled: unsafe however gcc accomplishes it. Just remove that copy:
it's done safely afterwards by on_each_cpu, as in open_low_hpage_areas.
Signed-off-by: Hugh Dickins <hugh@veritas.com>
---
I think this patch should go into 2.6.19 (but no reports to justify 18-stable).
arch/powerpc/mm/hugetlbpage.c | 3 ---
1 file changed, 3 deletions(-)
--- 2.6.19-rc4/arch/powerpc/mm/hugetlbpage.c 2006-09-20 04:42:06.000000000 +0100
+++ linux/arch/powerpc/mm/hugetlbpage.c 2006-10-30 19:27:05.000000000 +0000
@@ -480,9 +480,6 @@ static int open_high_hpage_areas(struct
mm->context.high_htlb_areas |= newareas;
- /* update the paca copy of the context struct */
- get_paca()->context = mm->context;
-
/* the context change must make it to memory before the flush,
* so that further SLB misses do the right thing. */
mb();
^ permalink raw reply
* [PATCH 3/5] ppc64: make mmiowb's io_sync preempt safe
From: Hugh Dickins @ 2006-10-31 18:41 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev
In-Reply-To: <Pine.LNX.4.64.0610311834580.26470@blonde.wat.veritas.com>
If mmiowb() is always used prior to releasing spinlock as Doc suggests,
then it's safe against preemption; but I'm not convinced that's always
the case. If preemption occurs between sync and get_paca()->io_sync = 0,
I believe there's no problem. But in the unlikely event that gcc does
the store relative to another register than r13 (as it did with current),
then there's a small danger of setting another cpu's io_sync to 0, after
it had just set it to 1. Rewrite ppc64 mmiowb to prevent that.
The remaining io_sync assignments in io.h all get_paca()->io_sync = 1,
which is harmless even if preempted to the wrong cpu (the context switch
itself syncs); and those in spinlock.h are while preemption is disabled.
Signed-off-by: Hugh Dickins <hugh@veritas.com>
---
I'm clueless with powerpc and inline asm, this patch is likely to be
nonsense: more a placeholder to provoke whatever is the correct patch.
But I think the resulting patch should probably go into 2.6.19.
include/asm-powerpc/io.h | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
--- 2.6.19-rc4/include/asm-powerpc/io.h 2006-10-24 04:34:33.000000000 +0100
+++ linux/include/asm-powerpc/io.h 2006-10-30 19:27:05.000000000 +0000
@@ -163,8 +163,11 @@ extern void _outsl_ns(volatile u32 __iom
static inline void mmiowb(void)
{
- __asm__ __volatile__ ("sync" : : : "memory");
- get_paca()->io_sync = 0;
+ unsigned long tmp;
+
+ __asm__ __volatile__("sync; li %0,0; stb %0,%1(13)"
+ : "=&r" (tmp) : "i" (offsetof(struct paca_struct, io_sync))
+ : "memory");
}
/*
^ permalink raw reply
* [PATCH 1/5] ppc64: make current preempt safe
From: Hugh Dickins @ 2006-10-31 18:39 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev
Repeated -j20 kernel builds on a G5 Quad running an SMP PREEMPT kernel
would often collapse within a day, some exec failing with "Bad address".
In each case examined, load_elf_binary was doing a kernel_read, but
generic_file_aio_read's access_ok saw current->thread.fs.seg as USER_DS
instead of KERNEL_DS.
objdump of filemap.o shows gcc 4.1.0 emitting "mr r5,r13 ... ld r9,416(r5)"
here for get_paca()->__current, instead of the expected and much more usual
"ld r9,416(r13)"; I've seen other gcc4s do the same, but perhaps not gcc3s.
So, if the task is preempted and rescheduled on a different cpu in between
the mr and the ld, r5 will be looking at a different paca_struct from the
one it's now on, pick up the wrong __current, and perhaps the wrong seg.
Presumably much worse could happen elsewhere, though that split is rare.
Other architectures appear to be safe (x86_64's read_pda is more limiting
than get_paca), but ppc64 needs to force "current" into one instruction.
Signed-off-by: Hugh Dickins <hugh@veritas.com>
---
I think this patch should go into both 2.6.19 and 2.6.18-stable.
include/asm-powerpc/current.h | 12 +++++++++++-
1 file changed, 11 insertions(+), 1 deletion(-)
--- 2.6.19-rc4/include/asm-powerpc/current.h 2006-03-20 05:53:29.000000000 +0000
+++ linux/include/asm-powerpc/current.h 2006-10-30 19:27:05.000000000 +0000
@@ -14,7 +14,17 @@ struct task_struct;
#ifdef __powerpc64__
#include <asm/paca.h>
-#define current (get_paca()->__current)
+static inline struct task_struct *get_current(void)
+{
+ struct task_struct *task;
+
+ __asm__ __volatile__("ld %0,%1(13)"
+ : "=r" (task)
+ : "i" (offsetof(struct paca_struct, __current)));
+
+ return task;
+}
+#define current get_current()
#else
^ permalink raw reply
* Re: [PATCH 1/2] Add MPC52xx Interrupt controller support for ARCH=powerpc
From: Nicolas DET @ 2006-10-31 20:04 UTC (permalink / raw)
To: Nicolas DET; +Cc: linuxppc-embedded, sl, sha, linuxppc-dev
In-Reply-To: <454712A4.3000501@bplan-gmbh.de>
[-- Attachment #1: Type: text/plain, Size: 35449 bytes --]
Nicolas DET wrote:
> Benjamin Herrenschmidt wrote:
>> On Tue, 2006-10-31 at 09:25 +0100, Nicolas DET wrote:
>>
>>> Ok. By the way, the mbar is include as property in our OpenFrimware.
>>> Moreover, the G2CORE CPU has a new SPR 'MBAR' which is the MBAR ;-).
>>> It would maybe make sense to create a new file
>>> (arch/powerpc/sysdev/mpc52xx.c) which would contain chip specific code.
>>>
>>> Like mpc52xx_get_mbar(), mpc52xx_get_ipbfreq(), etc...
>>>
>>> I updated a bit the patches. I applied Dale requests.
>>> My kernel still compiles and boots. ;-)
>>>
>>> Should I post the new patches?
>>
>> Sure.
>>
>
> Ok. Should be done this morning.
>
Here is is ;-).
As my mailer can insert a file, I copy paste. I hope it's still ok...
archpowerpc_efika.patch
-----------------------
--- a/arch/powerpc/platforms/efika/setup.c 1970-01-01 01:00:00.000000000
+0100
+++ b/arch/powerpc/platforms/efika/setup.c 2006-10-31 12:31:55.000000000
+0100
@@ -0,0 +1,153 @@
+/*
+ *
+ * Efika 5K2 platform setup
+ *
+ * Copyright (C) 2006 bplan GmbH
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ *
+ */
+
+#include <linux/errno.h>
+#include <linux/sched.h>
+#include <linux/kernel.h>
+#include <linux/ptrace.h>
+#include <linux/slab.h>
+#include <linux/user.h>
+#include <linux/interrupt.h>
+#include <linux/reboot.h>
+#include <linux/init.h>
+#include <linux/utsrelease.h>
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <linux/console.h>
+#include <linux/seq_file.h>
+#include <linux/root_dev.h>
+#include <linux/initrd.h>
+#include <linux/module.h>
+#include <linux/timer.h>
+
+#include <asm/pgtable.h>
+#include <asm/prom.h>
+#include <asm/dma.h>
+#include <asm/machdep.h>
+#include <asm/irq.h>
+#include <asm/sections.h>
+#include <asm/time.h>
+#include <asm/rtas.h>
+#include <asm/mpc52xx.h>
+
+#include "efika.h"
+
+void rtas_indicator_progress(char *, unsigned short);
+
+extern unsigned long loops_per_jiffy;
+
+static void efika_show_cpuinfo(struct seq_file *m)
+{
+ struct device_node *root;
+ const char *revision = NULL;
+ const char *codegendescription = NULL;
+ const char *codegenvendor = NULL;
+
+ root = find_path_device("/");
+ if (root) {
+ revision = get_property(root, "revision", NULL);
+ codegendescription =
+ get_property(root, "CODEGEN,description", NULL);
+ codegenvendor = get_property(root, "CODEGEN,vendor", NULL);
+ }
+
+ if (codegendescription)
+ seq_printf(m, "machine\t\t: %s\n", codegendescription);
+ else
+ seq_printf(m, "machine\t\t: Efika\n");
+
+ if (revision)
+ seq_printf(m, "revision\t: %s\n", revision);
+
+ if (codegenvendor)
+ seq_printf(m, "vendor\t\t: %s\n", codegenvendor);
+}
+
+static void __init efika_setup_arch(void)
+{
+ /* init to some ~sane value until calibrate_delay() runs */
+ loops_per_jiffy = 50000000 / HZ;
+
+ rtas_initialize();
+
+#ifdef CONFIG_BLK_DEV_INITRD
+ initrd_below_start_ok = 1;
+
+ if (initrd_start)
+ ROOT_DEV = Root_RAM0;
+ else
+#endif
+ ROOT_DEV = Root_SDA2; /* sda2 (sda1 is for the kernel) */
+
+ pci_create_OF_bus_map();
+
+ efika_pcisetup();
+
+ if (ppc_md.progress)
+ ppc_md.progress("Linux/PPC " UTS_RELEASE " runnung on Efika ;-)\n", 0x0);
+}
+
+static void __init efika_init_IRQ(void)
+{
+ of_irq_map_init(0);
+ mpc52xx_init_irq();
+}
+
+static void __init efika_init(void)
+{
+ if (ppc_md.progress)
+ ppc_md.progress(" Have fun with your Efika! ", 0x7777);
+}
+
+static int __init efika_probe(void)
+{
+ char *model = of_get_flat_dt_prop(of_get_flat_dt_root(),
+ "model", NULL);
+
+ if (model == NULL)
+ return 0;
+ if (strcmp(model, "EFIKA5K2"))
+ return 0;
+
+ ISA_DMA_THRESHOLD = ~0L;
+ DMA_MODE_READ = 0x44;
+ DMA_MODE_WRITE = 0x48;
+
+ /*
+ * Others values (isa_mem_base, pci_dram_base) are 0
+ * in CHRP for us. Only isa_io_base is changed.
+ */
+ isa_io_base = CHRP_ISA_IO_BASE;
+
+ return 1;
+}
+
+define_machine(efika)
+{
+ .name = EFIKA_PLATFORM_NAME,
+ .probe = efika_probe,
+ .setup_arch = efika_setup_arch,
+ .init = efika_init,
+ .show_cpuinfo = efika_show_cpuinfo,
+ .init_IRQ = efika_init_IRQ,
+ .get_irq = mpc52xx_get_irq,
+ .restart = rtas_restart,
+ .power_off = rtas_power_off,
+ .halt = rtas_halt,
+ .set_rtc_time = rtas_set_rtc_time,
+ .get_rtc_time = rtas_get_rtc_time,
+ .progress = rtas_progress,
+ .get_boot_time = rtas_get_boot_time,
+ .calibrate_decr = generic_calibrate_decr,
+ .phys_mem_access_prot = pci_phys_mem_access_prot,
+ .pcibios_fixup = efika_pciirq_map,
+};
--- a/arch/powerpc/platforms/efika/pci.c 1970-01-01 01:00:00.000000000 +0100
+++ b/arch/powerpc/platforms/efika/pci.c 2006-10-31 12:31:55.000000000 +0100
@@ -0,0 +1,150 @@
+
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/delay.h>
+#include <linux/string.h>
+#include <linux/init.h>
+#include <linux/ide.h>
+
+#include <asm/io.h>
+#include <asm/pgtable.h>
+#include <asm/irq.h>
+#include <asm/hydra.h>
+#include <asm/prom.h>
+#include <asm/gg2.h>
+#include <asm/machdep.h>
+#include <asm/sections.h>
+#include <asm/pci-bridge.h>
+#include <asm/grackle.h>
+#include <asm/rtas.h>
+
+#include "efika.h"
+
+static struct device_node *efika_pcictrl;
+
+/*
+ * Access functions for PCI config space using RTAS calls.
+ */
+static int rtas_read_config(struct pci_bus *bus, unsigned int devfn,
int offset,
+ int len, u32 * val)
+{
+ struct pci_controller *hose = bus->sysdata;
+ unsigned long addr = (offset & 0xff) | ((devfn & 0xff) << 8)
+ | (((bus->number - hose->first_busno) & 0xff) << 16)
+ | (hose->index << 24);
+ int ret = -1;
+ int rval;
+
+ rval = rtas_call(rtas_token("read-pci-config"), 2, 2, &ret, addr, len);
+ *val = ret;
+ return rval ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
+}
+
+static int rtas_write_config(struct pci_bus *bus, unsigned int devfn,
+ int offset, int len, u32 val)
+{
+ struct pci_controller *hose = bus->sysdata;
+ unsigned long addr = (offset & 0xff) | ((devfn & 0xff) << 8)
+ | (((bus->number - hose->first_busno) & 0xff) << 16)
+ | (hose->index << 24);
+ int rval;
+
+ rval = rtas_call(rtas_token("write-pci-config"), 3, 1, NULL,
+ addr, len, val);
+ return rval ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
+}
+
+static struct pci_ops rtas_pci_ops = {
+ rtas_read_config,
+ rtas_write_config
+};
+
+void __init efika_pcisetup(void)
+{
+ const int *bus_range;
+ int len;
+ struct pci_controller *hose;
+ struct device_node *root;
+ struct device_node *pcictrl;
+
+ root = of_find_node_by_path("/");
+ if (root == NULL) {
+ printk(KERN_WARNING EFIKA_PLATFORM_NAME
+ ": Unable to find the root node\n");
+ return;
+ }
+
+ for (pcictrl = NULL;;) {
+ pcictrl = of_get_next_child(root, pcictrl);
+ if ((pcictrl == NULL) || (strcmp(pcictrl->name, "pci") == 0))
+ break;
+ }
+
+ if (pcictrl == NULL) {
+ printk(KERN_WARNING EFIKA_PLATFORM_NAME
+ ": Unable to find the PCI bridge node\n");
+ return;
+ }
+
+ efika_pcictrl = pcictrl;
+
+ bus_range = get_property(pcictrl, "bus-range", &len);
+ if (bus_range == NULL || len < 2 * sizeof(int)) {
+ printk(KERN_WARNING EFIKA_PLATFORM_NAME
+ ": Can't get bus-range for %s\n", pcictrl->full_name);
+ return;
+ }
+ if (bus_range[1] == bus_range[0])
+ printk(KERN_INFO EFIKA_PLATFORM_NAME ": PCI bus %d",
+ bus_range[0]);
+ else
+ printk(KERN_INFO EFIKA_PLATFORM_NAME ": PCI buses %d..%d",
+ bus_range[0], bus_range[1]);
+ printk(" controlled by %s", pcictrl->full_name);
+ printk("\n");
+
+ hose = pcibios_alloc_controller();
+ if (!hose) {
+ printk(KERN_WARNING EFIKA_PLATFORM_NAME
+ ": Can't allocate PCI controller structure for %s\n",
+ pcictrl->full_name);
+ return;
+ }
+
+ hose->arch_data = pcictrl;
+ hose->first_busno = bus_range[0];
+ hose->last_busno = bus_range[1];
+ hose->ops = &rtas_pci_ops;
+
+ pci_process_bridge_OF_ranges(hose, pcictrl, 0);
+}
+
+void __init efika_pciirq_map(void)
+{
+ struct device_node *pcictrl = efika_pcictrl;
+ struct pci_dev *pdev = NULL;
+ struct device_node *ofwdev;
+
+ if (pcictrl == NULL)
+ return;
+
+ /*
+ * We need to find PCI irq, create a virtual mapping, and set
+ * the irq number into the PCI structure (software/Linux side)
+ * I could to this by walking into the /pci node, do
+ * of_irq_map_pci(), irq_create_of_mapping(), then find
+ * the good 'struct pci_dev *' and update pci_dev->irq.
+ * However, pci_read_irq_line() should do everything correctly!
+ */
+
+ for_each_pci_dev(pdev)
+ {
+ if (pci_read_irq_line(pdev) < 0)
+ continue;
+
+ ofwdev = pci_device_to_OF_node(pdev);
+ if (ofwdev)
+ printk(KERN_INFO EFIKA_PLATFORM_NAME ": got IRQ 0x%x for '%s'\n",
pdev->irq, ofwdev->full_name);
+ }
+
+}
--- a/arch/powerpc/platforms/efika/efika.h 1970-01-01 01:00:00.000000000
+0100
+++ b/arch/powerpc/platforms/efika/efika.h 2006-10-31 12:31:55.000000000
+0100
@@ -0,0 +1,20 @@
+/*
+ * Efika 5K2 platform setup - Header file
+ *
+ * Copyright (C) 2006 bplan GmbH
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ *
+ */
+
+#ifndef __ARCH_POWERPC_EFIKA__
+#define __ARCH_POWERPC_EFIKA__
+
+#define EFIKA_PLATFORM_NAME "Efika"
+
+void __init efika_pcisetup(void);
+void __init efika_pciirq_map(void);
+
+#endif
--- a/arch/powerpc/platforms/efika/Makefile 1970-01-01
01:00:00.000000000 +0100
+++ b/arch/powerpc/platforms/efika/Makefile 2006-10-31
20:03:05.000000000 +0100
@@ -0,0 +1 @@
+obj-y += setup.o pci.o
--- a/arch/powerpc/platforms/Makefile 2006-10-31 20:28:06.000000000 +0100
+++ b/arch/powerpc/platforms/Makefile 2006-10-31 12:31:55.000000000 +0100
@@ -6,6 +6,7 @@ obj-$(CONFIG_PPC_PMAC) += powermac/
endif
endif
obj-$(CONFIG_PPC_CHRP) += chrp/
+obj-$(CONFIG_PPC_EFIKA) += efika/
obj-$(CONFIG_4xx) += 4xx/
obj-$(CONFIG_PPC_83xx) += 83xx/
obj-$(CONFIG_PPC_85xx) += 85xx/
--- a/arch/powerpc/boot/Makefile 2006-10-25 19:07:23.000000000 +0200
+++ b/arch/powerpc/boot/Makefile 2006-10-31 12:31:55.000000000 +0100
@@ -155,6 +155,7 @@ image-$(CONFIG_PPC_PSERIES) += zImage.p
image-$(CONFIG_PPC_MAPLE) += zImage.pseries
image-$(CONFIG_PPC_IBM_CELL_BLADE) += zImage.pseries
image-$(CONFIG_PPC_CHRP) += zImage.chrp
+image-$(CONFIG_PPC_EFIKA) += zImage.chrp
image-$(CONFIG_PPC_PMAC) += zImage.pmac
image-$(CONFIG_DEFAULT_UIMAGE) += uImage
--- a/arch/powerpc/Kconfig 2006-10-31 20:28:06.000000000 +0100
+++ b/arch/powerpc/Kconfig 2006-10-31 19:57:57.000000000 +0100
@@ -386,6 +386,19 @@ config PPC_CHRP
select PPC_UDBG_16550
default y
+config PPC_MPC52xx_PIC
+ bool
+ default y
+
+config PPC_EFIKA
+ bool "bPlan Efika 5k2. MPC5200B based computer"
+ depends on PPC_MULTIPLATFORM && PPC32
+ select PPC_RTAS
+ select RTAS_PROC
+ select PPC_MPC52xx
+ select PPC_MPC52xx_PIC
+ default y
+
config PPC_PMAC
bool "Apple PowerMac based machines"
depends on PPC_MULTIPLATFORM
archpowerpc_mpc52xx.patch
-------------------------
--- a/arch/powerpc/sysdev/mpc52xx_pic.c 1970-01-01 01:00:00.000000000 +0100
+++ b/arch/powerpc/sysdev/mpc52xx_pic.c 2006-10-31 19:56:22.000000000 +0100
@@ -0,0 +1,511 @@
+/*
+ *
+ * Programmable Interrupt Controller functions for the Freescale MPC52xx.
+ *
+ * Copyright (C) 2006 bplan GmbH
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ *
+ */
+
+#undef DEBUG
+
+#include <linux/stddef.h>
+#include <linux/init.h>
+#include <linux/sched.h>
+#include <linux/signal.h>
+#include <linux/stddef.h>
+#include <linux/delay.h>
+#include <linux/irq.h>
+#include <linux/hardirq.h>
+
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <asm/system.h>
+#include <asm/irq.h>
+#include <asm/prom.h>
+#include <asm/mpc52xx.h>
+
+static struct mpc52xx_intr __iomem *intr;
+static struct mpc52xx_sdma __iomem *sdma;
+static struct irq_host *mpc52xx_irqhost = NULL;
+
+static unsigned char mpc52xx_map_senses[4] = {
+ IRQ_TYPE_LEVEL_HIGH,
+ IRQ_TYPE_EDGE_FALLING,
+ IRQ_TYPE_EDGE_RISING,
+ IRQ_TYPE_LEVEL_LOW,
+};
+
+/*
+ *
+*/
+
+static inline void io_be_setbit(u32 __iomem *addr, int bitno)
+{
+ out_be32(addr, in_be32(addr) | (1 << bitno) );
+}
+
+static inline void io_be_clrbit(u32 __iomem *addr, int bitno)
+{
+ out_be32(addr, in_be32(addr) & ~(1 << bitno));
+}
+
+/*
+ * Critial interrupt irq_chip
+*/
+static void mpc52xx_crit_mask(unsigned int virq)
+{
+ int irq;
+ int l2irq;
+
+ irq = irq_map[virq].hwirq;
+ l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
+
+ pr_debug("%s: irq=%x, l2=%d\n", __func__, irq, l2irq);
+
+ BUG_ON(l2irq != 0);
+
+ io_be_clrbit(&intr->ctrl, 11);
+}
+
+static void mpc52xx_crit_unmask(unsigned int virq)
+{
+ int irq;
+ int l2irq;
+
+ irq = irq_map[virq].hwirq;
+ l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
+
+ pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
+
+ BUG_ON(l2irq != 0);
+
+ io_be_setbit(&intr->ctrl, 11);
+}
+
+static void mpc52xx_crit_ack(unsigned int virq)
+{
+ int irq;
+ int l2irq;
+
+ irq = irq_map[virq].hwirq;
+ l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
+
+ pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
+
+ BUG_ON(l2irq != 0);
+
+ io_be_setbit(&intr->ctrl, 27);
+}
+
+static struct irq_chip mpc52xx_crit_irqchip = {
+ .typename = "MPC52xx IRQ0",
+ .mask = mpc52xx_crit_mask,
+ .unmask = mpc52xx_crit_unmask,
+ .ack = mpc52xx_crit_ack,
+};
+
+/*
+ * IRQ[1-3] interrupt irq_chip
+*/
+
+static void mpc52xx_mainirq_mask(unsigned int virq)
+{
+ int irq;
+ int l2irq;
+
+ irq = irq_map[virq].hwirq;
+ l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
+
+ pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
+
+ io_be_clrbit(&intr->ctrl, 11 - l2irq);
+}
+
+static void mpc52xx_mainirq_unmask(unsigned int virq)
+{
+ int irq;
+ int l2irq;
+
+ irq = irq_map[virq].hwirq;
+ l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
+
+ pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
+
+ io_be_setbit(&intr->ctrl, 11 - l2irq);
+}
+
+static void mpc52xx_mainirq_ack(unsigned int virq)
+{
+ int irq;
+ int l2irq;
+
+ irq = irq_map[virq].hwirq;
+ l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
+
+ pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
+
+ io_be_setbit(&intr->ctrl, 27-l2irq);
+}
+
+static struct irq_chip mpc52xx_mainirq_irqchip = {
+ .typename = " MPC52xx IRQ[1-3] ",
+ .mask = mpc52xx_mainirq_mask,
+ .unmask = mpc52xx_mainirq_unmask,
+ .ack = mpc52xx_mainirq_ack,
+};
+
+/*
+ * Main interrupt irq_chip
+*/
+
+static void mpc52xx_main_mask(unsigned int virq)
+{
+ int irq;
+ int l2irq;
+
+ irq = irq_map[virq].hwirq;
+ l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
+
+ pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
+
+ io_be_setbit(&intr->main_mask, 15 - l2irq);
+}
+
+static void mpc52xx_main_unmask(unsigned int virq)
+{
+ int irq;
+ int l2irq;
+
+ irq = irq_map[virq].hwirq;
+ l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
+
+ pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
+
+ io_be_clrbit(&intr->main_mask, 15 - l2irq);
+}
+
+static struct irq_chip mpc52xx_main_irqchip = {
+ .typename = "MPC52xx Main",
+ .mask = mpc52xx_main_mask,
+ .mask_ack = mpc52xx_main_mask,
+ .unmask = mpc52xx_main_unmask,
+};
+
+/*
+ * Peripherals interrupt irq_chip
+*/
+
+static void mpc52xx_periph_mask(unsigned int virq)
+{
+ int irq;
+ int l2irq;
+
+ irq = irq_map[virq].hwirq;
+ l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
+
+ pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
+
+ io_be_setbit(&intr->per_mask, 31 - l2irq);
+}
+
+static void mpc52xx_periph_unmask(unsigned int virq)
+{
+ int irq;
+ int l2irq;
+
+ irq = irq_map[virq].hwirq;
+ l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
+
+ pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
+
+ io_be_clrbit(&intr->per_mask, 31 - l2irq);
+}
+
+static struct irq_chip mpc52xx_periph_irqchip = {
+ .typename = "MPC52xx Peripherals",
+ .mask = mpc52xx_periph_mask,
+ .mask_ack = mpc52xx_periph_mask,
+ .unmask = mpc52xx_periph_unmask,
+};
+
+/*
+ * SDMA interrupt irq_chip
+*/
+
+static void mpc52xx_sdma_mask(unsigned int virq)
+{
+ int irq;
+ int l2irq;
+
+ irq = irq_map[virq].hwirq;
+ l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
+
+ pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
+
+ io_be_setbit(&sdma->IntMask, l2irq);
+}
+
+static void mpc52xx_sdma_unmask(unsigned int virq)
+{
+ int irq;
+ int l2irq;
+
+ irq = irq_map[virq].hwirq;
+ l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
+
+ pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
+
+ io_be_clrbit(&sdma->IntMask, l2irq);
+}
+
+static void mpc52xx_sdma_ack(unsigned int virq)
+{
+ int irq;
+ int l2irq;
+
+ irq = irq_map[virq].hwirq;
+ l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
+
+ pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
+
+ out_be32(&sdma->IntPend, 1 << l2irq);
+}
+
+static struct irq_chip mpc52xx_sdma_irqchip = {
+ .typename = "MPC52xx SDMA",
+ .mask = mpc52xx_sdma_mask,
+ .unmask = mpc52xx_sdma_unmask,
+ .ack = mpc52xx_sdma_ack,
+};
+
+/*
+ * irq_host
+*/
+
+static int mpc52xx_irqhost_match(struct irq_host *h, struct device_node
*node)
+{
+ pr_debug("%s: %p vs %p\n", __func__, find_mpc52xx_picnode(), node);
+ return mpc52xx_irqhost->host_data == node;
+}
+
+static int mpc52xx_irqhost_xlate(struct irq_host *h, struct device_node
*ct,
+ u32 * intspec, unsigned int intsize,
+ irq_hw_number_t * out_hwirq,
+ unsigned int *out_flags)
+{
+ int intrvect_l1;
+ int intrvect_l2;
+ int intrvect_type;
+ int intrvect_linux;
+
+ if (intsize != 3)
+ return -1;
+
+ intrvect_l1 = (int)intspec[0];
+ intrvect_l2 = (int)intspec[1];
+ intrvect_type = (int)intspec[2];
+
+ intrvect_linux =
+ (intrvect_l1 << MPC52xx_IRQ_L1_OFFSET) & MPC52xx_IRQ_L1_MASK;
+ intrvect_linux |=
+ (intrvect_l2 << MPC52xx_IRQ_L2_OFFSET) & MPC52xx_IRQ_L2_MASK;
+
+ pr_debug("return %x, l1=%d, l2=%d\n", intrvect_linux, intrvect_l1,
+ intrvect_l2);
+
+ *out_hwirq = intrvect_linux;
+ *out_flags = mpc52xx_map_senses[intrvect_type];
+
+ return 0;
+}
+
+/*
+ * this function retrieves the correct IRQ type out
+ * of the MPC regs
+ * Only externals IRQs needs this
+*/
+static int mpc52xx_irqx_gettype(int irq)
+{
+ int type;
+ u32 ctrl_reg;
+
+ ctrl_reg = in_be32(&intr->ctrl);
+ type = (ctrl_reg >> (22 - irq * 2)) & 0x3;
+
+ return mpc52xx_map_senses[type];
+}
+
+static int mpc52xx_irqhost_map(struct irq_host *h, unsigned int virq,
+ irq_hw_number_t irq)
+{
+ int l1irq;
+ int l2irq;
+ struct irq_chip *good_irqchip;
+ void *good_handle;
+ int type;
+
+ l1irq = (irq & MPC52xx_IRQ_L1_MASK) >> MPC52xx_IRQ_L1_OFFSET;
+ l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
+
+ /*
+ * Most of ours IRQs will be level low
+ * Only external IRQs on some platform may be others
+ */
+ type = IRQ_TYPE_LEVEL_LOW;
+
+ switch (l1irq) {
+ case MPC52xx_IRQ_L1_CRIT:
+ pr_debug("%s: Critical. l2=%x\n", __func__, l2irq);
+
+ BUG_ON(l2irq != 0);
+
+ type = mpc52xx_irqx_gettype(l2irq);
+ good_irqchip = &mpc52xx_crit_irqchip;
+ break;
+
+ case MPC52xx_IRQ_L1_MAIN:
+ pr_debug("%s: Main IRQ[1-3] l2=%x\n", __func__, l2irq);
+
+ if ((l2irq >= 0) && (l2irq <= 3)) {
+ type = mpc52xx_irqx_gettype(l2irq);
+ good_irqchip = &mpc52xx_mainirq_irqchip;
+ } else {
+ good_irqchip = &mpc52xx_main_irqchip;
+ }
+ break;
+
+ case MPC52xx_IRQ_L1_PERP:
+ pr_debug("%s: Peripherals. l2=%x\n", __func__, l2irq);
+ good_irqchip = &mpc52xx_periph_irqchip;
+ break;
+
+ case MPC52xx_IRQ_L1_SDMA:
+ pr_debug("%s: SDMA. l2=%x\n", __func__, l2irq);
+ good_irqchip = &mpc52xx_sdma_irqchip;
+ break;
+
+ default:
+ pr_debug("%s: Error, unknown L1 IRQ (0x%x)\n", __func__, l1irq);
+ printk(KERN_ERR "Unknow IRQ!\n");
+ return -EINVAL;
+ }
+
+ switch (type) {
+ case IRQ_TYPE_EDGE_FALLING:
+ case IRQ_TYPE_EDGE_RISING:
+ good_handle = handle_edge_irq;
+ break;
+ default:
+ good_handle = handle_level_irq;
+ }
+
+ set_irq_chip_and_handler(virq, good_irqchip, good_handle);
+
+ pr_debug("%s: virq=%x, hw=%x. type=%x\n", __func__, virq,
+ (int)irq, type);
+
+ return 0;
+}
+
+static struct irq_host_ops mpc52xx_irqhost_ops = {
+ .match = mpc52xx_irqhost_match,
+ .xlate = mpc52xx_irqhost_xlate,
+ .map = mpc52xx_irqhost_map,
+};
+
+/*
+ * init (public)
+*/
+
+void __init mpc52xx_init_irq(void)
+{
+ u32 intr_ctrl;
+
+ /* Remap the necessary zones */
+ intr = ioremap(MPC52xx_PA(MPC52xx_INTR_OFFSET), MPC52xx_INTR_SIZE);
+ sdma = ioremap(MPC52xx_PA(MPC52xx_SDMA_OFFSET), MPC52xx_SDMA_SIZE);
+
+ if ((intr == NULL) || (sdma == NULL))
+ panic("Can't ioremap PIC/SDMA register or init_irq !");
+
+ /* Disable all interrupt sources. */
+ out_be32(&sdma->IntPend, 0xffffffff); /* 1 means clear pending */
+ out_be32(&sdma->IntMask, 0xffffffff); /* 1 means disabled */
+ out_be32(&intr->per_mask, 0x7ffffc00); /* 1 means disabled */
+ out_be32(&intr->main_mask, 0x00010fff); /* 1 means disabled */
+ intr_ctrl = in_be32(&intr->ctrl);
+ intr_ctrl &= 0x00ff0000; /* Keeps IRQ[0-3] config */
+ intr_ctrl |= 0x0f000000 | /* clear IRQ 0-3 */
+ 0x00001000 | /* MEE master external enable */
+ 0x00000000 | /* 0 means disable IRQ 0-3 */
+ 0x00000001; /* CEb route critical normally */
+ out_be32(&intr->ctrl, intr_ctrl);
+
+ /* Zero a bunch of the priority settings. */
+ out_be32(&intr->per_pri1, 0);
+ out_be32(&intr->per_pri2, 0);
+ out_be32(&intr->per_pri3, 0);
+ out_be32(&intr->main_pri1, 0);
+ out_be32(&intr->main_pri2, 0);
+
+ /*
+ * As last step, add an irq host to translate the real
+ * hw irq information provided by the ofw to linux virq
+ */
+
+ mpc52xx_irqhost =
+ irq_alloc_host(IRQ_HOST_MAP_LINEAR, 0xd0,
+ &mpc52xx_irqhost_ops, -1);
+
+ if (mpc52xx_irqhost)
+ mpc52xx_irqhost->host_data = (void *)find_mpc52xx_picnode();
+}
+
+/*
+ * get_irq (public)
+*/
+unsigned int mpc52xx_get_irq(void)
+{
+ u32 status;
+ int irq = NO_IRQ_IGNORE;
+
+ status = in_be32(&intr->enc_status);
+ if (status & 0x00000400) { /* critical */
+ irq = (status >> 8) & 0x3;
+ if (irq == 2) /* high priority peripheral */
+ goto peripheral;
+ irq |=
+ (MPC52xx_IRQ_L1_CRIT << MPC52xx_IRQ_L1_OFFSET) &
+ MPC52xx_IRQ_L1_MASK;
+ } else if (status & 0x00200000) { /* main */
+ irq = (status >> 16) & 0x1f;
+ if (irq == 4) /* low priority peripheral */
+ goto peripheral;
+ irq |=
+ (MPC52xx_IRQ_L1_MAIN << MPC52xx_IRQ_L1_OFFSET) &
+ MPC52xx_IRQ_L1_MASK;
+ } else if (status & 0x20000000) { /* peripheral */
+ peripheral:
+ irq = (status >> 24) & 0x1f;
+ if (irq == 0) { /* bestcomm */
+ status = in_be32(&sdma->IntPend);
+ irq = ffs(status) - 1;
+ irq |=
+ (MPC52xx_IRQ_L1_SDMA << MPC52xx_IRQ_L1_OFFSET) &
+ MPC52xx_IRQ_L1_MASK;
+ } else
+ irq |=
+ (MPC52xx_IRQ_L1_PERP << MPC52xx_IRQ_L1_OFFSET) &
+ MPC52xx_IRQ_L1_MASK;
+
+ }
+
+ pr_debug("%s: irq=%x. virq=%d\n", __func__, irq,
+ irq_linear_revmap(mpc52xx_irqhost, irq));
+
+ return irq_linear_revmap(mpc52xx_irqhost, irq);
+}
--- a/arch/powerpc/sysdev/Makefile 2006-10-25 19:07:24.000000000 +0200
+++ b/arch/powerpc/sysdev/Makefile 2006-10-31 19:56:41.000000000 +0100
@@ -13,6 +13,7 @@ obj-$(CONFIG_FSL_SOC) += fsl_soc.o
obj-$(CONFIG_PPC_TODC) += todc.o
obj-$(CONFIG_TSI108_BRIDGE) += tsi108_pci.o tsi108_dev.o
obj-$(CONFIG_QUICC_ENGINE) += qe_lib/
+obj-$(CONFIG_PPC_MPC52xx_PIC) += mpc52xx_pic.o
ifeq ($(CONFIG_PPC_MERGE),y)
obj-$(CONFIG_PPC_I8259) += i8259.o
--- a/include/asm-powerpc/mpc52xx.h 1970-01-01 01:00:00.000000000 +0100
+++ b/include/asm-powerpc/mpc52xx.h 2006-10-31 12:31:55.000000000 +0100
@@ -0,0 +1,373 @@
+/*
+ *
+ * Prototypes, etc. for the Freescale MPC52xx embedded cpu chips
+ * May need to be cleaned as the port goes on ...
+ *
+ * Copyright (C) 2004-2005 Sylvain Munaut <tnt@246tNt.com>
+ * Copyright (C) 2003 MontaVista, Software, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#ifndef __ASM_POWERPC_MPC52xx_H__
+#define __ASM_POWERPC_MPC52xx_H__
+
+#ifndef __ASSEMBLY__
+#include <asm/types.h>
+#include <asm/prom.h>
+
+#endif /* __ASSEMBLY__ */
+
+#ifdef CONFIG_PCI
+#define _IO_BASE isa_io_base
+#define _ISA_MEM_BASE isa_mem_base
+#define PCI_DRAM_OFFSET pci_dram_offset
+#else
+#define _IO_BASE 0
+#define _ISA_MEM_BASE 0
+#define PCI_DRAM_OFFSET 0
+#endif
+
+/*
======================================================================== */
+/* Main registers/struct addresses
*/
+/*
======================================================================== */
+
+/* MBAR position */
+#define MPC52xx_MBAR 0xf0000000 /* Phys address */
+#define MPC52xx_MBAR_VIRT 0xf0000000 /* Virt address */
+#define MPC52xx_MBAR_SIZE 0x00010000
+
+#define MPC52xx_PA(x) ((phys_addr_t)(MPC52xx_MBAR + (x)))
+#define MPC52xx_VA(x) ((void __iomem *)(MPC52xx_MBAR_VIRT + (x)))
+
+/* Registers zone offset/size */
+#define MPC52xx_MMAP_CTL_OFFSET 0x0000
+#define MPC52xx_MMAP_CTL_SIZE 0x068
+#define MPC52xx_SDRAM_OFFSET 0x0100
+#define MPC52xx_SDRAM_SIZE 0x010
+#define MPC52xx_CDM_OFFSET 0x0200
+#define MPC52xx_CDM_SIZE 0x038
+#define MPC52xx_INTR_OFFSET 0x0500
+#define MPC52xx_INTR_SIZE 0x04c
+#define MPC52xx_GPTx_OFFSET(x) (0x0600 + ((x)<<4))
+#define MPC52xx_GPT_SIZE 0x010
+#define MPC52xx_RTC_OFFSET 0x0800
+#define MPC52xx_RTC_SIZE 0x024
+#define MPC52xx_GPIO_OFFSET 0x0b00
+#define MPC52xx_GPIO_SIZE 0x040
+#define MPC52xx_GPIO_WKUP_OFFSET 0x0c00
+#define MPC52xx_GPIO_WKUP_SIZE 0x028
+#define MPC52xx_PCI_OFFSET 0x0d00
+#define MPC52xx_PCI_SIZE 0x100
+#define MPC52xx_SDMA_OFFSET 0x1200
+#define MPC52xx_SDMA_SIZE 0x100
+#define MPC52xx_XLB_OFFSET 0x1f00
+#define MPC52xx_XLB_SIZE 0x100
+#define MPC52xx_PSCx_OFFSET(x) (((x)!=6)?(0x1e00+((x)<<9)):0x2c00)
+#define MPC52xx_PSC_SIZE 0x0a0
+
+/* SRAM used for SDMA */
+#define MPC52xx_SRAM_OFFSET 0x8000
+#define MPC52xx_SRAM_SIZE 0x4000
+
+/*
======================================================================== */
+/* IRQ mapping
*/
+/*
======================================================================== */
+
+#define MPC52xx_IRQ_L1_CRIT (0)
+#define MPC52xx_IRQ_L1_MAIN (1)
+#define MPC52xx_IRQ_L1_PERP (2)
+#define MPC52xx_IRQ_L1_SDMA (3)
+
+#define MPC52xx_IRQ_L1_OFFSET (6)
+#define MPC52xx_IRQ_L1_MASK (0x00c0)
+
+#define MPC52xx_IRQ_L2_OFFSET (0)
+#define MPC52xx_IRQ_L2_MASK (0x003f)
+
+/*
+ * 24 peripherals ints
+ * + 16 mains ints
+ * + 4 crit
+ * + 16 bestcomm task
+ * = 64
+*/
+#define MPC52xx_IRQ_MAXCOUNT (64)
+
+/*
======================================================================== */
+/* Structures mapping of some unit register set
*/
+/*
======================================================================== */
+
+#ifndef __ASSEMBLY__
+
+/* Memory Mapping Control */
+struct mpc52xx_mmap_ctl {
+ u32 mbar; /* MMAP_CTRL + 0x00 */
+
+ u32 cs0_start; /* MMAP_CTRL + 0x04 */
+ u32 cs0_stop; /* MMAP_CTRL + 0x08 */
+ u32 cs1_start; /* MMAP_CTRL + 0x0c */
+ u32 cs1_stop; /* MMAP_CTRL + 0x10 */
+ u32 cs2_start; /* MMAP_CTRL + 0x14 */
+ u32 cs2_stop; /* MMAP_CTRL + 0x18 */
+ u32 cs3_start; /* MMAP_CTRL + 0x1c */
+ u32 cs3_stop; /* MMAP_CTRL + 0x20 */
+ u32 cs4_start; /* MMAP_CTRL + 0x24 */
+ u32 cs4_stop; /* MMAP_CTRL + 0x28 */
+ u32 cs5_start; /* MMAP_CTRL + 0x2c */
+ u32 cs5_stop; /* MMAP_CTRL + 0x30 */
+
+ u32 sdram0; /* MMAP_CTRL + 0x34 */
+ u32 sdram1; /* MMAP_CTRL + 0X38 */
+
+ u32 reserved[4]; /* MMAP_CTRL + 0x3c .. 0x48 */
+
+ u32 boot_start; /* MMAP_CTRL + 0x4c */
+ u32 boot_stop; /* MMAP_CTRL + 0x50 */
+
+ u32 ipbi_ws_ctrl; /* MMAP_CTRL + 0x54 */
+
+ u32 cs6_start; /* MMAP_CTRL + 0x58 */
+ u32 cs6_stop; /* MMAP_CTRL + 0x5c */
+ u32 cs7_start; /* MMAP_CTRL + 0x60 */
+ u32 cs7_stop; /* MMAP_CTRL + 0x64 */
+};
+
+/* SDRAM control */
+struct mpc52xx_sdram {
+ u32 mode; /* SDRAM + 0x00 */
+ u32 ctrl; /* SDRAM + 0x04 */
+ u32 config1; /* SDRAM + 0x08 */
+ u32 config2; /* SDRAM + 0x0c */
+};
+
+/* Interrupt controller */
+struct mpc52xx_intr {
+ u32 per_mask; /* INTR + 0x00 */
+ u32 per_pri1; /* INTR + 0x04 */
+ u32 per_pri2; /* INTR + 0x08 */
+ u32 per_pri3; /* INTR + 0x0c */
+ u32 ctrl; /* INTR + 0x10 */
+ u32 main_mask; /* INTR + 0x14 */
+ u32 main_pri1; /* INTR + 0x18 */
+ u32 main_pri2; /* INTR + 0x1c */
+ u32 reserved1; /* INTR + 0x20 */
+ u32 enc_status; /* INTR + 0x24 */
+ u32 crit_status; /* INTR + 0x28 */
+ u32 main_status; /* INTR + 0x2c */
+ u32 per_status; /* INTR + 0x30 */
+ u32 reserved2; /* INTR + 0x34 */
+ u32 per_error; /* INTR + 0x38 */
+};
+
+/* SDMA */
+struct mpc52xx_sdma {
+ u32 taskBar; /* SDMA + 0x00 */
+ u32 currentPointer; /* SDMA + 0x04 */
+ u32 endPointer; /* SDMA + 0x08 */
+ u32 variablePointer; /* SDMA + 0x0c */
+
+ u8 IntVect1; /* SDMA + 0x10 */
+ u8 IntVect2; /* SDMA + 0x11 */
+ u16 PtdCntrl; /* SDMA + 0x12 */
+
+ u32 IntPend; /* SDMA + 0x14 */
+ u32 IntMask; /* SDMA + 0x18 */
+
+ u16 tcr[16]; /* SDMA + 0x1c .. 0x3a */
+
+ u8 ipr[32]; /* SDMA + 0x3c .. 0x5b */
+
+ u32 cReqSelect; /* SDMA + 0x5c */
+ u32 task_size0; /* SDMA + 0x60 */
+ u32 task_size1; /* SDMA + 0x64 */
+ u32 MDEDebug; /* SDMA + 0x68 */
+ u32 ADSDebug; /* SDMA + 0x6c */
+ u32 Value1; /* SDMA + 0x70 */
+ u32 Value2; /* SDMA + 0x74 */
+ u32 Control; /* SDMA + 0x78 */
+ u32 Status; /* SDMA + 0x7c */
+ u32 PTDDebug; /* SDMA + 0x80 */
+};
+
+/* GPT */
+struct mpc52xx_gpt {
+ u32 mode; /* GPTx + 0x00 */
+ u32 count; /* GPTx + 0x04 */
+ u32 pwm; /* GPTx + 0x08 */
+ u32 status; /* GPTx + 0X0c */
+};
+
+/* RTC */
+struct mpc52xx_rtc {
+ u32 time_set; /* RTC + 0x00 */
+ u32 date_set; /* RTC + 0x04 */
+ u32 stopwatch; /* RTC + 0x08 */
+ u32 int_enable; /* RTC + 0x0c */
+ u32 time; /* RTC + 0x10 */
+ u32 date; /* RTC + 0x14 */
+ u32 stopwatch_intr; /* RTC + 0x18 */
+ u32 bus_error; /* RTC + 0x1c */
+ u32 dividers; /* RTC + 0x20 */
+};
+
+/* GPIO */
+struct mpc52xx_gpio {
+ u32 port_config; /* GPIO + 0x00 */
+ u32 simple_gpioe; /* GPIO + 0x04 */
+ u32 simple_ode; /* GPIO + 0x08 */
+ u32 simple_ddr; /* GPIO + 0x0c */
+ u32 simple_dvo; /* GPIO + 0x10 */
+ u32 simple_ival; /* GPIO + 0x14 */
+ u8 outo_gpioe; /* GPIO + 0x18 */
+ u8 reserved1[3]; /* GPIO + 0x19 */
+ u8 outo_dvo; /* GPIO + 0x1c */
+ u8 reserved2[3]; /* GPIO + 0x1d */
+ u8 sint_gpioe; /* GPIO + 0x20 */
+ u8 reserved3[3]; /* GPIO + 0x21 */
+ u8 sint_ode; /* GPIO + 0x24 */
+ u8 reserved4[3]; /* GPIO + 0x25 */
+ u8 sint_ddr; /* GPIO + 0x28 */
+ u8 reserved5[3]; /* GPIO + 0x29 */
+ u8 sint_dvo; /* GPIO + 0x2c */
+ u8 reserved6[3]; /* GPIO + 0x2d */
+ u8 sint_inten; /* GPIO + 0x30 */
+ u8 reserved7[3]; /* GPIO + 0x31 */
+ u16 sint_itype; /* GPIO + 0x34 */
+ u16 reserved8; /* GPIO + 0x36 */
+ u8 gpio_control; /* GPIO + 0x38 */
+ u8 reserved9[3]; /* GPIO + 0x39 */
+ u8 sint_istat; /* GPIO + 0x3c */
+ u8 sint_ival; /* GPIO + 0x3d */
+ u8 bus_errs; /* GPIO + 0x3e */
+ u8 reserved10; /* GPIO + 0x3f */
+};
+
+#define MPC52xx_GPIO_PSC_CONFIG_UART_WITHOUT_CD 4
+#define MPC52xx_GPIO_PSC_CONFIG_UART_WITH_CD 5
+#define MPC52xx_GPIO_PCI_DIS (1<<15)
+
+/* GPIO with WakeUp*/
+struct mpc52xx_gpio_wkup {
+ u8 wkup_gpioe; /* GPIO_WKUP + 0x00 */
+ u8 reserved1[3]; /* GPIO_WKUP + 0x03 */
+ u8 wkup_ode; /* GPIO_WKUP + 0x04 */
+ u8 reserved2[3]; /* GPIO_WKUP + 0x05 */
+ u8 wkup_ddr; /* GPIO_WKUP + 0x08 */
+ u8 reserved3[3]; /* GPIO_WKUP + 0x09 */
+ u8 wkup_dvo; /* GPIO_WKUP + 0x0C */
+ u8 reserved4[3]; /* GPIO_WKUP + 0x0D */
+ u8 wkup_inten; /* GPIO_WKUP + 0x10 */
+ u8 reserved5[3]; /* GPIO_WKUP + 0x11 */
+ u8 wkup_iinten; /* GPIO_WKUP + 0x14 */
+ u8 reserved6[3]; /* GPIO_WKUP + 0x15 */
+ u16 wkup_itype; /* GPIO_WKUP + 0x18 */
+ u8 reserved7[2]; /* GPIO_WKUP + 0x1A */
+ u8 wkup_maste; /* GPIO_WKUP + 0x1C */
+ u8 reserved8[3]; /* GPIO_WKUP + 0x1D */
+ u8 wkup_ival; /* GPIO_WKUP + 0x20 */
+ u8 reserved9[3]; /* GPIO_WKUP + 0x21 */
+ u8 wkup_istat; /* GPIO_WKUP + 0x24 */
+ u8 reserved10[3]; /* GPIO_WKUP + 0x25 */
+};
+
+/* XLB Bus control */
+struct mpc52xx_xlb {
+ u8 reserved[0x40];
+ u32 config; /* XLB + 0x40 */
+ u32 version; /* XLB + 0x44 */
+ u32 status; /* XLB + 0x48 */
+ u32 int_enable; /* XLB + 0x4c */
+ u32 addr_capture; /* XLB + 0x50 */
+ u32 bus_sig_capture; /* XLB + 0x54 */
+ u32 addr_timeout; /* XLB + 0x58 */
+ u32 data_timeout; /* XLB + 0x5c */
+ u32 bus_act_timeout; /* XLB + 0x60 */
+ u32 master_pri_enable; /* XLB + 0x64 */
+ u32 master_priority; /* XLB + 0x68 */
+ u32 base_address; /* XLB + 0x6c */
+ u32 snoop_window; /* XLB + 0x70 */
+};
+
+#define MPC52xx_XLB_CFG_PLDIS (1 << 31)
+#define MPC52xx_XLB_CFG_SNOOP (1 << 15)
+
+/* Clock Distribution control */
+struct mpc52xx_cdm {
+ u32 jtag_id; /* CDM + 0x00 reg0 read only */
+ u32 rstcfg; /* CDM + 0x04 reg1 read only */
+ u32 breadcrumb; /* CDM + 0x08 reg2 */
+
+ u8 mem_clk_sel; /* CDM + 0x0c reg3 byte0 */
+ u8 xlb_clk_sel; /* CDM + 0x0d reg3 byte1 read only */
+ u8 ipb_clk_sel; /* CDM + 0x0e reg3 byte2 */
+ u8 pci_clk_sel; /* CDM + 0x0f reg3 byte3 */
+
+ u8 ext_48mhz_en; /* CDM + 0x10 reg4 byte0 */
+ u8 fd_enable; /* CDM + 0x11 reg4 byte1 */
+ u16 fd_counters; /* CDM + 0x12 reg4 byte2,3 */
+
+ u32 clk_enables; /* CDM + 0x14 reg5 */
+
+ u8 osc_disable; /* CDM + 0x18 reg6 byte0 */
+ u8 reserved0[3]; /* CDM + 0x19 reg6 byte1,2,3 */
+
+ u8 ccs_sleep_enable; /* CDM + 0x1c reg7 byte0 */
+ u8 osc_sleep_enable; /* CDM + 0x1d reg7 byte1 */
+ u8 reserved1; /* CDM + 0x1e reg7 byte2 */
+ u8 ccs_qreq_test; /* CDM + 0x1f reg7 byte3 */
+
+ u8 soft_reset; /* CDM + 0x20 u8 byte0 */
+ u8 no_ckstp; /* CDM + 0x21 u8 byte0 */
+ u8 reserved2[2]; /* CDM + 0x22 u8 byte1,2,3 */
+
+ u8 pll_lock; /* CDM + 0x24 reg9 byte0 */
+ u8 pll_looselock; /* CDM + 0x25 reg9 byte1 */
+ u8 pll_sm_lockwin; /* CDM + 0x26 reg9 byte2 */
+ u8 reserved3; /* CDM + 0x27 reg9 byte3 */
+
+ u16 reserved4; /* CDM + 0x28 reg10 byte0,1 */
+ u16 mclken_div_psc1; /* CDM + 0x2a reg10 byte2,3 */
+
+ u16 reserved5; /* CDM + 0x2c reg11 byte0,1 */
+ u16 mclken_div_psc2; /* CDM + 0x2e reg11 byte2,3 */
+
+ u16 reserved6; /* CDM + 0x30 reg12 byte0,1 */
+ u16 mclken_div_psc3; /* CDM + 0x32 reg12 byte2,3 */
+
+ u16 reserved7; /* CDM + 0x34 reg13 byte0,1 */
+ u16 mclken_div_psc6; /* CDM + 0x36 reg13 byte2,3 */
+};
+
+#endif /* __ASSEMBLY__ */
+
+/*
========================================================================= */
+/* Prototypes for MPC52xx syslib
*/
+/*
========================================================================= */
+
+#ifndef __ASSEMBLY__
+
+extern void mpc52xx_init_irq(void);
+extern unsigned int mpc52xx_get_irq(void);
+
+static inline struct device_node *find_mpc52xx_picnode(void)
+{
+ return of_find_compatible_node(NULL, "interrupt-controller",
+ "mpc5200-pic");
+}
+
+ /* Matching of PSC function */
+struct mpc52xx_psc_func {
+ int id;
+ char *func;
+};
+
+extern int mpc52xx_match_psc_function(int psc_idx, const char *func);
+extern struct mpc52xx_psc_func mpc52xx_psc_functions[];
+ /* This array is to be defined in platform file */
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* _ASM_POWERPC_MPC52xx_H__ */
[-- Attachment #2: nd.vcf --]
[-- Type: text/x-vcard, Size: 249 bytes --]
begin:vcard
fn:Nicolas DET ( bplan GmbH )
n:DET;Nicolas
org:bplan GmbH
adr:;;;;;;Germany
email;internet:nd@bplan-gmbh.de
title:Software Entwicklung
tel;work:+49 6171 9187 - 31
x-mozilla-html:FALSE
url:http://www.bplan-gmbh.de
version:2.1
end:vcard
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