* Re: powerpc: "unable to handle .. paging request" during IPR probe
From: Josh Boyer @ 2006-11-01 19:08 UTC (permalink / raw)
To: John Rose; +Cc: External List, Brian King
In-Reply-To: <1162407611.28335.27.camel@sinatra.austin.ibm.com>
On Wed, 2006-11-01 at 13:00 -0600, John Rose wrote:
> Anyone else seen this crash during boot on pseries? This is 2.6.19-rc4
> with 4k pages.
I think so. Try changing module_init(ata_init) to subsys_init(ata_init)
in drivers/ata/libata-core.c
josh
^ permalink raw reply
* Re: powerpc: "unable to handle .. paging request" during IPR probe
From: John Rose @ 2006-11-01 19:45 UTC (permalink / raw)
To: Josh Boyer; +Cc: External List, Brian King
In-Reply-To: <1162408093.18733.6.camel@zod.rchland.ibm.com>
> I think so. Try changing module_init(ata_init) to subsys_init(ata_init)
> in drivers/ata/libata-core.c
I gave it a try, but still seeing the same crash :( Have you observed
this fix working?
Thanks-
John
^ permalink raw reply
* Re: [RFC] Current Lite5200b patchset
From: Jon Loeliger @ 2006-11-01 19:47 UTC (permalink / raw)
To: Grant Likely; +Cc: linuxppc-embedded@ozlabs.org
In-Reply-To: <11623703962380-git-send-email-grant.likely@secretlab.ca>
On Wed, 2006-11-01 at 02:39, Grant Likely wrote:
> You'll also need to get the lite5200 device tree patch for u-boot off the
> u-boot-users mailing list, and the device tree compiler from www.jdl.com.
>
> Device tree is compiled w/:
> $ dtc -V 0x10 -f -O dtb arch/powerpc/boot/dts/lite5200b.dts > lite5200b.dtb
And note that I just made -V 0x10 the default!
jdl
^ permalink raw reply
* [PATCH/RFC] powerpc: Add MPC5200 Interrupt Controller support.
From: Nicolas DET @ 2006-11-01 20:27 UTC (permalink / raw)
To: linuxppc-dev, benh, sl, linuxppc-embedded
[-- Attachment #1: Type: text/plain, Size: 286 bytes --]
This patch add MPC52xx Interrupt controller for ARCH=powerpc.
It includes the main code in arch/powerpc/sysdev/ ad well as an header
file in include/asm-powerpc.
PS: I did not success to properly inline the file using thrunderbird.
Signed-off-by: Nicolas DET <nd@bplan-gmbh.de>
[-- Attachment #2: archpowerpc_mpc52x.patch --]
[-- Type: text/plain, Size: 24485 bytes --]
--- a/arch/powerpc/sysdev/mpc52xx_pic.c 1970-01-01 01:00:00.000000000 +0100
+++ b/arch/powerpc/sysdev/mpc52xx_pic.c 2006-11-01 21:16:40.000000000 +0100
@@ -0,0 +1,566 @@
+/*
+ *
+ * Programmable Interrupt Controller functions for the Freescale MPC52xx.
+ *
+ * Copyright (C) 2006 bplan GmbH
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ *
+ */
+
+#undef DEBUG
+
+#include <linux/stddef.h>
+#include <linux/init.h>
+#include <linux/sched.h>
+#include <linux/signal.h>
+#include <linux/stddef.h>
+#include <linux/delay.h>
+#include <linux/irq.h>
+#include <linux/hardirq.h>
+
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <asm/system.h>
+#include <asm/irq.h>
+#include <asm/prom.h>
+#include <asm/mpc52xx.h>
+
+/*
+ *
+*/
+
+static struct mpc52xx_intr __iomem *intr;
+static struct mpc52xx_sdma __iomem *sdma;
+static struct irq_host *mpc52xx_irqhost = NULL;
+
+static unsigned char mpc52xx_map_senses[4] = {
+ IRQ_TYPE_LEVEL_HIGH,
+ IRQ_TYPE_EDGE_FALLING,
+ IRQ_TYPE_EDGE_RISING,
+ IRQ_TYPE_LEVEL_LOW,
+};
+
+/*
+ *
+*/
+
+static inline void io_be_setbit(u32 __iomem *addr, int bitno)
+{
+ out_be32(addr, in_be32(addr) | (1 << bitno) );
+}
+
+static inline void io_be_clrbit(u32 __iomem *addr, int bitno)
+{
+ out_be32(addr, in_be32(addr) & ~(1 << bitno));
+}
+
+static inline struct device_node *find_mpc52xx_picnode(void)
+{
+ return of_find_compatible_node(NULL, "interrupt-controller",
+ "mpc5200-pic");
+}
+
+static inline struct device_node *find_mpc52xx_sdmanode(void)
+{
+ return of_find_compatible_node(NULL, "dma-controller",
+ "mpc5200-bestcomm");
+}
+
+/*
+ * Critial interrupt irq_chip
+*/
+static void mpc52xx_crit_mask(unsigned int virq)
+{
+ int irq;
+ int l2irq;
+
+ irq = irq_map[virq].hwirq;
+ l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
+
+ pr_debug("%s: irq=%x, l2=%d\n", __func__, irq, l2irq);
+
+ BUG_ON(l2irq != 0);
+
+ io_be_clrbit(&intr->ctrl, 11);
+}
+
+static void mpc52xx_crit_unmask(unsigned int virq)
+{
+ int irq;
+ int l2irq;
+
+ irq = irq_map[virq].hwirq;
+ l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
+
+ pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
+
+ BUG_ON(l2irq != 0);
+
+ io_be_setbit(&intr->ctrl, 11);
+}
+
+static void mpc52xx_crit_ack(unsigned int virq)
+{
+ int irq;
+ int l2irq;
+
+ irq = irq_map[virq].hwirq;
+ l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
+
+ pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
+
+ BUG_ON(l2irq != 0);
+
+ io_be_setbit(&intr->ctrl, 27);
+}
+
+static struct irq_chip mpc52xx_crit_irqchip = {
+ .typename = "MPC52xx IRQ0",
+ .mask = mpc52xx_crit_mask,
+ .unmask = mpc52xx_crit_unmask,
+ .ack = mpc52xx_crit_ack,
+};
+
+/*
+ * IRQ[1-3] interrupt irq_chip
+*/
+
+static void mpc52xx_mainirq_mask(unsigned int virq)
+{
+ int irq;
+ int l2irq;
+
+ irq = irq_map[virq].hwirq;
+ l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
+
+ pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
+
+ io_be_clrbit(&intr->ctrl, 11 - l2irq);
+}
+
+static void mpc52xx_mainirq_unmask(unsigned int virq)
+{
+ int irq;
+ int l2irq;
+
+ irq = irq_map[virq].hwirq;
+ l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
+
+ pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
+
+ io_be_setbit(&intr->ctrl, 11 - l2irq);
+}
+
+static void mpc52xx_mainirq_ack(unsigned int virq)
+{
+ int irq;
+ int l2irq;
+
+ irq = irq_map[virq].hwirq;
+ l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
+
+ pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
+
+ io_be_setbit(&intr->ctrl, 27-l2irq);
+}
+
+static struct irq_chip mpc52xx_mainirq_irqchip = {
+ .typename = " MPC52xx IRQ[1-3] ",
+ .mask = mpc52xx_mainirq_mask,
+ .unmask = mpc52xx_mainirq_unmask,
+ .ack = mpc52xx_mainirq_ack,
+};
+
+/*
+ * Main interrupt irq_chip
+*/
+
+static void mpc52xx_main_mask(unsigned int virq)
+{
+ int irq;
+ int l2irq;
+
+ irq = irq_map[virq].hwirq;
+ l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
+
+ pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
+
+ io_be_setbit(&intr->main_mask, 15 - l2irq);
+}
+
+static void mpc52xx_main_unmask(unsigned int virq)
+{
+ int irq;
+ int l2irq;
+
+ irq = irq_map[virq].hwirq;
+ l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
+
+ pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
+
+ io_be_clrbit(&intr->main_mask, 15 - l2irq);
+}
+
+static struct irq_chip mpc52xx_main_irqchip = {
+ .typename = "MPC52xx Main",
+ .mask = mpc52xx_main_mask,
+ .mask_ack = mpc52xx_main_mask,
+ .unmask = mpc52xx_main_unmask,
+};
+
+/*
+ * Peripherals interrupt irq_chip
+*/
+
+static void mpc52xx_periph_mask(unsigned int virq)
+{
+ int irq;
+ int l2irq;
+
+ irq = irq_map[virq].hwirq;
+ l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
+
+ pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
+
+ io_be_setbit(&intr->per_mask, 31 - l2irq);
+}
+
+static void mpc52xx_periph_unmask(unsigned int virq)
+{
+ int irq;
+ int l2irq;
+
+ irq = irq_map[virq].hwirq;
+ l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
+
+ pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
+
+ io_be_clrbit(&intr->per_mask, 31 - l2irq);
+}
+
+static struct irq_chip mpc52xx_periph_irqchip = {
+ .typename = "MPC52xx Peripherals",
+ .mask = mpc52xx_periph_mask,
+ .mask_ack = mpc52xx_periph_mask,
+ .unmask = mpc52xx_periph_unmask,
+};
+
+/*
+ * SDMA interrupt irq_chip
+*/
+
+static void mpc52xx_sdma_mask(unsigned int virq)
+{
+ int irq;
+ int l2irq;
+
+ irq = irq_map[virq].hwirq;
+ l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
+
+ pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
+
+ io_be_setbit(&sdma->IntMask, l2irq);
+}
+
+static void mpc52xx_sdma_unmask(unsigned int virq)
+{
+ int irq;
+ int l2irq;
+
+ irq = irq_map[virq].hwirq;
+ l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
+
+ pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
+
+ io_be_clrbit(&sdma->IntMask, l2irq);
+}
+
+static void mpc52xx_sdma_ack(unsigned int virq)
+{
+ int irq;
+ int l2irq;
+
+ irq = irq_map[virq].hwirq;
+ l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
+
+ pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
+
+ out_be32(&sdma->IntPend, 1 << l2irq);
+}
+
+static struct irq_chip mpc52xx_sdma_irqchip = {
+ .typename = "MPC52xx SDMA",
+ .mask = mpc52xx_sdma_mask,
+ .unmask = mpc52xx_sdma_unmask,
+ .ack = mpc52xx_sdma_ack,
+};
+
+/*
+ * irq_host
+*/
+
+static int mpc52xx_irqhost_match(struct irq_host *h, struct device_node *node)
+{
+ pr_debug("%s: %p vs %p\n", __func__, find_mpc52xx_picnode(), node);
+ return mpc52xx_irqhost->host_data == node;
+}
+
+static int mpc52xx_irqhost_xlate(struct irq_host *h, struct device_node *ct,
+ u32 * intspec, unsigned int intsize,
+ irq_hw_number_t * out_hwirq,
+ unsigned int *out_flags)
+{
+ int intrvect_l1;
+ int intrvect_l2;
+ int intrvect_type;
+ int intrvect_linux;
+
+ if (intsize != 3)
+ return -1;
+
+ intrvect_l1 = (int)intspec[0];
+ intrvect_l2 = (int)intspec[1];
+ intrvect_type = (int)intspec[2];
+
+ intrvect_linux =
+ (intrvect_l1 << MPC52xx_IRQ_L1_OFFSET) & MPC52xx_IRQ_L1_MASK;
+ intrvect_linux |=
+ (intrvect_l2 << MPC52xx_IRQ_L2_OFFSET) & MPC52xx_IRQ_L2_MASK;
+
+ pr_debug("return %x, l1=%d, l2=%d\n", intrvect_linux, intrvect_l1,
+ intrvect_l2);
+
+ *out_hwirq = intrvect_linux;
+ *out_flags = mpc52xx_map_senses[intrvect_type];
+
+ return 0;
+}
+
+/*
+ * this function retrieves the correct IRQ type out
+ * of the MPC regs
+ * Only externals IRQs needs this
+*/
+static int mpc52xx_irqx_gettype(int irq)
+{
+ int type;
+ u32 ctrl_reg;
+
+ ctrl_reg = in_be32(&intr->ctrl);
+ type = (ctrl_reg >> (22 - irq * 2)) & 0x3;
+
+ return mpc52xx_map_senses[type];
+}
+
+static int mpc52xx_irqhost_map(struct irq_host *h, unsigned int virq,
+ irq_hw_number_t irq)
+{
+ int l1irq;
+ int l2irq;
+ struct irq_chip *good_irqchip;
+ void *good_handle;
+ int type;
+
+ l1irq = (irq & MPC52xx_IRQ_L1_MASK) >> MPC52xx_IRQ_L1_OFFSET;
+ l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
+
+ /*
+ * Most of ours IRQs will be level low
+ * Only external IRQs on some platform may be others
+ */
+ type = IRQ_TYPE_LEVEL_LOW;
+
+ switch (l1irq) {
+ case MPC52xx_IRQ_L1_CRIT:
+ pr_debug("%s: Critical. l2=%x\n", __func__, l2irq);
+
+ BUG_ON(l2irq != 0);
+
+ type = mpc52xx_irqx_gettype(l2irq);
+ good_irqchip = &mpc52xx_crit_irqchip;
+ break;
+
+ case MPC52xx_IRQ_L1_MAIN:
+ pr_debug("%s: Main IRQ[1-3] l2=%x\n", __func__, l2irq);
+
+ if ((l2irq >= 0) && (l2irq <= 3)) {
+ type = mpc52xx_irqx_gettype(l2irq);
+ good_irqchip = &mpc52xx_mainirq_irqchip;
+ } else {
+ good_irqchip = &mpc52xx_main_irqchip;
+ }
+ break;
+
+ case MPC52xx_IRQ_L1_PERP:
+ pr_debug("%s: Peripherals. l2=%x\n", __func__, l2irq);
+ good_irqchip = &mpc52xx_periph_irqchip;
+ break;
+
+ case MPC52xx_IRQ_L1_SDMA:
+ pr_debug("%s: SDMA. l2=%x\n", __func__, l2irq);
+ good_irqchip = &mpc52xx_sdma_irqchip;
+ break;
+
+ default:
+ pr_debug("%s: Error, unknown L1 IRQ (0x%x)\n", __func__, l1irq);
+ printk(KERN_ERR "Unknow IRQ!\n");
+ return -EINVAL;
+ }
+
+ switch (type) {
+ case IRQ_TYPE_EDGE_FALLING:
+ case IRQ_TYPE_EDGE_RISING:
+ good_handle = handle_edge_irq;
+ break;
+ default:
+ good_handle = handle_level_irq;
+ }
+
+ set_irq_chip_and_handler(virq, good_irqchip, good_handle);
+
+ pr_debug("%s: virq=%x, hw=%x. type=%x\n", __func__, virq,
+ (int)irq, type);
+
+ return 0;
+}
+
+static struct irq_host_ops mpc52xx_irqhost_ops = {
+ .match = mpc52xx_irqhost_match,
+ .xlate = mpc52xx_irqhost_xlate,
+ .map = mpc52xx_irqhost_map,
+};
+
+/*
+ * init (public)
+*/
+
+void __init mpc52xx_init_irq(void)
+{
+ struct device_node *picnode;
+ int picnode_regsize;
+ u32 picnode_regoffset;
+
+ struct device_node *sdmanode;
+ int sdmanode_regsize;
+ u32 sdmanode_regoffset;
+
+ u64 size64;
+ int flags;
+
+ u32 intr_ctrl;
+
+ picnode = find_mpc52xx_picnode();
+ sdmanode = find_mpc52xx_sdmanode();
+
+ if ( (picnode == NULL) || (sdmanode == NULL) )
+ return;
+
+ /* Retrieve PIC ressources */
+ picnode_regoffset = (u32) of_get_address(picnode, 0, &size64, &flags);
+ if (picnode_regoffset == 0)
+ return ;
+
+ picnode_regoffset = of_translate_address(picnode, (u32 *) picnode_regoffset);
+ picnode_regsize = (int)size64;
+
+ /* Retrieve SDMA ressources */
+ sdmanode_regoffset = (u32) of_get_address(sdmanode, 0, &size64, &flags);
+ if (sdmanode_regoffset == 0)
+ return ;
+
+ sdmanode_regoffset = of_translate_address(sdmanode, (u32 *) sdmanode_regoffset);
+ sdmanode_regsize = (int)size64;
+
+ /* Remap the necessary zones */
+ intr = ioremap(picnode_regoffset, picnode_regsize);
+ sdma = ioremap(sdmanode_regoffset, sdmanode_regsize);
+
+ if ((intr == NULL) || (sdma == NULL))
+ panic("Can't ioremap PIC/SDMA register or init_irq !");
+
+ printk(KERN_INFO "Remapped MPC52xx PIC at 0x%8.8x\n", picnode_regoffset);
+ printk(KERN_INFO "Remapped MPC52xx SDMA at 0x%8.8x\n", sdmanode_regoffset);
+
+ of_node_put(picnode);
+ of_node_put(sdmanode);
+
+ /* Disable all interrupt sources. */
+ out_be32(&sdma->IntPend, 0xffffffff); /* 1 means clear pending */
+ out_be32(&sdma->IntMask, 0xffffffff); /* 1 means disabled */
+ out_be32(&intr->per_mask, 0x7ffffc00); /* 1 means disabled */
+ out_be32(&intr->main_mask, 0x00010fff); /* 1 means disabled */
+ intr_ctrl = in_be32(&intr->ctrl);
+ intr_ctrl &= 0x00ff0000; /* Keeps IRQ[0-3] config */
+ intr_ctrl |= 0x0f000000 | /* clear IRQ 0-3 */
+ 0x00001000 | /* MEE master external enable */
+ 0x00000000 | /* 0 means disable IRQ 0-3 */
+ 0x00000001; /* CEb route critical normally */
+ out_be32(&intr->ctrl, intr_ctrl);
+
+ /* Zero a bunch of the priority settings. */
+ out_be32(&intr->per_pri1, 0);
+ out_be32(&intr->per_pri2, 0);
+ out_be32(&intr->per_pri3, 0);
+ out_be32(&intr->main_pri1, 0);
+ out_be32(&intr->main_pri2, 0);
+
+ /*
+ * As last step, add an irq host to translate the real
+ * hw irq information provided by the ofw to linux virq
+ */
+
+ mpc52xx_irqhost =
+ irq_alloc_host(IRQ_HOST_MAP_LINEAR, MPC52xx_IRQ_HIGHTESTVIRQ,
+ &mpc52xx_irqhost_ops, -1);
+
+ if (mpc52xx_irqhost)
+ mpc52xx_irqhost->host_data = picnode;
+}
+
+/*
+ * get_irq (public)
+*/
+unsigned int mpc52xx_get_irq(void)
+{
+ u32 status;
+ int irq = NO_IRQ_IGNORE;
+
+ status = in_be32(&intr->enc_status);
+ if (status & 0x00000400) { /* critical */
+ irq = (status >> 8) & 0x3;
+ if (irq == 2) /* high priority peripheral */
+ goto peripheral;
+ irq |=
+ (MPC52xx_IRQ_L1_CRIT << MPC52xx_IRQ_L1_OFFSET) &
+ MPC52xx_IRQ_L1_MASK;
+ } else if (status & 0x00200000) { /* main */
+ irq = (status >> 16) & 0x1f;
+ if (irq == 4) /* low priority peripheral */
+ goto peripheral;
+ irq |=
+ (MPC52xx_IRQ_L1_MAIN << MPC52xx_IRQ_L1_OFFSET) &
+ MPC52xx_IRQ_L1_MASK;
+ } else if (status & 0x20000000) { /* peripheral */
+ peripheral:
+ irq = (status >> 24) & 0x1f;
+ if (irq == 0) { /* bestcomm */
+ status = in_be32(&sdma->IntPend);
+ irq = ffs(status) - 1;
+ irq |=
+ (MPC52xx_IRQ_L1_SDMA << MPC52xx_IRQ_L1_OFFSET) &
+ MPC52xx_IRQ_L1_MASK;
+ } else
+ irq |=
+ (MPC52xx_IRQ_L1_PERP << MPC52xx_IRQ_L1_OFFSET) &
+ MPC52xx_IRQ_L1_MASK;
+
+ }
+
+ pr_debug("%s: irq=%x. virq=%d\n", __func__, irq,
+ irq_linear_revmap(mpc52xx_irqhost, irq));
+
+ return irq_linear_revmap(mpc52xx_irqhost, irq);
+}
--- a/arch/powerpc/sysdev/Makefile 2006-11-01 09:18:43.000000000 +0100
+++ b/arch/powerpc/sysdev/Makefile 2006-10-31 19:56:41.000000000 +0100
@@ -13,6 +13,7 @@ obj-$(CONFIG_FSL_SOC) += fsl_soc.o
obj-$(CONFIG_PPC_TODC) += todc.o
obj-$(CONFIG_TSI108_BRIDGE) += tsi108_pci.o tsi108_dev.o
obj-$(CONFIG_QUICC_ENGINE) += qe_lib/
+obj-$(CONFIG_PPC_MPC52xx_PIC) += mpc52xx_pic.o
ifeq ($(CONFIG_PPC_MERGE),y)
obj-$(CONFIG_PPC_I8259) += i8259.o
--- a/include/asm-powerpc/mpc52xx.h 1970-01-01 01:00:00.000000000 +0100
+++ b/include/asm-powerpc/mpc52xx.h 2006-11-01 21:18:38.000000000 +0100
@@ -0,0 +1,319 @@
+/*
+ *
+ * Prototypes, etc. for the Freescale MPC52xx embedded cpu chips
+ * May need to be cleaned as the port goes on ...
+ *
+ * Copyright (C) 2004-2005 Sylvain Munaut <tnt@246tNt.com>
+ * Copyright (C) 2003 MontaVista, Software, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#ifndef __ASM_POWERPC_MPC52xx_H__
+#define __ASM_POWERPC_MPC52xx_H__
+
+#ifndef __ASSEMBLY__
+#include <asm/types.h>
+#include <asm/prom.h>
+
+#endif /* __ASSEMBLY__ */
+
+/* ======================================================================== */
+/* Main registers/struct addresses */
+/* ======================================================================== */
+
+/* Registers zone offset/size */
+#define MPC52xx_MMAP_CTL_OFFSET 0x0000
+#define MPC52xx_MMAP_CTL_SIZE 0x068
+#define MPC52xx_SDRAM_OFFSET 0x0100
+#define MPC52xx_SDRAM_SIZE 0x010
+#define MPC52xx_CDM_OFFSET 0x0200
+#define MPC52xx_CDM_SIZE 0x038
+#define MPC52xx_INTR_OFFSET 0x0500
+#define MPC52xx_INTR_SIZE 0x04c
+#define MPC52xx_GPTx_OFFSET(x) (0x0600 + ((x)<<4))
+#define MPC52xx_GPT_SIZE 0x010
+#define MPC52xx_RTC_OFFSET 0x0800
+#define MPC52xx_RTC_SIZE 0x024
+#define MPC52xx_GPIO_OFFSET 0x0b00
+#define MPC52xx_GPIO_SIZE 0x040
+#define MPC52xx_GPIO_WKUP_OFFSET 0x0c00
+#define MPC52xx_GPIO_WKUP_SIZE 0x028
+#define MPC52xx_PCI_OFFSET 0x0d00
+#define MPC52xx_PCI_SIZE 0x100
+#define MPC52xx_SDMA_OFFSET 0x1200
+#define MPC52xx_SDMA_SIZE 0x100
+#define MPC52xx_XLB_OFFSET 0x1f00
+#define MPC52xx_XLB_SIZE 0x100
+#define MPC52xx_PSCx_OFFSET(x) (((x)!=6)?(0x1e00+((x)<<9)):0x2c00)
+#define MPC52xx_PSC_SIZE 0x0a0
+
+/* SRAM used for SDMA */
+#define MPC52xx_SRAM_OFFSET 0x8000
+#define MPC52xx_SRAM_SIZE 0x4000
+
+/* ======================================================================== */
+/* IRQ mapping */
+/* ======================================================================== */
+
+#define MPC52xx_IRQ_L1_CRIT (0)
+#define MPC52xx_IRQ_L1_MAIN (1)
+#define MPC52xx_IRQ_L1_PERP (2)
+#define MPC52xx_IRQ_L1_SDMA (3)
+
+#define MPC52xx_IRQ_L1_OFFSET (6)
+#define MPC52xx_IRQ_L1_MASK (0x00c0)
+
+#define MPC52xx_IRQ_L2_OFFSET (0)
+#define MPC52xx_IRQ_L2_MASK (0x003f)
+
+#define MPC52xx_IRQ_HIGHTESTVIRQ (0xd0)
+
+/* ======================================================================== */
+/* Structures mapping of some unit register set */
+/* ======================================================================== */
+
+#ifndef __ASSEMBLY__
+
+/* Memory Mapping Control */
+struct mpc52xx_mmap_ctl {
+ u32 mbar; /* MMAP_CTRL + 0x00 */
+
+ u32 cs0_start; /* MMAP_CTRL + 0x04 */
+ u32 cs0_stop; /* MMAP_CTRL + 0x08 */
+ u32 cs1_start; /* MMAP_CTRL + 0x0c */
+ u32 cs1_stop; /* MMAP_CTRL + 0x10 */
+ u32 cs2_start; /* MMAP_CTRL + 0x14 */
+ u32 cs2_stop; /* MMAP_CTRL + 0x18 */
+ u32 cs3_start; /* MMAP_CTRL + 0x1c */
+ u32 cs3_stop; /* MMAP_CTRL + 0x20 */
+ u32 cs4_start; /* MMAP_CTRL + 0x24 */
+ u32 cs4_stop; /* MMAP_CTRL + 0x28 */
+ u32 cs5_start; /* MMAP_CTRL + 0x2c */
+ u32 cs5_stop; /* MMAP_CTRL + 0x30 */
+
+ u32 sdram0; /* MMAP_CTRL + 0x34 */
+ u32 sdram1; /* MMAP_CTRL + 0X38 */
+
+ u32 reserved[4]; /* MMAP_CTRL + 0x3c .. 0x48 */
+
+ u32 boot_start; /* MMAP_CTRL + 0x4c */
+ u32 boot_stop; /* MMAP_CTRL + 0x50 */
+
+ u32 ipbi_ws_ctrl; /* MMAP_CTRL + 0x54 */
+
+ u32 cs6_start; /* MMAP_CTRL + 0x58 */
+ u32 cs6_stop; /* MMAP_CTRL + 0x5c */
+ u32 cs7_start; /* MMAP_CTRL + 0x60 */
+ u32 cs7_stop; /* MMAP_CTRL + 0x64 */
+};
+
+/* SDRAM control */
+struct mpc52xx_sdram {
+ u32 mode; /* SDRAM + 0x00 */
+ u32 ctrl; /* SDRAM + 0x04 */
+ u32 config1; /* SDRAM + 0x08 */
+ u32 config2; /* SDRAM + 0x0c */
+};
+
+/* Interrupt controller */
+struct mpc52xx_intr {
+ u32 per_mask; /* INTR + 0x00 */
+ u32 per_pri1; /* INTR + 0x04 */
+ u32 per_pri2; /* INTR + 0x08 */
+ u32 per_pri3; /* INTR + 0x0c */
+ u32 ctrl; /* INTR + 0x10 */
+ u32 main_mask; /* INTR + 0x14 */
+ u32 main_pri1; /* INTR + 0x18 */
+ u32 main_pri2; /* INTR + 0x1c */
+ u32 reserved1; /* INTR + 0x20 */
+ u32 enc_status; /* INTR + 0x24 */
+ u32 crit_status; /* INTR + 0x28 */
+ u32 main_status; /* INTR + 0x2c */
+ u32 per_status; /* INTR + 0x30 */
+ u32 reserved2; /* INTR + 0x34 */
+ u32 per_error; /* INTR + 0x38 */
+};
+
+/* SDMA */
+struct mpc52xx_sdma {
+ u32 taskBar; /* SDMA + 0x00 */
+ u32 currentPointer; /* SDMA + 0x04 */
+ u32 endPointer; /* SDMA + 0x08 */
+ u32 variablePointer; /* SDMA + 0x0c */
+
+ u8 IntVect1; /* SDMA + 0x10 */
+ u8 IntVect2; /* SDMA + 0x11 */
+ u16 PtdCntrl; /* SDMA + 0x12 */
+
+ u32 IntPend; /* SDMA + 0x14 */
+ u32 IntMask; /* SDMA + 0x18 */
+
+ u16 tcr[16]; /* SDMA + 0x1c .. 0x3a */
+
+ u8 ipr[32]; /* SDMA + 0x3c .. 0x5b */
+
+ u32 cReqSelect; /* SDMA + 0x5c */
+ u32 task_size0; /* SDMA + 0x60 */
+ u32 task_size1; /* SDMA + 0x64 */
+ u32 MDEDebug; /* SDMA + 0x68 */
+ u32 ADSDebug; /* SDMA + 0x6c */
+ u32 Value1; /* SDMA + 0x70 */
+ u32 Value2; /* SDMA + 0x74 */
+ u32 Control; /* SDMA + 0x78 */
+ u32 Status; /* SDMA + 0x7c */
+ u32 PTDDebug; /* SDMA + 0x80 */
+};
+
+/* GPT */
+struct mpc52xx_gpt {
+ u32 mode; /* GPTx + 0x00 */
+ u32 count; /* GPTx + 0x04 */
+ u32 pwm; /* GPTx + 0x08 */
+ u32 status; /* GPTx + 0X0c */
+};
+
+/* GPIO */
+struct mpc52xx_gpio {
+ u32 port_config; /* GPIO + 0x00 */
+ u32 simple_gpioe; /* GPIO + 0x04 */
+ u32 simple_ode; /* GPIO + 0x08 */
+ u32 simple_ddr; /* GPIO + 0x0c */
+ u32 simple_dvo; /* GPIO + 0x10 */
+ u32 simple_ival; /* GPIO + 0x14 */
+ u8 outo_gpioe; /* GPIO + 0x18 */
+ u8 reserved1[3]; /* GPIO + 0x19 */
+ u8 outo_dvo; /* GPIO + 0x1c */
+ u8 reserved2[3]; /* GPIO + 0x1d */
+ u8 sint_gpioe; /* GPIO + 0x20 */
+ u8 reserved3[3]; /* GPIO + 0x21 */
+ u8 sint_ode; /* GPIO + 0x24 */
+ u8 reserved4[3]; /* GPIO + 0x25 */
+ u8 sint_ddr; /* GPIO + 0x28 */
+ u8 reserved5[3]; /* GPIO + 0x29 */
+ u8 sint_dvo; /* GPIO + 0x2c */
+ u8 reserved6[3]; /* GPIO + 0x2d */
+ u8 sint_inten; /* GPIO + 0x30 */
+ u8 reserved7[3]; /* GPIO + 0x31 */
+ u16 sint_itype; /* GPIO + 0x34 */
+ u16 reserved8; /* GPIO + 0x36 */
+ u8 gpio_control; /* GPIO + 0x38 */
+ u8 reserved9[3]; /* GPIO + 0x39 */
+ u8 sint_istat; /* GPIO + 0x3c */
+ u8 sint_ival; /* GPIO + 0x3d */
+ u8 bus_errs; /* GPIO + 0x3e */
+ u8 reserved10; /* GPIO + 0x3f */
+};
+
+#define MPC52xx_GPIO_PSC_CONFIG_UART_WITHOUT_CD 4
+#define MPC52xx_GPIO_PSC_CONFIG_UART_WITH_CD 5
+#define MPC52xx_GPIO_PCI_DIS (1<<15)
+
+/* GPIO with WakeUp*/
+struct mpc52xx_gpio_wkup {
+ u8 wkup_gpioe; /* GPIO_WKUP + 0x00 */
+ u8 reserved1[3]; /* GPIO_WKUP + 0x03 */
+ u8 wkup_ode; /* GPIO_WKUP + 0x04 */
+ u8 reserved2[3]; /* GPIO_WKUP + 0x05 */
+ u8 wkup_ddr; /* GPIO_WKUP + 0x08 */
+ u8 reserved3[3]; /* GPIO_WKUP + 0x09 */
+ u8 wkup_dvo; /* GPIO_WKUP + 0x0C */
+ u8 reserved4[3]; /* GPIO_WKUP + 0x0D */
+ u8 wkup_inten; /* GPIO_WKUP + 0x10 */
+ u8 reserved5[3]; /* GPIO_WKUP + 0x11 */
+ u8 wkup_iinten; /* GPIO_WKUP + 0x14 */
+ u8 reserved6[3]; /* GPIO_WKUP + 0x15 */
+ u16 wkup_itype; /* GPIO_WKUP + 0x18 */
+ u8 reserved7[2]; /* GPIO_WKUP + 0x1A */
+ u8 wkup_maste; /* GPIO_WKUP + 0x1C */
+ u8 reserved8[3]; /* GPIO_WKUP + 0x1D */
+ u8 wkup_ival; /* GPIO_WKUP + 0x20 */
+ u8 reserved9[3]; /* GPIO_WKUP + 0x21 */
+ u8 wkup_istat; /* GPIO_WKUP + 0x24 */
+ u8 reserved10[3]; /* GPIO_WKUP + 0x25 */
+};
+
+/* XLB Bus control */
+struct mpc52xx_xlb {
+ u8 reserved[0x40];
+ u32 config; /* XLB + 0x40 */
+ u32 version; /* XLB + 0x44 */
+ u32 status; /* XLB + 0x48 */
+ u32 int_enable; /* XLB + 0x4c */
+ u32 addr_capture; /* XLB + 0x50 */
+ u32 bus_sig_capture; /* XLB + 0x54 */
+ u32 addr_timeout; /* XLB + 0x58 */
+ u32 data_timeout; /* XLB + 0x5c */
+ u32 bus_act_timeout; /* XLB + 0x60 */
+ u32 master_pri_enable; /* XLB + 0x64 */
+ u32 master_priority; /* XLB + 0x68 */
+ u32 base_address; /* XLB + 0x6c */
+ u32 snoop_window; /* XLB + 0x70 */
+};
+
+#define MPC52xx_XLB_CFG_PLDIS (1 << 31)
+#define MPC52xx_XLB_CFG_SNOOP (1 << 15)
+
+/* Clock Distribution control */
+struct mpc52xx_cdm {
+ u32 jtag_id; /* CDM + 0x00 reg0 read only */
+ u32 rstcfg; /* CDM + 0x04 reg1 read only */
+ u32 breadcrumb; /* CDM + 0x08 reg2 */
+
+ u8 mem_clk_sel; /* CDM + 0x0c reg3 byte0 */
+ u8 xlb_clk_sel; /* CDM + 0x0d reg3 byte1 read only */
+ u8 ipb_clk_sel; /* CDM + 0x0e reg3 byte2 */
+ u8 pci_clk_sel; /* CDM + 0x0f reg3 byte3 */
+
+ u8 ext_48mhz_en; /* CDM + 0x10 reg4 byte0 */
+ u8 fd_enable; /* CDM + 0x11 reg4 byte1 */
+ u16 fd_counters; /* CDM + 0x12 reg4 byte2,3 */
+
+ u32 clk_enables; /* CDM + 0x14 reg5 */
+
+ u8 osc_disable; /* CDM + 0x18 reg6 byte0 */
+ u8 reserved0[3]; /* CDM + 0x19 reg6 byte1,2,3 */
+
+ u8 ccs_sleep_enable; /* CDM + 0x1c reg7 byte0 */
+ u8 osc_sleep_enable; /* CDM + 0x1d reg7 byte1 */
+ u8 reserved1; /* CDM + 0x1e reg7 byte2 */
+ u8 ccs_qreq_test; /* CDM + 0x1f reg7 byte3 */
+
+ u8 soft_reset; /* CDM + 0x20 u8 byte0 */
+ u8 no_ckstp; /* CDM + 0x21 u8 byte0 */
+ u8 reserved2[2]; /* CDM + 0x22 u8 byte1,2,3 */
+
+ u8 pll_lock; /* CDM + 0x24 reg9 byte0 */
+ u8 pll_looselock; /* CDM + 0x25 reg9 byte1 */
+ u8 pll_sm_lockwin; /* CDM + 0x26 reg9 byte2 */
+ u8 reserved3; /* CDM + 0x27 reg9 byte3 */
+
+ u16 reserved4; /* CDM + 0x28 reg10 byte0,1 */
+ u16 mclken_div_psc1; /* CDM + 0x2a reg10 byte2,3 */
+
+ u16 reserved5; /* CDM + 0x2c reg11 byte0,1 */
+ u16 mclken_div_psc2; /* CDM + 0x2e reg11 byte2,3 */
+
+ u16 reserved6; /* CDM + 0x30 reg12 byte0,1 */
+ u16 mclken_div_psc3; /* CDM + 0x32 reg12 byte2,3 */
+
+ u16 reserved7; /* CDM + 0x34 reg13 byte0,1 */
+ u16 mclken_div_psc6; /* CDM + 0x36 reg13 byte2,3 */
+};
+
+#endif /* __ASSEMBLY__ */
+
+/* ========================================================================= */
+/* Prototypes for MPC52xx syslib */
+/* ========================================================================= */
+
+#ifndef __ASSEMBLY__
+
+extern void mpc52xx_init_irq(void);
+extern unsigned int mpc52xx_get_irq(void);
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* _ASM_POWERPC_MPC52xx_H__ */
^ permalink raw reply
* [PATCH/RFC] powerpc: Add Efika platform support
From: Nicolas DET @ 2006-11-01 20:29 UTC (permalink / raw)
To: linuxppc-dev, benh, sl, linuxppc-embedded
[-- Attachment #1: Type: text/plain, Size: 145 bytes --]
Add Efika platform support
PS: I did not success to properly inline the file using thrunderbird.
Signed-off-by: Nicolas DET <nd@bplan-gmbh.de>
[-- Attachment #2: archpowerpc_efika.patch --]
[-- Type: text/plain, Size: 9908 bytes --]
--- a/arch/powerpc/platforms/efika/setup.c 1970-01-01 01:00:00.000000000 +0100
+++ b/arch/powerpc/platforms/efika/setup.c 2006-11-01 21:16:06.000000000 +0100
@@ -0,0 +1,164 @@
+/*
+ *
+ * Efika 5K2 platform setup
+ * Some code really inspired from the lite5200b platform.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ *
+ */
+
+#include <linux/errno.h>
+#include <linux/sched.h>
+#include <linux/kernel.h>
+#include <linux/ptrace.h>
+#include <linux/slab.h>
+#include <linux/user.h>
+#include <linux/interrupt.h>
+#include <linux/reboot.h>
+#include <linux/init.h>
+#include <linux/utsrelease.h>
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <linux/console.h>
+#include <linux/seq_file.h>
+#include <linux/root_dev.h>
+#include <linux/initrd.h>
+#include <linux/module.h>
+#include <linux/timer.h>
+
+#include <asm/pgtable.h>
+#include <asm/prom.h>
+#include <asm/dma.h>
+#include <asm/machdep.h>
+#include <asm/irq.h>
+#include <asm/sections.h>
+#include <asm/time.h>
+#include <asm/rtas.h>
+#include <asm/of_device.h>
+#include <asm/mpc52xx.h>
+
+#include "efika.h"
+
+static void efika_show_cpuinfo(struct seq_file *m)
+{
+ struct device_node *root;
+ const char *revision = NULL;
+ const char *codegendescription = NULL;
+ const char *codegenvendor = NULL;
+
+ root = of_find_node_by_path("/");
+ if (root) {
+ revision = get_property(root, "revision", NULL);
+ codegendescription =
+ get_property(root, "CODEGEN,description", NULL);
+ codegenvendor = get_property(root, "CODEGEN,vendor", NULL);
+ }
+
+ if (codegendescription)
+ seq_printf(m, "machine\t\t: %s\n", codegendescription);
+ else
+ seq_printf(m, "machine\t\t: Efika\n");
+
+ if (revision)
+ seq_printf(m, "revision\t: %s\n", revision);
+
+ if (codegenvendor)
+ seq_printf(m, "vendor\t\t: %s\n", codegenvendor);
+}
+
+static void __init efika_setup_arch(void)
+{
+ rtas_initialize();
+
+#ifdef CONFIG_BLK_DEV_INITRD
+ initrd_below_start_ok = 1;
+
+ if (initrd_start)
+ ROOT_DEV = Root_RAM0;
+ else
+#endif
+ ROOT_DEV = Root_SDA2; /* sda2 (sda1 is for the kernel) */
+
+ efika_pcisetup();
+
+ if (ppc_md.progress)
+ ppc_md.progress("Linux/PPC " UTS_RELEASE " runnung on Efika ;-)\n", 0x0);
+}
+
+static void __init efika_init_IRQ(void)
+{
+ mpc52xx_init_irq();
+}
+
+static void __init efika_init(void)
+{
+ struct device_node *np;
+ struct device_node *cnp = NULL;
+ const u32 *base;
+ char *name;
+
+ /* Find every child of the SOC node and add it to of_platform */
+ np = of_find_node_by_name(NULL, "builtin");
+ if (np) {
+ while ((cnp = of_get_next_child(np, cnp))) {
+ name = kmalloc(BUS_ID_SIZE, GFP_KERNEL);
+ if (name == NULL)
+ continue;
+
+ strcpy(name, cnp->name);
+
+ base = get_property(cnp, "reg", NULL);
+ if (base == NULL) {
+ kfree(name);
+ continue;
+ }
+
+ sprintf(name+strlen(name), "@%x", *base);
+ of_platform_device_create(cnp, name, NULL);
+
+ printk(KERN_INFO ": Added %s (%s) to the known devices\n", name, cnp->full_name);
+ }
+ }
+
+ if (ppc_md.progress)
+ ppc_md.progress(" Have fun with your Efika! ", 0x7777);
+}
+
+static int __init efika_probe(void)
+{
+ char *model = of_get_flat_dt_prop(of_get_flat_dt_root(),
+ "model", NULL);
+
+ if (model == NULL)
+ return 0;
+ if (strcmp(model, "EFIKA5K2"))
+ return 0;
+
+ ISA_DMA_THRESHOLD = ~0L;
+ DMA_MODE_READ = 0x44;
+ DMA_MODE_WRITE = 0x48;
+
+ return 1;
+}
+
+define_machine(efika)
+{
+ .name = EFIKA_PLATFORM_NAME,
+ .probe = efika_probe,
+ .setup_arch = efika_setup_arch,
+ .init = efika_init,
+ .show_cpuinfo = efika_show_cpuinfo,
+ .init_IRQ = efika_init_IRQ,
+ .get_irq = mpc52xx_get_irq,
+ .restart = rtas_restart,
+ .power_off = rtas_power_off,
+ .halt = rtas_halt,
+ .set_rtc_time = rtas_set_rtc_time,
+ .get_rtc_time = rtas_get_rtc_time,
+ .progress = rtas_progress,
+ .get_boot_time = rtas_get_boot_time,
+ .calibrate_decr = generic_calibrate_decr,
+ .phys_mem_access_prot = pci_phys_mem_access_prot,
+};
--- a/arch/powerpc/platforms/efika/pci.c 1970-01-01 01:00:00.000000000 +0100
+++ b/arch/powerpc/platforms/efika/pci.c 2006-11-01 21:16:06.000000000 +0100
@@ -0,0 +1,119 @@
+
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/string.h>
+#include <linux/init.h>
+
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/prom.h>
+#include <asm/machdep.h>
+#include <asm/sections.h>
+#include <asm/pci-bridge.h>
+#include <asm/rtas.h>
+
+#include "efika.h"
+
+#ifdef CONFIG_PCI
+/*
+ * Access functions for PCI config space using RTAS calls.
+ */
+static int rtas_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
+ int len, u32 * val)
+{
+ struct pci_controller *hose = bus->sysdata;
+ unsigned long addr = (offset & 0xff) | ((devfn & 0xff) << 8)
+ | (((bus->number - hose->first_busno) & 0xff) << 16)
+ | (hose->index << 24);
+ int ret = -1;
+ int rval;
+
+ rval = rtas_call(rtas_token("read-pci-config"), 2, 2, &ret, addr, len);
+ *val = ret;
+ return rval ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
+}
+
+static int rtas_write_config(struct pci_bus *bus, unsigned int devfn,
+ int offset, int len, u32 val)
+{
+ struct pci_controller *hose = bus->sysdata;
+ unsigned long addr = (offset & 0xff) | ((devfn & 0xff) << 8)
+ | (((bus->number - hose->first_busno) & 0xff) << 16)
+ | (hose->index << 24);
+ int rval;
+
+ rval = rtas_call(rtas_token("write-pci-config"), 3, 1, NULL,
+ addr, len, val);
+ return rval ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
+}
+
+static struct pci_ops rtas_pci_ops = {
+ rtas_read_config,
+ rtas_write_config
+};
+
+void __init efika_pcisetup(void)
+{
+ const int *bus_range;
+ int len;
+ struct pci_controller *hose;
+ struct device_node *root;
+ struct device_node *pcictrl;
+
+ root = of_find_node_by_path("/");
+ if (root == NULL) {
+ printk(KERN_WARNING EFIKA_PLATFORM_NAME
+ ": Unable to find the root node\n");
+ return;
+ }
+
+ for (pcictrl = NULL;;) {
+ pcictrl = of_get_next_child(root, pcictrl);
+ if ((pcictrl == NULL) || (strcmp(pcictrl->name, "pci") == 0))
+ break;
+ }
+
+ if (pcictrl == NULL) {
+ printk(KERN_WARNING EFIKA_PLATFORM_NAME
+ ": Unable to find the PCI bridge node\n");
+ return;
+ }
+
+ of_node_put(pcictrl);
+ of_node_put(root);
+
+ bus_range = get_property(pcictrl, "bus-range", &len);
+ if (bus_range == NULL || len < 2 * sizeof(int)) {
+ printk(KERN_WARNING EFIKA_PLATFORM_NAME
+ ": Can't get bus-range for %s\n", pcictrl->full_name);
+ return;
+ }
+ if (bus_range[1] == bus_range[0])
+ printk(KERN_INFO EFIKA_PLATFORM_NAME ": PCI bus %d",
+ bus_range[0]);
+ else
+ printk(KERN_INFO EFIKA_PLATFORM_NAME ": PCI buses %d..%d",
+ bus_range[0], bus_range[1]);
+ printk(" controlled by %s", pcictrl->full_name);
+ printk("\n");
+
+ hose = pcibios_alloc_controller();
+ if (!hose) {
+ printk(KERN_WARNING EFIKA_PLATFORM_NAME
+ ": Can't allocate PCI controller structure for %s\n",
+ pcictrl->full_name);
+ return;
+ }
+
+ hose->arch_data = pcictrl;
+ hose->first_busno = bus_range[0];
+ hose->last_busno = bus_range[1];
+ hose->ops = &rtas_pci_ops;
+
+ pci_process_bridge_OF_ranges(hose, pcictrl, 0);
+}
+
+#else
+void __init efika_pcisetup(void)
+{}
+#endif
--- a/arch/powerpc/platforms/efika/efika.h 1970-01-01 01:00:00.000000000 +0100
+++ b/arch/powerpc/platforms/efika/efika.h 2006-11-01 21:16:06.000000000 +0100
@@ -0,0 +1,19 @@
+/*
+ * Efika 5K2 platform setup - Header file
+ *
+ * Copyright (C) 2006 bplan GmbH
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ *
+ */
+
+#ifndef __ARCH_POWERPC_EFIKA__
+#define __ARCH_POWERPC_EFIKA__
+
+#define EFIKA_PLATFORM_NAME "Efika"
+
+extern void __init efika_pcisetup(void);
+
+#endif
--- a/arch/powerpc/platforms/efika/Makefile 1970-01-01 01:00:00.000000000 +0100
+++ b/arch/powerpc/platforms/efika/Makefile 2006-11-01 21:16:06.000000000 +0100
@@ -0,0 +1 @@
+obj-y += setup.o mpc52xx.o pci.o
--- a/arch/powerpc/platforms/Makefile 2006-11-01 09:18:43.000000000 +0100
+++ b/arch/powerpc/platforms/Makefile 2006-11-01 21:16:06.000000000 +0100
@@ -6,6 +6,7 @@ obj-$(CONFIG_PPC_PMAC) += powermac/
endif
endif
obj-$(CONFIG_PPC_CHRP) += chrp/
+obj-$(CONFIG_PPC_EFIKA) += efika/
obj-$(CONFIG_4xx) += 4xx/
obj-$(CONFIG_PPC_83xx) += 83xx/
obj-$(CONFIG_PPC_85xx) += 85xx/
--- a/arch/powerpc/boot/Makefile 2006-11-01 09:18:42.000000000 +0100
+++ b/arch/powerpc/boot/Makefile 2006-10-31 12:31:55.000000000 +0100
@@ -115,7 +115,7 @@ endif
quiet_cmd_wrap = WRAP $@
cmd_wrap =$(CONFIG_SHELL) $(wrapper) -c -o $@ -p $2 $(CROSSWRAP) vmlinux
quiet_cmd_wrap_initrd = WRAP $@
- cmd_wrap_initrd =$(CONFIG_SHELL) $(wrapper) -c -o $@ -p $2 $(CROSSWRAP) \
+ cmd_wrap_initrd =$(wrapper) -c -o $@ -p $2 $(CROSSWRAP) \
-i $(obj)/ramdisk.image.gz vmlinux
$(obj)/zImage.chrp: vmlinux $(wrapperbits)
@@ -155,6 +155,7 @@ image-$(CONFIG_PPC_PSERIES) += zImage.p
image-$(CONFIG_PPC_MAPLE) += zImage.pseries
image-$(CONFIG_PPC_IBM_CELL_BLADE) += zImage.pseries
image-$(CONFIG_PPC_CHRP) += zImage.chrp
+image-$(CONFIG_PPC_EFIKA) += zImage.chrp
image-$(CONFIG_PPC_PMAC) += zImage.pmac
image-$(CONFIG_DEFAULT_UIMAGE) += uImage
--- a/arch/powerpc/Kconfig 2006-11-01 09:18:42.000000000 +0100
+++ b/arch/powerpc/Kconfig 2006-11-01 21:17:02.000000000 +0100
@@ -386,6 +386,14 @@ config PPC_CHRP
select PPC_UDBG_16550
default y
+config PPC_EFIKA
+ bool "bPlan Efika 5k2. MPC5200B based computer"
+ depends on PPC_MULTIPLATFORM && PPC32
+ select PPC_RTAS
+ select RTAS_PROC
+ select PPC_MPC52xx
+ default y
+
config PPC_PMAC
bool "Apple PowerMac based machines"
depends on PPC_MULTIPLATFORM
[-- Attachment #3: nd.vcf --]
[-- Type: text/x-vcard, Size: 249 bytes --]
begin:vcard
fn:Nicolas DET ( bplan GmbH )
n:DET;Nicolas
org:bplan GmbH
adr:;;;;;;Germany
email;internet:nd@bplan-gmbh.de
title:Software Entwicklung
tel;work:+49 6171 9187 - 31
x-mozilla-html:FALSE
url:http://www.bplan-gmbh.de
version:2.1
end:vcard
^ permalink raw reply
* [PATCH/RFC] powerpc: Add of_platform support for OHCI/Bigendian HC
From: Nicolas DET @ 2006-11-01 20:31 UTC (permalink / raw)
To: linuxppc-dev, benh, sl, linuxppc-embedded
[-- Attachment #1: Type: text/plain, Size: 193 bytes --]
This patch use of_platform device to probe and install OHCI big endian HC.
PS: I did not success to properly inline the file using thrunderbird.
Signed-off-by: Nicolas DET <nd@bplan-gmbh.de>
[-- Attachment #2: archpowerpc_ohciof.patch --]
[-- Type: text/plain, Size: 7160 bytes --]
--- a/drivers/usb/host/ohci-ppc-of.c 1970-01-01 01:00:00.000000000 +0100
+++ b/drivers/usb/host/ohci-ppc-of.c 2006-11-01 21:16:06.000000000 +0100
@@ -0,0 +1,251 @@
+/*
+ * OHCI HCD (Host Controller Driver) for USB.
+ *
+ * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
+ * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
+ * (C) Copyright 2002 Hewlett-Packard Company
+ * (C) Copyright 2003-2005 MontaVista Software Inc.
+ *
+ * Probe and init OHCI Big endian HC from OpenFirmware device tree
+ * Tested on Efika 5k2
+ *
+ * Modified by Dale Farnsworth <dale@farnsworth.org> from ohci-sa1111.c
+ *
+ * This file is licenced under the GPL.
+ */
+
+#include <linux/signal.h>
+
+#include <asm/of_device.h>
+#include <asm/prom.h>
+
+/* configure so an HC device and id are always provided */
+/* always called with process context; sleeping is OK */
+
+/**
+ * usb_hcd_ppc_of_probe - initialize On-Chip HCDs
+ * Context: !in_interrupt()
+ *
+ * Allocates basic resources for this USB host controller.
+ *
+ * Store this function in the HCD's struct pci_driver as probe().
+ */
+static int usb_hcd_ppc_of_probe(const struct hc_driver *driver,
+ struct of_device *dev)
+{
+ int retval;
+ struct usb_hcd *hcd;
+ struct ohci_hcd *ohci;
+ struct resource res;
+ int irq;
+ int ret;
+
+ pr_debug("initializing PPC-OF USB Controller\n");
+
+ if ((ret = of_address_to_resource(dev->node, 0, &res)) != 0)
+ return ret;
+
+ hcd = usb_create_hcd(driver, &dev->dev, "PPC-OF USB");
+ if (!hcd)
+ return -ENOMEM;
+ hcd->rsrc_start = res.start;
+ hcd->rsrc_len = res.end - res.start + 1;
+
+ if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) {
+ pr_debug(__FILE__ ": request_mem_region failed\n");
+ retval = -EBUSY;
+ goto err1;
+ }
+
+ irq = irq_of_parse_and_map(dev->node, 0);
+ if (irq == NO_IRQ) {
+ retval = -EBUSY;
+ goto err2;
+ }
+
+ hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len);
+ if (!hcd->regs) {
+ pr_debug(__FILE__ ": ioremap failed\n");
+ retval = -ENOMEM;
+ goto err2;
+ }
+
+ ohci = hcd_to_ohci(hcd);
+ ohci->flags |= OHCI_BIG_ENDIAN;
+ ohci_hcd_init(ohci);
+
+ retval = usb_add_hcd(hcd, irq, IRQF_DISABLED);
+ if (retval == 0)
+ return retval;
+
+ pr_debug("Removing PPC-OF USB Controller\n");
+
+ iounmap(hcd->regs);
+ err2:
+ release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
+ err1:
+ usb_put_hcd(hcd);
+ return retval;
+}
+
+
+/* may be called without controller electrically present */
+/* may be called with controller, bus, and devices active */
+
+/**
+ * usb_hcd_ppc_of_remove - shutdown processing for On-Chip HCDs
+ * @pdev: USB Host Controller being removed
+ * Context: !in_interrupt()
+ *
+ * Reverses the effect of usb_hcd_ppc_of_probe().
+ * It is always called from a thread
+ * context, normally "rmmod", "apmd", or something similar.
+ *
+ */
+static void usb_hcd_ppc_of_remove(struct usb_hcd *hcd,
+ struct of_device *op)
+{
+ usb_remove_hcd(hcd);
+
+ pr_debug("stopping PPC-OF USB Controller\n");
+
+ iounmap(hcd->regs);
+ release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
+ usb_put_hcd(hcd);
+}
+
+static int __devinit
+ohci_ppc_of_start(struct usb_hcd *hcd)
+{
+ struct ohci_hcd *ohci = hcd_to_ohci(hcd);
+ int ret;
+
+ if ((ret = ohci_init(ohci)) < 0)
+ return ret;
+
+ if ((ret = ohci_run(ohci)) < 0) {
+ err("can't start %s", ohci_to_hcd(ohci)->self.bus_name);
+ ohci_stop(hcd);
+ return ret;
+ }
+
+ return 0;
+}
+
+static const struct hc_driver ohci_ppc_of_hc_driver = {
+ .description = hcd_name,
+ .hcd_priv_size = sizeof(struct ohci_hcd),
+
+ /*
+ * generic hardware linkage
+ */
+ .irq = ohci_irq,
+ .flags = HCD_USB11 | HCD_MEMORY,
+
+ /*
+ * basic lifecycle operations
+ */
+ .start = ohci_ppc_of_start,
+ .stop = ohci_stop,
+ .shutdown = ohci_shutdown,
+
+ /*
+ * managing i/o requests and associated device resources
+ */
+ .urb_enqueue = ohci_urb_enqueue,
+ .urb_dequeue = ohci_urb_dequeue,
+ .endpoint_disable = ohci_endpoint_disable,
+
+ /*
+ * scheduling support
+ */
+ .get_frame_number = ohci_get_frame,
+
+ /*
+ * root hub support
+ */
+ .hub_status_data = ohci_hub_status_data,
+ .hub_control = ohci_hub_control,
+ .hub_irq_enable = ohci_rhsc_enable,
+#ifdef CONFIG_PM
+ .bus_suspend = ohci_bus_suspend,
+ .bus_resume = ohci_bus_resume,
+#endif
+ .start_port_reset = ohci_start_port_reset,
+};
+
+static int __devinit
+ohci_hcd_ppc_of_drv_probe(struct of_device *op, const struct of_device_id *match)
+{
+ int ret;
+
+ if (usb_disabled())
+ return -ENODEV;
+
+ ret = usb_hcd_ppc_of_probe(&ohci_ppc_of_hc_driver, op);
+ return ret;
+}
+
+static int ohci_hcd_ppc_of_drv_remove(struct of_device *op)
+{
+ struct usb_hcd *hcd = dev_get_drvdata(&op->dev);
+ dev_set_drvdata(&op->dev, NULL);
+
+ usb_hcd_ppc_of_remove(hcd, op);
+ return 0;
+}
+
+static int ohci_hcd_ppc_of_drv_shutdown(struct of_device *op)
+{
+ struct usb_hcd *hcd = dev_get_drvdata(&op->dev);
+
+ if (hcd->driver->shutdown)
+ hcd->driver->shutdown(hcd);
+
+ return 0;
+}
+
+static struct of_device_id ohci_hcd_ppc_of_match[] = {
+ {
+ .name = "usb",
+ .compatible = "ohci-bigendian",
+ },
+ {
+ .name = "usb",
+ .compatible = "ohci-be",
+ },
+ {},
+};
+
+
+static struct of_platform_driver ohci_hcd_ppc_of_driver = {
+ .name = "ppc-of-ohci",
+ .match_table = ohci_hcd_ppc_of_match,
+ .probe = ohci_hcd_ppc_of_drv_probe,
+ .remove = ohci_hcd_ppc_of_drv_remove,
+ .shutdown = ohci_hcd_ppc_of_drv_shutdown,
+#ifdef CONFIG_PM
+ /*.suspend = ohci_hcd_ppc_soc_drv_suspend,*/
+ /*.resume = ohci_hcd_ppc_soc_drv_resume,*/
+#endif
+ .driver = {
+ .name = "ppc-of-ohci",
+ .owner = THIS_MODULE,
+ },
+};
+
+static int __init ohci_hcd_ppc_of_init(void)
+{
+ pr_debug(DRIVER_INFO " (PPC OF)\n");
+ pr_debug("block sizes: ed %d td %d\n", sizeof(struct ed),
+ sizeof(struct td));
+ return of_register_driver(&ohci_hcd_ppc_of_driver);
+}
+
+static void __exit ohci_hcd_ppc_of_cleanup(void)
+{
+ of_unregister_driver(&ohci_hcd_ppc_of_driver);
+}
+
+module_init(ohci_hcd_ppc_of_init);
+module_exit(ohci_hcd_ppc_of_cleanup);
--- a/drivers/usb/host/Kconfig 2006-11-01 09:18:56.000000000 +0100
+++ b/drivers/usb/host/Kconfig 2006-11-01 21:16:06.000000000 +0100
@@ -106,6 +106,14 @@ config USB_OHCI_HCD_PPC_SOC
Enables support for the USB controller on the MPC52xx or
STB03xxx processor chip. If unsure, say Y.
+config USB_OHCI_HCD_PPC_OF
+ bool "OHCI support for PPC USB controller for OpenFirmware platform"
+ depends on USB_OHCI_HCD && PPC_OF
+ default y
+ select USB_OHCI_BIG_ENDIAN
+ ---help---
+ Enables support for the USB controller PowerPC OpenFirmware platform
+
config USB_OHCI_HCD_PCI
bool "OHCI support for PCI-bus USB controllers"
depends on USB_OHCI_HCD && PCI && (STB03xxx || PPC_MPC52xx)
--- a/drivers/usb/host/ohci-hcd.c 2006-11-01 09:18:56.000000000 +0100
+++ b/drivers/usb/host/ohci-hcd.c 2006-11-01 21:16:06.000000000 +0100
@@ -930,6 +930,12 @@ MODULE_LICENSE ("GPL");
#include "ohci-ppc-soc.c"
#endif
+#ifdef CONFIG_USB_OHCI_HCD_PPC_OF
+#include "ohci-ppc-of.c"
+#endif
+
+
+
#if defined(CONFIG_ARCH_AT91RM9200) || defined(CONFIG_ARCH_AT91SAM9261)
#include "ohci-at91.c"
#endif
[-- Attachment #3: nd.vcf --]
[-- Type: text/x-vcard, Size: 249 bytes --]
begin:vcard
fn:Nicolas DET ( bplan GmbH )
n:DET;Nicolas
org:bplan GmbH
adr:;;;;;;Germany
email;internet:nd@bplan-gmbh.de
title:Software Entwicklung
tel;work:+49 6171 9187 - 31
x-mozilla-html:FALSE
url:http://www.bplan-gmbh.de
version:2.1
end:vcard
^ permalink raw reply
* RE: plb_temac w/linux 2.6.18.1 driver init error
From: robert corley @ 2006-11-01 20:33 UTC (permalink / raw)
To: David Bolcsfoldi; +Cc: linux linuxppc-embedded
Anyone?;=0A=0AThe offending instruction is:=0A=0Aout_be32((volatile unsigne=
d *) InstancePtr->RegBaseAddress+XPF_V200A_RESET_REG_OFFSET, XPF_V200A_RESE=
T_FIFO_MASK);=0A=0Acalled vai a #define in "drivers/xilinx_edk/xpacket_fifo=
_v2_00_a.c"=0A=0AWould anyone care to speculate if the error is in the out_=
be32 definition or is this a function of a memory access to an incorrect va=
lue?=0A=0AHere is the latest dump:=0A=0A[ 2.702189] xtenet_probe: xtemac=
0: IO resources obtained. IRQ =3D 0, MEM =3D 0x60000000=0A[ 2.710095] =
xtenet_probe: xtemac 0: private data initialized=0A[ 2.715872] remap=
info =3D> start =3D 0x60000000, end=3D0x60003fff, total=3D16384, virtual d=
est.=3D0xc5050000=0A[ 2.725007] xtenet_probe: TEMAC config lookup succee=
ded. Details =3D =0A[ 2.731369] Base address =3D 0x60000000=
=0A[ 2.735471] Unique ID =3D 0x0000=0A[ 2.739230] =
RCV FIFO depth =3D 0x131072=0A[ 2.743161] XMIT FIFO depth =
=3D 0x131072=0A[ 2.747091] MAC FIFO depth =3D 0x64=0A[ 2.750=
677] IPIF/DMA config =3D 0x03=0A[ 2.754260] DCR Host =
=3D 0x0=0A[ 2.757759] DRE Engine? =3D 0x1=0A[ 2.76126=
0] Initialize : Handlers set up. Configuring FIFO access...=0A[ 2.76770=
9] XPacketFifoV200a_Initialize : setting FIFO REG base address to 0xC505201=
0=0A[ 2.775548] XPacketFifoV200a_Initialize : setting FIFO DATA base add=
ress to 0xC5052200=0A[ 2.783474] XPacketFifoV200a_Initialize : setting I=
sReady to 286331153=0A[ 2.790011] XPacketFifoV200a_Initialize : resettin=
g FIFO by writing 0x000A to 0xC5052010=0A[ 2.798103] Data machine check =
in kernel mode.=0A[ 2.802544] Oops: machine check, sig: 7 [#1]=0A=0A-cy=
=0A=0A=0A=0A=0A
^ permalink raw reply
* Re: [PATCH/RFC] powerpc: Add Efika platform support
From: Nicolas DET @ 2006-11-01 20:34 UTC (permalink / raw)
To: Nicolas DET; +Cc: linuxppc-dev, linuxppc-embedded, sl
In-Reply-To: <45490394.8020202@bplan-gmbh.de>
[-- Attachment #1: Type: text/plain, Size: 348 bytes --]
Nicolas DET wrote:
> Add Efika platform support
>
I'll soon (well It's alraedy done) run out of time to spend of this.
This means, I won't be able to work more on the interrupt controller,
and others devices support.
I hope patches could be finally accepted. Moreover, I think the code is
now in better shape han it was in arch/ppc.
Regards
[-- Attachment #2: nd.vcf --]
[-- Type: text/x-vcard, Size: 249 bytes --]
begin:vcard
fn:Nicolas DET ( bplan GmbH )
n:DET;Nicolas
org:bplan GmbH
adr:;;;;;;Germany
email;internet:nd@bplan-gmbh.de
title:Software Entwicklung
tel;work:+49 6171 9187 - 31
x-mozilla-html:FALSE
url:http://www.bplan-gmbh.de
version:2.1
end:vcard
^ permalink raw reply
* Re: [PATCH] [POWERPC] Move mpc52xx-psc uart driver to of_device from platform_device
From: Nicolas DET @ 2006-11-01 20:37 UTC (permalink / raw)
To: Grant Likely; +Cc: linuxppc-embedded
In-Reply-To: <11623704073308-git-send-email-grant.likely@secretlab.ca>
[-- Attachment #1: Type: text/plain, Size: 925 bytes --]
Grant Likely wrote:
> As part of the transition to arch/powerpc, this patch moves the mpc5200 PSC
> driver over to the OF platform bus infrastructure.
>
> This patch is not acceptable for mainline as-is because it breaks arch/ppc
> support for the mpc52xx. More rework is needed to allow it to compile for
> either arch (or alternately, fork the driver)
>
It has been hard to apply on 2.6.19-rc4 but it seems to perform well.
I add to add some entries in mpc52xx_uart_match[]
In now looks like this:
static struct of_device_id mpc52xx_uart_match[] = {
{
.name = "serial",
.compatible = "mpc52xx-psc",
},
{
.name = "serial",
.compatible = "mpc52xx-serial",
},
{
.name = "serial",
.compatible = "mpc5200-psc",
},
{
.name = "serial",
.compatible = "mpc5200-serial",
},
{},
};
By the way, why not using mpc52xx_uart_match[] to also in
mpc52xx_console_setup() to track down any devices?
Regards,
[-- Attachment #2: nd.vcf --]
[-- Type: text/x-vcard, Size: 249 bytes --]
begin:vcard
fn:Nicolas DET ( bplan GmbH )
n:DET;Nicolas
org:bplan GmbH
adr:;;;;;;Germany
email;internet:nd@bplan-gmbh.de
title:Software Entwicklung
tel;work:+49 6171 9187 - 31
x-mozilla-html:FALSE
url:http://www.bplan-gmbh.de
version:2.1
end:vcard
^ permalink raw reply
* Re: [PATCH] powerpc: Make alignment exception always check exception table
From: Benjamin Herrenschmidt @ 2006-11-01 20:43 UTC (permalink / raw)
To: Greg KH; +Cc: linuxppc-dev list, Paul Mackerras
In-Reply-To: <20061101063401.GA25664@kroah.com>
On Tue, 2006-10-31 at 22:34 -0800, Greg KH wrote:
> On Wed, Nov 01, 2006 at 02:09:30PM +1100, Benjamin Herrenschmidt wrote:
> > The alignment exception used to only check the exception table for
> > -EFAULT, not for other errors. That opens an oops window if we can
> > coerce the kernel into getting an alignment exception for other reasons
> > in what would normally be a user-protected accessor, which can be done
> > via some of the futex ops. This fixes it by always checking the
> > exception tables.
> >
> > Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> > ---
> >
> > This is 2.6.19 material and should probably go into stable as well.
> > (Greg: take it if paulus acks it and it applies :)
>
> Please forward the final patch (which ever version it is :) to the
> stable@kernel.org address when this goes into mainline.
Ok, will do. I wan't sure what the proper procedure was.
Cheers,
Ben.
^ permalink raw reply
* Re: [PATCH] [POWERPC] Move mpc52xx-psc uart driver to of_device from platform_device
From: Grant Likely @ 2006-11-01 20:50 UTC (permalink / raw)
To: Nicolas DET; +Cc: linuxppc-embedded
In-Reply-To: <4549056C.6080503@bplan-gmbh.de>
On 11/1/06, Nicolas DET <nd@bplan-gmbh.de> wrote:
> Grant Likely wrote:
> > As part of the transition to arch/powerpc, this patch moves the mpc5200 PSC
> > driver over to the OF platform bus infrastructure.
> >
> > This patch is not acceptable for mainline as-is because it breaks arch/ppc
> > support for the mpc52xx. More rework is needed to allow it to compile for
> > either arch (or alternately, fork the driver)
> >
>
> It has been hard to apply on 2.6.19-rc4 but it seems to perform well.
> I add to add some entries in mpc52xx_uart_match[]
Good news, thanks for the feedback. I take it you are able to use the
serial port with this driver?
>
> In now looks like this:
> static struct of_device_id mpc52xx_uart_match[] = {
> {
> .name = "serial",
> .compatible = "mpc52xx-psc",
> },
> {
> .name = "serial",
> .compatible = "mpc52xx-serial",
> },
> {
> .name = "serial",
> .compatible = "mpc5200-psc",
> },
> {
> .name = "serial",
> .compatible = "mpc5200-serial",
> },
> {},
> };
I'd rather not do this for the mainline code. I'd rather define a
naming convention and all of us use it. We're early enough in this
process that we can do that since there are only two major boards
(lite5200 & Efika) on track to be supported in mainline ATM.
Having 4 compatibility blocks to support 2 boards is over-engineering. :)
>
> By the way, why not using mpc52xx_uart_match[] to also in
> mpc52xx_console_setup() to track down any devices?
Because I hadn't thought of that, and therefore have not decided if
that's a good idea! :) I'll take a look.
g.
--
Grant Likely, B.Sc. P.Eng.
Secret Lab Technologies Ltd.
grant.likely@secretlab.ca
(403) 399-0195
^ permalink raw reply
* Re: [PATCH] [POWERPC] Move mpc52xx-psc uart driver to of_device from platform_device
From: Nicolas DET @ 2006-11-01 20:54 UTC (permalink / raw)
To: Grant Likely; +Cc: linuxppc-embedded
In-Reply-To: <528646bc0611011250h6ce7d29al494ff94f891b0b07@mail.gmail.com>
[-- Attachment #1: Type: text/plain, Size: 1706 bytes --]
Grant Likely wrote:
> On 11/1/06, Nicolas DET <nd@bplan-gmbh.de> wrote:
>> Grant Likely wrote:
>> > As part of the transition to arch/powerpc, this patch moves the
>> mpc5200 PSC
>> > driver over to the OF platform bus infrastructure.
>> >
>> > This patch is not acceptable for mainline as-is because it breaks
>> arch/ppc
>> > support for the mpc52xx. More rework is needed to allow it to
>> compile for
>> > either arch (or alternately, fork the driver)
>> >
>>
>> It has been hard to apply on 2.6.19-rc4 but it seems to perform well.
>> I add to add some entries in mpc52xx_uart_match[]
>
> Good news, thanks for the feedback. I take it you are able to use the
> serial port with this driver?
Yes.
>>
>> In now looks like this:
>> static struct of_device_id mpc52xx_uart_match[] = {
>> {
>> .name = "serial",
>> .compatible = "mpc52xx-psc",
>> },
>> {
>> .name = "serial",
>> .compatible = "mpc52xx-serial",
>> },
>> {
>> .name = "serial",
>> .compatible = "mpc5200-psc",
>> },
>> {
>> .name = "serial",
>> .compatible = "mpc5200-serial",
>> },
>> {},
>> };
>
> I'd rather not do this for the mainline code. I'd rather define a
> naming convention and all of us use it. We're early enough in this
> process that we can do that since there are only two major boards
> (lite5200 & Efika) on track to be supported in mainline ATM.
>
> Having 4 compatibility blocks to support 2 boards is over-engineering. :)
Ok. Efika will have "mpc5200-serial' inside the "compatible" property.
Regards,
[-- Attachment #2: nd.vcf --]
[-- Type: text/x-vcard, Size: 249 bytes --]
begin:vcard
fn:Nicolas DET ( bplan GmbH )
n:DET;Nicolas
org:bplan GmbH
adr:;;;;;;Germany
email;internet:nd@bplan-gmbh.de
title:Software Entwicklung
tel;work:+49 6171 9187 - 31
x-mozilla-html:FALSE
url:http://www.bplan-gmbh.de
version:2.1
end:vcard
^ permalink raw reply
* Re: [PATCH 1/2] Add MPC52xx Interrupt controller support for ARCH=powerpc
From: Benjamin Herrenschmidt @ 2006-11-01 20:56 UTC (permalink / raw)
To: Nicolas DET; +Cc: linuxppc-dev, sl, sha, linuxppc-embedded
In-Reply-To: <454867AB.2010904@bplan-gmbh.de>
> In my opinion, as it reflects a bit better hwow the hw itself is
> architectured (critical, main, peripheral...) it's better to do it like
> this. I do not wish to change this. Moreover, it's yet working pretty well.
I disagree completely here. The HW works the way the registers are laid
out. The -whole-point- of doing that Level1 vs. Level2 thing was to
abstract is such that Level1 represents the register set used. Now, what
you essentially did is split is so that one Level1 is a special case of
one register set, the second Level1 can be either the rest of that
register or another, and 3 and 4 are properly separate register sets.
That makes no sense at all.
> It normaly does not compile if I remove it as state earlier. I'll remove
> them and fixed the compile issue.
>
> > if defined(CONFIG_PPC_MPC52xx) && !defined(CONFIG_PPC_MERGE)
It compiles if you also fixup asm-ppc/io.h by doing the above.
> Will be removed and replace by another define to reflect the highest
> virq (0xd0).
>
> #define MPC52xx_IRQ_MACVIRQ (0xd0)
>
> sounds ok ?
No, it's not a V irq, it's a HW irq number. (and MAC vs. MAX ?)
Ben
^ permalink raw reply
* RE: plb_temac w/linux 2.6.18.1 driver init error
From: Rick Moleres @ 2006-11-01 20:45 UTC (permalink / raw)
To: robert corley, David Bolcsfoldi; +Cc: linux linuxppc-embedded
Robert,
I haven't seen this before, but perhaps the plb_temac hardware is built
for DMA but xparameters.h is out of sync and thinks it's built with FIFO
mode? This would probably cause a machine check if trying to write a
FIFO register but it doesn't exist. You can crosscheck xparameters.h
with your hardware design to verify.
-Rick
-----Original Message-----
From: linuxppc-embedded-bounces+moleres=3Dxilinx.com@ozlabs.org
[mailto:linuxppc-embedded-bounces+moleres=3Dxilinx.com@ozlabs.org] On
Behalf Of robert corley
Sent: Wednesday, November 01, 2006 1:33 PM
To: David Bolcsfoldi
Cc: linux linuxppc-embedded
Subject: RE: plb_temac w/linux 2.6.18.1 driver init error
Anyone?;
The offending instruction is:
out_be32((volatile unsigned *)
InstancePtr->RegBaseAddress+XPF_V200A_RESET_REG_OFFSET,
XPF_V200A_RESET_FIFO_MASK);
called vai a #define in "drivers/xilinx_edk/xpacket_fifo_v2_00_a.c"
Would anyone care to speculate if the error is in the out_be32
definition or is this a function of a memory access to an incorrect
value?
Here is the latest dump:
[ 2.702189] xtenet_probe: xtemac 0: IO resources obtained. IRQ =3D =
0,
MEM =3D 0x60000000
[ 2.710095] xtenet_probe: xtemac 0: private data initialized
[ 2.715872] remap info =3D> start =3D 0x60000000, =
end=3D0x60003fff,
total=3D16384, virtual dest.=3D0xc5050000
[ 2.725007] xtenet_probe: TEMAC config lookup succeeded. Details =3D =
[ 2.731369] Base address =3D 0x60000000
[ 2.735471] Unique ID =3D 0x0000
[ 2.739230] RCV FIFO depth =3D 0x131072
[ 2.743161] XMIT FIFO depth =3D 0x131072
[ 2.747091] MAC FIFO depth =3D 0x64
[ 2.750677] IPIF/DMA config =3D 0x03
[ 2.754260] DCR Host =3D 0x0
[ 2.757759] DRE Engine? =3D 0x1
[ 2.761260] Initialize : Handlers set up. Configuring FIFO access...
[ 2.767709] XPacketFifoV200a_Initialize : setting FIFO REG base
address to 0xC5052010
[ 2.775548] XPacketFifoV200a_Initialize : setting FIFO DATA base
address to 0xC5052200
[ 2.783474] XPacketFifoV200a_Initialize : setting IsReady to
286331153
[ 2.790011] XPacketFifoV200a_Initialize : resetting FIFO by writing
0x000A to 0xC5052010
[ 2.798103] Data machine check in kernel mode.
[ 2.802544] Oops: machine check, sig: 7 [#1]
-cy
_______________________________________________
Linuxppc-embedded mailing list
Linuxppc-embedded@ozlabs.org
https://ozlabs.org/mailman/listinfo/linuxppc-embedded
^ permalink raw reply
* Re: [PATCH/RFC] powerpc: Add MPC5200 Interrupt Controller support.
From: Sven Luther @ 2006-11-01 22:07 UTC (permalink / raw)
To: Dale Farnsworth; +Cc: linuxppc-dev, sven, linuxppc-embedded
In-Reply-To: <20061101220543.1541.qmail@farnsworth.org>
On Wed, Nov 01, 2006 at 10:05:43PM -0000, Dale Farnsworth wrote:
> In article <454902F9.20206@bplan-gmbh.de> Nicolas wrote:
> > --- a/arch/powerpc/sysdev/mpc52xx_pic.c 1970-01-01 01:00:00.000000000 +0100
> > +++ b/arch/powerpc/sysdev/mpc52xx_pic.c 2006-11-01 21:16:40.000000000 +0100
> > @@ -0,0 +1,566 @@
> > +/*
> > + *
> > + * Programmable Interrupt Controller functions for the Freescale MPC52xx.
> > + *
> > + * Copyright (C) 2006 bplan GmbH
> > + *
> > + * This file is licensed under the terms of the GNU General Public License
>
> Once again, please restore the copyright lines you removed from this file.
Hehe, you are aware that, IIRW, someone suggested to cut them earlier in this
thread ?
Friendly,
Sven Luther
^ permalink raw reply
* Re: [PATCH/RFC] powerpc: Add MPC5200 Interrupt Controller support.
From: Benjamin Herrenschmidt @ 2006-11-01 22:12 UTC (permalink / raw)
To: Nicolas DET; +Cc: linuxppc-dev, Sylvain Munaut, sl, linuxppc-embedded
In-Reply-To: <454902F9.20206@bplan-gmbh.de>
My only remaining comment is what I said earlier about the way you
divided the interrupt in levels.
In fact, I've finally dug into the doc and found out that the situation
is even less clear :)
The whole point of this division is to avoid special cases and properly
deal with the separation in different HW registers. We have basically 4
register sets controlling irqs:
- intr->ctrl
- intr->main_mask
- intr->per_mask
- sdma (different device)
Now, your current setup ends up defining a "level" and 5 irq_chips !!!
- intr->ctrl bit 11 has it's own chip
- intr->ctrl other bits or intr->main_mask (2 different chips)
- intr->per_mask a chip
- sdma a chip
which seems to totally gross since the first one is basically "main" irq
0, and has no reason whatsoever to be kept separate from "main". Which
would give us something much more sensible with 4 levels and 4 chips:
- intr->ctrl based interrupts (crit and main, crit being just main 0)
- intr->main_mask
- intr->per_mask
- sdma
In that case, you have a nice 1 level == 1 irq_chip == one register set.
Now, in addition to that, we have another issue I haven't spotted
before, but it might be worth considering:
Do we actually want the sdma interrupts handled there ? Because if you
look closely, the SDMA is basically a cascaded interrupt controller. It
hangs of per interrupt 0 :)
Thus we could simply remove the code for it from that driver and
implement it as as separate controller with a separate interrupt domain.
I know you won't like that idea because it means having a different
interrupt tree but it's worth having the discussion.
Ben.
^ permalink raw reply
* Re: [PATCH/RFC] powerpc: Add MPC5200 Interrupt Controller support.
From: Dale Farnsworth @ 2006-11-01 22:05 UTC (permalink / raw)
To: nd, linuxppc-embedded, linuxppc-dev
In-Reply-To: <454902F9.20206@bplan-gmbh.de>
In article <454902F9.20206@bplan-gmbh.de> Nicolas wrote:
> --- a/arch/powerpc/sysdev/mpc52xx_pic.c 1970-01-01 01:00:00.000000000 +0100
> +++ b/arch/powerpc/sysdev/mpc52xx_pic.c 2006-11-01 21:16:40.000000000 +0100
> @@ -0,0 +1,566 @@
> +/*
> + *
> + * Programmable Interrupt Controller functions for the Freescale MPC52xx.
> + *
> + * Copyright (C) 2006 bplan GmbH
> + *
> + * This file is licensed under the terms of the GNU General Public License
Once again, please restore the copyright lines you removed from this file.
Dale Farnsworth
^ permalink raw reply
* Re: glibc-2.5 test suite hangs/crashes the machine
From: Steve Munroe @ 2006-11-01 22:17 UTC (permalink / raw)
To: Benjamin Herrenschmidt
Cc: linuxppc-dev, Jeff Bailey, Fabio Massimo Di Nitto, Paul Mackerras,
Ben Collins
In-Reply-To: <1162172825.25682.139.camel@localhost.localdomain>
Benjamin Herrenschmidt <benh@kernel=2Ecrashing=2Eorg> wrote on 10/29/20=
06
07:47:05 PM:
> On Fri, 2006-10-27 at 12:22 -0400, Jeff Bailey wrote:
> > Le vendredi 27 octobre 2006 =E0 07:56 +0200, Fabio Massimo Di Nitto=
a
> > =E9crit :
> > > Hi everybody,
> > >
> > > i am in the process of bootstrapping the new toolchain for ubuntu=
and
I am
> > > hitting a problem building glibc-2=2E5 on ppc=2E
> > >
> > > This behaviour has been reproduced on 2=2E6=2E15/2=2E6=2E17 and 2=
=2E6=2E19-
> rc2 (where the
> > > machine crashes) and with ppc32 and ppc64 kernels=2E
> > > A hard reboot of the machine is required to get rid of the Zl
> processes hanging
> > > around that keep spinning the CPU at 100%=2E
> > >
> > > I did place sources here: http://people=2Eubuntu=2Ecom/~fabbione/=
benh/
> > >
> > > but i start to believe it is a kernel bug we are exploiting only =
now=2E
> > >
> > > Any hint or help for what to look for would be extremely apprecia=
ted=2E
> >
> > Heya Fabio, just an update, it looks like the tests that are zombie=
'ing
> > are the nptl tst-robust[1-8] tests=2E According to /proc/##/wchan,=
the
> > tasks are cheerfully spinning in do_exit=2E
>
> So I've built that glibc with debian 2=2E6=2E16 kernel headers (since=
Fabio
> says the problem doesn't happen with glibc built with 2=2E6=2E19 head=
ers)
> and have ran that with 2=2E6=2E19-rc3-git-du-jour=2E
>
> The machine didn't crash, nor did I see any zombie with those
> tst-robust[1-8], however, I did get as SIGBUS with tst-robustpi1=2E I=
've
> tracked it down to being an alignment exception=2E It looks like glib=
c is
> doing a lwarx on a non-aligned value, though I can't say precisely
> what's up here=2E I don't know how I can get a backtrace when running=
> those test-cases=2E=2E=2E the test harness seems to catch signals, I =
suppose
> it could be modified to spit one out=2E
>
> At this point, it would be useful to have somebody who knows glibc to=
> tell us:
>
> - what are those tst-robust all about ? (what do they do "special" t=
hat
> might trigger bad reactions with older kernels)
> - how can glibc ever do atomic operations on a non-aligned value ?
>
> Ben=2E
>
The tst-robustpi# test are exercising the new PTHREAD_MUXTEX_ROBUST api=
,
with PTHREAD_PRIO_INHERIT attribute=2E
The fuxtex word seems to include the waiters TID, I don't know if the
kernel cares about this or not=2E
Steven J=2E Munroe
Linux on Power Toolchain Architect
IBM Corporation, Linux Technology Center=
^ permalink raw reply
* Re: [PATCH/RFC] powerpc: Add Efika platform support
From: Benjamin Herrenschmidt @ 2006-11-01 22:19 UTC (permalink / raw)
To: Nicolas DET; +Cc: linuxppc-dev, sl, linuxppc-embedded
In-Reply-To: <45490394.8020202@bplan-gmbh.de>
On Wed, 2006-11-01 at 21:29 +0100, Nicolas DET wrote:
> +
> +static void efika_show_cpuinfo(struct seq_file *m)
> +{
> + struct device_node *root;
> + const char *revision = NULL;
> + const char *codegendescription = NULL;
> + const char *codegenvendor = NULL;
> +
> + root = of_find_node_by_path("/");
> + if (root) {
> + revision = get_property(root, "revision", NULL);
> + codegendescription =
> + get_property(root, "CODEGEN,description", NULL);
> + codegenvendor = get_property(root, "CODEGEN,vendor", NULL);
> + }
> +
> + if (codegendescription)
> + seq_printf(m, "machine\t\t: %s\n", codegendescription);
> + else
> + seq_printf(m, "machine\t\t: Efika\n");
> +
> + if (revision)
> + seq_printf(m, "revision\t: %s\n", revision);
> +
> + if (codegenvendor)
> + seq_printf(m, "vendor\t\t: %s\n", codegenvendor);
+ of_node_put(root);
> +
> +static void __init efika_init_IRQ(void)
> +{
> + mpc52xx_init_irq();
> +}
Ya pas moyen que mpc52xx_init_irq() ait le bon prototype pour que tu le
colle directement dans ppc_md. ?
> +
> + ISA_DMA_THRESHOLD = ~0L;
> + DMA_MODE_READ = 0x44;
> + DMA_MODE_WRITE = 0x48;
Ca viens de CHRP ca ? Je suis pas sur que ca soit super utile... mais
bon, ca mange pas de pain.. Au cas ou qqun colle un southbridge ISA sur
le bus PCI :)
> +void __init efika_pcisetup(void)
> +{
> + const int *bus_range;
> + int len;
> + struct pci_controller *hose;
> + struct device_node *root;
> + struct device_node *pcictrl;
> +
> + root = of_find_node_by_path("/");
> + if (root == NULL) {
> + printk(KERN_WARNING EFIKA_PLATFORM_NAME
> + ": Unable to find the root node\n");
> + return;
> + }
> +
> + for (pcictrl = NULL;;) {
> + pcictrl = of_get_next_child(root, pcictrl);
> + if ((pcictrl == NULL) || (strcmp(pcictrl->name, "pci") == 0))
> + break;
> + }
> +
> + if (pcictrl == NULL) {
> + printk(KERN_WARNING EFIKA_PLATFORM_NAME
> + ": Unable to find the PCI bridge node\n");
> + return;
> + }
> +
> + of_node_put(pcictrl);
> + of_node_put(root);
Euh... non... tu fait pas of_node_put(pcictrl) avant de t'en servir...
tu fait ca quand tu as fini. Ca veut dire probablement changer test
"return" en "goto bail;" ou un truc du genre.
> + if (bus_range[1] == bus_range[0])
> + printk(KERN_INFO EFIKA_PLATFORM_NAME ": PCI bus %d",
> + bus_range[0]);
> + else
> + printk(KERN_INFO EFIKA_PLATFORM_NAME ": PCI buses %d..%d",
> + bus_range[0], bus_range[1]);
> + printk(" controlled by %s", pcictrl->full_name);
> + printk("\n");
You really need the above printk's ?
> + hose = pcibios_alloc_controller();
> + if (!hose) {
> + printk(KERN_WARNING EFIKA_PLATFORM_NAME
> + ": Can't allocate PCI controller structure for %s\n",
> + pcictrl->full_name);
> + return;
> + }
> +
> + hose->arch_data = pcictrl;
Et ici, tu garde une reference, donc to fait
hose->arch_data = of_node_get(pcictrl);
> + hose->first_busno = bus_range[0];
> + hose->last_busno = bus_range[1];
> + hose->ops = &rtas_pci_ops;
> +
> + pci_process_bridge_OF_ranges(hose, pcictrl, 0);
> +}
Le reste est bon.
On y est presque ! :)
Ben.
^ permalink raw reply
* Re: [PATCH/RFC] powerpc: Add MPC5200 Interrupt Controller support.
From: Dale Farnsworth @ 2006-11-01 22:21 UTC (permalink / raw)
To: Sven Luther; +Cc: linuxppc-embedded, linuxppc-dev
In-Reply-To: <20061101220708.GA3328@powerlinux.fr>
On Wed, Nov 01, 2006 at 11:07:08PM +0100, Sven Luther wrote:
> On Wed, Nov 01, 2006 at 10:05:43PM -0000, Dale Farnsworth wrote:
> > In article <454902F9.20206@bplan-gmbh.de> Nicolas wrote:
> > > --- a/arch/powerpc/sysdev/mpc52xx_pic.c 1970-01-01 01:00:00.000000000 +0100
> > > +++ b/arch/powerpc/sysdev/mpc52xx_pic.c 2006-11-01 21:16:40.000000000 +0100
> > > @@ -0,0 +1,566 @@
> > > +/*
> > > + *
> > > + * Programmable Interrupt Controller functions for the Freescale MPC52xx.
> > > + *
> > > + * Copyright (C) 2006 bplan GmbH
> > > + *
> > > + * This file is licensed under the terms of the GNU General Public License
> >
> > Once again, please restore the copyright lines you removed from this file.
>
> Hehe, you are aware that, IIRW, someone suggested to cut them earlier in this
> thread ?
I think people called for removing the "Maintained by" and the
changelog-like commentary, but not the copyrights.
-Dale
^ permalink raw reply
* Re: [PATCH/RFC] powerpc: Add of_platform support for OHCI/Bigendian HC
From: Benjamin Herrenschmidt @ 2006-11-01 22:23 UTC (permalink / raw)
To: Nicolas DET; +Cc: linuxppc-dev, sl, linuxppc-embedded
In-Reply-To: <45490407.1010700@bplan-gmbh.de>
On Wed, 2006-11-01 at 21:31 +0100, Nicolas DET wrote:
> +/**+ ohci = hcd_to_ohci(hcd);
> + ohci->flags |= OHCI_BIG_ENDIAN;
> + ohci_hcd_init(ohci);
Bon, c'est pas mal. Le seul truc ici, c'est que je prefererais que
big-endian ne soit pas hard-code comme ca mais depende du device-tree.
Ce code doit pouvoir etre re-utilise pour des implementations
little-endian.
> + retval = usb_add_hcd(hcd, irq, IRQF_DISABLED);
> + if (retval == 0)
> + return retval;
Pourquoi IRQF_DISABLED ?
> +module_init(ohci_hcd_ppc_of_init);
> +module_exit(ohci_hcd_ppc_of_cleanup);
> --- a/drivers/usb/host/Kconfig 2006-11-01 09:18:56.000000000 +0100
> +++ b/drivers/usb/host/Kconfig 2006-11-01 21:16:06.000000000 +0100
> @@ -106,6 +106,14 @@ config USB_OHCI_HCD_PPC_SOC
> Enables support for the USB controller on the MPC52xx or
> STB03xxx processor chip. If unsure, say Y.
>
> +config USB_OHCI_HCD_PPC_OF
> + bool "OHCI support for PPC USB controller for OpenFirmware platform"
> + depends on USB_OHCI_HCD && PPC_OF
> + default y
> + select USB_OHCI_BIG_ENDIAN
> + ---help---
> + Enables support for the USB controller PowerPC OpenFirmware platform
> +
Je prefererais que USB_OHCI_BIG_ENDIAN soit une option a choisir.
Ben.
^ permalink raw reply
* Re: glibc-2.5 test suite hangs/crashes the machine
From: Benjamin Herrenschmidt @ 2006-11-01 22:35 UTC (permalink / raw)
To: Steve Munroe
Cc: linuxppc-dev, Jeff Bailey, Fabio Massimo Di Nitto, Paul Mackerras,
Ben Collins
In-Reply-To: <OF160F7BCC.ADD0D85F-ON86257219.00795AB5-86257219.007A72E6@us.ibm.com>
> The tst-robustpi# test are exercising the new PTHREAD_MUXTEX_ROBUST api,
> with PTHREAD_PRIO_INHERIT attribute.
>
> The fuxtex word seems to include the waiters TID, I don't know if the
> kernel cares about this or not.
Ok, well, we have seen a few issues so far with these. 2 are kernel
issues, but one might not be:
- kernels 2.6.15 .. .17 at least it seems wire the robust futex
syscalls on powerpc without properly implementing the support, which can
cause hangs in process exit. Do you have any way to "blacklist" kernels
in glibc ?
- kernel 2.6.18 and current git until yesterday (fix got in today) has
a bug if you manage to pass a wrong futex with a non-aligned atomic
value, it will possibly oops the kernel. With the fix, it will return an
error.
Now what seems to be a glibc issue:
- I've had the tst-robustpi# tests (in fact the very first one, I
haven't tested the others) die on me with a SIGBUS caused by glibc
trying to do a lwarx/starx. on an odd address.
I do not know for sure yet if the crash reported by Fabio with 2.6.19
(before my fix above) was related to the same kind of misaligned futex
managing to reach the kernel and triggering the oops I've talked about,
but it's very possible.
In my case, glibc was built against 2.6.16 headers, in fabio case, I
think it was built against 2.6.15 or .17 headers. It -seems- that fabio
cannot reproduce the problem when building glibc against 2.6.19 headers,
though at this point I can't explain why and I haven't reproduced here
yet.
Do you have any insight in what might be happening or should we just dig
more ?
Cheers,
Ben.
^ permalink raw reply
* Re: [PATCH] powerpc: Eliminate "exceeds stub group size" linker warning
From: Paul Mackerras @ 2006-11-01 22:43 UTC (permalink / raw)
To: Linus Torvalds; +Cc: akpm, linuxppc-dev, linux-kernel
In-Reply-To: <Pine.LNX.4.64.0611010647040.25218@g5.osdl.org>
Linus Torvalds writes:
> Hmm. I'd love to get rid of the warnings, because they obviously mean that
> I don't look at warnings much at all ("they're all bogus"), but this patch
> must be against some version of arch/powerpc/kernel/head_64.S that I've
> never seen.
Sorry, my mistake, it was against the "master" head of the powerpc.git
tree. New patch coming.
Paul.
^ permalink raw reply
* [PATCH v2] powerpc: Eliminate "exceeds stub group size" linker warning
From: Paul Mackerras @ 2006-11-01 22:44 UTC (permalink / raw)
To: Linus Torvalds; +Cc: akpm, linuxppc-dev, linux-kernel
It turns out that the linker warnings on 64-bit powerpc about "section
blah exceeds stub group size" were being triggered by conditional
branches in head_64.S branching to global symbols, whether in
head_64.S or in other files. This eliminates the warnings by making
some global symbols in head_64.S no longer global, and by rearranging
some branches.
Signed-off-by: Paul Mackerras <paulus@samba.org>
---
diff --git a/arch/powerpc/kernel/head_64.S b/arch/powerpc/kernel/head_64.S
index 291e362..e720729 100644
--- a/arch/powerpc/kernel/head_64.S
+++ b/arch/powerpc/kernel/head_64.S
@@ -487,7 +487,7 @@ BEGIN_FTR_SECTION
rlwimi r13,r12,16,0x20
mfcr r12
cmpwi r13,0x2c
- beq .do_stab_bolted_pSeries
+ beq do_stab_bolted_pSeries
mtcrf 0x80,r12
mfspr r12,SPRN_SPRG2
END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
@@ -600,7 +600,7 @@ #endif /* CONFIG_CBE_RAS */
STD_EXCEPTION_PSERIES(., performance_monitor)
.align 7
-_GLOBAL(do_stab_bolted_pSeries)
+do_stab_bolted_pSeries:
mtcrf 0x80,r12
mfspr r12,SPRN_SPRG2
EXCEPTION_PROLOG_PSERIES(PACA_EXSLB, .do_stab_bolted)
@@ -1046,7 +1046,7 @@ slb_miss_fault:
li r5,0
std r4,_DAR(r1)
std r5,_DSISR(r1)
- b .handle_page_fault
+ b handle_page_fault
unrecov_user_slb:
EXCEPTION_PROLOG_COMMON(0x4200, PACA_EXGEN)
@@ -1174,12 +1174,13 @@ program_check_common:
.globl fp_unavailable_common
fp_unavailable_common:
EXCEPTION_PROLOG_COMMON(0x800, PACA_EXGEN)
- bne .load_up_fpu /* if from user, just load it up */
+ bne 1f /* if from user, just load it up */
bl .save_nvgprs
addi r3,r1,STACK_FRAME_OVERHEAD
ENABLE_INTS
bl .kernel_fp_unavailable_exception
BUG_OPCODE
+1: b .load_up_fpu
.align 7
.globl altivec_unavailable_common
@@ -1279,10 +1280,10 @@ _GLOBAL(do_hash_page)
std r4,_DSISR(r1)
andis. r0,r4,0xa450 /* weird error? */
- bne- .handle_page_fault /* if not, try to insert a HPTE */
+ bne- handle_page_fault /* if not, try to insert a HPTE */
BEGIN_FTR_SECTION
andis. r0,r4,0x0020 /* Is it a segment table fault? */
- bne- .do_ste_alloc /* If so handle it */
+ bne- do_ste_alloc /* If so handle it */
END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
/*
@@ -1324,7 +1325,7 @@ BEGIN_FW_FTR_SECTION
* because ret_from_except_lite will check for and handle pending
* interrupts if necessary.
*/
- beq .ret_from_except_lite
+ beq 13f
/* For a hash failure, we don't bother re-enabling interrupts */
ble- 12f
@@ -1346,14 +1347,14 @@ BEGIN_FW_FTR_SECTION
END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES)
/* Here we have a page fault that hash_page can't handle. */
-_GLOBAL(handle_page_fault)
+handle_page_fault:
ENABLE_INTS
11: ld r4,_DAR(r1)
ld r5,_DSISR(r1)
addi r3,r1,STACK_FRAME_OVERHEAD
bl .do_page_fault
cmpdi r3,0
- beq+ .ret_from_except_lite
+ beq+ 13f
bl .save_nvgprs
mr r5,r3
addi r3,r1,STACK_FRAME_OVERHEAD
@@ -1370,12 +1371,14 @@ _GLOBAL(handle_page_fault)
bl .low_hash_fault
b .ret_from_except
+13: b .ret_from_except_lite
+
/* here we have a segment miss */
-_GLOBAL(do_ste_alloc)
+do_ste_alloc:
bl .ste_allocate /* try to insert stab entry */
cmpdi r3,0
- beq+ fast_exception_return
- b .handle_page_fault
+ bne- handle_page_fault
+ b fast_exception_return
/*
* r13 points to the PACA, r9 contains the saved CR,
^ permalink raw reply related
* Re: glibc-2.5 test suite hangs/crashes the machine
From: Steve Munroe @ 2006-11-01 22:56 UTC (permalink / raw)
To: Benjamin Herrenschmidt
Cc: linuxppc-dev, Jeff Bailey, Fabio Massimo Di Nitto, Paul Mackerras,
Ben Collins
In-Reply-To: <1162420552.25682.471.camel@localhost.localdomain>
Benjamin Herrenschmidt <benh@kernel.crashing.org> wrote on 11/01/2006
04:35:52 PM:
>
> > The tst-robustpi# test are exercising the new PTHREAD_MUXTEX_ROBUST
api,
> > with PTHREAD_PRIO_INHERIT attribute.
> >
> > The fuxtex word seems to include the waiters TID, I don't know if the
> > kernel cares about this or not.
>
> Ok, well, we have seen a few issues so far with these. 2 are kernel
> issues, but one might not be:
>
> - kernels 2.6.15 .. .17 at least it seems wire the robust futex
> syscalls on powerpc without properly implementing the support, which can
> cause hangs in process exit. Do you have any way to "blacklist" kernels
> in glibc ?
>
>From libc/sysdeps/unix/sysv/linux/kernel-features.h
/* Support for inter-process robust mutexes was added in 2.6.17. */
#if __LINUX_KERNEL_VERSION >= 0x020611
# define __ASSUME_SET_ROBUST_LIST 1
#endif
/* Support for PI futexes was added in 2.6.18. */
#if __LINUX_KERNEL_VERSION >= 0x020612
# define __ASSUME_FUTEX_LOCK_PI 1
#endif
So I need to delay __ASSUME_SET_ROBUST_LIST to 2.6.18 for __powerpc__ ?
What about __ASSUME_FUTEX_LOCK_PI ?
> - kernel 2.6.18 and current git until yesterday (fix got in today) has
> a bug if you manage to pass a wrong futex with a non-aligned atomic
> value, it will possibly oops the kernel. With the fix, it will return an
> error.
>
> Now what seems to be a glibc issue:
>
> - I've had the tst-robustpi# tests (in fact the very first one, I
> haven't tested the others) die on me with a SIGBUS caused by glibc
> trying to do a lwarx/starx. on an odd address.
>
Rayn reminded me of a bug where the new robust code did not account for the
fact that the TID was not at the same place as i386. I think Ryan has a
patch.
Steven J. Munroe
Linux on Power Toolchain Architect
IBM Corporation, Linux Technology Center
^ permalink raw reply
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