* Re: [PATCH 2.6.19-rc4 1/3] ehea: Nullpointer dereferencation fix
From: Jeff Garzik @ 2006-11-06 7:55 UTC (permalink / raw)
To: Thomas Klein
Cc: Thomas Klein, Jan-Bernd Themann, netdev, linux-kernel,
Christoph Raisch, linux-ppc, Marcus Eder
In-Reply-To: <200611031747.21667.osstklei@de.ibm.com>
applied 1-3
^ permalink raw reply
* Re: Can't build drivers/infiniband/hw/ipath/ipath_keys.c on arch/powerpc
From: Benjamin Herrenschmidt @ 2006-11-06 8:06 UTC (permalink / raw)
To: michael; +Cc: support, Andrew Morton, openib-general, linuxppc-dev list
In-Reply-To: <1162798399.8175.24.camel@localhost.localdomain>
On Mon, 2006-11-06 at 18:33 +1100, Michael Ellerman wrote:
> Hi,
>
> Just a heads-up, drivers/infiniband/hw/ipath/ipath_keys.c doesn't build
> on powerpc because we have don't have bus_to_virt().
>
> (Actually you can't select CONFIG_INFINIBAND_IPATH on mainline because
> powerpc doesn't enable PCI_MSI, but we will real soon now, and when we
> do this will start breaking people's all modconfig builds).
I'm surprised that something as recent as infiniband requires a
long-deprecated function bus_to_virt().
What is it trying to do there that needs that call ?
Ben.
^ permalink raw reply
* Re: [openib-general] Can't build drivers/infiniband/hw/ipath/ipath_keys.c on arch/powerpc
From: Robert Walsh @ 2006-11-06 7:42 UTC (permalink / raw)
To: Michael Ellerman
Cc: support, Andrew Morton, openib-general, linuxppc-dev list
In-Reply-To: <1162798399.8175.24.camel@localhost.localdomain>
Michael Ellerman wrote:
> Hi,
>
> Just a heads-up, drivers/infiniband/hw/ipath/ipath_keys.c doesn't build
> on powerpc because we have don't have bus_to_virt().
>
> (Actually you can't select CONFIG_INFINIBAND_IPATH on mainline because
> powerpc doesn't enable PCI_MSI, but we will real soon now, and when we
> do this will start breaking people's all modconfig builds).
Thanks for the heads-up. We're working to remove this requirement as we
speak.
Regards,
Robert.
^ permalink raw reply
* Re: [openib-general] Can't build drivers/infiniband/hw/ipath/ipath_keys.c on arch/powerpc
From: Michael Ellerman @ 2006-11-06 8:31 UTC (permalink / raw)
To: Robert Walsh; +Cc: support, Andrew Morton, openib-general, linuxppc-dev list
In-Reply-To: <454EE778.2030109@pathscale.com>
[-- Attachment #1: Type: text/plain, Size: 818 bytes --]
On Sun, 2006-11-05 at 23:42 -0800, Robert Walsh wrote:
> Michael Ellerman wrote:
> > Hi,
> >
> > Just a heads-up, drivers/infiniband/hw/ipath/ipath_keys.c doesn't build
> > on powerpc because we have don't have bus_to_virt().
> >
> > (Actually you can't select CONFIG_INFINIBAND_IPATH on mainline because
> > powerpc doesn't enable PCI_MSI, but we will real soon now, and when we
> > do this will start breaking people's all modconfig builds).
>
> Thanks for the heads-up. We're working to remove this requirement as we
> speak.
Sweet.
cheers
--
Michael Ellerman
OzLabs, IBM Australia Development Lab
wwweb: http://michael.ellerman.id.au
phone: +61 2 6212 1183 (tie line 70 21183)
We do not inherit the earth from our ancestors,
we borrow it from our children. - S.M.A.R.T Person
[-- Attachment #2: This is a digitally signed message part --]
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^ permalink raw reply
* Flash programming using a BDI2000 on a MPC8248 CPU
From: Laurent Pinchart @ 2006-11-06 8:42 UTC (permalink / raw)
To: linuxppc-embedded
Hi everybody,
I'm having problems using my BDI2000 to program an external flash on a MPC8248
board. I contacted Abatron's technical support (through its French
distributor, as nobody at Abatron seems to speak English or French). They
haven't been able to provide a solution (they really don't seem to care)
after more than a month, so I'm hoping to find some help here.
I can't get the BDI2000 to program the flash using the internal workspace
(fast algorithm) on a blank flash.
What works:
- Programming the flash without using the internal workspace (slow, JTAG-only
algorithm).
- Programming the flash using the internal workspace ONLY WHEN the flash has
already been programmed with a valid U-Boot copy, and the breakpoint
specified in the BDI2000 configuration file (BOOTADDR) is set to a wrong
value.
What doesn't work:
- Programming the flash using the internal workspace when the flash is empty.
- Programming the flash using the internal workspace when the flash has
already been programmed with a valid U-Boot copy, and the breakpoint
specified in the BDI2000 configuration file (BOOTADDR) is set to the right
value.
When the reset breakpoints fails (BOOTADDR set to 0x00000100 instead of
0xFFF00100 for instance), U-Boot starts to initialize the board before the
BDI2000 freezes the CPU. I assume that must be the reason why programming the
flash using the internal workspace then works. I tried having a look at the
U-Boot startup code, and initializing the same registers in the BDI2000
configuration file, but without success. I probably missed something.
Here is my BDI2000 configuration file. The hardware reset configuration word
is set to 0x00000000.
-----------------------------------------------------------------------------
[INIT]
WREG MSR 0x00000000
WM32 0x00010004 0xffff2081 ; SYPCR
WM32 0x00010024 0x00000000 ; BCR
WM32 0x00010000 0x82240000 ; SIUMCR
WM32 0x00010c80 0x00000001 ; SCCR
WM32 0x000119c4 0x00000000 ; RCCR
; Initialize the flash memory controller
WM32 0x00010100 0x40001001 ; BR0
WM32 0x00010104 0xf8000834 ; OR0
[TARGET]
CPUTYPE 8260 ; the CPU type (603EV,750,8240,8260)
JTAGCLOCK 0 ; use 16 MHz JTAG clock
BOOTADDR 0xFFF00100
BDIMODE AGENT ; the BDI working mode
BREAKMODE SOFT ; SOFT or HARD
VECTOR CATCH ; catch unhandled exceptions
DCACHE NOFLUSH ; data cache flushing (FLUSH | NOFLUSH)
SIO 2002 115200
[FLASH]
CHIPTYPE MIRRORX16 ; Flash type
CHIPSIZE 0x1000000 ; The size of one flash chip in bytes
BUSWIDTH 16 ; The width of the flash memory bus in bits
ERASE 0x40000000 CHIP
FILE u-boot.bin
FORMAT BIN
;WORKSPACE 0x00008000
[HOST]
IP 192.168.2.1
LOAD MANUAL ; load code MANUAL or AUTO after reset
[REGS]
DMM1 0x00000000
FILE bdi2000/reg8272.def
-----------------------------------------------------------------------------
Any help would be greatly appreciated (and would also prove community support
is better than Abatron's commercial support ;-) ).
Best regards,
Laurent Pinchart
^ permalink raw reply
* Re: [PATCH/RFC] powerpc: Add MPC5200 Interrupt Controller support.
From: Sylvain Munaut @ 2006-11-06 8:39 UTC (permalink / raw)
To: Grant Likely; +Cc: linuxppc-embedded, sl, linuxppc-dev
In-Reply-To: <528646bc0611052228j20a4c197x94da47467dce8d67@mail.gmail.com>
Grant Likely wrote:
> On 11/4/06, Benjamin Herrenschmidt <benh@kernel.crashing.org> wrote:
>> On Sun, 2006-11-05 at 01:27 +0100, Sylvain Munaut wrote:
>> > with a helper that would do
>> > - The find_node
>> > - get_address / translate / get_size
>> > - ioremap
>> >
>> > Something like :
>> >
>> > intr = mpc52xx_find_and_map("mpc52xx-intr");
>> > sdma = mpc52xx_find_and_map("mpc52xx-sdma");
>>
>> Hrm... I don't care that much but I also don't think we need that
>> helper. It's not saving much.
>
> While on this topic... if a helper is added, what about it is 52xx
> specific? Wouldn't the same code apply to all platforms?
>
> g.
>
The code would look like what I included at the end (untested). Not that
I used
of_find_by_name and not find_compatible. We can fix a naming convention
for those units ...
I think it does save quite a few lines and variable. It also simplifies the
error path ... granted it's not an exceptionnal reduction but still
worth it.
If it's not included now it's not that bad, I'll probably submitt a
patch later
when it's used in more places than mpc52xx_pic.c ...
About the use on other platform, maybe but do other platform need that a
lot ?
Here we have several unit that need to be mapped at different places ...
Sylvain
---
void __iomem *mpc52xx_find_and_map(const char *name)
{
struct device_node *ofn;
const u32 *regaddr_p;
u64 regaddr64, size64;
ofn = of_find_by_name(NULL, name);
if (!ofn)
return NULL;
regaddr_p = of_get_address(ofn, 0, &size64, NULL);
if (!regaddr_p) {
of_node_put(ofn);
return NULL;
}
regaddr64 = of_translate_address(ofn, regaddr_p);
of_node_put(ofn);
return ioremap((u32)regaddr64, (u32)size64);
}
^ permalink raw reply
* Re: [PATCH] Add MPC52xx PIO/ATA support for arch/powerpc
From: Roman Fietze @ 2006-11-06 9:13 UTC (permalink / raw)
To: linuxppc-embedded
In-Reply-To: <20061105105325.44e7287f.nd@bplan-gmbh.de>
[-- Attachment #1: Type: text/plain, Size: 662 bytes --]
Hallo,
On Sunday 05 November 2006 12:57, Nicolas DET wrote:
> This patch adds ATA/PIO support for Freescale MPC5200 plaforms.
Assumed I've got a preliminary version of an MPC5200 ATA driver with
BestComm ATA support (besides a FEC driver with DMA support as well)
mainly based on code from Sylvain Munaut, Dale Farnsworth and John
Rigby.
Would you recommend posting those patches here? They are working on
our platform, any comment would be appreciated.
Roman
--
Roman Fietze Telemotive AG Büro Mühlhausen
Breitwiesen 73347 Mühlhausen
Tel.: +49(0)7335/18493-45 http://www.telemotive.de
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^ permalink raw reply
* Re: [PATCH] Add MPC52xx PIO/ATA support for arch/powerpc
From: Sylvain Munaut @ 2006-11-06 9:25 UTC (permalink / raw)
To: Roman Fietze; +Cc: linuxppc-embedded
In-Reply-To: <200611061013.43676.roman.fietze@telemotive.de>
Roman Fietze wrote:
> Hallo,
>
> On Sunday 05 November 2006 12:57, Nicolas DET wrote:
>
>
>> This patch adds ATA/PIO support for Freescale MPC5200 plaforms.
>>
>
> Assumed I've got a preliminary version of an MPC5200 ATA driver with
> BestComm ATA support (besides a FEC driver with DMA support as well)
> mainly based on code from Sylvain Munaut, Dale Farnsworth and John
> Rigby.
>
> Would you recommend posting those patches here? They are working on
> our platform, any comment would be appreciated.
>
You can post it won't hurt.
But bestcomm will change for it's arch/powerpc transition so they will need
adaptation ...
Sylvain
^ permalink raw reply
* Re: [PATCH 2.6.19 1/4] ehca: assure 4k alignment for firmware control block in 64k page mode
From: Hoang-Nam Nguyen @ 2006-11-06 10:00 UTC (permalink / raw)
To: Arnd Bergmann
Cc: linuxppc-dev, Christoph Raisch, linux-kernel, openib-general
In-Reply-To: <200611060045.59074.arnd@arndb.de>
Hi Arnd,
> This seems broken. You have a constructor for newly allocated objects,
but
> there is no destructor and it seems that objects passed to
> ehca_free_fw_ctrlblock are not guaranteed to be initialized either.
> I'd simply move the memset into the alloc function and get rid of the
> constructor here.
Yep, I was not aware that ctor is not called for every
kmem_cache_alloc(). Thx for pointing this out.
Nam
^ permalink raw reply
* Re: [patch 04/16] powerpc: remove dead code in iommu.h
From: Sascha Hauer @ 2006-11-06 10:19 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev
In-Reply-To: <1162709223.28571.213.camel@localhost.localdomain>
Subject: powerpc: remove dead code in iommu.h
From: Sascha Hauer <s.hauer@pengutronix.de>
iommu_setup_pSeries() and iommu_setup_dart() are declared extern but are
not implemented, so remove them. Remove ifdef around extern function
declaration.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Index: include/asm-powerpc/iommu.h
===================================================================
--- a/include/asm-powerpc/iommu.h.orig
+++ b/include/asm-powerpc/iommu.h
@@ -70,17 +70,9 @@ struct iommu_table {
struct scatterlist;
struct device_node;
-#ifdef CONFIG_PPC_MULTIPLATFORM
-
-/* Walks all buses and creates iommu tables */
-extern void iommu_setup_pSeries(void);
-extern void iommu_setup_dart(void);
-
/* Frees table for an individual device node */
extern void iommu_free_table(struct device_node *dn);
-#endif /* CONFIG_PPC_MULTIPLATFORM */
-
/* Initializes an iommu_table based in values set in the passed-in
* structure
*/
--
Dipl.-Ing. Sascha Hauer | http://www.pengutronix.de
Pengutronix - Linux Solutions for Science and Industry
Handelsregister: Amtsgericht Hildesheim, HRA 2686
Hannoversche Str. 2, 31134 Hildesheim, Germany
Phone: +49-5121-206917-0 | Fax: +49-5121-206917-9
^ permalink raw reply
* Linux Kernel 2.6 on Artesyn Katana Board (3750) with IBM 750FX PP C
From: Goel, Mudit (Mudit) @ 2006-11-06 10:11 UTC (permalink / raw)
To: 'linuxppc-embedded@ozlabs.org'
All ,
We have Artesyn Katana Boards with ppc boot version 1.2.0 (with different
release dates ).We have MV Linux to be
used on these cards.
We are trying to upgrade the kernel to 2.6. The kernel upgrade is success
on one card with ppc boot version 1.2
with release date of July 2004.
But all other cards which have different dates but same boot version the
kernel upgrade is not successful.
Here is the boot output
----------------------------
P1(2.01)=>go 0x08010000
## Starting application at 0x08010000 ...
loaded at: 08010000 081EA320
relocated to: 00800000 009DA320
zimage at: 00805909 009D78BD
avail ram: 00700000 00B00000
max kernel: 00600000
Linux/PPC load: root=/dev/nfs rw nfsroot=172.31.4.10:/app2/cpsbeplg
nfsaddrs=172
.31.4.50:172.31.4.10:172.31.4.254:255.255.255.0:cpsbcicc-50:eth0:off
Uncompressing Linux...done.
Now booting the kernel
Total memory = 256MB; using 512kB for hash table (at c0480000)
Linux version 2.6.10_mvlcge401-katana (root@hdrlin03) (gcc version 3.4.3
(MontaV
ista 3.4.3-25.0.41.0501420 2005-09-07)) #29 Mon Nov 6 14:58:36 IST 2006
RMON: rmon_first_init
Artesyn Communication Products, LLC - Katana(TM)
Real-Time Preemption Support (c) Ingo Molnar
Built 1 zonelists
Kernel command line: root=/dev/nfs rw nfsroot=172.31.4.10:/app2/cpsbeplg
nfsaddr
s=172.31.4.50:172.31.4.10:172.31.4.254:255.255.255.0:cpsbcicc-50:eth0:off
PID hash table entries: 2048 (order: 11, 32768 bytes)
time_init: decrementer frequency = 33.333333 MHz
Console: colour dummy device 80x25
Dentry cache hash table entries: 65536 (order: 6, 262144 bytes)
Inode-cache hash table entries: 32768 (order: 5, 131072 bytes)
Memory: 254576k available (2856k kernel code, 1468k data, 152k init, 0k
highmem)
RMON - kernel resource monitoring
Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
spawn_desched_task(00000000)
desched cpu_callback 3/00000000
ksoftirqd started up.
softirq RT prio: 24.
desched cpu_callback 2/00000000
desched thread 0 started up.
NET: Registered protocol family 16
PCI: Probing PCI hardware
VFS: Disk quotas dquot_6.5.1
Dquot-cache hash table entries: 1024 (order 0, 4096 bytes)
JFFS2 version 2.2. (NAND) (C) 2001-2003 Red Hat, Inc.
SGI XFS with ACLs, no debug enabled
SGI XFS Quota Management subsystem
Initializing Cryptographic API
Fast Real Time Domain (c) 2005 Montavista Software, Inc.
FRD major device number is 254
Generic RTC Driver v1.07
Serial: MPSC driver $Revision: 1.00 $
ttyMM0 at MMIO 0xd10bc000 (irq = 36) is a MPSC
ttyMM1 at MMIO 0xd10c2000 (irq = 38) is a MPSC
io scheduler noop registered
io scheduler anticipatory registered
io scheduler deadline registered
io scheduler cfq registered
RAMDISK driver initialized: 16 RAM disks of 8192K size 1024 blocksize
loop: loaded (max 8 devices)
MV-643xx 10/100/1000 Ethernet Driver
eth0: port 2 with MAC address 00:80:f9:64:a8:c0
eth0: RX NAPI Enabled
i2c /dev entries driver
IPMB I2C Client 0.07 05 Nov 2004 - Loaded on address 0x08 (0x10)
mv64xxx: i2c slave interface enabled
Local Slave Address: 80
Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2
ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx
elevator: using anticipatory as default io scheduler
physmap flash device: 4000000 at e0000000
phys_mapped_flash: Found 2 x16 devices at 0x0 in 32-bit bank
Intel/Sharp Extended Query Table at 0x0031
Using buffer write method
cfi_cmdset_0001: Erase suspend on write enabled
cmdlinepart partition parsing not available
RedBoot partition parsing not available
Using physmap partition definition
Creating 6 MTD partitions on "phys_mapped_flash":
0x00000000-0x00100000 : "Monitor"
0x00100000-0x00300000 : "Primary Kernel"
0x00300000-0x02080000 : "Primary Filesystem"
0x02080000-0x02280000 : "Secondary Kernel"
0x02280000-0x04000000 : "Secondary Filesystem"
0x00100000-0x04000000 : "User FLASH"
mice: PS/2 mouse device common for all mice
NET: Registered protocol family 2
IP: routing cache hash table of 256 buckets, 14Kbytes
TCP: Hash tables configured (established 2048 bind 2340)
NET: Registered protocol family 1
NET: Registered protocol family 17
IP-Config: Complete:
device=eth0, addr=172.31.4.50, mask=255.255.255.0, gw=172.31.4.254,
host=cpsbcicc-50, domain=, nis-domain=(none),
bootserver=172.31.4.10, rootserver=172.31.4.10, rootpath=
Looking up port of RPC 100003/2 on 172.31.4.10
portmap: server 172.31.4.10 not responding, timed out
Root-NFS: Unable to get nfsd port number from server, using default
Looking up port of RPC 100005/1 on 172.31.4.10
portmap: server 172.31.4.10 not responding, timed out
Root-NFS: Unable to get mountd port number from server, using default
mount: server 172.31.4.10 not responding, timed out
Root-NFS: Server returned error -5 while mounting /app2/cpsbeplg
VFS: Unable to mount root fs via NFS, trying floppy.
VFS: Cannot open root device "nfs" or unknown-block(2,0)
Please append a correct "root=" boot option
Kernel panic - not syncing: VFS: Unable to mount root fs on
unknown-block(2,0)
<0>Rebooting in 180 seconds..
---------------------------
Thanx
Mudit Goel
^ permalink raw reply
* [PATCH/RFC] powerpc: Add MPC5200 Interrupt Controller support.
From: Nicolas DET @ 2006-11-06 10:26 UTC (permalink / raw)
To: linuxppc-embedded; +Cc: linuxppc-dev
This patch add MPC52xx Interrupt controller for ARCH=3Dpowerpc.
It includes the main code in arch/powerpc/sysdev/ ad well as an header file=
in include/asm-powerpc.
Signed-off-by: Nicolas DET <nd@bplan-gmbh.de>
---
--- a/arch/powerpc/sysdev/mpc52xx_pic.c=091970-01-01 01:00:00.000000000 +01=
00
+++ b/arch/powerpc/sysdev/mpc52xx_pic.c=092006-11-06 11:10:29.000000000 +01=
00
@@ -0,0 +1,527 @@
+/*
+ *
+ * Programmable Interrupt Controller functions for the Freescale MPC52xx.
+ *
+ * Copyright (C) 2006 bplan GmbH
+ *
+ * Based on (well, mostly copied from) the code from the 2.4 kernel by
+ * Dale Farnsworth <dfarnsworth@mvista.com> and Kent Borg.
+ *=20
+ * Copyright (C) 2004 Sylvain Munaut <tnt@246tNt.com>
+ * Copyright (C) 2003 Montavista Software, Inc
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ *
+ */
+
+#undef DEBUG
+
+#include <linux/stddef.h>
+#include <linux/init.h>
+#include <linux/sched.h>
+#include <linux/signal.h>
+#include <linux/stddef.h>
+#include <linux/delay.h>
+#include <linux/irq.h>
+#include <linux/hardirq.h>
+
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <asm/system.h>
+#include <asm/irq.h>
+#include <asm/prom.h>
+#include <asm/mpc52xx.h>
+
+/*
+ *
+*/
+
+static struct mpc52xx_intr __iomem *intr;
+static struct mpc52xx_sdma __iomem *sdma;
+static struct irq_host *mpc52xx_irqhost =3D NULL;
+
+static unsigned char mpc52xx_map_senses[4] =3D {
+=09IRQ_TYPE_LEVEL_HIGH,
+=09IRQ_TYPE_EDGE_RISING,
+=09IRQ_TYPE_EDGE_FALLING,
+=09IRQ_TYPE_LEVEL_LOW,
+};
+
+/*
+ *
+*/
+
+static inline void io_be_setbit(u32 __iomem *addr, int bitno)
+{
+=09out_be32(addr, in_be32(addr) | (1 << bitno) );
+}
+
+static inline void io_be_clrbit(u32 __iomem *addr, int bitno)
+{
+=09out_be32(addr, in_be32(addr) & ~(1 << bitno));
+}
+
+/*
+ * IRQ[0-3] interrupt irq_chip
+*/
+
+static void mpc52xx_extirq_mask(unsigned int virq)
+{
+=09int irq;
+=09int l2irq;
+
+=09irq =3D irq_map[virq].hwirq;
+=09l2irq =3D (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
+
+=09pr_debug("%s: irq=3D%x. l2=3D%dn", __func__, irq, l2irq);
+
+=09io_be_clrbit(&intr->ctrl, 11 - l2irq);
+}
+
+static void mpc52xx_extirq_unmask(unsigned int virq)
+{
+=09int irq;
+=09int l2irq;
+
+=09irq =3D irq_map[virq].hwirq;
+=09l2irq =3D (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
+
+=09pr_debug("%s: irq=3D%x. l2=3D%dn", __func__, irq, l2irq);
+
+=09io_be_setbit(&intr->ctrl, 11 - l2irq);
+}
+
+static void mpc52xx_extirq_ack(unsigned int virq)
+{
+=09int irq;
+=09int l2irq;
+
+=09irq =3D irq_map[virq].hwirq;
+=09l2irq =3D (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
+
+=09pr_debug("%s: irq=3D%x. l2=3D%dn", __func__, irq, l2irq);
+
+=09io_be_setbit(&intr->ctrl, 27-l2irq);
+}
+
+static struct irq_chip mpc52xx_extirq_irqchip =3D {
+=09.typename =3D " MPC52xx IRQ[0-3] ",
+=09.mask =3D mpc52xx_extirq_mask,
+=09.unmask =3D mpc52xx_extirq_unmask,
+=09.ack =3D mpc52xx_extirq_ack,
+};
+
+/*
+ * Main interrupt irq_chip
+*/
+
+static void mpc52xx_main_mask(unsigned int virq)
+{
+=09int irq;
+=09int l2irq;
+
+=09irq =3D irq_map[virq].hwirq;
+=09l2irq =3D (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
+
+=09pr_debug("%s: irq=3D%x. l2=3D%dn", __func__, irq, l2irq);
+
+=09io_be_setbit(&intr->main_mask, 15 - l2irq);
+}
+
+static void mpc52xx_main_unmask(unsigned int virq)
+{
+=09int irq;
+=09int l2irq;
+
+=09irq =3D irq_map[virq].hwirq;
+=09l2irq =3D (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
+
+=09pr_debug("%s: irq=3D%x. l2=3D%dn", __func__, irq, l2irq);
+
+=09io_be_clrbit(&intr->main_mask, 15 - l2irq);
+}
+
+static struct irq_chip mpc52xx_main_irqchip =3D {
+=09.typename =3D "MPC52xx Main",
+=09.mask =3D mpc52xx_main_mask,
+=09.mask_ack =3D mpc52xx_main_mask,
+=09.unmask =3D mpc52xx_main_unmask,
+};
+
+/*
+ * Peripherals interrupt irq_chip
+*/
+
+static void mpc52xx_periph_mask(unsigned int virq)
+{
+=09int irq;
+=09int l2irq;
+
+=09irq =3D irq_map[virq].hwirq;
+=09l2irq =3D (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
+
+=09pr_debug("%s: irq=3D%x. l2=3D%dn", __func__, irq, l2irq);
+
+=09io_be_setbit(&intr->per_mask, 31 - l2irq);
+}
+
+static void mpc52xx_periph_unmask(unsigned int virq)
+{
+=09int irq;
+=09int l2irq;
+
+=09irq =3D irq_map[virq].hwirq;
+=09l2irq =3D (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
+
+=09pr_debug("%s: irq=3D%x. l2=3D%dn", __func__, irq, l2irq);
+
+=09io_be_clrbit(&intr->per_mask, 31 - l2irq);
+}
+
+static struct irq_chip mpc52xx_periph_irqchip =3D {
+=09.typename =3D "MPC52xx Peripherals",
+=09.mask =3D mpc52xx_periph_mask,
+=09.mask_ack =3D mpc52xx_periph_mask,
+=09.unmask =3D mpc52xx_periph_unmask,
+};
+
+/*
+ * SDMA interrupt irq_chip
+*/
+
+static void mpc52xx_sdma_mask(unsigned int virq)
+{
+=09int irq;
+=09int l2irq;
+
+=09irq =3D irq_map[virq].hwirq;
+=09l2irq =3D (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
+
+=09pr_debug("%s: irq=3D%x. l2=3D%dn", __func__, irq, l2irq);
+
+=09io_be_setbit(&sdma->IntMask, l2irq);
+}
+
+static void mpc52xx_sdma_unmask(unsigned int virq)
+{
+=09int irq;
+=09int l2irq;
+
+=09irq =3D irq_map[virq].hwirq;
+=09l2irq =3D (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
+
+=09pr_debug("%s: irq=3D%x. l2=3D%dn", __func__, irq, l2irq);
+
+=09io_be_clrbit(&sdma->IntMask, l2irq);
+}
+
+static void mpc52xx_sdma_ack(unsigned int virq)
+{
+=09int irq;
+=09int l2irq;
+
+=09irq =3D irq_map[virq].hwirq;
+=09l2irq =3D (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
+
+=09pr_debug("%s: irq=3D%x. l2=3D%dn", __func__, irq, l2irq);
+
+=09out_be32(&sdma->IntPend, 1 << l2irq);
+}
+
+static struct irq_chip mpc52xx_sdma_irqchip =3D {
+=09.typename =3D "MPC52xx SDMA",
+=09.mask =3D mpc52xx_sdma_mask,
+=09.unmask =3D mpc52xx_sdma_unmask,
+=09.ack =3D mpc52xx_sdma_ack,
+};
+
+/*
+ * irq_host
+*/
+
+static int mpc52xx_irqhost_match(struct irq_host *h, struct device_node *n=
ode)
+{
+=09pr_debug("%s: node=3D%pn", __func__, node);
+=09return mpc52xx_irqhost->host_data =3D=3D node;
+}
+
+static int mpc52xx_irqhost_xlate(struct irq_host *h, struct device_node *c=
t,
+=09=09=09=09 u32 * intspec, unsigned int intsize,
+=09=09=09=09 irq_hw_number_t * out_hwirq,
+=09=09=09=09 unsigned int *out_flags)
+{
+=09int intrvect_l1;
+=09int intrvect_l2;
+=09int intrvect_type;
+=09int intrvect_linux;
+
+=09if (intsize !=3D 3)
+=09=09return -1;
+
+=09intrvect_l1 =3D (int)intspec[0];
+=09intrvect_l2 =3D (int)intspec[1];
+=09intrvect_type =3D (int)intspec[2];
+
+=09intrvect_linux =3D
+=09 (intrvect_l1 << MPC52xx_IRQ_L1_OFFSET) & MPC52xx_IRQ_L1_MASK;
+=09intrvect_linux |=3D
+=09 (intrvect_l2 << MPC52xx_IRQ_L2_OFFSET) & MPC52xx_IRQ_L2_MASK;
+
+=09pr_debug("return %x, l1=3D%d, l2=3D%dn", intrvect_linux, intrvect_l1,
+=09=09 intrvect_l2);
+
+=09*out_hwirq =3D intrvect_linux;
+=09*out_flags =3D mpc52xx_map_senses[intrvect_type];
+
+=09return 0;
+}
+
+/*
+ * this function retrieves the correct IRQ type out
+ * of the MPC regs
+ * Only externals IRQs needs this
+*/
+static int mpc52xx_irqx_gettype(int irq)
+{
+=09int type;
+=09u32 ctrl_reg;
+
+=09ctrl_reg =3D in_be32(&intr->ctrl);
+=09type =3D (ctrl_reg >> (22 - irq * 2)) & 0x3;
+
+=09return mpc52xx_map_senses[type];
+}
+
+static int mpc52xx_irqhost_map(struct irq_host *h, unsigned int virq,
+=09=09=09 irq_hw_number_t irq)
+{
+=09int l1irq;
+=09int l2irq;
+=09struct irq_chip *good_irqchip;
+=09void *good_handle;
+=09int type;
+
+=09l1irq =3D (irq & MPC52xx_IRQ_L1_MASK) >> MPC52xx_IRQ_L1_OFFSET;
+=09l2irq =3D (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
+
+=09/*
+=09 * Most of ours IRQs will be level low
+=09 * Only external IRQs on some platform may be others
+=09 */
+=09type =3D IRQ_TYPE_LEVEL_LOW;
+
+=09switch (l1irq) {
+=09case MPC52xx_IRQ_L1_CRIT:
+=09=09pr_debug("%s: Critical. l2=3D%xn", __func__, l2irq);
+
+=09=09BUG_ON(l2irq !=3D 0);
+
+=09=09type =3D mpc52xx_irqx_gettype(l2irq);
+=09=09good_irqchip =3D &mpc52xx_extirq_irqchip;
+=09=09break;
+
+=09case MPC52xx_IRQ_L1_MAIN:
+=09=09pr_debug("%s: Main IRQ[1-3] l2=3D%xn", __func__, l2irq);
+
+=09=09if ((l2irq >=3D 1) && (l2irq <=3D 3)) {
+=09=09=09type =3D mpc52xx_irqx_gettype(l2irq);
+=09=09=09good_irqchip =3D &mpc52xx_extirq_irqchip;
+=09=09} else {
+=09=09=09good_irqchip =3D &mpc52xx_main_irqchip;
+=09=09}
+=09=09break;
+
+=09case MPC52xx_IRQ_L1_PERP:
+=09=09pr_debug("%s: Peripherals. l2=3D%xn", __func__, l2irq);
+=09=09good_irqchip =3D &mpc52xx_periph_irqchip;
+=09=09break;
+
+=09case MPC52xx_IRQ_L1_SDMA:
+=09=09pr_debug("%s: SDMA. l2=3D%xn", __func__, l2irq);
+=09=09good_irqchip =3D &mpc52xx_sdma_irqchip;
+=09=09break;
+
+=09default:
+=09=09pr_debug("%s: Error, unknown L1 IRQ (0x%x)n", __func__, l1irq);
+=09=09printk(KERN_ERR "Unknow IRQ!n");
+=09=09return -EINVAL;
+=09}
+
+=09switch (type) {
+=09case IRQ_TYPE_EDGE_FALLING:
+=09case IRQ_TYPE_EDGE_RISING:
+=09=09good_handle =3D handle_edge_irq;
+=09=09break;
+=09default:
+=09=09good_handle =3D handle_level_irq;
+=09}
+
+=09set_irq_chip_and_handler(virq, good_irqchip, good_handle);
+
+=09pr_debug("%s: virq=3D%x, hw=3D%x. type=3D%xn", __func__, virq,
+=09=09 (int)irq, type);
+
+=09return 0;
+}
+
+static struct irq_host_ops mpc52xx_irqhost_ops =3D {
+=09.match =3D mpc52xx_irqhost_match,
+=09.xlate =3D mpc52xx_irqhost_xlate,
+=09.map =3D mpc52xx_irqhost_map,
+};
+
+/*
+ * init (public)
+*/
+
+void __init mpc52xx_init_irq(void)
+{
+=09struct device_node *picnode =3D NULL;
+=09int picnode_regsize;
+=09u32 picnode_regoffset;
+
+=09struct device_node *sdmanode =3D NULL;
+=09int sdmanode_regsize;
+=09u32 sdmanode_regoffset;
+
+=09u64 size64;
+=09int flags;
+
+=09u32 intr_ctrl;
+
+=09picnode =3D of_find_compatible_node(NULL, "interrupt-controller", "mpc5=
200-pic");
+=09if (picnode =3D=3D NULL) {
+=09=09printk(KERN_ERR "MPC52xx PIC: Unable to find the interrupt controlle=
r in the OpenFirmware device treen");
+=09=09goto end;
+=09}
+
+=09sdmanode =3D of_find_compatible_node(NULL, "dma-controller", "mpc5200-b=
estcomm");
+=09if (sdmanode =3D=3D NULL) {
+=09=09printk(KERN_ERR "MPC52xx PIC: Unable to find the Bestcomm DMA contro=
ller device in the OpenFirmware device treen");
+=09=09goto end;
+=09}
+
+=09/* Retrieve PIC ressources */
+=09picnode_regoffset =3D (u32) of_get_address(picnode, 0, &size64, &flags)=
;
+=09if (picnode_regoffset =3D=3D 0) {
+=09=09printk(KERN_ERR "MPC52xx PIC: Unable to get the interrupt controller=
addressn");
+=09=09goto end;
+=09}
+
+=09picnode_regoffset =3D of_translate_address(picnode, (u32 *) picnode_reg=
offset);
+=09picnode_regsize =3D (int) size64;=09
+
+=09/* Retrieve SDMA ressources */
+=09sdmanode_regoffset =3D (u32) of_get_address(sdmanode, 0, &size64, &flag=
s);
+=09if (sdmanode_regoffset =3D=3D 0) {
+=09=09printk(KERN_ERR "MPC52xx PIC: Unable to get the Bestcomm DMA control=
ler addressn");
+=09=09goto end;
+=09}
+
+=09sdmanode_regoffset =3D of_translate_address(sdmanode, (u32 *) sdmanode_=
regoffset);
+=09sdmanode_regsize =3D (int) size64;
+
+=09/* Remap the necessary zones */
+=09intr =3D ioremap(picnode_regoffset, picnode_regsize);
+=09if (intr =3D=3D NULL) {
+=09=09printk(KERN_ERR "MPC52xx PIC: Unable to ioremap interrupt controller=
registers!");
+=09=09goto end;
+=09}
+
+=09sdma =3D ioremap(sdmanode_regoffset, sdmanode_regsize);
+=09if (sdma =3D=3D NULL) {
+=09=09iounmap(intr);
+=09=09printk(KERN_ERR "MPC52xx PIC: Unable to ioremap Bestcomm DMA control=
ler registers!");
+=09=09goto end;
+=09}
+
+=09printk(KERN_INFO "MPC52xx PIC: MPC52xx PIC Remapped at 0x%8.8xn", picno=
de_regoffset);
+=09printk(KERN_INFO "MPC52xx PIC: MPC52xx SDMA Remapped at 0x%8.8xn", sdma=
node_regoffset);
+
+=09/* Disable all interrupt sources. */
+=09out_be32(&sdma->IntPend, 0xffffffff);=09/* 1 means clear pending */
+=09out_be32(&sdma->IntMask, 0xffffffff);=09/* 1 means disabled */
+=09out_be32(&intr->per_mask, 0x7ffffc00);=09/* 1 means disabled */
+=09out_be32(&intr->main_mask, 0x00010fff);=09/* 1 means disabled */
+=09intr_ctrl =3D in_be32(&intr->ctrl);
+=09intr_ctrl &=3D 0x00ff0000;=09/* Keeps IRQ[0-3] config */
+=09intr_ctrl |=3D 0x0f000000 |=09/* clear IRQ 0-3 */
+=09 0x00001000 |=09/* MEE master external enable */
+=09 0x00000000 |=09/* 0 means disable IRQ 0-3 */
+=09 0x00000001;=09=09/* CEb route critical normally */
+=09out_be32(&intr->ctrl, intr_ctrl);
+
+=09/* Zero a bunch of the priority settings. */
+=09out_be32(&intr->per_pri1, 0);
+=09out_be32(&intr->per_pri2, 0);
+=09out_be32(&intr->per_pri3, 0);
+=09out_be32(&intr->main_pri1, 0);
+=09out_be32(&intr->main_pri2, 0);
+
+=09/*
+=09 * As last step, add an irq host to translate the real
+=09 * hw irq information provided by the ofw to linux virq
+=09 */
+
+=09mpc52xx_irqhost =3D
+=09 irq_alloc_host(IRQ_HOST_MAP_LINEAR, MPC52xx_IRQ_HIGHTESTHWIRQ,
+=09=09=09 &mpc52xx_irqhost_ops, -1);
+
+=09if (mpc52xx_irqhost) {
+=09=09mpc52xx_irqhost->host_data =3D picnode;
+=09=09printk(KERN_INFO "MPC52xx PIC is up and running!n");
+=09} else {
+=09=09printk(KERN_ERR "MPC52xx PIC: Unable to allocate the IRQ hostn");
+=09}
+
+end:
+=09of_node_put(picnode);
+=09of_node_put(sdmanode);
+}
+
+/*
+ * get_irq (public)
+*/
+unsigned int mpc52xx_get_irq(void)
+{
+=09u32 status;
+=09int irq =3D NO_IRQ_IGNORE;
+
+=09status =3D in_be32(&intr->enc_status);
+=09if (status & 0x00000400) {=09/* critical */
+=09=09irq =3D (status >> 8) & 0x3;
+=09=09if (irq =3D=3D 2)=09/* high priority peripheral */
+=09=09=09goto peripheral;
+=09=09irq |=3D
+=09=09 (MPC52xx_IRQ_L1_CRIT << MPC52xx_IRQ_L1_OFFSET) &
+=09=09 MPC52xx_IRQ_L1_MASK;
+=09} else if (status & 0x00200000) {=09/* main */
+=09=09irq =3D (status >> 16) & 0x1f;
+=09=09if (irq =3D=3D 4)=09/* low priority peripheral */
+=09=09=09goto peripheral;
+=09=09irq |=3D
+=09=09 (MPC52xx_IRQ_L1_MAIN << MPC52xx_IRQ_L1_OFFSET) &
+=09=09 MPC52xx_IRQ_L1_MASK;
+=09} else if (status & 0x20000000) {=09/* peripheral */
+=09 peripheral:
+=09=09irq =3D (status >> 24) & 0x1f;
+=09=09if (irq =3D=3D 0) {=09/* bestcomm */
+=09=09=09status =3D in_be32(&sdma->IntPend);
+=09=09=09irq =3D ffs(status) - 1;
+=09=09=09irq |=3D
+=09=09=09 (MPC52xx_IRQ_L1_SDMA << MPC52xx_IRQ_L1_OFFSET) &
+=09=09=09 MPC52xx_IRQ_L1_MASK;
+=09=09} else
+=09=09=09irq |=3D
+=09=09=09 (MPC52xx_IRQ_L1_PERP << MPC52xx_IRQ_L1_OFFSET) &
+=09=09=09 MPC52xx_IRQ_L1_MASK;
+
+=09}
+
+=09pr_debug("%s: irq=3D%x. virq=3D%dn", __func__, irq,
+=09=09 irq_linear_revmap(mpc52xx_irqhost, irq));
+
+=09return irq_linear_revmap(mpc52xx_irqhost, irq);
+}
--- a/arch/powerpc/sysdev/Makefile=092006-11-01 09:18:43.000000000 +0100
+++ b/arch/powerpc/sysdev/Makefile=092006-11-06 11:10:46.000000000 +0100
@@ -13,6 +13,7 @@ obj-$(CONFIG_FSL_SOC)=09=09+=3D fsl_soc.o
obj-$(CONFIG_PPC_TODC)=09=09+=3D todc.o
obj-$(CONFIG_TSI108_BRIDGE)=09+=3D tsi108_pci.o tsi108_dev.o
obj-$(CONFIG_QUICC_ENGINE)=09+=3D qe_lib/
+obj-$(CONFIG_PPC_MPC52xx)=09+=3D mpc52xx_pic.o
=20
ifeq ($(CONFIG_PPC_MERGE),y)
obj-$(CONFIG_PPC_I8259)=09=09+=3D i8259.o
--- a/include/asm-powerpc/mpc52xx.h=091970-01-01 01:00:00.000000000 +0100
+++ b/include/asm-powerpc/mpc52xx.h=092006-11-06 11:10:29.000000000 +0100
@@ -0,0 +1,283 @@
+/*
+ * Prototypes, etc. for the Freescale MPC52xx embedded cpu chips
+ * May need to be cleaned as the port goes on ...
+ *
+ * Copyright (C) 2004-2005 Sylvain Munaut <tnt@246tNt.com>
+ * Copyright (C) 2003 MontaVista, Software, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#ifndef __ASM_POWERPC_MPC52xx_H__
+#define __ASM_POWERPC_MPC52xx_H__
+
+#ifndef __ASSEMBLY__
+#include <asm/types.h>
+#include <asm/prom.h>
+#endif /* __ASSEMBLY__ */
+
+/* HW IRQ mapping */
+#define MPC52xx_IRQ_L1_CRIT=09(0)
+#define MPC52xx_IRQ_L1_MAIN=09(1)
+#define MPC52xx_IRQ_L1_PERP=09(2)
+#define MPC52xx_IRQ_L1_SDMA=09(3)
+
+#define MPC52xx_IRQ_L1_OFFSET (6)
+#define MPC52xx_IRQ_L1_MASK (0xc0)
+
+#define MPC52xx_IRQ_L2_OFFSET (0)
+#define MPC52xx_IRQ_L2_MASK (0x3f)
+
+#define MPC52xx_IRQ_HIGHTESTHWIRQ (0xd0)
+
+/* Interrupt controller Register set */
+struct mpc52xx_intr {
+=09u32 per_mask;=09=09/* INTR + 0x00 */
+=09u32 per_pri1;=09=09/* INTR + 0x04 */
+=09u32 per_pri2;=09=09/* INTR + 0x08 */
+=09u32 per_pri3;=09=09/* INTR + 0x0c */
+=09u32 ctrl;=09=09/* INTR + 0x10 */
+=09u32 main_mask;=09=09/* INTR + 0x14 */
+=09u32 main_pri1;=09=09/* INTR + 0x18 */
+=09u32 main_pri2;=09=09/* INTR + 0x1c */
+=09u32 reserved1;=09=09/* INTR + 0x20 */
+=09u32 enc_status;=09=09/* INTR + 0x24 */
+=09u32 crit_status;=09/* INTR + 0x28 */
+=09u32 main_status;=09/* INTR + 0x2c */
+=09u32 per_status;=09=09/* INTR + 0x30 */
+=09u32 reserved2;=09=09/* INTR + 0x34 */
+=09u32 per_error;=09=09/* INTR + 0x38 */
+};
+
+
+/* =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D */
+/* Structures mapping of some unit register set =
*/
+/* =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D */
+
+#ifndef __ASSEMBLY__
+
+/* Memory Mapping Control */
+struct mpc52xx_mmap_ctl {
+=09u32 mbar;=09=09/* MMAP_CTRL + 0x00 */
+
+=09u32 cs0_start;=09=09/* MMAP_CTRL + 0x04 */
+=09u32 cs0_stop;=09=09/* MMAP_CTRL + 0x08 */
+=09u32 cs1_start;=09=09/* MMAP_CTRL + 0x0c */
+=09u32 cs1_stop;=09=09/* MMAP_CTRL + 0x10 */
+=09u32 cs2_start;=09=09/* MMAP_CTRL + 0x14 */
+=09u32 cs2_stop;=09=09/* MMAP_CTRL + 0x18 */
+=09u32 cs3_start;=09=09/* MMAP_CTRL + 0x1c */
+=09u32 cs3_stop;=09=09/* MMAP_CTRL + 0x20 */
+=09u32 cs4_start;=09=09/* MMAP_CTRL + 0x24 */
+=09u32 cs4_stop;=09=09/* MMAP_CTRL + 0x28 */
+=09u32 cs5_start;=09=09/* MMAP_CTRL + 0x2c */
+=09u32 cs5_stop;=09=09/* MMAP_CTRL + 0x30 */
+
+=09u32 sdram0;=09=09/* MMAP_CTRL + 0x34 */
+=09u32 sdram1;=09=09/* MMAP_CTRL + 0X38 */
+
+=09u32 reserved[4];=09/* MMAP_CTRL + 0x3c .. 0x48 */
+
+=09u32 boot_start;=09=09/* MMAP_CTRL + 0x4c */
+=09u32 boot_stop;=09=09/* MMAP_CTRL + 0x50 */
+
+=09u32 ipbi_ws_ctrl;=09/* MMAP_CTRL + 0x54 */
+
+=09u32 cs6_start;=09=09/* MMAP_CTRL + 0x58 */
+=09u32 cs6_stop;=09=09/* MMAP_CTRL + 0x5c */
+=09u32 cs7_start;=09=09/* MMAP_CTRL + 0x60 */
+=09u32 cs7_stop;=09=09/* MMAP_CTRL + 0x64 */
+};
+
+/* SDRAM control */
+struct mpc52xx_sdram {
+=09u32 mode;=09=09/* SDRAM + 0x00 */
+=09u32 ctrl;=09=09/* SDRAM + 0x04 */
+=09u32 config1;=09=09/* SDRAM + 0x08 */
+=09u32 config2;=09=09/* SDRAM + 0x0c */
+};
+
+/* SDMA */
+struct mpc52xx_sdma {
+=09u32 taskBar;=09=09/* SDMA + 0x00 */
+=09u32 currentPointer;=09/* SDMA + 0x04 */
+=09u32 endPointer;=09=09/* SDMA + 0x08 */
+=09u32 variablePointer;=09/* SDMA + 0x0c */
+
+=09u8 IntVect1;=09=09/* SDMA + 0x10 */
+=09u8 IntVect2;=09=09/* SDMA + 0x11 */
+=09u16 PtdCntrl;=09=09/* SDMA + 0x12 */
+
+=09u32 IntPend;=09=09/* SDMA + 0x14 */
+=09u32 IntMask;=09=09/* SDMA + 0x18 */
+
+=09u16 tcr[16];=09=09/* SDMA + 0x1c .. 0x3a */
+
+=09u8 ipr[32];=09=09/* SDMA + 0x3c .. 0x5b */
+
+=09u32 cReqSelect;=09=09/* SDMA + 0x5c */
+=09u32 task_size0;=09=09/* SDMA + 0x60 */
+=09u32 task_size1;=09=09/* SDMA + 0x64 */
+=09u32 MDEDebug;=09=09/* SDMA + 0x68 */
+=09u32 ADSDebug;=09=09/* SDMA + 0x6c */
+=09u32 Value1;=09=09/* SDMA + 0x70 */
+=09u32 Value2;=09=09/* SDMA + 0x74 */
+=09u32 Control;=09=09/* SDMA + 0x78 */
+=09u32 Status;=09=09/* SDMA + 0x7c */
+=09u32 PTDDebug;=09=09/* SDMA + 0x80 */
+};
+
+/* GPT */
+struct mpc52xx_gpt {
+=09u32 mode;=09=09/* GPTx + 0x00 */
+=09u32 count;=09=09/* GPTx + 0x04 */
+=09u32 pwm;=09=09/* GPTx + 0x08 */
+=09u32 status;=09=09/* GPTx + 0X0c */
+};
+
+/* GPIO */
+struct mpc52xx_gpio {
+=09u32 port_config;=09/* GPIO + 0x00 */
+=09u32 simple_gpioe;=09/* GPIO + 0x04 */
+=09u32 simple_ode;=09=09/* GPIO + 0x08 */
+=09u32 simple_ddr;=09=09/* GPIO + 0x0c */
+=09u32 simple_dvo;=09=09/* GPIO + 0x10 */
+=09u32 simple_ival;=09/* GPIO + 0x14 */
+=09u8 outo_gpioe;=09=09/* GPIO + 0x18 */
+=09u8 reserved1[3];=09/* GPIO + 0x19 */
+=09u8 outo_dvo;=09=09/* GPIO + 0x1c */
+=09u8 reserved2[3];=09/* GPIO + 0x1d */
+=09u8 sint_gpioe;=09=09/* GPIO + 0x20 */
+=09u8 reserved3[3];=09/* GPIO + 0x21 */
+=09u8 sint_ode;=09=09/* GPIO + 0x24 */
+=09u8 reserved4[3];=09/* GPIO + 0x25 */
+=09u8 sint_ddr;=09=09/* GPIO + 0x28 */
+=09u8 reserved5[3];=09/* GPIO + 0x29 */
+=09u8 sint_dvo;=09=09/* GPIO + 0x2c */
+=09u8 reserved6[3];=09/* GPIO + 0x2d */
+=09u8 sint_inten;=09=09/* GPIO + 0x30 */
+=09u8 reserved7[3];=09/* GPIO + 0x31 */
+=09u16 sint_itype;=09=09/* GPIO + 0x34 */
+=09u16 reserved8;=09=09/* GPIO + 0x36 */
+=09u8 gpio_control;=09/* GPIO + 0x38 */
+=09u8 reserved9[3];=09/* GPIO + 0x39 */
+=09u8 sint_istat;=09=09/* GPIO + 0x3c */
+=09u8 sint_ival;=09=09/* GPIO + 0x3d */
+=09u8 bus_errs;=09=09/* GPIO + 0x3e */
+=09u8 reserved10;=09=09/* GPIO + 0x3f */
+};
+
+#define MPC52xx_GPIO_PSC_CONFIG_UART_WITHOUT_CD=094
+#define MPC52xx_GPIO_PSC_CONFIG_UART_WITH_CD=095
+#define MPC52xx_GPIO_PCI_DIS=09=09=09(1<<15)
+
+/* GPIO with WakeUp*/
+struct mpc52xx_gpio_wkup {
+=09u8 wkup_gpioe;=09=09/* GPIO_WKUP + 0x00 */
+=09u8 reserved1[3];=09/* GPIO_WKUP + 0x03 */
+=09u8 wkup_ode;=09=09/* GPIO_WKUP + 0x04 */
+=09u8 reserved2[3];=09/* GPIO_WKUP + 0x05 */
+=09u8 wkup_ddr;=09=09/* GPIO_WKUP + 0x08 */
+=09u8 reserved3[3];=09/* GPIO_WKUP + 0x09 */
+=09u8 wkup_dvo;=09=09/* GPIO_WKUP + 0x0C */
+=09u8 reserved4[3];=09/* GPIO_WKUP + 0x0D */
+=09u8 wkup_inten;=09=09/* GPIO_WKUP + 0x10 */
+=09u8 reserved5[3];=09/* GPIO_WKUP + 0x11 */
+=09u8 wkup_iinten;=09=09/* GPIO_WKUP + 0x14 */
+=09u8 reserved6[3];=09/* GPIO_WKUP + 0x15 */
+=09u16 wkup_itype;=09=09/* GPIO_WKUP + 0x18 */
+=09u8 reserved7[2];=09/* GPIO_WKUP + 0x1A */
+=09u8 wkup_maste;=09=09/* GPIO_WKUP + 0x1C */
+=09u8 reserved8[3];=09/* GPIO_WKUP + 0x1D */
+=09u8 wkup_ival;=09=09/* GPIO_WKUP + 0x20 */
+=09u8 reserved9[3];=09/* GPIO_WKUP + 0x21 */
+=09u8 wkup_istat;=09=09/* GPIO_WKUP + 0x24 */
+=09u8 reserved10[3];=09/* GPIO_WKUP + 0x25 */
+};
+
+/* XLB Bus control */
+struct mpc52xx_xlb {
+=09u8 reserved[0x40];
+=09u32 config;=09=09/* XLB + 0x40 */
+=09u32 version;=09=09/* XLB + 0x44 */
+=09u32 status;=09=09/* XLB + 0x48 */
+=09u32 int_enable;=09=09/* XLB + 0x4c */
+=09u32 addr_capture;=09/* XLB + 0x50 */
+=09u32 bus_sig_capture;=09/* XLB + 0x54 */
+=09u32 addr_timeout;=09/* XLB + 0x58 */
+=09u32 data_timeout;=09/* XLB + 0x5c */
+=09u32 bus_act_timeout;=09/* XLB + 0x60 */
+=09u32 master_pri_enable;=09/* XLB + 0x64 */
+=09u32 master_priority;=09/* XLB + 0x68 */
+=09u32 base_address;=09/* XLB + 0x6c */
+=09u32 snoop_window;=09/* XLB + 0x70 */
+};
+
+#define MPC52xx_XLB_CFG_PLDIS=09=09(1 << 31)
+#define MPC52xx_XLB_CFG_SNOOP=09=09(1 << 15)
+
+/* Clock Distribution control */
+struct mpc52xx_cdm {
+=09u32 jtag_id;=09=09/* CDM + 0x00 reg0 read only */
+=09u32 rstcfg;=09=09/* CDM + 0x04 reg1 read only */
+=09u32 breadcrumb;=09=09/* CDM + 0x08 reg2 */
+
+=09u8 mem_clk_sel;=09=09/* CDM + 0x0c reg3 byte0 */
+=09u8 xlb_clk_sel;=09=09/* CDM + 0x0d reg3 byte1 read only */
+=09u8 ipb_clk_sel;=09=09/* CDM + 0x0e reg3 byte2 */
+=09u8 pci_clk_sel;=09=09/* CDM + 0x0f reg3 byte3 */
+
+=09u8 ext_48mhz_en;=09/* CDM + 0x10 reg4 byte0 */
+=09u8 fd_enable;=09=09/* CDM + 0x11 reg4 byte1 */
+=09u16 fd_counters;=09/* CDM + 0x12 reg4 byte2,3 */
+
+=09u32 clk_enables;=09/* CDM + 0x14 reg5 */
+
+=09u8 osc_disable;=09=09/* CDM + 0x18 reg6 byte0 */
+=09u8 reserved0[3];=09/* CDM + 0x19 reg6 byte1,2,3 */
+
+=09u8 ccs_sleep_enable;=09/* CDM + 0x1c reg7 byte0 */
+=09u8 osc_sleep_enable;=09/* CDM + 0x1d reg7 byte1 */
+=09u8 reserved1;=09=09/* CDM + 0x1e reg7 byte2 */
+=09u8 ccs_qreq_test;=09/* CDM + 0x1f reg7 byte3 */
+
+=09u8 soft_reset;=09=09/* CDM + 0x20 u8 byte0 */
+=09u8 no_ckstp;=09=09/* CDM + 0x21 u8 byte0 */
+=09u8 reserved2[2];=09/* CDM + 0x22 u8 byte1,2,3 */
+
+=09u8 pll_lock;=09=09/* CDM + 0x24 reg9 byte0 */
+=09u8 pll_looselock;=09/* CDM + 0x25 reg9 byte1 */
+=09u8 pll_sm_lockwin;=09/* CDM + 0x26 reg9 byte2 */
+=09u8 reserved3;=09=09/* CDM + 0x27 reg9 byte3 */
+
+=09u16 reserved4;=09=09/* CDM + 0x28 reg10 byte0,1 */
+=09u16 mclken_div_psc1;=09/* CDM + 0x2a reg10 byte2,3 */
+
+=09u16 reserved5;=09=09/* CDM + 0x2c reg11 byte0,1 */
+=09u16 mclken_div_psc2;=09/* CDM + 0x2e reg11 byte2,3 */
+
+=09u16 reserved6;=09=09/* CDM + 0x30 reg12 byte0,1 */
+=09u16 mclken_div_psc3;=09/* CDM + 0x32 reg12 byte2,3 */
+
+=09u16 reserved7;=09=09/* CDM + 0x34 reg13 byte0,1 */
+=09u16 mclken_div_psc6;=09/* CDM + 0x36 reg13 byte2,3 */
+};
+
+#endif /* __ASSEMBLY__ */
+
+
+/* =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
*/
+/* Prototypes for MPC52xx sysdev =
*/
+/* =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
*/
+
+#ifndef __ASSEMBLY__
+
+extern void mpc52xx_init_irq(void);
+extern unsigned int mpc52xx_get_irq(void);
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __ASM_POWERPC_MPC52xx_H__ */
+
^ permalink raw reply
* Clock Modification of MPC885 for USB Host Functionality
From: Prakash Ramaraju @ 2006-11-06 10:29 UTC (permalink / raw)
To: linuxppc-embedded
[-- Attachment #1: Type: text/plain, Size: 1057 bytes --]
Greetings
Currently I have a MPC885 based board running at 50MHz. I want USB host
working at full speed with internal clock. Assuming I need to change the
General System Clock Frequency (GCLK2) to 48MHz, I got this calculation with
input frequency of 10MHz from an u-boot script.
pdf mfi mfn mfd s dbrmo dpref dpgdck jdbck gclk2 exact?
--- --- --- --- - ----- ----- ------ ----- ----- ------
0 9 3 4 1 0 10000000 192000000 96000000 48000000 YES
0 9 6 9 1 0 10000000 192000000 96000000 48000000 YES
0 9 9 14 1 0 10000000 192000000 96000000 48000000 YES
0 9 12 19 1 0 10000000 192000000 96000000 48000000 YES
I modified CFG_PLPRCR (to 19194000) in u-boot config file to match this. But
I'm getting only 45MHz output clock (not exactly 48MHz which is needed for
USB to work)
If anyone can shed some info making the USB work on MPC885 with internal
clock or changing the clock freq to exact 48MHz, it will be helpful.
Thanks
--
With best regards,
Prakash
[-- Attachment #2: Type: text/html, Size: 1606 bytes --]
^ permalink raw reply
* Re: Linux Kernel 2.6 on Artesyn Katana Board (3750) with IBM 750FX PP C
From: Wolfgang Denk @ 2006-11-06 10:31 UTC (permalink / raw)
To: Goel, Mudit (Mudit); +Cc: 'linuxppc-embedded@ozlabs.org'
In-Reply-To: <3BE48DD0EC7D3948BC183931D9150C210BBB0BAB@ii0015exch001u.iprc.lucent.com>
In message <3BE48DD0EC7D3948BC183931D9150C210BBB0BAB@ii0015exch001u.iprc.lucent.com> you wrote:
> We are trying to upgrade the kernel to 2.6. The kernel upgrade is success
> on one card with ppc boot version 1.2
> with release date of July 2004.
>
> But all other cards which have different dates but same boot version the
> kernel upgrade is not successful.
> Here is the boot output
> ----------------------------
> P1(2.01)=>go 0x08010000
> ## Starting application at 0x08010000 ...
> loaded at: 08010000 081EA320
> relocated to: 00800000 009DA320
> zimage at: 00805909 009D78BD
> avail ram: 00700000 00B00000
> max kernel: 00600000
This is NOT the correct way to boot Linux using U-Boot. You should
create a U-Boot image file (using the mkimage tool, resp. running
"make uImage"), and boot this using the "bootm" command as
documented in the README and the manual.
Please read the documentation.
Best regards,
Wolfgang Denk
--
Software Engineering: Embedded and Realtime Systems, Embedded Linux
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de
I'm what passes for a Unix guru in my office. This is a frightening
concept. - Lee Ann Goldstein, in <3k55ba$c43@butch.lmsc.lockheed.com>
^ permalink raw reply
* [PATCH] powerpc: Add of_platform support for OHCI/Bigendian HC
From: Nicolas DET @ 2006-11-06 10:35 UTC (permalink / raw)
To: linuxppc-dev; +Cc: akpm@osdl.org, linuxppc-embedded
This patch use of_platform device to probe and install OHCI big endian HC.
PS: I did not success to properly inline the file using thrunderbird.
Signed-off-by: Nicolas DET <nd@bplan-gmbh.de>=20
---
--- a/drivers/usb/host/ohci-ppc-of.c=091970-01-01 01:00:00.000000000 +0100
+++ b/drivers/usb/host/ohci-ppc-of.c=092006-11-06 11:10:29.000000000 +0100
@@ -0,0 +1,283 @@
+/*
+ * OHCI HCD (Host Controller Driver) for USB.
+ *
+ * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
+ * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net=
>
+ * (C) Copyright 2002 Hewlett-Packard Company
+ * (C) Copyright 2003-2005 MontaVista Software Inc.
+ *=20
+ * Probe and init OHCI Big endian HC from OpenFirmware device tree
+ * Tested on Efika 5k2
+ *
+ * Modified by Dale Farnsworth <dale@farnsworth.org> from ohci-sa1111.c
+ *
+ * This file is licenced under the GPL.
+ */
+
+#include <linux/signal.h>
+
+#include <asm/of_device.h>
+#include <asm/prom.h>
+
+/* configure so an HC device and id are always provided */
+/* always called with process context; sleeping is OK */
+
+/*
+ * usb_hcd_ppc_of_probe - initialize On-Chip HCDs
+ * Context: !in_interrupt()
+ *
+ * Allocates basic resources for this USB host controller.
+ *
+ * Store this function in the HCD's struct pci_driver as probe().
+ */
+static int usb_hcd_ppc_of_probe(const struct hc_driver *driver,
+=09=09=09 struct of_device *dev, int is_bigendian)
+{
+=09int retval;
+=09struct usb_hcd *hcd;
+=09struct ohci_hcd=09*ohci;
+=09struct resource res;
+=09int irq;
+=09int ret;
+
+=09pr_debug("initializing PPC-OF USB Controllern");
+
+=09if ((ret =3D of_address_to_resource(dev->node, 0, &res)) !=3D 0)
+=09=09return ret;
+
+=09hcd =3D usb_create_hcd(driver, &dev->dev, "PPC-OF USB");
+=09if (!hcd)
+=09=09return -ENOMEM;
+
+=09hcd->rsrc_start =3D res.start;
+=09hcd->rsrc_len =3D res.end - res.start + 1;
+
+=09if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) {
+=09=09pr_debug(__FILE__ ": request_mem_region failedn");
+=09=09retval =3D -EBUSY;
+=09=09goto err1;
+=09}
+
+=09irq =3D irq_of_parse_and_map(dev->node, 0);
+=09if (irq =3D=3D NO_IRQ) {
+=09=09retval =3D -EBUSY;
+=09=09goto err2;
+=09}
+
+=09hcd->regs =3D ioremap(hcd->rsrc_start, hcd->rsrc_len);
+=09if (!hcd->regs) {
+=09=09pr_debug(__FILE__ ": ioremap failedn");
+=09=09retval =3D -ENOMEM;
+=09=09goto err2;
+=09}
+
+=09ohci =3D hcd_to_ohci(hcd);
+=09if (is_bigendian)
+=09=09ohci->flags |=3D OHCI_BIG_ENDIAN;
+
+=09ohci_hcd_init(ohci);
+
+=09retval =3D usb_add_hcd(hcd, irq, 0);
+=09if (retval =3D=3D 0)
+=09=09return retval;
+
+=09pr_debug("Removing PPC-OF USB Controllern");
+
+=09iounmap(hcd->regs);
+ err2:
+=09release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
+ err1:
+ =09usb_put_hcd(hcd);
+=09return retval;
+}
+
+
+/* may be called without controller electrically present */
+/* may be called with controller, bus, and devices active */
+
+/*
+ * usb_hcd_ppc_of_remove - shutdown processing for On-Chip HCDs
+ * @pdev: USB Host Controller being removed
+ * Context: !in_interrupt()
+ *
+ * Reverses the effect of usb_hcd_ppc_of_probe().
+ * It is always called from a thread
+ * context, normally "rmmod", "apmd", or something similar.
+ *
+ */
+static void usb_hcd_ppc_of_remove(struct usb_hcd *hcd,
+=09=09struct of_device *op)
+{
+=09usb_remove_hcd(hcd);
+
+=09pr_debug("stopping PPC-OF USB Controllern");
+
+=09iounmap(hcd->regs);
+=09release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
+=09usb_put_hcd(hcd);
+}
+
+static int __devinit
+ohci_ppc_of_start(struct usb_hcd *hcd)
+{
+=09struct ohci_hcd=09*ohci =3D hcd_to_ohci(hcd);
+=09int=09=09ret;
+
+=09if ((ret =3D ohci_init(ohci)) < 0)
+=09=09return ret;
+
+=09if ((ret =3D ohci_run(ohci)) < 0) {
+=09=09err("can't start %s", ohci_to_hcd(ohci)->self.bus_name);
+=09=09ohci_stop(hcd);
+=09=09return ret;
+=09}
+
+=09return 0;
+}
+
+static const struct hc_driver ohci_ppc_of_hc_driver =3D {
+=09.description =3D=09=09hcd_name,
+=09.hcd_priv_size =3D=09sizeof(struct ohci_hcd),
+
+=09/*
+=09 * generic hardware linkage
+=09 */
+=09.irq =3D=09=09=09ohci_irq,
+=09.flags =3D=09=09HCD_USB11 | HCD_MEMORY,
+
+=09/*
+=09 * basic lifecycle operations
+=09 */
+=09.start =3D=09=09ohci_ppc_of_start,
+=09.stop =3D=09=09=09ohci_stop,
+=09.shutdown =3D =09=09ohci_shutdown,
+
+=09/*
+=09 * managing i/o requests and associated device resources
+=09 */
+=09.urb_enqueue =3D=09=09ohci_urb_enqueue,
+=09.urb_dequeue =3D=09=09ohci_urb_dequeue,
+=09.endpoint_disable =3D=09ohci_endpoint_disable,
+
+=09/*
+=09 * scheduling support
+=09 */
+=09.get_frame_number =3D=09ohci_get_frame,
+
+=09/*
+=09 * root hub support
+=09 */
+=09.hub_status_data =3D=09ohci_hub_status_data,
+=09.hub_control =3D=09=09ohci_hub_control,
+=09.hub_irq_enable =3D=09ohci_rhsc_enable,
+#ifdef=09CONFIG_PM
+=09.bus_suspend =3D=09=09ohci_bus_suspend,
+=09.bus_resume =3D=09=09ohci_bus_resume,
+#endif
+=09.start_port_reset =3D=09ohci_start_port_reset,
+};
+
+
+
+static int ohci_hcd_ppc_of_drv_remove(struct of_device *op)
+{
+=09struct usb_hcd *hcd =3D dev_get_drvdata(&op->dev);
+=09dev_set_drvdata(&op->dev, NULL);
+
+=09usb_hcd_ppc_of_remove(hcd, op);
+=09return 0;
+}
+
+static int ohci_hcd_ppc_of_drv_shutdown(struct of_device *op)
+{
+=09struct usb_hcd *hcd =3D dev_get_drvdata(&op->dev);
+
+ if (hcd->driver->shutdown)
+ hcd->driver->shutdown(hcd);
+
+=09return 0;
+}
+
+/*
+ *
+*/
+
+static struct of_device_id ohci_hcd_ppc_of_match[] =3D {
+#ifdef CONFIG_USB_OHCI_HCD_PPC_OF_BE
+=09{
+=09=09.name =3D "usb",
+=09=09.compatible =3D "ohci-bigendian",
+=09},
+=09{
+=09=09.name =3D "usb",
+=09=09.compatible =3D "ohci-be",
+=09},
+#endif
+#ifdef CONFIG_USB_OHCI_HCD_PPC_OF_LE
+=09{
+=09=09.name =3D "usb",
+=09=09.compatible =3D "ohci-littledian",
+=09},
+=09{
+=09=09.name =3D "usb",
+=09=09.compatible =3D "ohci-le",
+=09},
+#endif
+=09{},
+};
+
+static int __devinit
+ohci_hcd_ppc_of_drv_probe(struct of_device *op, const struct of_device_id =
*match)
+{
+=09struct device_node *dev;
+=09int ret;
+=09int is_bigendian;
+
+=09if (usb_disabled())
+=09=09return -ENODEV;
+
+=09dev =3D op->node;
+=09is_bigendian =3D 0;
+
+=09if ( device_is_compatible(dev, "ohci-bigendian") )
+=09=09is_bigendian =3D 1;
+
+=09if ( device_is_compatible(dev, "ohci-be") )
+=09=09is_bigendian =3D 1;=09
+
+=09ret =3D usb_hcd_ppc_of_probe(&ohci_ppc_of_hc_driver, op, is_bigendian);
+=09return ret;
+}
+
+static struct of_platform_driver ohci_hcd_ppc_of_driver =3D {
+=09.name=09=3D "ppc-of-ohci",
+=09.match_table=09=3D ohci_hcd_ppc_of_match,
+=09.probe=09=09=3D ohci_hcd_ppc_of_drv_probe,
+=09.remove=09=09=3D ohci_hcd_ppc_of_drv_remove,
+=09.shutdown =09=3D ohci_hcd_ppc_of_drv_shutdown,
+#ifdef=09CONFIG_PM
+=09/*.suspend=09=3D ohci_hcd_ppc_soc_drv_suspend,*/
+=09/*.resume=09=3D ohci_hcd_ppc_soc_drv_resume,*/
+#endif
+=09.driver=09=09=3D {
+=09=09.name=09=3D "ppc-of-ohci",
+=09=09.owner=09=3D THIS_MODULE,
+=09},
+};
+
+static int __init ohci_hcd_ppc_of_init(void)
+{
+=09pr_debug(DRIVER_INFO " (PPC OF)n");
+=09pr_debug("block sizes: ed %d td %dn", sizeof(struct ed),
+=09=09=09=09=09=09=09sizeof(struct td));
+=09
+=09return of_register_driver(&ohci_hcd_ppc_of_driver); =20
+}
+
+static void __exit ohci_hcd_ppc_of_cleanup(void)
+{
+=09of_unregister_driver(&ohci_hcd_ppc_of_driver);
+}
+
+module_init(ohci_hcd_ppc_of_init);
+module_exit(ohci_hcd_ppc_of_cleanup);
--- a/drivers/usb/host/Kconfig=092006-11-01 09:18:56.000000000 +0100
+++ b/drivers/usb/host/Kconfig=092006-11-06 11:10:29.000000000 +0100
@@ -106,6 +106,25 @@ config USB_OHCI_HCD_PPC_SOC
=09 Enables support for the USB controller on the MPC52xx or
=09 STB03xxx processor chip. If unsure, say Y.
=20
+config USB_OHCI_HCD_PPC_OF
+=09bool "OHCI support for PPC USB controller for OpenFirmware platform"
+=09depends on USB_OHCI_HCD && PPC_OF
+=09default y
+=09---help---
+=09 Enables support for the USB controller PowerPC OpenFirmware platform
+
+config USB_OHCI_HCD_PPC_OF_BE
+=09bool "Support big endian HC"
+=09depends on USB_OHCI_HCD_PPC_OF
+=09default y
+=09select USB_OHCI_BIG_ENDIAN
+
+config USB_OHCI_HCD_PPC_OF_LE
+=09bool "Support little endian HC"
+=09depends on USB_OHCI_HCD_PPC_OF
+=09default n
+=09select USB_OHCI_LITTLE_ENDIAN
+
config USB_OHCI_HCD_PCI
=09bool "OHCI support for PCI-bus USB controllers"
=09depends on USB_OHCI_HCD && PCI && (STB03xxx || PPC_MPC52xx)
--- a/drivers/usb/host/ohci-hcd.c=092006-11-01 09:18:56.000000000 +0100
+++ b/drivers/usb/host/ohci-hcd.c=092006-11-06 11:10:29.000000000 +0100
@@ -930,6 +930,10 @@ MODULE_LICENSE ("GPL");
#include "ohci-ppc-soc.c"
#endif
=20
+#ifdef CONFIG_USB_OHCI_HCD_PPC_OF
+#include "ohci-ppc-of.c"
+#endif
+
#if defined(CONFIG_ARCH_AT91RM9200) || defined(CONFIG_ARCH_AT91SAM9261)
#include "ohci-at91.c"
#endif
@@ -950,6 +954,8 @@ MODULE_LICENSE ("GPL");
|| defined (CONFIG_ARCH_AT91RM9200)=20
|| defined (CONFIG_ARCH_AT91SAM9261)=20
|| defined (CONFIG_ARCH_PNX4008)=20
+ || defined (CONFIG_USB_OHCI_HCD_PPC_OF_LE)=20
+ || defined (CONFIG_USB_OHCI_HCD_PPC_OF_BE)=20
=09)
#error "missing bus glue for ohci-hcd"
#endif
^ permalink raw reply
* Re: [PATCH 2.6.19 1/4] ehca: assure 4k alignment for firmware control block in 64k page mode
From: Hoang-Nam Nguyen @ 2006-11-06 10:39 UTC (permalink / raw)
To: rolandd
Cc: linuxppc-dev, Christoph Raisch, Arnd Bergmann, linux-kernel,
openib-general
In-Reply-To: <200611060045.59074.arnd@arndb.de>
Hi Roland!
> Arnd wrote:
> This seems broken. You have a constructor for newly allocated objects,
but
> there is no destructor and it seems that objects passed to
> ehca_free_fw_ctrlblock are not guaranteed to be initialized either.
> I'd simply move the memset into the alloc function and get rid of the
> constructor here.
As Arnd stated I need to fix this ctor issue. Do you prefer me to resend
all patches in proper format (non-mangled inline) or just this one bug fix?
Thanks!
Nam
^ permalink raw reply
* RE: Linux Kernel 2.6 on Artesyn Katana Board (3750) with IBM 750F X PP C
From: Goel, Mudit (Mudit) @ 2006-11-06 10:46 UTC (permalink / raw)
To: 'wd@denx.de', Goel, Mudit (Mudit)
Cc: 'linuxppc-embedded@ozlabs.org'
Wolfgang,
After making an uIamge and using bootm here is the o/p. I have tried using
DHCP/ RARP options also
but I dont see any requests coming onto the host machine where the server
is runnig. Is there something
incorrect in the configuration that I have.
In the same configuration if I use Kernel 2.2 Everything works fine.
Thanks
Mudit
--------------
P1(2.01)=>bootm
## Booting image at 08000000 ...
Image Name: Linux-2.6.10_mvlcge401-katana
Image Type: PowerPC Linux Kernel Image (gzip compressed)
Data Size: 1908661 Bytes = 1.8 MB
Load Address: 00000000
Entry Point: 00000000
Verifying Checksum ... OK
Uncompressing Kernel Image ... OK
Total memory = 256MB; using 512kB for hash table (at c0480000)
Linux version 2.6.10_mvlcge401-katana (root@hdrlin03) (gcc version 3.4.3
(MontaV
ista 3.4.3-25.0.41.0501420 2005-09-07)) #32 Mon Nov 6 16:03:17 IST 2006
RMON: rmon_first_init
Artesyn Communication Products, LLC - Katana(TM)
Real-Time Preemption Support (c) Ingo Molnar
Built 1 zonelists
Kernel command line: root=/dev/nfs rw nfsroot=172.31.4.10:/app2/cpsbeplg
nfsaddr
s=172.31.4.50:172.31.4.10:172.31.4.254:255.255.255.0:cpsbcicc-50:eth0:off
PID hash table entries: 2048 (order: 11, 32768 bytes)
time_init: decrementer frequency = 33.333333 MHz
Console: colour dummy device 80x25
Dentry cache hash table entries: 65536 (order: 6, 262144 bytes)
Inode-cache hash table entries: 32768 (order: 5, 131072 bytes)
Memory: 254576k available (2856k kernel code, 1468k data, 152k init, 0k
highmem)
RMON - kernel resource monitoring
Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
spawn_desched_task(00000000)
desched cpu_callback 3/00000000
ksoftirqd started up.
softirq RT prio: 24.
desched cpu_callback 2/00000000
desched thread 0 started up.
NET: Registered protocol family 16
PCI: Probing PCI hardware
VFS: Disk quotas dquot_6.5.1
Dquot-cache hash table entries: 1024 (order 0, 4096 bytes)
JFFS2 version 2.2. (NAND) (C) 2001-2003 Red Hat, Inc.
SGI XFS with ACLs, no debug enabled
SGI XFS Quota Management subsystem
Initializing Cryptographic API
Fast Real Time Domain (c) 2005 Montavista Software, Inc.
FRD major device number is 254
Generic RTC Driver v1.07
Serial: MPSC driver $Revision: 1.00 $
ttyMM0 at MMIO 0xd10bc000 (irq = 36) is a MPSC
ttyMM1 at MMIO 0xd10c2000 (irq = 38) is a MPSC
io scheduler noop registered
io scheduler anticipatory registered
io scheduler deadline registered
io scheduler cfq registered
RAMDISK driver initialized: 16 RAM disks of 8192K size 1024 blocksize
loop: loaded (max 8 devices)
MV-643xx 10/100/1000 Ethernet Driver
eth0: port 2 with MAC address 00:80:f9:64:a8:c0
eth0: RX NAPI Enabled
i2c /dev entries driver
IPMB I2C Client 0.07 05 Nov 2004 - Loaded on address 0x08 (0x10)
mv64xxx: i2c slave interface enabled
Local Slave Address: 80
Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2
ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx
elevator: using anticipatory as default io scheduler
physmap flash device: 4000000 at e0000000
phys_mapped_flash: Found 2 x16 devices at 0x0 in 32-bit bank
Intel/Sharp Extended Query Table at 0x0031
Using buffer write method
cfi_cmdset_0001: Erase suspend on write enabled
cmdlinepart partition parsing not available
RedBoot partition parsing not available
Using physmap partition definition
Creating 6 MTD partitions on "phys_mapped_flash":
0x00000000-0x00100000 : "Monitor"
0x00100000-0x00300000 : "Primary Kernel"
0x00300000-0x02080000 : "Primary Filesystem"
0x02080000-0x02280000 : "Secondary Kernel"
0x02280000-0x04000000 : "Secondary Filesystem"
0x00100000-0x04000000 : "User FLASH"
mice: PS/2 mouse device common for all mice
NET: Registered protocol family 2
IP: routing cache hash table of 256 buckets, 14Kbytes
TCP: Hash tables configured (established 2048 bind 2340)
NET: Registered protocol family 1
NET: Registered protocol family 17
IP-Config: Complete:
device=eth0, addr=172.31.4.50, mask=255.255.255.0, gw=172.31.4.254,
host=cpsbcicc-50, domain=, nis-domain=(none),
bootserver=172.31.4.10, rootserver=172.31.4.10, rootpath=
Looking up port of RPC 100003/2 on 172.31.4.10
portmap: server 172.31.4.10 not responding, timed out
Root-NFS: Unable to get nfsd port number from server, using default
Looking up port of RPC 100005/1 on 172.31.4.10
portmap: server 172.31.4.10 not responding, timed out
Root-NFS: Unable to get mountd port number from server, using default
--------------
-----Original Message-----
From: wd@denx.de [mailto:wd@denx.de]
Sent: Monday, November 06, 2006 4:02 PM
To: Goel, Mudit (Mudit)
Cc: 'linuxppc-embedded@ozlabs.org'
Subject: Re: Linux Kernel 2.6 on Artesyn Katana Board (3750) with IBM
750FX PP C
In message
<3BE48DD0EC7D3948BC183931D9150C210BBB0BAB@ii0015exch001u.iprc.lucent.com>
you wrote:
> We are trying to upgrade the kernel to 2.6. The kernel upgrade is
success
> on one card with ppc boot version 1.2
> with release date of July 2004.
>
> But all other cards which have different dates but same boot version the
> kernel upgrade is not successful.
> Here is the boot output
> ----------------------------
> P1(2.01)=>go 0x08010000
> ## Starting application at 0x08010000 ...
> loaded at: 08010000 081EA320
> relocated to: 00800000 009DA320
> zimage at: 00805909 009D78BD
> avail ram: 00700000 00B00000
> max kernel: 00600000
This is NOT the correct way to boot Linux using U-Boot. You should
create a U-Boot image file (using the mkimage tool, resp. running
"make uImage"), and boot this using the "bootm" command as
documented in the README and the manual.
Please read the documentation.
Best regards,
Wolfgang Denk
--
Software Engineering: Embedded and Realtime Systems, Embedded Linux
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de
I'm what passes for a Unix guru in my office. This is a frightening
concept. - Lee Ann Goldstein, in <3k55ba$c43@butch.lmsc.lockheed.com>
^ permalink raw reply
* [PATCH] powerpc: Add of_platform support for OHCI/Bigendian HC
From: Nicolas DET @ 2006-11-06 11:01 UTC (permalink / raw)
To: linuxppc-dev; +Cc: linuxppc-embedded
[-- Attachment #1: Type: text/html, Size: 9868 bytes --]
[-- Attachment #2: Type: text/plain, Size: 8793 bytes --]
This patch use of_platform device to probe and install OHCI big endian HC.
PS: I did not success to properly inline the file using thrunderbird.
Signed-off-by: Nicolas DET <nd@bplan-gmbh.de>
---
--- a/drivers/usb/host/ohci-ppc-of.c 1970-01-01 01:00:00.000000000 +0100
+++ b/drivers/usb/host/ohci-ppc-of.c 2006-11-06 11:10:29.000000000 +0100
@@ -0,0 +1,283 @@
+/*
+ * OHCI HCD (Host Controller Driver) for USB.
+ *
+ * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
+ * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
+ * (C) Copyright 2002 Hewlett-Packard Company
+ * (C) Copyright 2003-2005 MontaVista Software Inc.
+ *
+ * Probe and init OHCI Big endian HC from OpenFirmware device tree
+ * Tested on Efika 5k2
+ *
+ * Modified by Dale Farnsworth <dale@farnsworth.org> from ohci-sa1111.c
+ *
+ * This file is licenced under the GPL.
+ */
+
+#include <linux/signal.h>
+
+#include <asm/of_device.h>
+#include <asm/prom.h>
+
+/* configure so an HC device and id are always provided */
+/* always called with process context; sleeping is OK */
+
+/*
+ * usb_hcd_ppc_of_probe - initialize On-Chip HCDs
+ * Context: !in_interrupt()
+ *
+ * Allocates basic resources for this USB host controller.
+ *
+ * Store this function in the HCD's struct pci_driver as probe().
+ */
+static int usb_hcd_ppc_of_probe(const struct hc_driver *driver,
+ struct of_device *dev, int is_bigendian)
+{
+ int retval;
+ struct usb_hcd *hcd;
+ struct ohci_hcd *ohci;
+ struct resource res;
+ int irq;
+ int ret;
+
+ pr_debug("initializing PPC-OF USB Controller\n");
+
+ if ((ret = of_address_to_resource(dev->node, 0, &res)) != 0)
+ return ret;
+
+ hcd = usb_create_hcd(driver, &dev->dev, "PPC-OF USB");
+ if (!hcd)
+ return -ENOMEM;
+
+ hcd->rsrc_start = res.start;
+ hcd->rsrc_len = res.end - res.start + 1;
+
+ if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) {
+ pr_debug(__FILE__ ": request_mem_region failed\n");
+ retval = -EBUSY;
+ goto err1;
+ }
+
+ irq = irq_of_parse_and_map(dev->node, 0);
+ if (irq == NO_IRQ) {
+ retval = -EBUSY;
+ goto err2;
+ }
+
+ hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len);
+ if (!hcd->regs) {
+ pr_debug(__FILE__ ": ioremap failed\n");
+ retval = -ENOMEM;
+ goto err2;
+ }
+
+ ohci = hcd_to_ohci(hcd);
+ if (is_bigendian)
+ ohci->flags |= OHCI_BIG_ENDIAN;
+
+ ohci_hcd_init(ohci);
+
+ retval = usb_add_hcd(hcd, irq, 0);
+ if (retval == 0)
+ return retval;
+
+ pr_debug("Removing PPC-OF USB Controller\n");
+
+ iounmap(hcd->regs);
+ err2:
+ release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
+ err1:
+ usb_put_hcd(hcd);
+ return retval;
+}
+
+
+/* may be called without controller electrically present */
+/* may be called with controller, bus, and devices active */
+
+/*
+ * usb_hcd_ppc_of_remove - shutdown processing for On-Chip HCDs
+ * @pdev: USB Host Controller being removed
+ * Context: !in_interrupt()
+ *
+ * Reverses the effect of usb_hcd_ppc_of_probe().
+ * It is always called from a thread
+ * context, normally "rmmod", "apmd", or something similar.
+ *
+ */
+static void usb_hcd_ppc_of_remove(struct usb_hcd *hcd,
+ struct of_device *op)
+{
+ usb_remove_hcd(hcd);
+
+ pr_debug("stopping PPC-OF USB Controller\n");
+
+ iounmap(hcd->regs);
+ release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
+ usb_put_hcd(hcd);
+}
+
+static int __devinit
+ohci_ppc_of_start(struct usb_hcd *hcd)
+{
+ struct ohci_hcd *ohci = hcd_to_ohci(hcd);
+ int ret;
+
+ if ((ret = ohci_init(ohci)) < 0)
+ return ret;
+
+ if ((ret = ohci_run(ohci)) < 0) {
+ err("can't start %s", ohci_to_hcd(ohci)->self.bus_name);
+ ohci_stop(hcd);
+ return ret;
+ }
+
+ return 0;
+}
+
+static const struct hc_driver ohci_ppc_of_hc_driver = {
+ .description = hcd_name,
+ .hcd_priv_size = sizeof(struct ohci_hcd),
+
+ /*
+ * generic hardware linkage
+ */
+ .irq = ohci_irq,
+ .flags = HCD_USB11 | HCD_MEMORY,
+
+ /*
+ * basic lifecycle operations
+ */
+ .start = ohci_ppc_of_start,
+ .stop = ohci_stop,
+ .shutdown = ohci_shutdown,
+
+ /*
+ * managing i/o requests and associated device resources
+ */
+ .urb_enqueue = ohci_urb_enqueue,
+ .urb_dequeue = ohci_urb_dequeue,
+ .endpoint_disable = ohci_endpoint_disable,
+
+ /*
+ * scheduling support
+ */
+ .get_frame_number = ohci_get_frame,
+
+ /*
+ * root hub support
+ */
+ .hub_status_data = ohci_hub_status_data,
+ .hub_control = ohci_hub_control,
+ .hub_irq_enable = ohci_rhsc_enable,
+#ifdef CONFIG_PM
+ .bus_suspend = ohci_bus_suspend,
+ .bus_resume = ohci_bus_resume,
+#endif
+ .start_port_reset = ohci_start_port_reset,
+};
+
+
+
+static int ohci_hcd_ppc_of_drv_remove(struct of_device *op)
+{
+ struct usb_hcd *hcd = dev_get_drvdata(&op->dev);
+ dev_set_drvdata(&op->dev, NULL);
+
+ usb_hcd_ppc_of_remove(hcd, op);
+ return 0;
+}
+
+static int ohci_hcd_ppc_of_drv_shutdown(struct of_device *op)
+{
+ struct usb_hcd *hcd = dev_get_drvdata(&op->dev);
+
+ if (hcd->driver->shutdown)
+ hcd->driver->shutdown(hcd);
+
+ return 0;
+}
+
+/*
+ *
+*/
+
+static struct of_device_id ohci_hcd_ppc_of_match[] = {
+#ifdef CONFIG_USB_OHCI_HCD_PPC_OF_BE
+ {
+ .name = "usb",
+ .compatible = "ohci-bigendian",
+ },
+ {
+ .name = "usb",
+ .compatible = "ohci-be",
+ },
+#endif
+#ifdef CONFIG_USB_OHCI_HCD_PPC_OF_LE
+ {
+ .name = "usb",
+ .compatible = "ohci-littledian",
+ },
+ {
+ .name = "usb",
+ .compatible = "ohci-le",
+ },
+#endif
+ {},
+};
+
+static int __devinit
+ohci_hcd_ppc_of_drv_probe(struct of_device *op, const struct of_device_id *match)
+{
+ struct device_node *dev;
+ int ret;
+ int is_bigendian;
+
+ if (usb_disabled())
+ return -ENODEV;
+
+ dev = op->node;
+ is_bigendian = 0;
+
+ if ( device_is_compatible(dev, "ohci-bigendian") )
+ is_bigendian = 1;
+
+ if ( device_is_compatible(dev, "ohci-be") )
+ is_bigendian = 1;
+
+ ret = usb_hcd_ppc_of_probe(&ohci_ppc_of_hc_driver, op, is_bigendian);
+ return ret;
+}
+
+static struct of_platform_driver ohci_hcd_ppc_of_driver = {
+ .name = "ppc-of-ohci",
+ .match_table = ohci_hcd_ppc_of_match,
+ .probe = ohci_hcd_ppc_of_drv_probe,
+ .remove = ohci_hcd_ppc_of_drv_remove,
+ .shutdown = ohci_hcd_ppc_of_drv_shutdown,
+#ifdef CONFIG_PM
+ /*.suspend = ohci_hcd_ppc_soc_drv_suspend,*/
+ /*.resume = ohci_hcd_ppc_soc_drv_resume,*/
+#endif
+ .driver = {
+ .name = "ppc-of-ohci",
+ .owner = THIS_MODULE,
+ },
+};
+
+static int __init ohci_hcd_ppc_of_init(void)
+{
+ pr_debug(DRIVER_INFO " (PPC OF)\n");
+ pr_debug("block sizes: ed %d td %d\n", sizeof(struct ed),
+ sizeof(struct td));
+
+ return of_register_driver(&ohci_hcd_ppc_of_driver);
+}
+
+static void __exit ohci_hcd_ppc_of_cleanup(void)
+{
+ of_unregister_driver(&ohci_hcd_ppc_of_driver);
+}
+
+module_init(ohci_hcd_ppc_of_init);
+module_exit(ohci_hcd_ppc_of_cleanup);
--- a/drivers/usb/host/Kconfig 2006-11-01 09:18:56.000000000 +0100
+++ b/drivers/usb/host/Kconfig 2006-11-06 11:10:29.000000000 +0100
@@ -106,6 +106,25 @@ config USB_OHCI_HCD_PPC_SOC
Enables support for the USB controller on the MPC52xx or
STB03xxx processor chip. If unsure, say Y.
+config USB_OHCI_HCD_PPC_OF
+ bool "OHCI support for PPC USB controller for OpenFirmware platform"
+ depends on USB_OHCI_HCD && PPC_OF
+ default y
+ ---help---
+ Enables support for the USB controller PowerPC OpenFirmware platform
+
+config USB_OHCI_HCD_PPC_OF_BE
+ bool "Support big endian HC"
+ depends on USB_OHCI_HCD_PPC_OF
+ default y
+ select USB_OHCI_BIG_ENDIAN
+
+config USB_OHCI_HCD_PPC_OF_LE
+ bool "Support little endian HC"
+ depends on USB_OHCI_HCD_PPC_OF
+ default n
+ select USB_OHCI_LITTLE_ENDIAN
+
config USB_OHCI_HCD_PCI
bool "OHCI support for PCI-bus USB controllers"
depends on USB_OHCI_HCD && PCI && (STB03xxx || PPC_MPC52xx)
--- a/drivers/usb/host/ohci-hcd.c 2006-11-01 09:18:56.000000000 +0100
+++ b/drivers/usb/host/ohci-hcd.c 2006-11-06 11:10:29.000000000 +0100
@@ -930,6 +930,10 @@ MODULE_LICENSE ("GPL");
#include "ohci-ppc-soc.c"
#endif
+#ifdef CONFIG_USB_OHCI_HCD_PPC_OF
+#include "ohci-ppc-of.c"
+#endif
+
#if defined(CONFIG_ARCH_AT91RM9200) || defined(CONFIG_ARCH_AT91SAM9261)
#include "ohci-at91.c"
#endif
@@ -950,6 +954,8 @@ MODULE_LICENSE ("GPL");
|| defined (CONFIG_ARCH_AT91RM9200) \
|| defined (CONFIG_ARCH_AT91SAM9261) \
|| defined (CONFIG_ARCH_PNX4008) \
+ || defined (CONFIG_USB_OHCI_HCD_PPC_OF_LE) \
+ || defined (CONFIG_USB_OHCI_HCD_PPC_OF_BE) \
)
#error "missing bus glue for ohci-hcd"
#endif
^ permalink raw reply
* [PATCH/RFC] powerpc: Add MPC5200 Interrupt Controller support.
From: Nicolas DET @ 2006-11-06 11:03 UTC (permalink / raw)
To: linuxppc-dev; +Cc: linuxppc-embedded
[-- Attachment #1: Type: text/html, Size: 26187 bytes --]
[-- Attachment #2: Type: text/plain, Size: 23707 bytes --]
This patch add MPC52xx Interrupt controller for ARCH=powerpc.
It includes the main code in arch/powerpc/sysdev/ ad well as an header file in
include/asm-powerpc.
Signed-off-by: Nicolas DET <nd@bplan-gmbh.de>
---
--- a/arch/powerpc/sysdev/mpc52xx_pic.c 1970-01-01 01:00:00.000000000 +0100
+++ b/arch/powerpc/sysdev/mpc52xx_pic.c 2006-11-06 11:10:29.000000000 +0100
@@ -0,0 +1,527 @@
+/*
+ *
+ * Programmable Interrupt Controller functions for the Freescale MPC52xx.
+ *
+ * Copyright (C) 2006 bplan GmbH
+ *
+ * Based on (well, mostly copied from) the code from the 2.4 kernel by
+ * Dale Farnsworth <dfarnsworth@mvista.com> and Kent Borg.
+ *
+ * Copyright (C) 2004 Sylvain Munaut <tnt@246tNt.com>
+ * Copyright (C) 2003 Montavista Software, Inc
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ *
+ */
+
+#undef DEBUG
+
+#include <linux/stddef.h>
+#include <linux/init.h>
+#include <linux/sched.h>
+#include <linux/signal.h>
+#include <linux/stddef.h>
+#include <linux/delay.h>
+#include <linux/irq.h>
+#include <linux/hardirq.h>
+
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <asm/system.h>
+#include <asm/irq.h>
+#include <asm/prom.h>
+#include <asm/mpc52xx.h>
+
+/*
+ *
+*/
+
+static struct mpc52xx_intr __iomem *intr;
+static struct mpc52xx_sdma __iomem *sdma;
+static struct irq_host *mpc52xx_irqhost = NULL;
+
+static unsigned char mpc52xx_map_senses[4] = {
+ IRQ_TYPE_LEVEL_HIGH,
+ IRQ_TYPE_EDGE_RISING,
+ IRQ_TYPE_EDGE_FALLING,
+ IRQ_TYPE_LEVEL_LOW,
+};
+
+/*
+ *
+*/
+
+static inline void io_be_setbit(u32 __iomem *addr, int bitno)
+{
+ out_be32(addr, in_be32(addr) | (1 << bitno) );
+}
+
+static inline void io_be_clrbit(u32 __iomem *addr, int bitno)
+{
+ out_be32(addr, in_be32(addr) & ~(1 << bitno));
+}
+
+/*
+ * IRQ[0-3] interrupt irq_chip
+*/
+
+static void mpc52xx_extirq_mask(unsigned int virq)
+{
+ int irq;
+ int l2irq;
+
+ irq = irq_map[virq].hwirq;
+ l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
+
+ pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
+
+ io_be_clrbit(&intr->ctrl, 11 - l2irq);
+}
+
+static void mpc52xx_extirq_unmask(unsigned int virq)
+{
+ int irq;
+ int l2irq;
+
+ irq = irq_map[virq].hwirq;
+ l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
+
+ pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
+
+ io_be_setbit(&intr->ctrl, 11 - l2irq);
+}
+
+static void mpc52xx_extirq_ack(unsigned int virq)
+{
+ int irq;
+ int l2irq;
+
+ irq = irq_map[virq].hwirq;
+ l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
+
+ pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
+
+ io_be_setbit(&intr->ctrl, 27-l2irq);
+}
+
+static struct irq_chip mpc52xx_extirq_irqchip = {
+ .typename = " MPC52xx IRQ[0-3] ",
+ .mask = mpc52xx_extirq_mask,
+ .unmask = mpc52xx_extirq_unmask,
+ .ack = mpc52xx_extirq_ack,
+};
+
+/*
+ * Main interrupt irq_chip
+*/
+
+static void mpc52xx_main_mask(unsigned int virq)
+{
+ int irq;
+ int l2irq;
+
+ irq = irq_map[virq].hwirq;
+ l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
+
+ pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
+
+ io_be_setbit(&intr->main_mask, 15 - l2irq);
+}
+
+static void mpc52xx_main_unmask(unsigned int virq)
+{
+ int irq;
+ int l2irq;
+
+ irq = irq_map[virq].hwirq;
+ l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
+
+ pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
+
+ io_be_clrbit(&intr->main_mask, 15 - l2irq);
+}
+
+static struct irq_chip mpc52xx_main_irqchip = {
+ .typename = "MPC52xx Main",
+ .mask = mpc52xx_main_mask,
+ .mask_ack = mpc52xx_main_mask,
+ .unmask = mpc52xx_main_unmask,
+};
+
+/*
+ * Peripherals interrupt irq_chip
+*/
+
+static void mpc52xx_periph_mask(unsigned int virq)
+{
+ int irq;
+ int l2irq;
+
+ irq = irq_map[virq].hwirq;
+ l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
+
+ pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
+
+ io_be_setbit(&intr->per_mask, 31 - l2irq);
+}
+
+static void mpc52xx_periph_unmask(unsigned int virq)
+{
+ int irq;
+ int l2irq;
+
+ irq = irq_map[virq].hwirq;
+ l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
+
+ pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
+
+ io_be_clrbit(&intr->per_mask, 31 - l2irq);
+}
+
+static struct irq_chip mpc52xx_periph_irqchip = {
+ .typename = "MPC52xx Peripherals",
+ .mask = mpc52xx_periph_mask,
+ .mask_ack = mpc52xx_periph_mask,
+ .unmask = mpc52xx_periph_unmask,
+};
+
+/*
+ * SDMA interrupt irq_chip
+*/
+
+static void mpc52xx_sdma_mask(unsigned int virq)
+{
+ int irq;
+ int l2irq;
+
+ irq = irq_map[virq].hwirq;
+ l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
+
+ pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
+
+ io_be_setbit(&sdma->IntMask, l2irq);
+}
+
+static void mpc52xx_sdma_unmask(unsigned int virq)
+{
+ int irq;
+ int l2irq;
+
+ irq = irq_map[virq].hwirq;
+ l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
+
+ pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
+
+ io_be_clrbit(&sdma->IntMask, l2irq);
+}
+
+static void mpc52xx_sdma_ack(unsigned int virq)
+{
+ int irq;
+ int l2irq;
+
+ irq = irq_map[virq].hwirq;
+ l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
+
+ pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
+
+ out_be32(&sdma->IntPend, 1 << l2irq);
+}
+
+static struct irq_chip mpc52xx_sdma_irqchip = {
+ .typename = "MPC52xx SDMA",
+ .mask = mpc52xx_sdma_mask,
+ .unmask = mpc52xx_sdma_unmask,
+ .ack = mpc52xx_sdma_ack,
+};
+
+/*
+ * irq_host
+*/
+
+static int mpc52xx_irqhost_match(struct irq_host *h, struct device_node *node)
+{
+ pr_debug("%s: node=%p\n", __func__, node);
+ return mpc52xx_irqhost->host_data == node;
+}
+
+static int mpc52xx_irqhost_xlate(struct irq_host *h, struct device_node *ct,
+ u32 * intspec, unsigned int intsize,
+ irq_hw_number_t * out_hwirq,
+ unsigned int *out_flags)
+{
+ int intrvect_l1;
+ int intrvect_l2;
+ int intrvect_type;
+ int intrvect_linux;
+
+ if (intsize != 3)
+ return -1;
+
+ intrvect_l1 = (int)intspec[0];
+ intrvect_l2 = (int)intspec[1];
+ intrvect_type = (int)intspec[2];
+
+ intrvect_linux =
+ (intrvect_l1 << MPC52xx_IRQ_L1_OFFSET) & MPC52xx_IRQ_L1_MASK;
+ intrvect_linux |=
+ (intrvect_l2 << MPC52xx_IRQ_L2_OFFSET) & MPC52xx_IRQ_L2_MASK;
+
+ pr_debug("return %x, l1=%d, l2=%d\n", intrvect_linux, intrvect_l1,
+ intrvect_l2);
+
+ *out_hwirq = intrvect_linux;
+ *out_flags = mpc52xx_map_senses[intrvect_type];
+
+ return 0;
+}
+
+/*
+ * this function retrieves the correct IRQ type out
+ * of the MPC regs
+ * Only externals IRQs needs this
+*/
+static int mpc52xx_irqx_gettype(int irq)
+{
+ int type;
+ u32 ctrl_reg;
+
+ ctrl_reg = in_be32(&intr->ctrl);
+ type = (ctrl_reg >> (22 - irq * 2)) & 0x3;
+
+ return mpc52xx_map_senses[type];
+}
+
+static int mpc52xx_irqhost_map(struct irq_host *h, unsigned int virq,
+ irq_hw_number_t irq)
+{
+ int l1irq;
+ int l2irq;
+ struct irq_chip *good_irqchip;
+ void *good_handle;
+ int type;
+
+ l1irq = (irq & MPC52xx_IRQ_L1_MASK) >> MPC52xx_IRQ_L1_OFFSET;
+ l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
+
+ /*
+ * Most of ours IRQs will be level low
+ * Only external IRQs on some platform may be others
+ */
+ type = IRQ_TYPE_LEVEL_LOW;
+
+ switch (l1irq) {
+ case MPC52xx_IRQ_L1_CRIT:
+ pr_debug("%s: Critical. l2=%x\n", __func__, l2irq);
+
+ BUG_ON(l2irq != 0);
+
+ type = mpc52xx_irqx_gettype(l2irq);
+ good_irqchip = &mpc52xx_extirq_irqchip;
+ break;
+
+ case MPC52xx_IRQ_L1_MAIN:
+ pr_debug("%s: Main IRQ[1-3] l2=%x\n", __func__, l2irq);
+
+ if ((l2irq >= 1) && (l2irq <= 3)) {
+ type = mpc52xx_irqx_gettype(l2irq);
+ good_irqchip = &mpc52xx_extirq_irqchip;
+ } else {
+ good_irqchip = &mpc52xx_main_irqchip;
+ }
+ break;
+
+ case MPC52xx_IRQ_L1_PERP:
+ pr_debug("%s: Peripherals. l2=%x\n", __func__, l2irq);
+ good_irqchip = &mpc52xx_periph_irqchip;
+ break;
+
+ case MPC52xx_IRQ_L1_SDMA:
+ pr_debug("%s: SDMA. l2=%x\n", __func__, l2irq);
+ good_irqchip = &mpc52xx_sdma_irqchip;
+ break;
+
+ default:
+ pr_debug("%s: Error, unknown L1 IRQ (0x%x)\n", __func__, l1irq);
+ printk(KERN_ERR "Unknow IRQ!\n");
+ return -EINVAL;
+ }
+
+ switch (type) {
+ case IRQ_TYPE_EDGE_FALLING:
+ case IRQ_TYPE_EDGE_RISING:
+ good_handle = handle_edge_irq;
+ break;
+ default:
+ good_handle = handle_level_irq;
+ }
+
+ set_irq_chip_and_handler(virq, good_irqchip, good_handle);
+
+ pr_debug("%s: virq=%x, hw=%x. type=%x\n", __func__, virq,
+ (int)irq, type);
+
+ return 0;
+}
+
+static struct irq_host_ops mpc52xx_irqhost_ops = {
+ .match = mpc52xx_irqhost_match,
+ .xlate = mpc52xx_irqhost_xlate,
+ .map = mpc52xx_irqhost_map,
+};
+
+/*
+ * init (public)
+*/
+
+void __init mpc52xx_init_irq(void)
+{
+ struct device_node *picnode = NULL;
+ int picnode_regsize;
+ u32 picnode_regoffset;
+
+ struct device_node *sdmanode = NULL;
+ int sdmanode_regsize;
+ u32 sdmanode_regoffset;
+
+ u64 size64;
+ int flags;
+
+ u32 intr_ctrl;
+
+ picnode = of_find_compatible_node(NULL, "interrupt-controller", "mpc5200-pic");
+ if (picnode == NULL) {
+ printk(KERN_ERR "MPC52xx PIC: Unable to find the interrupt controller in the OpenFirmware device tree\n");
+ goto end;
+ }
+
+ sdmanode = of_find_compatible_node(NULL, "dma-controller", "mpc5200-bestcomm");
+ if (sdmanode == NULL) {
+ printk(KERN_ERR "MPC52xx PIC: Unable to find the Bestcomm DMA controller device in the OpenFirmware device tree\n");
+ goto end;
+ }
+
+ /* Retrieve PIC ressources */
+ picnode_regoffset = (u32) of_get_address(picnode, 0, &size64, &flags);
+ if (picnode_regoffset == 0) {
+ printk(KERN_ERR "MPC52xx PIC: Unable to get the interrupt controller address\n");
+ goto end;
+ }
+
+ picnode_regoffset = of_translate_address(picnode, (u32 *) picnode_regoffset);
+ picnode_regsize = (int) size64;
+
+ /* Retrieve SDMA ressources */
+ sdmanode_regoffset = (u32) of_get_address(sdmanode, 0, &size64, &flags);
+ if (sdmanode_regoffset == 0) {
+ printk(KERN_ERR "MPC52xx PIC: Unable to get the Bestcomm DMA controller address\n");
+ goto end;
+ }
+
+ sdmanode_regoffset = of_translate_address(sdmanode, (u32 *) sdmanode_regoffset);
+ sdmanode_regsize = (int) size64;
+
+ /* Remap the necessary zones */
+ intr = ioremap(picnode_regoffset, picnode_regsize);
+ if (intr == NULL) {
+ printk(KERN_ERR "MPC52xx PIC: Unable to ioremap interrupt controller registers!");
+ goto end;
+ }
+
+ sdma = ioremap(sdmanode_regoffset, sdmanode_regsize);
+ if (sdma == NULL) {
+ iounmap(intr);
+ printk(KERN_ERR "MPC52xx PIC: Unable to ioremap Bestcomm DMA controller registers!");
+ goto end;
+ }
+
+ printk(KERN_INFO "MPC52xx PIC: MPC52xx PIC Remapped at 0x%8.8x\n", picnode_regoffset);
+ printk(KERN_INFO "MPC52xx PIC: MPC52xx SDMA Remapped at 0x%8.8x\n", sdmanode_regoffset);
+
+ /* Disable all interrupt sources. */
+ out_be32(&sdma->IntPend, 0xffffffff); /* 1 means clear pending */
+ out_be32(&sdma->IntMask, 0xffffffff); /* 1 means disabled */
+ out_be32(&intr->per_mask, 0x7ffffc00); /* 1 means disabled */
+ out_be32(&intr->main_mask, 0x00010fff); /* 1 means disabled */
+ intr_ctrl = in_be32(&intr->ctrl);
+ intr_ctrl &= 0x00ff0000; /* Keeps IRQ[0-3] config */
+ intr_ctrl |= 0x0f000000 | /* clear IRQ 0-3 */
+ 0x00001000 | /* MEE master external enable */
+ 0x00000000 | /* 0 means disable IRQ 0-3 */
+ 0x00000001; /* CEb route critical normally */
+ out_be32(&intr->ctrl, intr_ctrl);
+
+ /* Zero a bunch of the priority settings. */
+ out_be32(&intr->per_pri1, 0);
+ out_be32(&intr->per_pri2, 0);
+ out_be32(&intr->per_pri3, 0);
+ out_be32(&intr->main_pri1, 0);
+ out_be32(&intr->main_pri2, 0);
+
+ /*
+ * As last step, add an irq host to translate the real
+ * hw irq information provided by the ofw to linux virq
+ */
+
+ mpc52xx_irqhost =
+ irq_alloc_host(IRQ_HOST_MAP_LINEAR, MPC52xx_IRQ_HIGHTESTHWIRQ,
+ &mpc52xx_irqhost_ops, -1);
+
+ if (mpc52xx_irqhost) {
+ mpc52xx_irqhost->host_data = picnode;
+ printk(KERN_INFO "MPC52xx PIC is up and running!\n");
+ } else {
+ printk(KERN_ERR "MPC52xx PIC: Unable to allocate the IRQ host\n");
+ }
+
+end:
+ of_node_put(picnode);
+ of_node_put(sdmanode);
+}
+
+/*
+ * get_irq (public)
+*/
+unsigned int mpc52xx_get_irq(void)
+{
+ u32 status;
+ int irq = NO_IRQ_IGNORE;
+
+ status = in_be32(&intr->enc_status);
+ if (status & 0x00000400) { /* critical */
+ irq = (status >> 8) & 0x3;
+ if (irq == 2) /* high priority peripheral */
+ goto peripheral;
+ irq |=
+ (MPC52xx_IRQ_L1_CRIT << MPC52xx_IRQ_L1_OFFSET) &
+ MPC52xx_IRQ_L1_MASK;
+ } else if (status & 0x00200000) { /* main */
+ irq = (status >> 16) & 0x1f;
+ if (irq == 4) /* low priority peripheral */
+ goto peripheral;
+ irq |=
+ (MPC52xx_IRQ_L1_MAIN << MPC52xx_IRQ_L1_OFFSET) &
+ MPC52xx_IRQ_L1_MASK;
+ } else if (status & 0x20000000) { /* peripheral */
+ peripheral:
+ irq = (status >> 24) & 0x1f;
+ if (irq == 0) { /* bestcomm */
+ status = in_be32(&sdma->IntPend);
+ irq = ffs(status) - 1;
+ irq |=
+ (MPC52xx_IRQ_L1_SDMA << MPC52xx_IRQ_L1_OFFSET) &
+ MPC52xx_IRQ_L1_MASK;
+ } else
+ irq |=
+ (MPC52xx_IRQ_L1_PERP << MPC52xx_IRQ_L1_OFFSET) &
+ MPC52xx_IRQ_L1_MASK;
+
+ }
+
+ pr_debug("%s: irq=%x. virq=%d\n", __func__, irq,
+ irq_linear_revmap(mpc52xx_irqhost, irq));
+
+ return irq_linear_revmap(mpc52xx_irqhost, irq);
+}
--- a/arch/powerpc/sysdev/Makefile 2006-11-01 09:18:43.000000000 +0100
+++ b/arch/powerpc/sysdev/Makefile 2006-11-06 11:10:46.000000000 +0100
@@ -13,6 +13,7 @@ obj-$(CONFIG_FSL_SOC) += fsl_soc.o
obj-$(CONFIG_PPC_TODC) += todc.o
obj-$(CONFIG_TSI108_BRIDGE) += tsi108_pci.o tsi108_dev.o
obj-$(CONFIG_QUICC_ENGINE) += qe_lib/
+obj-$(CONFIG_PPC_MPC52xx) += mpc52xx_pic.o
ifeq ($(CONFIG_PPC_MERGE),y)
obj-$(CONFIG_PPC_I8259) += i8259.o
--- a/include/asm-powerpc/mpc52xx.h 1970-01-01 01:00:00.000000000 +0100
+++ b/include/asm-powerpc/mpc52xx.h 2006-11-06 11:10:29.000000000 +0100
@@ -0,0 +1,283 @@
+/*
+ * Prototypes, etc. for the Freescale MPC52xx embedded cpu chips
+ * May need to be cleaned as the port goes on ...
+ *
+ * Copyright (C) 2004-2005 Sylvain Munaut <tnt@246tNt.com>
+ * Copyright (C) 2003 MontaVista, Software, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#ifndef __ASM_POWERPC_MPC52xx_H__
+#define __ASM_POWERPC_MPC52xx_H__
+
+#ifndef __ASSEMBLY__
+#include <asm/types.h>
+#include <asm/prom.h>
+#endif /* __ASSEMBLY__ */
+
+/* HW IRQ mapping */
+#define MPC52xx_IRQ_L1_CRIT (0)
+#define MPC52xx_IRQ_L1_MAIN (1)
+#define MPC52xx_IRQ_L1_PERP (2)
+#define MPC52xx_IRQ_L1_SDMA (3)
+
+#define MPC52xx_IRQ_L1_OFFSET (6)
+#define MPC52xx_IRQ_L1_MASK (0xc0)
+
+#define MPC52xx_IRQ_L2_OFFSET (0)
+#define MPC52xx_IRQ_L2_MASK (0x3f)
+
+#define MPC52xx_IRQ_HIGHTESTHWIRQ (0xd0)
+
+/* Interrupt controller Register set */
+struct mpc52xx_intr {
+ u32 per_mask; /* INTR + 0x00 */
+ u32 per_pri1; /* INTR + 0x04 */
+ u32 per_pri2; /* INTR + 0x08 */
+ u32 per_pri3; /* INTR + 0x0c */
+ u32 ctrl; /* INTR + 0x10 */
+ u32 main_mask; /* INTR + 0x14 */
+ u32 main_pri1; /* INTR + 0x18 */
+ u32 main_pri2; /* INTR + 0x1c */
+ u32 reserved1; /* INTR + 0x20 */
+ u32 enc_status; /* INTR + 0x24 */
+ u32 crit_status; /* INTR + 0x28 */
+ u32 main_status; /* INTR + 0x2c */
+ u32 per_status; /* INTR + 0x30 */
+ u32 reserved2; /* INTR + 0x34 */
+ u32 per_error; /* INTR + 0x38 */
+};
+
+
+/* ======================================================================== */
+/* Structures mapping of some unit register set */
+/* ======================================================================== */
+
+#ifndef __ASSEMBLY__
+
+/* Memory Mapping Control */
+struct mpc52xx_mmap_ctl {
+ u32 mbar; /* MMAP_CTRL + 0x00 */
+
+ u32 cs0_start; /* MMAP_CTRL + 0x04 */
+ u32 cs0_stop; /* MMAP_CTRL + 0x08 */
+ u32 cs1_start; /* MMAP_CTRL + 0x0c */
+ u32 cs1_stop; /* MMAP_CTRL + 0x10 */
+ u32 cs2_start; /* MMAP_CTRL + 0x14 */
+ u32 cs2_stop; /* MMAP_CTRL + 0x18 */
+ u32 cs3_start; /* MMAP_CTRL + 0x1c */
+ u32 cs3_stop; /* MMAP_CTRL + 0x20 */
+ u32 cs4_start; /* MMAP_CTRL + 0x24 */
+ u32 cs4_stop; /* MMAP_CTRL + 0x28 */
+ u32 cs5_start; /* MMAP_CTRL + 0x2c */
+ u32 cs5_stop; /* MMAP_CTRL + 0x30 */
+
+ u32 sdram0; /* MMAP_CTRL + 0x34 */
+ u32 sdram1; /* MMAP_CTRL + 0X38 */
+
+ u32 reserved[4]; /* MMAP_CTRL + 0x3c .. 0x48 */
+
+ u32 boot_start; /* MMAP_CTRL + 0x4c */
+ u32 boot_stop; /* MMAP_CTRL + 0x50 */
+
+ u32 ipbi_ws_ctrl; /* MMAP_CTRL + 0x54 */
+
+ u32 cs6_start; /* MMAP_CTRL + 0x58 */
+ u32 cs6_stop; /* MMAP_CTRL + 0x5c */
+ u32 cs7_start; /* MMAP_CTRL + 0x60 */
+ u32 cs7_stop; /* MMAP_CTRL + 0x64 */
+};
+
+/* SDRAM control */
+struct mpc52xx_sdram {
+ u32 mode; /* SDRAM + 0x00 */
+ u32 ctrl; /* SDRAM + 0x04 */
+ u32 config1; /* SDRAM + 0x08 */
+ u32 config2; /* SDRAM + 0x0c */
+};
+
+/* SDMA */
+struct mpc52xx_sdma {
+ u32 taskBar; /* SDMA + 0x00 */
+ u32 currentPointer; /* SDMA + 0x04 */
+ u32 endPointer; /* SDMA + 0x08 */
+ u32 variablePointer; /* SDMA + 0x0c */
+
+ u8 IntVect1; /* SDMA + 0x10 */
+ u8 IntVect2; /* SDMA + 0x11 */
+ u16 PtdCntrl; /* SDMA + 0x12 */
+
+ u32 IntPend; /* SDMA + 0x14 */
+ u32 IntMask; /* SDMA + 0x18 */
+
+ u16 tcr[16]; /* SDMA + 0x1c .. 0x3a */
+
+ u8 ipr[32]; /* SDMA + 0x3c .. 0x5b */
+
+ u32 cReqSelect; /* SDMA + 0x5c */
+ u32 task_size0; /* SDMA + 0x60 */
+ u32 task_size1; /* SDMA + 0x64 */
+ u32 MDEDebug; /* SDMA + 0x68 */
+ u32 ADSDebug; /* SDMA + 0x6c */
+ u32 Value1; /* SDMA + 0x70 */
+ u32 Value2; /* SDMA + 0x74 */
+ u32 Control; /* SDMA + 0x78 */
+ u32 Status; /* SDMA + 0x7c */
+ u32 PTDDebug; /* SDMA + 0x80 */
+};
+
+/* GPT */
+struct mpc52xx_gpt {
+ u32 mode; /* GPTx + 0x00 */
+ u32 count; /* GPTx + 0x04 */
+ u32 pwm; /* GPTx + 0x08 */
+ u32 status; /* GPTx + 0X0c */
+};
+
+/* GPIO */
+struct mpc52xx_gpio {
+ u32 port_config; /* GPIO + 0x00 */
+ u32 simple_gpioe; /* GPIO + 0x04 */
+ u32 simple_ode; /* GPIO + 0x08 */
+ u32 simple_ddr; /* GPIO + 0x0c */
+ u32 simple_dvo; /* GPIO + 0x10 */
+ u32 simple_ival; /* GPIO + 0x14 */
+ u8 outo_gpioe; /* GPIO + 0x18 */
+ u8 reserved1[3]; /* GPIO + 0x19 */
+ u8 outo_dvo; /* GPIO + 0x1c */
+ u8 reserved2[3]; /* GPIO + 0x1d */
+ u8 sint_gpioe; /* GPIO + 0x20 */
+ u8 reserved3[3]; /* GPIO + 0x21 */
+ u8 sint_ode; /* GPIO + 0x24 */
+ u8 reserved4[3]; /* GPIO + 0x25 */
+ u8 sint_ddr; /* GPIO + 0x28 */
+ u8 reserved5[3]; /* GPIO + 0x29 */
+ u8 sint_dvo; /* GPIO + 0x2c */
+ u8 reserved6[3]; /* GPIO + 0x2d */
+ u8 sint_inten; /* GPIO + 0x30 */
+ u8 reserved7[3]; /* GPIO + 0x31 */
+ u16 sint_itype; /* GPIO + 0x34 */
+ u16 reserved8; /* GPIO + 0x36 */
+ u8 gpio_control; /* GPIO + 0x38 */
+ u8 reserved9[3]; /* GPIO + 0x39 */
+ u8 sint_istat; /* GPIO + 0x3c */
+ u8 sint_ival; /* GPIO + 0x3d */
+ u8 bus_errs; /* GPIO + 0x3e */
+ u8 reserved10; /* GPIO + 0x3f */
+};
+
+#define MPC52xx_GPIO_PSC_CONFIG_UART_WITHOUT_CD 4
+#define MPC52xx_GPIO_PSC_CONFIG_UART_WITH_CD 5
+#define MPC52xx_GPIO_PCI_DIS (1<<15)
+
+/* GPIO with WakeUp*/
+struct mpc52xx_gpio_wkup {
+ u8 wkup_gpioe; /* GPIO_WKUP + 0x00 */
+ u8 reserved1[3]; /* GPIO_WKUP + 0x03 */
+ u8 wkup_ode; /* GPIO_WKUP + 0x04 */
+ u8 reserved2[3]; /* GPIO_WKUP + 0x05 */
+ u8 wkup_ddr; /* GPIO_WKUP + 0x08 */
+ u8 reserved3[3]; /* GPIO_WKUP + 0x09 */
+ u8 wkup_dvo; /* GPIO_WKUP + 0x0C */
+ u8 reserved4[3]; /* GPIO_WKUP + 0x0D */
+ u8 wkup_inten; /* GPIO_WKUP + 0x10 */
+ u8 reserved5[3]; /* GPIO_WKUP + 0x11 */
+ u8 wkup_iinten; /* GPIO_WKUP + 0x14 */
+ u8 reserved6[3]; /* GPIO_WKUP + 0x15 */
+ u16 wkup_itype; /* GPIO_WKUP + 0x18 */
+ u8 reserved7[2]; /* GPIO_WKUP + 0x1A */
+ u8 wkup_maste; /* GPIO_WKUP + 0x1C */
+ u8 reserved8[3]; /* GPIO_WKUP + 0x1D */
+ u8 wkup_ival; /* GPIO_WKUP + 0x20 */
+ u8 reserved9[3]; /* GPIO_WKUP + 0x21 */
+ u8 wkup_istat; /* GPIO_WKUP + 0x24 */
+ u8 reserved10[3]; /* GPIO_WKUP + 0x25 */
+};
+
+/* XLB Bus control */
+struct mpc52xx_xlb {
+ u8 reserved[0x40];
+ u32 config; /* XLB + 0x40 */
+ u32 version; /* XLB + 0x44 */
+ u32 status; /* XLB + 0x48 */
+ u32 int_enable; /* XLB + 0x4c */
+ u32 addr_capture; /* XLB + 0x50 */
+ u32 bus_sig_capture; /* XLB + 0x54 */
+ u32 addr_timeout; /* XLB + 0x58 */
+ u32 data_timeout; /* XLB + 0x5c */
+ u32 bus_act_timeout; /* XLB + 0x60 */
+ u32 master_pri_enable; /* XLB + 0x64 */
+ u32 master_priority; /* XLB + 0x68 */
+ u32 base_address; /* XLB + 0x6c */
+ u32 snoop_window; /* XLB + 0x70 */
+};
+
+#define MPC52xx_XLB_CFG_PLDIS (1 << 31)
+#define MPC52xx_XLB_CFG_SNOOP (1 << 15)
+
+/* Clock Distribution control */
+struct mpc52xx_cdm {
+ u32 jtag_id; /* CDM + 0x00 reg0 read only */
+ u32 rstcfg; /* CDM + 0x04 reg1 read only */
+ u32 breadcrumb; /* CDM + 0x08 reg2 */
+
+ u8 mem_clk_sel; /* CDM + 0x0c reg3 byte0 */
+ u8 xlb_clk_sel; /* CDM + 0x0d reg3 byte1 read only */
+ u8 ipb_clk_sel; /* CDM + 0x0e reg3 byte2 */
+ u8 pci_clk_sel; /* CDM + 0x0f reg3 byte3 */
+
+ u8 ext_48mhz_en; /* CDM + 0x10 reg4 byte0 */
+ u8 fd_enable; /* CDM + 0x11 reg4 byte1 */
+ u16 fd_counters; /* CDM + 0x12 reg4 byte2,3 */
+
+ u32 clk_enables; /* CDM + 0x14 reg5 */
+
+ u8 osc_disable; /* CDM + 0x18 reg6 byte0 */
+ u8 reserved0[3]; /* CDM + 0x19 reg6 byte1,2,3 */
+
+ u8 ccs_sleep_enable; /* CDM + 0x1c reg7 byte0 */
+ u8 osc_sleep_enable; /* CDM + 0x1d reg7 byte1 */
+ u8 reserved1; /* CDM + 0x1e reg7 byte2 */
+ u8 ccs_qreq_test; /* CDM + 0x1f reg7 byte3 */
+
+ u8 soft_reset; /* CDM + 0x20 u8 byte0 */
+ u8 no_ckstp; /* CDM + 0x21 u8 byte0 */
+ u8 reserved2[2]; /* CDM + 0x22 u8 byte1,2,3 */
+
+ u8 pll_lock; /* CDM + 0x24 reg9 byte0 */
+ u8 pll_looselock; /* CDM + 0x25 reg9 byte1 */
+ u8 pll_sm_lockwin; /* CDM + 0x26 reg9 byte2 */
+ u8 reserved3; /* CDM + 0x27 reg9 byte3 */
+
+ u16 reserved4; /* CDM + 0x28 reg10 byte0,1 */
+ u16 mclken_div_psc1; /* CDM + 0x2a reg10 byte2,3 */
+
+ u16 reserved5; /* CDM + 0x2c reg11 byte0,1 */
+ u16 mclken_div_psc2; /* CDM + 0x2e reg11 byte2,3 */
+
+ u16 reserved6; /* CDM + 0x30 reg12 byte0,1 */
+ u16 mclken_div_psc3; /* CDM + 0x32 reg12 byte2,3 */
+
+ u16 reserved7; /* CDM + 0x34 reg13 byte0,1 */
+ u16 mclken_div_psc6; /* CDM + 0x36 reg13 byte2,3 */
+};
+
+#endif /* __ASSEMBLY__ */
+
+
+/* ========================================================================= */
+/* Prototypes for MPC52xx sysdev */
+/* ========================================================================= */
+
+#ifndef __ASSEMBLY__
+
+extern void mpc52xx_init_irq(void);
+extern unsigned int mpc52xx_get_irq(void);
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __ASM_POWERPC_MPC52xx_H__ */
+
^ permalink raw reply
* Re: Has anyone 2.6 kernel with Xenomai and MPC5200 Lite running?
From: Wolfgang Grandegger @ 2006-11-06 11:21 UTC (permalink / raw)
To: linuxppc-embedded
In-Reply-To: <20061105212429.GA35760@server.idefix.loc>
Hello Matthias,
Matthias Fechner wrote:
> Hello Wolfgang,
>
> * Wolfgang Grandegger <wg@grandegger.com> [05-11-06 21:50]:
>> I also tried to get Sylvain's patches working on 2.6.18 and gave up
>> rather frustrated. They do not work "as is" :-(. I can offer you a
>> solution for Xenomai on 2.6.17, if this is an option for you. That's
>> what I got working for development.
>
> that would be fantastic.
> I only need kernel 2.6 running on MPC5200 with xenomai.
> I can give you access to one of my servers if you want to copy there
> the kernel.
Some time ago I got the MPC5200 patches from the Pengutronix's OSELAS
project working for DENX Linux 2.6.17. In the meantime they have update
to 2.6.18. Take OSELAS.BSP-Phytec-phyCORE-MPC5200B-tiny-4.tar.gz from
http://www.pengutronix.de/oselas/bsp/phytec/download/phyCORE-MPC5200B-tiny/,
unpack it and apply the relevant patches from the kernel-patches-target
diretory to linux-2.6-denx#v2.6.18. I think the following patches should
be sufficient (in that order):
fec_mpc52xx_bestcomm.diff
fec_mpc52xx.diff
drivers_serial_mpc52xx_uart_fix.diff
mpc5200_physmap.diff
You can find the most recent Xenomai patch 2.6.18-ppc-1.05.00 at
"ftp://ftp.denx.de/xenomai". I'm going to test them later today with
Xenomai.
Good luck.
Wolfgang.
^ permalink raw reply
* Re: Has anyone 2.6 kernel with Xenomai and MPC5200 Lite running?
From: Wolfgang Grandegger @ 2006-11-06 11:25 UTC (permalink / raw)
To: linuxppc-embedded
In-Reply-To: <20061105212429.GA35760@server.idefix.loc>
Hello Matthias,
Matthias Fechner wrote:
> Hello Wolfgang,
>
> * Wolfgang Grandegger <wg@grandegger.com> [05-11-06 21:50]:
>> I also tried to get Sylvain's patches working on 2.6.18 and gave up
>> rather frustrated. They do not work "as is" :-(. I can offer you a
>> solution for Xenomai on 2.6.17, if this is an option for you. That's
>> what I got working for development.
>
> that would be fantastic.
> I only need kernel 2.6 running on MPC5200 with xenomai.
> I can give you access to one of my servers if you want to copy there
> the kernel.
Some time ago I got the MPC5200 patches from the Pengutronix's OSELAS
project working for DENX Linux 2.6.17. In the meantime they have update
to 2.6.18. Take OSELAS.BSP-Phytec-phyCORE-MPC5200B-tiny-4.tar.gz from
http://www.pengutronix.de/oselas/bsp/phytec/download/phyCORE-MPC5200B-tiny/,
unpack it and apply the relevant patches from the kernel-patches-target
directory to linux-2.6-denx#v2.6.18. I think the following patches
should be sufficient (in that order):
fec_mpc52xx_bestcomm.diff
fec_mpc52xx.diff
drivers_serial_mpc52xx_uart_fix.diff
mpc5200_physmap.diff
You can find the most recent Xenomai patch 2.6.18-ppc-1.05.00 at
ftp://ftp.denx.de/xenomai. I'm going to test them later today with Xenomai.
Good luck.
Wolfgang.
^ permalink raw reply
* Re: Flash programming using a BDI2000 on a MPC8248 CPU
From: Adrian Cox @ 2006-11-06 11:11 UTC (permalink / raw)
To: Laurent Pinchart; +Cc: linuxppc-embedded
In-Reply-To: <200611060942.05419.laurent.pinchart@tbox.biz>
On Mon, 2006-11-06 at 09:42 +0100, Laurent Pinchart wrote:
> [INIT]
> WREG MSR 0x00000000
> WM32 0x00010004 0xffff2081 ; SYPCR
> WM32 0x00010024 0x00000000 ; BCR
> WM32 0x00010000 0x82240000 ; SIUMCR
> WM32 0x00010c80 0x00000001 ; SCCR
> WM32 0x000119c4 0x00000000 ; RCCR
> ; Initialize the flash memory controller
> WM32 0x00010100 0x40001001 ; BR0
> WM32 0x00010104 0xf8000834 ; OR0
It looks like your workspace is in RAM, but there's nothing in the setup
above to initialise the memory controller banks for your RAM. Check that
you can read and write the workspace locations with mm and md from the
BDI command line.
--
Adrian Cox <adrian@humboldt.co.uk>
^ permalink raw reply
* Re: Flash programming using a BDI2000 on a MPC8248 CPU
From: Laurent Pinchart @ 2006-11-06 12:16 UTC (permalink / raw)
To: Adrian Cox; +Cc: linuxppc-embedded
In-Reply-To: <1162811478.16089.8.camel@localhost.localdomain>
Hi Adrian,
> > [INIT]
> > WREG MSR 0x00000000
> > WM32 0x00010004 0xffff2081 ; SYPCR
> > WM32 0x00010024 0x00000000 ; BCR
> > WM32 0x00010000 0x82240000 ; SIUMCR
> > WM32 0x00010c80 0x00000001 ; SCCR
> > WM32 0x000119c4 0x00000000 ; RCCR
> > ; Initialize the flash memory controller
> > WM32 0x00010100 0x40001001 ; BR0
> > WM32 0x00010104 0xf8000834 ; OR0
>
> It looks like your workspace is in RAM, but there's nothing in the setup
> above to initialise the memory controller banks for your RAM. Check that
> you can read and write the workspace locations with mm and md from the
> BDI command line.
The workspace is in internal RAM, mapped at address 0x00000000 (the hardware
reset configuration register is 0x00000000). I tried setting IMMR to
0xf0000000 and mapping the SDRAM at 0x00000000, without success. The BDI2000
reports successfull flash programming, but the flash is definitely empty.
BDI>prog 0x40000000 u-boot-1.1.4-ucc32.16-0005 BIN
Programming u-boot-1.1.4-ucc32.16-0005 , please wait ....
Programming flash passed
BDI>md 0x40000000
40000000 : ffffffff ffffffff ffffffff ffffffff ................
40000010 : ffffffff ffffffff ffffffff ffffffff ................
40000020 : ffffffff ffffffff ffffffff ffffffff ................
40000030 : ffffffff ffffffff ffffffff ffffffff ................
40000040 : ffffffff ffffffff ffffffff ffffffff ................
40000050 : ffffffff ffffffff ffffffff ffffffff ................
40000060 : ffffffff ffffffff ffffffff ffffffff ................
40000070 : ffffffff ffffffff ffffffff ffffffff ................
40000080 : ffffffff ffffffff ffffffff ffffffff ................
40000090 : ffffffff ffffffff ffffffff ffffffff ................
400000a0 : ffffffff ffffffff ffffffff ffffffff ................
400000b0 : ffffffff ffffffff ffffffff ffffffff ................
400000c0 : ffffffff ffffffff ffffffff ffffffff ................
400000d0 : ffffffff ffffffff ffffffff ffffffff ................
400000e0 : ffffffff ffffffff ffffffff ffffffff ................
400000f0 : ffffffff ffffffff ffffffff ffffffff ................
I made sure I can write to the workspace at 0x00008000 using mm and md, using
both internal RAM (IMMR = 0x00000000) or SDRAM (IMMR = 0xf0000000).
Laurent Pinchart
^ permalink raw reply
* Re: Flash programming using a BDI2000 on a MPC8248 CPU
From: Adrian Cox @ 2006-11-06 12:26 UTC (permalink / raw)
To: Laurent Pinchart; +Cc: linuxppc-embedded
In-Reply-To: <200611061316.47705.laurent.pinchart@tbox.biz>
On Mon, 2006-11-06 at 13:16 +0100, Laurent Pinchart wrote:
> The workspace is in internal RAM, mapped at address 0x00000000 (the hardware
> reset configuration register is 0x00000000). I tried setting IMMR to
> 0xf0000000 and mapping the SDRAM at 0x00000000, without success. The BDI2000
> reports successfull flash programming, but the flash is definitely empty.
I've also had problems with 8260 family flash programming caused by the
processor reading the Hard Reset Configuration Word from flash before
the BDI takes over. Does your board allow you to change RSTCONF to stop
the processor reading the HRCW?
--
Adrian Cox <adrian@humboldt.co.uk>
^ permalink raw reply
* Re: Flash programming using a BDI2000 on a MPC8248 CPU
From: Laurent Pinchart @ 2006-11-06 12:38 UTC (permalink / raw)
To: Adrian Cox; +Cc: linuxppc-embedded
In-Reply-To: <1162815970.20962.3.camel@localhost.localdomain>
> > The workspace is in internal RAM, mapped at address 0x00000000 (the
> > hardware reset configuration register is 0x00000000). I tried setting
> > IMMR to 0xf0000000 and mapping the SDRAM at 0x00000000, without success.
> > The BDI2000 reports successfull flash programming, but the flash is
> > definitely empty.
>
> I've also had problems with 8260 family flash programming caused by the
> processor reading the Hard Reset Configuration Word from flash before
> the BDI takes over. Does your board allow you to change RSTCONF to stop
> the processor reading the HRCW?
Yes it does. The HRCW is set to 0x00000000 by deasserting RSTCONF (logic
high). All tests were made with RSTCONF high (and thus HRCW equal to
0x00000000).
Laurent Pinchart
^ permalink raw reply
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