* Re: [Cbe-oss-dev] [PATCH] cell: abstract spu management routines
From: Michael Ellerman @ 2006-11-08 6:28 UTC (permalink / raw)
To: Geoff Levand; +Cc: linuxppc-dev, cbe-oss-dev, Arnd Bergmann
In-Reply-To: <45516A0C.5050607@am.sony.com>
[-- Attachment #1: Type: text/plain, Size: 1137 bytes --]
On Tue, 2006-11-07 at 21:24 -0800, Geoff Levand wrote:
> Michael Ellerman wrote:
> >> +static struct platform_data *platform_data(struct spu *spu)
> >> +{
> >> + BUG_ON(!spu->platform_data);
> >> + return (struct platform_data*)spu->platform_data;
> >> +}
> >
> > I don't see the point of this, why not just grab platform data directly?
>
> Well, first, it does a check, and second, you can't just grab platform_data,
> you need to always do the cast also. So then, is something like
> '((struct platform_data*)spu->platform_data)->' preferred over
> 'platform_data(spu)->'?
Stephen points out that you shouldn't do the cast at all (inside the
function), it's implied by the return type. And by casting explicitly
you create the potential for the return type and the cast to get out of
sync.
At some point we'll actually read the rest of the patch ;)
cheers
--
Michael Ellerman
OzLabs, IBM Australia Development Lab
wwweb: http://michael.ellerman.id.au
phone: +61 2 6212 1183 (tie line 70 21183)
We do not inherit the earth from our ancestors,
we borrow it from our children. - S.M.A.R.T Person
[-- Attachment #2: This is a digitally signed message part --]
[-- Type: application/pgp-signature, Size: 189 bytes --]
^ permalink raw reply
* Re: [Cbe-oss-dev] [PATCH] cell: abstract spu management routines
From: Stephen Rothwell @ 2006-11-08 6:28 UTC (permalink / raw)
To: Geoff Levand; +Cc: linuxppc-dev, cbe-oss-dev, Arnd Bergmann
In-Reply-To: <45517325.3090808@am.sony.com>
[-- Attachment #1: Type: text/plain, Size: 608 bytes --]
On Tue, 07 Nov 2006 22:03:17 -0800 Geoff Levand <geoffrey.levand@am.sony.com> wrote:
>
> Michael Ellerman wrote:
> > On Tue, 2006-11-07 at 21:24 -0800, Geoff Levand wrote:
> >> Michael Ellerman wrote:
> >> >> +static struct platform_data *platform_data(struct spu *spu)
> >> >> +{
> >> >> + BUG_ON(!spu->platform_data);
> >> >> + return (struct platform_data*)spu->platform_data;
^^^^^^^^^^^^^^^^^^^^^^^
Since platform_data is a void *, you don't need (or want) this explicit cast.
--
Cheers,
Stephen Rothwell sfr@canb.auug.org.au
http://www.canb.auug.org.au/~sfr/
[-- Attachment #2: Type: application/pgp-signature, Size: 189 bytes --]
^ permalink raw reply
* Re: [PATCH] Changed gianfar device tree definition to make it more flexible
From: Kumar Gala @ 2006-11-08 6:28 UTC (permalink / raw)
To: Andy Fleming; +Cc: linuxppc-dev, Paul Mackerras
In-Reply-To: <Pine.LNX.4.61.0611071707520.6936@ld0175-tx32.am.freescale.net>
>
> diff --git a/Documentation/powerpc/booting-without-of.txt b/
> Documentation/powerpc/booting-without-of.txt
> index 27b457c..bb1a402 100644
> --- a/Documentation/powerpc/booting-without-of.txt
> +++ b/Documentation/powerpc/booting-without-of.txt
> @@ -1193,6 +1193,7 @@ platforms are moved over to use the flat
>
> - device_type : Should be "network"
> - model : Model of the device. Can be "TSEC", "eTSEC", or "FEC"
> + (This is deprecated in favor of the feature bits)
> - compatible : Should be "gianfar"
> - reg : Offset and length of the register set for the device
> - mac-address : List of bytes representing the ethernet
> address of
> @@ -1206,6 +1207,30 @@ platforms are moved over to use the flat
> services interrupts for this device.
> - phy-handle : The phandle for the PHY connected to this ethernet
> controller.
> + - interface : The interface this ethernet is using. Current
> options are:
> + GMII, MII, RGMII, SGMII, TBI, RMII, and RTBI
> +
> + Optional properties (features):
> + - gigabit : Indicates support for 1000 Mbit operation
> + - coalescing : Indicates support for interrupt coalescing
> + - rmon : Indicates support for RMON-style counters
> + - checksumming : Indicates support for hardware TCP/UDP
> checksumming
> + - vlan-insertion : Indicates support for hardware vlan header
> insertion
> + - extended-hash : Indicates support for using the Individual
> + Address Hash registers to extend the Group Address Hash
> registers
> + - padding : Indicates support for padding between the FCB and
> + the frame
> + - filer : Indicates support for the Filer
What exactly does parseL2, L3, L4 actually mean? (what feature is this)
> + - parseL2 : Indicates support for parsing L2 headers
> + - parseL3 : Indicates support for parsing L3 headers
> + - parseL4 : Indicates support for parsing L4 headers
> + - multi-queue : Indicates support for sending and receiving
> + into multiple queues
> +
Shouldn't we have a flag for L2 stashing as well? (83xx TSECs don't
support it since no L2 on the parts :)
>
> + The "eTSEC" model implements all these features, while the
> + "TSEC" model implements only the first 3. The "FEC" has none
> + of these features.
> +
>
> Example:
>
> @@ -1213,12 +1238,16 @@ platforms are moved over to use the flat
> #size-cells = <0>;
> device_type = "network";
> model = "TSEC";
> + gigabit;
> + coalescing;
> + rmon;
> compatible = "gianfar";
> reg = <24000 1000>;
> mac-address = [ 00 E0 0C 00 73 00 ];
> interrupts = <d 3 e 3 12 3>;
> interrupt-parent = <40000>;
> phy-handle = <2452000>
> + interface = "GMII";
> };
>
>
> @@ -1238,6 +1267,7 @@ platforms are moved over to use the flat
> - reg : The ID number for the phy, usually a small integer
> - linux,phandle : phandle for this node; likely referenced by an
> ethernet controller node.
> + - flags : PHY-specific flags (defined by the device driver)
>
>
> Example:
> @@ -1246,6 +1276,7 @@ platforms are moved over to use the flat
> linux,phandle = <2452000>
> interrupt-parent = <40000>;
> interrupts = <35 1>;
> + flags = <0>;
> reg = <0>;
> device_type = "ethernet-phy";
> };
^ permalink raw reply
* [PATCH] powerpc: check for null init_early routine
From: Geoff Levand @ 2006-11-08 8:24 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev
Add a check for a null ppc_md.init_early to allow platforms that
don't require an init_early routine to just set this member to null.
Signed-off-by: Geoff Levand <geoffrey.levand@am.sony.com>
---
Index: cell--common--6/arch/powerpc/kernel/setup_64.c
===================================================================
--- cell--common--6.orig/arch/powerpc/kernel/setup_64.c
+++ cell--common--6/arch/powerpc/kernel/setup_64.c
@@ -392,7 +392,8 @@
* setting up the hash table pointers. It also sets up some interrupt-mapping
* related options that will be used by finish_device_tree()
*/
- ppc_md.init_early();
+ if (ppc_md.init_early)
+ ppc_md.init_early();
/*
* We can discover serial ports now since the above did setup the
^ permalink raw reply
* Re: minor progress with plb_temac v3.00a, EDK 8.2, & 2.6.18.1
From: Pradeep Sampath @ 2006-11-08 8:44 UTC (permalink / raw)
To: robert corley, linuxppc-embedded
In-Reply-To: <20061107183700.62673.qmail@web56307.mail.re3.yahoo.com>
[-- Attachment #1: Type: text/plain, Size: 1350 bytes --]
Robert,
I now created the BSP from scratch and its lot better than attempting to upgrade an existing design. I patched "xilinx_temac" and "xilinx_common" , but i am running into another error. I guess i have to start patching the code all over again.
Please take a look if you can comment on it...
psampath@psampath-test:~/kernel2.6.18$ make ARCH=ppc zImage.initrd
CHK include/linux/version.h
CHK include/linux/utsrelease.h
CC arch/ppc/kernel/asm-offsets.s
In file included from include/asm/ibm4xx.h:54,
from include/asm/io.h:28,
from include/asm/pgtable.h:14,
from include/linux/mm.h:38,
from include/linux/mman.h:14,
from arch/ppc/kernel/asm-offsets.c:19:
arch/ppc/platforms/4xx/xilinx_ml403.h:33: error: two or more data types in declaration of `bd_t'
make[1]: *** [arch/ppc/kernel/asm-offsets.s] Error 1
make: *** [prepare0] Error 2
psampath@psampath-test:~/kernel2.6.18$
-Pradeep
robert corley <rdcorle@yahoo.com> wrote: Pradeep;
I found the process of "uprading" the xapp902 reference design to be troublesome when I removed the GMII loop-back; as
such, I aborted the process and just started from scratch.
I am currently debugging my design and have a functional plb_temac but only at 10Mbps speeds.
-R. Corley
[-- Attachment #2: Type: text/html, Size: 2297 bytes --]
^ permalink raw reply
* [PATCH] cell: replace spu.nid with spu.node
From: Geoff Levand @ 2006-11-08 8:44 UTC (permalink / raw)
To: Arnd Bergmann; +Cc: linuxppc-dev, cbe-oss-dev
Replace the use of the platform specific variable spu.nid with the
platform independednt variable spu.node.
Signed-off-by: Geoff Levand <geoffrey.levand@am.sony.com>
---
Index: cell--common--6/arch/powerpc/platforms/cell/spu_base.c
===================================================================
--- cell--common--6.orig/arch/powerpc/platforms/cell/spu_base.c
+++ cell--common--6/arch/powerpc/platforms/cell/spu_base.c
@@ -810,14 +810,14 @@
return ret;
}
- sysfs_add_device_to_node(&spu->sysdev, spu->nid);
+ sysfs_add_device_to_node(&spu->sysdev, spu->node);
return 0;
}
static void spu_destroy_sysdev(struct spu *spu)
{
- sysfs_remove_device_from_node(&spu->sysdev, spu->nid);
+ sysfs_remove_device_from_node(&spu->sysdev, spu->node);
sysdev_unregister(&spu->sysdev);
}
^ permalink raw reply
* Re: [PATCH] powerpc: force 4k update_flash block and list sizes
From: Arnd Bergmann @ 2006-11-08 9:28 UTC (permalink / raw)
To: linuxppc-dev, michael; +Cc: Paul Mackerras, Michael Neuling
In-Reply-To: <1162960860.20271.13.camel@localhost.localdomain>
On Wednesday 08 November 2006 05:41, Michael Ellerman wrote:
> Just being picky .. but why did you decide to use the slab cache? Does
> it make the code neater? I would have thought you could guarantee 4k
> alignment some other way, and it seems slightly odd to use the slab
> cache for something you only do once ..
There are not so many allocators available. kmalloc does not guarantee
alignment beyond a few bytes and the buddy allocator and vmalloc don't
give you allocations smaller than PAGE_SIZE.
The ehca people had the same problem, and I could imagine there are
others with similar issues. How about adding a special slab allocator
architecture-wide that gives out aligned 4k chunks independent of
page size?
Arnd <>z
^ permalink raw reply
* Mpc860T rebooting problem
From: bharathi kandimalla @ 2006-11-08 10:10 UTC (permalink / raw)
To: linuxppc-embedded
[-- Attachment #1: Type: text/plain, Size: 1048 bytes --]
hi
I am working on powerpc(Mpc860T) with linux-2.4 kernnel,
As I am developping application using spi and with irqs:
For each one millisec I am getting siu interrupt,In the
interrupt handler I have to load frequency(using spi communication)
I am able to write it (I am able load the frequency also)
All other interrupts I am using are cpm interrupts(smc2.timer2,spi),one
siu interrupt for the present ,
I am facing the following problems:
1.system rebooting: case-if i tried to write continuously to externel hardware through spi ,in externel (siu)intrrupt handler,and timer2(cpm)intrrupt handler,
2. if I limited number of times of write to hardware system not getting rebooted.
I observed that the problem occured due to passing of control signals to externel hardware (those are memory mapped signals) in irqs.how can i solve this with getting rebooted.
thanks to all ...
Bharathi
---------------------------------
Sponsored Link
Degrees online in as fast as 1 Yr - MBA, Bachelor's, Master's, Associate - Click now to apply
[-- Attachment #2: Type: text/html, Size: 1306 bytes --]
^ permalink raw reply
* Re: [PATCH 2.6.19 2/4] ehca: hcp_phyp.c: correct page mapping in 64k page mode
From: Christoph Raisch @ 2006-11-08 10:22 UTC (permalink / raw)
To: Roland Dreier; +Cc: linuxppc-dev, linux-kernel, openib-general
In-Reply-To: <aday7qngiuf.fsf@cisco.com>
Roland Dreier wrote on 07.11.2006 20:25:12:
> > - *mapaddr = (u64)(ioremap(physaddr, EHCA_PAGESIZE));
> > + *mapaddr = (u64)ioremap((physaddr & PAGE_MASK), PAGE_SIZE) +
> > + (physaddr & (~PAGE_MASK));
>
> I'm confused -- shouldn't ioremap() do the right thing even if
> physaddr isn't page-aligned? Why is this needed?
>
> - R.
ioremap maps 4k pages on 4k kernels and on 64k pages on 64k kernels. So far
the theory.
This is true for memory.
For mapped PCI or ebus registers things are a bit different.
Some PCI adapters expect that every other 4k page is a new area with
different meaning starts
(some PCI adapters are definetly ehca and mellanox here). The consequence
is you have to map
only 4k instead of 64k, otherwise you'd map 15 other "access areas" are
also mapped.
On POWER the ebus memory is mapped by H_ENTER.
The hypervisor checks for 4k page size on H_ENTER, reason see above.
The nopage handler now does seperate 4k H_ENTERs even for 64k pages in the
ebus area,
therefore we have to register a 64k page on a 64k boundary, and the nopage
triggers the right H_ENTER
as soon as we access the page at the right offset.
We plan to change that as soon as the base kernel can handle mixed
pagesizes in a more official way.
Christop R.
^ permalink raw reply
* Re: [RFC/PATCH 0/7] Powerpc MSI Implementation
From: Eric W. Biederman @ 2006-11-08 10:26 UTC (permalink / raw)
To: michael; +Cc: Greg KH, linuxppc-dev, linux-pci, David S. Miller
In-Reply-To: <1162963101.20271.18.camel@localhost.localdomain>
Michael Ellerman <michael@ellerman.id.au> writes:
>> Oh, and I think your first two patches can be applied now to the tree
>> (header file changes). Any objection to me doing this?
>
> There's a trivial bug in 1/7 (HT #defines), so hold back on that one
> until I resend. The movement of MSI-X #defines is good to go. I also
> sent you the patch to add HT_SUBCAP_OFFSET yesterday that I think is
> ready to merge.
Actually now that I am thinking about it I'm not at all certain about
the HT_SUBCAP_OFFSET patch. The basic issue is that it suggests that
the field that specifies which type of hypertransport capability has a
fixed number of bits. While in reality the encoding is variable
length.
Eric
^ permalink raw reply
* Re: [PATCH] PowerPC: clockevents and HRT support
From: Sergei Shtylyov @ 2006-11-08 14:14 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev, tglx, greg.weeks
In-Reply-To: <1162951594.28571.625.camel@localhost.localdomain>
Hello.
Benjamin Herrenschmidt wrote:
>>>> Whatever. I don't care about that feature. I did my best to solve this
>>>>gracefully.
>>>Very typical of Montavista to not care about doing the right thing.
We also have schedule to follow.
>>Hmmm...
> Yeah, ok, maybe not -everybody- there :-)
I think I'm among the least deserving such compliments here.
> Ben.
WBR, Sergei
^ permalink raw reply
* Re: [PATCH] PowerPC: clockevents and HRT support
From: Sergei Shtylyov @ 2006-11-08 14:21 UTC (permalink / raw)
To: Paul Mackerras; +Cc: tglx, greg.weeks, linuxppc-dev
In-Reply-To: <17745.14911.693171.717979@cargo.ozlabs.ibm.com>
Hello.
Paul Mackerras wrote:
>> Arch-specific accounting hooks which this feature makes use of can't be
>>called from the generic clockevents code.
> Which hooks specifically?
You aren't saying you don't know your own code?
Specifically, it's local account_process_time() function being called
instead of updated_process_times() with CONFIG_VIRT_CPU_ACCOUNTING option on.
> The deterministic accounting is an essential feature; there's no way
> I'll accept a patch which disables it.
I'm not talking you into accepting it in any way, this is just to keep
people informed.
And I left people a choice: they can either have fancy accounting or HRT,
just not both at once. What's wrong with that?
> Paul.
WBR, Sergei
^ permalink raw reply
* Re: [PATCH] adding ROM chips to device tree: respin
From: Sergei Shtylyov @ 2006-11-08 14:27 UTC (permalink / raw)
To: Vitaly Wool; +Cc: linuxppc-embedded
In-Reply-To: <45510B5E.9000104@ru.mvista.com>
Hello, I wrote:
> We could also try using "device_type" or "name" properties to name the
> of_device -- this name doesn't matter much anyway...
Now, after looking thru some code, I think using the "name" prop is indeed
the way to go...
WBR, Sergei
^ permalink raw reply
* Re: [PATCH] Changed gianfar device tree definition to make it more flexible
From: Sergei Shtylyov @ 2006-11-08 16:00 UTC (permalink / raw)
To: Andy Fleming; +Cc: linuxppc-dev, Paul Mackerras
In-Reply-To: <Pine.LNX.4.61.0611071707520.6936@ld0175-tx32.am.freescale.net>
Hello.
Andy Fleming wrote:
> diff --git a/Documentation/powerpc/booting-without-of.txt b/Documentation/powerpc/booting-without-of.txt
> index 27b457c..bb1a402 100644
> --- a/Documentation/powerpc/booting-without-of.txt
> +++ b/Documentation/powerpc/booting-without-of.txt
> @@ -1193,6 +1193,7 @@ platforms are moved over to use the flat
>
> - device_type : Should be "network"
> - model : Model of the device. Can be "TSEC", "eTSEC", or "FEC"
> + (This is deprecated in favor of the feature bits)
> - compatible : Should be "gianfar"
> - reg : Offset and length of the register set for the device
> - mac-address : List of bytes representing the ethernet address of
> @@ -1206,6 +1207,30 @@ platforms are moved over to use the flat
> services interrupts for this device.
> - phy-handle : The phandle for the PHY connected to this ethernet
> controller.
> + - interface : The interface this ethernet is using. Current options are:
> + GMII, MII, RGMII, SGMII, TBI, RMII, and RTBI
> +
> + Optional properties (features):
> + - gigabit : Indicates support for 1000 Mbit operation
There's standard "supported-network-type" property listing supported
speeds/connectors already, why introduce another one?
WBR, Sergei
^ permalink raw reply
* Re: [PATCH] powerpc: force 4k update_flash block and list sizes
From: John Rose @ 2006-11-08 16:07 UTC (permalink / raw)
To: Michael Neuling; +Cc: External List, Paul Mackerras
In-Reply-To: <945.1162960744@neuling.org>
> Arrh, did anything change?
Sorry, attached the wrong thing! That's what I get for trying to submit
code after 10PM :)
The enablement of 64k pages on POWER platforms exposed a quirk in the RTAS
mechanism for updating firmware. RTAS assumes 4k for flash block and list
sizes, and use of any other sizes results in a failure.
This patch changes the rtas_flash module to force the use of 4k memory block
and list sizes when preparing and sending a firmware image to RTAS. It also
changes rtas_flash to use a slab cache to ensure 4k alignment of flash block
data. Such alignment is a documented requirement.
Signed-off-by: John Rose <johnrose@austin.ibm.com>
---
uf_4k-johnrose/arch/powerpc/kernel/rtas_flash.c | 47 ++++++++++++++++++------
1 files changed, 37 insertions(+), 10 deletions(-)
diff -puN arch/powerpc/kernel/rtas_flash.c~uf_4k_alt2 arch/powerpc/kernel/rtas_flash.c
--- uf_4k/arch/powerpc/kernel/rtas_flash.c~uf_4k_alt2 2006-11-06 16:59:27.000000000 -0600
+++ uf_4k-johnrose/arch/powerpc/kernel/rtas_flash.c 2006-11-07 22:29:52.000000000 -0600
@@ -72,6 +72,10 @@
#define VALIDATE_BUF_SIZE 4096
#define RTAS_MSG_MAXLEN 64
+/* Quirk - RTAS requires 4k list length and block size */
+#define RTAS_BLKLIST_LENGTH 4096
+#define RTAS_BLK_SIZE 4096
+
struct flash_block {
char *data;
unsigned long length;
@@ -83,7 +87,7 @@ struct flash_block {
* into a version/length and translate the pointers
* to absolute.
*/
-#define FLASH_BLOCKS_PER_NODE ((PAGE_SIZE - 16) / sizeof(struct flash_block))
+#define FLASH_BLOCKS_PER_NODE ((RTAS_BLKLIST_LENGTH - 16) / sizeof(struct flash_block))
struct flash_block_list {
unsigned long num_blocks;
struct flash_block_list *next;
@@ -96,6 +100,9 @@ struct flash_block_list_header { /* just
static struct flash_block_list_header rtas_firmware_flash_list = {0, NULL};
+/* Use slab cache to guarantee 4k alignment */
+static kmem_cache_t *flash_block_cache = NULL;
+
#define FLASH_BLOCK_LIST_VERSION (1UL)
/* Local copy of the flash block list.
@@ -153,7 +160,7 @@ static int flash_list_valid(struct flash
return FLASH_IMG_NULL_DATA;
}
block_size = f->blocks[i].length;
- if (block_size <= 0 || block_size > PAGE_SIZE) {
+ if (block_size <= 0 || block_size > RTAS_BLK_SIZE) {
return FLASH_IMG_BAD_LEN;
}
image_size += block_size;
@@ -177,9 +184,9 @@ static void free_flash_list(struct flash
while (f) {
for (i = 0; i < f->num_blocks; i++)
- free_page((unsigned long)(f->blocks[i].data));
+ kmem_cache_free(flash_block_cache, f->blocks[i].data);
next = f->next;
- free_page((unsigned long)f);
+ kmem_cache_free(flash_block_cache, f);
f = next;
}
}
@@ -278,6 +285,12 @@ static ssize_t rtas_flash_read(struct fi
return msglen;
}
+/* constructor for flash_block_cache */
+void rtas_block_ctor(void *ptr, kmem_cache_t *cache, unsigned long flags)
+{
+ memset(ptr, 0, RTAS_BLK_SIZE);
+}
+
/* We could be much more efficient here. But to keep this function
* simple we allocate a page to the block list no matter how small the
* count is. If the system is low on memory it will be just as well
@@ -302,7 +315,7 @@ static ssize_t rtas_flash_write(struct f
* proc file
*/
if (uf->flist == NULL) {
- uf->flist = (struct flash_block_list *) get_zeroed_page(GFP_KERNEL);
+ uf->flist = kmem_cache_alloc(flash_block_cache, GFP_KERNEL);
if (!uf->flist)
return -ENOMEM;
}
@@ -313,21 +326,21 @@ static ssize_t rtas_flash_write(struct f
next_free = fl->num_blocks;
if (next_free == FLASH_BLOCKS_PER_NODE) {
/* Need to allocate another block_list */
- fl->next = (struct flash_block_list *)get_zeroed_page(GFP_KERNEL);
+ fl->next = kmem_cache_alloc(flash_block_cache, GFP_KERNEL);
if (!fl->next)
return -ENOMEM;
fl = fl->next;
next_free = 0;
}
- if (count > PAGE_SIZE)
- count = PAGE_SIZE;
- p = (char *)get_zeroed_page(GFP_KERNEL);
+ if (count > RTAS_BLK_SIZE)
+ count = RTAS_BLK_SIZE;
+ p = kmem_cache_alloc(flash_block_cache, GFP_KERNEL);
if (!p)
return -ENOMEM;
if(copy_from_user(p, buffer, count)) {
- free_page((unsigned long)p);
+ kmem_cache_free(flash_block_cache, p);
return -EFAULT;
}
fl->blocks[next_free].data = p;
@@ -791,6 +804,16 @@ int __init rtas_flash_init(void)
goto cleanup;
rtas_flash_term_hook = rtas_flash_firmware;
+
+ flash_block_cache = kmem_cache_create("rtas_flash_cache",
+ RTAS_BLK_SIZE, RTAS_BLK_SIZE, 0,
+ rtas_block_ctor, NULL);
+ if (!flash_block_cache) {
+ printk(KERN_ERR "%s: failed to create block cache\n",
+ __FUNCTION__);
+ rc = -ENOMEM;
+ goto cleanup;
+ }
return 0;
cleanup:
@@ -805,6 +828,10 @@ cleanup:
void __exit rtas_flash_cleanup(void)
{
rtas_flash_term_hook = NULL;
+
+ if (flash_block_cache)
+ kmem_cache_destroy(flash_block_cache);
+
remove_flash_pde(firmware_flash_pde);
remove_flash_pde(firmware_update_pde);
remove_flash_pde(validate_pde);
_
^ permalink raw reply
* [PATCH] powerpc: Add MPC5200 Interrupt Controller support.
From: Nicolas DET @ 2006-11-08 16:14 UTC (permalink / raw)
To: Paul Mackerras; +Cc: ML PPC dev, ML PPC embedded
This patch add MPC52xx Interrupt controller for ARCH=powerpc.
It includes the main code in arch/powerpc/sysdev/ ad well as an header file in
include/asm-powerpc.
Signed-off-by: Nicolas DET <nd@bplan-gmbh.de>
Acked-by: Sylvain Munaut <tnt@246tNt.com>
Acked-by: Grant Likely <grant.likely@secretlab.ca>
---
arch/powerpc/sysdev/Makefile | 1
arch/powerpc/sysdev/mpc52xx_pic.c | 538 +++++++++++++++++++++++++++++++++++++
include/asm-powerpc/mpc52xx.h | 287 ++++++++++++++++++++
3 files changed, 826 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile
index f15af0e..5b87f7b 100644
--- a/arch/powerpc/sysdev/Makefile
+++ b/arch/powerpc/sysdev/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_MMIO_NVRAM) += mmio_nvram.o
obj-$(CONFIG_FSL_SOC) += fsl_soc.o
obj-$(CONFIG_TSI108_BRIDGE) += tsi108_pci.o tsi108_dev.o
obj-$(CONFIG_QUICC_ENGINE) += qe_lib/
+obj-$(CONFIG_PPC_MPC52xx) += mpc52xx_pic.o
ifeq ($(CONFIG_PPC_MERGE),y)
obj-$(CONFIG_PPC_I8259) += i8259.o
diff --git a/arch/powerpc/sysdev/mpc52xx_pic.c b/arch/powerpc/sysdev/mpc52xx_pic.c
new file mode 100644
index 0000000..6df51f0
--- /dev/null
+++ b/arch/powerpc/sysdev/mpc52xx_pic.c
@@ -0,0 +1,538 @@
+/*
+ *
+ * Programmable Interrupt Controller functions for the Freescale MPC52xx.
+ *
+ * Copyright (C) 2006 bplan GmbH
+ *
+ * Based on the code from the 2.4 kernel by
+ * Dale Farnsworth <dfarnsworth@mvista.com> and Kent Borg.
+ *
+ * Copyright (C) 2004 Sylvain Munaut <tnt@246tNt.com>
+ * Copyright (C) 2003 Montavista Software, Inc
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ *
+ */
+
+#undef DEBUG
+
+#include <linux/stddef.h>
+#include <linux/init.h>
+#include <linux/sched.h>
+#include <linux/signal.h>
+#include <linux/stddef.h>
+#include <linux/delay.h>
+#include <linux/irq.h>
+#include <linux/hardirq.h>
+
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <asm/system.h>
+#include <asm/irq.h>
+#include <asm/prom.h>
+#include <asm/mpc52xx.h>
+
+/*
+ *
+*/
+
+static struct mpc52xx_intr __iomem *intr;
+static struct mpc52xx_sdma __iomem *sdma;
+static struct irq_host *mpc52xx_irqhost = NULL;
+
+static unsigned char mpc52xx_map_senses[4] = {
+ IRQ_TYPE_LEVEL_HIGH,
+ IRQ_TYPE_EDGE_RISING,
+ IRQ_TYPE_EDGE_FALLING,
+ IRQ_TYPE_LEVEL_LOW,
+};
+
+/*
+ *
+*/
+
+static inline void io_be_setbit(u32 __iomem * addr, int bitno)
+{
+ out_be32(addr, in_be32(addr) | (1 << bitno));
+}
+
+static inline void io_be_clrbit(u32 __iomem * addr, int bitno)
+{
+ out_be32(addr, in_be32(addr) & ~(1 << bitno));
+}
+
+/*
+ * IRQ[0-3] interrupt irq_chip
+*/
+
+static void mpc52xx_extirq_mask(unsigned int virq)
+{
+ int irq;
+ int l2irq;
+
+ irq = irq_map[virq].hwirq;
+ l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
+
+ pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
+
+ io_be_clrbit(&intr->ctrl, 11 - l2irq);
+}
+
+static void mpc52xx_extirq_unmask(unsigned int virq)
+{
+ int irq;
+ int l2irq;
+
+ irq = irq_map[virq].hwirq;
+ l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
+
+ pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
+
+ io_be_setbit(&intr->ctrl, 11 - l2irq);
+}
+
+static void mpc52xx_extirq_ack(unsigned int virq)
+{
+ int irq;
+ int l2irq;
+
+ irq = irq_map[virq].hwirq;
+ l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
+
+ pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
+
+ io_be_setbit(&intr->ctrl, 27 - l2irq);
+}
+
+static struct irq_chip mpc52xx_extirq_irqchip = {
+ .typename = " MPC52xx IRQ[0-3] ",
+ .mask = mpc52xx_extirq_mask,
+ .unmask = mpc52xx_extirq_unmask,
+ .ack = mpc52xx_extirq_ack,
+};
+
+/*
+ * Main interrupt irq_chip
+*/
+
+static void mpc52xx_main_mask(unsigned int virq)
+{
+ int irq;
+ int l2irq;
+
+ irq = irq_map[virq].hwirq;
+ l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
+
+ pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
+
+ io_be_setbit(&intr->main_mask, 15 - l2irq);
+}
+
+static void mpc52xx_main_unmask(unsigned int virq)
+{
+ int irq;
+ int l2irq;
+
+ irq = irq_map[virq].hwirq;
+ l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
+
+ pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
+
+ io_be_clrbit(&intr->main_mask, 15 - l2irq);
+}
+
+static struct irq_chip mpc52xx_main_irqchip = {
+ .typename = "MPC52xx Main",
+ .mask = mpc52xx_main_mask,
+ .mask_ack = mpc52xx_main_mask,
+ .unmask = mpc52xx_main_unmask,
+};
+
+/*
+ * Peripherals interrupt irq_chip
+*/
+
+static void mpc52xx_periph_mask(unsigned int virq)
+{
+ int irq;
+ int l2irq;
+
+ irq = irq_map[virq].hwirq;
+ l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
+
+ pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
+
+ io_be_setbit(&intr->per_mask, 31 - l2irq);
+}
+
+static void mpc52xx_periph_unmask(unsigned int virq)
+{
+ int irq;
+ int l2irq;
+
+ irq = irq_map[virq].hwirq;
+ l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
+
+ pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
+
+ io_be_clrbit(&intr->per_mask, 31 - l2irq);
+}
+
+static struct irq_chip mpc52xx_periph_irqchip = {
+ .typename = "MPC52xx Peripherals",
+ .mask = mpc52xx_periph_mask,
+ .mask_ack = mpc52xx_periph_mask,
+ .unmask = mpc52xx_periph_unmask,
+};
+
+/*
+ * SDMA interrupt irq_chip
+*/
+
+static void mpc52xx_sdma_mask(unsigned int virq)
+{
+ int irq;
+ int l2irq;
+
+ irq = irq_map[virq].hwirq;
+ l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
+
+ pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
+
+ io_be_setbit(&sdma->IntMask, l2irq);
+}
+
+static void mpc52xx_sdma_unmask(unsigned int virq)
+{
+ int irq;
+ int l2irq;
+
+ irq = irq_map[virq].hwirq;
+ l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
+
+ pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
+
+ io_be_clrbit(&sdma->IntMask, l2irq);
+}
+
+static void mpc52xx_sdma_ack(unsigned int virq)
+{
+ int irq;
+ int l2irq;
+
+ irq = irq_map[virq].hwirq;
+ l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
+
+ pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
+
+ out_be32(&sdma->IntPend, 1 << l2irq);
+}
+
+static struct irq_chip mpc52xx_sdma_irqchip = {
+ .typename = "MPC52xx SDMA",
+ .mask = mpc52xx_sdma_mask,
+ .unmask = mpc52xx_sdma_unmask,
+ .ack = mpc52xx_sdma_ack,
+};
+
+/*
+ * irq_host
+*/
+
+static int mpc52xx_irqhost_match(struct irq_host *h, struct device_node *node)
+{
+ pr_debug("%s: node=%p\n", __func__, node);
+ return mpc52xx_irqhost->host_data == node;
+}
+
+static int mpc52xx_irqhost_xlate(struct irq_host *h, struct device_node *ct,
+ u32 * intspec, unsigned int intsize,
+ irq_hw_number_t * out_hwirq,
+ unsigned int *out_flags)
+{
+ int intrvect_l1;
+ int intrvect_l2;
+ int intrvect_type;
+ int intrvect_linux;
+
+ if (intsize != 3)
+ return -1;
+
+ intrvect_l1 = (int)intspec[0];
+ intrvect_l2 = (int)intspec[1];
+ intrvect_type = (int)intspec[2];
+
+ intrvect_linux =
+ (intrvect_l1 << MPC52xx_IRQ_L1_OFFSET) & MPC52xx_IRQ_L1_MASK;
+ intrvect_linux |=
+ (intrvect_l2 << MPC52xx_IRQ_L2_OFFSET) & MPC52xx_IRQ_L2_MASK;
+
+ pr_debug("return %x, l1=%d, l2=%d\n", intrvect_linux, intrvect_l1,
+ intrvect_l2);
+
+ *out_hwirq = intrvect_linux;
+ *out_flags = mpc52xx_map_senses[intrvect_type];
+
+ return 0;
+}
+
+/*
+ * this function retrieves the correct IRQ type out
+ * of the MPC regs
+ * Only externals IRQs needs this
+*/
+static int mpc52xx_irqx_gettype(int irq)
+{
+ int type;
+ u32 ctrl_reg;
+
+ ctrl_reg = in_be32(&intr->ctrl);
+ type = (ctrl_reg >> (22 - irq * 2)) & 0x3;
+
+ return mpc52xx_map_senses[type];
+}
+
+static int mpc52xx_irqhost_map(struct irq_host *h, unsigned int virq,
+ irq_hw_number_t irq)
+{
+ int l1irq;
+ int l2irq;
+ struct irq_chip *good_irqchip;
+ void *good_handle;
+ int type;
+
+ l1irq = (irq & MPC52xx_IRQ_L1_MASK) >> MPC52xx_IRQ_L1_OFFSET;
+ l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
+
+ /*
+ * Most of ours IRQs will be level low
+ * Only external IRQs on some platform may be others
+ */
+ type = IRQ_TYPE_LEVEL_LOW;
+
+ switch (l1irq) {
+ case MPC52xx_IRQ_L1_CRIT:
+ pr_debug("%s: Critical. l2=%x\n", __func__, l2irq);
+
+ BUG_ON(l2irq != 0);
+
+ type = mpc52xx_irqx_gettype(l2irq);
+ good_irqchip = &mpc52xx_extirq_irqchip;
+ break;
+
+ case MPC52xx_IRQ_L1_MAIN:
+ pr_debug("%s: Main IRQ[1-3] l2=%x\n", __func__, l2irq);
+
+ if ((l2irq >= 1) && (l2irq <= 3)) {
+ type = mpc52xx_irqx_gettype(l2irq);
+ good_irqchip = &mpc52xx_extirq_irqchip;
+ } else {
+ good_irqchip = &mpc52xx_main_irqchip;
+ }
+ break;
+
+ case MPC52xx_IRQ_L1_PERP:
+ pr_debug("%s: Peripherals. l2=%x\n", __func__, l2irq);
+ good_irqchip = &mpc52xx_periph_irqchip;
+ break;
+
+ case MPC52xx_IRQ_L1_SDMA:
+ pr_debug("%s: SDMA. l2=%x\n", __func__, l2irq);
+ good_irqchip = &mpc52xx_sdma_irqchip;
+ break;
+
+ default:
+ pr_debug("%s: Error, unknown L1 IRQ (0x%x)\n", __func__, l1irq);
+ printk(KERN_ERR "Unknow IRQ!\n");
+ return -EINVAL;
+ }
+
+ switch (type) {
+ case IRQ_TYPE_EDGE_FALLING:
+ case IRQ_TYPE_EDGE_RISING:
+ good_handle = handle_edge_irq;
+ break;
+ default:
+ good_handle = handle_level_irq;
+ }
+
+ set_irq_chip_and_handler(virq, good_irqchip, good_handle);
+
+ pr_debug("%s: virq=%x, hw=%x. type=%x\n", __func__, virq,
+ (int)irq, type);
+
+ return 0;
+}
+
+static struct irq_host_ops mpc52xx_irqhost_ops = {
+ .match = mpc52xx_irqhost_match,
+ .xlate = mpc52xx_irqhost_xlate,
+ .map = mpc52xx_irqhost_map,
+};
+
+/*
+ * init (public)
+*/
+
+void __init mpc52xx_init_irq(void)
+{
+ struct device_node *picnode = NULL;
+ int picnode_regsize;
+ u32 picnode_regoffset;
+
+ struct device_node *sdmanode = NULL;
+ int sdmanode_regsize;
+ u32 sdmanode_regoffset;
+
+ u64 size64;
+ int flags;
+
+ u32 intr_ctrl;
+
+ picnode = of_find_compatible_node(NULL, "interrupt-controller",
+ "mpc5200-pic");
+ if (picnode == NULL) {
+ printk(KERN_ERR "MPC52xx PIC: "
+ "Unable to find the interrupt controller "
+ "in the OpenFirmware device tree\n");
+ goto end;
+ }
+
+ sdmanode = of_find_compatible_node(NULL, "dma-controller",
+ "mpc5200-bestcomm");
+ if (sdmanode == NULL) {
+ printk(KERN_ERR "MPC52xx PIC"
+ "Unable to find the Bestcomm DMA controller device "
+ "in the OpenFirmware device tree\n");
+ goto end;
+ }
+
+ /* Retrieve PIC ressources */
+ picnode_regoffset = (u32) of_get_address(picnode, 0, &size64, &flags);
+ if (picnode_regoffset == 0) {
+ printk(KERN_ERR "MPC52xx PIC"
+ "Unable to get the interrupt controller address\n");
+ goto end;
+ }
+
+ picnode_regoffset =
+ of_translate_address(picnode, (u32 *) picnode_regoffset);
+ picnode_regsize = (int)size64;
+
+ /* Retrieve SDMA ressources */
+ sdmanode_regoffset = (u32) of_get_address(sdmanode, 0, &size64, &flags);
+ if (sdmanode_regoffset == 0) {
+ printk(KERN_ERR "MPC52xx PIC: "
+ "Unable to get the Bestcomm DMA controller address\n");
+ goto end;
+ }
+
+ sdmanode_regoffset =
+ of_translate_address(sdmanode, (u32 *) sdmanode_regoffset);
+ sdmanode_regsize = (int)size64;
+
+ /* Remap the necessary zones */
+ intr = ioremap(picnode_regoffset, picnode_regsize);
+ if (intr == NULL) {
+ printk(KERN_ERR "MPC52xx PIC: "
+ "Unable to ioremap interrupt controller registers!\n");
+ goto end;
+ }
+
+ sdma = ioremap(sdmanode_regoffset, sdmanode_regsize);
+ if (sdma == NULL) {
+ iounmap(intr);
+ printk(KERN_ERR "MPC52xx PIC: "
+ "Unable to ioremap Bestcomm DMA registers!\n");
+ goto end;
+ }
+
+ printk(KERN_INFO "MPC52xx PIC: MPC52xx PIC Remapped at 0x%8.8x\n",
+ picnode_regoffset);
+ printk(KERN_INFO "MPC52xx PIC: MPC52xx SDMA Remapped at 0x%8.8x\n",
+ sdmanode_regoffset);
+
+ /* Disable all interrupt sources. */
+ out_be32(&sdma->IntPend, 0xffffffff); /* 1 means clear pending */
+ out_be32(&sdma->IntMask, 0xffffffff); /* 1 means disabled */
+ out_be32(&intr->per_mask, 0x7ffffc00); /* 1 means disabled */
+ out_be32(&intr->main_mask, 0x00010fff); /* 1 means disabled */
+ intr_ctrl = in_be32(&intr->ctrl);
+ intr_ctrl &= 0x00ff0000; /* Keeps IRQ[0-3] config */
+ intr_ctrl |= 0x0f000000 | /* clear IRQ 0-3 */
+ 0x00001000 | /* MEE master external enable */
+ 0x00000000 | /* 0 means disable IRQ 0-3 */
+ 0x00000001; /* CEb route critical normally */
+ out_be32(&intr->ctrl, intr_ctrl);
+
+ /* Zero a bunch of the priority settings. */
+ out_be32(&intr->per_pri1, 0);
+ out_be32(&intr->per_pri2, 0);
+ out_be32(&intr->per_pri3, 0);
+ out_be32(&intr->main_pri1, 0);
+ out_be32(&intr->main_pri2, 0);
+
+ /*
+ * As last step, add an irq host to translate the real
+ * hw irq information provided by the ofw to linux virq
+ */
+
+ mpc52xx_irqhost =
+ irq_alloc_host(IRQ_HOST_MAP_LINEAR, MPC52xx_IRQ_HIGHTESTHWIRQ,
+ &mpc52xx_irqhost_ops, -1);
+
+ if (mpc52xx_irqhost) {
+ mpc52xx_irqhost->host_data = picnode;
+ printk(KERN_INFO "MPC52xx PIC is up and running!\n");
+ } else {
+ printk(KERN_ERR
+ "MPC52xx PIC: Unable to allocate the IRQ host\n");
+ }
+
+end:
+ of_node_put(picnode);
+ of_node_put(sdmanode);
+}
+
+/*
+ * get_irq (public)
+*/
+unsigned int mpc52xx_get_irq(void)
+{
+ u32 status;
+ int irq = NO_IRQ_IGNORE;
+
+ status = in_be32(&intr->enc_status);
+ if (status & 0x00000400) { /* critical */
+ irq = (status >> 8) & 0x3;
+ if (irq == 2) /* high priority peripheral */
+ goto peripheral;
+ irq |= (MPC52xx_IRQ_L1_CRIT << MPC52xx_IRQ_L1_OFFSET) &
+ MPC52xx_IRQ_L1_MASK;
+ } else if (status & 0x00200000) { /* main */
+ irq = (status >> 16) & 0x1f;
+ if (irq == 4) /* low priority peripheral */
+ goto peripheral;
+ irq |= (MPC52xx_IRQ_L1_MAIN << MPC52xx_IRQ_L1_OFFSET) &
+ MPC52xx_IRQ_L1_MASK;
+ } else if (status & 0x20000000) { /* peripheral */
+ peripheral:
+ irq = (status >> 24) & 0x1f;
+ if (irq == 0) { /* bestcomm */
+ status = in_be32(&sdma->IntPend);
+ irq = ffs(status) - 1;
+ irq |= (MPC52xx_IRQ_L1_SDMA << MPC52xx_IRQ_L1_OFFSET) &
+ MPC52xx_IRQ_L1_MASK;
+ } else
+ irq |= (MPC52xx_IRQ_L1_PERP << MPC52xx_IRQ_L1_OFFSET) &
+ MPC52xx_IRQ_L1_MASK;
+ }
+
+ pr_debug("%s: irq=%x. virq=%d\n", __func__, irq,
+ irq_linear_revmap(mpc52xx_irqhost, irq));
+
+ return irq_linear_revmap(mpc52xx_irqhost, irq);
+}
+
diff --git a/include/asm-powerpc/mpc52xx.h b/include/asm-powerpc/mpc52xx.h
new file mode 100644
index 0000000..e9aa622
--- /dev/null
+++ b/include/asm-powerpc/mpc52xx.h
@@ -0,0 +1,287 @@
+/*
+ * Prototypes, etc. for the Freescale MPC52xx embedded cpu chips
+ * May need to be cleaned as the port goes on ...
+ *
+ * Copyright (C) 2004-2005 Sylvain Munaut <tnt@246tNt.com>
+ * Copyright (C) 2003 MontaVista, Software, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#ifndef __ASM_POWERPC_MPC52xx_H__
+#define __ASM_POWERPC_MPC52xx_H__
+
+#ifndef __ASSEMBLY__
+#include <asm/types.h>
+#include <asm/prom.h>
+#endif /* __ASSEMBLY__ */
+
+
+/* ======================================================================== */
+/* HW IRQ mapping */
+/* ======================================================================== */
+
+#define MPC52xx_IRQ_L1_CRIT (0)
+#define MPC52xx_IRQ_L1_MAIN (1)
+#define MPC52xx_IRQ_L1_PERP (2)
+#define MPC52xx_IRQ_L1_SDMA (3)
+
+#define MPC52xx_IRQ_L1_OFFSET (6)
+#define MPC52xx_IRQ_L1_MASK (0xc0)
+
+#define MPC52xx_IRQ_L2_OFFSET (0)
+#define MPC52xx_IRQ_L2_MASK (0x3f)
+
+#define MPC52xx_IRQ_HIGHTESTHWIRQ (0xd0)
+
+
+/* ======================================================================== */
+/* Structures mapping of some unit register set */
+/* ======================================================================== */
+
+#ifndef __ASSEMBLY__
+
+/* Interrupt controller Register set */
+struct mpc52xx_intr {
+ u32 per_mask; /* INTR + 0x00 */
+ u32 per_pri1; /* INTR + 0x04 */
+ u32 per_pri2; /* INTR + 0x08 */
+ u32 per_pri3; /* INTR + 0x0c */
+ u32 ctrl; /* INTR + 0x10 */
+ u32 main_mask; /* INTR + 0x14 */
+ u32 main_pri1; /* INTR + 0x18 */
+ u32 main_pri2; /* INTR + 0x1c */
+ u32 reserved1; /* INTR + 0x20 */
+ u32 enc_status; /* INTR + 0x24 */
+ u32 crit_status; /* INTR + 0x28 */
+ u32 main_status; /* INTR + 0x2c */
+ u32 per_status; /* INTR + 0x30 */
+ u32 reserved2; /* INTR + 0x34 */
+ u32 per_error; /* INTR + 0x38 */
+};
+
+/* Memory Mapping Control */
+struct mpc52xx_mmap_ctl {
+ u32 mbar; /* MMAP_CTRL + 0x00 */
+
+ u32 cs0_start; /* MMAP_CTRL + 0x04 */
+ u32 cs0_stop; /* MMAP_CTRL + 0x08 */
+ u32 cs1_start; /* MMAP_CTRL + 0x0c */
+ u32 cs1_stop; /* MMAP_CTRL + 0x10 */
+ u32 cs2_start; /* MMAP_CTRL + 0x14 */
+ u32 cs2_stop; /* MMAP_CTRL + 0x18 */
+ u32 cs3_start; /* MMAP_CTRL + 0x1c */
+ u32 cs3_stop; /* MMAP_CTRL + 0x20 */
+ u32 cs4_start; /* MMAP_CTRL + 0x24 */
+ u32 cs4_stop; /* MMAP_CTRL + 0x28 */
+ u32 cs5_start; /* MMAP_CTRL + 0x2c */
+ u32 cs5_stop; /* MMAP_CTRL + 0x30 */
+
+ u32 sdram0; /* MMAP_CTRL + 0x34 */
+ u32 sdram1; /* MMAP_CTRL + 0X38 */
+
+ u32 reserved[4]; /* MMAP_CTRL + 0x3c .. 0x48 */
+
+ u32 boot_start; /* MMAP_CTRL + 0x4c */
+ u32 boot_stop; /* MMAP_CTRL + 0x50 */
+
+ u32 ipbi_ws_ctrl; /* MMAP_CTRL + 0x54 */
+
+ u32 cs6_start; /* MMAP_CTRL + 0x58 */
+ u32 cs6_stop; /* MMAP_CTRL + 0x5c */
+ u32 cs7_start; /* MMAP_CTRL + 0x60 */
+ u32 cs7_stop; /* MMAP_CTRL + 0x64 */
+};
+
+/* SDRAM control */
+struct mpc52xx_sdram {
+ u32 mode; /* SDRAM + 0x00 */
+ u32 ctrl; /* SDRAM + 0x04 */
+ u32 config1; /* SDRAM + 0x08 */
+ u32 config2; /* SDRAM + 0x0c */
+};
+
+/* SDMA */
+struct mpc52xx_sdma {
+ u32 taskBar; /* SDMA + 0x00 */
+ u32 currentPointer; /* SDMA + 0x04 */
+ u32 endPointer; /* SDMA + 0x08 */
+ u32 variablePointer; /* SDMA + 0x0c */
+
+ u8 IntVect1; /* SDMA + 0x10 */
+ u8 IntVect2; /* SDMA + 0x11 */
+ u16 PtdCntrl; /* SDMA + 0x12 */
+
+ u32 IntPend; /* SDMA + 0x14 */
+ u32 IntMask; /* SDMA + 0x18 */
+
+ u16 tcr[16]; /* SDMA + 0x1c .. 0x3a */
+
+ u8 ipr[32]; /* SDMA + 0x3c .. 0x5b */
+
+ u32 cReqSelect; /* SDMA + 0x5c */
+ u32 task_size0; /* SDMA + 0x60 */
+ u32 task_size1; /* SDMA + 0x64 */
+ u32 MDEDebug; /* SDMA + 0x68 */
+ u32 ADSDebug; /* SDMA + 0x6c */
+ u32 Value1; /* SDMA + 0x70 */
+ u32 Value2; /* SDMA + 0x74 */
+ u32 Control; /* SDMA + 0x78 */
+ u32 Status; /* SDMA + 0x7c */
+ u32 PTDDebug; /* SDMA + 0x80 */
+};
+
+/* GPT */
+struct mpc52xx_gpt {
+ u32 mode; /* GPTx + 0x00 */
+ u32 count; /* GPTx + 0x04 */
+ u32 pwm; /* GPTx + 0x08 */
+ u32 status; /* GPTx + 0X0c */
+};
+
+/* GPIO */
+struct mpc52xx_gpio {
+ u32 port_config; /* GPIO + 0x00 */
+ u32 simple_gpioe; /* GPIO + 0x04 */
+ u32 simple_ode; /* GPIO + 0x08 */
+ u32 simple_ddr; /* GPIO + 0x0c */
+ u32 simple_dvo; /* GPIO + 0x10 */
+ u32 simple_ival; /* GPIO + 0x14 */
+ u8 outo_gpioe; /* GPIO + 0x18 */
+ u8 reserved1[3]; /* GPIO + 0x19 */
+ u8 outo_dvo; /* GPIO + 0x1c */
+ u8 reserved2[3]; /* GPIO + 0x1d */
+ u8 sint_gpioe; /* GPIO + 0x20 */
+ u8 reserved3[3]; /* GPIO + 0x21 */
+ u8 sint_ode; /* GPIO + 0x24 */
+ u8 reserved4[3]; /* GPIO + 0x25 */
+ u8 sint_ddr; /* GPIO + 0x28 */
+ u8 reserved5[3]; /* GPIO + 0x29 */
+ u8 sint_dvo; /* GPIO + 0x2c */
+ u8 reserved6[3]; /* GPIO + 0x2d */
+ u8 sint_inten; /* GPIO + 0x30 */
+ u8 reserved7[3]; /* GPIO + 0x31 */
+ u16 sint_itype; /* GPIO + 0x34 */
+ u16 reserved8; /* GPIO + 0x36 */
+ u8 gpio_control; /* GPIO + 0x38 */
+ u8 reserved9[3]; /* GPIO + 0x39 */
+ u8 sint_istat; /* GPIO + 0x3c */
+ u8 sint_ival; /* GPIO + 0x3d */
+ u8 bus_errs; /* GPIO + 0x3e */
+ u8 reserved10; /* GPIO + 0x3f */
+};
+
+#define MPC52xx_GPIO_PSC_CONFIG_UART_WITHOUT_CD 4
+#define MPC52xx_GPIO_PSC_CONFIG_UART_WITH_CD 5
+#define MPC52xx_GPIO_PCI_DIS (1<<15)
+
+/* GPIO with WakeUp*/
+struct mpc52xx_gpio_wkup {
+ u8 wkup_gpioe; /* GPIO_WKUP + 0x00 */
+ u8 reserved1[3]; /* GPIO_WKUP + 0x03 */
+ u8 wkup_ode; /* GPIO_WKUP + 0x04 */
+ u8 reserved2[3]; /* GPIO_WKUP + 0x05 */
+ u8 wkup_ddr; /* GPIO_WKUP + 0x08 */
+ u8 reserved3[3]; /* GPIO_WKUP + 0x09 */
+ u8 wkup_dvo; /* GPIO_WKUP + 0x0C */
+ u8 reserved4[3]; /* GPIO_WKUP + 0x0D */
+ u8 wkup_inten; /* GPIO_WKUP + 0x10 */
+ u8 reserved5[3]; /* GPIO_WKUP + 0x11 */
+ u8 wkup_iinten; /* GPIO_WKUP + 0x14 */
+ u8 reserved6[3]; /* GPIO_WKUP + 0x15 */
+ u16 wkup_itype; /* GPIO_WKUP + 0x18 */
+ u8 reserved7[2]; /* GPIO_WKUP + 0x1A */
+ u8 wkup_maste; /* GPIO_WKUP + 0x1C */
+ u8 reserved8[3]; /* GPIO_WKUP + 0x1D */
+ u8 wkup_ival; /* GPIO_WKUP + 0x20 */
+ u8 reserved9[3]; /* GPIO_WKUP + 0x21 */
+ u8 wkup_istat; /* GPIO_WKUP + 0x24 */
+ u8 reserved10[3]; /* GPIO_WKUP + 0x25 */
+};
+
+/* XLB Bus control */
+struct mpc52xx_xlb {
+ u8 reserved[0x40];
+ u32 config; /* XLB + 0x40 */
+ u32 version; /* XLB + 0x44 */
+ u32 status; /* XLB + 0x48 */
+ u32 int_enable; /* XLB + 0x4c */
+ u32 addr_capture; /* XLB + 0x50 */
+ u32 bus_sig_capture; /* XLB + 0x54 */
+ u32 addr_timeout; /* XLB + 0x58 */
+ u32 data_timeout; /* XLB + 0x5c */
+ u32 bus_act_timeout; /* XLB + 0x60 */
+ u32 master_pri_enable; /* XLB + 0x64 */
+ u32 master_priority; /* XLB + 0x68 */
+ u32 base_address; /* XLB + 0x6c */
+ u32 snoop_window; /* XLB + 0x70 */
+};
+
+#define MPC52xx_XLB_CFG_PLDIS (1 << 31)
+#define MPC52xx_XLB_CFG_SNOOP (1 << 15)
+
+/* Clock Distribution control */
+struct mpc52xx_cdm {
+ u32 jtag_id; /* CDM + 0x00 reg0 read only */
+ u32 rstcfg; /* CDM + 0x04 reg1 read only */
+ u32 breadcrumb; /* CDM + 0x08 reg2 */
+
+ u8 mem_clk_sel; /* CDM + 0x0c reg3 byte0 */
+ u8 xlb_clk_sel; /* CDM + 0x0d reg3 byte1 read only */
+ u8 ipb_clk_sel; /* CDM + 0x0e reg3 byte2 */
+ u8 pci_clk_sel; /* CDM + 0x0f reg3 byte3 */
+
+ u8 ext_48mhz_en; /* CDM + 0x10 reg4 byte0 */
+ u8 fd_enable; /* CDM + 0x11 reg4 byte1 */
+ u16 fd_counters; /* CDM + 0x12 reg4 byte2,3 */
+
+ u32 clk_enables; /* CDM + 0x14 reg5 */
+
+ u8 osc_disable; /* CDM + 0x18 reg6 byte0 */
+ u8 reserved0[3]; /* CDM + 0x19 reg6 byte1,2,3 */
+
+ u8 ccs_sleep_enable; /* CDM + 0x1c reg7 byte0 */
+ u8 osc_sleep_enable; /* CDM + 0x1d reg7 byte1 */
+ u8 reserved1; /* CDM + 0x1e reg7 byte2 */
+ u8 ccs_qreq_test; /* CDM + 0x1f reg7 byte3 */
+
+ u8 soft_reset; /* CDM + 0x20 u8 byte0 */
+ u8 no_ckstp; /* CDM + 0x21 u8 byte0 */
+ u8 reserved2[2]; /* CDM + 0x22 u8 byte1,2,3 */
+
+ u8 pll_lock; /* CDM + 0x24 reg9 byte0 */
+ u8 pll_looselock; /* CDM + 0x25 reg9 byte1 */
+ u8 pll_sm_lockwin; /* CDM + 0x26 reg9 byte2 */
+ u8 reserved3; /* CDM + 0x27 reg9 byte3 */
+
+ u16 reserved4; /* CDM + 0x28 reg10 byte0,1 */
+ u16 mclken_div_psc1; /* CDM + 0x2a reg10 byte2,3 */
+
+ u16 reserved5; /* CDM + 0x2c reg11 byte0,1 */
+ u16 mclken_div_psc2; /* CDM + 0x2e reg11 byte2,3 */
+
+ u16 reserved6; /* CDM + 0x30 reg12 byte0,1 */
+ u16 mclken_div_psc3; /* CDM + 0x32 reg12 byte2,3 */
+
+ u16 reserved7; /* CDM + 0x34 reg13 byte0,1 */
+ u16 mclken_div_psc6; /* CDM + 0x36 reg13 byte2,3 */
+};
+
+#endif /* __ASSEMBLY__ */
+
+
+/* ========================================================================= */
+/* Prototypes for MPC52xx sysdev */
+/* ========================================================================= */
+
+#ifndef __ASSEMBLY__
+
+extern void mpc52xx_init_irq(void);
+extern unsigned int mpc52xx_get_irq(void);
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __ASM_POWERPC_MPC52xx_H__ */
+
--
1.4.2
^ permalink raw reply related
* [PATCH] powerpc iseries link error in allmodconfig
From: Judith Lebzelter @ 2006-11-08 17:34 UTC (permalink / raw)
To: linuxppc-dev; +Cc: sfr, paulus, linux-kernel
Choose rpa_vscsi.c over iseries_vscsi.c when building both
pseries and iseries. This fixes a link error.
Signed-off-by: Judith Lebzelter <judith@osdl.org>
---
Index: linux/drivers/scsi/ibmvscsi/Makefile
===================================================================
--- linux.orig/drivers/scsi/ibmvscsi/Makefile 2006-11-06 16:52:09.000000000 -0800
+++ linux/drivers/scsi/ibmvscsi/Makefile 2006-11-07 09:35:34.019969437 -0800
@@ -1,7 +1,9 @@
obj-$(CONFIG_SCSI_IBMVSCSI) += ibmvscsic.o
ibmvscsic-y += ibmvscsi.o
+ifndef CONFIG_PPC_PSERIES
ibmvscsic-$(CONFIG_PPC_ISERIES) += iseries_vscsi.o
+endif
ibmvscsic-$(CONFIG_PPC_PSERIES) += rpa_vscsi.o
obj-$(CONFIG_SCSI_IBMVSCSIS) += ibmvstgt.o
^ permalink raw reply
* [PATCH] client-architecture termination
From: Jake Moilanen @ 2006-11-08 20:12 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linux-ppc
Firmware is crashing during CAS parsing. It appears that a portion of
Will's patch got dropped.
http://patchwork.ozlabs.org/linuxppc/patch?id=6768
Signed-off-by: Jake Moilanen <moilanen@austin.ibm.com>
arch/powerpc/kernel/prom_init.c | 1 +
1 files changed, 1 insertion(+)
Index: 2.6/arch/powerpc/kernel/prom_init.c
===================================================================
--- 2.6.orig/arch/powerpc/kernel/prom_init.c
+++ 2.6/arch/powerpc/kernel/prom_init.c
@@ -649,6 +649,7 @@ static unsigned char ibm_architecture_ve
W(0xfffe0000), W(0x003a0000), /* POWER5/POWER5+ */
W(0xffff0000), W(0x003e0000), /* POWER6 */
W(0xfffffffe), W(0x0f000001), /* all 2.04-compliant and earlier */
+ W(0x00000000), W(0xffffffff), /* Terminator-list-entry */
5 - 1, /* 5 option vectors */
/* option vector 1: processor architectures supported */
^ permalink raw reply
* Re: [RFC/PATCH 5/7] RTAS MSI implementation
From: Jake Moilanen @ 2006-11-08 20:16 UTC (permalink / raw)
To: Michael Ellerman
Cc: Greg Kroah-Hartman, linuxppc-dev, Eric W. Biederman, linux-pci,
David S. Miller
In-Reply-To: <20061107072126.2EE7167CC6@ozlabs.org>
On Tue, 2006-11-07 at 18:21 +1100, Michael Ellerman wrote:
> Powerpc MSI support via RTAS. Based on Jake's code.
>
Missing the CAS flags to indicate to firmware that we support MSI.
Signed-off-by: Jake Moilanen <moilanen@austin.ibm.com>
Index: git/arch/powerpc/kernel/prom_init.c
===================================================================
--- git.orig/arch/powerpc/kernel/prom_init.c
+++ git/arch/powerpc/kernel/prom_init.c
@@ -634,6 +634,12 @@ static void __init early_cmdline_parse(v
/* ibm,dynamic-reconfiguration-memory property supported */
#define OV5_DRCONF_MEMORY 0x20
#define OV5_LARGE_PAGES 0x10 /* large pages supported */
+/* PCIe/MSI support. Without MSI full PCIe is not supported */
+#ifdef CONFIG_PCI_MSI
+#define OV5_MSI 0x01 /* PCIe/MSI supported */
+#else
+#define OV5_MSI 0x00
+#endif
/*
* The architecture vector has an array of PVR mask/value pairs,
@@ -677,7 +683,7 @@ static unsigned char ibm_architecture_ve
/* option vector 5: PAPR/OF options */
3 - 1, /* length */
0, /* don't ignore, don't halt */
- OV5_LPAR | OV5_SPLPAR | OV5_LARGE_PAGES,
+ OV5_LPAR | OV5_SPLPAR | OV5_LARGE_PAGES | OV5_MSI,
};
/* Old method - ELF header with PT_NOTE sections */
^ permalink raw reply
* [PATCH] PowerPC: dynamic tick support
From: Sergei Shtylyov @ 2006-11-08 20:37 UTC (permalink / raw)
To: tglx; +Cc: linuxppc-dev, greg.weeks
Add dynamic tick support for PowerPC.
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
---
This patch is reworked against 2.6.18-hrt-dyntick2 patchset.
Known issues:
1) with 2.6.18-hrt-dyntick2, dynamic tick mode causes bootup slowdown after the
HRT mode is entered (it seems to return to normal shortly);
2) with 2.6.18-rt7 (plus an extra patch to make it actually working :-) in the
kernel preemption mode other than RT, that slowdown seems permanent (this
was not happening with 2.6.18-rt6).
I don't have time to investigate now, so anybody interested is welcome to...
or I may even return to this if/when the time permits. :-)
arch/powerpc/kernel/idle.c | 4 ++++
1 files changed, 4 insertions(+)
Index: linux-2.6/arch/powerpc/kernel/idle.c
===================================================================
--- linux-2.6.orig/arch/powerpc/kernel/idle.c
+++ linux-2.6/arch/powerpc/kernel/idle.c
@@ -49,6 +49,8 @@ void cpu_idle(void)
set_thread_flag(TIF_POLLING_NRFLAG);
while (1) {
+ hrtimer_stop_sched_tick();
+
while (!need_resched() && !cpu_should_die()) {
ppc64_runlatch_off();
@@ -82,6 +84,8 @@ void cpu_idle(void)
ppc64_runlatch_on();
if (cpu_should_die())
cpu_die();
+
+ hrtimer_restart_sched_tick();
preempt_enable_no_resched();
schedule();
preempt_disable();
^ permalink raw reply
* Re: [PATCH 2.6.19 2/4] ehca: hcp_phyp.c: correct page mapping in 64k page mode
From: Roland Dreier @ 2006-11-08 22:06 UTC (permalink / raw)
To: Christoph Raisch; +Cc: linuxppc-dev, linux-kernel, openib-general
In-Reply-To: <OF60EFC2CD.F8FB1D23-ONC1257220.00315F90-C1257220.0038B8E3@de.ibm.com>
> We plan to change that as soon as the base kernel can handle mixed
> pagesizes in a more official way.
OK, so this is just a temporary workaround for powerpc's broken ioremap()?
I'll apply for 2.6.19, and I hope we can back this out in 2.6.20.
- R.
^ permalink raw reply
* Re: Freescale combined ethernet driver
From: Jim Heck @ 2006-11-08 22:00 UTC (permalink / raw)
To: robin.gilks; +Cc: ppc embedded list
In-Reply-To: <45515913.3080206@tait.co.nz>
Assuming you have a filesystem and can get some software onto it (with
the network not up...), the package 'iproute' contains the 'ip' tool
that would quickly show you the name of the device using the command.
ip link show
# ip link show
1: lo: <LOOPBACK,UP,10000> mtu 16436 qdisc noqueue
link/loopback 00:00:00:00:00:00 brd 00:00:00:00:00:00
2: eth0: <BROADCAST,MULTICAST,UP,10000> mtu 1500 qdisc pfifo_fast qlen 1000
link/ether 00:0b:cd:01:d0:6b brd ff:ff:ff:ff:ff:ff
3: eth1: <NO-CARRIER,BROADCAST,MULTICAST,UP> mtu 1500 qdisc pfifo_fast
qlen 1000 link/ether 00:01:02:48:4d:41 brd ff:ff:ff:ff:ff:ff
4: sit0: <NOARP> mtu 1480 qdisc noop
link/sit 0.0.0.0 brd 0.0.0.0
-Jim
Robin Gilks wrote:
> OK - I give up - whats the name of the device?
>
> I've tried eth0, fsl-cpm-fec0 (and other combinations) with a
> commandline of the form:
>
> ip=172.25.206.113:172.25.140.15::255.255.0.0:unset:fsl-cpm-fec0:off \
> panic=1 console=ttyCPM0
>
> and I get the following errors:
> [ 37.249708] TCP bic registered
> [ 37.255389] Initializing IPsec netlink socket
> [ 37.264134] NET: Registered protocol family 1
> [ 37.272673] NET: Registered protocol family 17
> [ 37.281436] NET: Registered protocol family 15
> [ 37.796233] IP-Config: Device `fsl-cpm-fec0' not found.
> [ 37.807814] Looking up port of RPC 100003/2 on 172.25.140.15
> [ 37.819328] portmap: RPC call returned error 101
>
> This is on an 859T CPU so its a CPM1 and I'm using the single SCC
> channel as a serial UART.
>
>
^ permalink raw reply
* Re: [PATCH] client-architecture termination
From: Paul Mackerras @ 2006-11-08 22:08 UTC (permalink / raw)
To: Jake Moilanen; +Cc: linux-ppc
In-Reply-To: <1163016748.9913.273.camel@goblue>
Jake Moilanen writes:
> Firmware is crashing during CAS parsing. It appears that a portion of
> Will's patch got dropped.
Indeed it got dropped, because it would make the contents of our
ibm_architecture_vec incorrect according to PAPR. The platform
architects confirmed some time ago that what we have is correct, and
the bug is in firmware - and this was communicated to the firmware
developers.
This came up a while ago; I'm surprised that firmware hasn't fixed
their bug yet. What firmware level are you seeing this problem with?
Paul.
^ permalink raw reply
* Re: [PATCH] powerpc: force 4k update_flash block and list sizes
From: Michael Ellerman @ 2006-11-08 22:40 UTC (permalink / raw)
To: Arnd Bergmann; +Cc: linuxppc-dev, Paul Mackerras, Michael Neuling
In-Reply-To: <200611081028.32038.arnd@arndb.de>
[-- Attachment #1: Type: text/plain, Size: 1376 bytes --]
On Wed, 2006-11-08 at 10:28 +0100, Arnd Bergmann wrote:
> On Wednesday 08 November 2006 05:41, Michael Ellerman wrote:
> > Just being picky .. but why did you decide to use the slab cache? Does
> > it make the code neater? I would have thought you could guarantee 4k
> > alignment some other way, and it seems slightly odd to use the slab
> > cache for something you only do once ..
>
> There are not so many allocators available. kmalloc does not guarantee
> alignment beyond a few bytes and the buddy allocator and vmalloc don't
> give you allocations smaller than PAGE_SIZE.
Yeah, I assumed kmalloc aligned on the size of the allocation, but it
doesn't looking at the code. We could set ARCH_KMALLOC_MINALIGN to 4k,
but that aligns all caches which is probably not what we want.
> The ehca people had the same problem, and I could imagine there are
> others with similar issues. How about adding a special slab allocator
> architecture-wide that gives out aligned 4k chunks independent of
> page size?
Yeah that sounds like a plan, I'm sure there's other code around that
could use it.
cheers
--
Michael Ellerman
OzLabs, IBM Australia Development Lab
wwweb: http://michael.ellerman.id.au
phone: +61 2 6212 1183 (tie line 70 21183)
We do not inherit the earth from our ancestors,
we borrow it from our children. - S.M.A.R.T Person
[-- Attachment #2: This is a digitally signed message part --]
[-- Type: application/pgp-signature, Size: 189 bytes --]
^ permalink raw reply
* Re: [PATCH 2.6.19 4/4] ehca: ehca_av.c use constant for max mtu
From: Roland Dreier @ 2006-11-08 23:08 UTC (permalink / raw)
To: Hoang-Nam Nguyen; +Cc: linuxppc-dev, linux-kernel, openib-general
In-Reply-To: <200611052142.56722.hnguyen@de.ibm.com>
Thanks, I've applied 1 through 4.
^ permalink raw reply
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox