* [PATCH] [POWERPC] get_property cleanups
From: Stephen Rothwell @ 2007-04-29 6:29 UTC (permalink / raw)
To: paulus; +Cc: Olof Johansson, ppc-dev
Just another pass through arch/powerpc for old usages.
Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
---
arch/powerpc/platforms/cell/ras.c | 4 ++--
arch/powerpc/platforms/pasemi/cpufreq.c | 11 ++++++-----
arch/powerpc/platforms/pasemi/gpio_mdio.c | 6 +++---
arch/powerpc/sysdev/uic.c | 8 ++++----
4 files changed, 15 insertions(+), 14 deletions(-)
--
Cheers,
Stephen Rothwell sfr@canb.auug.org.au
diff --git a/arch/powerpc/platforms/cell/ras.c b/arch/powerpc/platforms/cell/ras.c
index b5ebc91..3961a08 100644
--- a/arch/powerpc/platforms/cell/ras.c
+++ b/arch/powerpc/platforms/cell/ras.c
@@ -149,7 +149,7 @@ static int __init cbe_ptcal_enable(void)
if (!np)
return -ENODEV;
- size = get_property(np, "ibm,cbe-ptcal-size", NULL);
+ size = of_get_property(np, "ibm,cbe-ptcal-size", NULL);
if (!size)
return -ENODEV;
@@ -168,7 +168,7 @@ static int __init cbe_ptcal_enable(void)
/* support for older device tree - use cpu nodes */
for_each_node_by_type(np, "cpu") {
- const u32 *nid = get_property(np, "node-id", NULL);
+ const u32 *nid = of_get_property(np, "node-id", NULL);
if (!nid) {
printk(KERN_ERR "%s: node %s is missing node-id?\n",
__FUNCTION__, np->full_name);
diff --git a/arch/powerpc/platforms/pasemi/cpufreq.c b/arch/powerpc/platforms/pasemi/cpufreq.c
index 4dd5c51..2a57d60 100644
--- a/arch/powerpc/platforms/pasemi/cpufreq.c
+++ b/arch/powerpc/platforms/pasemi/cpufreq.c
@@ -134,7 +134,8 @@ void restore_astate(int cpu)
static int pas_cpufreq_cpu_init(struct cpufreq_policy *policy)
{
- u32 *max_freq;
+ const u32 *max_freqp;
+ u32 max_freq;
int i, cur_astate;
struct resource res;
struct device_node *cpu, *dn;
@@ -175,16 +176,16 @@ static int pas_cpufreq_cpu_init(struct cpufreq_policy *policy)
pr_debug("init cpufreq on CPU %d\n", policy->cpu);
- max_freq = (u32*) get_property(cpu, "clock-frequency", NULL);
- if (!max_freq) {
+ max_freqp = of_get_property(cpu, "clock-frequency", NULL);
+ if (!max_freqp) {
err = -EINVAL;
goto out_unmap_sdcpwr;
}
/* we need the freq in kHz */
- *max_freq /= 1000;
+ max_freq = *max_freqp / 1000;
- pr_debug("max clock-frequency is at %u kHz\n", *max_freq);
+ pr_debug("max clock-frequency is at %u kHz\n", max_freq);
pr_debug("initializing frequency table\n");
/* initialize frequency table */
diff --git a/arch/powerpc/platforms/pasemi/gpio_mdio.c b/arch/powerpc/platforms/pasemi/gpio_mdio.c
index b1d3b6b..c91a335 100644
--- a/arch/powerpc/platforms/pasemi/gpio_mdio.c
+++ b/arch/powerpc/platforms/pasemi/gpio_mdio.c
@@ -258,7 +258,7 @@ static int __devinit gpio_mdio_probe(struct of_device *ofdev,
new_bus->write = &gpio_mdio_write,
new_bus->reset = &gpio_mdio_reset,
- prop = get_property(np, "reg", NULL);
+ prop = of_get_property(np, "reg", NULL);
new_bus->id = *prop;
new_bus->priv = priv;
@@ -269,10 +269,10 @@ static int __devinit gpio_mdio_probe(struct of_device *ofdev,
new_bus->irq[i] = irq_create_mapping(NULL, 10);
- prop = get_property(np, "mdc-pin", NULL);
+ prop = of_get_property(np, "mdc-pin", NULL);
priv->mdc_pin = *prop;
- prop = get_property(np, "mdio-pin", NULL);
+ prop = of_get_property(np, "mdio-pin", NULL);
priv->mdio_pin = *prop;
new_bus->dev = dev;
diff --git a/arch/powerpc/sysdev/uic.c b/arch/powerpc/sysdev/uic.c
index cdbe684..968fb40 100644
--- a/arch/powerpc/sysdev/uic.c
+++ b/arch/powerpc/sysdev/uic.c
@@ -230,7 +230,7 @@ static struct uic * __init uic_init_one(struct device_node *node)
memset(uic, 0, sizeof(*uic));
spin_lock_init(&uic->lock);
uic->of_node = of_node_get(node);
- indexp = get_property(node, "cell-index", &len);
+ indexp = of_get_property(node, "cell-index", &len);
if (!indexp || (len != sizeof(u32))) {
printk(KERN_ERR "uic: Device node %s has missing or invalid "
"cell-index property\n", node->full_name);
@@ -238,7 +238,7 @@ static struct uic * __init uic_init_one(struct device_node *node)
}
uic->index = *indexp;
- dcrreg = get_property(node, "dcr-reg", &len);
+ dcrreg = of_get_property(node, "dcr-reg", &len);
if (!dcrreg || (len != 2*sizeof(u32))) {
printk(KERN_ERR "uic: Device node %s has missing or invalid "
"dcr-reg property\n", node->full_name);
@@ -278,7 +278,7 @@ void __init uic_init_tree(void)
np = of_find_compatible_node(NULL, NULL, "ibm,uic");
while (np) {
- interrupts = get_property(np, "interrupts", NULL);
+ interrupts = of_get_property(np, "interrupts", NULL);
if (! interrupts)
break;
@@ -297,7 +297,7 @@ void __init uic_init_tree(void)
/* The scan again for cascaded UICs */
np = of_find_compatible_node(NULL, NULL, "ibm,uic");
while (np) {
- interrupts = get_property(np, "interrupts", NULL);
+ interrupts = of_get_property(np, "interrupts", NULL);
if (interrupts) {
/* Secondary UIC */
int cascade_virq;
--
1.5.1.2
^ permalink raw reply related
* Re: [PATCH] [POWERPC] get_property cleanups
From: Olof Johansson @ 2007-04-29 6:55 UTC (permalink / raw)
To: Stephen Rothwell; +Cc: ppc-dev, paulus
In-Reply-To: <20070429162908.c8bffbec.sfr@canb.auug.org.au>
On Sun, Apr 29, 2007 at 04:29:08PM +1000, Stephen Rothwell wrote:
> Just another pass through arch/powerpc for old usages.
>
> Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
> ---
> arch/powerpc/platforms/cell/ras.c | 4 ++--
> arch/powerpc/platforms/pasemi/cpufreq.c | 11 ++++++-----
> arch/powerpc/platforms/pasemi/gpio_mdio.c | 6 +++---
> arch/powerpc/sysdev/uic.c | 8 ++++----
arch/powerpc/platforms/cell/cbe-cpufreq.c needs the same changes as paseemi/cpufreq.c.
-Olof
^ permalink raw reply
* Re: [PATCH] [POWERPC] get_property cleanups
From: Stephen Rothwell @ 2007-04-29 7:35 UTC (permalink / raw)
To: Olof Johansson; +Cc: ppc-dev, paulus
In-Reply-To: <20070429065533.GA8241@lixom.net>
[-- Attachment #1: Type: text/plain, Size: 283 bytes --]
On Sun, 29 Apr 2007 01:55:33 -0500 olof@lixom.net (Olof Johansson) wrote:
>
> arch/powerpc/platforms/cell/cbe-cpufreq.c needs the same changes as paseemi/cpufreq.c.
Already done.
--
Cheers,
Stephen Rothwell sfr@canb.auug.org.au
http://www.canb.auug.org.au/~sfr/
[-- Attachment #2: Type: application/pgp-signature, Size: 189 bytes --]
^ permalink raw reply
* Re: [PATCH 2/2] Rename get_property to of_get_property: drivers/net
From: Andrew Morton @ 2007-04-29 7:43 UTC (permalink / raw)
To: David Miller; +Cc: sfr, netdev, paulus, jeff, linuxppc-dev
In-Reply-To: <20070428.204754.62343452.davem@davemloft.net>
On Sat, 28 Apr 2007 20:47:54 -0700 (PDT) David Miller <davem@davemloft.net> wrote:
> From: Stephen Rothwell <sfr@canb.auug.org.au>
> Date: Sun, 29 Apr 2007 11:44:46 +1000
>
> > So can I take this as a future OK for architecture specific network
> > drivers changes to go through the architecture trees (cc'd to you)?
>
> It's been my experience that if I'm just working through some
> platform or bus specific API changes, people like Jeff tend to
> not mind if it goes via ARCH trees and the like.
This all started with me having a dummyspit over yet another huge reject
because of intersections between subsystem trees.
Normally we get away with it but when there's so much material pending,
things deteriorate.
^ permalink raw reply
* Re: [PATCH v4] powerpc: 64K page support for kexec
From: Paul Mackerras @ 2007-04-29 8:30 UTC (permalink / raw)
To: Luke Browning
Cc: Arnd Bergmann, Milton Miller, linuxppc-dev, Olof Johansson,
cbe-oss-dev
In-Reply-To: <1177695045.24866.135.camel@luke-laptop>
Luke Browning writes:
> How about the following as an alternative.
>
> BUG_ON((hpte_v & 0x4000000000000000UL) && (crashing_cpus == -1));
> BUG_ON((size == MMU_PAGE_16G) && (crashing_cpus == -1));
> BUG_ON((size == MMU_PAGE_64K_AP) && (crashing_cpus == -1));
How much effort would it be to add the code to cope with those
conditions and give the correct answers? I'd much prefer that to
these BUG_ONs.
Paul.
^ permalink raw reply
* Re: [PATCH v4] powerpc: 64K page support for kexec
From: Benjamin Herrenschmidt @ 2007-04-29 9:31 UTC (permalink / raw)
To: Paul Mackerras
Cc: Arnd Bergmann, Milton Miller, linuxppc-dev, Olof Johansson,
cbe-oss-dev
In-Reply-To: <17972.22463.103425.51542@cargo.ozlabs.ibm.com>
On Sun, 2007-04-29 at 18:30 +1000, Paul Mackerras wrote:
> Luke Browning writes:
>
> > How about the following as an alternative.
> >
> > BUG_ON((hpte_v & 0x4000000000000000UL) && (crashing_cpus == -1));
> > BUG_ON((size == MMU_PAGE_16G) && (crashing_cpus == -1));
> > BUG_ON((size == MMU_PAGE_64K_AP) && (crashing_cpus == -1));
>
> How much effort would it be to add the code to cope with those
> conditions and give the correct answers? I'd much prefer that to
> these BUG_ONs.
hrm...
1T segments shouldn't be too hard... 16G pages goes with it pretty much,
and AP ... well... do they work on any implementation anyway ?
Ben.
^ permalink raw reply
* Re: [PATCH v4] powerpc: 64K page support for kexec
From: Segher Boessenkool @ 2007-04-29 13:27 UTC (permalink / raw)
To: Paul Mackerras
Cc: Arnd Bergmann, Milton Miller, linuxppc-dev, Olof Johansson,
cbe-oss-dev
In-Reply-To: <17972.22463.103425.51542@cargo.ozlabs.ibm.com>
>> BUG_ON((hpte_v & 0x4000000000000000UL) && (crashing_cpus == -1));
>> BUG_ON((size == MMU_PAGE_16G) && (crashing_cpus == -1));
>> BUG_ON((size == MMU_PAGE_64K_AP) && (crashing_cpus == -1));
>
> How much effort would it be to add the code to cope with those
> conditions and give the correct answers? I'd much prefer that to
> these BUG_ONs.
The test "& 0x400..." should be "& 0xc00..." since the
"B" filed in a page table entry is the top _two_ bits.
Not sure what that tells us about the work involved in
making this code do the right thing under all conditions,
but it would seem to indicate trouble ahead. Also, the
encodings with bit 0 = 1 are reserved (says arch v2.03),
so there would probably still be a BUG_ON() here.
Segher
^ permalink raw reply
* Re: [PATCH] [POWERPC] get_property cleanups
From: Olof Johansson @ 2007-04-29 15:13 UTC (permalink / raw)
To: Stephen Rothwell; +Cc: ppc-dev, paulus
In-Reply-To: <20070429173531.dcc33d43.sfr@canb.auug.org.au>
On Sun, Apr 29, 2007 at 05:35:31PM +1000, Stephen Rothwell wrote:
> On Sun, 29 Apr 2007 01:55:33 -0500 olof@lixom.net (Olof Johansson) wrote:
> >
> > arch/powerpc/platforms/cell/cbe-cpufreq.c needs the same changes as paseemi/cpufreq.c.
>
> Already done.
Yep, nevermind. I looked at the file yesterday but it must have been an older version.
-Olof
^ permalink raw reply
* Re: [PATCH] [POWERPC] get_property cleanups
From: Olof Johansson @ 2007-04-29 15:15 UTC (permalink / raw)
To: Stephen Rothwell; +Cc: ppc-dev, paulus
In-Reply-To: <20070429162908.c8bffbec.sfr@canb.auug.org.au>
On Sun, Apr 29, 2007 at 04:29:08PM +1000, Stephen Rothwell wrote:
> Just another pass through arch/powerpc for old usages.
>
> Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
Acked-by: Olof Johansson <olof@lixom.net>
-Olof
^ permalink raw reply
* USB Host Controller MPC875 Linux 2.6
From: Henrik Larson @ 2007-04-29 17:19 UTC (permalink / raw)
To: linuxppc-embedded
Hi,
I have a board with a MPC875 processor with a Linux 2.6.16 kernel and
looking for USB support.
Previous, for the 2.4 kernel, I've used used Brad Parker's
m8xxhci driver (with success).
Does anyone know if there is a Linux 2.6.x USB Host Controller driver
for MPC875 (or MPC8xx) somewhere ?
Thanks.
/Henrik
^ permalink raw reply
* problems with slip and slattach
From: melinda develey @ 2007-04-29 19:50 UTC (permalink / raw)
To: linuxppc-embedded
[-- Attachment #1: Type: text/plain, Size: 319 bytes --]
I'm trying to setup a slip link, I enabled the slip kernel support, I launched slattach -p slip /dev/ttyS0 & but sl0 interface is not created.
Any help would be appreciated.
Bye,
Melinda.
---------------------------------
Ahhh...imagining that irresistible "new car" smell?
Check outnew cars at Yahoo! Autos.
[-- Attachment #2: Type: text/html, Size: 488 bytes --]
^ permalink raw reply
* Virtex-4 PPC405 first instruction after reset - ultracontroller vs regular designs
From: Mohammad Sadegh Sadri @ 2007-04-29 21:31 UTC (permalink / raw)
To: Linux PPC Linux PPC
Hi all
may be not really related to linux but I hope some body can help me with th=
is
As you know PPC405 runs the instruction at 0xfffffffc address as it's first=
instruction
when generating a base system for ML403 using XPS, one should certainly add=
PLB BRAM controller , this module will reside on PLB and contains some BRA=
M instances. A Code called boot loop is located in these block memories. PP=
C405 runs boot loop until sysace makes linux elf ready.=20
Looking in the generated xparameters.h you see that the base address for PL=
B BRAM IF is 0xffff0000 and since the first instruction should be located a=
t 0xfffffffc , you have to define the size of this PLB BRAM IF equal to 64k=
when generating your system in XPS.
Now looking at ultracontroller reference design one can see that PPC405 loo=
ks for 0xfffffffc address on its IS OCM bus , but in regular designs as you=
see PPC405 looks for this address on PLB Instruction bus, I'm wondering ho=
w PPC understands to do so in each of these designs? Does PPC have a specia=
l input port which is assigned a fix value and indicates where should PPC l=
ook for 0xfffffffc address ( ISOCM or IS PLB )?
thanks.
_________________________________________________________________
Connect to the next generation of MSN Messenger=A0
http://imagine-msn.com/messenger/launch80/default.aspx?locale=3Den-us&sourc=
e=3Dwlmailtagline=
^ permalink raw reply
* Re: [PATCH v4] powerpc: 64K page support for kexec
From: Benjamin Herrenschmidt @ 2007-04-29 22:49 UTC (permalink / raw)
To: Segher Boessenkool
Cc: Arnd Bergmann, Milton Miller, linuxppc-dev, Paul Mackerras,
Olof Johansson, cbe-oss-dev
In-Reply-To: <c08e2dc179070866364d96a7b5ade65b@kernel.crashing.org>
On Sun, 2007-04-29 at 15:27 +0200, Segher Boessenkool wrote:
> >> BUG_ON((hpte_v & 0x4000000000000000UL) && (crashing_cpus == -1));
> >> BUG_ON((size == MMU_PAGE_16G) && (crashing_cpus == -1));
> >> BUG_ON((size == MMU_PAGE_64K_AP) && (crashing_cpus == -1));
> >
> > How much effort would it be to add the code to cope with those
> > conditions and give the correct answers? I'd much prefer that to
> > these BUG_ONs.
>
> The test "& 0x400..." should be "& 0xc00..." since the
> "B" filed in a page table entry is the top _two_ bits.
Yup, we need to put some symbolic constants too. We can dig them from
the old never-applied 1T segment patch I did a while ago.
> Not sure what that tells us about the work involved in
> making this code do the right thing under all conditions,
> but it would seem to indicate trouble ahead. Also, the
> encodings with bit 0 = 1 are reserved (says arch v2.03),
> so there would probably still be a BUG_ON() here.
Ben.
^ permalink raw reply
* Re: [PATCH v2] powerpc: fix suspend states again
From: Paul Mackerras @ 2007-04-30 0:14 UTC (permalink / raw)
To: Johannes Berg; +Cc: Olof Johansson, linuxppc-dev
In-Reply-To: <1177711372.3565.73.camel@johannes.berg>
Johannes Berg writes:
> +void save_processor_state(void)
> +{
> + /* Giveup the lazy FPU & vec so we don't have to back them
> + * up from the low level code
> + */
> + enable_kernel_fp();
> +
> +#ifdef CONFIG_ALTIVEC
> + if (cur_cpu_spec->cpu_features & CPU_FTR_ALTIVEC)
> + enable_kernel_altivec();
> +#endif /* CONFIG_ALTIVEC */
> +
> +#ifdef CONFIG_SPE
> + enable_kernel_spe();
> +#endif
> +}
This achieves essentially the same effect as prepare_to_copy() in
arch/powerpc/kernel/process.c, except that we don't end up with fp,
altivec and/or spe enabled - but that's OK since the following code
doesn't actually need fp/altivec/spe.
It would be good to avoid this duplication, or at least to use the
flush_* calls instead of the enable_kernel_* calls.
Paul.
^ permalink raw reply
* Please pull powerpc.git for-2.6.22 branch
From: Paul Mackerras @ 2007-04-30 3:20 UTC (permalink / raw)
To: torvalds; +Cc: linuxppc-dev
Linus,
Please do:
git pull \
git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc.git for-2.6.22
to get a powerpc update for 2.6.22.
Thanks,
Paul.
Documentation/powerpc/booting-without-of.txt | 256 +-
arch/powerpc/Kconfig | 472 ---
arch/powerpc/Kconfig.debug | 12
arch/powerpc/Makefile | 11
arch/powerpc/boot/.gitignore | 3
arch/powerpc/boot/Makefile | 122 -
arch/powerpc/boot/crt0.S | 37
arch/powerpc/boot/cuboot-83xx.c | 68 +
arch/powerpc/boot/cuboot-85xx.c | 69 +
arch/powerpc/boot/devtree.c | 307 ++
arch/powerpc/boot/dts/kuroboxHD.dts | 7
arch/powerpc/boot/dts/kuroboxHG.dts | 7
arch/powerpc/boot/dts/lite5200.dts | 1
arch/powerpc/boot/dts/lite5200b.dts | 1
arch/powerpc/boot/dts/mpc7448hpc2.dts | 1
arch/powerpc/boot/dts/mpc8272ads.dts | 1
arch/powerpc/boot/dts/mpc8313erdb.dts | 1
arch/powerpc/boot/dts/mpc832x_mds.dts | 1
arch/powerpc/boot/dts/mpc832x_rdb.dts | 291 ++
arch/powerpc/boot/dts/mpc8349emitx.dts | 1
arch/powerpc/boot/dts/mpc8349emitxgp.dts | 1
arch/powerpc/boot/dts/mpc834x_mds.dts | 1
arch/powerpc/boot/dts/mpc836x_mds.dts | 1
arch/powerpc/boot/dts/mpc8540ads.dts | 1
arch/powerpc/boot/dts/mpc8541cds.dts | 1
arch/powerpc/boot/dts/mpc8544ds.dts | 136 +
arch/powerpc/boot/dts/mpc8548cds.dts | 1
arch/powerpc/boot/dts/mpc8555cds.dts | 1
arch/powerpc/boot/dts/mpc8560ads.dts | 1
arch/powerpc/boot/dts/mpc8568mds.dts | 1
arch/powerpc/boot/dts/mpc8641_hpcn.dts | 25
arch/powerpc/boot/dts/mpc866ads.dts | 1
arch/powerpc/boot/dts/mpc885ads.dts | 1
arch/powerpc/boot/elf.h | 8
arch/powerpc/boot/elf_util.c | 76 +
arch/powerpc/boot/flatdevtree.c | 199 +
arch/powerpc/boot/flatdevtree.h | 7
arch/powerpc/boot/flatdevtree_misc.c | 42
arch/powerpc/boot/gunzip_util.c | 206 ++
arch/powerpc/boot/gunzip_util.h | 45
arch/powerpc/boot/main.c | 369 +--
arch/powerpc/boot/ns16550.c | 9
arch/powerpc/boot/of.c | 21
arch/powerpc/boot/ops.h | 103 +
arch/powerpc/boot/ppcboot.h | 108 +
arch/powerpc/boot/reg.h | 22
arch/powerpc/boot/simple_alloc.c | 31
arch/powerpc/boot/stdio.h | 5
arch/powerpc/boot/wrapper | 53
arch/powerpc/boot/zImage.coff.lds.S | 3
arch/powerpc/boot/zImage.lds.S | 1
arch/powerpc/configs/cell_defconfig | 57
arch/powerpc/configs/g5_defconfig | 2
arch/powerpc/configs/maple_defconfig | 2
arch/powerpc/configs/mpc832x_rdb_defconfig | 1292 ++++++++++
arch/powerpc/configs/mpc8544_ds_defconfig | 1077 ++++++++
arch/powerpc/configs/ppc64_defconfig | 2
arch/powerpc/kernel/Makefile | 4
arch/powerpc/kernel/align.c | 56
arch/powerpc/kernel/asm-offsets.c | 2
arch/powerpc/kernel/btext.c | 22
arch/powerpc/kernel/cpu_setup_pa6t.S | 2
arch/powerpc/kernel/cputable.c | 14
arch/powerpc/kernel/entry_32.S | 1
arch/powerpc/kernel/head_64.S | 16
arch/powerpc/kernel/ibmebus.c | 288 +-
arch/powerpc/kernel/iommu.c | 35
arch/powerpc/kernel/irq.c | 2
arch/powerpc/kernel/kprobes.c | 36
arch/powerpc/kernel/legacy_serial.c | 24
arch/powerpc/kernel/lparcfg.c | 58
arch/powerpc/kernel/machine_kexec_64.c | 14
arch/powerpc/kernel/misc_32.S | 4
arch/powerpc/kernel/of_device.c | 112 +
arch/powerpc/kernel/of_platform.c | 5
arch/powerpc/kernel/pci_32.c | 42
arch/powerpc/kernel/pci_64.c | 32
arch/powerpc/kernel/pci_dn.c | 9
arch/powerpc/kernel/ppc_ksyms.c | 1
arch/powerpc/kernel/process.c | 54
arch/powerpc/kernel/prom.c | 167 -
arch/powerpc/kernel/prom_init.c | 55
arch/powerpc/kernel/prom_parse.c | 51
arch/powerpc/kernel/rtas-proc.c | 4
arch/powerpc/kernel/rtas.c | 19
arch/powerpc/kernel/rtas_pci.c | 14
arch/powerpc/kernel/setup-common.c | 68 -
arch/powerpc/kernel/setup_32.c | 17
arch/powerpc/kernel/setup_64.c | 11
arch/powerpc/kernel/smp.c | 4
arch/powerpc/kernel/sys_ppc32.c | 4
arch/powerpc/kernel/sysfs.c | 17
arch/powerpc/kernel/time.c | 2
arch/powerpc/kernel/traps.c | 76 -
arch/powerpc/kernel/vio.c | 17
arch/powerpc/lib/copyuser_64.S | 6
arch/powerpc/lib/locks.c | 4
arch/powerpc/lib/mem_64.S | 6
arch/powerpc/lib/memcpy_64.S | 6
arch/powerpc/lib/sstep.c | 45
arch/powerpc/mm/hash_low_32.S | 22
arch/powerpc/mm/hash_low_64.S | 5
arch/powerpc/mm/hash_native_64.c | 2
arch/powerpc/mm/hash_utils_64.c | 127 +
arch/powerpc/mm/hugetlbpage.c | 16
arch/powerpc/mm/init_32.c | 4
arch/powerpc/mm/lmb.c | 4
arch/powerpc/mm/mem.c | 3
arch/powerpc/mm/mmu_decl.h | 5
arch/powerpc/mm/numa.c | 24
arch/powerpc/mm/pgtable_32.c | 76 -
arch/powerpc/mm/ppc_mmu_32.c | 4
arch/powerpc/mm/tlb_64.c | 68 -
arch/powerpc/oprofile/Makefile | 2
arch/powerpc/oprofile/common.c | 3
arch/powerpc/oprofile/op_model_cell.c | 3
arch/powerpc/oprofile/op_model_pa6t.c | 234 ++
arch/powerpc/platforms/4xx/Kconfig | 372 +--
arch/powerpc/platforms/52xx/Kconfig | 35
arch/powerpc/platforms/52xx/efika.c | 15
arch/powerpc/platforms/52xx/lite5200.c | 12
arch/powerpc/platforms/52xx/mpc52xx_common.c | 2
arch/powerpc/platforms/52xx/mpc52xx_pci.c | 2
arch/powerpc/platforms/82xx/Kconfig | 45
arch/powerpc/platforms/82xx/mpc82xx.c | 6
arch/powerpc/platforms/82xx/mpc82xx_ads.c | 12
arch/powerpc/platforms/83xx/Kconfig | 15
arch/powerpc/platforms/83xx/Makefile | 1
arch/powerpc/platforms/83xx/mpc832x_mds.c | 1
arch/powerpc/platforms/83xx/mpc832x_mds.h | 19
arch/powerpc/platforms/83xx/mpc832x_rdb.c | 138 +
arch/powerpc/platforms/83xx/mpc834x_itx.h | 23
arch/powerpc/platforms/83xx/pci.c | 2
arch/powerpc/platforms/85xx/Kconfig | 38
arch/powerpc/platforms/85xx/Makefile | 1
arch/powerpc/platforms/85xx/mpc8544_ds.c | 144 +
arch/powerpc/platforms/85xx/mpc85xx_ads.c | 2
arch/powerpc/platforms/85xx/mpc85xx_cds.c | 2
arch/powerpc/platforms/85xx/mpc85xx_mds.c | 2
arch/powerpc/platforms/85xx/pci.c | 2
arch/powerpc/platforms/86xx/Kconfig | 18
arch/powerpc/platforms/86xx/Makefile | 2
arch/powerpc/platforms/86xx/mpc86xx_hpcn.c | 4
arch/powerpc/platforms/86xx/pci.c | 4
arch/powerpc/platforms/8xx/Kconfig | 67
arch/powerpc/platforms/8xx/m8xx_setup.c | 8
arch/powerpc/platforms/8xx/mpc86xads.h | 2
arch/powerpc/platforms/8xx/mpc86xads_setup.c | 4
arch/powerpc/platforms/8xx/mpc885ads.h | 2
arch/powerpc/platforms/8xx/mpc885ads_setup.c | 4
arch/powerpc/platforms/Kconfig | 259 ++
arch/powerpc/platforms/cell/Kconfig | 24
arch/powerpc/platforms/cell/cbe_cpufreq.c | 112 +
arch/powerpc/platforms/cell/cbe_regs.c | 168 +
arch/powerpc/platforms/cell/cbe_regs.h | 5
arch/powerpc/platforms/cell/cbe_thermal.c | 181 +
arch/powerpc/platforms/cell/interrupt.c | 4
arch/powerpc/platforms/cell/io-workarounds.c | 2
arch/powerpc/platforms/cell/iommu.c | 16
arch/powerpc/platforms/cell/ras.c | 160 +
arch/powerpc/platforms/cell/setup.c | 12
arch/powerpc/platforms/cell/spider-pic.c | 8
arch/powerpc/platforms/cell/spu_base.c | 163 -
arch/powerpc/platforms/cell/spu_coredump.c | 34
arch/powerpc/platforms/cell/spu_manage.c | 18
arch/powerpc/platforms/cell/spufs/Makefile | 2
arch/powerpc/platforms/cell/spufs/backing_ops.c | 6
arch/powerpc/platforms/cell/spufs/context.c | 45
arch/powerpc/platforms/cell/spufs/coredump.c | 19
arch/powerpc/platforms/cell/spufs/fault.c | 211 ++
arch/powerpc/platforms/cell/spufs/file.c | 152 +
arch/powerpc/platforms/cell/spufs/hw_ops.c | 9
arch/powerpc/platforms/cell/spufs/inode.c | 44
arch/powerpc/platforms/cell/spufs/run.c | 123 -
arch/powerpc/platforms/cell/spufs/sched.c | 113 -
arch/powerpc/platforms/cell/spufs/spufs.h | 34
arch/powerpc/platforms/cell/spufs/switch.c | 8
arch/powerpc/platforms/celleb/Kconfig | 9
arch/powerpc/platforms/celleb/iommu.c | 6
arch/powerpc/platforms/celleb/pci.c | 18
arch/powerpc/platforms/celleb/setup.c | 12
arch/powerpc/platforms/chrp/Kconfig | 11
arch/powerpc/platforms/chrp/nvram.c | 2
arch/powerpc/platforms/chrp/pci.c | 25
arch/powerpc/platforms/chrp/setup.c | 52
arch/powerpc/platforms/chrp/time.c | 13
arch/powerpc/platforms/embedded6xx/Kconfig | 264 --
arch/powerpc/platforms/embedded6xx/linkstation.c | 8
arch/powerpc/platforms/embedded6xx/ls_uart.c | 4
arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c | 15
arch/powerpc/platforms/iseries/Kconfig | 4
arch/powerpc/platforms/iseries/iommu.c | 4
arch/powerpc/platforms/iseries/irq.c | 4
arch/powerpc/platforms/iseries/pci.c | 5
arch/powerpc/platforms/iseries/setup.c | 10
arch/powerpc/platforms/iseries/viopath.c | 2
arch/powerpc/platforms/maple/Kconfig | 17
arch/powerpc/platforms/maple/pci.c | 8
arch/powerpc/platforms/maple/setup.c | 17
arch/powerpc/platforms/pasemi/Kconfig | 19
arch/powerpc/platforms/pasemi/Makefile | 3
arch/powerpc/platforms/pasemi/cpufreq.c | 308 ++
arch/powerpc/platforms/pasemi/gpio_mdio.c | 339 +++
arch/powerpc/platforms/pasemi/idle.c | 9
arch/powerpc/platforms/pasemi/iommu.c | 6
arch/powerpc/platforms/pasemi/pasemi.h | 8
arch/powerpc/platforms/pasemi/pci.c | 16
arch/powerpc/platforms/pasemi/setup.c | 28
arch/powerpc/platforms/powermac/Kconfig | 20
arch/powerpc/platforms/powermac/backlight.c | 9
arch/powerpc/platforms/powermac/cpufreq_32.c | 24
arch/powerpc/platforms/powermac/cpufreq_64.c | 16
arch/powerpc/platforms/powermac/feature.c | 101 -
arch/powerpc/platforms/powermac/low_i2c.c | 15
arch/powerpc/platforms/powermac/pci.c | 41
arch/powerpc/platforms/powermac/pfunc_base.c | 2
arch/powerpc/platforms/powermac/pfunc_core.c | 5
arch/powerpc/platforms/powermac/pic.c | 8
arch/powerpc/platforms/powermac/setup.c | 61
arch/powerpc/platforms/powermac/smp.c | 11
arch/powerpc/platforms/powermac/time.c | 38
arch/powerpc/platforms/powermac/udbg_scc.c | 6
arch/powerpc/platforms/prep/Kconfig | 9
arch/powerpc/platforms/ps3/Kconfig | 16
arch/powerpc/platforms/ps3/htab.c | 2
arch/powerpc/platforms/pseries/Kconfig | 10
arch/powerpc/platforms/pseries/Makefile | 5
arch/powerpc/platforms/pseries/eeh.c | 204 +-
arch/powerpc/platforms/pseries/eeh_driver.c | 78 -
arch/powerpc/platforms/pseries/eeh_event.c | 8
arch/powerpc/platforms/pseries/firmware.c | 2
arch/powerpc/platforms/pseries/hotplug-cpu.c | 4
arch/powerpc/platforms/pseries/iommu.c | 67
arch/powerpc/platforms/pseries/lpar.c | 6
arch/powerpc/platforms/pseries/nvram.c | 2
arch/powerpc/platforms/pseries/pci.c | 3
arch/powerpc/platforms/pseries/pci_dlpar.c | 1
arch/powerpc/platforms/pseries/ras.c | 2
arch/powerpc/platforms/pseries/rtasd.c | 2
arch/powerpc/platforms/pseries/setup.c | 44
arch/powerpc/platforms/pseries/xics.c | 17
arch/powerpc/sysdev/Makefile | 5
arch/powerpc/sysdev/dart_iommu.c | 4
arch/powerpc/sysdev/dcr.c | 14
arch/powerpc/sysdev/fsl_pcie.c | 2
arch/powerpc/sysdev/fsl_pcie.h | 94 +
arch/powerpc/sysdev/fsl_soc.c | 90 -
arch/powerpc/sysdev/mpic.c | 32
arch/powerpc/sysdev/pmi.c | 29
arch/powerpc/sysdev/qe_lib/Kconfig | 10
arch/powerpc/sysdev/qe_lib/qe.c | 4
arch/powerpc/sysdev/qe_lib/qe_io.c | 6
arch/powerpc/sysdev/qe_lib/ucc_slow.c | 4
arch/powerpc/sysdev/timer.c | 71 +
arch/powerpc/sysdev/tsi108_dev.c | 16
arch/powerpc/sysdev/tsi108_pci.c | 2
arch/powerpc/sysdev/uic.c | 342 +++
arch/powerpc/xmon/xmon.c | 11
arch/ppc/8xx_io/Kconfig | 4
arch/ppc/8xx_io/Makefile | 1
arch/ppc/8xx_io/cs4218.h | 166 -
arch/ppc/8xx_io/cs4218_tdm.c | 2833 ---------------------
arch/ppc/boot/common/misc-common.c | 15
arch/ppc/boot/simple/Makefile | 1
arch/ppc/boot/simple/uartlite_tty.c | 37
arch/ppc/kernel/asm-offsets.c | 1
arch/ppc/kernel/entry.S | 1
arch/ppc/platforms/4xx/Kconfig | 15
arch/ppc/platforms/4xx/Makefile | 1
arch/ppc/platforms/4xx/ocotea.c | 4
arch/ppc/platforms/4xx/taishan.c | 2
arch/ppc/platforms/4xx/virtex.c | 56
arch/ppc/platforms/4xx/virtex.h | 34
arch/ppc/platforms/4xx/xilinx_ml300.c | 65
arch/ppc/platforms/4xx/xilinx_ml300.h | 45
arch/ppc/platforms/4xx/xilinx_ml403.c | 66
arch/ppc/platforms/4xx/xilinx_ml403.h | 49
arch/ppc/platforms/4xx/xparameters/xparameters.h | 60
arch/ppc/platforms/rpxclassic.h | 4
arch/ppc/platforms/rpxhiox.h | 41
arch/ppc/platforms/rpxlite.h | 4
arch/ppc/syslib/Makefile | 3
arch/ppc/syslib/cpc710.h | 81 -
arch/ppc/syslib/m8xx_setup.c | 2
arch/ppc/syslib/ppc4xx_sgdma.c | 1
arch/ppc/syslib/virtex_devices.c | 233 ++
arch/ppc/syslib/virtex_devices.h | 27
drivers/char/briq_panel.c | 7
drivers/char/hvc_console.c | 49
drivers/char/hvc_iseries.c | 2
drivers/char/hvc_vio.c | 2
drivers/char/hvsi.c | 4
drivers/char/tpm/tpm_atmel.h | 4
drivers/char/watchdog/Kconfig | 2
drivers/hwmon/ams/ams-core.c | 4
drivers/hwmon/ams/ams-i2c.c | 4
drivers/hwmon/ams/ams-pmu.c | 4
drivers/infiniband/hw/ehca/ehca_main.c | 4
drivers/macintosh/adb.c | 42
drivers/macintosh/ans-lcd.c | 9
drivers/macintosh/apm_emu.c | 13
drivers/macintosh/mac_hid.c | 2
drivers/macintosh/macio-adb.c | 16
drivers/macintosh/macio_asic.c | 100 -
drivers/macintosh/macio_sysfs.c | 10
drivers/macintosh/rack-meter.c | 2
drivers/macintosh/smu.c | 8
drivers/macintosh/therm_adt746x.c | 8
drivers/macintosh/therm_pm72.c | 8
drivers/macintosh/therm_windtunnel.c | 2
drivers/macintosh/via-cuda.c | 2
drivers/macintosh/via-pmu-led.c | 10
drivers/macintosh/via-pmu.c | 55
drivers/macintosh/windfarm_lm75_sensor.c | 2
drivers/macintosh/windfarm_max6690_sensor.c | 2
drivers/macintosh/windfarm_smu_controls.c | 8
drivers/macintosh/windfarm_smu_sat.c | 8
drivers/macintosh/windfarm_smu_sensors.c | 6
drivers/media/video/planb.c | 5
drivers/net/Kconfig | 9
drivers/ps3/vuart.c | 8
drivers/scsi/ibmvscsi/ibmvstgt.c | 7
drivers/scsi/ibmvscsi/rpa_vscsi.c | 3
drivers/serial/pmac_zilog.c | 4
drivers/video/Kconfig | 2
drivers/video/aty/radeon_pm.c | 2
drivers/video/controlfb.c | 16
fs/proc/proc_devtree.c | 2
include/asm-powerpc/asm-compat.h | 10
include/asm-powerpc/cacheflush.h | 6
include/asm-powerpc/cell-pmu.h | 5
include/asm-powerpc/cputable.h | 11
include/asm-powerpc/current.h | 1
include/asm-powerpc/edac.h | 40
include/asm-powerpc/eeh_event.h | 6
include/asm-powerpc/ibmebus.h | 44
include/asm-powerpc/immap_86xx.h | 75 -
include/asm-powerpc/io.h | 7
include/asm-powerpc/kprobes.h | 5
include/asm-powerpc/machdep.h | 3
include/asm-powerpc/mmu-hash64.h | 400 +++
include/asm-powerpc/mmu.h | 405 ---
include/asm-powerpc/mpic.h | 12
include/asm-powerpc/of_device.h | 3
include/asm-powerpc/oprofile_impl.h | 2
include/asm-powerpc/paca.h | 4
include/asm-powerpc/parport.h | 6
include/asm-powerpc/pci.h | 14
include/asm-powerpc/pgtable-4k.h | 3
include/asm-powerpc/pgtable-64k.h | 5
include/asm-powerpc/pgtable.h | 60
include/asm-powerpc/pmc.h | 1
include/asm-powerpc/ppc-pci.h | 12
include/asm-powerpc/processor.h | 1
include/asm-powerpc/prom.h | 34
include/asm-powerpc/reg.h | 68 -
include/asm-powerpc/spu_csa.h | 1
include/asm-powerpc/system.h | 1
include/asm-powerpc/tlb.h | 1
include/asm-powerpc/tlbflush.h | 172 +
include/asm-powerpc/uaccess.h | 28
include/asm-powerpc/uic.h | 23
include/asm-ppc/ibm4xx.h | 8
include/asm-ppc/ppc_sys.h | 2
include/asm-ppc/prom.h | 3
include/linux/pmu.h | 12
sound/aoa/codecs/snd-aoa-codec-onyx.c | 4
sound/aoa/codecs/snd-aoa-codec-tas.c | 9
sound/aoa/core/snd-aoa-gpio-feature.c | 8
sound/aoa/fabrics/snd-aoa-fabric-layout.c | 8
sound/aoa/soundbus/core.c | 4
sound/aoa/soundbus/i2sbus/i2sbus-core.c | 8
sound/oss/dmasound/dmasound_awacs.c | 121 +
sound/oss/dmasound/tas_common.c | 9
sound/ppc/pmac.c | 41
sound/ppc/tumbler.c | 55
376 files changed, 11546 insertions(+), 7892 deletions(-)
create mode 100644 arch/powerpc/boot/cuboot-83xx.c
create mode 100644 arch/powerpc/boot/cuboot-85xx.c
create mode 100644 arch/powerpc/boot/devtree.c
create mode 100644 arch/powerpc/boot/dts/mpc832x_rdb.dts
create mode 100644 arch/powerpc/boot/dts/mpc8544ds.dts
create mode 100644 arch/powerpc/boot/elf_util.c
create mode 100644 arch/powerpc/boot/gunzip_util.c
create mode 100644 arch/powerpc/boot/gunzip_util.h
create mode 100644 arch/powerpc/boot/ppcboot.h
create mode 100644 arch/powerpc/boot/reg.h
create mode 100644 arch/powerpc/configs/mpc832x_rdb_defconfig
create mode 100644 arch/powerpc/configs/mpc8544_ds_defconfig
create mode 100644 arch/powerpc/oprofile/op_model_pa6t.c
create mode 100644 arch/powerpc/platforms/52xx/Kconfig
delete mode 100644 arch/powerpc/platforms/83xx/mpc832x_mds.h
create mode 100644 arch/powerpc/platforms/83xx/mpc832x_rdb.c
delete mode 100644 arch/powerpc/platforms/83xx/mpc834x_itx.h
create mode 100644 arch/powerpc/platforms/85xx/mpc8544_ds.c
create mode 100644 arch/powerpc/platforms/Kconfig
create mode 100644 arch/powerpc/platforms/cell/spufs/fault.c
create mode 100644 arch/powerpc/platforms/celleb/Kconfig
create mode 100644 arch/powerpc/platforms/chrp/Kconfig
create mode 100644 arch/powerpc/platforms/maple/Kconfig
create mode 100644 arch/powerpc/platforms/pasemi/cpufreq.c
create mode 100644 arch/powerpc/platforms/pasemi/gpio_mdio.c
create mode 100644 arch/powerpc/platforms/powermac/Kconfig
rename arch/powerpc/{platforms/86xx/mpc86xx_pcie.c => sysdev/fsl_pcie.c} (100%)
create mode 100644 arch/powerpc/sysdev/fsl_pcie.h
create mode 100644 arch/powerpc/sysdev/timer.c
create mode 100644 arch/powerpc/sysdev/uic.c
delete mode 100644 arch/ppc/8xx_io/cs4218.h
delete mode 100644 arch/ppc/8xx_io/cs4218_tdm.c
create mode 100644 arch/ppc/boot/simple/uartlite_tty.c
delete mode 100644 arch/ppc/platforms/4xx/virtex.c
delete mode 100644 arch/ppc/platforms/4xx/xilinx_ml300.h
delete mode 100644 arch/ppc/platforms/4xx/xilinx_ml403.h
delete mode 100644 arch/ppc/platforms/rpxhiox.h
delete mode 100644 arch/ppc/syslib/cpc710.h
create mode 100644 arch/ppc/syslib/virtex_devices.c
create mode 100644 arch/ppc/syslib/virtex_devices.h
create mode 100644 include/asm-powerpc/edac.h
create mode 100644 include/asm-powerpc/mmu-hash64.h
create mode 100644 include/asm-powerpc/uic.h
Adrian Bunk (2):
[POWERPC] Unexport mac_hid_mouse_emulate_buttons
[POWERPC] Remove the unused HTDMSOUND driver
Akinobu Mita (6):
[POWERPC] spufs: check spu_acquire_runnable() return value
[POWERPC] spufs: fix missing error handling in module_init()
[POWERPC] spufs: fix memory leak on spufs reloading
[POWERPC] spufs: use memcpy_fromio() to copy from local store
[POWERPC] spufs: enable SPU coredump for kernel-builtin spufs
[POWERPC] Enable make install
Alan Cox (2):
[POWERPC] pci_32.c: Switch to ref counting PCI API
[POWERPC] via-pmu: Switch to ref counting PCI API
Ananth N Mavinakayanahalli (2):
[POWERPC] Emulate more instructions in software
[POWERPC] kprobes: Eliminate sstep exception if instruction can be emulated
Andrew Morton (2):
[POWERPC] Fix compile error in prom.h
[POWERPC] ppc4xx_sgdma needs dma-mapping.h
Anton Blanchard (3):
[POWERPC] Remove _get_SP
[POWERPC] Remove last_syscall
[POWERPC] Fix WARN_ON when entering xmon
Arnd Bergmann (4):
[POWERPC] spufs: add memory barriers after set_bit
[POWERPC] spufs: make spu page faults not block scheduling
[POWERPC] spufs: fix memory leak on coredump
[POWERPC] update cell_defconfig
Bart Van Assche (1):
[POWERPC] Ocotea board: ntpd complains that the frequency error exceeds the tolerance
Benjamin Herrenschmidt (8):
[POWERPC] Add inatomic versions of __get_user and __put_user
[POWERPC] Alignment exception uses __get/put_user_inatomic
[POWERPC] Make tlb flush batch use lazy MMU mode
[POWERPC] Cleanup 32-bit map_page
[POWERPC] Fix 32-bit mm operations when not using BATs
[POWERPC] DEBUG_PAGEALLOC for 32-bit
[POWERPC] DEBUG_PAGEALLOC for 64-bit
[POWERPC] Always use -mno-string
Christian Krafft (8):
[POWERPC] cell: add cbe_node_to_cpu function
[POWERPC] cbe_thermal: clean up computation of temperature
[POWERPC] cbe_thermal: add throttling attributes to cpu and spu nodes
[POWERPC] cell: use pmi in cpufreq driver
[POWERPC] add check for initialized driver data to pmi driver
[POWERPC] pmi probe device by device-type
[POWERPC] add of_iomap function
[POWERPC] cell: add support for proper device-tree
Christoph Hellwig (12):
[POWERPC] spufs: don't yield CPU in spu_yield
[POWERPC] spufs: use cancel_rearming_delayed_workqueue when stopping spu contexts
[POWERPC] spufs: clear mapping pointers after last close
[POWERPC] spu sched: ensure preempted threads are put back on the runqueue
[POWERPC] spu sched: ensure preempted threads are put back on the runqueue, part2
[POWERPC] spufs: remove woken threads from the runqueue early
[POWERPC] spufs: streamline locking for isolated spu setup
[POWERPC] spu_base: move spu_init_channels out of spu_mutex
[POWERPC] spufs: turn run_sema into run_mutex
[POWERPC] spufs: avoid spurious memory barriers
[POWERPC] spufs: various run.c cleanups
[POWERPC] spu_base: remove cleanup_spu_base
Dave Jiang (2):
[POWERPC] EDAC ECC software scrubber
[POWERPC] remove kernel module option for booke wdt
David Gibson (16):
[POWERPC] Allow duplicate lmb_reserve() calls
[POWERPC] Automatically lmb_reserve() initrd
[POWERPC] zImage: Add more flexible gunzip convenience functions
[POWERPC] zImage: Cleanup and improve prep_kernel()
[POWERPC] zImage: Cleanup and improve zImage entry point
[POWERPC] Update documentation for flat device tree format v17
[POWERPC] Add documentation for the zImage's gunzip convenience functions
[POWERPC] Add gcc format warnings to zImage printf()
[POWERPC] New reg.h for the zImage
[POWERPC] Add device tree utility functions to zImage
[POWERPC] Clean up zImage handling of the command line
[POWERPC] Re-organize Kconfig code for 4xx in arch/powerpc
[POWERPC] Add arch/powerpc driver for UIC, PPC4xx interrupt controller
[POWERPC] Cleanup and fix breakage in tlbflush.h
[POWERPC] Abolish PHYS_FMT macro from arch/powerpc
[POWERPC] Prepare for splitting up mmu.h by MMU type
Domen Puncer (1):
[POWERPC] Fix typos in booting-without-of.txt
Geert Uytterhoeven (3):
[POWERPC] ps3: always make sure we're running on a PS3
[POWERPC] CBE thermal support on PS3
[POWERPC] bootwrapper: Use `unsigned long' for malloc sizes
Giuliano Pochini (1):
[POWERPC] Fix breakage caused by 72486f1f8f0a2bc828b9d30cf4690cf2dd6807fc
Grant Likely (8):
[POWERPC] Fix comment typo in Kurobox device tree
[POWERPC] Rework Kconfig dependancies for Xilinx Virtex ppc405 platform
[POWERPC] Merge common virtex header files
[POWERPC] New registration for common Xilinx Virtex ppc405 platform devices
[POWERPC] Stop using ppc_sys for Xilinx Virtex boards
[POWERPC] Add uartlite boot console driver for the zImage wrapper
[POWERPC] Add sane defaults for Xilinx EDK generated xparameters files
[POWERPC] Don't define a custom bd_t for Xilixn Virtex based boards.
Jake Moilanen (3):
[POWERPC] DMA 4GB boundary protection
[POWERPC] 750CL cputable entry
[POWERPC] DMA 4GB boundary protection
Jeremy Kerr (5):
[POWERPC] spufs: provide siginfo for SPE faults
[POWERPC] spufs: add mode= mount option
[POWERPC] spufs: Minor cleanup of spu_wait
[POWERPC] spu_base: fix initialisation on systems with no SPEs
[POWERPC] cell: enable RTAS-based PTCAL for Cell XDR memory
Joachim Fenkes (3):
[POWERPC] ibmebus: whitespace fixes
[POWERPC] ibmebus: dynamic addition/removal of adapters, some code cleanup
[POWERPC] ibmebus: change probe/remove interface from using loc-code to DT path
Johannes Berg (3):
[POWERPC] Generic time suspend/resume code
[POWERPC] powermac: disallow pmu sleep notifiers from aborting sleep
[POWERPC] Declare enable_kernel_spe in a header
John Rigby (1):
[POWERPC] Avoid putting cpu node twice
Jon Loeliger (3):
[POWERPC] 86xx/85xx: Move 8641 PCI-Express to arch/powerpc/sysdev/fsl_pcie.c.
[POWERPC] 85xx: Add initial MPC8544 DS platform files.
[POWERPC] 85xx: Add initial MPC8544DS basic port defconfig.
Josh Boyer (1):
[POWERPC] Fix PowerPC 750CL and 750GX CPU features
Kumar Gala (14):
[POWERPC] Split 52xx platforms into their own Kconfig file
[POWERPC] Split powermac platforms into their own Kconfig file
[POWERPC] Split cell platforms into their respective Kconfig file
[POWERPC] Removed config options that we don't support in embedded6xx
[POWERPC] Split several platforms into their respective Kconfig file
[POWERPC] Created arch/powerpc/platforms/Kconfig for "Platform support"
[POWERPC] 83xx: Removed dead header
[POWERPC] Ensure platform CONFIG options have correct dependencies
[POWERPC] Convert 86xx platform to unified platform Kconfig
[POWERPC] Convert 83xx platform to unified platform Kconfig
[POWERPC] Convert 82xx platform to unified platform Kconfig
[POWERPC] Convert 8xx platform to unified platform Kconfig
[POWERPC] Convert 85xx platform to unified platform Kconfig
[POWERPC] Miscellaneous arch/powerpc Kconfig and platform/Kconfig cleanup
Linas Vepstas (11):
[POWERPC] EEH: modify order of EEH state checking
[POWERPC] EEH: Add clarifying messages.
[POWERPC] EEH: Tolerate high mmio
[POWERPC] EEH: support ibm,get-config-addr-info2 RTAS call
[POWERPC] EEH: hotplug recovery bugfix
[POWERPC] EEH: multifunction recovery bugfix
[POWERPC] EEH: handle reset state high
[POWERPC] EEH: wait for slot status
[POWERPC] EEH: rm un-needed data
[POWERPC] EEH: verify state change
[POWERPC] EEH: restructure multi-function support
Luke Browning (1):
[POWERPC] spu sched: make addition to stop_wq and runque atomic vs wakeup
MOKUNO Masakazu (1):
[POWERPC] Remove some redundant isync instructions
Mariusz Kozlowski (1):
[POWERPC] 8xx parenthesis balance
Mark A. Greer (4):
[POWERPC] 32-bit early_init() should zero from __bss_start to __bss_stop only
[POWERPC] Move bootwrapper ELF parsing routines to a file
[POWERPC] Routine to find the devtree node of a linux,phandle
[POWERPC] Add dt_xlate_addr() to bootwrapper
Michael Barkowski (1):
[POWERPC] 83xx: Add MPC832x RDB board support.
Michael Ellerman (1):
[POWERPC] Rename MPIC_BROKEN_U3 to MPIC_U3_HT_IRQS
Milind Arun Choudhary (1):
[POWERPC] Clean up unused ROUND_UP, NAME_OFFSET macros in arch/powerpc
Milton Miller (11):
[POWERPC] boot: rebuild when wrapper changes
[POWERPC] boot: export flush_cache
[POWERPC] bootwrapper: Add a fatal error helper
[POWERPC] bootwrapper: Allow platforms to call library zImage_start
[POWERPC] boot: Use FORCE
[POWERPC] boot: clean rule fixes
[POWERPC] boot: Use a common zImage rule
[POWERPC] bootwrapper: missing relocation in crt0.S
[POWERPC] bootwrapper: no-gzip fixes
[POWERPC] bootwrapper: Decompress less, check more
[POWERPC] boot: More verbose gunzip error message
Olaf Hering (7):
[POWERPC] Include stddef.h in asm-powerpc/current.h to get offsetof
[POWERPC] Fix link errors when EEH is disabled
[POWERPC] Remove unused inclusion of linux/ide.h
[POWERPC] Autodetect serial console on efika
[POWERPC] Fix modalias content in sysfs for macio devices
[POWERPC] Add correct interrupt property for pegasos ide
[POWERPC] Generic check_legacy_ioport
Olof Johansson (12):
[POWERPC] Use mtocrf instruction in asm when CONFIG_POWER4_ONLY=y
[POWERPC] pasemi: Allow 8KB config space for I/O bridge
[POWERPC] pasemi: Enable one more hid bit
[POWERPC] pasemi: Reset mpic on boot
[POWERPC] pasemi: PA6T oprofile support
[POWERPC] pasemi: GPIO MDIO of_platform driver
[POWERPC] Save trap number in bad_stack
[POWERPC] pasemi: Remove build warning
[POWERPC] pasemi: Kconfig for gpio_mdio
[POWERPC] pasemi: Cpufreq driver
[POWERPC] Clean up cpufreq Kconfig dependencies
[POWERPC] cell: cbe_cpufreq cleanup and crash fix
Paul Mackerras (8):
[POWERPC] Harden validate_sp against stack corruption
[POWERPC] Allow drivers to map individual 4k pages to userspace
[POWERPC] Fix detection of loader-supplied initrd on OF platforms
[POWERPC] Partially revert "Add correct interrupt property for pegasos ide"
Revert "[POWERPC] DMA 4GB boundary protection"
Revert "[POWERPC] Rename get_property to of_get_property: drivers"
Revert "[POWERPC] Autodetect serial console on efika"
[POWERPC] Remove dev_dbg redefinition in drivers/ps3/vuart.c
Robert P. J. Day (3):
[POWERPC] Correct apparently misspelled "XMON" preprocessor symbol.
[POWERPC] 83xx: Delete unused header file.
[POWERPC] Remove unused header file: arch/ppc/syslib/cpc710.h.
Scott Wood (25):
[POWERPC] bootwrapper: Add stddef.h to ops.h
[POWERPC] bootwrapper: Add ft_root_node().
[POWERPC] bootwrapper: Rename ft_node_add() to ft_get_phandle().
[POWERPC] bootwrapper: Make ft_get_phandle() accept and return NULL.
[POWERPC] bootwrapper: Preserve the pp pointer in ft_make_space() when calling ft_reorder().
[POWERPC] bootwrapper: Modify *pp, not *p, in ft_shuffle().
[POWERPC] bootwrapper: Use map_string() instead of lookup_string() in ft_prop().
[POWERPC] bootwrapper: Add ft_find_device_rel().
[POWERPC] bootwrapper: Refactor ft_get_prop() into internal and external functions.
[POWERPC] bootwrapper: Make ft_get_parent() return a phandle, and NULL if already top-level.
[POWERPC] bootwrapper: Add ft_find_node_by_prop_value().
[POWERPC] bootwrapper: Make ft_create_node() pay attention to the parent parameter.
[POWERPC] bootwrapper: Add dt_ops methods.
[POWERPC] bootwrapper: Make compression of the kernel image optional.
[POWERPC] Document the linux,network-index property.
[POWERPC] bootwrapper: Make setprop accept a const buffer.
[POWERPC] bootwrapper: Add dt_xlate_reg(), and use it to find serial registers.
[POWERPC] bootwrapper: Add CONFIG_DEVICE_TREE
[POWERPC] bootwrapper: Add a cuboot platform and a cuImage target
[POWERPC] bootwrapper: Add ppcboot.h
[POWERPC] bootwrapper: cuboot for 83xx
[POWERPC] bootwrapper: Fix array handling in dt_xlate_reg().
[POWERPC] bootwrapper: cuImage for 85xx
[POWERPC] bootwrapper: cuboot-83xx: Exclude upper 1MB from heap.
[POWERPC] bootwrapper: CONFIG_ -> CONFIG_DEVICE_TREE
Segher Boessenkool (1):
[POWERPC] PowerPC: select default image for Linkstation
Sonny Rao (1):
[POWERPC] Remove stale comment from head_64.S
Srinivasa Ds (1):
[POWERPC] arch/powerpc/sysdev/timer.c build fix
Stefan Roese (1):
[POWERPC] ppc: Fix PCIX configuration of Ocotea & Taishan for > 512MB DDR
Stephen Rothwell (29):
[POWERPC] Allocate syscall number for sys_getcpu
[POWERPC] Make ppc64_defconfig without CONFIG_PPC_PSERIES build
[POWERPC] Create and use set_pci_dma_ops
[POWERPC] Create and use get_pci_dma_ops()
[POWERPC] Make iSeries build without CONFIG_PCI
[POWERPC] Allow pSeries to build without CONFIG_PCI
[POWERPC] Allow xmon to build without CONFIG_DEBUG_BUGVERBOSE
[POWERPC] Make find_and_init_pbs() a void function
[POWERPC] Minor paca optimisation
[POWERPC] get_property returns const
[POWERPC] Rename get_property to of_get_property
[POWERPC] Rename device_is_compatible to of_device_is_compatible
[POWERPC] Rename prom_n_addr_cells to of_n_addr_cells
[POWERPC] Rename prom_n_size_cells to of_n_size_cells
[POWERPC] Make struct property's value a void *
[POWERPC] Rename get_property to of_get_property: include
[POWERPC] Rename get_property to of_get_property: arch/powerpc
[POWERPC] Rename get_property to of_get_property: sound
[POWERPC] Rename get_property to of_get_property: drivers
[POWERPC] Rename get_property to of_get_property: the last one
[POWERPC] Rename last get_property calls
[POWERPC] Remove find_compatible_devices
[POWERPC] Remove find_all_nodes
[POWERPC] Remove old interface find_path_device
[POWERPC] Remove old interface find_type_devices
[POWERPC] Remove old interface find_devices
[POWERPC] Rename get_property to of_get_property: partial drivers
[POWERPC] Partially revert a7edd0e676d51145ae634a2acf7a447e319200fa
[POWERPC] get_property cleanups
Stuart Yoder (3):
[POWERPC] Remove interrupt-controller as a property under /chosen
[POWERPC] Remove unused, undocumented #cpus property from cpus node
[POWERPC] Update interrupt info in booting-without-of.txt
Sylvain Munaut (3):
[POWERPC] Add a unified uevent handler for bus based on of_device
[POWERPC] powermac: Use the new of_device common uevent handler
[POWERPC] Add uevent handler for of_platform_bus
Thomas Gleixner (1):
[POWERPC] Spinlock initializer cleanup
Timur Tabi (2):
[POWERPC] QE: automatically select QE options
[POWERPC] QE: fix invalid pointer usage in ucc_slow_init()
Tony Vroon (1):
[POWERPC] PMU LED whitelisting of PowerMac 7,2 and 7,3
Will Schmidt (2):
[POWERPC] hvc_console: Polling mode timer backoff
[POWERPC] Replace if-then-else with a switch statement
Zang Roy-r61911 (2):
[POWERPC] Remove fixed setting of ROOT_DEV for 7448HPC2 platforms
[POWERPC] 86xx/85xx: Unify Freescale PCI Express memory map registers structure
Zhang Wei (1):
[POWERPC] 86xx: Added 2nd PCI-Ex controller support for MPC8641 HPCN to DTS.
anton@samba.org (5):
[POWERPC] Add missing oops_enter/oops_exit
[POWERPC] Clean up pmac_backlight_unblank in oops path
[POWERPC] Handle recursive oopses
[POWERPC] Fix backwards ? : when printing machine type
[POWERPC] Use lowercase for hex printouts in oops messages.
will schmidt (1):
[POWERPC] hvc_console: Typo fixes
^ permalink raw reply
* Re: Small cleanups to the cuboot bootwrapper code
From: David Gibson @ 2007-04-30 3:40 UTC (permalink / raw)
To: Scott Wood; +Cc: linuxppc-dev, Paul Mackerras
In-Reply-To: <463237EA.4010102@freescale.com>
On Fri, Apr 27, 2007 at 12:50:34PM -0500, Scott Wood wrote:
> David Gibson wrote:
> > Index: working-2.6/arch/powerpc/boot/Makefile
> > ===================================================================
> > --- working-2.6.orig/arch/powerpc/boot/Makefile 2007-04-27 11:48:56.000000000 +1000
> > +++ working-2.6/arch/powerpc/boot/Makefile 2007-04-27 11:57:41.000000000 +1000
> > @@ -129,7 +129,8 @@ image-$(CONFIG_PPC_CELLEB) += zImage.ps
> > image-$(CONFIG_PPC_CHRP) += zImage.chrp
> > image-$(CONFIG_PPC_EFIKA) += zImage.chrp
> > image-$(CONFIG_PPC_PMAC) += zImage.pmac
> > -image-$(CONFIG_DEFAULT_UIMAGE) += uImage cuImage
> > +image-$(CONFIG_PPC_83xx) += cuImage.83xx
> > +image-$(CONFIG_DEFAULT_UIMAGE) += uImage
>
> You need to update BOOT_TARGETS in arch/powerpc/Makefile as well.
> Otherwise, it looks good.
Ok, revised patch coming shortly. Actually, I just removed cuImage
from the BOOT_TARGETS list. Since the only sensible thing it could
really be is another alias for zImage, I don't see that there was
really much point to it. Patch also updated to apply on top of your
85xx additions.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
^ permalink raw reply
* Small cleanups to the cuboot bootwrapper code
From: David Gibson @ 2007-04-30 3:42 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev
This patch makes a few small cleanups to the cuboot code.
- It removes the double layered selection of images, via
cuboot-plat-y, instead having the cuboot platforms directly select a
suitable image-y (this changes the name of the final cuboot image from
plain cuImage to cuImage.<platform>).
- Factors out some code in the wrapper that's potentially
useful to platforms other than uboot.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
arch/powerpc/Makefile | 2 +-
arch/powerpc/boot/Makefile | 15 ++++++---------
arch/powerpc/boot/wrapper | 28 +++++++++++++---------------
3 files changed, 20 insertions(+), 25 deletions(-)
Index: working-2.6/arch/powerpc/boot/Makefile
===================================================================
--- working-2.6.orig/arch/powerpc/boot/Makefile 2007-04-30 13:37:31.000000000 +1000
+++ working-2.6/arch/powerpc/boot/Makefile 2007-04-30 13:41:00.000000000 +1000
@@ -129,7 +129,9 @@ image-$(CONFIG_PPC_CELLEB) += zImage.ps
image-$(CONFIG_PPC_CHRP) += zImage.chrp
image-$(CONFIG_PPC_EFIKA) += zImage.chrp
image-$(CONFIG_PPC_PMAC) += zImage.pmac
-image-$(CONFIG_DEFAULT_UIMAGE) += uImage cuImage
+image-$(CONFIG_PPC_83xx) += cuImage.83xx
+image-$(CONFIG_PPC_85xx) += cuImage.85xx
+image-$(CONFIG_DEFAULT_UIMAGE) += uImage
# For 32-bit powermacs, build the COFF and miboot images
# as well as the ELF images.
@@ -162,15 +164,11 @@ $(obj)/zImage.initrd.ps3: vmlinux
$(obj)/uImage: vmlinux $(wrapperbits)
$(call if_changed,wrap,uboot)
-cuboot-plat-$(CONFIG_83xx) += 83xx
-cuboot-plat-$(CONFIG_85xx) += 85xx
-cuboot-plat-y += unknown-platform
-
dts = $(if $(shell echo $(CONFIG_) | grep '^/'),\
,$(srctree)/$(src)/dts/)$(CONFIG_DEVICE_TREE)
-$(obj)/cuImage: vmlinux $(wrapperbits)
- $(call if_changed,wrap,cuboot-$(word 1,$(cuboot-plat-y)),$(dts))
+$(obj)/cuImage.%: vmlinux $(wrapperbits)
+ $(call if_changed,wrap,cuboot-$*,$(dts))
$(obj)/zImage: $(addprefix $(obj)/, $(image-y))
@rm -f $@; ln $< $@
@@ -181,8 +179,7 @@ install: $(CONFIGURE) $(addprefix $(obj)
sh -x $(srctree)/$(src)/install.sh "$(KERNELRELEASE)" vmlinux System.map "$(INSTALL_PATH)" $<
# anything not in $(targets)
-clean-files += $(image-) $(initrd-) zImage zImage.initrd \
- cuImage.elf cuImage.bin.gz
+clean-files += $(image-) $(initrd-) zImage zImage.initrd cuImage.*
# clean up files cached by wrapper
clean-kernel := vmlinux.strip vmlinux.bin
Index: working-2.6/arch/powerpc/boot/wrapper
===================================================================
--- working-2.6.orig/arch/powerpc/boot/wrapper 2007-04-30 13:37:31.000000000 +1000
+++ working-2.6/arch/powerpc/boot/wrapper 2007-04-30 13:41:00.000000000 +1000
@@ -163,20 +163,19 @@ fi
vmz="$vmz$gzip"
-case "$platform" in
-uboot|cuboot*)
- version=`${CROSS}strings "$kernel" | grep '^Linux version [-0-9.]' | \
- cut -d' ' -f3`
- if [ -n "$version" ]; then
- version="-n Linux-$version"
- fi
-esac
+# Extract kernel version information, some platforms want to include
+# it in the image header
+version=`${CROSS}strings "$kernel" | grep '^Linux version [-0-9.]' | \
+ cut -d' ' -f3`
+if [ -n "$version" ]; then
+ uboot_version="-n Linux-$version"
+fi
case "$platform" in
uboot)
rm -f "$ofile"
mkimage -A ppc -O linux -T kernel -C gzip -a 00000000 -e 00000000 \
- $version -d "$vmz" "$ofile"
+ $uboot_version -d "$vmz" "$ofile"
if [ -z "$cacheit" ]; then
rm -f "$vmz"
fi
@@ -212,25 +211,24 @@ if [ "$platform" != "miboot" ]; then
rm $tmp
fi
+# Some platforms need the zImage's entry point and base address
+base=0x`${CROSS}nm "$ofile" | grep ' _start$' | cut -d' ' -f1`
+entry=`${CROSS}objdump -f "$ofile" | grep '^start address ' | cut -d' ' -f3`
+
# post-processing needed for some platforms
case "$platform" in
pseries|chrp)
$object/addnote "$ofile"
;;
pmaccoff)
- entry=`objdump -f "$ofile" | grep '^start address ' | \
- cut -d' ' -f3`
${CROSS}objcopy -O aixcoff-rs6000 --set-start "$entry" "$ofile"
$object/hack-coff "$ofile"
;;
cuboot*)
- base=`${CROSS}nm "$ofile" | grep ' _start$' | cut -d' ' -f1`
- entry=`${CROSS}objdump -f "$ofile" | grep '^start address ' | \
- cut -d' ' -f3`
mv "$ofile" "$ofile".elf
${CROSS}objcopy -O binary "$ofile".elf "$ofile".bin
gzip -f -9 "$ofile".bin
mkimage -A ppc -O linux -T kernel -C gzip -a "$base" -e "$entry" \
- $version -d "$ofile".bin.gz "$ofile"
+ $uboot_version -d "$ofile".bin.gz "$ofile"
;;
esac
Index: working-2.6/arch/powerpc/Makefile
===================================================================
--- working-2.6.orig/arch/powerpc/Makefile 2007-04-30 13:37:55.000000000 +1000
+++ working-2.6/arch/powerpc/Makefile 2007-04-30 13:38:13.000000000 +1000
@@ -148,7 +148,7 @@ all: $(KBUILD_IMAGE)
CPPFLAGS_vmlinux.lds := -Upowerpc
-BOOT_TARGETS = zImage zImage.initrd uImage cuImage
+BOOT_TARGETS = zImage zImage.initrd uImage
PHONY += $(BOOT_TARGETS)
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
^ permalink raw reply
* [PATCH v2] powerpc: Show current speed in /proc/cpuinfo
From: Olof Johansson @ 2007-04-30 3:53 UTC (permalink / raw)
To: paulus; +Cc: linuxppc-dev
In-Reply-To: <20070427084118.GA8842@lixom.net>
On other architectures, the frequency in /proc/cpuinfo moves with cpufreq
changes. It makes sense to do the same on powerpc to keep users from
getting confused.
Change the format to three decimals, having full Hz granularity is silly
these days. Also specify in output if it's cpufreq or firmware-reported:
clock : 1250.000MHz (from firmware)
or:
clock : 2500.000MHz (actual speed)
Signed-off-by: Olof Johansson <olof@lixom.net>
Index: powerpc/arch/powerpc/kernel/setup-common.c
===================================================================
--- powerpc.orig/arch/powerpc/kernel/setup-common.c
+++ powerpc/arch/powerpc/kernel/setup-common.c
@@ -29,6 +29,7 @@
#include <linux/root_dev.h>
#include <linux/notifier.h>
#include <linux/cpu.h>
+#include <linux/cpufreq.h>
#include <linux/unistd.h>
#include <linux/serial.h>
#include <linux/serial_8250.h>
@@ -160,6 +161,7 @@ static int show_cpuinfo(struct seq_file
unsigned int pvr;
unsigned short maj;
unsigned short min;
+ unsigned int freq;
if (cpu_id == NR_CPUS) {
#if defined(CONFIG_SMP) && defined(CONFIG_PPC32)
@@ -226,13 +228,16 @@ static int show_cpuinfo(struct seq_file
}
#endif /* CONFIG_TAU */
- /*
- * Assume here that all clock rates are the same in a
- * smp system. -- Cort
- */
- if (ppc_proc_freq)
- seq_printf(m, "clock\t\t: %lu.%06luMHz\n",
- ppc_proc_freq / 1000000, ppc_proc_freq % 1000000);
+ /* cpufreq_quick_get() is in kHz */
+ freq = cpufreq_quick_get(cpu_id);
+
+ if (freq)
+ seq_printf(m, "clock\t\t: %u.%03uMHz (actual speed)\n",
+ freq / 1000, freq % 1000);
+ else if (ppc_proc_freq)
+ seq_printf(m, "clock\t\t: %lu.%03luMHz (from firmware)\n",
+ ppc_proc_freq / 1000000,
+ (ppc_proc_freq / 1000) % 1000);
if (ppc_md.show_percpuinfo != NULL)
ppc_md.show_percpuinfo(m, cpu_id);
^ permalink raw reply
* powerpc: Revise PPC44x MMU code for arch/powerpc
From: David Gibson @ 2007-04-30 4:06 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev
This patch takes the definitions for the PPC44x MMU (a software loaded
TLB) from asm-ppc/mmu.h, cleans them up of things no longer necessary
in arch/powerpc and puts them in a new asm-powerpc/mmu_44x.h file. It
also substantially simplifies arch/powerpc/mm/44x_mmu.c and makes a
couple of small fixes necessary for the 44x MMU code to build and work
properly in arch/powerpc.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
Paulus, I think this one's ready to go now. Please apply.
arch/powerpc/kernel/head_44x.S | 4 +-
arch/powerpc/mm/44x_mmu.c | 82 +++++++++--------------------------------
arch/powerpc/mm/mmu_decl.h | 3 +
include/asm-powerpc/mmu-44x.h | 72 ++++++++++++++++++++++++++++++++++++
include/asm-powerpc/mmu.h | 7 ++-
5 files changed, 100 insertions(+), 68 deletions(-)
Index: working-2.6/include/asm-powerpc/mmu.h
===================================================================
--- working-2.6.orig/include/asm-powerpc/mmu.h 2007-04-30 10:57:48.000000000 +1000
+++ working-2.6/include/asm-powerpc/mmu.h 2007-04-30 14:04:21.000000000 +1000
@@ -5,9 +5,12 @@
#ifdef CONFIG_PPC64
/* 64-bit classic hash table MMU */
# include <asm/mmu-hash64.h>
+#elif defined(CONFIG_44x)
+/* 44x-style software loaded TLB */
+# include <asm/mmu-44x.h>
#else
-/* 32-bit. FIXME: split up the 32-bit MMU types, and revise for
- * arch/powerpc */
+/* Other 32-bit. FIXME: split up the other 32-bit MMU types, and
+ * revise for arch/powerpc */
# include <asm-ppc/mmu.h>
#endif
Index: working-2.6/arch/powerpc/kernel/head_44x.S
===================================================================
--- working-2.6.orig/arch/powerpc/kernel/head_44x.S 2007-02-14 10:58:22.000000000 +1100
+++ working-2.6/arch/powerpc/kernel/head_44x.S 2007-04-30 14:05:35.000000000 +1000
@@ -120,8 +120,8 @@ skpinv: addi r4,r4,1 /* Increment */
* Configure and load pinned entry into TLB slot 63.
*/
- lis r3,KERNELBASE@h /* Load the kernel virtual address */
- ori r3,r3,KERNELBASE@l
+ lis r3,PAGE_OFFSET@h
+ ori r3,r3,PAGE_OFFSET@l
/* Kernel is at the base of RAM */
li r4, 0 /* Load the kernel physical address */
Index: working-2.6/arch/powerpc/mm/44x_mmu.c
===================================================================
--- working-2.6.orig/arch/powerpc/mm/44x_mmu.c 2006-12-08 10:42:48.000000000 +1100
+++ working-2.6/arch/powerpc/mm/44x_mmu.c 2007-04-30 14:04:21.000000000 +1000
@@ -24,73 +24,38 @@
*
*/
-#include <linux/signal.h>
-#include <linux/sched.h>
-#include <linux/kernel.h>
-#include <linux/errno.h>
-#include <linux/string.h>
-#include <linux/types.h>
-#include <linux/ptrace.h>
-#include <linux/mman.h>
-#include <linux/mm.h>
-#include <linux/swap.h>
-#include <linux/stddef.h>
-#include <linux/vmalloc.h>
#include <linux/init.h>
-#include <linux/delay.h>
-#include <linux/highmem.h>
-
-#include <asm/pgalloc.h>
-#include <asm/prom.h>
-#include <asm/io.h>
-#include <asm/mmu_context.h>
-#include <asm/pgtable.h>
#include <asm/mmu.h>
-#include <asm/uaccess.h>
-#include <asm/smp.h>
-#include <asm/bootx.h>
-#include <asm/machdep.h>
-#include <asm/setup.h>
+#include <asm/system.h>
+#include <asm/page.h>
#include "mmu_decl.h"
-extern char etext[], _stext[];
-
/* Used by the 44x TLB replacement exception handler.
* Just needed it declared someplace.
*/
-unsigned int tlb_44x_index = 0;
-unsigned int tlb_44x_hwater = 62;
+unsigned int tlb_44x_index; /* = 0 */
+unsigned int tlb_44x_hwater = PPC44x_TLB_SIZE - 1 - PPC44x_EARLY_TLBS;
/*
* "Pins" a 256MB TLB entry in AS0 for kernel lowmem
*/
-static void __init
-ppc44x_pin_tlb(int slot, unsigned int virt, unsigned int phys)
+static void __init ppc44x_pin_tlb(unsigned int virt, unsigned int phys)
{
- unsigned long attrib = 0;
-
- __asm__ __volatile__("\
- clrrwi %2,%2,10\n\
- ori %2,%2,%4\n\
- clrrwi %1,%1,10\n\
- li %0,0\n\
- ori %0,%0,%5\n\
- tlbwe %2,%3,%6\n\
- tlbwe %1,%3,%7\n\
- tlbwe %0,%3,%8"
+ __asm__ __volatile__(
+ "tlbwe %2,%3,%4\n"
+ "tlbwe %1,%3,%5\n"
+ "tlbwe %0,%3,%6\n"
:
- : "r" (attrib), "r" (phys), "r" (virt), "r" (slot),
- "i" (PPC44x_TLB_VALID | PPC44x_TLB_256M),
- "i" (PPC44x_TLB_SW | PPC44x_TLB_SR | PPC44x_TLB_SX | PPC44x_TLB_G),
+ : "r" (PPC44x_TLB_SW | PPC44x_TLB_SR | PPC44x_TLB_SX | PPC44x_TLB_G),
+ "r" (phys),
+ "r" (virt | PPC44x_TLB_VALID | PPC44x_TLB_256M),
+ "r" (tlb_44x_hwater--), /* slot for this TLB entry */
"i" (PPC44x_TLB_PAGEID),
"i" (PPC44x_TLB_XLAT),
"i" (PPC44x_TLB_ATTRIB));
}
-/*
- * MMU_init_hw does the chip-specific initialization of the MMU hardware.
- */
void __init MMU_init_hw(void)
{
flush_instruction_cache();
@@ -98,22 +63,13 @@ void __init MMU_init_hw(void)
unsigned long __init mmu_mapin_ram(void)
{
- unsigned int pinned_tlbs = 1;
- int i;
+ unsigned long addr;
- /* Determine number of entries necessary to cover lowmem */
- pinned_tlbs = (unsigned int)
- (_ALIGN(total_lowmem, PPC_PIN_SIZE) >> PPC44x_PIN_SHIFT);
-
- /* Write upper watermark to save location */
- tlb_44x_hwater = PPC44x_LOW_SLOT - pinned_tlbs;
-
- /* If necessary, set additional pinned TLBs */
- if (pinned_tlbs > 1)
- for (i = (PPC44x_LOW_SLOT-(pinned_tlbs-1)); i < PPC44x_LOW_SLOT; i++) {
- unsigned int phys_addr = (PPC44x_LOW_SLOT-i) * PPC_PIN_SIZE;
- ppc44x_pin_tlb(i, phys_addr+PAGE_OFFSET, phys_addr);
- }
+ /* Pin in enough TLBs to cover any lowmem not covered by the
+ * initial 256M mapping established in head_44x.S */
+ for (addr = PPC_PIN_SIZE; addr < total_lowmem;
+ addr += PPC_PIN_SIZE)
+ ppc44x_pin_tlb(addr + PAGE_OFFSET, addr);
return total_lowmem;
}
Index: working-2.6/include/asm-powerpc/mmu-44x.h
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ working-2.6/include/asm-powerpc/mmu-44x.h 2007-04-30 14:05:35.000000000 +1000
@@ -0,0 +1,72 @@
+#ifndef _ASM_POWERPC_MMU_44X_H_
+#define _ASM_POWERPC_MMU_44X_H_
+/*
+ * PPC440 support
+ */
+
+#define PPC44x_MMUCR_TID 0x000000ff
+#define PPC44x_MMUCR_STS 0x00010000
+
+#define PPC44x_TLB_PAGEID 0
+#define PPC44x_TLB_XLAT 1
+#define PPC44x_TLB_ATTRIB 2
+
+/* Page identification fields */
+#define PPC44x_TLB_EPN_MASK 0xfffffc00 /* Effective Page Number */
+#define PPC44x_TLB_VALID 0x00000200 /* Valid flag */
+#define PPC44x_TLB_TS 0x00000100 /* Translation address space */
+#define PPC44x_TLB_1K 0x00000000 /* Page sizes */
+#define PPC44x_TLB_4K 0x00000010
+#define PPC44x_TLB_16K 0x00000020
+#define PPC44x_TLB_64K 0x00000030
+#define PPC44x_TLB_256K 0x00000040
+#define PPC44x_TLB_1M 0x00000050
+#define PPC44x_TLB_16M 0x00000070
+#define PPC44x_TLB_256M 0x00000090
+
+/* Translation fields */
+#define PPC44x_TLB_RPN_MASK 0xfffffc00 /* Real Page Number */
+#define PPC44x_TLB_ERPN_MASK 0x0000000f
+
+/* Storage attribute and access control fields */
+#define PPC44x_TLB_ATTR_MASK 0x0000ff80
+#define PPC44x_TLB_U0 0x00008000 /* User 0 */
+#define PPC44x_TLB_U1 0x00004000 /* User 1 */
+#define PPC44x_TLB_U2 0x00002000 /* User 2 */
+#define PPC44x_TLB_U3 0x00001000 /* User 3 */
+#define PPC44x_TLB_W 0x00000800 /* Caching is write-through */
+#define PPC44x_TLB_I 0x00000400 /* Caching is inhibited */
+#define PPC44x_TLB_M 0x00000200 /* Memory is coherent */
+#define PPC44x_TLB_G 0x00000100 /* Memory is guarded */
+#define PPC44x_TLB_E 0x00000080 /* Memory is guarded */
+
+#define PPC44x_TLB_PERM_MASK 0x0000003f
+#define PPC44x_TLB_UX 0x00000020 /* User execution */
+#define PPC44x_TLB_UW 0x00000010 /* User write */
+#define PPC44x_TLB_UR 0x00000008 /* User read */
+#define PPC44x_TLB_SX 0x00000004 /* Super execution */
+#define PPC44x_TLB_SW 0x00000002 /* Super write */
+#define PPC44x_TLB_SR 0x00000001 /* Super read */
+
+/* Number of TLB entries */
+#define PPC44x_TLB_SIZE 64
+
+#ifndef __ASSEMBLY__
+
+typedef unsigned long long phys_addr_t;
+
+extern phys_addr_t fixup_bigphys_addr(phys_addr_t, phys_addr_t);
+
+typedef struct {
+ unsigned long id;
+ unsigned long vdso_base;
+} mm_context_t;
+
+#endif /* !__ASSEMBLY__ */
+
+#define PPC44x_EARLY_TLBS 1
+
+/* Size of the TLBs used for pinning in lowmem */
+#define PPC_PIN_SIZE (1 << 28) /* 256M */
+
+#endif /* _ASM_POWERPC_MMU_44X_H_ */
Index: working-2.6/arch/powerpc/mm/mmu_decl.h
===================================================================
--- working-2.6.orig/arch/powerpc/mm/mmu_decl.h 2007-04-26 13:57:24.000000000 +1000
+++ working-2.6/arch/powerpc/mm/mmu_decl.h 2007-04-30 14:04:21.000000000 +1000
@@ -40,7 +40,8 @@ extern int __map_without_bats;
extern unsigned long ioremap_base;
extern unsigned int rtas_data, rtas_size;
-extern PTE *Hash, *Hash_end;
+struct _PTE;
+extern struct _PTE *Hash, *Hash_end;
extern unsigned long Hash_size, Hash_mask;
extern unsigned int num_tlbcam_entries;
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
^ permalink raw reply
* Re: [PATCH 2/5] [PPC] Merge common virtex header files
From: Peter Korsgaard @ 2007-04-30 4:26 UTC (permalink / raw)
To: linuxppc-embedded
In-Reply-To: <528646bc0704271149w211bd5cbscb467123ab962703@mail.gmail.com>
>>>>> "GL" == Grant Likely <grant.likely@secretlab.ca> writes:
Hi,
>> instead? I'm using RedBoot on a virtex platform, and hence another
>> struct bd_info than the ML300/ML403.
GL> Alternate suggestion: Can we change virtex support to use the
GL> structure defined in ppcboot.h instead? (I've actually got that
GL> change in my tree and was planning on posting it for review today
GL> or tomorrow). bd_t is a stinking ugly mess, but things would be
GL> better if we standardize all virtex platforms on the stinking ugly
GL> mess shared by almost all the other ppc embedded board ports.
That's where the ugly mess pops up - RedBoot uses another
(incompatible) bd_t definition than U-boot, E.G:
typedef struct bd_info {
unsigned int bi_tag; /* Should be 0x42444944 "BDID" */
unsigned int bi_size; /* Size of this structure */
unsigned int bi_revision; /* revision of this structure */
unsigned int bi_bdate; /* bootstrap date, i.e. 0x11061997 */
unsigned int bi_memstart; /* Memory start address */
unsigned int bi_memsize; /* Memory (end) size in bytes */
unsigned int bi_intfreq; /* Internal Freq, in Hz */
unsigned int bi_busfreq; /* Bus Freq, in Hz */
unsigned int bi_cpmfreq; /* CPM Freq, in Hz */
unsigned int bi_brgfreq; /* BRG Freq, in Hz */
unsigned int bi_vco; /* VCO Out from PLL */
unsigned int bi_pci_freq; /* PCI Freq, in Hz */
unsigned int bi_baudrate; /* Default console baud rate */
unsigned int bi_immr; /* IMMR when called from boot rom */
unsigned char bi_enetaddr[6];
unsigned int bi_flashbase; /* Physical address of FLASH memory */
unsigned int bi_flashsize; /* Length of FLASH memory */
int bi_flashwidth; /* Width (8,16,32,64) */
unsigned char *bi_cmdline; /* Pointer to command line */
} bd_t;
I should probably migrate to U-boot anyway, but still ..
--
Bye, Peter Korsgaard
^ permalink raw reply
* Re: [PATCH 2/5] [PPC] Merge common virtex header files
From: Grant Likely @ 2007-04-30 4:41 UTC (permalink / raw)
To: Peter Korsgaard; +Cc: linuxppc-embedded
In-Reply-To: <87slai5vz3.fsf@sleipner.barco.com>
On 4/29/07, Peter Korsgaard <peter.korsgaard@barco.com> wrote:
> >>>>> "GL" == Grant Likely <grant.likely@secretlab.ca> writes:
>
> Hi,
>
> >> instead? I'm using RedBoot on a virtex platform, and hence another
> >> struct bd_info than the ML300/ML403.
>
> GL> Alternate suggestion: Can we change virtex support to use the
> GL> structure defined in ppcboot.h instead? (I've actually got that
> GL> change in my tree and was planning on posting it for review today
> GL> or tomorrow). bd_t is a stinking ugly mess, but things would be
> GL> better if we standardize all virtex platforms on the stinking ugly
> GL> mess shared by almost all the other ppc embedded board ports.
>
> That's where the ugly mess pops up - RedBoot uses another
> (incompatible) bd_t definition than U-boot, E.G:
Is the redboot bd_info structure already in the kernel tree? We could
use a config option to select between the u-boot and redboot
structures for all virtex platforms. That would keep the uglyness
down to a minimum.
g.
--
Grant Likely, B.Sc. P.Eng.
Secret Lab Technologies Ltd.
grant.likely@secretlab.ca
(403) 399-0195
^ permalink raw reply
* Re: [PATCH] powermac: proper sleep management
From: Paul Mackerras @ 2007-04-30 5:31 UTC (permalink / raw)
To: Johannes Berg; +Cc: linuxppc-dev
In-Reply-To: <1177767996.5102.9.camel@johannes.berg>
Johannes Berg writes:
> Are you serious? The only thing the generic code does here is invoke our
> stuff in the right order. That shouldn't be too much of a constraint. We
Yes I'm serious. At a quick look, the generic code is calling
freeze_processes and shrink_all_memory, and I don't see where it's
doing a sync. I really don't like the process freezer; as Linus
pointed out, it has caused more deadlocks than it solved.
Also, you're now calling pbook_alloc_pci_save after interrupts are
disabled, and it does a kmalloc(..., GFP_KERNEL). Oops.
Part of the problem is exactly what Linus pointed out: that the
generic code tries to use the same code paths for suspend to RAM and
suspend to disk, but they are two totally different things.
I have no objection to adding code to enable the generic code to do
the (mostly) right thing when you write "mem" into /sys/power/state.
I have no objection to code being refactored to eliminate
duplication. All I ask is that the PMU ioctls continue to do
essentially the same things in the same order.
Paul.
^ permalink raw reply
* Re: [PATCH] bootwrapper: CONFIG_ -> CONFIG_DEVICE_TREE
From: David Gibson @ 2007-04-30 5:35 UTC (permalink / raw)
To: Scott Wood; +Cc: linuxppc-dev, paulus
In-Reply-To: <20070427203215.GA12814@ld0162-tx32.am.freescale.net>
On Fri, Apr 27, 2007 at 03:32:15PM -0500, Scott Wood wrote:
> A usage of CONFIG_DEVICE_TREE got accidentally truncated; this
> fix allows out-of-tree dts files to work.
>
> Signed-off-by: Scott Wood <scottwood@freescale.com>
Acked-by: David Gibson <david@gibson.dropbear.id.au>
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
^ permalink raw reply
* powerpc: Fix STRICT_MM_TYPECHECKS
From: David Gibson @ 2007-04-30 5:37 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev
Since we don't have it active by default, the STRICT_MM_TYPECHECKS
option has bitrotted again. This patch fixes a couple of simple build
fixes if the option is selected. First, pud_t mustn't be defined in
page.h on 32-bit systems, because it conflicts with the version in the
generic pud-folding code. Second, pci_32.c is missing a __pgprot()
wrapper call. Third, a couple of PS3 files use constants of type
pgprot_t when they need the raw values, we add pgprot_val() calls to
fix this.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
arch/powerpc/kernel/pci_32.c | 2 +-
arch/powerpc/platforms/ps3/htab.c | 3 ++-
arch/powerpc/platforms/ps3/spu.c | 2 +-
include/asm-powerpc/page.h | 2 +-
4 files changed, 5 insertions(+), 4 deletions(-)
Index: working-2.6/include/asm-powerpc/page.h
===================================================================
--- working-2.6.orig/include/asm-powerpc/page.h 2007-04-30 15:33:05.000000000 +1000
+++ working-2.6/include/asm-powerpc/page.h 2007-04-30 15:36:20.000000000 +1000
@@ -126,7 +126,7 @@ typedef struct { unsigned long pmd; } pm
#define __pmd(x) ((pmd_t) { (x) })
/* PUD level exusts only on 4k pages */
-#ifndef CONFIG_PPC_64K_PAGES
+#if defined(CONFIG_PPC64) && !defined(CONFIG_PPC_64K_PAGES)
typedef struct { unsigned long pud; } pud_t;
#define pud_val(x) ((x).pud)
#define __pud(x) ((pud_t) { (x) })
Index: working-2.6/arch/powerpc/kernel/pci_32.c
===================================================================
--- working-2.6.orig/arch/powerpc/kernel/pci_32.c 2007-04-30 15:33:00.000000000 +1000
+++ working-2.6/arch/powerpc/kernel/pci_32.c 2007-04-30 15:33:11.000000000 +1000
@@ -1658,7 +1658,7 @@ pgprot_t pci_phys_mem_access_prot(struct
int i;
if (page_is_ram(pfn))
- return prot;
+ return __pgprot(prot);
prot |= _PAGE_NO_CACHE | _PAGE_GUARDED;
Index: working-2.6/arch/powerpc/platforms/ps3/spu.c
===================================================================
--- working-2.6.orig/arch/powerpc/platforms/ps3/spu.c 2007-04-30 15:33:00.000000000 +1000
+++ working-2.6/arch/powerpc/platforms/ps3/spu.c 2007-04-30 15:33:11.000000000 +1000
@@ -184,7 +184,7 @@ static int __init setup_areas(struct spu
spu_pdata(spu)->shadow = __ioremap(
spu_pdata(spu)->shadow_addr, sizeof(struct spe_shadow),
- PAGE_READONLY | _PAGE_NO_CACHE | _PAGE_GUARDED);
+ pgprot_val(PAGE_READONLY) | _PAGE_NO_CACHE | _PAGE_GUARDED);
if (!spu_pdata(spu)->shadow) {
pr_debug("%s:%d: ioremap shadow failed\n", __func__, __LINE__);
goto fail_ioremap;
Index: working-2.6/arch/powerpc/platforms/ps3/htab.c
===================================================================
--- working-2.6.orig/arch/powerpc/platforms/ps3/htab.c 2007-04-30 15:33:01.000000000 +1000
+++ working-2.6/arch/powerpc/platforms/ps3/htab.c 2007-04-30 15:33:11.000000000 +1000
@@ -273,7 +273,8 @@ void __init ps3_map_htab(void)
result = lv1_map_htab(0, &htab_addr);
- htab = (hpte_t *)__ioremap(htab_addr, htab_size, PAGE_READONLY_X);
+ htab = (hpte_t *)__ioremap(htab_addr, htab_size,
+ pgprot_val(PAGE_READONLY_X));
DBG("%s:%d: lpar %016lxh, virt %016lxh\n", __func__, __LINE__,
htab_addr, (unsigned long)htab);
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
^ permalink raw reply
* powerpc: Remove arch/powerpc's dependence on asm-ppc/pg{alloc, table}.h
From: David Gibson @ 2007-04-30 5:37 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev
Currently, all 32-bit powerpc platforms use asm-ppc/pgtable.h and
asm-ppc/pgalloc.h, even when otherwise compiled with ARCH=powerpc.
Those asm-ppc files are a fairly nasty tangle of #ifdefs including a
bunch of things which shouldn't be necessary any more in arch/powerpc.
Cleaning up that mess is going to take a while, but this patch is a
first step. It separates the asm-powerpc/pg{alloc,table}.h into 64
bit and 32 bit versions in asm-powerpc, which the basic .h files in
asm-powerpc select based on config. We make a few tiny tweaks to the
innards of the files along the way, making the outermost ifdefs
(double-inclusion protection and __KERNEL__) a little cleaner, and
#including asm-generic/pgtable.h from the top-level
asm-powerpc/pgtable.h (since both the old 32-bit and 64-bit versions
ended with such an #include).
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
include/asm-powerpc/pgalloc-32.h | 41 +
include/asm-powerpc/pgalloc-64.h | 152 ++++++
include/asm-powerpc/pgalloc.h | 154 ------
include/asm-powerpc/pgtable-4k.h | 3
include/asm-powerpc/pgtable-64k.h | 5
include/asm-powerpc/pgtable-ppc32.h | 838 ++++++++++++++++++++++++++++++++++++
include/asm-powerpc/pgtable-ppc64.h | 492 +++++++++++++++++++++
include/asm-powerpc/pgtable.h | 493 ---------------------
8 files changed, 1532 insertions(+), 646 deletions(-)
Index: working-2.6/include/asm-powerpc/pgtable.h
===================================================================
--- working-2.6.orig/include/asm-powerpc/pgtable.h 2007-04-30 15:36:22.000000000 +1000
+++ working-2.6/include/asm-powerpc/pgtable.h 2007-04-30 15:36:29.000000000 +1000
@@ -2,502 +2,15 @@
#define _ASM_POWERPC_PGTABLE_H
#ifdef __KERNEL__
-#ifndef CONFIG_PPC64
-#include <asm-ppc/pgtable.h>
+#if defined(CONFIG_PPC64)
+# include <asm/pgtable-ppc64.h>
#else
-
-/*
- * This file contains the functions and defines necessary to modify and use
- * the ppc64 hashed page table.
- */
-
-#ifndef __ASSEMBLY__
-#include <linux/stddef.h>
-#include <asm/processor.h> /* For TASK_SIZE */
-#include <asm/mmu.h>
-#include <asm/page.h>
-#include <asm/tlbflush.h>
-struct mm_struct;
-#endif /* __ASSEMBLY__ */
-
-#ifdef CONFIG_PPC_64K_PAGES
-#include <asm/pgtable-64k.h>
-#else
-#include <asm/pgtable-4k.h>
-#endif
-
-#define FIRST_USER_ADDRESS 0
-
-/*
- * Size of EA range mapped by our pagetables.
- */
-#define PGTABLE_EADDR_SIZE (PTE_INDEX_SIZE + PMD_INDEX_SIZE + \
- PUD_INDEX_SIZE + PGD_INDEX_SIZE + PAGE_SHIFT)
-#define PGTABLE_RANGE (1UL << PGTABLE_EADDR_SIZE)
-
-#if TASK_SIZE_USER64 > PGTABLE_RANGE
-#error TASK_SIZE_USER64 exceeds pagetable range
-#endif
-
-#if TASK_SIZE_USER64 > (1UL << (USER_ESID_BITS + SID_SHIFT))
-#error TASK_SIZE_USER64 exceeds user VSID range
+# include <asm/pgtable-ppc32.h>
#endif
-/*
- * Define the address range of the vmalloc VM area.
- */
-#define VMALLOC_START ASM_CONST(0xD000000000000000)
-#define VMALLOC_SIZE ASM_CONST(0x80000000000)
-#define VMALLOC_END (VMALLOC_START + VMALLOC_SIZE)
-
-/*
- * Define the address range of the imalloc VM area.
- */
-#define PHBS_IO_BASE VMALLOC_END
-#define IMALLOC_BASE (PHBS_IO_BASE + 0x80000000ul) /* Reserve 2 gigs for PHBs */
-#define IMALLOC_END (VMALLOC_START + PGTABLE_RANGE)
-
-/*
- * Region IDs
- */
-#define REGION_SHIFT 60UL
-#define REGION_MASK (0xfUL << REGION_SHIFT)
-#define REGION_ID(ea) (((unsigned long)(ea)) >> REGION_SHIFT)
-
-#define VMALLOC_REGION_ID (REGION_ID(VMALLOC_START))
-#define KERNEL_REGION_ID (REGION_ID(PAGE_OFFSET))
-#define USER_REGION_ID (0UL)
-
-/*
- * Common bits in a linux-style PTE. These match the bits in the
- * (hardware-defined) PowerPC PTE as closely as possible. Additional
- * bits may be defined in pgtable-*.h
- */
-#define _PAGE_PRESENT 0x0001 /* software: pte contains a translation */
-#define _PAGE_USER 0x0002 /* matches one of the PP bits */
-#define _PAGE_FILE 0x0002 /* (!present only) software: pte holds file offset */
-#define _PAGE_EXEC 0x0004 /* No execute on POWER4 and newer (we invert) */
-#define _PAGE_GUARDED 0x0008
-#define _PAGE_COHERENT 0x0010 /* M: enforce memory coherence (SMP systems) */
-#define _PAGE_NO_CACHE 0x0020 /* I: cache inhibit */
-#define _PAGE_WRITETHRU 0x0040 /* W: cache write-through */
-#define _PAGE_DIRTY 0x0080 /* C: page changed */
-#define _PAGE_ACCESSED 0x0100 /* R: page referenced */
-#define _PAGE_RW 0x0200 /* software: user write access allowed */
-#define _PAGE_HASHPTE 0x0400 /* software: pte has an associated HPTE */
-#define _PAGE_BUSY 0x0800 /* software: PTE & hash are busy */
-
-#define _PAGE_BASE (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_COHERENT)
-
-#define _PAGE_WRENABLE (_PAGE_RW | _PAGE_DIRTY)
-
-/* __pgprot defined in asm-powerpc/page.h */
-#define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED)
-
-#define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_RW | _PAGE_USER)
-#define PAGE_SHARED_X __pgprot(_PAGE_BASE | _PAGE_RW | _PAGE_USER | _PAGE_EXEC)
-#define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_USER)
-#define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
-#define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_USER)
-#define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
-#define PAGE_KERNEL __pgprot(_PAGE_BASE | _PAGE_WRENABLE)
-#define PAGE_KERNEL_CI __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \
- _PAGE_WRENABLE | _PAGE_NO_CACHE | _PAGE_GUARDED)
-#define PAGE_KERNEL_EXEC __pgprot(_PAGE_BASE | _PAGE_WRENABLE | _PAGE_EXEC)
-
-#define PAGE_AGP __pgprot(_PAGE_BASE | _PAGE_WRENABLE | _PAGE_NO_CACHE)
-#define HAVE_PAGE_AGP
-
-/* PTEIDX nibble */
-#define _PTEIDX_SECONDARY 0x8
-#define _PTEIDX_GROUP_IX 0x7
-
-
-/*
- * POWER4 and newer have per page execute protection, older chips can only
- * do this on a segment (256MB) basis.
- *
- * Also, write permissions imply read permissions.
- * This is the closest we can get..
- *
- * Note due to the way vm flags are laid out, the bits are XWR
- */
-#define __P000 PAGE_NONE
-#define __P001 PAGE_READONLY
-#define __P010 PAGE_COPY
-#define __P011 PAGE_COPY
-#define __P100 PAGE_READONLY_X
-#define __P101 PAGE_READONLY_X
-#define __P110 PAGE_COPY_X
-#define __P111 PAGE_COPY_X
-
-#define __S000 PAGE_NONE
-#define __S001 PAGE_READONLY
-#define __S010 PAGE_SHARED
-#define __S011 PAGE_SHARED
-#define __S100 PAGE_READONLY_X
-#define __S101 PAGE_READONLY_X
-#define __S110 PAGE_SHARED_X
-#define __S111 PAGE_SHARED_X
-
#ifndef __ASSEMBLY__
-
-/*
- * ZERO_PAGE is a global shared page that is always zero: used
- * for zero-mapped memory areas etc..
- */
-extern unsigned long empty_zero_page[PAGE_SIZE/sizeof(unsigned long)];
-#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
-#endif /* __ASSEMBLY__ */
-
-#ifdef CONFIG_HUGETLB_PAGE
-
-#define HAVE_ARCH_UNMAPPED_AREA
-#define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
-
-#endif
-
-#ifndef __ASSEMBLY__
-
-/*
- * Conversion functions: convert a page and protection to a page entry,
- * and a page entry and page directory to the page they refer to.
- *
- * mk_pte takes a (struct page *) as input
- */
-#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
-
-static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot)
-{
- pte_t pte;
-
-
- pte_val(pte) = (pfn << PTE_RPN_SHIFT) | pgprot_val(pgprot);
- return pte;
-}
-
-#define pte_modify(_pte, newprot) \
- (__pte((pte_val(_pte) & _PAGE_CHG_MASK) | pgprot_val(newprot)))
-
-#define pte_none(pte) ((pte_val(pte) & ~_PAGE_HPTEFLAGS) == 0)
-#define pte_present(pte) (pte_val(pte) & _PAGE_PRESENT)
-
-/* pte_clear moved to later in this file */
-
-#define pte_pfn(x) ((unsigned long)((pte_val(x)>>PTE_RPN_SHIFT)))
-#define pte_page(x) pfn_to_page(pte_pfn(x))
-
-#define PMD_BAD_BITS (PTE_TABLE_SIZE-1)
-#define PUD_BAD_BITS (PMD_TABLE_SIZE-1)
-
-#define pmd_set(pmdp, pmdval) (pmd_val(*(pmdp)) = (pmdval))
-#define pmd_none(pmd) (!pmd_val(pmd))
-#define pmd_bad(pmd) (!is_kernel_addr(pmd_val(pmd)) \
- || (pmd_val(pmd) & PMD_BAD_BITS))
-#define pmd_present(pmd) (pmd_val(pmd) != 0)
-#define pmd_clear(pmdp) (pmd_val(*(pmdp)) = 0)
-#define pmd_page_vaddr(pmd) (pmd_val(pmd) & ~PMD_MASKED_BITS)
-#define pmd_page(pmd) virt_to_page(pmd_page_vaddr(pmd))
-
-#define pud_set(pudp, pudval) (pud_val(*(pudp)) = (pudval))
-#define pud_none(pud) (!pud_val(pud))
-#define pud_bad(pud) (!is_kernel_addr(pud_val(pud)) \
- || (pud_val(pud) & PUD_BAD_BITS))
-#define pud_present(pud) (pud_val(pud) != 0)
-#define pud_clear(pudp) (pud_val(*(pudp)) = 0)
-#define pud_page_vaddr(pud) (pud_val(pud) & ~PUD_MASKED_BITS)
-#define pud_page(pud) virt_to_page(pud_page_vaddr(pud))
-
-#define pgd_set(pgdp, pudp) ({pgd_val(*(pgdp)) = (unsigned long)(pudp);})
-
-/*
- * Find an entry in a page-table-directory. We combine the address region
- * (the high order N bits) and the pgd portion of the address.
- */
-/* to avoid overflow in free_pgtables we don't use PTRS_PER_PGD here */
-#define pgd_index(address) (((address) >> (PGDIR_SHIFT)) & 0x1ff)
-
-#define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
-
-#define pmd_offset(pudp,addr) \
- (((pmd_t *) pud_page_vaddr(*(pudp))) + (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1)))
-
-#define pte_offset_kernel(dir,addr) \
- (((pte_t *) pmd_page_vaddr(*(dir))) + (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)))
-
-#define pte_offset_map(dir,addr) pte_offset_kernel((dir), (addr))
-#define pte_offset_map_nested(dir,addr) pte_offset_kernel((dir), (addr))
-#define pte_unmap(pte) do { } while(0)
-#define pte_unmap_nested(pte) do { } while(0)
-
-/* to find an entry in a kernel page-table-directory */
-/* This now only contains the vmalloc pages */
-#define pgd_offset_k(address) pgd_offset(&init_mm, address)
-
-/*
- * The following only work if pte_present() is true.
- * Undefined behaviour if not..
- */
-static inline int pte_read(pte_t pte) { return pte_val(pte) & _PAGE_USER;}
-static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_RW;}
-static inline int pte_exec(pte_t pte) { return pte_val(pte) & _PAGE_EXEC;}
-static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY;}
-static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED;}
-static inline int pte_file(pte_t pte) { return pte_val(pte) & _PAGE_FILE;}
-
-static inline void pte_uncache(pte_t pte) { pte_val(pte) |= _PAGE_NO_CACHE; }
-static inline void pte_cache(pte_t pte) { pte_val(pte) &= ~_PAGE_NO_CACHE; }
-
-static inline pte_t pte_rdprotect(pte_t pte) {
- pte_val(pte) &= ~_PAGE_USER; return pte; }
-static inline pte_t pte_exprotect(pte_t pte) {
- pte_val(pte) &= ~_PAGE_EXEC; return pte; }
-static inline pte_t pte_wrprotect(pte_t pte) {
- pte_val(pte) &= ~(_PAGE_RW); return pte; }
-static inline pte_t pte_mkclean(pte_t pte) {
- pte_val(pte) &= ~(_PAGE_DIRTY); return pte; }
-static inline pte_t pte_mkold(pte_t pte) {
- pte_val(pte) &= ~_PAGE_ACCESSED; return pte; }
-static inline pte_t pte_mkread(pte_t pte) {
- pte_val(pte) |= _PAGE_USER; return pte; }
-static inline pte_t pte_mkexec(pte_t pte) {
- pte_val(pte) |= _PAGE_USER | _PAGE_EXEC; return pte; }
-static inline pte_t pte_mkwrite(pte_t pte) {
- pte_val(pte) |= _PAGE_RW; return pte; }
-static inline pte_t pte_mkdirty(pte_t pte) {
- pte_val(pte) |= _PAGE_DIRTY; return pte; }
-static inline pte_t pte_mkyoung(pte_t pte) {
- pte_val(pte) |= _PAGE_ACCESSED; return pte; }
-static inline pte_t pte_mkhuge(pte_t pte) {
- return pte; }
-
-/* Atomic PTE updates */
-static inline unsigned long pte_update(struct mm_struct *mm,
- unsigned long addr,
- pte_t *ptep, unsigned long clr,
- int huge)
-{
- unsigned long old, tmp;
-
- __asm__ __volatile__(
- "1: ldarx %0,0,%3 # pte_update\n\
- andi. %1,%0,%6\n\
- bne- 1b \n\
- andc %1,%0,%4 \n\
- stdcx. %1,0,%3 \n\
- bne- 1b"
- : "=&r" (old), "=&r" (tmp), "=m" (*ptep)
- : "r" (ptep), "r" (clr), "m" (*ptep), "i" (_PAGE_BUSY)
- : "cc" );
-
- if (old & _PAGE_HASHPTE)
- hpte_need_flush(mm, addr, ptep, old, huge);
- return old;
-}
-
-static inline int __ptep_test_and_clear_young(struct mm_struct *mm,
- unsigned long addr, pte_t *ptep)
-{
- unsigned long old;
-
- if ((pte_val(*ptep) & (_PAGE_ACCESSED | _PAGE_HASHPTE)) == 0)
- return 0;
- old = pte_update(mm, addr, ptep, _PAGE_ACCESSED, 0);
- return (old & _PAGE_ACCESSED) != 0;
-}
-#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
-#define ptep_test_and_clear_young(__vma, __addr, __ptep) \
-({ \
- int __r; \
- __r = __ptep_test_and_clear_young((__vma)->vm_mm, __addr, __ptep); \
- __r; \
-})
-
-/*
- * On RW/DIRTY bit transitions we can avoid flushing the hpte. For the
- * moment we always flush but we need to fix hpte_update and test if the
- * optimisation is worth it.
- */
-static inline int __ptep_test_and_clear_dirty(struct mm_struct *mm,
- unsigned long addr, pte_t *ptep)
-{
- unsigned long old;
-
- if ((pte_val(*ptep) & _PAGE_DIRTY) == 0)
- return 0;
- old = pte_update(mm, addr, ptep, _PAGE_DIRTY, 0);
- return (old & _PAGE_DIRTY) != 0;
-}
-#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_DIRTY
-#define ptep_test_and_clear_dirty(__vma, __addr, __ptep) \
-({ \
- int __r; \
- __r = __ptep_test_and_clear_dirty((__vma)->vm_mm, __addr, __ptep); \
- __r; \
-})
-
-#define __HAVE_ARCH_PTEP_SET_WRPROTECT
-static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr,
- pte_t *ptep)
-{
- unsigned long old;
-
- if ((pte_val(*ptep) & _PAGE_RW) == 0)
- return;
- old = pte_update(mm, addr, ptep, _PAGE_RW, 0);
-}
-
-/*
- * We currently remove entries from the hashtable regardless of whether
- * the entry was young or dirty. The generic routines only flush if the
- * entry was young or dirty which is not good enough.
- *
- * We should be more intelligent about this but for the moment we override
- * these functions and force a tlb flush unconditionally
- */
-#define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH
-#define ptep_clear_flush_young(__vma, __address, __ptep) \
-({ \
- int __young = __ptep_test_and_clear_young((__vma)->vm_mm, __address, \
- __ptep); \
- __young; \
-})
-
-#define __HAVE_ARCH_PTEP_CLEAR_DIRTY_FLUSH
-#define ptep_clear_flush_dirty(__vma, __address, __ptep) \
-({ \
- int __dirty = __ptep_test_and_clear_dirty((__vma)->vm_mm, __address, \
- __ptep); \
- __dirty; \
-})
-
-#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
-static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
- unsigned long addr, pte_t *ptep)
-{
- unsigned long old = pte_update(mm, addr, ptep, ~0UL, 0);
- return __pte(old);
-}
-
-static inline void pte_clear(struct mm_struct *mm, unsigned long addr,
- pte_t * ptep)
-{
- pte_update(mm, addr, ptep, ~0UL, 0);
-}
-
-/*
- * set_pte stores a linux PTE into the linux page table.
- */
-static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
- pte_t *ptep, pte_t pte)
-{
- if (pte_present(*ptep))
- pte_clear(mm, addr, ptep);
- pte = __pte(pte_val(pte) & ~_PAGE_HPTEFLAGS);
- *ptep = pte;
-}
-
-/* Set the dirty and/or accessed bits atomically in a linux PTE, this
- * function doesn't need to flush the hash entry
- */
-#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
-static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry, int dirty)
-{
- unsigned long bits = pte_val(entry) &
- (_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_RW | _PAGE_EXEC);
- unsigned long old, tmp;
-
- __asm__ __volatile__(
- "1: ldarx %0,0,%4\n\
- andi. %1,%0,%6\n\
- bne- 1b \n\
- or %0,%3,%0\n\
- stdcx. %0,0,%4\n\
- bne- 1b"
- :"=&r" (old), "=&r" (tmp), "=m" (*ptep)
- :"r" (bits), "r" (ptep), "m" (*ptep), "i" (_PAGE_BUSY)
- :"cc");
-}
-#define ptep_set_access_flags(__vma, __address, __ptep, __entry, __dirty) \
- do { \
- __ptep_set_access_flags(__ptep, __entry, __dirty); \
- flush_tlb_page_nohash(__vma, __address); \
- } while(0)
-
-/*
- * Macro to mark a page protection value as "uncacheable".
- */
-#define pgprot_noncached(prot) (__pgprot(pgprot_val(prot) | _PAGE_NO_CACHE | _PAGE_GUARDED))
-
-struct file;
-extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
- unsigned long size, pgprot_t vma_prot);
-#define __HAVE_PHYS_MEM_ACCESS_PROT
-
-#define __HAVE_ARCH_PTE_SAME
-#define pte_same(A,B) (((pte_val(A) ^ pte_val(B)) & ~_PAGE_HPTEFLAGS) == 0)
-
-#define pte_ERROR(e) \
- printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
-#define pmd_ERROR(e) \
- printk("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e))
-#define pgd_ERROR(e) \
- printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
-
-extern pgd_t swapper_pg_dir[];
-
-extern void paging_init(void);
-
-/* Encode and de-code a swap entry */
-#define __swp_type(entry) (((entry).val >> 1) & 0x3f)
-#define __swp_offset(entry) ((entry).val >> 8)
-#define __swp_entry(type, offset) ((swp_entry_t){((type)<< 1)|((offset)<<8)})
-#define __pte_to_swp_entry(pte) ((swp_entry_t){pte_val(pte) >> PTE_RPN_SHIFT})
-#define __swp_entry_to_pte(x) ((pte_t) { (x).val << PTE_RPN_SHIFT })
-#define pte_to_pgoff(pte) (pte_val(pte) >> PTE_RPN_SHIFT)
-#define pgoff_to_pte(off) ((pte_t) {((off) << PTE_RPN_SHIFT)|_PAGE_FILE})
-#define PTE_FILE_MAX_BITS (BITS_PER_LONG - PTE_RPN_SHIFT)
-
-/*
- * kern_addr_valid is intended to indicate whether an address is a valid
- * kernel address. Most 32-bit archs define it as always true (like this)
- * but most 64-bit archs actually perform a test. What should we do here?
- * The only use is in fs/ncpfs/dir.c
- */
-#define kern_addr_valid(addr) (1)
-
-#define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \
- remap_pfn_range(vma, vaddr, pfn, size, prot)
-
-void pgtable_cache_init(void);
-
-/*
- * find_linux_pte returns the address of a linux pte for a given
- * effective address and directory. If not found, it returns zero.
- */static inline pte_t *find_linux_pte(pgd_t *pgdir, unsigned long ea)
-{
- pgd_t *pg;
- pud_t *pu;
- pmd_t *pm;
- pte_t *pt = NULL;
-
- pg = pgdir + pgd_index(ea);
- if (!pgd_none(*pg)) {
- pu = pud_offset(pg, ea);
- if (!pud_none(*pu)) {
- pm = pmd_offset(pu, ea);
- if (pmd_present(*pm))
- pt = pte_offset_kernel(pm, ea);
- }
- }
- return pt;
-}
-
-
#include <asm-generic/pgtable.h>
-
#endif /* __ASSEMBLY__ */
-#endif /* CONFIG_PPC64 */
#endif /* __KERNEL__ */
#endif /* _ASM_POWERPC_PGTABLE_H */
Index: working-2.6/include/asm-powerpc/pgtable-4k.h
===================================================================
--- working-2.6.orig/include/asm-powerpc/pgtable-4k.h 2007-04-30 15:36:22.000000000 +1000
+++ working-2.6/include/asm-powerpc/pgtable-4k.h 2007-04-30 15:36:29.000000000 +1000
@@ -1,3 +1,5 @@
+#ifndef _ASM_POWERPC_PGTABLE_4K_H
+#define _ASM_POWERPC_PGTABLE_4K_H
/*
* Entries per page directory level. The PTE level must use a 64b record
* for each page table entry. The PMD and PGD level use a 32b record for
@@ -100,3 +102,4 @@
#define remap_4k_pfn(vma, addr, pfn, prot) \
remap_pfn_range((vma), (addr), (pfn), PAGE_SIZE, (prot))
+#endif /* _ASM_POWERPC_PGTABLE_4K_H */
Index: working-2.6/include/asm-powerpc/pgtable-64k.h
===================================================================
--- working-2.6.orig/include/asm-powerpc/pgtable-64k.h 2007-04-30 15:36:22.000000000 +1000
+++ working-2.6/include/asm-powerpc/pgtable-64k.h 2007-04-30 15:36:29.000000000 +1000
@@ -1,6 +1,5 @@
#ifndef _ASM_POWERPC_PGTABLE_64K_H
#define _ASM_POWERPC_PGTABLE_64K_H
-#ifdef __KERNEL__
#include <asm-generic/pgtable-nopud.h>
@@ -65,8 +64,6 @@
/* Bits to mask out from a PGD/PUD to get to the PMD page */
#define PUD_MASKED_BITS 0x1ff
-#ifndef __ASSEMBLY__
-
/* Manipulate "rpte" values */
#define __real_pte(e,p) ((real_pte_t) { \
(e), pte_val(*((p) + PTRS_PER_PTE)) })
@@ -98,6 +95,4 @@
remap_pfn_range((vma), (addr), (pfn), PAGE_SIZE, \
__pgprot(pgprot_val((prot)) | _PAGE_4K_PFN))
-#endif /* __ASSEMBLY__ */
-#endif /* __KERNEL__ */
#endif /* _ASM_POWERPC_PGTABLE_64K_H */
Index: working-2.6/include/asm-powerpc/pgtable-ppc64.h
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ working-2.6/include/asm-powerpc/pgtable-ppc64.h 2007-04-30 15:36:29.000000000 +1000
@@ -0,0 +1,492 @@
+#ifndef _ASM_POWERPC_PGTABLE_PPG64_H_
+#define _ASM_POWERPC_PGTABLE_PPC64_H_
+/*
+ * This file contains the functions and defines necessary to modify and use
+ * the ppc64 hashed page table.
+ */
+
+#ifndef __ASSEMBLY__
+#include <linux/stddef.h>
+#include <asm/processor.h> /* For TASK_SIZE */
+#include <asm/mmu.h>
+#include <asm/page.h>
+#include <asm/tlbflush.h>
+struct mm_struct;
+#endif /* __ASSEMBLY__ */
+
+#ifdef CONFIG_PPC_64K_PAGES
+#include <asm/pgtable-64k.h>
+#else
+#include <asm/pgtable-4k.h>
+#endif
+
+#define FIRST_USER_ADDRESS 0
+
+/*
+ * Size of EA range mapped by our pagetables.
+ */
+#define PGTABLE_EADDR_SIZE (PTE_INDEX_SIZE + PMD_INDEX_SIZE + \
+ PUD_INDEX_SIZE + PGD_INDEX_SIZE + PAGE_SHIFT)
+#define PGTABLE_RANGE (1UL << PGTABLE_EADDR_SIZE)
+
+#if TASK_SIZE_USER64 > PGTABLE_RANGE
+#error TASK_SIZE_USER64 exceeds pagetable range
+#endif
+
+#if TASK_SIZE_USER64 > (1UL << (USER_ESID_BITS + SID_SHIFT))
+#error TASK_SIZE_USER64 exceeds user VSID range
+#endif
+
+/*
+ * Define the address range of the vmalloc VM area.
+ */
+#define VMALLOC_START ASM_CONST(0xD000000000000000)
+#define VMALLOC_SIZE ASM_CONST(0x80000000000)
+#define VMALLOC_END (VMALLOC_START + VMALLOC_SIZE)
+
+/*
+ * Define the address range of the imalloc VM area.
+ */
+#define PHBS_IO_BASE VMALLOC_END
+#define IMALLOC_BASE (PHBS_IO_BASE + 0x80000000ul) /* Reserve 2 gigs for PHBs */
+#define IMALLOC_END (VMALLOC_START + PGTABLE_RANGE)
+
+/*
+ * Region IDs
+ */
+#define REGION_SHIFT 60UL
+#define REGION_MASK (0xfUL << REGION_SHIFT)
+#define REGION_ID(ea) (((unsigned long)(ea)) >> REGION_SHIFT)
+
+#define VMALLOC_REGION_ID (REGION_ID(VMALLOC_START))
+#define KERNEL_REGION_ID (REGION_ID(PAGE_OFFSET))
+#define USER_REGION_ID (0UL)
+
+/*
+ * Common bits in a linux-style PTE. These match the bits in the
+ * (hardware-defined) PowerPC PTE as closely as possible. Additional
+ * bits may be defined in pgtable-*.h
+ */
+#define _PAGE_PRESENT 0x0001 /* software: pte contains a translation */
+#define _PAGE_USER 0x0002 /* matches one of the PP bits */
+#define _PAGE_FILE 0x0002 /* (!present only) software: pte holds file offset */
+#define _PAGE_EXEC 0x0004 /* No execute on POWER4 and newer (we invert) */
+#define _PAGE_GUARDED 0x0008
+#define _PAGE_COHERENT 0x0010 /* M: enforce memory coherence (SMP systems) */
+#define _PAGE_NO_CACHE 0x0020 /* I: cache inhibit */
+#define _PAGE_WRITETHRU 0x0040 /* W: cache write-through */
+#define _PAGE_DIRTY 0x0080 /* C: page changed */
+#define _PAGE_ACCESSED 0x0100 /* R: page referenced */
+#define _PAGE_RW 0x0200 /* software: user write access allowed */
+#define _PAGE_HASHPTE 0x0400 /* software: pte has an associated HPTE */
+#define _PAGE_BUSY 0x0800 /* software: PTE & hash are busy */
+
+#define _PAGE_BASE (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_COHERENT)
+
+#define _PAGE_WRENABLE (_PAGE_RW | _PAGE_DIRTY)
+
+/* __pgprot defined in asm-powerpc/page.h */
+#define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED)
+
+#define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_RW | _PAGE_USER)
+#define PAGE_SHARED_X __pgprot(_PAGE_BASE | _PAGE_RW | _PAGE_USER | _PAGE_EXEC)
+#define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_USER)
+#define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
+#define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_USER)
+#define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
+#define PAGE_KERNEL __pgprot(_PAGE_BASE | _PAGE_WRENABLE)
+#define PAGE_KERNEL_CI __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \
+ _PAGE_WRENABLE | _PAGE_NO_CACHE | _PAGE_GUARDED)
+#define PAGE_KERNEL_EXEC __pgprot(_PAGE_BASE | _PAGE_WRENABLE | _PAGE_EXEC)
+
+#define PAGE_AGP __pgprot(_PAGE_BASE | _PAGE_WRENABLE | _PAGE_NO_CACHE)
+#define HAVE_PAGE_AGP
+
+/* PTEIDX nibble */
+#define _PTEIDX_SECONDARY 0x8
+#define _PTEIDX_GROUP_IX 0x7
+
+
+/*
+ * POWER4 and newer have per page execute protection, older chips can only
+ * do this on a segment (256MB) basis.
+ *
+ * Also, write permissions imply read permissions.
+ * This is the closest we can get..
+ *
+ * Note due to the way vm flags are laid out, the bits are XWR
+ */
+#define __P000 PAGE_NONE
+#define __P001 PAGE_READONLY
+#define __P010 PAGE_COPY
+#define __P011 PAGE_COPY
+#define __P100 PAGE_READONLY_X
+#define __P101 PAGE_READONLY_X
+#define __P110 PAGE_COPY_X
+#define __P111 PAGE_COPY_X
+
+#define __S000 PAGE_NONE
+#define __S001 PAGE_READONLY
+#define __S010 PAGE_SHARED
+#define __S011 PAGE_SHARED
+#define __S100 PAGE_READONLY_X
+#define __S101 PAGE_READONLY_X
+#define __S110 PAGE_SHARED_X
+#define __S111 PAGE_SHARED_X
+
+#ifndef __ASSEMBLY__
+
+/*
+ * ZERO_PAGE is a global shared page that is always zero: used
+ * for zero-mapped memory areas etc..
+ */
+extern unsigned long empty_zero_page[PAGE_SIZE/sizeof(unsigned long)];
+#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
+#endif /* __ASSEMBLY__ */
+
+#ifdef CONFIG_HUGETLB_PAGE
+
+#define HAVE_ARCH_UNMAPPED_AREA
+#define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
+
+#endif
+
+#ifndef __ASSEMBLY__
+
+/*
+ * Conversion functions: convert a page and protection to a page entry,
+ * and a page entry and page directory to the page they refer to.
+ *
+ * mk_pte takes a (struct page *) as input
+ */
+#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
+
+static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot)
+{
+ pte_t pte;
+
+
+ pte_val(pte) = (pfn << PTE_RPN_SHIFT) | pgprot_val(pgprot);
+ return pte;
+}
+
+#define pte_modify(_pte, newprot) \
+ (__pte((pte_val(_pte) & _PAGE_CHG_MASK) | pgprot_val(newprot)))
+
+#define pte_none(pte) ((pte_val(pte) & ~_PAGE_HPTEFLAGS) == 0)
+#define pte_present(pte) (pte_val(pte) & _PAGE_PRESENT)
+
+/* pte_clear moved to later in this file */
+
+#define pte_pfn(x) ((unsigned long)((pte_val(x)>>PTE_RPN_SHIFT)))
+#define pte_page(x) pfn_to_page(pte_pfn(x))
+
+#define PMD_BAD_BITS (PTE_TABLE_SIZE-1)
+#define PUD_BAD_BITS (PMD_TABLE_SIZE-1)
+
+#define pmd_set(pmdp, pmdval) (pmd_val(*(pmdp)) = (pmdval))
+#define pmd_none(pmd) (!pmd_val(pmd))
+#define pmd_bad(pmd) (!is_kernel_addr(pmd_val(pmd)) \
+ || (pmd_val(pmd) & PMD_BAD_BITS))
+#define pmd_present(pmd) (pmd_val(pmd) != 0)
+#define pmd_clear(pmdp) (pmd_val(*(pmdp)) = 0)
+#define pmd_page_vaddr(pmd) (pmd_val(pmd) & ~PMD_MASKED_BITS)
+#define pmd_page(pmd) virt_to_page(pmd_page_vaddr(pmd))
+
+#define pud_set(pudp, pudval) (pud_val(*(pudp)) = (pudval))
+#define pud_none(pud) (!pud_val(pud))
+#define pud_bad(pud) (!is_kernel_addr(pud_val(pud)) \
+ || (pud_val(pud) & PUD_BAD_BITS))
+#define pud_present(pud) (pud_val(pud) != 0)
+#define pud_clear(pudp) (pud_val(*(pudp)) = 0)
+#define pud_page_vaddr(pud) (pud_val(pud) & ~PUD_MASKED_BITS)
+#define pud_page(pud) virt_to_page(pud_page_vaddr(pud))
+
+#define pgd_set(pgdp, pudp) ({pgd_val(*(pgdp)) = (unsigned long)(pudp);})
+
+/*
+ * Find an entry in a page-table-directory. We combine the address region
+ * (the high order N bits) and the pgd portion of the address.
+ */
+/* to avoid overflow in free_pgtables we don't use PTRS_PER_PGD here */
+#define pgd_index(address) (((address) >> (PGDIR_SHIFT)) & 0x1ff)
+
+#define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
+
+#define pmd_offset(pudp,addr) \
+ (((pmd_t *) pud_page_vaddr(*(pudp))) + (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1)))
+
+#define pte_offset_kernel(dir,addr) \
+ (((pte_t *) pmd_page_vaddr(*(dir))) + (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)))
+
+#define pte_offset_map(dir,addr) pte_offset_kernel((dir), (addr))
+#define pte_offset_map_nested(dir,addr) pte_offset_kernel((dir), (addr))
+#define pte_unmap(pte) do { } while(0)
+#define pte_unmap_nested(pte) do { } while(0)
+
+/* to find an entry in a kernel page-table-directory */
+/* This now only contains the vmalloc pages */
+#define pgd_offset_k(address) pgd_offset(&init_mm, address)
+
+/*
+ * The following only work if pte_present() is true.
+ * Undefined behaviour if not..
+ */
+static inline int pte_read(pte_t pte) { return pte_val(pte) & _PAGE_USER;}
+static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_RW;}
+static inline int pte_exec(pte_t pte) { return pte_val(pte) & _PAGE_EXEC;}
+static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY;}
+static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED;}
+static inline int pte_file(pte_t pte) { return pte_val(pte) & _PAGE_FILE;}
+
+static inline void pte_uncache(pte_t pte) { pte_val(pte) |= _PAGE_NO_CACHE; }
+static inline void pte_cache(pte_t pte) { pte_val(pte) &= ~_PAGE_NO_CACHE; }
+
+static inline pte_t pte_rdprotect(pte_t pte) {
+ pte_val(pte) &= ~_PAGE_USER; return pte; }
+static inline pte_t pte_exprotect(pte_t pte) {
+ pte_val(pte) &= ~_PAGE_EXEC; return pte; }
+static inline pte_t pte_wrprotect(pte_t pte) {
+ pte_val(pte) &= ~(_PAGE_RW); return pte; }
+static inline pte_t pte_mkclean(pte_t pte) {
+ pte_val(pte) &= ~(_PAGE_DIRTY); return pte; }
+static inline pte_t pte_mkold(pte_t pte) {
+ pte_val(pte) &= ~_PAGE_ACCESSED; return pte; }
+static inline pte_t pte_mkread(pte_t pte) {
+ pte_val(pte) |= _PAGE_USER; return pte; }
+static inline pte_t pte_mkexec(pte_t pte) {
+ pte_val(pte) |= _PAGE_USER | _PAGE_EXEC; return pte; }
+static inline pte_t pte_mkwrite(pte_t pte) {
+ pte_val(pte) |= _PAGE_RW; return pte; }
+static inline pte_t pte_mkdirty(pte_t pte) {
+ pte_val(pte) |= _PAGE_DIRTY; return pte; }
+static inline pte_t pte_mkyoung(pte_t pte) {
+ pte_val(pte) |= _PAGE_ACCESSED; return pte; }
+static inline pte_t pte_mkhuge(pte_t pte) {
+ return pte; }
+
+/* Atomic PTE updates */
+static inline unsigned long pte_update(struct mm_struct *mm,
+ unsigned long addr,
+ pte_t *ptep, unsigned long clr,
+ int huge)
+{
+ unsigned long old, tmp;
+
+ __asm__ __volatile__(
+ "1: ldarx %0,0,%3 # pte_update\n\
+ andi. %1,%0,%6\n\
+ bne- 1b \n\
+ andc %1,%0,%4 \n\
+ stdcx. %1,0,%3 \n\
+ bne- 1b"
+ : "=&r" (old), "=&r" (tmp), "=m" (*ptep)
+ : "r" (ptep), "r" (clr), "m" (*ptep), "i" (_PAGE_BUSY)
+ : "cc" );
+
+ if (old & _PAGE_HASHPTE)
+ hpte_need_flush(mm, addr, ptep, old, huge);
+ return old;
+}
+
+static inline int __ptep_test_and_clear_young(struct mm_struct *mm,
+ unsigned long addr, pte_t *ptep)
+{
+ unsigned long old;
+
+ if ((pte_val(*ptep) & (_PAGE_ACCESSED | _PAGE_HASHPTE)) == 0)
+ return 0;
+ old = pte_update(mm, addr, ptep, _PAGE_ACCESSED, 0);
+ return (old & _PAGE_ACCESSED) != 0;
+}
+#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
+#define ptep_test_and_clear_young(__vma, __addr, __ptep) \
+({ \
+ int __r; \
+ __r = __ptep_test_and_clear_young((__vma)->vm_mm, __addr, __ptep); \
+ __r; \
+})
+
+/*
+ * On RW/DIRTY bit transitions we can avoid flushing the hpte. For the
+ * moment we always flush but we need to fix hpte_update and test if the
+ * optimisation is worth it.
+ */
+static inline int __ptep_test_and_clear_dirty(struct mm_struct *mm,
+ unsigned long addr, pte_t *ptep)
+{
+ unsigned long old;
+
+ if ((pte_val(*ptep) & _PAGE_DIRTY) == 0)
+ return 0;
+ old = pte_update(mm, addr, ptep, _PAGE_DIRTY, 0);
+ return (old & _PAGE_DIRTY) != 0;
+}
+#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_DIRTY
+#define ptep_test_and_clear_dirty(__vma, __addr, __ptep) \
+({ \
+ int __r; \
+ __r = __ptep_test_and_clear_dirty((__vma)->vm_mm, __addr, __ptep); \
+ __r; \
+})
+
+#define __HAVE_ARCH_PTEP_SET_WRPROTECT
+static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr,
+ pte_t *ptep)
+{
+ unsigned long old;
+
+ if ((pte_val(*ptep) & _PAGE_RW) == 0)
+ return;
+ old = pte_update(mm, addr, ptep, _PAGE_RW, 0);
+}
+
+/*
+ * We currently remove entries from the hashtable regardless of whether
+ * the entry was young or dirty. The generic routines only flush if the
+ * entry was young or dirty which is not good enough.
+ *
+ * We should be more intelligent about this but for the moment we override
+ * these functions and force a tlb flush unconditionally
+ */
+#define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH
+#define ptep_clear_flush_young(__vma, __address, __ptep) \
+({ \
+ int __young = __ptep_test_and_clear_young((__vma)->vm_mm, __address, \
+ __ptep); \
+ __young; \
+})
+
+#define __HAVE_ARCH_PTEP_CLEAR_DIRTY_FLUSH
+#define ptep_clear_flush_dirty(__vma, __address, __ptep) \
+({ \
+ int __dirty = __ptep_test_and_clear_dirty((__vma)->vm_mm, __address, \
+ __ptep); \
+ __dirty; \
+})
+
+#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
+static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
+ unsigned long addr, pte_t *ptep)
+{
+ unsigned long old = pte_update(mm, addr, ptep, ~0UL, 0);
+ return __pte(old);
+}
+
+static inline void pte_clear(struct mm_struct *mm, unsigned long addr,
+ pte_t * ptep)
+{
+ pte_update(mm, addr, ptep, ~0UL, 0);
+}
+
+/*
+ * set_pte stores a linux PTE into the linux page table.
+ */
+static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
+ pte_t *ptep, pte_t pte)
+{
+ if (pte_present(*ptep))
+ pte_clear(mm, addr, ptep);
+ pte = __pte(pte_val(pte) & ~_PAGE_HPTEFLAGS);
+ *ptep = pte;
+}
+
+/* Set the dirty and/or accessed bits atomically in a linux PTE, this
+ * function doesn't need to flush the hash entry
+ */
+#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
+static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry, int dirty)
+{
+ unsigned long bits = pte_val(entry) &
+ (_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_RW | _PAGE_EXEC);
+ unsigned long old, tmp;
+
+ __asm__ __volatile__(
+ "1: ldarx %0,0,%4\n\
+ andi. %1,%0,%6\n\
+ bne- 1b \n\
+ or %0,%3,%0\n\
+ stdcx. %0,0,%4\n\
+ bne- 1b"
+ :"=&r" (old), "=&r" (tmp), "=m" (*ptep)
+ :"r" (bits), "r" (ptep), "m" (*ptep), "i" (_PAGE_BUSY)
+ :"cc");
+}
+#define ptep_set_access_flags(__vma, __address, __ptep, __entry, __dirty) \
+ do { \
+ __ptep_set_access_flags(__ptep, __entry, __dirty); \
+ flush_tlb_page_nohash(__vma, __address); \
+ } while(0)
+
+/*
+ * Macro to mark a page protection value as "uncacheable".
+ */
+#define pgprot_noncached(prot) (__pgprot(pgprot_val(prot) | _PAGE_NO_CACHE | _PAGE_GUARDED))
+
+struct file;
+extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
+ unsigned long size, pgprot_t vma_prot);
+#define __HAVE_PHYS_MEM_ACCESS_PROT
+
+#define __HAVE_ARCH_PTE_SAME
+#define pte_same(A,B) (((pte_val(A) ^ pte_val(B)) & ~_PAGE_HPTEFLAGS) == 0)
+
+#define pte_ERROR(e) \
+ printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
+#define pmd_ERROR(e) \
+ printk("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e))
+#define pgd_ERROR(e) \
+ printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
+
+extern pgd_t swapper_pg_dir[];
+
+extern void paging_init(void);
+
+/* Encode and de-code a swap entry */
+#define __swp_type(entry) (((entry).val >> 1) & 0x3f)
+#define __swp_offset(entry) ((entry).val >> 8)
+#define __swp_entry(type, offset) ((swp_entry_t){((type)<< 1)|((offset)<<8)})
+#define __pte_to_swp_entry(pte) ((swp_entry_t){pte_val(pte) >> PTE_RPN_SHIFT})
+#define __swp_entry_to_pte(x) ((pte_t) { (x).val << PTE_RPN_SHIFT })
+#define pte_to_pgoff(pte) (pte_val(pte) >> PTE_RPN_SHIFT)
+#define pgoff_to_pte(off) ((pte_t) {((off) << PTE_RPN_SHIFT)|_PAGE_FILE})
+#define PTE_FILE_MAX_BITS (BITS_PER_LONG - PTE_RPN_SHIFT)
+
+/*
+ * kern_addr_valid is intended to indicate whether an address is a valid
+ * kernel address. Most 32-bit archs define it as always true (like this)
+ * but most 64-bit archs actually perform a test. What should we do here?
+ * The only use is in fs/ncpfs/dir.c
+ */
+#define kern_addr_valid(addr) (1)
+
+#define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \
+ remap_pfn_range(vma, vaddr, pfn, size, prot)
+
+void pgtable_cache_init(void);
+
+/*
+ * find_linux_pte returns the address of a linux pte for a given
+ * effective address and directory. If not found, it returns zero.
+ */static inline pte_t *find_linux_pte(pgd_t *pgdir, unsigned long ea)
+{
+ pgd_t *pg;
+ pud_t *pu;
+ pmd_t *pm;
+ pte_t *pt = NULL;
+
+ pg = pgdir + pgd_index(ea);
+ if (!pgd_none(*pg)) {
+ pu = pud_offset(pg, ea);
+ if (!pud_none(*pu)) {
+ pm = pmd_offset(pu, ea);
+ if (pmd_present(*pm))
+ pt = pte_offset_kernel(pm, ea);
+ }
+ }
+ return pt;
+}
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* _ASM_POWERPC_PGTABLE_PPC64_H_ */
Index: working-2.6/include/asm-powerpc/pgtable-ppc32.h
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ working-2.6/include/asm-powerpc/pgtable-ppc32.h 2007-04-30 15:36:29.000000000 +1000
@@ -0,0 +1,838 @@
+#ifndef _ASM_POWERPC_PGTABLE_PPC32_H
+#define _ASM_POWERPC_PGTABLE_PPC32_H
+
+#include <asm-generic/4level-fixup.h>
+
+#ifndef __ASSEMBLY__
+#include <linux/sched.h>
+#include <linux/threads.h>
+#include <asm/processor.h> /* For TASK_SIZE */
+#include <asm/mmu.h>
+#include <asm/page.h>
+#include <asm/io.h> /* For sub-arch specific PPC_PIN_SIZE */
+struct mm_struct;
+
+extern unsigned long va_to_phys(unsigned long address);
+extern pte_t *va_to_pte(unsigned long address);
+extern unsigned long ioremap_bot, ioremap_base;
+#endif /* __ASSEMBLY__ */
+
+/*
+ * The PowerPC MMU uses a hash table containing PTEs, together with
+ * a set of 16 segment registers (on 32-bit implementations), to define
+ * the virtual to physical address mapping.
+ *
+ * We use the hash table as an extended TLB, i.e. a cache of currently
+ * active mappings. We maintain a two-level page table tree, much
+ * like that used by the i386, for the sake of the Linux memory
+ * management code. Low-level assembler code in hashtable.S
+ * (procedure hash_page) is responsible for extracting ptes from the
+ * tree and putting them into the hash table when necessary, and
+ * updating the accessed and modified bits in the page table tree.
+ */
+
+/*
+ * The PowerPC MPC8xx uses a TLB with hardware assisted, software tablewalk.
+ * We also use the two level tables, but we can put the real bits in them
+ * needed for the TLB and tablewalk. These definitions require Mx_CTR.PPM = 0,
+ * Mx_CTR.PPCS = 0, and MD_CTR.TWAM = 1. The level 2 descriptor has
+ * additional page protection (when Mx_CTR.PPCS = 1) that allows TLB hit
+ * based upon user/super access. The TLB does not have accessed nor write
+ * protect. We assume that if the TLB get loaded with an entry it is
+ * accessed, and overload the changed bit for write protect. We use
+ * two bits in the software pte that are supposed to be set to zero in
+ * the TLB entry (24 and 25) for these indicators. Although the level 1
+ * descriptor contains the guarded and writethrough/copyback bits, we can
+ * set these at the page level since they get copied from the Mx_TWC
+ * register when the TLB entry is loaded. We will use bit 27 for guard, since
+ * that is where it exists in the MD_TWC, and bit 26 for writethrough.
+ * These will get masked from the level 2 descriptor at TLB load time, and
+ * copied to the MD_TWC before it gets loaded.
+ * Large page sizes added. We currently support two sizes, 4K and 8M.
+ * This also allows a TLB hander optimization because we can directly
+ * load the PMD into MD_TWC. The 8M pages are only used for kernel
+ * mapping of well known areas. The PMD (PGD) entries contain control
+ * flags in addition to the address, so care must be taken that the
+ * software no longer assumes these are only pointers.
+ */
+
+/*
+ * At present, all PowerPC 400-class processors share a similar TLB
+ * architecture. The instruction and data sides share a unified,
+ * 64-entry, fully-associative TLB which is maintained totally under
+ * software control. In addition, the instruction side has a
+ * hardware-managed, 4-entry, fully-associative TLB which serves as a
+ * first level to the shared TLB. These two TLBs are known as the UTLB
+ * and ITLB, respectively (see "mmu.h" for definitions).
+ */
+
+/*
+ * The normal case is that PTEs are 32-bits and we have a 1-page
+ * 1024-entry pgdir pointing to 1-page 1024-entry PTE pages. -- paulus
+ *
+ * For any >32-bit physical address platform, we can use the following
+ * two level page table layout where the pgdir is 8KB and the MS 13 bits
+ * are an index to the second level table. The combined pgdir/pmd first
+ * level has 2048 entries and the second level has 512 64-bit PTE entries.
+ * -Matt
+ */
+/* PMD_SHIFT determines the size of the area mapped by the PTE pages */
+#define PMD_SHIFT (PAGE_SHIFT + PTE_SHIFT)
+#define PMD_SIZE (1UL << PMD_SHIFT)
+#define PMD_MASK (~(PMD_SIZE-1))
+
+/* PGDIR_SHIFT determines what a top-level page table entry can map */
+#define PGDIR_SHIFT PMD_SHIFT
+#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
+#define PGDIR_MASK (~(PGDIR_SIZE-1))
+
+/*
+ * entries per page directory level: our page-table tree is two-level, so
+ * we don't really have any PMD directory.
+ */
+#define PTRS_PER_PTE (1 << PTE_SHIFT)
+#define PTRS_PER_PMD 1
+#define PTRS_PER_PGD (1 << (32 - PGDIR_SHIFT))
+
+#define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE)
+#define FIRST_USER_ADDRESS 0
+
+#define USER_PGD_PTRS (PAGE_OFFSET >> PGDIR_SHIFT)
+#define KERNEL_PGD_PTRS (PTRS_PER_PGD-USER_PGD_PTRS)
+
+#define pte_ERROR(e) \
+ printk("%s:%d: bad pte "PTE_FMT".\n", __FILE__, __LINE__, pte_val(e))
+#define pmd_ERROR(e) \
+ printk("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e))
+#define pgd_ERROR(e) \
+ printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
+
+/*
+ * Just any arbitrary offset to the start of the vmalloc VM area: the
+ * current 64MB value just means that there will be a 64MB "hole" after the
+ * physical memory until the kernel virtual memory starts. That means that
+ * any out-of-bounds memory accesses will hopefully be caught.
+ * The vmalloc() routines leaves a hole of 4kB between each vmalloced
+ * area for the same reason. ;)
+ *
+ * We no longer map larger than phys RAM with the BATs so we don't have
+ * to worry about the VMALLOC_OFFSET causing problems. We do have to worry
+ * about clashes between our early calls to ioremap() that start growing down
+ * from ioremap_base being run into the VM area allocations (growing upwards
+ * from VMALLOC_START). For this reason we have ioremap_bot to check when
+ * we actually run into our mappings setup in the early boot with the VM
+ * system. This really does become a problem for machines with good amounts
+ * of RAM. -- Cort
+ */
+#define VMALLOC_OFFSET (0x1000000) /* 16M */
+#ifdef PPC_PIN_SIZE
+#define VMALLOC_START (((_ALIGN((long)high_memory, PPC_PIN_SIZE) + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)))
+#else
+#define VMALLOC_START ((((long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)))
+#endif
+#define VMALLOC_END ioremap_bot
+
+/*
+ * Bits in a linux-style PTE. These match the bits in the
+ * (hardware-defined) PowerPC PTE as closely as possible.
+ */
+
+#if defined(CONFIG_40x)
+
+/* There are several potential gotchas here. The 40x hardware TLBLO
+ field looks like this:
+
+ 0 1 2 3 4 ... 18 19 20 21 22 23 24 25 26 27 28 29 30 31
+ RPN..................... 0 0 EX WR ZSEL....... W I M G
+
+ Where possible we make the Linux PTE bits match up with this
+
+ - bits 20 and 21 must be cleared, because we use 4k pages (40x can
+ support down to 1k pages), this is done in the TLBMiss exception
+ handler.
+ - We use only zones 0 (for kernel pages) and 1 (for user pages)
+ of the 16 available. Bit 24-26 of the TLB are cleared in the TLB
+ miss handler. Bit 27 is PAGE_USER, thus selecting the correct
+ zone.
+ - PRESENT *must* be in the bottom two bits because swap cache
+ entries use the top 30 bits. Because 40x doesn't support SMP
+ anyway, M is irrelevant so we borrow it for PAGE_PRESENT. Bit 30
+ is cleared in the TLB miss handler before the TLB entry is loaded.
+ - All other bits of the PTE are loaded into TLBLO without
+ modification, leaving us only the bits 20, 21, 24, 25, 26, 30 for
+ software PTE bits. We actually use use bits 21, 24, 25, and
+ 30 respectively for the software bits: ACCESSED, DIRTY, RW, and
+ PRESENT.
+*/
+
+/* Definitions for 40x embedded chips. */
+#define _PAGE_GUARDED 0x001 /* G: page is guarded from prefetch */
+#define _PAGE_FILE 0x001 /* when !present: nonlinear file mapping */
+#define _PAGE_PRESENT 0x002 /* software: PTE contains a translation */
+#define _PAGE_NO_CACHE 0x004 /* I: caching is inhibited */
+#define _PAGE_WRITETHRU 0x008 /* W: caching is write-through */
+#define _PAGE_USER 0x010 /* matches one of the zone permission bits */
+#define _PAGE_RW 0x040 /* software: Writes permitted */
+#define _PAGE_DIRTY 0x080 /* software: dirty page */
+#define _PAGE_HWWRITE 0x100 /* hardware: Dirty & RW, set in exception */
+#define _PAGE_HWEXEC 0x200 /* hardware: EX permission */
+#define _PAGE_ACCESSED 0x400 /* software: R: page referenced */
+
+#define _PMD_PRESENT 0x400 /* PMD points to page of PTEs */
+#define _PMD_BAD 0x802
+#define _PMD_SIZE 0x0e0 /* size field, != 0 for large-page PMD entry */
+#define _PMD_SIZE_4M 0x0c0
+#define _PMD_SIZE_16M 0x0e0
+#define PMD_PAGE_SIZE(pmdval) (1024 << (((pmdval) & _PMD_SIZE) >> 4))
+
+#elif defined(CONFIG_44x)
+/*
+ * Definitions for PPC440
+ *
+ * Because of the 3 word TLB entries to support 36-bit addressing,
+ * the attribute are difficult to map in such a fashion that they
+ * are easily loaded during exception processing. I decided to
+ * organize the entry so the ERPN is the only portion in the
+ * upper word of the PTE and the attribute bits below are packed
+ * in as sensibly as they can be in the area below a 4KB page size
+ * oriented RPN. This at least makes it easy to load the RPN and
+ * ERPN fields in the TLB. -Matt
+ *
+ * Note that these bits preclude future use of a page size
+ * less than 4KB.
+ *
+ *
+ * PPC 440 core has following TLB attribute fields;
+ *
+ * TLB1:
+ * 0 1 2 3 4 ... 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
+ * RPN................................. - - - - - - ERPN.......
+ *
+ * TLB2:
+ * 0 1 2 3 4 ... 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
+ * - - - - - - U0 U1 U2 U3 W I M G E - UX UW UR SX SW SR
+ *
+ * There are some constrains and options, to decide mapping software bits
+ * into TLB entry.
+ *
+ * - PRESENT *must* be in the bottom three bits because swap cache
+ * entries use the top 29 bits for TLB2.
+ *
+ * - FILE *must* be in the bottom three bits because swap cache
+ * entries use the top 29 bits for TLB2.
+ *
+ * - CACHE COHERENT bit (M) has no effect on PPC440 core, because it
+ * doesn't support SMP. So we can use this as software bit, like
+ * DIRTY.
+ *
+ * With the PPC 44x Linux implementation, the 0-11th LSBs of the PTE are used
+ * for memory protection related functions (see PTE structure in
+ * include/asm-ppc/mmu.h). The _PAGE_XXX definitions in this file map to the
+ * above bits. Note that the bit values are CPU specific, not architecture
+ * specific.
+ *
+ * The kernel PTE entry holds an arch-dependent swp_entry structure under
+ * certain situations. In other words, in such situations some portion of
+ * the PTE bits are used as a swp_entry. In the PPC implementation, the
+ * 3-24th LSB are shared with swp_entry, however the 0-2nd three LSB still
+ * hold protection values. That means the three protection bits are
+ * reserved for both PTE and SWAP entry at the most significant three
+ * LSBs.
+ *
+ * There are three protection bits available for SWAP entry:
+ * _PAGE_PRESENT
+ * _PAGE_FILE
+ * _PAGE_HASHPTE (if HW has)
+ *
+ * So those three bits have to be inside of 0-2nd LSB of PTE.
+ *
+ */
+
+#define _PAGE_PRESENT 0x00000001 /* S: PTE valid */
+#define _PAGE_RW 0x00000002 /* S: Write permission */
+#define _PAGE_FILE 0x00000004 /* S: nonlinear file mapping */
+#define _PAGE_ACCESSED 0x00000008 /* S: Page referenced */
+#define _PAGE_HWWRITE 0x00000010 /* H: Dirty & RW */
+#define _PAGE_HWEXEC 0x00000020 /* H: Execute permission */
+#define _PAGE_USER 0x00000040 /* S: User page */
+#define _PAGE_ENDIAN 0x00000080 /* H: E bit */
+#define _PAGE_GUARDED 0x00000100 /* H: G bit */
+#define _PAGE_DIRTY 0x00000200 /* S: Page dirty */
+#define _PAGE_NO_CACHE 0x00000400 /* H: I bit */
+#define _PAGE_WRITETHRU 0x00000800 /* H: W bit */
+
+/* TODO: Add large page lowmem mapping support */
+#define _PMD_PRESENT 0
+#define _PMD_PRESENT_MASK (PAGE_MASK)
+#define _PMD_BAD (~PAGE_MASK)
+
+/* ERPN in a PTE never gets cleared, ignore it */
+#define _PTE_NONE_MASK 0xffffffff00000000ULL
+
+#elif defined(CONFIG_FSL_BOOKE)
+/*
+ MMU Assist Register 3:
+
+ 32 33 34 35 36 ... 50 51 52 53 54 55 56 57 58 59 60 61 62 63
+ RPN...................... 0 0 U0 U1 U2 U3 UX SX UW SW UR SR
+
+ - PRESENT *must* be in the bottom three bits because swap cache
+ entries use the top 29 bits.
+
+ - FILE *must* be in the bottom three bits because swap cache
+ entries use the top 29 bits.
+*/
+
+/* Definitions for FSL Book-E Cores */
+#define _PAGE_PRESENT 0x00001 /* S: PTE contains a translation */
+#define _PAGE_USER 0x00002 /* S: User page (maps to UR) */
+#define _PAGE_FILE 0x00002 /* S: when !present: nonlinear file mapping */
+#define _PAGE_ACCESSED 0x00004 /* S: Page referenced */
+#define _PAGE_HWWRITE 0x00008 /* H: Dirty & RW, set in exception */
+#define _PAGE_RW 0x00010 /* S: Write permission */
+#define _PAGE_HWEXEC 0x00020 /* H: UX permission */
+
+#define _PAGE_ENDIAN 0x00040 /* H: E bit */
+#define _PAGE_GUARDED 0x00080 /* H: G bit */
+#define _PAGE_COHERENT 0x00100 /* H: M bit */
+#define _PAGE_NO_CACHE 0x00200 /* H: I bit */
+#define _PAGE_WRITETHRU 0x00400 /* H: W bit */
+
+#ifdef CONFIG_PTE_64BIT
+#define _PAGE_DIRTY 0x08000 /* S: Page dirty */
+
+/* ERPN in a PTE never gets cleared, ignore it */
+#define _PTE_NONE_MASK 0xffffffffffff0000ULL
+#else
+#define _PAGE_DIRTY 0x00800 /* S: Page dirty */
+#endif
+
+#define _PMD_PRESENT 0
+#define _PMD_PRESENT_MASK (PAGE_MASK)
+#define _PMD_BAD (~PAGE_MASK)
+
+#elif defined(CONFIG_8xx)
+/* Definitions for 8xx embedded chips. */
+#define _PAGE_PRESENT 0x0001 /* Page is valid */
+#define _PAGE_FILE 0x0002 /* when !present: nonlinear file mapping */
+#define _PAGE_NO_CACHE 0x0002 /* I: cache inhibit */
+#define _PAGE_SHARED 0x0004 /* No ASID (context) compare */
+
+/* These five software bits must be masked out when the entry is loaded
+ * into the TLB.
+ */
+#define _PAGE_EXEC 0x0008 /* software: i-cache coherency required */
+#define _PAGE_GUARDED 0x0010 /* software: guarded access */
+#define _PAGE_DIRTY 0x0020 /* software: page changed */
+#define _PAGE_RW 0x0040 /* software: user write access allowed */
+#define _PAGE_ACCESSED 0x0080 /* software: page referenced */
+
+/* Setting any bits in the nibble with the follow two controls will
+ * require a TLB exception handler change. It is assumed unused bits
+ * are always zero.
+ */
+#define _PAGE_HWWRITE 0x0100 /* h/w write enable: never set in Linux PTE */
+#define _PAGE_USER 0x0800 /* One of the PP bits, the other is USER&~RW */
+
+#define _PMD_PRESENT 0x0001
+#define _PMD_BAD 0x0ff0
+#define _PMD_PAGE_MASK 0x000c
+#define _PMD_PAGE_8M 0x000c
+
+/*
+ * The 8xx TLB miss handler allegedly sets _PAGE_ACCESSED in the PTE
+ * for an address even if _PAGE_PRESENT is not set, as a performance
+ * optimization. This is a bug if you ever want to use swap unless
+ * _PAGE_ACCESSED is 2, which it isn't, or unless you have 8xx-specific
+ * definitions for __swp_entry etc. below, which would be gross.
+ * -- paulus
+ */
+#define _PTE_NONE_MASK _PAGE_ACCESSED
+
+#else /* CONFIG_6xx */
+/* Definitions for 60x, 740/750, etc. */
+#define _PAGE_PRESENT 0x001 /* software: pte contains a translation */
+#define _PAGE_HASHPTE 0x002 /* hash_page has made an HPTE for this pte */
+#define _PAGE_FILE 0x004 /* when !present: nonlinear file mapping */
+#define _PAGE_USER 0x004 /* usermode access allowed */
+#define _PAGE_GUARDED 0x008 /* G: prohibit speculative access */
+#define _PAGE_COHERENT 0x010 /* M: enforce memory coherence (SMP systems) */
+#define _PAGE_NO_CACHE 0x020 /* I: cache inhibit */
+#define _PAGE_WRITETHRU 0x040 /* W: cache write-through */
+#define _PAGE_DIRTY 0x080 /* C: page changed */
+#define _PAGE_ACCESSED 0x100 /* R: page referenced */
+#define _PAGE_EXEC 0x200 /* software: i-cache coherency required */
+#define _PAGE_RW 0x400 /* software: user write access allowed */
+
+#define _PTE_NONE_MASK _PAGE_HASHPTE
+
+#define _PMD_PRESENT 0
+#define _PMD_PRESENT_MASK (PAGE_MASK)
+#define _PMD_BAD (~PAGE_MASK)
+#endif
+
+/*
+ * Some bits are only used on some cpu families...
+ */
+#ifndef _PAGE_HASHPTE
+#define _PAGE_HASHPTE 0
+#endif
+#ifndef _PTE_NONE_MASK
+#define _PTE_NONE_MASK 0
+#endif
+#ifndef _PAGE_SHARED
+#define _PAGE_SHARED 0
+#endif
+#ifndef _PAGE_HWWRITE
+#define _PAGE_HWWRITE 0
+#endif
+#ifndef _PAGE_HWEXEC
+#define _PAGE_HWEXEC 0
+#endif
+#ifndef _PAGE_EXEC
+#define _PAGE_EXEC 0
+#endif
+#ifndef _PMD_PRESENT_MASK
+#define _PMD_PRESENT_MASK _PMD_PRESENT
+#endif
+#ifndef _PMD_SIZE
+#define _PMD_SIZE 0
+#define PMD_PAGE_SIZE(pmd) bad_call_to_PMD_PAGE_SIZE()
+#endif
+
+#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY)
+
+/*
+ * Note: the _PAGE_COHERENT bit automatically gets set in the hardware
+ * PTE if CONFIG_SMP is defined (hash_page does this); there is no need
+ * to have it in the Linux PTE, and in fact the bit could be reused for
+ * another purpose. -- paulus.
+ */
+
+#ifdef CONFIG_44x
+#define _PAGE_BASE (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_GUARDED)
+#else
+#define _PAGE_BASE (_PAGE_PRESENT | _PAGE_ACCESSED)
+#endif
+#define _PAGE_WRENABLE (_PAGE_RW | _PAGE_DIRTY | _PAGE_HWWRITE)
+#define _PAGE_KERNEL (_PAGE_BASE | _PAGE_SHARED | _PAGE_WRENABLE)
+
+#ifdef CONFIG_PPC_STD_MMU
+/* On standard PPC MMU, no user access implies kernel read/write access,
+ * so to write-protect kernel memory we must turn on user access */
+#define _PAGE_KERNEL_RO (_PAGE_BASE | _PAGE_SHARED | _PAGE_USER)
+#else
+#define _PAGE_KERNEL_RO (_PAGE_BASE | _PAGE_SHARED)
+#endif
+
+#define _PAGE_IO (_PAGE_KERNEL | _PAGE_NO_CACHE | _PAGE_GUARDED)
+#define _PAGE_RAM (_PAGE_KERNEL | _PAGE_HWEXEC)
+
+#if defined(CONFIG_KGDB) || defined(CONFIG_XMON) || defined(CONFIG_BDI_SWITCH)
+/* We want the debuggers to be able to set breakpoints anywhere, so
+ * don't write protect the kernel text */
+#define _PAGE_RAM_TEXT _PAGE_RAM
+#else
+#define _PAGE_RAM_TEXT (_PAGE_KERNEL_RO | _PAGE_HWEXEC)
+#endif
+
+#define PAGE_NONE __pgprot(_PAGE_BASE)
+#define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_USER)
+#define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
+#define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW)
+#define PAGE_SHARED_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW | _PAGE_EXEC)
+#define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_USER)
+#define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
+
+#define PAGE_KERNEL __pgprot(_PAGE_RAM)
+#define PAGE_KERNEL_NOCACHE __pgprot(_PAGE_IO)
+
+/*
+ * The PowerPC can only do execute protection on a segment (256MB) basis,
+ * not on a page basis. So we consider execute permission the same as read.
+ * Also, write permissions imply read permissions.
+ * This is the closest we can get..
+ */
+#define __P000 PAGE_NONE
+#define __P001 PAGE_READONLY_X
+#define __P010 PAGE_COPY
+#define __P011 PAGE_COPY_X
+#define __P100 PAGE_READONLY
+#define __P101 PAGE_READONLY_X
+#define __P110 PAGE_COPY
+#define __P111 PAGE_COPY_X
+
+#define __S000 PAGE_NONE
+#define __S001 PAGE_READONLY_X
+#define __S010 PAGE_SHARED
+#define __S011 PAGE_SHARED_X
+#define __S100 PAGE_READONLY
+#define __S101 PAGE_READONLY_X
+#define __S110 PAGE_SHARED
+#define __S111 PAGE_SHARED_X
+
+#ifndef __ASSEMBLY__
+/* Make sure we get a link error if PMD_PAGE_SIZE is ever called on a
+ * kernel without large page PMD support */
+extern unsigned long bad_call_to_PMD_PAGE_SIZE(void);
+
+/*
+ * Conversions between PTE values and page frame numbers.
+ */
+
+/* in some case we want to additionaly adjust where the pfn is in the pte to
+ * allow room for more flags */
+#if defined(CONFIG_FSL_BOOKE) && defined(CONFIG_PTE_64BIT)
+#define PFN_SHIFT_OFFSET (PAGE_SHIFT + 8)
+#else
+#define PFN_SHIFT_OFFSET (PAGE_SHIFT)
+#endif
+
+#define pte_pfn(x) (pte_val(x) >> PFN_SHIFT_OFFSET)
+#define pte_page(x) pfn_to_page(pte_pfn(x))
+
+#define pfn_pte(pfn, prot) __pte(((pte_basic_t)(pfn) << PFN_SHIFT_OFFSET) |\
+ pgprot_val(prot))
+#define mk_pte(page, prot) pfn_pte(page_to_pfn(page), prot)
+
+/*
+ * ZERO_PAGE is a global shared page that is always zero: used
+ * for zero-mapped memory areas etc..
+ */
+extern unsigned long empty_zero_page[1024];
+#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
+
+#endif /* __ASSEMBLY__ */
+
+#define pte_none(pte) ((pte_val(pte) & ~_PTE_NONE_MASK) == 0)
+#define pte_present(pte) (pte_val(pte) & _PAGE_PRESENT)
+#define pte_clear(mm,addr,ptep) do { set_pte_at((mm), (addr), (ptep), __pte(0)); } while (0)
+
+#define pmd_none(pmd) (!pmd_val(pmd))
+#define pmd_bad(pmd) (pmd_val(pmd) & _PMD_BAD)
+#define pmd_present(pmd) (pmd_val(pmd) & _PMD_PRESENT_MASK)
+#define pmd_clear(pmdp) do { pmd_val(*(pmdp)) = 0; } while (0)
+
+#ifndef __ASSEMBLY__
+/*
+ * The "pgd_xxx()" functions here are trivial for a folded two-level
+ * setup: the pgd is never bad, and a pmd always exists (as it's folded
+ * into the pgd entry)
+ */
+static inline int pgd_none(pgd_t pgd) { return 0; }
+static inline int pgd_bad(pgd_t pgd) { return 0; }
+static inline int pgd_present(pgd_t pgd) { return 1; }
+#define pgd_clear(xp) do { } while (0)
+
+#define pgd_page_vaddr(pgd) \
+ ((unsigned long) __va(pgd_val(pgd) & PAGE_MASK))
+
+/*
+ * The following only work if pte_present() is true.
+ * Undefined behaviour if not..
+ */
+static inline int pte_read(pte_t pte) { return pte_val(pte) & _PAGE_USER; }
+static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_RW; }
+static inline int pte_exec(pte_t pte) { return pte_val(pte) & _PAGE_EXEC; }
+static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; }
+static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; }
+static inline int pte_file(pte_t pte) { return pte_val(pte) & _PAGE_FILE; }
+
+static inline void pte_uncache(pte_t pte) { pte_val(pte) |= _PAGE_NO_CACHE; }
+static inline void pte_cache(pte_t pte) { pte_val(pte) &= ~_PAGE_NO_CACHE; }
+
+static inline pte_t pte_rdprotect(pte_t pte) {
+ pte_val(pte) &= ~_PAGE_USER; return pte; }
+static inline pte_t pte_wrprotect(pte_t pte) {
+ pte_val(pte) &= ~(_PAGE_RW | _PAGE_HWWRITE); return pte; }
+static inline pte_t pte_exprotect(pte_t pte) {
+ pte_val(pte) &= ~_PAGE_EXEC; return pte; }
+static inline pte_t pte_mkclean(pte_t pte) {
+ pte_val(pte) &= ~(_PAGE_DIRTY | _PAGE_HWWRITE); return pte; }
+static inline pte_t pte_mkold(pte_t pte) {
+ pte_val(pte) &= ~_PAGE_ACCESSED; return pte; }
+
+static inline pte_t pte_mkread(pte_t pte) {
+ pte_val(pte) |= _PAGE_USER; return pte; }
+static inline pte_t pte_mkexec(pte_t pte) {
+ pte_val(pte) |= _PAGE_USER | _PAGE_EXEC; return pte; }
+static inline pte_t pte_mkwrite(pte_t pte) {
+ pte_val(pte) |= _PAGE_RW; return pte; }
+static inline pte_t pte_mkdirty(pte_t pte) {
+ pte_val(pte) |= _PAGE_DIRTY; return pte; }
+static inline pte_t pte_mkyoung(pte_t pte) {
+ pte_val(pte) |= _PAGE_ACCESSED; return pte; }
+
+static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
+{
+ pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot);
+ return pte;
+}
+
+/*
+ * When flushing the tlb entry for a page, we also need to flush the hash
+ * table entry. flush_hash_pages is assembler (for speed) in hashtable.S.
+ */
+extern int flush_hash_pages(unsigned context, unsigned long va,
+ unsigned long pmdval, int count);
+
+/* Add an HPTE to the hash table */
+extern void add_hash_page(unsigned context, unsigned long va,
+ unsigned long pmdval);
+
+/*
+ * Atomic PTE updates.
+ *
+ * pte_update clears and sets bit atomically, and returns
+ * the old pte value. In the 64-bit PTE case we lock around the
+ * low PTE word since we expect ALL flag bits to be there
+ */
+#ifndef CONFIG_PTE_64BIT
+static inline unsigned long pte_update(pte_t *p, unsigned long clr,
+ unsigned long set)
+{
+ unsigned long old, tmp;
+
+ __asm__ __volatile__("\
+1: lwarx %0,0,%3\n\
+ andc %1,%0,%4\n\
+ or %1,%1,%5\n"
+ PPC405_ERR77(0,%3)
+" stwcx. %1,0,%3\n\
+ bne- 1b"
+ : "=&r" (old), "=&r" (tmp), "=m" (*p)
+ : "r" (p), "r" (clr), "r" (set), "m" (*p)
+ : "cc" );
+ return old;
+}
+#else
+static inline unsigned long long pte_update(pte_t *p, unsigned long clr,
+ unsigned long set)
+{
+ unsigned long long old;
+ unsigned long tmp;
+
+ __asm__ __volatile__("\
+1: lwarx %L0,0,%4\n\
+ lwzx %0,0,%3\n\
+ andc %1,%L0,%5\n\
+ or %1,%1,%6\n"
+ PPC405_ERR77(0,%3)
+" stwcx. %1,0,%4\n\
+ bne- 1b"
+ : "=&r" (old), "=&r" (tmp), "=m" (*p)
+ : "r" (p), "r" ((unsigned long)(p) + 4), "r" (clr), "r" (set), "m" (*p)
+ : "cc" );
+ return old;
+}
+#endif
+
+/*
+ * set_pte stores a linux PTE into the linux page table.
+ * On machines which use an MMU hash table we avoid changing the
+ * _PAGE_HASHPTE bit.
+ */
+static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
+ pte_t *ptep, pte_t pte)
+{
+#if _PAGE_HASHPTE != 0
+ pte_update(ptep, ~_PAGE_HASHPTE, pte_val(pte) & ~_PAGE_HASHPTE);
+#else
+ *ptep = pte;
+#endif
+}
+
+/*
+ * 2.6 calles this without flushing the TLB entry, this is wrong
+ * for our hash-based implementation, we fix that up here
+ */
+#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
+static inline int __ptep_test_and_clear_young(unsigned int context, unsigned long addr, pte_t *ptep)
+{
+ unsigned long old;
+ old = pte_update(ptep, _PAGE_ACCESSED, 0);
+#if _PAGE_HASHPTE != 0
+ if (old & _PAGE_HASHPTE) {
+ unsigned long ptephys = __pa(ptep) & PAGE_MASK;
+ flush_hash_pages(context, addr, ptephys, 1);
+ }
+#endif
+ return (old & _PAGE_ACCESSED) != 0;
+}
+#define ptep_test_and_clear_young(__vma, __addr, __ptep) \
+ __ptep_test_and_clear_young((__vma)->vm_mm->context.id, __addr, __ptep)
+
+#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_DIRTY
+static inline int ptep_test_and_clear_dirty(struct vm_area_struct *vma,
+ unsigned long addr, pte_t *ptep)
+{
+ return (pte_update(ptep, (_PAGE_DIRTY | _PAGE_HWWRITE), 0) & _PAGE_DIRTY) != 0;
+}
+
+#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
+static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr,
+ pte_t *ptep)
+{
+ return __pte(pte_update(ptep, ~_PAGE_HASHPTE, 0));
+}
+
+#define __HAVE_ARCH_PTEP_SET_WRPROTECT
+static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr,
+ pte_t *ptep)
+{
+ pte_update(ptep, (_PAGE_RW | _PAGE_HWWRITE), 0);
+}
+
+#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
+static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry, int dirty)
+{
+ unsigned long bits = pte_val(entry) &
+ (_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_RW);
+ pte_update(ptep, 0, bits);
+}
+
+#define ptep_set_access_flags(__vma, __address, __ptep, __entry, __dirty) \
+ do { \
+ __ptep_set_access_flags(__ptep, __entry, __dirty); \
+ flush_tlb_page_nohash(__vma, __address); \
+ } while(0)
+
+/*
+ * Macro to mark a page protection value as "uncacheable".
+ */
+#define pgprot_noncached(prot) (__pgprot(pgprot_val(prot) | _PAGE_NO_CACHE | _PAGE_GUARDED))
+
+struct file;
+extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
+ unsigned long size, pgprot_t vma_prot);
+#define __HAVE_PHYS_MEM_ACCESS_PROT
+
+#define __HAVE_ARCH_PTE_SAME
+#define pte_same(A,B) (((pte_val(A) ^ pte_val(B)) & ~_PAGE_HASHPTE) == 0)
+
+/*
+ * Note that on Book E processors, the pmd contains the kernel virtual
+ * (lowmem) address of the pte page. The physical address is less useful
+ * because everything runs with translation enabled (even the TLB miss
+ * handler). On everything else the pmd contains the physical address
+ * of the pte page. -- paulus
+ */
+#ifndef CONFIG_BOOKE
+#define pmd_page_vaddr(pmd) \
+ ((unsigned long) __va(pmd_val(pmd) & PAGE_MASK))
+#define pmd_page(pmd) \
+ (mem_map + (pmd_val(pmd) >> PAGE_SHIFT))
+#else
+#define pmd_page_vaddr(pmd) \
+ ((unsigned long) (pmd_val(pmd) & PAGE_MASK))
+#define pmd_page(pmd) \
+ (mem_map + (__pa(pmd_val(pmd)) >> PAGE_SHIFT))
+#endif
+
+/* to find an entry in a kernel page-table-directory */
+#define pgd_offset_k(address) pgd_offset(&init_mm, address)
+
+/* to find an entry in a page-table-directory */
+#define pgd_index(address) ((address) >> PGDIR_SHIFT)
+#define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
+
+/* Find an entry in the second-level page table.. */
+static inline pmd_t * pmd_offset(pgd_t * dir, unsigned long address)
+{
+ return (pmd_t *) dir;
+}
+
+/* Find an entry in the third-level page table.. */
+#define pte_index(address) \
+ (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
+#define pte_offset_kernel(dir, addr) \
+ ((pte_t *) pmd_page_vaddr(*(dir)) + pte_index(addr))
+#define pte_offset_map(dir, addr) \
+ ((pte_t *) kmap_atomic(pmd_page(*(dir)), KM_PTE0) + pte_index(addr))
+#define pte_offset_map_nested(dir, addr) \
+ ((pte_t *) kmap_atomic(pmd_page(*(dir)), KM_PTE1) + pte_index(addr))
+
+#define pte_unmap(pte) kunmap_atomic(pte, KM_PTE0)
+#define pte_unmap_nested(pte) kunmap_atomic(pte, KM_PTE1)
+
+extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
+
+extern void paging_init(void);
+
+/*
+ * Encode and decode a swap entry.
+ * Note that the bits we use in a PTE for representing a swap entry
+ * must not include the _PAGE_PRESENT bit, the _PAGE_FILE bit, or the
+ *_PAGE_HASHPTE bit (if used). -- paulus
+ */
+#define __swp_type(entry) ((entry).val & 0x1f)
+#define __swp_offset(entry) ((entry).val >> 5)
+#define __swp_entry(type, offset) ((swp_entry_t) { (type) | ((offset) << 5) })
+#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) >> 3 })
+#define __swp_entry_to_pte(x) ((pte_t) { (x).val << 3 })
+
+/* Encode and decode a nonlinear file mapping entry */
+#define PTE_FILE_MAX_BITS 29
+#define pte_to_pgoff(pte) (pte_val(pte) >> 3)
+#define pgoff_to_pte(off) ((pte_t) { ((off) << 3) | _PAGE_FILE })
+
+/* CONFIG_APUS */
+/* For virtual address to physical address conversion */
+extern void cache_clear(__u32 addr, int length);
+extern void cache_push(__u32 addr, int length);
+extern int mm_end_of_chunk (unsigned long addr, int len);
+extern unsigned long iopa(unsigned long addr);
+extern unsigned long mm_ptov(unsigned long addr) __attribute_const__;
+
+/* Values for nocacheflag and cmode */
+/* These are not used by the APUS kernel_map, but prevents
+ compilation errors. */
+#define KERNELMAP_FULL_CACHING 0
+#define KERNELMAP_NOCACHE_SER 1
+#define KERNELMAP_NOCACHE_NONSER 2
+#define KERNELMAP_NO_COPYBACK 3
+
+/*
+ * Map some physical address range into the kernel address space.
+ */
+extern unsigned long kernel_map(unsigned long paddr, unsigned long size,
+ int nocacheflag, unsigned long *memavailp );
+
+/*
+ * Set cache mode of (kernel space) address range.
+ */
+extern void kernel_set_cachemode (unsigned long address, unsigned long size,
+ unsigned int cmode);
+
+/* Needs to be defined here and not in linux/mm.h, as it is arch dependent */
+#define kern_addr_valid(addr) (1)
+
+#ifdef CONFIG_PHYS_64BIT
+extern int remap_pfn_range(struct vm_area_struct *vma, unsigned long from,
+ unsigned long paddr, unsigned long size, pgprot_t prot);
+
+static inline int io_remap_pfn_range(struct vm_area_struct *vma,
+ unsigned long vaddr,
+ unsigned long pfn,
+ unsigned long size,
+ pgprot_t prot)
+{
+ phys_addr_t paddr64 = fixup_bigphys_addr(pfn << PAGE_SHIFT, size);
+ return remap_pfn_range(vma, vaddr, paddr64 >> PAGE_SHIFT, size, prot);
+}
+#else
+#define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \
+ remap_pfn_range(vma, vaddr, pfn, size, prot)
+#endif
+
+/*
+ * No page table caches to initialise
+ */
+#define pgtable_cache_init() do { } while (0)
+
+extern int get_pteptr(struct mm_struct *mm, unsigned long addr, pte_t **ptep,
+ pmd_t **pmdp);
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* _ASM_POWERPC_PGTABLE_PPC32_H */
Index: working-2.6/include/asm-powerpc/pgalloc-32.h
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ working-2.6/include/asm-powerpc/pgalloc-32.h 2007-04-30 15:36:29.000000000 +1000
@@ -0,0 +1,41 @@
+#ifndef _ASM_POWERPC_PGALLOC_32_H
+#define _ASM_POWERPC_PGALLOC_32_H
+
+#include <linux/threads.h>
+
+extern void __bad_pte(pmd_t *pmd);
+
+extern pgd_t *pgd_alloc(struct mm_struct *mm);
+extern void pgd_free(pgd_t *pgd);
+
+/*
+ * We don't have any real pmd's, and this code never triggers because
+ * the pgd will always be present..
+ */
+#define pmd_alloc_one(mm,address) ({ BUG(); ((pmd_t *)2); })
+#define pmd_free(x) do { } while (0)
+#define __pmd_free_tlb(tlb,x) do { } while (0)
+#define pgd_populate(mm, pmd, pte) BUG()
+
+#ifndef CONFIG_BOOKE
+#define pmd_populate_kernel(mm, pmd, pte) \
+ (pmd_val(*(pmd)) = __pa(pte) | _PMD_PRESENT)
+#define pmd_populate(mm, pmd, pte) \
+ (pmd_val(*(pmd)) = (page_to_pfn(pte) << PAGE_SHIFT) | _PMD_PRESENT)
+#else
+#define pmd_populate_kernel(mm, pmd, pte) \
+ (pmd_val(*(pmd)) = (unsigned long)pte | _PMD_PRESENT)
+#define pmd_populate(mm, pmd, pte) \
+ (pmd_val(*(pmd)) = (unsigned long)lowmem_page_address(pte) | _PMD_PRESENT)
+#endif
+
+extern pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long addr);
+extern struct page *pte_alloc_one(struct mm_struct *mm, unsigned long addr);
+extern void pte_free_kernel(pte_t *pte);
+extern void pte_free(struct page *pte);
+
+#define __pte_free_tlb(tlb, pte) pte_free((pte))
+
+#define check_pgt_cache() do { } while (0)
+
+#endif /* _ASM_POWERPC_PGALLOC_32_H */
Index: working-2.6/include/asm-powerpc/pgalloc-64.h
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ working-2.6/include/asm-powerpc/pgalloc-64.h 2007-04-30 15:36:29.000000000 +1000
@@ -0,0 +1,152 @@
+#ifndef _ASM_POWERPC_PGALLOC_64_H
+#define _ASM_POWERPC_PGALLOC_64_H
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include <linux/mm.h>
+#include <linux/slab.h>
+#include <linux/cpumask.h>
+#include <linux/percpu.h>
+
+extern struct kmem_cache *pgtable_cache[];
+
+#ifdef CONFIG_PPC_64K_PAGES
+#define PTE_CACHE_NUM 0
+#define PMD_CACHE_NUM 1
+#define PGD_CACHE_NUM 2
+#define HUGEPTE_CACHE_NUM 3
+#else
+#define PTE_CACHE_NUM 0
+#define PMD_CACHE_NUM 1
+#define PUD_CACHE_NUM 1
+#define PGD_CACHE_NUM 0
+#define HUGEPTE_CACHE_NUM 2
+#endif
+
+static inline pgd_t *pgd_alloc(struct mm_struct *mm)
+{
+ return kmem_cache_alloc(pgtable_cache[PGD_CACHE_NUM], GFP_KERNEL);
+}
+
+static inline void pgd_free(pgd_t *pgd)
+{
+ kmem_cache_free(pgtable_cache[PGD_CACHE_NUM], pgd);
+}
+
+#ifndef CONFIG_PPC_64K_PAGES
+
+#define pgd_populate(MM, PGD, PUD) pgd_set(PGD, PUD)
+
+static inline pud_t *pud_alloc_one(struct mm_struct *mm, unsigned long addr)
+{
+ return kmem_cache_alloc(pgtable_cache[PUD_CACHE_NUM],
+ GFP_KERNEL|__GFP_REPEAT);
+}
+
+static inline void pud_free(pud_t *pud)
+{
+ kmem_cache_free(pgtable_cache[PUD_CACHE_NUM], pud);
+}
+
+static inline void pud_populate(struct mm_struct *mm, pud_t *pud, pmd_t *pmd)
+{
+ pud_set(pud, (unsigned long)pmd);
+}
+
+#define pmd_populate(mm, pmd, pte_page) \
+ pmd_populate_kernel(mm, pmd, page_address(pte_page))
+#define pmd_populate_kernel(mm, pmd, pte) pmd_set(pmd, (unsigned long)(pte))
+
+
+#else /* CONFIG_PPC_64K_PAGES */
+
+#define pud_populate(mm, pud, pmd) pud_set(pud, (unsigned long)pmd)
+
+static inline void pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmd,
+ pte_t *pte)
+{
+ pmd_set(pmd, (unsigned long)pte);
+}
+
+#define pmd_populate(mm, pmd, pte_page) \
+ pmd_populate_kernel(mm, pmd, page_address(pte_page))
+
+#endif /* CONFIG_PPC_64K_PAGES */
+
+static inline pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long addr)
+{
+ return kmem_cache_alloc(pgtable_cache[PMD_CACHE_NUM],
+ GFP_KERNEL|__GFP_REPEAT);
+}
+
+static inline void pmd_free(pmd_t *pmd)
+{
+ kmem_cache_free(pgtable_cache[PMD_CACHE_NUM], pmd);
+}
+
+static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm,
+ unsigned long address)
+{
+ return kmem_cache_alloc(pgtable_cache[PTE_CACHE_NUM],
+ GFP_KERNEL|__GFP_REPEAT);
+}
+
+static inline struct page *pte_alloc_one(struct mm_struct *mm,
+ unsigned long address)
+{
+ return virt_to_page(pte_alloc_one_kernel(mm, address));
+}
+
+static inline void pte_free_kernel(pte_t *pte)
+{
+ kmem_cache_free(pgtable_cache[PTE_CACHE_NUM], pte);
+}
+
+static inline void pte_free(struct page *ptepage)
+{
+ pte_free_kernel(page_address(ptepage));
+}
+
+#define PGF_CACHENUM_MASK 0x3
+
+typedef struct pgtable_free {
+ unsigned long val;
+} pgtable_free_t;
+
+static inline pgtable_free_t pgtable_free_cache(void *p, int cachenum,
+ unsigned long mask)
+{
+ BUG_ON(cachenum > PGF_CACHENUM_MASK);
+
+ return (pgtable_free_t){.val = ((unsigned long) p & ~mask) | cachenum};
+}
+
+static inline void pgtable_free(pgtable_free_t pgf)
+{
+ void *p = (void *)(pgf.val & ~PGF_CACHENUM_MASK);
+ int cachenum = pgf.val & PGF_CACHENUM_MASK;
+
+ kmem_cache_free(pgtable_cache[cachenum], p);
+}
+
+extern void pgtable_free_tlb(struct mmu_gather *tlb, pgtable_free_t pgf);
+
+#define __pte_free_tlb(tlb, ptepage) \
+ pgtable_free_tlb(tlb, pgtable_free_cache(page_address(ptepage), \
+ PTE_CACHE_NUM, PTE_TABLE_SIZE-1))
+#define __pmd_free_tlb(tlb, pmd) \
+ pgtable_free_tlb(tlb, pgtable_free_cache(pmd, \
+ PMD_CACHE_NUM, PMD_TABLE_SIZE-1))
+#ifndef CONFIG_PPC_64K_PAGES
+#define __pud_free_tlb(tlb, pud) \
+ pgtable_free_tlb(tlb, pgtable_free_cache(pud, \
+ PUD_CACHE_NUM, PUD_TABLE_SIZE-1))
+#endif /* CONFIG_PPC_64K_PAGES */
+
+#define check_pgt_cache() do { } while (0)
+
+#endif /* _ASM_POWERPC_PGALLOC_64_H */
Index: working-2.6/include/asm-powerpc/pgalloc.h
===================================================================
--- working-2.6.orig/include/asm-powerpc/pgalloc.h 2007-04-30 15:36:22.000000000 +1000
+++ working-2.6/include/asm-powerpc/pgalloc.h 2007-04-30 15:36:29.000000000 +1000
@@ -2,159 +2,11 @@
#define _ASM_POWERPC_PGALLOC_H
#ifdef __KERNEL__
-#ifndef CONFIG_PPC64
-#include <asm-ppc/pgalloc.h>
+#ifdef CONFIG_PPC64
+#include <asm/pgalloc-64.h>
#else
-
-#include <linux/mm.h>
-#include <linux/slab.h>
-#include <linux/cpumask.h>
-#include <linux/percpu.h>
-
-extern struct kmem_cache *pgtable_cache[];
-
-#ifdef CONFIG_PPC_64K_PAGES
-#define PTE_CACHE_NUM 0
-#define PMD_CACHE_NUM 1
-#define PGD_CACHE_NUM 2
-#define HUGEPTE_CACHE_NUM 3
-#else
-#define PTE_CACHE_NUM 0
-#define PMD_CACHE_NUM 1
-#define PUD_CACHE_NUM 1
-#define PGD_CACHE_NUM 0
-#define HUGEPTE_CACHE_NUM 2
+#include <asm/pgalloc-32.h>
#endif
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-static inline pgd_t *pgd_alloc(struct mm_struct *mm)
-{
- return kmem_cache_alloc(pgtable_cache[PGD_CACHE_NUM], GFP_KERNEL);
-}
-
-static inline void pgd_free(pgd_t *pgd)
-{
- kmem_cache_free(pgtable_cache[PGD_CACHE_NUM], pgd);
-}
-
-#ifndef CONFIG_PPC_64K_PAGES
-
-#define pgd_populate(MM, PGD, PUD) pgd_set(PGD, PUD)
-
-static inline pud_t *pud_alloc_one(struct mm_struct *mm, unsigned long addr)
-{
- return kmem_cache_alloc(pgtable_cache[PUD_CACHE_NUM],
- GFP_KERNEL|__GFP_REPEAT);
-}
-
-static inline void pud_free(pud_t *pud)
-{
- kmem_cache_free(pgtable_cache[PUD_CACHE_NUM], pud);
-}
-
-static inline void pud_populate(struct mm_struct *mm, pud_t *pud, pmd_t *pmd)
-{
- pud_set(pud, (unsigned long)pmd);
-}
-
-#define pmd_populate(mm, pmd, pte_page) \
- pmd_populate_kernel(mm, pmd, page_address(pte_page))
-#define pmd_populate_kernel(mm, pmd, pte) pmd_set(pmd, (unsigned long)(pte))
-
-
-#else /* CONFIG_PPC_64K_PAGES */
-
-#define pud_populate(mm, pud, pmd) pud_set(pud, (unsigned long)pmd)
-
-static inline void pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmd,
- pte_t *pte)
-{
- pmd_set(pmd, (unsigned long)pte);
-}
-
-#define pmd_populate(mm, pmd, pte_page) \
- pmd_populate_kernel(mm, pmd, page_address(pte_page))
-
-#endif /* CONFIG_PPC_64K_PAGES */
-
-static inline pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long addr)
-{
- return kmem_cache_alloc(pgtable_cache[PMD_CACHE_NUM],
- GFP_KERNEL|__GFP_REPEAT);
-}
-
-static inline void pmd_free(pmd_t *pmd)
-{
- kmem_cache_free(pgtable_cache[PMD_CACHE_NUM], pmd);
-}
-
-static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm,
- unsigned long address)
-{
- return kmem_cache_alloc(pgtable_cache[PTE_CACHE_NUM],
- GFP_KERNEL|__GFP_REPEAT);
-}
-
-static inline struct page *pte_alloc_one(struct mm_struct *mm,
- unsigned long address)
-{
- return virt_to_page(pte_alloc_one_kernel(mm, address));
-}
-
-static inline void pte_free_kernel(pte_t *pte)
-{
- kmem_cache_free(pgtable_cache[PTE_CACHE_NUM], pte);
-}
-
-static inline void pte_free(struct page *ptepage)
-{
- pte_free_kernel(page_address(ptepage));
-}
-
-#define PGF_CACHENUM_MASK 0x3
-
-typedef struct pgtable_free {
- unsigned long val;
-} pgtable_free_t;
-
-static inline pgtable_free_t pgtable_free_cache(void *p, int cachenum,
- unsigned long mask)
-{
- BUG_ON(cachenum > PGF_CACHENUM_MASK);
-
- return (pgtable_free_t){.val = ((unsigned long) p & ~mask) | cachenum};
-}
-
-static inline void pgtable_free(pgtable_free_t pgf)
-{
- void *p = (void *)(pgf.val & ~PGF_CACHENUM_MASK);
- int cachenum = pgf.val & PGF_CACHENUM_MASK;
-
- kmem_cache_free(pgtable_cache[cachenum], p);
-}
-
-extern void pgtable_free_tlb(struct mmu_gather *tlb, pgtable_free_t pgf);
-
-#define __pte_free_tlb(tlb, ptepage) \
- pgtable_free_tlb(tlb, pgtable_free_cache(page_address(ptepage), \
- PTE_CACHE_NUM, PTE_TABLE_SIZE-1))
-#define __pmd_free_tlb(tlb, pmd) \
- pgtable_free_tlb(tlb, pgtable_free_cache(pmd, \
- PMD_CACHE_NUM, PMD_TABLE_SIZE-1))
-#ifndef CONFIG_PPC_64K_PAGES
-#define __pud_free_tlb(tlb, pud) \
- pgtable_free_tlb(tlb, pgtable_free_cache(pud, \
- PUD_CACHE_NUM, PUD_TABLE_SIZE-1))
-#endif /* CONFIG_PPC_64K_PAGES */
-
-#define check_pgt_cache() do { } while (0)
-
-#endif /* CONFIG_PPC64 */
#endif /* __KERNEL__ */
#endif /* _ASM_POWERPC_PGALLOC_H */
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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