* Re: fsl booke MM vs. SMP questions
From: Benjamin Herrenschmidt @ 2007-05-22 10:05 UTC (permalink / raw)
To: Gabriel Paubert; +Cc: ppc-dev, Dave Liu, Paul Mackerras, Kumar Gala
In-Reply-To: <20070522100212.GA13225@iram.es>
On Tue, 2007-05-22 at 12:02 +0200, Gabriel Paubert wrote:
>
> Well, there should always be an stwcx. to clear reservation before
> any interrupt return. Otherwise you'll be able to cause hard to
> reproduce bugs in the interrupted code.
Well, that's the point. The BookE TLB refill exception is a very fast
path that doesn't use the normal interrupt return code path. It thus
needs to be careful about not leaving dangling reservations.
On some CPUs, there are also performance issues with leaving dangling
lwarx iirc but I don't have the details off the top of my mind.
Cheers,
Ben.
^ permalink raw reply
* Re: fsl booke MM vs. SMP questions
From: Gabriel Paubert @ 2007-05-22 10:02 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: ppc-dev, Dave Liu, Paul Mackerras, Kumar Gala
In-Reply-To: <1179825278.32247.827.camel@localhost.localdomain>
On Tue, May 22, 2007 at 07:14:38PM +1000, Benjamin Herrenschmidt wrote:
> > Why do you want to clear the reservation here?
> >
> > Coming out of some code path with the reservation still held
> > can only affect buggy code (someone doing st[dw]cx. before
> > l[dw]arx) AFAIK.
>
> And buggy CPUs :-)
>
> Seriously, lots of CPU implementations don't test the address for local
> lwarx stwcx. so if your kernel code "replaces" a reservation with
> another that is left set, the userland stwcx. might well succeed which
> is bogus.
>
Well, there should always be an stwcx. to clear reservation before
any interrupt return. Otherwise you'll be able to cause hard to
reproduce bugs in the interrupted code.
Checking or not that the reservation address matches the stwcx.
is irrelevant.
Gabriel
^ permalink raw reply
* Re: [PATCH 07/13] Implement arch disable/enable irq hooks.
From: Johannes Berg @ 2007-05-22 9:24 UTC (permalink / raw)
To: Benjamin Herrenschmidt
Cc: linuxppc-dev, Paul Mackerras, Guennadi Liakhovetski
In-Reply-To: <1179825335.32247.829.camel@localhost.localdomain>
[-- Attachment #1: Type: text/plain, Size: 396 bytes --]
On Tue, 2007-05-22 at 19:15 +1000, Benjamin Herrenschmidt wrote:
> Global version calls into the ppc_md hooks and possibly provide a
> useable default if no hook is there (Scott's implementation looks like a
> reasonably good default).
Yes, I agree, for powermac for the pfuncs I'll need to override it but I
doubt Guennadi will for example need to change it for his stuff.
johannes
[-- Attachment #2: This is a digitally signed message part --]
[-- Type: application/pgp-signature, Size: 190 bytes --]
^ permalink raw reply
* Re: [PATCH 07/13] Implement arch disable/enable irq hooks.
From: Benjamin Herrenschmidt @ 2007-05-22 9:15 UTC (permalink / raw)
To: Johannes Berg; +Cc: linuxppc-dev, Paul Mackerras, Guennadi Liakhovetski
In-Reply-To: <1179824589.3673.1.camel@johannes.berg>
On Tue, 2007-05-22 at 11:03 +0200, Johannes Berg wrote:
> On Tue, 2007-05-22 at 17:14 +1000, Benjamin Herrenschmidt wrote:
> > On Mon, 2007-05-21 at 17:55 +0200, Johannes Berg wrote:
> > >
> > > Then again, if we don't implement these in common code, might we get
> > > link problems when we try building some multiplatform kernel?
> >
> > That's what ppc_md is for :-)
>
> So you're saying we should globally implement
> arch_suspend_irq_{enable,disable} and then call some ppc_md hook? Sounds
> good to me as well, I'd like to ask for a revision of this patch
> including that, then I'll update my patches for that.
Yup.
Global version calls into the ppc_md hooks and possibly provide a
useable default if no hook is there (Scott's implementation looks like a
reasonably good default).
Ben.
^ permalink raw reply
* Re: fsl booke MM vs. SMP questions
From: Benjamin Herrenschmidt @ 2007-05-22 9:14 UTC (permalink / raw)
To: Gabriel Paubert; +Cc: ppc-dev, Dave Liu, Paul Mackerras, Kumar Gala
In-Reply-To: <20070522084645.GA12009@iram.es>
> Why do you want to clear the reservation here?
>
> Coming out of some code path with the reservation still held
> can only affect buggy code (someone doing st[dw]cx. before
> l[dw]arx) AFAIK.
And buggy CPUs :-)
Seriously, lots of CPU implementations don't test the address for local
lwarx stwcx. so if your kernel code "replaces" a reservation with
another that is left set, the userland stwcx. might well succeed which
is bogus.
Ben.
^ permalink raw reply
* Re: [PATCH 07/13] Implement arch disable/enable irq hooks.
From: Johannes Berg @ 2007-05-22 9:03 UTC (permalink / raw)
To: Benjamin Herrenschmidt
Cc: linuxppc-dev, Paul Mackerras, Guennadi Liakhovetski
In-Reply-To: <1179818066.32247.812.camel@localhost.localdomain>
[-- Attachment #1: Type: text/plain, Size: 565 bytes --]
On Tue, 2007-05-22 at 17:14 +1000, Benjamin Herrenschmidt wrote:
> On Mon, 2007-05-21 at 17:55 +0200, Johannes Berg wrote:
> >
> > Then again, if we don't implement these in common code, might we get
> > link problems when we try building some multiplatform kernel?
>
> That's what ppc_md is for :-)
So you're saying we should globally implement
arch_suspend_irq_{enable,disable} and then call some ppc_md hook? Sounds
good to me as well, I'd like to ask for a revision of this patch
including that, then I'll update my patches for that.
johannes
[-- Attachment #2: This is a digitally signed message part --]
[-- Type: application/pgp-signature, Size: 190 bytes --]
^ permalink raw reply
* Re: fsl booke MM vs. SMP questions
From: Gabriel Paubert @ 2007-05-22 8:46 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: ppc-dev, Dave Liu, Paul Mackerras, Kumar Gala
In-Reply-To: <1179785273.32247.742.camel@localhost.localdomain>
On Tue, May 22, 2007 at 08:07:52AM +1000, Benjamin Herrenschmidt wrote:
>
> > > The tlb miss handler does:
> > >
> > > - tlbbusy = 1
> > > - barrier (make sure the following read is in order vs. the previous
> > > store to tlbbusy)
> > > - read linux PTE value
> > > - write it to the HW TLB
> >
> > and write the linux PTE with referenced bit?
>
> I've kept the reference bit rewrite out of that pseudo-code because I
> was approaching a different issue but yes. The idea i have there is to
> do break down the linux PTE operation that way:
>
> 1 - rX = read PTE value (normal load)
> 2 - if (!_PAGE_PRESENT)) -> out
> 3 - rY = rX | _PAGE_ACCESSED
> 4 - if (rX != rY)
> 5 - rZ = lwarx PTE value
> 6 - if (rZ != rX)
> 7 - stdcx. PTE, rZ (rewrite just read value to clear reserv)
Why do you want to clear the reservation here?
Coming out of some code path with the reservation still held
can only affect buggy code (someone doing st[dw]cx. before
l[dw]arx) AFAIK.
> 8 - goto 1 (try again)
> 9 - stdcx. PTE, rY
> 10 - if failed -> goto 1 (try again)
> 11 - that's it !
>
> In addition, I suppose performance can be improved by also dealing with
> dirty bit right in the TLB refill if the access is a write and the page
> is writeable rather than taking a double fault.
Regards,
Gabriel
^ permalink raw reply
* Re: [PATCH 07/13] Implement arch disable/enable irq hooks.
From: Johannes Berg @ 2007-05-21 15:55 UTC (permalink / raw)
To: Scott Wood; +Cc: linuxppc-dev, Guennadi Liakhovetski, Paul Mackerras
In-Reply-To: <20070507182950.GF26920@ld0162-tx32.am.freescale.net>
[-- Attachment #1: Type: text/plain, Size: 1089 bytes --]
On Mon, 2007-05-07 at 13:29 -0500, Scott Wood wrote:
> These hooks ensure that a decrementer interrupt is not pending when
> suspending; otherwise, problems may occur. For example, with deep sleep
> on the 831x, a pending decrementer will cause a system freeze because the
> SoC thinks the decrementer interrupt would have woken the system, but the
> core must have interrupts disabled due to the setup required for deep
> sleep.
Interesting to see this first use of these hooks we had to fight for for
so long... Can you put the arch_suspend_{enable,disable}_irqs along with
the actual power management code for 831x?
On the one hand I agree with this patch, this is exactly what we wanted
the hooks for, but on the other hand I would like to have these hooks
free for some more stuff for PMU-based sleep so that I don't need to do
ugly things with platform devices or something for the powermac platform
function stuff.
Then again, if we don't implement these in common code, might we get
link problems when we try building some multiplatform kernel?
johannes
[-- Attachment #2: This is a digitally signed message part --]
[-- Type: application/pgp-signature, Size: 190 bytes --]
^ permalink raw reply
* Re: [PATCH] power-management elements for 603e/fsl (version 2)
From: Johannes Berg @ 2007-05-21 15:54 UTC (permalink / raw)
To: Guennadi Liakhovetski; +Cc: linuxppc-dev, Paul Mackerras
In-Reply-To: <Pine.LNX.4.60.0705192013010.10162@poirot.grange>
[-- Attachment #1: Type: text/plain, Size: 1426 bytes --]
On Sat, 2007-05-19 at 21:22 +0200, Guennadi Liakhovetski wrote:
> +int fsl_suspend(suspend_state_t state)
> +{
> + struct pci_dev *bridge;
> + unsigned long flags;
> + u16 pmcr1;
> +
> + bridge = pci_find_slot(0, 0);
> + if (!bridge)
> + return -ENODEV;
> +
> + pci_read_config_word(bridge, 0x70, &pmcr1);
> + local_irq_save(flags);
> + /* Apparently, MacOS uses NAP mode for Grackle ??? */
That comment seems out of place :)
> + pmcr1 &= ~(MPC10X_DOZE | MPC10X_NAP);
> + pmcr1 |= MPC10X_PM | MPC10X_SLEEP | MPC10X_LP_REF_EN;
> + pci_write_config_word(bridge, 0x70, pmcr1);
> + local_irq_restore(flags);
> +
> + /* Make sure the decrementer won't interrupt us */
> + asm volatile("mtdec %0" : : "r" (0x7fffffff));
> + /* Make sure any pending DEC interrupt occurring while we did
> + * the above didn't re-enable the DEC */
> + mb();
> + asm volatile("mtdec %0" : : "r" (0x7fffffff)); /* 8 seconds */
Are you sure that's 8 seconds? Seems too fast.
Also, the whole irq handling thing in resume/suspend seems bogus. Both
resume and suspend are called with interrupts off, so the
local_irq_{save,restore} calls do nothing. You probably need to use
arch_suspend_{enable,disable}_irqs and do the decrementer magic there
(after all that's why we introduced these.)
Then again, see the other mail I'm about to send in response to a patch
from Scott Wood using these hooks.
johannes
[-- Attachment #2: This is a digitally signed message part --]
[-- Type: application/pgp-signature, Size: 190 bytes --]
^ permalink raw reply
* Re: [PATCH 07/13] Implement arch disable/enable irq hooks.
From: Benjamin Herrenschmidt @ 2007-05-22 7:14 UTC (permalink / raw)
To: Johannes Berg; +Cc: linuxppc-dev, Paul Mackerras, Guennadi Liakhovetski
In-Reply-To: <1179762902.9122.19.camel@johannes.berg>
On Mon, 2007-05-21 at 17:55 +0200, Johannes Berg wrote:
>
> Then again, if we don't implement these in common code, might we get
> link problems when we try building some multiplatform kernel?
That's what ppc_md is for :-)
Ben.
^ permalink raw reply
* [PATCH/RFC] Rework ptep_set_access_flags and fix sun4c
From: Benjamin Herrenschmidt @ 2007-05-22 6:28 UTC (permalink / raw)
To: Tom "spot" Callaway
Cc: mark, linux-mm, wli, linuxppc-dev, andrea, sparclinux,
Hugh Dickins, akpm, David Miller
In-Reply-To: <1179757647.6254.235.camel@localhost.localdomain>
This patch reworks ptep_set_access_flags() and the callers so that the
comparison to the old PTE is done inside that function, which then
returns wether an update_mmu_cache() is needed. That allows fixing
the sun4c situation where update_mmu_cache() needs to be forced,
always.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
Ok, so that's only compile tested on sparc32 and powerpc 32 bits, boot
tested on powerpc64 and not tested on others (I could use some help
testing x86, x86_64 and s390 who also have their own implementations).
Index: linux-work/include/asm-generic/pgtable.h
===================================================================
--- linux-work.orig/include/asm-generic/pgtable.h 2007-05-22 15:04:45.000000000 +1000
+++ linux-work/include/asm-generic/pgtable.h 2007-05-22 15:32:21.000000000 +1000
@@ -27,13 +27,20 @@ do { \
* Largely same as above, but only sets the access flags (dirty,
* accessed, and writable). Furthermore, we know it always gets set
* to a "more permissive" setting, which allows most architectures
- * to optimize this.
+ * to optimize this. We return wether the PTE actually changed, which
+ * in turn instructs the caller to do things like update__mmu_cache.
+ * This used to be done in the caller, but sparc needs minor faults to
+ * force that call on sun4c so we changed this macro slightly
*/
#define ptep_set_access_flags(__vma, __address, __ptep, __entry, __dirty) \
-do { \
- set_pte_at((__vma)->vm_mm, (__address), __ptep, __entry); \
- flush_tlb_page(__vma, __address); \
-} while (0)
+({ \
+ int __changed = !pte_same(*(__ptep), __entry); \
+ if (__changed) { \
+ set_pte_at((__vma)->vm_mm, (__address), __ptep, __entry); \
+ flush_tlb_page(__vma, __address); \
+ } \
+ __changed; \
+})
#endif
#ifndef __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
Index: linux-work/include/asm-powerpc/pgtable-ppc64.h
===================================================================
--- linux-work.orig/include/asm-powerpc/pgtable-ppc64.h 2007-05-22 15:04:45.000000000 +1000
+++ linux-work/include/asm-powerpc/pgtable-ppc64.h 2007-05-22 15:27:21.000000000 +1000
@@ -413,10 +413,14 @@ static inline void __ptep_set_access_fla
:"cc");
}
#define ptep_set_access_flags(__vma, __address, __ptep, __entry, __dirty) \
- do { \
- __ptep_set_access_flags(__ptep, __entry, __dirty); \
- flush_tlb_page_nohash(__vma, __address); \
- } while(0)
+({ \
+ int __changed = !pte_same(*(__ptep), __entry); \
+ if (__changed) { \
+ __ptep_set_access_flags(__ptep, __entry, __dirty); \
+ flush_tlb_page_nohash(__vma, __address); \
+ } \
+ __changed; \
+})
/*
* Macro to mark a page protection value as "uncacheable".
Index: linux-work/mm/memory.c
===================================================================
--- linux-work.orig/mm/memory.c 2007-05-22 15:04:45.000000000 +1000
+++ linux-work/mm/memory.c 2007-05-22 15:38:19.000000000 +1000
@@ -1691,9 +1691,10 @@ static int do_wp_page(struct mm_struct *
flush_cache_page(vma, address, pte_pfn(orig_pte));
entry = pte_mkyoung(orig_pte);
entry = maybe_mkwrite(pte_mkdirty(entry), vma);
- ptep_set_access_flags(vma, address, page_table, entry, 1);
- update_mmu_cache(vma, address, entry);
- lazy_mmu_prot_update(entry);
+ if (ptep_set_access_flags(vma, address, page_table, entry,1)) {
+ update_mmu_cache(vma, address, entry);
+ lazy_mmu_prot_update(entry);
+ }
ret |= VM_FAULT_WRITE;
goto unlock;
}
@@ -2525,10 +2526,9 @@ static inline int handle_pte_fault(struc
pte_t *pte, pmd_t *pmd, int write_access)
{
pte_t entry;
- pte_t old_entry;
spinlock_t *ptl;
- old_entry = entry = *pte;
+ entry = *pte;
if (!pte_present(entry)) {
if (pte_none(entry)) {
if (vma->vm_ops) {
@@ -2561,8 +2561,7 @@ static inline int handle_pte_fault(struc
entry = pte_mkdirty(entry);
}
entry = pte_mkyoung(entry);
- if (!pte_same(old_entry, entry)) {
- ptep_set_access_flags(vma, address, pte, entry, write_access);
+ if (ptep_set_access_flags(vma, address, pte, entry, write_access)) {
update_mmu_cache(vma, address, entry);
lazy_mmu_prot_update(entry);
} else {
Index: linux-work/include/asm-powerpc/pgtable-ppc32.h
===================================================================
--- linux-work.orig/include/asm-powerpc/pgtable-ppc32.h 2007-05-22 15:04:45.000000000 +1000
+++ linux-work/include/asm-powerpc/pgtable-ppc32.h 2007-05-22 15:26:07.000000000 +1000
@@ -673,10 +673,14 @@ static inline void __ptep_set_access_fla
}
#define ptep_set_access_flags(__vma, __address, __ptep, __entry, __dirty) \
- do { \
- __ptep_set_access_flags(__ptep, __entry, __dirty); \
- flush_tlb_page_nohash(__vma, __address); \
- } while(0)
+({ \
+ int __changed = !pte_same(*(__ptep), __entry); \
+ if (__changed) { \
+ __ptep_set_access_flags(__ptep, __entry, __dirty); \
+ flush_tlb_page_nohash(__vma, __address); \
+ } \
+ __changed; \
+})
/*
* Macro to mark a page protection value as "uncacheable".
Index: linux-work/include/asm-i386/pgtable.h
===================================================================
--- linux-work.orig/include/asm-i386/pgtable.h 2007-05-22 15:06:17.000000000 +1000
+++ linux-work/include/asm-i386/pgtable.h 2007-05-22 15:16:11.000000000 +1000
@@ -285,13 +285,15 @@ static inline pte_t native_local_ptep_ge
*/
#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
#define ptep_set_access_flags(vma, address, ptep, entry, dirty) \
-do { \
- if (dirty) { \
+({ \
+ int __changed = !pte_same(*(__ptep), __entry); \
+ if (__changed && dirty) { \
(ptep)->pte_low = (entry).pte_low; \
pte_update_defer((vma)->vm_mm, (address), (ptep)); \
flush_tlb_page(vma, address); \
} \
-} while (0)
+ __changed; \
+})
#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_DIRTY
#define ptep_test_and_clear_dirty(vma, addr, ptep) ({ \
Index: linux-work/include/asm-ppc/pgtable.h
===================================================================
--- linux-work.orig/include/asm-ppc/pgtable.h 2007-05-22 15:25:58.000000000 +1000
+++ linux-work/include/asm-ppc/pgtable.h 2007-05-22 15:26:08.000000000 +1000
@@ -694,10 +694,14 @@ static inline void __ptep_set_access_fla
}
#define ptep_set_access_flags(__vma, __address, __ptep, __entry, __dirty) \
- do { \
- __ptep_set_access_flags(__ptep, __entry, __dirty); \
- flush_tlb_page_nohash(__vma, __address); \
- } while(0)
+({ \
+ int __changed = !pte_same(*(__ptep), __entry); \
+ if (__changed) { \
+ __ptep_set_access_flags(__ptep, __entry, __dirty); \
+ flush_tlb_page_nohash(__vma, __address); \
+ } \
+ __changed; \
+})
/*
* Macro to mark a page protection value as "uncacheable".
Index: linux-work/include/asm-s390/pgtable.h
===================================================================
--- linux-work.orig/include/asm-s390/pgtable.h 2007-05-22 15:16:48.000000000 +1000
+++ linux-work/include/asm-s390/pgtable.h 2007-05-22 15:20:16.000000000 +1000
@@ -744,7 +744,12 @@ ptep_establish(struct vm_area_struct *vm
}
#define ptep_set_access_flags(__vma, __address, __ptep, __entry, __dirty) \
- ptep_establish(__vma, __address, __ptep, __entry)
+({ \
+ int __changed = !pte_same(*(__ptep), __entry); \
+ if (__changed) \
+ ptep_establish(__vma, __address, __ptep, __entry); \
+ __changed; \
+})
/*
* Test and clear dirty bit in storage key.
Index: linux-work/include/asm-sparc/pgtable.h
===================================================================
--- linux-work.orig/include/asm-sparc/pgtable.h 2007-05-22 15:30:48.000000000 +1000
+++ linux-work/include/asm-sparc/pgtable.h 2007-05-22 15:35:56.000000000 +1000
@@ -446,6 +446,17 @@ extern int io_remap_pfn_range(struct vm_
#define GET_IOSPACE(pfn) (pfn >> (BITS_PER_LONG - 4))
#define GET_PFN(pfn) (pfn & 0x0fffffffUL)
+#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
+#define ptep_set_access_flags(__vma, __address, __ptep, __entry, __dirty) \
+({ \
+ int __changed = !pte_same(*(__ptep), __entry); \
+ if (__changed) { \
+ set_pte_at((__vma)->vm_mm, (__address), __ptep, __entry); \
+ flush_tlb_page(__vma, __address); \
+ } \
+ (sparc_cpu_model == sun4c) || __changed; \
+})
+
#include <asm-generic/pgtable.h>
#endif /* !(__ASSEMBLY__) */
Index: linux-work/include/asm-x86_64/pgtable.h
===================================================================
--- linux-work.orig/include/asm-x86_64/pgtable.h 2007-05-22 15:20:40.000000000 +1000
+++ linux-work/include/asm-x86_64/pgtable.h 2007-05-22 15:21:52.000000000 +1000
@@ -395,12 +395,14 @@ static inline pte_t pte_modify(pte_t pte
* bit at the same time. */
#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
#define ptep_set_access_flags(__vma, __address, __ptep, __entry, __dirty) \
- do { \
- if (__dirty) { \
- set_pte(__ptep, __entry); \
- flush_tlb_page(__vma, __address); \
- } \
- } while (0)
+({ \
+ int __changed = !pte_same(*(__ptep), __entry); \
+ if (__changed && __dirty) { \
+ set_pte(__ptep, __entry); \
+ flush_tlb_page(__vma, __address); \
+ } \
+ __changed; \
+})
/* Encode and de-code a swap entry */
#define __swp_type(x) (((x).val >> 1) & 0x3f)
^ permalink raw reply
* [PATCH] powerpc: Fix warning on 32 bits with CONFIG_HIGHMEM
From: Benjamin Herrenschmidt @ 2007-05-22 6:25 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev list
Some missing fixup for the removal of 4 level fixup header
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Index: linux-work/arch/powerpc/mm/mem.c
===================================================================
--- linux-work.orig/arch/powerpc/mm/mem.c 2007-05-22 16:00:57.000000000 +1000
+++ linux-work/arch/powerpc/mm/mem.c 2007-05-22 16:02:06.000000000 +1000
@@ -310,11 +310,12 @@ void __init paging_init(void)
#ifdef CONFIG_HIGHMEM
map_page(PKMAP_BASE, 0, 0); /* XXX gross */
- pkmap_page_table = pte_offset_kernel(pmd_offset(pgd_offset_k
- (PKMAP_BASE), PKMAP_BASE), PKMAP_BASE);
+ pkmap_page_table = pte_offset_kernel(pmd_offset(pud_offset(pgd_offset_k
+ (PKMAP_BASE), PKMAP_BASE), PKMAP_BASE), PKMAP_BASE);
map_page(KMAP_FIX_BEGIN, 0, 0); /* XXX gross */
- kmap_pte = pte_offset_kernel(pmd_offset(pgd_offset_k
- (KMAP_FIX_BEGIN), KMAP_FIX_BEGIN), KMAP_FIX_BEGIN);
+ kmap_pte = pte_offset_kernel(pmd_offset(pud_offset(pgd_offset_k
+ (KMAP_FIX_BEGIN), KMAP_FIX_BEGIN), KMAP_FIX_BEGIN),
+ KMAP_FIX_BEGIN);
kmap_prot = PAGE_KERNEL;
#endif /* CONFIG_HIGHMEM */
^ permalink raw reply
* RE: [PATCH 0/5] Add the support for MPC8641 silicon rev 2.0 and MPC8641HPCN board 2.0
From: Zhang Wei-r63237 @ 2007-05-22 4:46 UTC (permalink / raw)
To: Kumar Gala; +Cc: linuxppc-dev, paulus
In-Reply-To: <B9B280B9-3F66-479B-ABB2-FD294EC25C7E@kernel.crashing.org>
Hi, Kumar,
Please see my inline comments:
> >
> > [PATCH 1/5] Remove the errata fix codes for MPC8641 silicon ver =20
> > 1.0 which is end of life.
This patch is not included in Wade's patch.
MPC8641 silicon 1.0 is end of life and not full following
PCI/PCI-Express specifications.
Rev 2.0 silicon fixes these PCI/PCI-Express errata and follows the
PCI/PCI-Ex specifications.
So, using generic PCI codes is okay.
> > [PATCH 2/5] Add uli1575 pci-bridge sector to MPC8641HPCN dts file.
This's a simple and clear solution to Wade's pci fix patch. Some changes
of Wade's pci fix patch are redundant.
> > [PATCH 3/5] Float the pci bus number on MPC8641HPCN board.
This patch is not included in Wade's patch.
Every PCI hose bus range number is started from 0 before. This patch
make the hose bus range number is started from previous hose last bus
number added one.
And PCI-Ex tranining status check is added to avoid the system halt.
> > [PATCH 4/5] Set RC of mpc8641 to transparent bridge for transfer =20
> > legacy I/O access.
This patch is different than Wade's pci fix patch.
Wade's pci patch changing MPC8641 PCI_CLASS property is not a good
solution. Only set it to transport bridge is okay.
And this quirk functions should applied to both MPC8641 and MPC8641D,
not only dual core version.
> > [PATCH 5/5] Set IDE in ULI1575 to not native mode.
This patch is not included in Wade's patch.
It makes IDE in ULI1575 works.
>=20
> How do these patches differ/interace from what Wade posted a=20
> few days =20
> ago?
Wade's MTD patch (patch 1), Legacy patch (patch 2), superIO patch (patch
3), RTC patch (patch 4) is not overlap with my patches.
But Wade's PCI patch (patch 5) most of codes is for supporting a
discontinued and end of life silicon and I do not agree with the changes
about PCI_CLASS of MPC8641. The dts fixing is too complex. I suggest to
reject Wade's PCI patch.
Thanks!
Wei
^ permalink raw reply
* [PATCH] powerpc: Fix powerpc vmlinux.lds.S
From: Benjamin Herrenschmidt @ 2007-05-22 4:33 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev list
Sam's recent changes broke things for us, some stuff sneaked in before
the entry point. In fact, we don't need that *(.text.*) thing anymore
and it incorrectly matched .text.init.refok, thus putting it
before .text. .. ouch !
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
Index: linux-work/arch/powerpc/kernel/vmlinux.lds.S
===================================================================
--- linux-work.orig/arch/powerpc/kernel/vmlinux.lds.S 2007-05-22 14:16:39.000000000 +1000
+++ linux-work/arch/powerpc/kernel/vmlinux.lds.S 2007-05-22 14:19:00.000000000 +1000
@@ -34,7 +34,6 @@ SECTIONS
/* Text and gots */
.text : {
_text = .;
- *(.text.*)
TEXT_TEXT
SCHED_TEXT
LOCK_TEXT
^ permalink raw reply
* Re: [PATCH 0/5] Add the support for MPC8641 silicon rev 2.0 and MPC8641HPCN board 2.0
From: Kumar Gala @ 2007-05-22 3:53 UTC (permalink / raw)
To: Zhang Wei; +Cc: linuxppc-dev, paulus
In-Reply-To: <11798051102658-git-send-email-wei.zhang@freescale.com>
On May 21, 2007, at 10:38 PM, Zhang Wei wrote:
> Hi, Paul,
>
> The below 5 patches add the support for MPC8641 rev 2.0 silicon and
> MPC8641HPCN board 2.0.
>
> [PATCH 1/5] Remove the errata fix codes for MPC8641 silicon ver
> 1.0 which is end of life.
> [PATCH 2/5] Add uli1575 pci-bridge sector to MPC8641HPCN dts file.
> [PATCH 3/5] Float the pci bus number on MPC8641HPCN board.
> [PATCH 4/5] Set RC of mpc8641 to transparent bridge for transfer
> legacy I/O access.
> [PATCH 5/5] Set IDE in ULI1575 to not native mode.
>
> The MPC8641 rev 2.0 silicon fix the PCI/PCI-Express errata in rev
> 1.0. And the rev 1.0 silicon is end of life. So the dts tree and
> codes should be changes. Codes which are not compatible with PCI/
> PCI-Express specifications are removed. Some minor issues are fixed.
How do these patches differ/interace from what Wade posted a few days
ago?
Also, please CC me on future Freescale related patches.
- k
^ permalink raw reply
* [PATCH 0/5] Add the support for MPC8641 silicon rev 2.0 and MPC8641HPCN board 2.0
From: Zhang Wei @ 2007-05-22 3:38 UTC (permalink / raw)
To: paulus; +Cc: linuxppc-dev
Hi, Paul,
The below 5 patches add the support for MPC8641 rev 2.0 silicon and MPC8641HPCN board 2.0.
[PATCH 1/5] Remove the errata fix codes for MPC8641 silicon ver 1.0 which is end of life.
[PATCH 2/5] Add uli1575 pci-bridge sector to MPC8641HPCN dts file.
[PATCH 3/5] Float the pci bus number on MPC8641HPCN board.
[PATCH 4/5] Set RC of mpc8641 to transparent bridge for transfer legacy I/O access.
[PATCH 5/5] Set IDE in ULI1575 to not native mode.
The MPC8641 rev 2.0 silicon fix the PCI/PCI-Express errata in rev 1.0. And the rev 1.0 silicon is end of life. So the dts tree and codes should be changes. Codes which are not compatible with PCI/PCI-Express specifications are removed. Some minor issues are fixed.
Thanks!
Best Regards,
Zhang Wei
^ permalink raw reply
* [PATCH 1/5] Remove the errata fix codes for MPC8641 silicon ver 1.0 which is end of life.
From: Zhang Wei @ 2007-05-22 3:38 UTC (permalink / raw)
To: paulus; +Cc: linuxppc-dev
In-Reply-To: <11798051102658-git-send-email-wei.zhang@freescale.com>
Remove the errata fix codes for MPC8641 silicon ver 1.0 which
is end of life.
The MPC8641 silicon ver 1.0 is not fully support PCI/PCI Express
specifications. The revision 2.0 fixes all of these errata
and the rev 1.0 silicon is end of life. So errata codes are removed.
Now, The chip is full compatible with PCI/PCI Express
specifications. The generic PCI code is used.
Signed-off-by: Zhang Wei <wei.zhang@freescale.com>
Acked-by: Roy Zang <tie-fei.zang@freescale.com>
---
arch/powerpc/Kconfig | 3 +--
arch/powerpc/platforms/86xx/mpc86xx.h | 6 ------
arch/powerpc/platforms/86xx/pci.c | 10 +---------
3 files changed, 2 insertions(+), 17 deletions(-)
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index f768de3..42c2c57 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -175,7 +175,6 @@ config PPC_86xx
bool "Freescale 86xx"
select 6xx
select FSL_SOC
- select FSL_PCIE
select PPC_FPU
select ALTIVEC
help
@@ -647,7 +646,7 @@ config FSL_SOC
config FSL_PCIE
bool
- depends on PPC_86xx
+ depends on PPC_85xx
# Yes MCA RS/6000s exist but Linux-PPC does not currently support any
config MCA
diff --git a/arch/powerpc/platforms/86xx/mpc86xx.h b/arch/powerpc/platforms/86xx/mpc86xx.h
index 2834462..740b300 100644
--- a/arch/powerpc/platforms/86xx/mpc86xx.h
+++ b/arch/powerpc/platforms/86xx/mpc86xx.h
@@ -19,12 +19,6 @@ extern int add_bridge(struct device_node *dev);
extern int mpc86xx_exclude_device(u_char bus, u_char devfn);
-extern void setup_indirect_pcie(struct pci_controller *hose,
- u32 cfg_addr, u32 cfg_data);
-extern void setup_indirect_pcie_nomap(struct pci_controller *hose,
- void __iomem *cfg_addr,
- void __iomem *cfg_data);
-
extern void __init mpc86xx_smp_init(void);
#endif /* __MPC86XX_H__ */
diff --git a/arch/powerpc/platforms/86xx/pci.c b/arch/powerpc/platforms/86xx/pci.c
index 8235c56..7efae7c 100644
--- a/arch/powerpc/platforms/86xx/pci.c
+++ b/arch/powerpc/platforms/86xx/pci.c
@@ -133,18 +133,10 @@ mpc86xx_setup_pcie(struct pci_controller *hose, u32 pcie_offset, u32 pcie_size)
early_write_config_word(hose, 0, 0, PCI_COMMAND, cmd);
early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80);
-
- /* PCIE Bus, Fix the MPC8641D host bridge's location to bus 0xFF. */
- early_read_config_dword(hose, 0, 0, PCI_PRIMARY_BUS, &temps);
- temps = (temps & 0xff000000) | (0xff) | (0x0 << 8) | (0xfe << 16);
- early_write_config_dword(hose, 0, 0, PCI_PRIMARY_BUS, temps);
}
int mpc86xx_exclude_device(u_char bus, u_char devfn)
{
- if (bus == 0 && PCI_SLOT(devfn) == 0)
- return PCIBIOS_DEVICE_NOT_FOUND;
-
return PCIBIOS_SUCCESSFUL;
}
@@ -178,7 +170,7 @@ int __init add_bridge(struct device_node *dev)
hose->first_busno = bus_range ? bus_range[0] : 0x0;
hose->last_busno = bus_range ? bus_range[1] : 0xfe;
- setup_indirect_pcie(hose, rsrc.start, rsrc.start + 0x4);
+ setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4);
/* Setup the PCIE host controller. */
mpc86xx_setup_pcie(hose, rsrc.start, rsrc.end - rsrc.start + 1);
--
1.5.1
^ permalink raw reply related
* [PATCH 3/5] Float the pci bus number on MPC8641HPCN board.
From: Zhang Wei @ 2007-05-22 3:38 UTC (permalink / raw)
To: paulus; +Cc: linuxppc-dev
In-Reply-To: <1179805110272-git-send-email-wei.zhang@freescale.com>
Float the pci bus number on MPC8641HPCN board.
For example, PCI hose 1 bus range is from 0 to 2, the PCI hose 2 bus
range will start from 3.
Add the pci-express link training stats check. It avoid the system halt
while the link training is fault.
Signed-off-by: Zhang Wei <wei.zhang@freescale.com>
Acked-by: Roy Zang <tie-fei.zang@freescale.com>
---
arch/powerpc/platforms/86xx/mpc86xx_hpcn.c | 1 +
arch/powerpc/platforms/86xx/pci.c | 23 ++++++++++++++++++++++-
2 files changed, 23 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c b/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c
index ae5714f..2dacc33 100644
--- a/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c
+++ b/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c
@@ -358,6 +358,7 @@ mpc86xx_hpcn_setup_arch(void)
}
#ifdef CONFIG_PCI
+ pci_assign_all_buses = 1;
for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;)
add_bridge(np);
diff --git a/arch/powerpc/platforms/86xx/pci.c b/arch/powerpc/platforms/86xx/pci.c
index 7efae7c..5612f6a 100644
--- a/arch/powerpc/platforms/86xx/pci.c
+++ b/arch/powerpc/platforms/86xx/pci.c
@@ -122,7 +122,6 @@ static void __init
mpc86xx_setup_pcie(struct pci_controller *hose, u32 pcie_offset, u32 pcie_size)
{
u16 cmd;
- unsigned int temps;
DBG("PCIE host controller register offset 0x%08x, size 0x%08x.\n",
pcie_offset, pcie_size);
@@ -137,9 +136,23 @@ mpc86xx_setup_pcie(struct pci_controller *hose, u32 pcie_offset, u32 pcie_size)
int mpc86xx_exclude_device(u_char bus, u_char devfn)
{
+ struct pci_controller *hose;
+
+ hose = pci_bus_to_hose(bus);
+ if (unlikely(!hose))
+ return PCIBIOS_DEVICE_NOT_FOUND;
+
+ /* Correcting the hose->bus_offset value. */
+ out_be32(hose->cfg_addr, 0x80000000 | ((hose->first_busno
+ - hose->bus_offset) << 16));
+ if (unlikely(in_le32(hose->cfg_data) == 0xffffffff))
+ hose->bus_offset = hose->bus_offset ? 0 : hose->first_busno;
+
return PCIBIOS_SUCCESSFUL;
}
+#define PCIE_LTSSM 0x04000004 /* PCIe Link Training and Status */
+#define PCIE_LTSSM_L0 0x16 /* L0 state */
int __init add_bridge(struct device_node *dev)
{
int len;
@@ -148,12 +161,20 @@ int __init add_bridge(struct device_node *dev)
const int *bus_range;
int has_address = 0;
int primary = 0;
+ void *pcicfg_addr;
DBG("Adding PCIE host bridge %s\n", dev->full_name);
/* Fetch host bridge registers address */
has_address = (of_address_to_resource(dev, 0, &rsrc) == 0);
+ /* Probe the hose link training status */
+ pcicfg_addr = ioremap(rsrc.start, 0x1000);
+ out_be32(pcicfg_addr, 0x80000000 | PCIE_LTSSM);
+ if (in_le16(pcicfg_addr + 4) < PCIE_LTSSM_L0)
+ return -ENXIO;
+ iounmap(pcicfg_addr);
+
/* Get bus range if any */
bus_range = of_get_property(dev, "bus-range", &len);
if (bus_range == NULL || len < 2 * sizeof(int))
--
1.5.1
^ permalink raw reply related
* [PATCH 4/5] Set RC of mpc8641 to transparent bridge for transfer legacy I/O access.
From: Zhang Wei @ 2007-05-22 3:38 UTC (permalink / raw)
To: paulus; +Cc: linuxppc-dev
In-Reply-To: <1179805110278-git-send-email-wei.zhang@freescale.com>
Set RC of mpc8641 to transparent bridge for transfer legacy I/O access.
Now, the children bus could use the I/O resource of the host bridge.
Note: The 0x7010 is the device ID of host bridge for MPC8641 and
0x7011 is the device ID of host bridge fro MPC8641D.
Signed-off-by: Zhang Wei <wei.zhang@freescale.com>
---
arch/powerpc/platforms/86xx/mpc86xx_hpcn.c | 7 +++++++
1 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c b/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c
index 2dacc33..eb2bc99 100644
--- a/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c
+++ b/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c
@@ -319,6 +319,11 @@ static void __devinit quirk_uli5229(struct pci_dev *dev)
pci_write_config_word(dev, 0x4a, temp);
}
+static void __devinit quirk_mpc8641_transparent(struct pci_dev *dev)
+{
+ dev->transparent = 1;
+}
+
static void __devinit early_uli5249(struct pci_dev *dev)
{
unsigned char temp;
@@ -333,6 +338,8 @@ static void __devinit early_uli5249(struct pci_dev *dev)
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x1575, quirk_uli1575);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5288, quirk_uli5288);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5229, quirk_uli5229);
+DECLARE_PCI_FIXUP_HEADER(0x1957, 0x7010, quirk_mpc8641_transparent);
+DECLARE_PCI_FIXUP_HEADER(0x1957, 0x7011, quirk_mpc8641_transparent);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AL, 0x5249, early_uli5249);
#endif /* CONFIG_PCI */
--
1.5.1
^ permalink raw reply related
* [PATCH 5/5] Set IDE in ULI1575 to not native mode.
From: Zhang Wei @ 2007-05-22 3:38 UTC (permalink / raw)
To: paulus; +Cc: linuxppc-dev
In-Reply-To: <11798051102051-git-send-email-wei.zhang@freescale.com>
Set IDE in ULI1575 to not 100% native mode, which forces
the IDE driver to probe the irq itself.
Signed-off-by: Zhang Wei <wei.zhang@freescale.com>
---
arch/powerpc/platforms/86xx/mpc86xx_hpcn.c | 1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c b/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c
index eb2bc99..2a2dea7 100644
--- a/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c
+++ b/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c
@@ -314,6 +314,7 @@ static void __devinit quirk_uli5229(struct pci_dev *dev)
{
unsigned short temp;
pci_write_config_word(dev, 0x04, 0x0405);
+ dev->class &= ~0x5;
pci_read_config_word(dev, 0x4a, &temp);
temp |= 0x1000;
pci_write_config_word(dev, 0x4a, temp);
--
1.5.1
^ permalink raw reply related
* [PATCH 2/5] Add uli1575 pci-bridge sector to MPC8641HPCN dts file.
From: Zhang Wei @ 2007-05-22 3:38 UTC (permalink / raw)
To: paulus; +Cc: linuxppc-dev
In-Reply-To: <11798051101543-git-send-email-wei.zhang@freescale.com>
Add uli1575 pci-bridge sector. It fixes the issue of ULI1575 not found on rev.2 board.
Signed-off-by: Zhang Wei <wei.zhang@freescale.com>
---
arch/powerpc/boot/dts/mpc8641_hpcn.dts | 6 ++++++
arch/powerpc/boot/dts/mpc8641_hpcn_srio.dts | 6 ++++++
2 files changed, 12 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/boot/dts/mpc8641_hpcn.dts b/arch/powerpc/boot/dts/mpc8641_hpcn.dts
index 260b264..04626b1 100644
--- a/arch/powerpc/boot/dts/mpc8641_hpcn.dts
+++ b/arch/powerpc/boot/dts/mpc8641_hpcn.dts
@@ -297,6 +297,12 @@
interrupts = <49 2>;
interrupt-parent = <&mpic>;
};
+ uli1575: uli1575@100 {
+ reg = <0 0 0 0 0>;
+ pci_bridge@200 {
+ reg = <0 0 0 0 0>;
+ };
+ };
};
--
1.5.1
^ permalink raw reply related
* Re: fsl booke MM vs. SMP questions
From: Benjamin Herrenschmidt @ 2007-05-22 3:09 UTC (permalink / raw)
To: Dave Liu; +Cc: ppc-dev, Paul Mackerras, Kumar Gala
In-Reply-To: <1179785273.32247.742.camel@localhost.localdomain>
> > > Now, the tlb invalidation code (which can use a batch to be even more
> > > efficient, see how 64 bits or x86 use batching for TLB invalidations)
> > > can then use the fact that the mm carries a cpu bitmask of all CPUs that
> > > ever touched that mm and thus can do, after a PTE has changed and before
> > > broadcasting an invalidation:
> >
> > How to interlock this PTE change with the PTE change of tlb miss?
>
> Look at pgtables-ppc32.h. PTE changes done by linux are atomic. If you
> use the procedure I outlined above, you will also have PTE modifications
> done by the TLB miss handler be atomic, though you also skip the atomic
> bit when not necessary (when _PAGE_ACCESSED is already set for example).
>
> Thus, the situation is basically that linux PTE changes need to
Note that overall, my method requires at least those barriers:
- setting the flag to 1 vs. reading the PTE
- writing the TLB entry vs. setting the flag to 0
Which means two barriers in the TLB refill handler. I'm not 100%
familiar with the barriers you have on fsl BookE and their exact
semantics and performance issues but you may need to closely look at the
impact of taking those.
In the end, the best solution might still be to simply not do any of
this and instead send an IPI on invalidations. That's the method used by
most architectures in linux (if not all) that do software TLB load on
SMP. Basically, the invalidate code path then does:
- Update the linux PTE
- write barrier
- send IPI interrupt to all CPUs in mm->cpu_vm_mask
- local TLB flush
And the IPI does a local TLB flush on all affected CPUs.
Ben.
^ permalink raw reply
* Re: fsl booke MM vs. SMP questions
From: Kumar Gala @ 2007-05-22 3:03 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: ppc-dev, Paul Mackerras, Kumar Gala
In-Reply-To: <1179731215.32247.659.camel@localhost.localdomain>
On May 21, 2007, at 2:06 AM, Benjamin Herrenschmidt wrote:
> Hi Folks !
>
> I see that the fsl booke code has some #ifdef CONFIG_SMP bits here or
> there, thus I suppose there are some SMP implementations of these
> right ?
There will be, the SMP code that exists was just some stuff I put in
w/o going through each case. The TLB mgmt code does need some fixup
for SMP.
- k
>
> I'm having some serious issues trying to figure out how the TLB
> management is made SMP safe however.
>
> There are at least two main issues I've spotted at this point (there's
> at least one more if there are HW threading, that is the TLB is shared
> between logical processors, but I'll ignore that for now since I don't
> think there is such a thing ... yet).
>
> - How do you guys shield PTE flushing vs. TLB misses on another CPU ?
> That is, how do you prevent (if you do) the following scenario:
>
> cpu 0 cpu 1
> tlb miss pte_clear (or similar)
> load PTE value
> write 0 to PTE (or replace)
> tlbviax (tlbie)
> tlbwe
>
> That scenario, as you can see, will leave you with stale entries in
> the
> TLB which will ultimately lead to all sort of unpleasant/random
> behaviours.
>
> If the answer is "oops ... we don't", then let's try to find out ways
> out of that since I may have a similar issue in a not too distant
> future :-) And I'm trying to find out a -fast- way to deal with that
> without bloating the fast path. My main problem is that I want to
> avoid
> taking a spin lock or equivalent atomic operation in the fast TLB
> reload
> path (which would solve the problem) since lwarx/stwcx. are generally
> real slow (hundreds of cycles on some processors).
>
> - I see that your TLB miss handle is using a non-atomic store to
> write
> the _PAGE_ACCESSED bit back to the PTE. Don't you have a similar race
> where something would do:
>
> cpu 0 cpu 1
> tlb miss pte_clear (or similar)
> load PTE value
> write 0 to PTE (or replace)
> write back PTE with _PAGE_ACCESSED
> tlbwe
>
> This is an extension of the previous race but it's a different problem
> so I listed it separately. In that case, the problem is worse,
> since not
> only you have a stale TLB entry, but you -also- have corrupted the
> linux
> PTE by writing back the old value in it.
>
> At this point, I'm afraid you may have no choice but going atomic,
> which
> means paying the cost of lwarx/stwcx. on TLB misses, though if you
> have
> a solution for the first problem, then you can avoid the atomic
> operation in the second problem if _PAGE_ACCESSED is already set.
>
> If not, you might have to use a _PAGE_BUSY bit similar to what 64 bits
> uses as a per-PTE lock, or use mmu_hash_lock... Unless you come up
> with
> a great idea or some HW black magic that makes the problem go away...
>
> In any case, I'm curious about how you have or intend to solve that
> since as I said above, I might be in a similar situation soon and am
> trying to keep the TLB miss handler as fast as humanly possible.
>
> Cheers,
> Ben.
>
^ permalink raw reply
* RE: [PATCH 5/5] PCI fixes for the MPC8641 Rev 2.0 silicon andRev1.02hardware
From: Zhang Wei-r63237 @ 2007-05-22 2:53 UTC (permalink / raw)
To: Wade Farnsworth; +Cc: linuxppc-dev
In-Reply-To: <1179763271.8132.288.camel@rhino>
Hi, Wade,
That's a good news. These codes is one of our patches. I'll commit them
myself.
Thanks!=20
-Wei
>=20
> Hmm. For some reason I thought that wouldn't work, but after some
> testing it appears I was wrong. I'll incorporate that into the next
> version of the patchset.
>=20
> Thanks.
>=20
> --Wade
>=20
>=20
^ permalink raw reply
* Re: [PATCH] pseries: asm/pci-bridge.h CONFIG_ minor cleanup
From: Michael Ellerman @ 2007-05-22 0:40 UTC (permalink / raw)
To: Linas Vepstas; +Cc: linuxppc-dev, Paul Mackerras
In-Reply-To: <20070521231816.GH5921@austin.ibm.com>
[-- Attachment #1: Type: text/plain, Size: 2325 bytes --]
On Mon, 2007-05-21 at 18:18 -0500, Linas Vepstas wrote:
> Use the correct CONFIG_ option to mark off the EEH bits.
> Move the EEH bits to the bottom of the struct.
>
> Signed-off-by: Linas Vepstas <linas@austin.ibm.com>
>
> ----
> include/asm-powerpc/pci-bridge.h | 15 ++++++++-------
> 1 file changed, 8 insertions(+), 7 deletions(-)
>
> Index: linux-2.6.22-rc1/include/asm-powerpc/pci-bridge.h
> ===================================================================
> --- linux-2.6.22-rc1.orig/include/asm-powerpc/pci-bridge.h 2007-05-21 18:13:00.000000000 -0500
> +++ linux-2.6.22-rc1/include/asm-powerpc/pci-bridge.h 2007-05-21 18:13:36.000000000 -0500
> @@ -70,19 +70,20 @@ struct pci_dn {
> int devfn; /* pci device and function number */
> int class_code; /* pci device class */
>
> -#ifdef CONFIG_PPC_PSERIES
> - int eeh_mode; /* See eeh.h for possible EEH_MODEs */
> - int eeh_config_addr;
> - int eeh_pe_config_addr; /* new-style partition endpoint address */
> - int eeh_check_count; /* # times driver ignored error */
> - int eeh_freeze_count; /* # times this device froze up. */
> -#endif
You're making the struct 4 bytes larger by creating a hole here :(
> int pci_ext_config_space; /* for pci devices */
> struct pci_controller *phb; /* for pci devices */
> struct iommu_table *iommu_table; /* for phb's or bridges */
> struct pci_dev *pcidev; /* back-pointer to the pci device */
> struct device_node *node; /* back-pointer to the device_node */
> +
> +#ifdef CONFIG_EEH
> + int eeh_mode; /* See eeh.h for possible EEH_MODEs */
> + int eeh_config_addr;
> + int eeh_pe_config_addr; /* new-style partition endpoint address */
> + int eeh_check_count; /* # times driver ignored error */
> + int eeh_freeze_count; /* # times this device froze up. */
> u32 config_space[16]; /* saved PCI config space */
> +#endif
It looks correct, but I think it's worth mentioning in the changelog
that config_space was previously unconditionally defined, but is now
within CONFIG_EEH.
cheers
--
Michael Ellerman
OzLabs, IBM Australia Development Lab
wwweb: http://michael.ellerman.id.au
phone: +61 2 6212 1183 (tie line 70 21183)
We do not inherit the earth from our ancestors,
we borrow it from our children. - S.M.A.R.T Person
[-- Attachment #2: This is a digitally signed message part --]
[-- Type: application/pgp-signature, Size: 189 bytes --]
^ permalink raw reply
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox