* pcimsg patch from eons ago
From: Grant Likely @ 2007-05-29 5:40 UTC (permalink / raw)
To: Adrian Cox, Linux PPC
Adrian,
Way back in the 2.2 timeframe, you had modified the ARM pcimsg patch
to port it to PPC and add features.
http://www.cs.helsinki.fi/linux/linux-kernel/2001-07/0572.html
I'd really like to take a look at it. I've been unable to find the
patch archived anywhere online in my searching. Do you still have a
copy of it tucked away anywhere?
Thanks,
g.
--
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.
grant.likely@secretlab.ca
(403) 399-0195
^ permalink raw reply
* Don't use HOSTCFLAGS in BOOTCFLAGS
From: David Gibson @ 2007-05-29 5:37 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev
In the bootwrapper code for powerpc, we include HOSTCFLAGS into the
BOOTCFLAGS used for buildinf the zImage wrapper code. Since the
wrapper code is not host code, this makes no sense. This patch
removes the use of HOSTCFLAGS here, instead including directly into
BOOTCFLAGS those flags from the normal kernel CFLAGS which also make
sense in the bootwrapper code.
In particular, this makes the bootwrapper use -msoft-float, preventing
the compiler from generating floating point instructions. Previously,
under some circumstances the compiler could generate floating point
instructions in the bootwrapper which would cause exceptions on
embedded CPUS which don't have floating point support.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Index: working-2.6/arch/powerpc/boot/Makefile
===================================================================
--- working-2.6.orig/arch/powerpc/boot/Makefile 2007-05-29 15:22:07.000000000 +1000
+++ working-2.6/arch/powerpc/boot/Makefile 2007-05-29 15:31:30.000000000 +1000
@@ -11,20 +11,18 @@
# bootloader and increase compatibility with OpenFirmware.
#
# To this end we need to define BOOTCC, etc, as the tools
-# needed to build the 32 bit image. These are normally HOSTCC,
-# but may be a third compiler if, for example, you are cross
-# compiling from an intel box. Once the 64bit ppc gcc is
-# stable it will probably simply be a compiler switch to
-# compile for 32bit mode.
+# needed to build the 32 bit image. That's normally the same
+# compiler for the rest of the kernel, with the -m32 flag added.
# To make it easier to setup a cross compiler,
# CROSS32_COMPILE is setup as a prefix just like CROSS_COMPILE
# in the toplevel makefile.
all: $(obj)/zImage
-HOSTCC := gcc
-BOOTCFLAGS := $(HOSTCFLAGS) -fno-builtin -nostdinc -isystem \
- $(shell $(CROSS32CC) -print-file-name=include) -fPIC
+BOOTCFLAGS := -Wall -Wundef -Wstrict-prototypes -Wno-trigraphs \
+ -fno-strict-aliasing -Os -msoft-float -pipe \
+ -fomit-frame-pointer -fno-builtin -fPIC -nostdinc \
+ -isystem $(shell $(CROSS32CC) -print-file-name=include)
BOOTAFLAGS := -D__ASSEMBLY__ $(BOOTCFLAGS) -traditional -nostdinc
ifeq ($(call cc-option-yn, -fstack-protector),y)
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
^ permalink raw reply
* Re: [PATCH] Powerpc compiler error fix for 2.6.21-rt8
From: Pradyumna Sampath @ 2007-05-29 5:36 UTC (permalink / raw)
To: linuxppc-embedded, linux-rt-users
In-Reply-To: <f87351060705282124q6d6b1562ic1dd4da4b8a62886@mail.gmail.com>
Oops !
Sorry missed this http://patchwork.ozlabs.org/linuxppc/patch?id=11304 .
regards
prady
On 5/29/07, Pradyumna Sampath <pradyumna.sampath@gmail.com> wrote:
> Hi everyone,
>
> Attached is a small patch to fix compile time errors which is broken
> in 2.6.21-rt8 for powerpc.
>
> thanks
> regards
> prady
>
>
--
htp://prady.livejournal.com
^ permalink raw reply
* Re: Don't use HOSTCFLAGS in BOOTCFLAGS
From: David Gibson @ 2007-05-29 5:34 UTC (permalink / raw)
To: Segher Boessenkool; +Cc: linuxppc-dev, Paul Mackerras
In-Reply-To: <d35e07648ef5813bd9e3572eec36bfb3@kernel.crashing.org>
On Tue, May 29, 2007 at 07:12:21AM +0200, Segher Boessenkool wrote:
> > # To this end we need to define BOOTCC, etc, as the tools
> > -# needed to build the 32 bit image. These are normally HOSTCC,
> > +# needed to build the 32 bit image.
> > # but may be a third compiler if, for example, you are cross
>
> You've broken this comment, you should pay for it now :-)
Eck, yes.
> > -HOSTCC := gcc
> > -BOOTCFLAGS := $(HOSTCFLAGS) -fno-builtin -fno-unit-at-a-time
> > -nostdinc -isystem \
> > - $(shell $(CROSS32CC) -print-file-name=include) -fPIC
> > +BOOTCFLAGS := -Wall -Wundef -Wstrict-prototypes -Wno-trigraphs \
> > + -fno-strict-aliasing -O2 -msoft-float -pipe \
>
> -Os instead?
Hrm, yeah, that's probably a good idea.
> > + -fomit-frame-pointer -fno-builtin -fno-unit-at-a-time \
>
> Why -fno-unit-at-a-time ?
Crap. Because I forgot that the patch stack I was working on had my
patch which adds -fno-unit-at-a-time (I often use that when debugging,
because it makes the disassembly more comprehensible). In fact
without that patch, this one doesn't apply.
> > + -fPIC -nostdinc \
> > + -isystem $(shell $(CROSS32CC) -print-file-name=include)
>
> Also, is there any reason why you can't simply use $(CC) -m32 with
> the kernel $(CFLAGS) ?
I did think about that. But the kernel CFLAGS does includes
-ffixed-r2 and -Iarch/powerpc which I don't think we want here.
Revised version coming shortly.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
^ permalink raw reply
* Re: Don't use HOSTCFLAGS in BOOTCFLAGS
From: Segher Boessenkool @ 2007-05-29 5:12 UTC (permalink / raw)
To: David Gibson; +Cc: linuxppc-dev, Paul Mackerras
In-Reply-To: <20070529032924.GA30266@localhost.localdomain>
> # To this end we need to define BOOTCC, etc, as the tools
> -# needed to build the 32 bit image. These are normally HOSTCC,
> +# needed to build the 32 bit image.
> # but may be a third compiler if, for example, you are cross
You've broken this comment, you should pay for it now :-)
> -HOSTCC := gcc
> -BOOTCFLAGS := $(HOSTCFLAGS) -fno-builtin -fno-unit-at-a-time
> -nostdinc -isystem \
> - $(shell $(CROSS32CC) -print-file-name=include) -fPIC
> +BOOTCFLAGS := -Wall -Wundef -Wstrict-prototypes -Wno-trigraphs \
> + -fno-strict-aliasing -O2 -msoft-float -pipe \
-Os instead?
> + -fomit-frame-pointer -fno-builtin -fno-unit-at-a-time \
Why -fno-unit-at-a-time ?
> + -fPIC -nostdinc \
> + -isystem $(shell $(CROSS32CC) -print-file-name=include)
Also, is there any reason why you can't simply use $(CC) -m32 with
the kernel $(CFLAGS) ?
Segher
^ permalink raw reply
* Re: Fix problems with Holly's DT representation of ethernet PHYs
From: David Gibson @ 2007-05-29 4:47 UTC (permalink / raw)
To: Segher Boessenkool; +Cc: Alexandre Bounine, linuxppc-dev list
In-Reply-To: <3b1087a7734a3836346e181eef4b606a@kernel.crashing.org>
On Mon, May 28, 2007 at 01:06:11PM +0200, Segher Boessenkool wrote:
> >>> - Second, the PHYs give only "bcm54xx" as a compatible
> >>> property. This is unfortunate, because there are many bcm54xx PHY
> >>> models, and they have differences which can matter. We add a more
> >>> precise compatible string, giving the precise PHY model (bcm5461A in
> >>> this case).
> >>
> >> You completely removed the "compatible" properties instead.
> >> Bad idea.
> >
> > Um... weren't you the one that was just saying compatible properties
> > aren't necessary if you can distinguish the hardware in other ways?
>
> The OS device driver doesn't need "compatible" if it
> can probe the device some other way; it doesn't need
> the device node at all, even. You still should have
> a "compatible" property (or, old style, a specific
> "name" property) if you want the OS to be able to use
> the device node to recognise the device (i.e., if a
> device node for the device exists at all: always).
Hrm. Ok. compatible property restored.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
^ permalink raw reply
* powerpc: Merge CPU features pertaining to icache coherency
From: David Gibson @ 2007-05-29 4:38 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev
Currently the powerpc kernel has a 64-bit only feature,
COHERENT_ICACHE used for those CPUS which maintain icache/dcache
coherency in hardware (POWER5, essentially). It also has a feature,
SPLIT_ID_CACHE, which is used on CPUs which have separate i and
d-caches, which is to say everything except 601 and Freescale E200.
In nearly all the places we check the SPLIT_ID_CACHE, what we actually
care about is whether the i and d-caches are coherent (which they will
be, trivially, if they're the same cache).
This patch tries to clarify the situation a little. The
COHERENT_ICACHE feature becomes availble on 32-bit and is set for all
CPUs where i and d-cache are effectively coherent, whether this is due
to special logic (POWER5) or because they're unified. We check this,
instead of SPLIT_ID_CACHE nearly everywhere.
The SPLIT_ID_CACHE feature itself is replaced by a UNIFIED_ID_CACHE
feature with reversed sense, set only on 601 and Freescale E200. In
the two places (one Freescale BookE specific) where we really care
whether it's a unified cache, not whether they're coherent, we check
this feature. The CPUs with unified cache are so few, we could
consider replacing this feature bit with explicit checks against the
PVR.
This patch will make unifying the 32-bit and 64-bit cache flush code a
little more straightforward.
Signed-off-by: David Gibson <dwg@au1.ibm.com>
arch/powerpc/kernel/cputable.c | 3 -
arch/powerpc/kernel/misc_32.S | 12 ++---
arch/powerpc/kernel/misc_64.S | 4 -
arch/powerpc/kernel/setup_32.c | 12 ++---
arch/ppc/kernel/misc.S | 12 ++---
arch/ppc/kernel/setup.c | 2
include/asm-powerpc/cputable.h | 88 ++++++++++++++++++++---------------------
7 files changed, 66 insertions(+), 67 deletions(-)
Index: working-2.6/include/asm-powerpc/cputable.h
===================================================================
--- working-2.6.orig/include/asm-powerpc/cputable.h 2007-05-21 12:47:17.000000000 +1000
+++ working-2.6/include/asm-powerpc/cputable.h 2007-05-29 14:34:24.000000000 +1000
@@ -111,7 +111,7 @@ extern void do_feature_fixups(unsigned l
/* CPU kernel features */
/* Retain the 32b definitions all use bottom half of word */
-#define CPU_FTR_SPLIT_ID_CACHE ASM_CONST(0x0000000000000001)
+#define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x0000000000000001)
#define CPU_FTR_L2CR ASM_CONST(0x0000000000000002)
#define CPU_FTR_SPEC7450 ASM_CONST(0x0000000000000004)
#define CPU_FTR_ALTIVEC ASM_CONST(0x0000000000000008)
@@ -135,6 +135,7 @@ extern void do_feature_fixups(unsigned l
#define CPU_FTR_PPC_LE ASM_CONST(0x0000000000200000)
#define CPU_FTR_REAL_LE ASM_CONST(0x0000000000400000)
#define CPU_FTR_FPU_UNAVAILABLE ASM_CONST(0x0000000000800000)
+#define CPU_FTR_UNIFIED_ID_CACHE ASM_CONST(0x0000000001000000)
/*
* Add the 64-bit processor unique features in the top half of the word;
@@ -154,7 +155,6 @@ extern void do_feature_fixups(unsigned l
#define CPU_FTR_MMCRA LONG_ASM_CONST(0x0000004000000000)
#define CPU_FTR_CTRL LONG_ASM_CONST(0x0000008000000000)
#define CPU_FTR_SMT LONG_ASM_CONST(0x0000010000000000)
-#define CPU_FTR_COHERENT_ICACHE LONG_ASM_CONST(0x0000020000000000)
#define CPU_FTR_LOCKLESS_TLBIE LONG_ASM_CONST(0x0000040000000000)
#define CPU_FTR_CI_LARGE_PAGE LONG_ASM_CONST(0x0000100000000000)
#define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000200000000000)
@@ -206,164 +206,163 @@ extern void do_feature_fixups(unsigned l
!defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \
!defined(CONFIG_BOOKE))
-#define CPU_FTRS_PPC601 (CPU_FTR_COMMON | CPU_FTR_601 | CPU_FTR_HPTE_TABLE)
-#define CPU_FTRS_603 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
+#define CPU_FTRS_PPC601 (CPU_FTR_COMMON | CPU_FTR_601 | CPU_FTR_HPTE_TABLE | \
+ CPU_FTR_UNIFIED_ID_CACHE)
+#define CPU_FTRS_603 (CPU_FTR_COMMON | \
CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
-#define CPU_FTRS_604 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
+#define CPU_FTRS_604 (CPU_FTR_COMMON | \
CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE | \
CPU_FTR_PPC_LE)
-#define CPU_FTRS_740_NOTAU (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
+#define CPU_FTRS_740_NOTAU (CPU_FTR_COMMON | \
CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
-#define CPU_FTRS_740 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
+#define CPU_FTRS_740 (CPU_FTR_COMMON | \
CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
CPU_FTR_PPC_LE)
-#define CPU_FTRS_750 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
+#define CPU_FTRS_750 (CPU_FTR_COMMON | \
CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
CPU_FTR_PPC_LE)
-#define CPU_FTRS_750CL (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
+#define CPU_FTRS_750CL (CPU_FTR_COMMON | \
CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
CPU_FTR_HAS_HIGH_BATS | CPU_FTR_PPC_LE)
-#define CPU_FTRS_750FX1 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
+#define CPU_FTRS_750FX1 (CPU_FTR_COMMON | \
CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM | CPU_FTR_PPC_LE)
-#define CPU_FTRS_750FX2 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
+#define CPU_FTRS_750FX2 (CPU_FTR_COMMON | \
CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
CPU_FTR_NO_DPM | CPU_FTR_PPC_LE)
-#define CPU_FTRS_750FX (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
+#define CPU_FTRS_750FX (CPU_FTR_COMMON | \
CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_PPC_LE)
-#define CPU_FTRS_750GX (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
+#define CPU_FTRS_750GX (CPU_FTR_COMMON | \
CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_PPC_LE)
-#define CPU_FTRS_7400_NOTAU (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
+#define CPU_FTRS_7400_NOTAU (CPU_FTR_COMMON | \
CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \
CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
-#define CPU_FTRS_7400 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
+#define CPU_FTRS_7400 (CPU_FTR_COMMON | \
CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \
CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
-#define CPU_FTRS_7450_20 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
+#define CPU_FTRS_7450_20 (CPU_FTR_COMMON | \
CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
-#define CPU_FTRS_7450_21 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
+#define CPU_FTRS_7450_21 (CPU_FTR_COMMON | \
CPU_FTR_USE_TB | \
CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
-#define CPU_FTRS_7450_23 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
+#define CPU_FTRS_7450_23 (CPU_FTR_COMMON | \
CPU_FTR_USE_TB | \
CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
-#define CPU_FTRS_7455_1 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
+#define CPU_FTRS_7455_1 (CPU_FTR_COMMON | \
CPU_FTR_USE_TB | \
CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \
CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_HAS_HIGH_BATS | \
CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
-#define CPU_FTRS_7455_20 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
+#define CPU_FTRS_7455_20 (CPU_FTR_COMMON | \
CPU_FTR_USE_TB | \
CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_PPC_LE)
-#define CPU_FTRS_7455 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
+#define CPU_FTRS_7455 (CPU_FTR_COMMON | \
CPU_FTR_USE_TB | \
CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
-#define CPU_FTRS_7447_10 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
+#define CPU_FTRS_7447_10 (CPU_FTR_COMMON | \
CPU_FTR_USE_TB | \
CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE)
-#define CPU_FTRS_7447 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
+#define CPU_FTRS_7447 (CPU_FTR_COMMON | \
CPU_FTR_USE_TB | \
CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
-#define CPU_FTRS_7447A (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
+#define CPU_FTRS_7447A (CPU_FTR_COMMON | \
CPU_FTR_USE_TB | \
CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
-#define CPU_FTRS_7448 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
+#define CPU_FTRS_7448 (CPU_FTR_COMMON | \
CPU_FTR_USE_TB | \
CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
CPU_FTR_PPC_LE)
-#define CPU_FTRS_82XX (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
+#define CPU_FTRS_82XX (CPU_FTR_COMMON | \
CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB)
-#define CPU_FTRS_G2_LE (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \
+#define CPU_FTRS_G2_LE (CPU_FTR_MAYBE_CAN_DOZE | \
CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS)
-#define CPU_FTRS_E300 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \
+#define CPU_FTRS_E300 (CPU_FTR_MAYBE_CAN_DOZE | \
CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS | \
CPU_FTR_COMMON)
-#define CPU_FTRS_E300C2 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \
+#define CPU_FTRS_E300C2 (CPU_FTR_MAYBE_CAN_DOZE | \
CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS | \
CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE)
-#define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
+#define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON | \
CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE)
-#define CPU_FTRS_8XX (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB)
-#define CPU_FTRS_40X (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
- CPU_FTR_NODSISRALIGN)
-#define CPU_FTRS_44X (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
- CPU_FTR_NODSISRALIGN)
-#define CPU_FTRS_E200 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN)
-#define CPU_FTRS_E500 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
- CPU_FTR_NODSISRALIGN)
-#define CPU_FTRS_E500_2 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
+#define CPU_FTRS_8XX (CPU_FTR_USE_TB)
+#define CPU_FTRS_40X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN)
+#define CPU_FTRS_44X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN)
+#define CPU_FTRS_E200 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN \
+ CPU_FTR_UNIFIED_ID_CACHE)
+#define CPU_FTRS_E500 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN)
+#define CPU_FTRS_E500_2 (CPU_FTR_USE_TB | \
CPU_FTR_BIG_PHYS | CPU_FTR_NODSISRALIGN)
#define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
/* 64-bit CPUs */
-#define CPU_FTRS_POWER3 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
+#define CPU_FTRS_POWER3 (CPU_FTR_USE_TB | \
CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | CPU_FTR_PPC_LE)
-#define CPU_FTRS_RS64 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
+#define CPU_FTRS_RS64 (CPU_FTR_USE_TB | \
CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | \
CPU_FTR_MMCRA | CPU_FTR_CTRL)
-#define CPU_FTRS_POWER4 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
+#define CPU_FTRS_POWER4 (CPU_FTR_USE_TB | \
CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
CPU_FTR_MMCRA)
-#define CPU_FTRS_PPC970 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
+#define CPU_FTRS_PPC970 (CPU_FTR_USE_TB | \
CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA)
-#define CPU_FTRS_POWER5 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
+#define CPU_FTRS_POWER5 (CPU_FTR_USE_TB | \
CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
CPU_FTR_MMCRA | CPU_FTR_SMT | \
CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
CPU_FTR_PURR)
-#define CPU_FTRS_POWER6 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
+#define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | \
CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
CPU_FTR_MMCRA | CPU_FTR_SMT | \
CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
CPU_FTR_DSCR)
-#define CPU_FTRS_CELL (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
+#define CPU_FTRS_CELL (CPU_FTR_USE_TB | \
CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
CPU_FTR_PAUSE_ZERO | CPU_FTR_CI_LARGE_PAGE | CPU_FTR_CELL_TB_BUG)
-#define CPU_FTRS_PA6T (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
+#define CPU_FTRS_PA6T (CPU_FTR_USE_TB | \
CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \
CPU_FTR_ALTIVEC_COMP | CPU_FTR_CI_LARGE_PAGE | \
CPU_FTR_PURR | CPU_FTR_REAL_LE)
-#define CPU_FTRS_COMPATIBLE (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
+#define CPU_FTRS_COMPATIBLE (CPU_FTR_USE_TB | \
CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2)
#ifdef __powerpc64__
Index: working-2.6/arch/powerpc/kernel/misc_32.S
===================================================================
--- working-2.6.orig/arch/powerpc/kernel/misc_32.S 2007-04-19 10:59:55.000000000 +1000
+++ working-2.6/arch/powerpc/kernel/misc_32.S 2007-05-29 14:32:33.000000000 +1000
@@ -392,7 +392,7 @@ BEGIN_FTR_SECTION
mtspr SPRN_L1CSR0,r3
isync
blr
-END_FTR_SECTION_IFCLR(CPU_FTR_SPLIT_ID_CACHE)
+END_FTR_SECTION_IFSET(CPU_FTR_UNIFIED_ID_CACHE)
mfspr r3,SPRN_L1CSR1
ori r3,r3,L1CSR1_ICFI|L1CSR1_ICLFR
mtspr SPRN_L1CSR1,r3
@@ -419,7 +419,7 @@ END_FTR_SECTION_IFCLR(CPU_FTR_SPLIT_ID_C
_GLOBAL(__flush_icache_range)
BEGIN_FTR_SECTION
blr /* for 601, do nothing */
-END_FTR_SECTION_IFCLR(CPU_FTR_SPLIT_ID_CACHE)
+END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
li r5,L1_CACHE_BYTES-1
andc r3,r3,r5
subf r4,r3,r4
@@ -514,8 +514,8 @@ _GLOBAL(invalidate_dcache_range)
*/
_GLOBAL(__flush_dcache_icache)
BEGIN_FTR_SECTION
- blr /* for 601, do nothing */
-END_FTR_SECTION_IFCLR(CPU_FTR_SPLIT_ID_CACHE)
+ blr
+END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
rlwinm r3,r3,0,0,19 /* Get page base address */
li r4,4096/L1_CACHE_BYTES /* Number of lines in a page */
mtctr r4
@@ -543,7 +543,7 @@ END_FTR_SECTION_IFCLR(CPU_FTR_SPLIT_ID_C
_GLOBAL(__flush_dcache_icache_phys)
BEGIN_FTR_SECTION
blr /* for 601, do nothing */
-END_FTR_SECTION_IFCLR(CPU_FTR_SPLIT_ID_CACHE)
+END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
mfmsr r10
rlwinm r0,r10,0,28,26 /* clear DR */
mtmsr r0
Index: working-2.6/arch/powerpc/kernel/setup_32.c
===================================================================
--- working-2.6.orig/arch/powerpc/kernel/setup_32.c 2007-04-26 13:57:24.000000000 +1000
+++ working-2.6/arch/powerpc/kernel/setup_32.c 2007-05-29 14:32:33.000000000 +1000
@@ -262,13 +262,11 @@ void __init setup_arch(char **cmdline_p)
* Systems with OF can look in the properties on the cpu node(s)
* for a possibly more accurate value.
*/
- if (cpu_has_feature(CPU_FTR_SPLIT_ID_CACHE)) {
- dcache_bsize = cur_cpu_spec->dcache_bsize;
- icache_bsize = cur_cpu_spec->icache_bsize;
- ucache_bsize = 0;
- } else
- ucache_bsize = dcache_bsize = icache_bsize
- = cur_cpu_spec->dcache_bsize;
+ dcache_bsize = cur_cpu_spec->dcache_bsize;
+ icache_bsize = cur_cpu_spec->icache_bsize;
+ ucache_bsize = 0;
+ if (cpu_has_feature(CPU_FTR_UNIFIED_ID_CACHE))
+ ucache_bsize = icache_bsize = dcache_bsize;
/* reboot on panic */
panic_timeout = 180;
Index: working-2.6/arch/ppc/kernel/misc.S
===================================================================
--- working-2.6.orig/arch/ppc/kernel/misc.S 2007-01-24 12:01:17.000000000 +1100
+++ working-2.6/arch/ppc/kernel/misc.S 2007-05-29 14:32:33.000000000 +1000
@@ -328,7 +328,7 @@ BEGIN_FTR_SECTION
mtspr SPRN_L1CSR0,r3
isync
blr
-END_FTR_SECTION_IFCLR(CPU_FTR_SPLIT_ID_CACHE)
+END_FTR_SECTION_IFSET(CPU_FTR_UNIFIED_ID_CACHE)
mfspr r3,SPRN_L1CSR1
ori r3,r3,L1CSR1_ICFI|L1CSR1_ICLFR
mtspr SPRN_L1CSR1,r3
@@ -355,7 +355,7 @@ END_FTR_SECTION_IFCLR(CPU_FTR_SPLIT_ID_C
_GLOBAL(__flush_icache_range)
BEGIN_FTR_SECTION
blr /* for 601, do nothing */
-END_FTR_SECTION_IFCLR(CPU_FTR_SPLIT_ID_CACHE)
+END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
li r5,L1_CACHE_BYTES-1
andc r3,r3,r5
subf r4,r3,r4
@@ -472,7 +472,7 @@ _GLOBAL(flush_dcache_all)
_GLOBAL(__flush_dcache_icache)
BEGIN_FTR_SECTION
blr /* for 601, do nothing */
-END_FTR_SECTION_IFCLR(CPU_FTR_SPLIT_ID_CACHE)
+END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
rlwinm r3,r3,0,0,19 /* Get page base address */
li r4,4096/L1_CACHE_BYTES /* Number of lines in a page */
mtctr r4
@@ -500,7 +500,7 @@ END_FTR_SECTION_IFCLR(CPU_FTR_SPLIT_ID_C
_GLOBAL(__flush_dcache_icache_phys)
BEGIN_FTR_SECTION
blr /* for 601, do nothing */
-END_FTR_SECTION_IFCLR(CPU_FTR_SPLIT_ID_CACHE)
+END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
mfmsr r10
rlwinm r0,r10,0,28,26 /* clear DR */
mtmsr r0
Index: working-2.6/arch/ppc/kernel/setup.c
===================================================================
--- working-2.6.orig/arch/ppc/kernel/setup.c 2007-02-14 10:58:22.000000000 +1100
+++ working-2.6/arch/ppc/kernel/setup.c 2007-05-29 14:32:33.000000000 +1000
@@ -526,7 +526,7 @@ void __init setup_arch(char **cmdline_p)
* Systems with OF can look in the properties on the cpu node(s)
* for a possibly more accurate value.
*/
- if (cpu_has_feature(CPU_FTR_SPLIT_ID_CACHE)) {
+ if (! cpu_has_feature(CPU_FTR_UNIFIED_ID_CACHE)) {
dcache_bsize = cur_cpu_spec->dcache_bsize;
icache_bsize = cur_cpu_spec->icache_bsize;
ucache_bsize = 0;
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
^ permalink raw reply
* Re: [PATCH 2/2] powerpc: Refuse to build 64-bit with GCC-4.2.0 and CONFIG_MODULES
From: Sam Ravnborg @ 2007-05-29 4:32 UTC (permalink / raw)
To: Segher Boessenkool; +Cc: linuxppc-dev
In-Reply-To: <91f430e6615a8895ec0d5293c21f618e@kernel.crashing.org>
On Tue, May 29, 2007 at 12:13:50AM +0200, Segher Boessenkool wrote:
> >>...since this won't work (compiler bug, see
> >><http://gcc.gnu.org/PR31490>).
> >
> >Applied both and documented cc-fullversion too.
>
> Thanks! For reference, where should I have documented this?
Documentation/kbuild/makefiles.txt
Sam
^ permalink raw reply
* [PATCH] Powerpc compiler error fix for 2.6.21-rt8
From: Pradyumna Sampath @ 2007-05-29 4:24 UTC (permalink / raw)
To: linuxppc-embedded, linux-rt-users
[-- Attachment #1: Type: text/plain, Size: 132 bytes --]
Hi everyone,
Attached is a small patch to fix compile time errors which is broken
in 2.6.21-rt8 for powerpc.
thanks
regards
prady
[-- Attachment #2: 2_6_21_rt8_powerpc_rt_compile_fix.diff --]
[-- Type: text/x-patch, Size: 664 bytes --]
diff -ur latest/linux-2.6.21/arch/powerpc/kernel/time.c linux-2.6.21/arch/powerpc/kernel/time.c
--- latest/linux-2.6.21/arch/powerpc/kernel/time.c 2007-05-29 09:58:12.000000000 +0530
+++ linux-2.6.21/arch/powerpc/kernel/time.c 2007-05-29 08:58:56.000000000 +0530
@@ -95,6 +95,8 @@
#define SCALE_XSEC(xsec, max) mulhwu((xsec) << 12, max)
#endif
+unsigned long cpu_khz; /* Detected as we calibrate the TSC */
+EXPORT_SYMBOL(cpu_khz);
unsigned long tb_ticks_per_jiffy;
unsigned long tb_ticks_per_usec = 100; /* sane default */
EXPORT_SYMBOL(tb_ticks_per_usec);
Only in linux-2.6.21/arch/powerpc/kernel: vmlinux.lds
Only in linux-2.6.21/scripts/kconfig: mconf
^ permalink raw reply
* Don't use HOSTCFLAGS in BOOTCFLAGS
From: David Gibson @ 2007-05-29 3:29 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev
In the bootwrapper code for powerpc, we include HOSTCFLAGS into the
BOOTCFLAGS used for buildinf the zImage wrapper code. Since the
wrapper code is not host code, this makes no sense. This patch
removes the use of HOSTCFLAGS here, instead including directly into
BOOTCFLAGS those flags from the normal kernel CFLAGS which also make
sense in the bootwrapper code.
In particular, this makes the bootwrapper use -msoft-float, preventing
the compiler from generating floating point instructions. Previously,
under some circumstances the compiler could generate floating point
instructions in the bootwrapper which would cause exceptions on
embedded CPUS which don't have floating point support.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Index: working-2.6/arch/powerpc/boot/Makefile
===================================================================
--- working-2.6.orig/arch/powerpc/boot/Makefile 2007-05-28 16:29:34.000000000 +1000
+++ working-2.6/arch/powerpc/boot/Makefile 2007-05-28 16:29:56.000000000 +1000
@@ -11,7 +11,7 @@
# bootloader and increase compatibility with OpenFirmware.
#
# To this end we need to define BOOTCC, etc, as the tools
-# needed to build the 32 bit image. These are normally HOSTCC,
+# needed to build the 32 bit image.
# but may be a third compiler if, for example, you are cross
# compiling from an intel box. Once the 64bit ppc gcc is
# stable it will probably simply be a compiler switch to
@@ -22,9 +22,11 @@
all: $(obj)/zImage
-HOSTCC := gcc
-BOOTCFLAGS := $(HOSTCFLAGS) -fno-builtin -fno-unit-at-a-time -nostdinc -isystem \
- $(shell $(CROSS32CC) -print-file-name=include) -fPIC
+BOOTCFLAGS := -Wall -Wundef -Wstrict-prototypes -Wno-trigraphs \
+ -fno-strict-aliasing -O2 -msoft-float -pipe \
+ -fomit-frame-pointer -fno-builtin -fno-unit-at-a-time \
+ -fPIC -nostdinc \
+ -isystem $(shell $(CROSS32CC) -print-file-name=include)
BOOTAFLAGS := -D__ASSEMBLY__ $(BOOTCFLAGS) -traditional -nostdinc
ifeq ($(call cc-option-yn, -fstack-protector),y)
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
^ permalink raw reply
* RE: 36bit addressing - adding more memory
From: Zhang Wei-r63237 @ 2007-05-29 2:39 UTC (permalink / raw)
To: Siva Prasad, linuxppc-dev, linuxppc-embedded
In-Reply-To: <D83235F0F3C86D4D889D8B9A0DA8C6D7769272@corpexc01.corp.networkrobots.com>
Hi, Siva,
Please use plain text to send email.
36bit addressing is supported by 8641D, but not in kernel now.
Best Regards,
Wei.
^ permalink raw reply
* [PATCH v2]: Fix e500 v2 core reboot bug
From: Zang Roy-r61911 @ 2007-05-29 2:36 UTC (permalink / raw)
To: Kumar Gala, Paul Mackerras; +Cc: linuxppc-dev list
Fix the e500 v2 core reset bug.
For e500 v2 core, a new reset control register is added to
reset the core.
On 85xx CDS board with e500 v2 core, normal reboot code will
induce DDR block in u-boot. This patch fixes this bug. It is
also tested on legacy e500 v1 core.
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
---
arch/powerpc/platforms/85xx/misc.c | 18 ++++++++++++++++++
1 files changed, 18 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/platforms/85xx/misc.c b/arch/powerpc/platforms/85xx/misc.c
index 3e62fcb..886a13f 100644
--- a/arch/powerpc/platforms/85xx/misc.c
+++ b/arch/powerpc/platforms/85xx/misc.c
@@ -13,11 +13,29 @@
#include <linux/irq.h>
#include <linux/module.h>
#include <asm/irq.h>
+#include <asm/io.h>
+#include <sysdev/fsl_soc.h>
+
+static __be32 __iomem *rstcr;
extern void abort(void);
+static int __init mpc85xx_rstcr(void)
+{
+ /* map reset control register */
+ rstcr = ioremap(get_immrbase() + 0xE00B0, 0xff);
+ return 0;
+}
+
+arch_initcall(mpc85xx_rstcr);
+
void mpc85xx_restart(char *cmd)
{
local_irq_disable();
+ if (rstcr)
+ /* set reset control register */
+ out_be32(rstcr, 0x2); /* HRESET_REQ */
+ else
+ printk (KERN_EMERG "Error: reset control register not mapped, spinning!\n");
abort();
}
--
1.5.1
^ permalink raw reply related
* Re: Xilinx git tree at source.mvista.com
From: John Williams @ 2007-05-28 23:30 UTC (permalink / raw)
To: Wolfgang Reissnegger
Cc: linuxppc-dev, Andrei Konovalov, David H. Lynch Jr.,
linuxppc-embedded
In-Reply-To: <20070525042616.35988808054@mail150-dub.bigfish.com>
Hi Wolfgang,
Wolfgang Reissnegger wrote:
> David H. Lynch Jr. wrote:
>
>>For me the most significant issue is the bazillion layers of nested
>>macro's and includes.
>
>
> I don't see the macros as an issue, just look at the implementation of,
> for example, spin_lock_irq() and Xilinx's macros seem like child's play :-)
> As for includes, yes, there are a few too many header files. But, as
> time progresses and the need arises they can be merged into fewer files.
It seems the kernel.org decision has been made re: the style issue.
None of the *_i.[ch], *_g.[ch] + adapter.c drivers will make it to
mainline.
I understand why Xilinx did it this way, but to be honest never agreed
with it myself either. Style issues aside, three levels of function
calls in an interrupt handler might be portable, but it still isn't a
good thing!
The effort to refactor these drivers is not huge, but it is an effort.
If Xilinx is committed to good quality Linux support for their silicon,
it will require tangible investment in the form of labour or resources.
I know you understand this, but Xilinx as an company still needs a good
hard shove in this direction.
Alternatively, drivers will trickle into kernel.org as the community
gets around to it, witness the uartlite and system ace drivers.
Same old story, if you want it "some day", then it will be free, if you
want it now, you've got to pay!
Cheers,
John
^ permalink raw reply
* Re: [PATCH] powerpc: automatically select QE options
From: Timur Tabi @ 2007-05-29 0:20 UTC (permalink / raw)
To: Sergei Shtylyov; +Cc: linuxppc-dev
In-Reply-To: <465B14B2.2020804@ru.mvista.com>
Sergei Shtylyov wrote:
> Grr... this causes menuconfig to complain on non-PPC archs:
>
> drivers/net/Kconfig:2278:warning: 'select' used by config symbol
> 'UCC_GETH' refer to undefined symbol 'UCC_FAST'
I submitted a fix for this a LONG time ago. It was applied to the -mm tree and to Kumar's tree, so I don't know why you don't have it.
^ permalink raw reply
* Re: [PATCH 2/2] powerpc: Refuse to build 64-bit with GCC-4.2.0 and CONFIG_MODULES
From: Segher Boessenkool @ 2007-05-28 22:13 UTC (permalink / raw)
To: Sam Ravnborg; +Cc: linuxppc-dev
In-Reply-To: <20070528202822.GA31605@uranus.ravnborg.org>
>> ...since this won't work (compiler bug, see
>> <http://gcc.gnu.org/PR31490>).
>
> Applied both and documented cc-fullversion too.
Thanks! For reference, where should I have documented this?
Segher
^ permalink raw reply
* Re: [Patch ] Kexec/Kdump support - POWER6
From: Benjamin Herrenschmidt @ 2007-05-28 21:31 UTC (permalink / raw)
To: sachinp; +Cc: linuxppc-dev, Paul Mackerras, kexec, Milton Miller II
In-Reply-To: <465ABFC9.9020502@in.ibm.com>
On Mon, 2007-05-28 at 17:10 +0530, Sachin P. Sant wrote:
>
> +#define HPTE_V_1TB_SEG ASM_CONST(0x4000000000000000)
> +#define HPTE_V_VRMA_MASK ASM_CONST(0x4001ffffff)
Move those to mmu-hash64.h along with the other ones. Also, keep the
mask aligned to the top bits
> static void pSeries_lpar_hptab_clear(void)
> {
> unsigned long size_bytes = 1UL << ppc64_pft_size;
> unsigned long hpte_count = size_bytes >> 4;
> - unsigned long dummy1, dummy2;
> + unsigned long dummy1, dummy2, dword0;
> + long lpar_rc;
> int i;
>
> /* TODO: Use bulk call */
> - for (i = 0; i < hpte_count; i++)
> - plpar_pte_remove_raw(0, i, 0, &dummy1, &dummy2);
> + for (i = 0; i < hpte_count; i++) {
> + /* dont remove HPTEs with VRMA mappings */
> + lpar_rc = plpar_pte_remove_raw(H_ANDCOND, i, HPTE_V_1TB_SEG,
> + &dummy1, &dummy2);
> + if (lpar_rc == H_NOT_FOUND) {
> + lpar_rc = plpar_pte_read_raw(0, i, &dword0, &dummy1);
> + if (!lpar_rc && (((dword0 >> 24) & HPTE_V_VRMA_MASK)
> + != HPTE_V_VRMA_MASK))
No need to shift >> 24, just have the mask left justified in the first
place. No need to have a "magic" shift value in there.
> + /* Can be hpte for 1TB Seg. So remove it */
> + plpar_pte_remove_raw(0, i, 0, &dummy1, &dummy2);
> + }
> + }
> }
Appart from that, looks good. Does it actually work ? :-)
Cheers,
Ben.
^ permalink raw reply
* Re: [PATCH 2/2] powerpc: Refuse to build 64-bit with GCC-4.2.0 and CONFIG_MODULES
From: Sam Ravnborg @ 2007-05-28 20:28 UTC (permalink / raw)
To: Segher Boessenkool; +Cc: linuxppc-dev
In-Reply-To: <bd3cddd2f3192e3aba4d7c886e38d8d0037c3510.1179593209.git.segher@kernel.crashing.org>
On Sat, May 19, 2007 at 06:49:08PM +0200, Segher Boessenkool wrote:
> ...since this won't work (compiler bug, see <http://gcc.gnu.org/PR31490>).
Applied both and documented cc-fullversion too.
Sam
^ permalink raw reply
* zImage.miboot and vmlinux.lds
From: Christian Kujau @ 2007-05-28 19:32 UTC (permalink / raw)
To: linuxppc-dev
[-- Attachment #1: Type: TEXT/PLAIN, Size: 331 bytes --]
Hi,
when doing a "make mrproper" or even "make distclean" on a current
2.6-git tree, I see 2 files being left over:
arch/powerpc/boot/zImage.miboot
arch/powerpc/kernel/vmlinux.lds
The attached 1-liner "fixes" this but I wonder why they've been kept at
all.
thanks,
Christian
--
BOFH excuse #23:
improperly oriented keyboard
[-- Attachment #2: Type: TEXT/x-diff, Size: 354 bytes --]
--- linux-2.6-dev/arch/powerpc/Makefile.orig 2007-05-28 21:24:39.000000000 +0200
+++ linux-2.6-dev/arch/powerpc/Makefile 2007-05-28 21:23:25.000000000 +0200
@@ -175,6 +175,7 @@ archclean:
archmrproper:
$(Q)rm -rf arch/$(ARCH)/include
+ $(Q)rm -f arch/$(ARCH)/boot/zImage.miboot arch/$(ARCH)/kernel/vmlinux.lds
archprepare: checkbin
^ permalink raw reply
* Re: [PATCH] mpc52xx: Correct calculation of FEC RX errors.
From: Sylvain Munaut @ 2007-05-28 19:04 UTC (permalink / raw)
To: Grzegorz Bernacki; +Cc: linuxppc-embedded
In-Reply-To: <46560B34.2070800@semihalf.com>
Nice catch,
I knew something was wrong ( 4 billion errors ;) but I never bothered to
look
it up.
Sylvain
Grzegorz Bernacki wrote:
> 'ifconfig eth0' command for mpc5200B-based cards shows error for RX.
> However none of RX MIB counters is set to value greater than zero.
> Number of errors is equal to number of multicast packet. In linux 2.4
> calculation of RX errors is slightly different and takes into account
> number of multicast packet. This change is a port of calculation method
> of RX errors for FEC controller from linux 2.4 to 2.6.
>
> Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
> ---
>
> drivers/net/fec_mpc52xx/fec.c | 4 +++-
> 1 files changed, 3 insertions(+), 1 deletions(-)
>
> diff --git a/drivers/net/fec_mpc52xx/fec.c b/drivers/net/fec_mpc52xx/fec.c
> index f0ce87e..d2087f6 100644
> --- a/drivers/net/fec_mpc52xx/fec.c
> +++ b/drivers/net/fec_mpc52xx/fec.c
> @@ -395,7 +395,9 @@ static struct net_device_stats *fec_get_stats(struct
> net_device *dev)
>
> stats->rx_bytes = in_be32(&fec->rmon_r_octets);
> stats->rx_packets = in_be32(&fec->rmon_r_packets);
> - stats->rx_errors = stats->rx_packets -
> in_be32(&fec->ieee_r_frame_ok);
> + stats->rx_errors = stats->rx_packets - (
> + in_be32(&fec->ieee_r_frame_ok) +
> + in_be32(&fec->rmon_r_mc_pkt));
> stats->tx_bytes = in_be32(&fec->rmon_t_octets);
> stats->tx_packets = in_be32(&fec->rmon_t_packets);
> stats->tx_errors = stats->tx_packets - (
>
> _______________________________________________
> Linuxppc-embedded mailing list
> Linuxppc-embedded@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-embedded
>
>
^ permalink raw reply
* Re: [PATCH] powerpc: automatically select QE options
From: Sergei Shtylyov @ 2007-05-28 17:43 UTC (permalink / raw)
To: Timur Tabi; +Cc: linuxppc-dev
In-Reply-To: <1173732027723-git-send-email-timur@freescale.com>
Hello.
Timur Tabi wrote:
> Change the Kconfig files so that the Freescale QE options are automatically
> selected if a QE device is selected. Previously, you'd need to manually
> select UCC_FAST if you want any "fast" UCC devices, such as Gigabit Ethernet.
> Now, the QE Gigabit Ethernet option is always available if the device has a
> QE, and UCC_FAST is automatically enabled. A side-effect is that the
> "QE Options" menu no longer exists.
> diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
> index d9400ef..b92a4e6 100644
> --- a/drivers/net/Kconfig
> +++ b/drivers/net/Kconfig
> @@ -2272,11 +2272,12 @@ config GFAR_NAPI
> depends on GIANFAR
>
> config UCC_GETH
> - tristate "Freescale QE UCC GETH"
> - depends on QUICC_ENGINE && UCC_FAST
> + tristate "Freescale QE Gigabit Ethernet"
> + depends on QUICC_ENGINE
> + select UCC_FAST
Grr... this causes menuconfig to complain on non-PPC archs:
drivers/net/Kconfig:2278:warning: 'select' used by config symbol 'UCC_GETH'
refer to undefined symbol 'UCC_FAST'
WBR, Sergei
^ permalink raw reply
* Re: Badness at include/linux/slub_def.h
From: Christian Kujau @ 2007-05-28 17:29 UTC (permalink / raw)
To: Michel Dänzer; +Cc: linuxppc-dev, linux-kernel, dri-devel
In-Reply-To: <1180083934.19648.442.camel@thor.sulgenrain.local>
[-- Attachment #1: Type: TEXT/PLAIN, Size: 491 bytes --]
Michel Dänzer wrote:
> Does the patch below against the drm tree fix it? Only build tested.
yes, now glxinfo/glxgears returns without this badness, DRI is still
working fine. I've attached some details.
Thank you!
Christian.
> ---
>>From f0e6bdc165cb484b8992b14172a7280f301bf513 Mon Sep 17 00:00:00 2001
> From: =?utf-8?q?Michel_D=C3=A4nzer?= <michel@tungstengraphics.com>
> Date: Fri, 25 May 2007 11:02:05 +0200
> Subject: Make sure the drawable code doesn't call malloc(0).
[-- Attachment #2: Type: APPLICATION/X-GZIP, Size: 9111 bytes --]
[-- Attachment #3: Type: TEXT/PLAIN, Size: 20693 bytes --]
[ 0.000000] Using PowerMac machine description
[ 0.000000] Total memory = 768MB; using 2048kB for hash table (at cfe00000)
[ 0.000000] Linux version 2.6.22-rc2-git7 (dummy@foobar-g4) (gcc version 4.1.2 (Ubuntu 4.1.2-0ubuntu4)) #1 PREEMPT Mon May 28 14:09:13 CEST 2007
[ 0.000000] Found UniNorth memory controller & host bridge @ 0xf8000000 revision: 0xd2
[ 0.000000] Mapped at 0xfdfc0000
[ 0.000000] Found a Intrepid mac-io controller, rev: 0, mapped at 0xfdf40000
[ 0.000000] Processor NAP mode on idle enabled.
[ 0.000000] PowerMac motherboard: iBook G4
[ 0.000000] via-pmu: Server Mode is disabled
[ 0.000000] PMU driver v2 initialized for Core99, firmware: 0c
[ 0.000000] Entering add_active_range(0, 0, 196608) 0 entries of 256 used
[ 0.000000] Found UniNorth PCI host bridge at 0x00000000f0000000. Firmware bus number: 0->0
[ 0.000000] Found UniNorth PCI host bridge at 0x00000000f2000000. Firmware bus number: 0->0
[ 0.000000] Found UniNorth PCI host bridge at 0x00000000f4000000. Firmware bus number: 0->0
[ 0.000000] nvram: Checking bank 0...
[ 0.000000] nvram: gen0=330, gen1=329
[ 0.000000] nvram: Active bank is: 0
[ 0.000000] nvram: OF partition at 0x410
[ 0.000000] nvram: XP partition at 0x1020
[ 0.000000] nvram: NR partition at 0x1120
[ 0.000000] Top of RAM: 0x30000000, Total RAM: 0x30000000
[ 0.000000] Memory hole size: 0MB
[ 0.000000] Zone PFN ranges:
[ 0.000000] DMA 0 -> 196608
[ 0.000000] Normal 196608 -> 196608
[ 0.000000] early_node_map[1] active PFN ranges
[ 0.000000] 0: 0 -> 196608
[ 0.000000] On node 0 totalpages: 196608
[ 0.000000] DMA zone: 1536 pages used for memmap
[ 0.000000] DMA zone: 0 pages reserved
[ 0.000000] DMA zone: 195072 pages, LIFO batch:31
[ 0.000000] Normal zone: 0 pages used for memmap
[ 0.000000] Built 1 zonelists. Total pages: 195072
[ 0.000000] Kernel command line: root=/dev/hda6 ro panic=10 netconsole=@192.168.10.29/eth0,6666@192.168.10.10/00:11:09:EA:13:63
[ 0.000000] netconsole: local port 6665
[ 0.000000] netconsole: local IP 192.168.10.29
[ 0.000000] netconsole: interface eth0
[ 0.000000] netconsole: remote port 6666
[ 0.000000] netconsole: remote IP 192.168.10.10
[ 0.000000] netconsole: remote ethernet address 00:11:09:ea:13:63
[ 0.000000] mpic: Setting up MPIC " MPIC 1 " version 1.2 at 80040000, max 4 CPUs
[ 0.000000] mpic: ISU size: 64, shift: 6, mask: 3f
[ 0.000000] mpic: Initializing for 64 sources
[ 0.000000] PID hash table entries: 4096 (order: 12, 16384 bytes)
[ 0.000000] GMT Delta read from XPRAM: 0 minutes, DST: off
[ 0.000000] time_init: decrementer frequency = 18.432000 MHz
[ 0.000000] time_init: processor frequency = 1199.999997 MHz
[ 20.112686] Console: colour dummy device 80x25
[ 20.113127] console handover: boot [udbg0] -> real [tty0]
[ 20.113613] ------------------------
[ 20.113624] | Locking API testsuite:
[ 20.113632] ----------------------------------------------------------------------------
[ 20.113645] | spin |wlock |rlock |mutex | wsem | rsem |
[ 20.113658] --------------------------------------------------------------------------
[ 20.113676] A-A deadlock:failed|failed| ok |failed|failed|failed|
[ 20.113723] A-B-B-A deadlock:failed|failed| ok |failed|failed|failed|
[ 20.113767] A-B-B-C-C-A deadlock:failed|failed| ok |failed|failed|failed|
[ 20.113809] A-B-C-A-B-C deadlock:failed|failed| ok |failed|failed|failed|
[ 20.113853] A-B-B-C-C-D-D-A deadlock:failed|failed| ok |failed|failed|failed|
[ 20.113899] A-B-C-D-B-D-D-A deadlock:failed|failed| ok |failed|failed|failed|
[ 20.113945] A-B-C-D-B-C-D-A deadlock:failed|failed| ok |failed|failed|failed|
[ 20.113991] double unlock: ok | ok |failed| ok |failed|failed|
[ 20.114030] initialize held:failed|failed|failed|failed|failed|failed|
[ 20.114077] bad unlock order: ok | ok | ok | ok | ok | ok |
[ 20.114124] --------------------------------------------------------------------------
[ 20.114147] recursive read-lock: | ok | |failed|
[ 20.114181] recursive read-lock #2: | ok | |failed|
[ 20.114215] mixed read-write-lock: |failed| |failed|
[ 20.114250] mixed write-read-lock: |failed| |failed|
[ 20.114284] --------------------------------------------------------------------------
[ 20.114307] hard-irqs-on + irq-safe-A/12:failed|failed| ok |
[ 20.114336] soft-irqs-on + irq-safe-A/12:failed|failed| ok |
[ 20.114366] hard-irqs-on + irq-safe-A/21:failed|failed| ok |
[ 20.114395] soft-irqs-on + irq-safe-A/21:failed|failed| ok |
[ 20.114429] sirq-safe-A => hirqs-on/12:failed|failed| ok |
[ 20.114459] sirq-safe-A => hirqs-on/21:failed|failed| ok |
[ 20.114487] hard-safe-A + irqs-on/12:failed|failed| ok |
[ 20.114517] soft-safe-A + irqs-on/12:failed|failed| ok |
[ 20.114547] hard-safe-A + irqs-on/21:failed|failed| ok |
[ 20.114576] soft-safe-A + irqs-on/21:failed|failed| ok |
[ 20.114604] hard-safe-A + unsafe-B #1/123:failed|failed| ok |
[ 20.114634] soft-safe-A + unsafe-B #1/123:failed|failed| ok |
[ 20.114665] hard-safe-A + unsafe-B #1/132:failed|failed| ok |
[ 20.114695] soft-safe-A + unsafe-B #1/132:failed|failed| ok |
[ 20.114725] hard-safe-A + unsafe-B #1/213:failed|failed| ok |
[ 20.114755] soft-safe-A + unsafe-B #1/213:failed|failed| ok |
[ 20.114785] hard-safe-A + unsafe-B #1/231:failed|failed| ok |
[ 20.114816] soft-safe-A + unsafe-B #1/231:failed|failed| ok |
[ 20.114846] hard-safe-A + unsafe-B #1/312:failed|failed| ok |
[ 20.114876] soft-safe-A + unsafe-B #1/312:failed|failed| ok |
[ 20.114906] hard-safe-A + unsafe-B #1/321:failed|failed| ok |
[ 20.114936] soft-safe-A + unsafe-B #1/321:failed|failed| ok |
[ 20.114965] hard-safe-A + unsafe-B #2/123:failed|failed| ok |
[ 20.114996] soft-safe-A + unsafe-B #2/123:failed|failed| ok |
[ 20.115026] hard-safe-A + unsafe-B #2/132:failed|failed| ok |
[ 20.115057] soft-safe-A + unsafe-B #2/132:failed|failed| ok |
[ 20.115087] hard-safe-A + unsafe-B #2/213:failed|failed| ok |
[ 20.115117] soft-safe-A + unsafe-B #2/213:failed|failed| ok |
[ 20.115147] hard-safe-A + unsafe-B #2/231:failed|failed| ok |
[ 20.115178] soft-safe-A + unsafe-B #2/231:failed|failed| ok |
[ 20.115208] hard-safe-A + unsafe-B #2/312:failed|failed| ok |
[ 20.115238] soft-safe-A + unsafe-B #2/312:failed|failed| ok |
[ 20.115268] hard-safe-A + unsafe-B #2/321:failed|failed| ok |
[ 20.115298] soft-safe-A + unsafe-B #2/321:failed|failed| ok |
[ 20.115328] hard-irq lock-inversion/123:failed|failed| ok |
[ 20.115359] soft-irq lock-inversion/123:failed|failed| ok |
[ 20.115389] hard-irq lock-inversion/132:failed|failed| ok |
[ 20.115424] soft-irq lock-inversion/132:failed|failed| ok |
[ 20.115454] hard-irq lock-inversion/213:failed|failed| ok |
[ 20.115485] soft-irq lock-inversion/213:failed|failed| ok |
[ 20.115515] hard-irq lock-inversion/231:failed|failed| ok |
[ 20.115545] soft-irq lock-inversion/231:failed|failed| ok |
[ 20.115575] hard-irq lock-inversion/312:failed|failed| ok |
[ 20.115605] soft-irq lock-inversion/312:failed|failed| ok |
[ 20.115635] hard-irq lock-inversion/321:failed|failed| ok |
[ 20.115665] soft-irq lock-inversion/321:failed|failed| ok |
[ 20.115695] hard-irq read-recursion/123: ok |
[ 20.115716] soft-irq read-recursion/123: ok |
[ 20.115736] hard-irq read-recursion/132: ok |
[ 20.115756] soft-irq read-recursion/132: ok |
[ 20.115776] hard-irq read-recursion/213: ok |
[ 20.115796] soft-irq read-recursion/213: ok |
[ 20.115817] hard-irq read-recursion/231: ok |
[ 20.115837] soft-irq read-recursion/231: ok |
[ 20.115857] hard-irq read-recursion/312: ok |
[ 20.115877] soft-irq read-recursion/312: ok |
[ 20.115897] hard-irq read-recursion/321: ok |
[ 20.115917] soft-irq read-recursion/321: ok |
[ 20.115937] --------------------------------------------------------
[ 20.115954] 142 out of 218 testcases failed, as expected. |
[ 20.115969] ----------------------------------------------------
[ 20.117123] Dentry cache hash table entries: 131072 (order: 7, 524288 bytes)
[ 20.118716] Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
[ 20.168329] Memory: 772096k/786432k available (4020k kernel code, 13828k reserved, 164k data, 213k bss, 168k init)
[ 20.168473] SLUB: Genslabs=23, HWalign=32, Order=0-1, MinObjects=4, Processors=1, Nodes=1
[ 20.168499] Calibrating delay loop... 36.73 BogoMIPS (lpj=18368)
[ 20.184482] Mount-cache hash table entries: 512
[ 20.184976] device-tree: Duplicate name in /cpus/PowerPC,G4@0, renamed to "l2-cache#1"
[ 20.188849] NET: Registered protocol family 16
[ 20.189870] KeyWest i2c @0xf8001003 irq 42 /uni-n@f8000000/i2c@f8001000
[ 20.189898] channel 0 bus <multibus>
[ 20.189912] channel 1 bus <multibus>
[ 20.189975] KeyWest i2c @0x80018000 irq 26 /pci@f2000000/mac-io@17/i2c@18000
[ 20.189994] channel 0 bus <multibus>
[ 20.190028] PMU i2c /pci@f2000000/mac-io@17/via-pmu@16000/pmu-i2c
[ 20.190044] channel 1 bus <multibus>
[ 20.190057] channel 2 bus <multibus>
[ 20.190185] PCI: Probing PCI hardware
[ 20.194055] PCI: Cannot allocate resource region 0 of device 0001:10:18.0
[ 20.194085] PCI: Cannot allocate resource region 0 of device 0001:10:19.0
[ 20.194133] Apple USB OHCI 0001:10:18.0 disabled by firmware
[ 20.194154] Apple USB OHCI 0001:10:19.0 disabled by firmware
[ 20.196972] usbcore: registered new interface driver usbfs
[ 20.197106] usbcore: registered new interface driver hub
[ 20.197249] usbcore: registered new device driver usb
[ 20.198478] NET: Registered protocol family 2
[ 20.207464] IP route cache hash table entries: 32768 (order: 5, 131072 bytes)
[ 20.207875] TCP established hash table entries: 131072 (order: 9, 2621440 bytes)
[ 20.218321] TCP bind hash table entries: 65536 (order: 8, 1310720 bytes)
[ 20.224583] TCP: Hash tables configured (established 131072 bind 65536)
[ 20.224614] TCP reno registered
[ 20.228134] Registering PowerMac CPU frequency driver
[ 20.228169] Low: 599 Mhz, High: 1199 Mhz, Boot: 599 Mhz
[ 20.229596] Initializing RT-Tester: OK
[ 20.238921] io scheduler noop registered
[ 20.238952] io scheduler anticipatory registered
[ 20.238967] io scheduler deadline registered
[ 20.239029] io scheduler cfq registered (default)
[ 20.239430] PCI: Enabling device 0000:00:10.0 (0006 -> 0007)
[ 20.435263] radeonfb (0000:00:10.0): Invalid ROM signature 0 should be 0xaa55
[ 20.435279] radeonfb: Retrieved PLL infos from Open Firmware
[ 20.435301] radeonfb: Reference=27.00 MHz (RefDiv=12) Memory=190.00 Mhz, System=183.00 MHz
[ 20.435325] radeonfb: PLL min 12000 max 35000
[ 20.512140] i2c-adapter i2c-2: unable to read EDID block.
[ 20.631133] i2c-adapter i2c-2: unable to read EDID block.
[ 20.750133] i2c-adapter i2c-2: unable to read EDID block.
[ 20.869134] i2c-adapter i2c-3: unable to read EDID block.
[ 20.988133] i2c-adapter i2c-3: unable to read EDID block.
[ 21.107133] i2c-adapter i2c-3: unable to read EDID block.
[ 21.150390] radeonfb: Monitor 1 type LCD found
[ 21.150407] radeonfb: EDID probed
[ 21.150420] radeonfb: Monitor 2 type no found
[ 21.150445] radeonfb: Using Firmware dividers 0x000600ad from PPLL 0
[ 21.262401] radeonfb: Dynamic Clock Power Management enabled
[ 21.285257] Console: switching to colour frame buffer device 128x48
[ 21.300935] radeonfb: Backlight initialized (radeonbl0)
[ 21.301126] radeonfb (0000:00:10.0): ATI Radeon \c
[ 21.308928] Generic RTC Driver v1.07
[ 21.309202] Macintosh non-volatile memory driver v1.1
[ 21.309560] Linux agpgart interface v0.102 (c) Dave Jones
[ 21.309849] agpgart: Detected Apple UniNorth 2 chipset
[ 21.310209] agpgart: configuring for size idx: 8
[ 21.310549] agpgart: AGP aperture is 32M @ 0x0
[ 21.310830] [drm] Initialized drm 1.1.0 20060810
[ 21.311301] [drm] Initialized radeon 1.27.0 20060524 on minor 0
[ 21.311703] sungem.c:v0.98 8/24/03 David S. Miller (davem@redhat.com)
[ 21.373753] PHY ID: 4061e4, addr: 0
[ 21.374617] eth0: Sun GEM (PCI) 10/100/1000BaseT Ethernet 00:0d:93:c9:95:ca
[ 21.374998] eth0: Found BCM5221 PHY
[ 21.375389] netconsole: device eth0 not up yet, forcing it
[ 25.385401] netconsole: timeout waiting for carrier
[ 26.267462] netconsole: network logging started
[ 26.273219] MacIO PCI driver attached to Intrepid chipset
[ 26.281384] adb: starting probe task...
[ 26.287984] Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2
[ 26.293556] ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx
[ 26.299514] PCI: Enabling device 0002:20:0d.0 (0000 -> 0002)
[ 26.549822] adb devices: [2]: 2 c4 [3]: 3 1 [7]: 7 1f
[ 26.556604] ADB keyboard at 2, handler 1
[ 26.562184] Detected ADB keyboard, type ISO, swapping keys.
[ 26.568016] input: ADB keyboard as /class/input/input0
[ 26.573861] input: ADB Powerbook buttons as /class/input/input1
[ 26.594894] ADB mouse at 3, handler set to 4 (trackpad)
[ 26.660257] input: ADB mouse as /class/input/input2
[ 26.666116] adb: finished probe task...
[ 27.316407] ide0: Found Apple UniNorth ATA-6 controller, bus ID 3, irq 39
[ 27.322355] Probing IDE interface ide0...
[ 27.585597] hda: TOSHIBA MK6025GAS, ATA DISK drive
[ 28.203415] hda: Enabling Ultra DMA 5
[ 28.210233] ide0 at 0xf101a000-0xf101a007,0xf101a160 on irq 39
[ 29.227406] ide1: Found Apple KeyLargo ATA-3 controller, bus ID 0, irq 24
[ 29.233452] Probing IDE interface ide1...
[ 29.598600] hdc: MATSHITACD-RW CW-8123, ATAPI CD/DVD-ROM drive
[ 29.910409] hdc: Enabling MultiWord DMA 2
[ 29.917692] ide1 at 0xf1006000-0xf1006007,0xf1006160 on irq 24
[ 29.924406] hda: max request size: 512KiB
[ 30.167046] hda: 117210240 sectors (60011 MB), CHS=16383/255/63, UDMA(100)
[ 30.173845] hda: cache flushes supported
[ 30.180594] hda: [mac] hda1 hda2 hda3 hda4 hda5 hda6 hda7 hda8
[ 30.496026] hdc: ATAPI 24X DVD-ROM CD-R/RW drive, 2048kB Cache, (U)DMA
[ 30.503081] Uniform CD-ROM driver Revision: 3.20
[ 30.512029] PCI: Enabling device 0001:10:1b.2 (0004 -> 0006)
[ 30.518908] ehci_hcd 0001:10:1b.2: EHCI Host Controller
[ 30.525952] ehci_hcd 0001:10:1b.2: new USB bus registered, assigned bus number 1
[ 30.553421] ehci_hcd 0001:10:1b.2: irq 63, io mem 0x80080000
[ 30.560354] ehci_hcd 0001:10:1b.2: USB 2.0 started, EHCI 1.00, driver 10 Dec 2004
[ 30.567774] usb usb1: configuration #1 chosen from 1 choice
[ 30.574943] hub 1-0:1.0: USB hub found
[ 30.581958] hub 1-0:1.0: 5 ports detected
[ 30.689671] ohci_hcd: 2006 August 04 USB 1.1 'Open' Host Controller (OHCI) Driver
[ 30.689862] Apple USB OHCI 0001:10:18.0 disabled by firmware
[ 30.696967] Apple USB OHCI 0001:10:19.0 disabled by firmware
[ 30.703968] PCI: Enabling device 0001:10:1a.0 (0000 -> 0002)
[ 30.710948] ohci_hcd 0001:10:1a.0: OHCI Host Controller
[ 30.717977] ohci_hcd 0001:10:1a.0: new USB bus registered, assigned bus number 2
[ 30.724961] ohci_hcd 0001:10:1a.0: irq 29, io mem 0x80083000
[ 30.802300] usb usb2: configuration #1 chosen from 1 choice
[ 30.809353] hub 2-0:1.0: USB hub found
[ 30.816286] hub 2-0:1.0: 2 ports detected
[ 30.923635] PCI: Enabling device 0001:10:1b.0 (0000 -> 0002)
[ 30.930562] ohci_hcd 0001:10:1b.0: OHCI Host Controller
[ 30.937557] ohci_hcd 0001:10:1b.0: new USB bus registered, assigned bus number 3
[ 30.944447] ohci_hcd 0001:10:1b.0: irq 63, io mem 0x80082000
[ 31.021265] usb usb3: configuration #1 chosen from 1 choice
[ 31.028141] hub 3-0:1.0: USB hub found
[ 31.034868] hub 3-0:1.0: 3 ports detected
[ 31.142614] PCI: Enabling device 0001:10:1b.1 (0000 -> 0002)
[ 31.149326] usb 2-1: new full speed USB device using ohci_hcd and address 2
[ 31.156147] ohci_hcd 0001:10:1b.1: OHCI Host Controller
[ 31.163055] ohci_hcd 0001:10:1b.1: new USB bus registered, assigned bus number 4
[ 31.169956] ohci_hcd 0001:10:1b.1: irq 63, io mem 0x80081000
[ 31.247264] usb usb4: configuration #1 chosen from 1 choice
[ 31.254114] hub 4-0:1.0: USB hub found
[ 31.260806] hub 4-0:1.0: 2 ports detected
[ 31.337685] usb 2-1: configuration #1 chosen from 1 choice
[ 31.368758] mice: PS/2 mouse device common for all mice
[ 31.522392] input: HID 05ac:1000 as /class/input/input3
[ 31.528999] input: USB HID v1.11 Keyboard [HID 05ac:1000] on usb-0001:10:1a.0-1
[ 31.554294] input: HID 05ac:1000 as /class/input/input4
[ 31.561014] input: USB HID v1.11 Mouse [HID 05ac:1000] on usb-0001:10:1a.0-1
[ 31.732409] usb 4-1: new low speed USB device using ohci_hcd and address 2
[ 31.886756] usb 4-1: configuration #1 chosen from 1 choice
[ 31.902284] input: Genius Optical Mouse as /class/input/input5
[ 31.909055] input: USB HID v1.10 Mouse [Genius Optical Mouse] on usb-0001:10:1b.1-1
[ 31.915854] usbcore: registered new interface driver usbhid
[ 31.922565] drivers/hid/usbhid/hid-core.c: v2.6:USB HID core driver
[ 31.929315] oprofile: using ppc/7450 performance monitoring.
[ 31.929614] TCP cubic registered
[ 31.936299] Initializing XFRM netlink socket
[ 31.943188] NET: Registered protocol family 1
[ 31.950413] NET: Registered protocol family 10
[ 31.957092] lo: Disabled Privacy Extensions
[ 31.963595] ADDRCONF(NETDEV_UP): eth0: link is not ready
[ 31.970230] IPv6 over IPv4 tunneling driver
[ 31.976990] sit0: Disabled Privacy Extensions
[ 31.983581] NET: Registered protocol family 17
[ 31.990107] NET: Registered protocol family 15
[ 32.051519] input: PMU as /class/input/input6
[ 32.058042] Registered led device: pmu-front-led
[ 32.093591] kjournald starting. Commit interval 5 seconds
[ 32.100193] EXT3-fs: mounted filesystem with ordered data mode.
[ 32.106645] VFS: Mounted root (ext3 filesystem) readonly.
[ 32.113219] Freeing unused kernel memory: 168k init
[ 44.882347] ieee80211_crypt: registered algorithm 'NULL'
[ 45.052795] ieee80211: 802.11 data/management/control stack, git-1.1.13
[ 45.068922] ieee80211: Copyright (C) 2004-2005 Intel Corporation <jketreno@linux.intel.com>
[ 45.693150] bcm43xx driver
[ 45.701699] PCI: Enabling device 0001:10:12.0 (0004 -> 0006)
[ 45.779626] PCI: Enabling device 0002:20:0e.0 (0000 -> 0002)
[ 45.844466] fw_ohci: Added fw-ohci device 0002:20:0e.0, OHCI version 1.10
[ 46.352726] fw_core: created new fw device fw0 (0 config rom retries)
[ 51.090071] PowerMac i2c bus pmu 2 registered
[ 51.108033] PowerMac i2c bus pmu 1 registered
[ 51.115942] PowerMac i2c bus mac-io 0 registered
[ 51.123611] PowerMac i2c bus uni-n 1 registered
[ 51.131221] PowerMac i2c bus uni-n 0 registered
[ 51.609602] input: PowerMac Beep as /class/input/input7
[ 51.829518] SCSI subsystem initialized
[ 57.617343] adt746x: version 1 (supported)
[ 57.624907] adt746x: Thermostat bus: 1, address: 0x2e, limit_adjust: 0, fan_speed: -1
[ 57.632764] sensor 0: PWR/MEMORY BOTTOMSIDE
[ 57.640511] sensor 1: CPU BOTTOMSIDE
[ 57.648206] sensor 2: GPU BOTTOMSIDE
[ 57.668252] adt746x: ADT7467 initializing
[ 57.678429] adt746x: Lowering max temperatures from 69, 92, 101 to 70, 50, 70
[ 57.894833] Adding 819192k swap on /dev/hda5. Priority:0 extents:1 across:819192k
[ 58.158841] EXT3 FS on hda6, internal journal
[ 65.255576] process `syslogd' is using obsolete setsockopt SO_BSDCOMPAT
[ 78.443062] agpgart: Putting AGP V2 device at 0000:00:0b.0 into 1x mode
[ 78.443086] agpgart: Putting AGP V2 device at 0000:00:10.0 into 1x mode
[ 78.775069] [drm] Setting GART location based on new memory map
[ 78.775510] [drm] Loading R200 Microcode
[ 78.775597] [drm] writeback test succeeded in 1 usecs
[ 214.096849] hfs: write access to a jounaled filesystem is not supported, use the force option at your own risk, mounting read-only.
[-- Attachment #4: Type: TEXT/PLAIN, Size: 4967 bytes --]
name of display: :0.0
display: :0 screen: 0
direct rendering: Yes
server glx vendor string: SGI
server glx version string: 1.2
server glx extensions:
GLX_ARB_multisample, GLX_EXT_import_context, GLX_EXT_texture_from_pixmap,
GLX_EXT_visual_info, GLX_EXT_visual_rating, GLX_MESA_copy_sub_buffer,
GLX_OML_swap_method, GLX_SGI_make_current_read, GLX_SGI_swap_control,
GLX_SGIS_multisample, GLX_SGIX_fbconfig, GLX_SGIX_visual_select_group
client glx vendor string: SGI
client glx version string: 1.4
client glx extensions:
GLX_ARB_get_proc_address, GLX_ARB_multisample, GLX_EXT_import_context,
GLX_EXT_visual_info, GLX_EXT_visual_rating, GLX_MESA_allocate_memory,
GLX_MESA_copy_sub_buffer, GLX_MESA_swap_control,
GLX_MESA_swap_frame_usage, GLX_OML_swap_method, GLX_OML_sync_control,
GLX_SGI_make_current_read, GLX_SGI_swap_control, GLX_SGI_video_sync,
GLX_SGIS_multisample, GLX_SGIX_fbconfig, GLX_SGIX_pbuffer,
GLX_SGIX_visual_select_group, GLX_EXT_texture_from_pixmap
GLX version: 1.2
GLX extensions:
GLX_ARB_get_proc_address, GLX_ARB_multisample, GLX_EXT_import_context,
GLX_EXT_visual_info, GLX_EXT_visual_rating, GLX_MESA_allocate_memory,
GLX_MESA_copy_sub_buffer, GLX_MESA_swap_control,
GLX_MESA_swap_frame_usage, GLX_OML_swap_method, GLX_SGI_make_current_read,
GLX_SGI_swap_control, GLX_SGI_video_sync, GLX_SGIS_multisample,
GLX_SGIX_fbconfig, GLX_SGIX_visual_select_group
OpenGL vendor string: Tungsten Graphics, Inc.
OpenGL renderer string: Mesa DRI R200 20060602 AGP 8x TCL
OpenGL version string: 1.3 Mesa 6.5.2
OpenGL extensions:
GL_ARB_imaging, GL_ARB_multisample, GL_ARB_multitexture,
GL_ARB_point_parameters, GL_ARB_point_sprite, GL_ARB_texture_border_clamp,
GL_ARB_texture_compression, GL_ARB_texture_cube_map,
GL_ARB_texture_env_add, GL_ARB_texture_env_combine,
GL_ARB_texture_env_crossbar, GL_ARB_texture_env_dot3,
GL_ARB_texture_mirrored_repeat, GL_ARB_texture_rectangle,
GL_ARB_transpose_matrix, GL_ARB_vertex_buffer_object,
GL_ARB_vertex_program, GL_ARB_window_pos, GL_EXT_abgr, GL_EXT_bgra,
GL_EXT_blend_color, GL_EXT_blend_equation_separate,
GL_EXT_blend_func_separate, GL_EXT_blend_minmax, GL_EXT_blend_subtract,
GL_EXT_clip_volume_hint, GL_EXT_compiled_vertex_array, GL_EXT_convolution,
GL_EXT_copy_texture, GL_EXT_draw_range_elements, GL_EXT_fog_coord,
GL_EXT_histogram, GL_EXT_packed_pixels, GL_EXT_point_parameters,
GL_EXT_polygon_offset, GL_EXT_rescale_normal, GL_EXT_secondary_color,
GL_EXT_separate_specular_color, GL_EXT_stencil_wrap, GL_EXT_subtexture,
GL_EXT_texture, GL_EXT_texture3D, GL_EXT_texture_edge_clamp,
GL_EXT_texture_env_add, GL_EXT_texture_env_combine,
GL_EXT_texture_env_dot3, GL_EXT_texture_filter_anisotropic,
GL_EXT_texture_lod_bias, GL_EXT_texture_mirror_clamp,
GL_EXT_texture_object, GL_EXT_texture_rectangle, GL_EXT_vertex_array,
GL_APPLE_packed_pixels, GL_ATI_blend_equation_separate,
GL_ATI_texture_env_combine3, GL_ATI_texture_mirror_once,
GL_ATI_fragment_shader, GL_IBM_rasterpos_clip,
GL_IBM_texture_mirrored_repeat, GL_INGR_blend_func_separate,
GL_MESA_pack_invert, GL_MESA_ycbcr_texture, GL_MESA_window_pos,
GL_NV_blend_square, GL_NV_light_max_exponent, GL_NV_texture_rectangle,
GL_NV_texgen_reflection, GL_OES_read_format, GL_SGI_color_matrix,
GL_SGI_color_table, GL_SGIS_generate_mipmap, GL_SGIS_texture_border_clamp,
GL_SGIS_texture_edge_clamp, GL_SGIS_texture_lod
visual x bf lv rg d st colorbuffer ax dp st accumbuffer ms cav
id dep cl sp sz l ci b ro r g b a bf th cl r g b a ns b eat
----------------------------------------------------------------------
0x23 24 tc 0 32 0 r y . 8 8 8 8 0 24 8 0 0 0 0 0 0 None
0x24 24 tc 0 32 0 r y . 8 8 8 8 0 24 0 0 0 0 0 0 0 None
0x25 24 tc 0 32 0 r y . 8 8 8 8 0 24 8 16 16 16 16 0 0 Slow
0x26 24 tc 0 32 0 r y . 8 8 8 8 0 24 0 16 16 16 16 0 0 Slow
0x27 24 tc 0 32 0 r . . 8 8 8 8 0 24 8 0 0 0 0 0 0 None
0x28 24 tc 0 32 0 r . . 8 8 8 8 0 24 0 0 0 0 0 0 0 None
0x29 24 tc 0 32 0 r . . 8 8 8 8 0 24 8 16 16 16 16 0 0 Slow
0x2a 24 tc 0 32 0 r . . 8 8 8 8 0 24 0 16 16 16 16 0 0 Slow
0x2b 24 dc 0 32 0 r y . 8 8 8 8 0 24 8 0 0 0 0 0 0 None
0x2c 24 dc 0 32 0 r y . 8 8 8 8 0 24 0 0 0 0 0 0 0 None
0x2d 24 dc 0 32 0 r y . 8 8 8 8 0 24 8 16 16 16 16 0 0 Slow
0x2e 24 dc 0 32 0 r y . 8 8 8 8 0 24 0 16 16 16 16 0 0 Slow
0x2f 24 dc 0 32 0 r . . 8 8 8 8 0 24 8 0 0 0 0 0 0 None
0x30 24 dc 0 32 0 r . . 8 8 8 8 0 24 0 0 0 0 0 0 0 None
0x31 24 dc 0 32 0 r . . 8 8 8 8 0 24 8 16 16 16 16 0 0 Slow
0x32 24 dc 0 32 0 r . . 8 8 8 8 0 24 0 16 16 16 16 0 0 Slow
0x4b 32 tc 0 32 0 r . . 8 8 8 8 0 0 0 0 0 0 0 0 0 Ncon
^ permalink raw reply
* Re: Is it possible to call a C function in transfer_to_handler(arch/ppc/kernel/entry.S)?
From: Nicholas Mc Guire @ 2007-05-28 15:25 UTC (permalink / raw)
To: Wang, Baojun; +Cc: ppc-dev, Nicholas McGuire
In-Reply-To: <380406375.32007@eyou.net>
-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1
>
> I'm sorry to ask this topic in this mailling list. I've spend more than 2
> days try to add a C function call in transfer_to_handler(in
> arch/ppc/kernel/entry.S) like this:
>
Why are you sorry ? This is what this list is for - and if nobody can
answer it then its good you sent it - thanks !
<snip...>
> #if 1 /* this is add by me */
could you change this to use onle R3-R13 as these are caller safe - My
suspicion i sthat you are using R0/1/2 and that is not healthy here.
> stwu r1, -16(r1)
> mflr r0
> stw r0, 20(r1)
> bl emulate_iret
> lwz r0, 20(r1)
> mtlr r0
> addi r1, r1, 16
> #endif
> addi r11,r1,STACK_FRAME_OVERHEAD
> stw r11,PT_REGS(r12)
>
out of PPC too long - but will see if I can find something.
hofrat
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iD8DBQFGWvR4nU7rXZKfY2oRArQDAJ99xJOrUlqYpPPuJtoqH27lGeDJ9ACeIj97
1bPlGITc1bVMw1V5YmXnG34=
=hvub
-----END PGP SIGNATURE-----
^ permalink raw reply
* 36bit addressing - adding more memory
From: Siva Prasad @ 2007-05-28 17:08 UTC (permalink / raw)
To: linuxppc-dev, linuxppc-embedded
[-- Attachment #1: Type: text/plain, Size: 335 bytes --]
Hi,
I am using 8641D and was wondering how to use 36bit addressing in Linux
to add more memory to the system.
I hear some Pentium architectures starting from Pentium Pro (PAE mode)
did the exact same thing to support extended memory. How does Linux 2.6
help us take advantage of this?
Thanks
Siva
[-- Attachment #2: Type: text/html, Size: 2423 bytes --]
^ permalink raw reply
* Re: [PATCH] [POWERPC] pasemi idle uses hard_smp_processor_id
From: Olof Johansson @ 2007-05-28 17:06 UTC (permalink / raw)
To: Stephen Rothwell; +Cc: ppc-dev, paulus
In-Reply-To: <20070528102045.5fb60480.sfr@canb.auug.org.au>
On Mon, May 28, 2007 at 10:20:45AM +1000, Stephen Rothwell wrote:
> and so needs to include asm/smp.h so a UP build works.
>
> Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
Thanks Stephen!
Acked-by: Olof Johansson <olof@lixom.net>
-Olof
^ permalink raw reply
* [Patch ] Kexec/Kdump support - POWER6
From: Sachin P. Sant @ 2007-05-28 11:40 UTC (permalink / raw)
To: Paul Mackerras; +Cc: Milton Miller II, kexec, linuxppc-dev
In-Reply-To: <1180132987.19517.9.camel@localhost.localdomain>
[-- Attachment #1: Type: text/plain, Size: 807 bytes --]
Benjamin Herrenschmidt wrote:
> If you're going to use the B (1T segment) bit instead of the bolted bit,
> at least define a proper constant in line with the existing naming of
> the hash table constants in mmu-hash64.h. I would suggest doing the same
> with the VRMA_MASK/VALUE thing and calling it HPTE_V_VRMA_MASK or
> something similar.
>
Well i had used them properly in my previous patches. Don't know why
i changed it in this patch :-(
Here is the updated patch.
>> + }
>> }
>>
> In addition, I would recommend following Michael's advice and using
> using the bulk remove Hcall whenever possible.
>
Yes will send out a separate patch to use bulk remove Hcall.
Thanks
-Sachin
Signed-off-by : Sachin Sant <sachinp@in.ibm.com>
Signed-off-by : Mohan Kumar M <mohan@in.ibm.com>
---
[-- Attachment #2: kexec-kdump-support-on-POWER6 --]
[-- Type: text/plain, Size: 2541 bytes --]
* On Power machines supporting VRMA, Kexec/Kdump does not work.
* Hypervisor stores VRMA mapping used by the OS, in the hpte hash tables.
* Make sure these hpte entries are left untouched.
*
* This patch also adds plpar_pte_read_raw() on the lines of
* plpar_pte_remove_raw().
Signed-off-by : Sachin Sant <sachinp@in.ibm.com>
Signed-off-by : Mohan Kumar M <mohan@in.ibm.com>
---
diff -Naurp a/arch/powerpc/platforms/pseries/lpar.c b/arch/powerpc/platforms/pseries/lpar.c
--- a/arch/powerpc/platforms/pseries/lpar.c 2007-05-19 09:36:17.000000000 +0530
+++ b/arch/powerpc/platforms/pseries/lpar.c 2007-05-28 16:49:46.000000000 +0530
@@ -369,16 +369,30 @@ static long pSeries_lpar_hpte_remove(uns
return -1;
}
+#define HPTE_V_1TB_SEG ASM_CONST(0x4000000000000000)
+#define HPTE_V_VRMA_MASK ASM_CONST(0x4001ffffff)
+
static void pSeries_lpar_hptab_clear(void)
{
unsigned long size_bytes = 1UL << ppc64_pft_size;
unsigned long hpte_count = size_bytes >> 4;
- unsigned long dummy1, dummy2;
+ unsigned long dummy1, dummy2, dword0;
+ long lpar_rc;
int i;
/* TODO: Use bulk call */
- for (i = 0; i < hpte_count; i++)
- plpar_pte_remove_raw(0, i, 0, &dummy1, &dummy2);
+ for (i = 0; i < hpte_count; i++) {
+ /* dont remove HPTEs with VRMA mappings */
+ lpar_rc = plpar_pte_remove_raw(H_ANDCOND, i, HPTE_V_1TB_SEG,
+ &dummy1, &dummy2);
+ if (lpar_rc == H_NOT_FOUND) {
+ lpar_rc = plpar_pte_read_raw(0, i, &dword0, &dummy1);
+ if (!lpar_rc && (((dword0 >> 24) & HPTE_V_VRMA_MASK)
+ != HPTE_V_VRMA_MASK))
+ /* Can be hpte for 1TB Seg. So remove it */
+ plpar_pte_remove_raw(0, i, 0, &dummy1, &dummy2);
+ }
+ }
}
/*
diff -Naurp a/arch/powerpc/platforms/pseries/plpar_wrappers.h b/arch/powerpc/platforms/pseries/plpar_wrappers.h
--- a/arch/powerpc/platforms/pseries/plpar_wrappers.h 2007-05-19 09:36:17.000000000 +0530
+++ b/arch/powerpc/platforms/pseries/plpar_wrappers.h 2007-05-25 12:20:38.000000000 +0530
@@ -108,6 +108,21 @@ static inline long plpar_pte_read(unsign
return rc;
}
+/* plpar_pte_read_raw can be called in real mode. It calls plpar_hcall_raw */
+static inline long plpar_pte_read_raw(unsigned long flags, unsigned long ptex,
+ unsigned long *old_pteh_ret, unsigned long *old_ptel_ret)
+{
+ long rc;
+ unsigned long retbuf[PLPAR_HCALL_BUFSIZE];
+
+ rc = plpar_hcall_raw(H_READ, retbuf, flags, ptex);
+
+ *old_pteh_ret = retbuf[0];
+ *old_ptel_ret = retbuf[1];
+
+ return rc;
+}
+
static inline long plpar_pte_protect(unsigned long flags, unsigned long ptex,
unsigned long avpn)
{
^ permalink raw reply
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