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* [RFC/PATCH 2/6] powerpc: ptrace cleanups
From: Benjamin Herrenschmidt @ 2007-05-30  7:17 UTC (permalink / raw)
  To: linuxppc-dev; +Cc: ulrich.weigand, Paul Mackerras, Anton Blanchard

The powerpc ptrace code has some weirdness, like a ptrace-common.h file that
is actually ppc64 only and some of the 32 bits code ifdef'ed inside ptrace.c.

There are also separate implementations for things like get/set_vrregs for
32 and 64 bits which is totally unnecessary.

This patch cleans that up a bit by having a ptrace-common.h which contains
really common code (and makes a lot more code common), and ptrace-ppc32.h and
ptrace-ppc64.h files that contain the few remaining different bits.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---

 arch/powerpc/kernel/ptrace-common.h |   89 +++++++---------
 arch/powerpc/kernel/ptrace-ppc32.h  |  100 ++++++++++++++++++
 arch/powerpc/kernel/ptrace-ppc64.h  |   51 +++++++++
 arch/powerpc/kernel/ptrace.c        |  198 ------------------------------------
 arch/powerpc/kernel/ptrace32.c      |    1 
 5 files changed, 197 insertions(+), 242 deletions(-)

Index: linux-cell/arch/powerpc/kernel/ptrace-common.h
===================================================================
--- linux-cell.orig/arch/powerpc/kernel/ptrace-common.h	2007-05-29 13:05:55.000000000 +1000
+++ linux-cell/arch/powerpc/kernel/ptrace-common.h	2007-05-29 16:22:00.000000000 +1000
@@ -1,5 +1,6 @@
 /*
  *    Copyright (c) 2002 Stephen Rothwell, IBM Coproration
+ *    Copyright (c) 2007 Benjamin Herrenschmidt, IBM Coproration
  *    Extracted from ptrace.c and ptrace32.c
  *
  * This file is subject to the terms and conditions of the GNU General
@@ -7,15 +8,8 @@
  * this archive for more details.
  */
 
-#ifndef _PPC64_PTRACE_COMMON_H
-#define _PPC64_PTRACE_COMMON_H
-
-#include <asm/system.h>
-
-/*
- * Set of msr bits that gdb can change on behalf of a process.
- */
-#define MSR_DEBUGCHANGE	(MSR_FE0 | MSR_SE | MSR_BE | MSR_FE1)
+#ifndef _POWERPC_PTRACE_COMMON_H
+#define _POWERPC_PTRACE_COMMON_H
 
 /*
  * Get contents of register REGNO in task TASK.
@@ -24,18 +18,18 @@ static inline unsigned long get_reg(stru
 {
 	unsigned long tmp = 0;
 
-	/*
-	 * Put the correct FP bits in, they might be wrong as a result
-	 * of our lazy FP restore.
-	 */
+	if (task->thread.regs == NULL)
+		return -EIO;
+
 	if (regno == PT_MSR) {
 		tmp = ((unsigned long *)task->thread.regs)[PT_MSR];
-		tmp |= task->thread.fpexc_mode;
-	} else if (regno < (sizeof(struct pt_regs) / sizeof(unsigned long))) {
-		tmp = ((unsigned long *)task->thread.regs)[regno];
+		return PT_MUNGE_MSR(tmp, task);
 	}
 
-	return tmp;
+	if (regno < (sizeof(struct pt_regs) / sizeof(unsigned long)))
+		return ((unsigned long *)task->thread.regs)[regno];
+
+	return -EIO;
 }
 
 /*
@@ -44,7 +38,10 @@ static inline unsigned long get_reg(stru
 static inline int put_reg(struct task_struct *task, int regno,
 			  unsigned long data)
 {
-	if (regno < PT_SOFTE) {
+	if (task->thread.regs == NULL)
+		return -EIO;
+
+	if (regno <= PT_MAX_PUT_REG) {
 		if (regno == PT_MSR)
 			data = (data & MSR_DEBUGCHANGE)
 				| (task->thread.regs->msr & ~MSR_DEBUGCHANGE);
@@ -54,21 +51,6 @@ static inline int put_reg(struct task_st
 	return -EIO;
 }
 
-static inline void set_single_step(struct task_struct *task)
-{
-	struct pt_regs *regs = task->thread.regs;
-	if (regs != NULL)
-		regs->msr |= MSR_SE;
-	set_tsk_thread_flag(task, TIF_SINGLESTEP);
-}
-
-static inline void clear_single_step(struct task_struct *task)
-{
-	struct pt_regs *regs = task->thread.regs;
-	if (regs != NULL)
-		regs->msr &= ~MSR_SE;
-	clear_tsk_thread_flag(task, TIF_SINGLESTEP);
-}
 
 #ifdef CONFIG_ALTIVEC
 /*
@@ -137,25 +119,36 @@ static inline int set_vrregs(struct task
 
 	return 0;
 }
-#endif
+#endif /* CONFIG_ALTIVEC */
 
-static inline int ptrace_set_debugreg(struct task_struct *task,
-				      unsigned long addr, unsigned long data)
+static inline void set_single_step(struct task_struct *task)
 {
-	/* We only support one DABR and no IABRS at the moment */
-	if (addr > 0)
-		return -EINVAL;
+	struct pt_regs *regs = task->thread.regs;
 
-	/* The bottom 3 bits are flags */
-	if ((data & ~0x7UL) >= TASK_SIZE)
-		return -EIO;
+	if (regs != NULL) {
+#if defined(CONFIG_40x) || defined(CONFIG_BOOKE)
+		task->thread.dbcr0 = DBCR0_IDM | DBCR0_IC;
+		regs->msr |= MSR_DE;
+#else
+		regs->msr |= MSR_SE;
+#endif
+	}
+	set_tsk_thread_flag(task, TIF_SINGLESTEP);
+}
 
-	/* Ensure translation is on */
-	if (data && !(data & DABR_TRANSLATION))
-		return -EIO;
+static inline void clear_single_step(struct task_struct *task)
+{
+	struct pt_regs *regs = task->thread.regs;
 
-	task->thread.dabr = data;
-	return 0;
+	if (regs != NULL) {
+#if defined(CONFIG_40x) || defined(CONFIG_BOOKE)
+		task->thread.dbcr0 = 0;
+		regs->msr &= ~MSR_DE;
+#else
+		regs->msr &= ~MSR_SE;
+#endif
+	}
+	clear_tsk_thread_flag(task, TIF_SINGLESTEP);
 }
 
-#endif /* _PPC64_PTRACE_COMMON_H */
+#endif /* _POWERPC_PTRACE_COMMON_H */
Index: linux-cell/arch/powerpc/kernel/ptrace-ppc32.h
===================================================================
--- /dev/null	1970-01-01 00:00:00.000000000 +0000
+++ linux-cell/arch/powerpc/kernel/ptrace-ppc32.h	2007-05-29 13:05:58.000000000 +1000
@@ -0,0 +1,100 @@
+/*
+ *    Copyright (c) 2007 Benjamin Herrenschmidt, IBM Coproration
+ *    Extracted from ptrace.c and ptrace32.c
+ *
+ * This file is subject to the terms and conditions of the GNU General
+ * Public License.  See the file README.legal in the main directory of
+ * this archive for more details.
+ */
+
+#ifndef _POWERPC_PTRACE_PPC32_H
+#define _POWERPC_PTRACE_PPC32_H
+
+/*
+ * Set of msr bits that gdb can change on behalf of a process.
+ */
+#if defined(CONFIG_40x) || defined(CONFIG_BOOKE)
+#define MSR_DEBUGCHANGE	0
+#else
+#define MSR_DEBUGCHANGE	(MSR_SE | MSR_BE)
+#endif
+
+/*
+ * Max register writeable via put_reg
+ */
+#define PT_MAX_PUT_REG	PT_MQ
+
+/*
+ * Munging of MSR on return from get_regs
+ *
+ * Nothing to do on ppc32
+ */
+#define PT_MUNGE_MSR(msr, task)	(msr)
+
+
+#ifdef CONFIG_SPE
+
+/*
+ * For get_evrregs/set_evrregs functions 'data' has the following layout:
+ *
+ * struct {
+ *   u32 evr[32];
+ *   u64 acc;
+ *   u32 spefscr;
+ * }
+ */
+
+/*
+ * Get contents of SPE register state in task TASK.
+ */
+static inline int get_evrregs(unsigned long *data, struct task_struct *task)
+{
+	int i;
+
+	if (!access_ok(VERIFY_WRITE, data, 35 * sizeof(unsigned long)))
+		return -EFAULT;
+
+	/* copy SPEFSCR */
+	if (__put_user(task->thread.spefscr, &data[34]))
+		return -EFAULT;
+
+	/* copy SPE registers EVR[0] .. EVR[31] */
+	for (i = 0; i < 32; i++, data++)
+		if (__put_user(task->thread.evr[i], data))
+			return -EFAULT;
+
+	/* copy ACC */
+	if (__put_user64(task->thread.acc, (unsigned long long *)data))
+		return -EFAULT;
+
+	return 0;
+}
+
+/*
+ * Write contents of SPE register state into task TASK.
+ */
+static inline int set_evrregs(struct task_struct *task, unsigned long *data)
+{
+	int i;
+
+	if (!access_ok(VERIFY_READ, data, 35 * sizeof(unsigned long)))
+		return -EFAULT;
+
+	/* copy SPEFSCR */
+	if (__get_user(task->thread.spefscr, &data[34]))
+		return -EFAULT;
+
+	/* copy SPE registers EVR[0] .. EVR[31] */
+	for (i = 0; i < 32; i++, data++)
+		if (__get_user(task->thread.evr[i], data))
+			return -EFAULT;
+	/* copy ACC */
+	if (__get_user64(task->thread.acc, (unsigned long long*)data))
+		return -EFAULT;
+
+	return 0;
+}
+#endif /* CONFIG_SPE */
+
+
+#endif /* _POWERPC_PTRACE_PPC32_H */
Index: linux-cell/arch/powerpc/kernel/ptrace-ppc64.h
===================================================================
--- /dev/null	1970-01-01 00:00:00.000000000 +0000
+++ linux-cell/arch/powerpc/kernel/ptrace-ppc64.h	2007-05-29 13:05:58.000000000 +1000
@@ -0,0 +1,51 @@
+/*
+ *    Copyright (c) 2002 Stephen Rothwell, IBM Coproration
+ *    Extracted from ptrace.c and ptrace32.c
+ *
+ * This file is subject to the terms and conditions of the GNU General
+ * Public License.  See the file README.legal in the main directory of
+ * this archive for more details.
+ */
+
+#ifndef _POWERPC_PTRACE_PPC64_H
+#define _POWERPC_PTRACE_PPC64_H
+
+/*
+ * Set of msr bits that gdb can change on behalf of a process.
+ */
+#define MSR_DEBUGCHANGE	(MSR_FE0 | MSR_SE | MSR_BE | MSR_FE1)
+
+/*
+ * Max register writeable via put_reg
+ */
+#define PT_MAX_PUT_REG	PT_CCR
+
+/*
+ * Munging of MSR on return from get_regs
+ *
+ * Put the correct FP bits in, they might be wrong as a result
+ * of our lazy FP restore.
+ */
+
+#define PT_MUNGE_MSR(msr, task)	({ (msr) | (task)->thread.fpexc_mode; })
+
+static inline int ptrace_set_debugreg(struct task_struct *task,
+				      unsigned long addr, unsigned long data)
+{
+	/* We only support one DABR and no IABRS at the moment */
+	if (addr > 0)
+		return -EINVAL;
+
+	/* The bottom 3 bits are flags */
+	if ((data & ~0x7UL) >= TASK_SIZE)
+		return -EIO;
+
+	/* Ensure translation is on */
+	if (data && !(data & DABR_TRANSLATION))
+		return -EIO;
+
+	task->thread.dabr = data;
+	return 0;
+}
+
+#endif /* _POWERPC_PTRACE_PPC64_H */
Index: linux-cell/arch/powerpc/kernel/ptrace.c
===================================================================
--- linux-cell.orig/arch/powerpc/kernel/ptrace.c	2007-05-29 13:05:55.000000000 +1000
+++ linux-cell/arch/powerpc/kernel/ptrace.c	2007-05-29 16:21:50.000000000 +1000
@@ -36,208 +36,18 @@
 #include <asm/system.h>
 
 #ifdef CONFIG_PPC64
-#include "ptrace-common.h"
-#endif
-
-#ifdef CONFIG_PPC32
-/*
- * Set of msr bits that gdb can change on behalf of a process.
- */
-#if defined(CONFIG_40x) || defined(CONFIG_BOOKE)
-#define MSR_DEBUGCHANGE	0
+#include "ptrace-ppc64.h"
 #else
-#define MSR_DEBUGCHANGE	(MSR_SE | MSR_BE)
+#include "ptrace-ppc32.h"
 #endif
-#endif /* CONFIG_PPC32 */
+
+#include "ptrace-common.h"
 
 /*
  * does not yet catch signals sent when the child dies.
  * in exit.c or in signal.c.
  */
 
-#ifdef CONFIG_PPC32
-/*
- * Get contents of register REGNO in task TASK.
- */
-static inline unsigned long get_reg(struct task_struct *task, int regno)
-{
-	if (regno < sizeof(struct pt_regs) / sizeof(unsigned long)
-	    && task->thread.regs != NULL)
-		return ((unsigned long *)task->thread.regs)[regno];
-	return (0);
-}
-
-/*
- * Write contents of register REGNO in task TASK.
- */
-static inline int put_reg(struct task_struct *task, int regno,
-			  unsigned long data)
-{
-	if (regno <= PT_MQ && task->thread.regs != NULL) {
-		if (regno == PT_MSR)
-			data = (data & MSR_DEBUGCHANGE)
-				| (task->thread.regs->msr & ~MSR_DEBUGCHANGE);
-		((unsigned long *)task->thread.regs)[regno] = data;
-		return 0;
-	}
-	return -EIO;
-}
-
-#ifdef CONFIG_ALTIVEC
-/*
- * Get contents of AltiVec register state in task TASK
- */
-static inline int get_vrregs(unsigned long __user *data, struct task_struct *task)
-{
-	int i, j;
-
-	if (!access_ok(VERIFY_WRITE, data, 133 * sizeof(unsigned long)))
-		return -EFAULT;
-
-	/* copy AltiVec registers VR[0] .. VR[31] */
-	for (i = 0; i < 32; i++)
-		for (j = 0; j < 4; j++, data++)
-			if (__put_user(task->thread.vr[i].u[j], data))
-				return -EFAULT;
-
-	/* copy VSCR */
-	for (i = 0; i < 4; i++, data++)
-		if (__put_user(task->thread.vscr.u[i], data))
-			return -EFAULT;
-
-        /* copy VRSAVE */
-	if (__put_user(task->thread.vrsave, data))
-		return -EFAULT;
-
-	return 0;
-}
-
-/*
- * Write contents of AltiVec register state into task TASK.
- */
-static inline int set_vrregs(struct task_struct *task, unsigned long __user *data)
-{
-	int i, j;
-
-	if (!access_ok(VERIFY_READ, data, 133 * sizeof(unsigned long)))
-		return -EFAULT;
-
-	/* copy AltiVec registers VR[0] .. VR[31] */
-	for (i = 0; i < 32; i++)
-		for (j = 0; j < 4; j++, data++)
-			if (__get_user(task->thread.vr[i].u[j], data))
-				return -EFAULT;
-
-	/* copy VSCR */
-	for (i = 0; i < 4; i++, data++)
-		if (__get_user(task->thread.vscr.u[i], data))
-			return -EFAULT;
-
-	/* copy VRSAVE */
-	if (__get_user(task->thread.vrsave, data))
-		return -EFAULT;
-
-	return 0;
-}
-#endif
-
-#ifdef CONFIG_SPE
-
-/*
- * For get_evrregs/set_evrregs functions 'data' has the following layout:
- *
- * struct {
- *   u32 evr[32];
- *   u64 acc;
- *   u32 spefscr;
- * }
- */
-
-/*
- * Get contents of SPE register state in task TASK.
- */
-static inline int get_evrregs(unsigned long *data, struct task_struct *task)
-{
-	int i;
-
-	if (!access_ok(VERIFY_WRITE, data, 35 * sizeof(unsigned long)))
-		return -EFAULT;
-
-	/* copy SPEFSCR */
-	if (__put_user(task->thread.spefscr, &data[34]))
-		return -EFAULT;
-
-	/* copy SPE registers EVR[0] .. EVR[31] */
-	for (i = 0; i < 32; i++, data++)
-		if (__put_user(task->thread.evr[i], data))
-			return -EFAULT;
-
-	/* copy ACC */
-	if (__put_user64(task->thread.acc, (unsigned long long *)data))
-		return -EFAULT;
-
-	return 0;
-}
-
-/*
- * Write contents of SPE register state into task TASK.
- */
-static inline int set_evrregs(struct task_struct *task, unsigned long *data)
-{
-	int i;
-
-	if (!access_ok(VERIFY_READ, data, 35 * sizeof(unsigned long)))
-		return -EFAULT;
-
-	/* copy SPEFSCR */
-	if (__get_user(task->thread.spefscr, &data[34]))
-		return -EFAULT;
-
-	/* copy SPE registers EVR[0] .. EVR[31] */
-	for (i = 0; i < 32; i++, data++)
-		if (__get_user(task->thread.evr[i], data))
-			return -EFAULT;
-	/* copy ACC */
-	if (__get_user64(task->thread.acc, (unsigned long long*)data))
-		return -EFAULT;
-
-	return 0;
-}
-#endif /* CONFIG_SPE */
-
-static inline void
-set_single_step(struct task_struct *task)
-{
-	struct pt_regs *regs = task->thread.regs;
-
-	if (regs != NULL) {
-#if defined(CONFIG_40x) || defined(CONFIG_BOOKE)
-		task->thread.dbcr0 = DBCR0_IDM | DBCR0_IC;
-		regs->msr |= MSR_DE;
-#else
-		regs->msr |= MSR_SE;
-#endif
-	}
-	set_tsk_thread_flag(task, TIF_SINGLESTEP);
-}
-
-static inline void
-clear_single_step(struct task_struct *task)
-{
-	struct pt_regs *regs = task->thread.regs;
-
-	if (regs != NULL) {
-#if defined(CONFIG_40x) || defined(CONFIG_BOOKE)
-		task->thread.dbcr0 = 0;
-		regs->msr &= ~MSR_DE;
-#else
-		regs->msr &= ~MSR_SE;
-#endif
-	}
-	clear_tsk_thread_flag(task, TIF_SINGLESTEP);
-}
-#endif /* CONFIG_PPC32 */
-
 /*
  * Called by kernel/ptrace.c when detaching..
  *
Index: linux-cell/arch/powerpc/kernel/ptrace32.c
===================================================================
--- linux-cell.orig/arch/powerpc/kernel/ptrace32.c	2007-05-29 13:05:55.000000000 +1000
+++ linux-cell/arch/powerpc/kernel/ptrace32.c	2007-05-29 16:21:50.000000000 +1000
@@ -33,6 +33,7 @@
 #include <asm/pgtable.h>
 #include <asm/system.h>
 
+#include "ptrace-ppc64.h"
 #include "ptrace-common.h"
 
 /*
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^ permalink raw reply

* [RFC/PATCH 1/6] powerpc: Disable broken PPC_PTRACE_GETFPREGS on 32 bits
From: Benjamin Herrenschmidt @ 2007-05-30  7:17 UTC (permalink / raw)
  To: linuxppc-dev; +Cc: ulrich.weigand, Paul Mackerras, Anton Blanchard

The handling of PPC_PTRACE_GETFPREGS is broken on 32 bits kernel,
it will only return half of the registers. Since that call didn't
initially exist for 32 bits kernel (added recently), rather than
fixing it, let's just remove it.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---

 arch/powerpc/kernel/ptrace.c |    2 ++
 1 file changed, 2 insertions(+)

Index: linux-cell/arch/powerpc/kernel/ptrace.c
===================================================================
--- linux-cell.orig/arch/powerpc/kernel/ptrace.c	2007-05-29 11:34:20.000000000 +1000
+++ linux-cell/arch/powerpc/kernel/ptrace.c	2007-05-29 11:34:35.000000000 +1000
@@ -434,6 +434,7 @@ long arch_ptrace(struct task_struct *chi
 		break;
 	}
 
+#ifdef CONFIG_PPC64
 	case PPC_PTRACE_GETFPREGS: { /* Get FPRs 0 - 31. */
 		int i;
 		unsigned long *reg = &((unsigned long *)child->thread.fpr)[0];
@@ -467,6 +468,7 @@ long arch_ptrace(struct task_struct *chi
 		}
 		break;
 	}
+#endif /* CONFIG_PPC64 */
 
 #ifdef CONFIG_ALTIVEC
 	case PTRACE_GETVRREGS:

^ permalink raw reply

* Merge CPU features pertaining to icache coherency
From: David Gibson @ 2007-05-30  6:37 UTC (permalink / raw)
  To: Paul Mackerras, linuxppc-dev

Currently the powerpc kernel has a 64-bit only feature,
COHERENT_ICACHE used for those CPUS which maintain icache/dcache
coherency in hardware (POWER5, essentially).  It also has a feature,
SPLIT_ID_CACHE, which is used on CPUs which have separate i and
d-caches, which is to say everything except 601 and Freescale E200.

In nearly all the places we check the SPLIT_ID_CACHE, what we actually
care about is whether the i and d-caches are coherent (which they will
be, trivially, if they're the same cache).

This patch tries to clarify the situation a little.  The
COHERENT_ICACHE feature becomes availble on 32-bit and is set for all
CPUs where i and d-cache are effectively coherent, whether this is due
to special logic (POWER5) or because they're unified.  We check this,
instead of SPLIT_ID_CACHE nearly everywhere.

The SPLIT_ID_CACHE feature itself is replaced by a UNIFIED_ID_CACHE
feature with reversed sense, set only on 601 and Freescale E200.  In
the two places (one Freescale BookE specific) where we really care
whether it's a unified cache, not whether they're coherent, we check
this feature.  The CPUs with unified cache are so few, we could
consider replacing this feature bit with explicit checks against the
PVR.

This patch will make unifying the 32-bit and 64-bit cache flush code a
little more straightforward.

Signed-off-by: David Gibson <dwg@au1.ibm.com>

 arch/powerpc/kernel/misc_32.S  |   10 ++--
 arch/powerpc/kernel/setup_32.c |   12 ++---
 arch/ppc/kernel/misc.S         |    8 +--
 arch/ppc/kernel/setup.c        |    2 
 include/asm-powerpc/cputable.h |   95 ++++++++++++++++++++---------------------
 5 files changed, 62 insertions(+), 65 deletions(-)
---
Fixed a stupid typo which caused a build failure on Freescale Book-E.

Index: working-2.6/include/asm-powerpc/cputable.h
===================================================================
--- working-2.6.orig/include/asm-powerpc/cputable.h	2007-05-21 12:47:17.000000000 +1000
+++ working-2.6/include/asm-powerpc/cputable.h	2007-05-30 16:35:31.000000000 +1000
@@ -111,7 +111,7 @@ extern void do_feature_fixups(unsigned l
 /* CPU kernel features */
 
 /* Retain the 32b definitions all use bottom half of word */
-#define CPU_FTR_SPLIT_ID_CACHE		ASM_CONST(0x0000000000000001)
+#define CPU_FTR_COHERENT_ICACHE		ASM_CONST(0x0000000000000001)
 #define CPU_FTR_L2CR			ASM_CONST(0x0000000000000002)
 #define CPU_FTR_SPEC7450		ASM_CONST(0x0000000000000004)
 #define CPU_FTR_ALTIVEC			ASM_CONST(0x0000000000000008)
@@ -135,6 +135,7 @@ extern void do_feature_fixups(unsigned l
 #define CPU_FTR_PPC_LE			ASM_CONST(0x0000000000200000)
 #define CPU_FTR_REAL_LE			ASM_CONST(0x0000000000400000)
 #define CPU_FTR_FPU_UNAVAILABLE		ASM_CONST(0x0000000000800000)
+#define CPU_FTR_UNIFIED_ID_CACHE	ASM_CONST(0x0000000001000000)
 
 /*
  * Add the 64-bit processor unique features in the top half of the word;
@@ -154,7 +155,6 @@ extern void do_feature_fixups(unsigned l
 #define CPU_FTR_MMCRA			LONG_ASM_CONST(0x0000004000000000)
 #define CPU_FTR_CTRL			LONG_ASM_CONST(0x0000008000000000)
 #define CPU_FTR_SMT			LONG_ASM_CONST(0x0000010000000000)
-#define CPU_FTR_COHERENT_ICACHE		LONG_ASM_CONST(0x0000020000000000)
 #define CPU_FTR_LOCKLESS_TLBIE		LONG_ASM_CONST(0x0000040000000000)
 #define CPU_FTR_CI_LARGE_PAGE		LONG_ASM_CONST(0x0000100000000000)
 #define CPU_FTR_PAUSE_ZERO		LONG_ASM_CONST(0x0000200000000000)
@@ -206,164 +206,163 @@ extern void do_feature_fixups(unsigned l
 		     !defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \
 		     !defined(CONFIG_BOOKE))
 
-#define CPU_FTRS_PPC601	(CPU_FTR_COMMON | CPU_FTR_601 | CPU_FTR_HPTE_TABLE)
-#define CPU_FTRS_603	(CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
+#define CPU_FTRS_PPC601	(CPU_FTR_COMMON | CPU_FTR_601 | CPU_FTR_HPTE_TABLE | \
+	CPU_FTR_COHERENT_ICACHE | CPU_FTR_UNIFIED_ID_CACHE)
+#define CPU_FTRS_603	(CPU_FTR_COMMON | \
 	    CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
 	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
-#define CPU_FTRS_604	(CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
+#define CPU_FTRS_604	(CPU_FTR_COMMON | \
 	    CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE | \
 	    CPU_FTR_PPC_LE)
-#define CPU_FTRS_740_NOTAU	(CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
+#define CPU_FTRS_740_NOTAU	(CPU_FTR_COMMON | \
 	    CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
 	    CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
-#define CPU_FTRS_740	(CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
+#define CPU_FTRS_740	(CPU_FTR_COMMON | \
 	    CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
 	    CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
 	    CPU_FTR_PPC_LE)
-#define CPU_FTRS_750	(CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
+#define CPU_FTRS_750	(CPU_FTR_COMMON | \
 	    CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
 	    CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
 	    CPU_FTR_PPC_LE)
-#define CPU_FTRS_750CL	(CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
+#define CPU_FTRS_750CL	(CPU_FTR_COMMON | \
 	    CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
 	    CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
 	    CPU_FTR_HAS_HIGH_BATS | CPU_FTR_PPC_LE)
-#define CPU_FTRS_750FX1	(CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
+#define CPU_FTRS_750FX1	(CPU_FTR_COMMON | \
 	    CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
 	    CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
 	    CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM | CPU_FTR_PPC_LE)
-#define CPU_FTRS_750FX2	(CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
+#define CPU_FTRS_750FX2	(CPU_FTR_COMMON | \
 	    CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
 	    CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
 	    CPU_FTR_NO_DPM | CPU_FTR_PPC_LE)
-#define CPU_FTRS_750FX	(CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
+#define CPU_FTRS_750FX	(CPU_FTR_COMMON | \
 	    CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
 	    CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
 	    CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_PPC_LE)
-#define CPU_FTRS_750GX	(CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
+#define CPU_FTRS_750GX	(CPU_FTR_COMMON | \
 	    CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
 	    CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
 	    CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_PPC_LE)
-#define CPU_FTRS_7400_NOTAU	(CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
+#define CPU_FTRS_7400_NOTAU	(CPU_FTR_COMMON | \
 	    CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
 	    CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \
 	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
-#define CPU_FTRS_7400	(CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
+#define CPU_FTRS_7400	(CPU_FTR_COMMON | \
 	    CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
 	    CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \
 	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
-#define CPU_FTRS_7450_20	(CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
+#define CPU_FTRS_7450_20	(CPU_FTR_COMMON | \
 	    CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
 	    CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
 	    CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
-#define CPU_FTRS_7450_21	(CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
+#define CPU_FTRS_7450_21	(CPU_FTR_COMMON | \
 	    CPU_FTR_USE_TB | \
 	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
 	    CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
 	    CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
 	    CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
-#define CPU_FTRS_7450_23	(CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
+#define CPU_FTRS_7450_23	(CPU_FTR_COMMON | \
 	    CPU_FTR_USE_TB | \
 	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
 	    CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
 	    CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
-#define CPU_FTRS_7455_1	(CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
+#define CPU_FTRS_7455_1	(CPU_FTR_COMMON | \
 	    CPU_FTR_USE_TB | \
 	    CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \
 	    CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_HAS_HIGH_BATS | \
 	    CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
-#define CPU_FTRS_7455_20	(CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
+#define CPU_FTRS_7455_20	(CPU_FTR_COMMON | \
 	    CPU_FTR_USE_TB | \
 	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
 	    CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
 	    CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
 	    CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_PPC_LE)
-#define CPU_FTRS_7455	(CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
+#define CPU_FTRS_7455	(CPU_FTR_COMMON | \
 	    CPU_FTR_USE_TB | \
 	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
 	    CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
 	    CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
 	    CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
-#define CPU_FTRS_7447_10	(CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
+#define CPU_FTRS_7447_10	(CPU_FTR_COMMON | \
 	    CPU_FTR_USE_TB | \
 	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
 	    CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
 	    CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
 	    CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE)
-#define CPU_FTRS_7447	(CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
+#define CPU_FTRS_7447	(CPU_FTR_COMMON | \
 	    CPU_FTR_USE_TB | \
 	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
 	    CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
 	    CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
 	    CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
-#define CPU_FTRS_7447A	(CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
+#define CPU_FTRS_7447A	(CPU_FTR_COMMON | \
 	    CPU_FTR_USE_TB | \
 	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
 	    CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
 	    CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
 	    CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
-#define CPU_FTRS_7448	(CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
+#define CPU_FTRS_7448	(CPU_FTR_COMMON | \
 	    CPU_FTR_USE_TB | \
 	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
 	    CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
 	    CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
 	    CPU_FTR_PPC_LE)
-#define CPU_FTRS_82XX	(CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
+#define CPU_FTRS_82XX	(CPU_FTR_COMMON | \
 	    CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB)
-#define CPU_FTRS_G2_LE	(CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \
+#define CPU_FTRS_G2_LE	(CPU_FTR_MAYBE_CAN_DOZE | \
 	    CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS)
-#define CPU_FTRS_E300	(CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \
+#define CPU_FTRS_E300	(CPU_FTR_MAYBE_CAN_DOZE | \
 	    CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS | \
 	    CPU_FTR_COMMON)
-#define CPU_FTRS_E300C2	(CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \
+#define CPU_FTRS_E300C2	(CPU_FTR_MAYBE_CAN_DOZE | \
 	    CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS | \
 	    CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE)
-#define CPU_FTRS_CLASSIC32	(CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
+#define CPU_FTRS_CLASSIC32	(CPU_FTR_COMMON | \
 	    CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE)
-#define CPU_FTRS_8XX	(CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB)
-#define CPU_FTRS_40X	(CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
-	    CPU_FTR_NODSISRALIGN)
-#define CPU_FTRS_44X	(CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
-	    CPU_FTR_NODSISRALIGN)
-#define CPU_FTRS_E200	(CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN)
-#define CPU_FTRS_E500	(CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
-	    CPU_FTR_NODSISRALIGN)
-#define CPU_FTRS_E500_2	(CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
+#define CPU_FTRS_8XX	(CPU_FTR_USE_TB)
+#define CPU_FTRS_40X	(CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN)
+#define CPU_FTRS_44X	(CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN)
+#define CPU_FTRS_E200	(CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
+	    CPU_FTR_COHERENT_ICACHE | CPU_FTR_UNIFIED_ID_CACHE)
+#define CPU_FTRS_E500	(CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN)
+#define CPU_FTRS_E500_2	(CPU_FTR_USE_TB | \
 	    CPU_FTR_BIG_PHYS | CPU_FTR_NODSISRALIGN)
 #define CPU_FTRS_GENERIC_32	(CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
 
 /* 64-bit CPUs */
-#define CPU_FTRS_POWER3	(CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
+#define CPU_FTRS_POWER3	(CPU_FTR_USE_TB | \
 	    CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | CPU_FTR_PPC_LE)
-#define CPU_FTRS_RS64	(CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
+#define CPU_FTRS_RS64	(CPU_FTR_USE_TB | \
 	    CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | \
 	    CPU_FTR_MMCRA | CPU_FTR_CTRL)
-#define CPU_FTRS_POWER4	(CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
+#define CPU_FTRS_POWER4	(CPU_FTR_USE_TB | \
 	    CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
 	    CPU_FTR_MMCRA)
-#define CPU_FTRS_PPC970	(CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
+#define CPU_FTRS_PPC970	(CPU_FTR_USE_TB | \
 	    CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
 	    CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA)
-#define CPU_FTRS_POWER5	(CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
+#define CPU_FTRS_POWER5	(CPU_FTR_USE_TB | \
 	    CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
 	    CPU_FTR_MMCRA | CPU_FTR_SMT | \
 	    CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
 	    CPU_FTR_PURR)
-#define CPU_FTRS_POWER6 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
+#define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | \
 	    CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
 	    CPU_FTR_MMCRA | CPU_FTR_SMT | \
 	    CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
 	    CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
 	    CPU_FTR_DSCR)
-#define CPU_FTRS_CELL	(CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
+#define CPU_FTRS_CELL	(CPU_FTR_USE_TB | \
 	    CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
 	    CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
 	    CPU_FTR_PAUSE_ZERO | CPU_FTR_CI_LARGE_PAGE | CPU_FTR_CELL_TB_BUG)
-#define CPU_FTRS_PA6T (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
+#define CPU_FTRS_PA6T (CPU_FTR_USE_TB | \
 	    CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \
 	    CPU_FTR_ALTIVEC_COMP | CPU_FTR_CI_LARGE_PAGE | \
 	    CPU_FTR_PURR | CPU_FTR_REAL_LE)
-#define CPU_FTRS_COMPATIBLE	(CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
+#define CPU_FTRS_COMPATIBLE	(CPU_FTR_USE_TB | \
 	    CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2)
 
 #ifdef __powerpc64__
Index: working-2.6/arch/powerpc/kernel/misc_32.S
===================================================================
--- working-2.6.orig/arch/powerpc/kernel/misc_32.S	2007-04-19 10:59:55.000000000 +1000
+++ working-2.6/arch/powerpc/kernel/misc_32.S	2007-05-30 16:35:31.000000000 +1000
@@ -392,7 +392,7 @@ BEGIN_FTR_SECTION
 	mtspr   SPRN_L1CSR0,r3
 	isync
 	blr
-END_FTR_SECTION_IFCLR(CPU_FTR_SPLIT_ID_CACHE)
+END_FTR_SECTION_IFSET(CPU_FTR_UNIFIED_ID_CACHE)
 	mfspr	r3,SPRN_L1CSR1
 	ori	r3,r3,L1CSR1_ICFI|L1CSR1_ICLFR
 	mtspr	SPRN_L1CSR1,r3
@@ -419,7 +419,7 @@ END_FTR_SECTION_IFCLR(CPU_FTR_SPLIT_ID_C
 _GLOBAL(__flush_icache_range)
 BEGIN_FTR_SECTION
 	blr				/* for 601, do nothing */
-END_FTR_SECTION_IFCLR(CPU_FTR_SPLIT_ID_CACHE)
+END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
 	li	r5,L1_CACHE_BYTES-1
 	andc	r3,r3,r5
 	subf	r4,r3,r4
@@ -514,8 +514,8 @@ _GLOBAL(invalidate_dcache_range)
  */
 _GLOBAL(__flush_dcache_icache)
 BEGIN_FTR_SECTION
-	blr					/* for 601, do nothing */
-END_FTR_SECTION_IFCLR(CPU_FTR_SPLIT_ID_CACHE)
+	blr
+END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
 	rlwinm	r3,r3,0,0,19			/* Get page base address */
 	li	r4,4096/L1_CACHE_BYTES	/* Number of lines in a page */
 	mtctr	r4
@@ -543,7 +543,7 @@ END_FTR_SECTION_IFCLR(CPU_FTR_SPLIT_ID_C
 _GLOBAL(__flush_dcache_icache_phys)
 BEGIN_FTR_SECTION
 	blr					/* for 601, do nothing */
-END_FTR_SECTION_IFCLR(CPU_FTR_SPLIT_ID_CACHE)
+END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
 	mfmsr	r10
 	rlwinm	r0,r10,0,28,26			/* clear DR */
 	mtmsr	r0
Index: working-2.6/arch/powerpc/kernel/setup_32.c
===================================================================
--- working-2.6.orig/arch/powerpc/kernel/setup_32.c	2007-04-26 13:57:24.000000000 +1000
+++ working-2.6/arch/powerpc/kernel/setup_32.c	2007-05-30 16:35:31.000000000 +1000
@@ -262,13 +262,11 @@ void __init setup_arch(char **cmdline_p)
 	 * Systems with OF can look in the properties on the cpu node(s)
 	 * for a possibly more accurate value.
 	 */
-	if (cpu_has_feature(CPU_FTR_SPLIT_ID_CACHE)) {
-		dcache_bsize = cur_cpu_spec->dcache_bsize;
-		icache_bsize = cur_cpu_spec->icache_bsize;
-		ucache_bsize = 0;
-	} else
-		ucache_bsize = dcache_bsize = icache_bsize
-			= cur_cpu_spec->dcache_bsize;
+	dcache_bsize = cur_cpu_spec->dcache_bsize;
+	icache_bsize = cur_cpu_spec->icache_bsize;
+	ucache_bsize = 0;
+	if (cpu_has_feature(CPU_FTR_UNIFIED_ID_CACHE))
+		ucache_bsize = icache_bsize = dcache_bsize;
 
 	/* reboot on panic */
 	panic_timeout = 180;
Index: working-2.6/arch/ppc/kernel/misc.S
===================================================================
--- working-2.6.orig/arch/ppc/kernel/misc.S	2007-01-24 12:01:17.000000000 +1100
+++ working-2.6/arch/ppc/kernel/misc.S	2007-05-30 16:35:31.000000000 +1000
@@ -328,7 +328,7 @@ BEGIN_FTR_SECTION
 	mtspr   SPRN_L1CSR0,r3
 	isync
 	blr
-END_FTR_SECTION_IFCLR(CPU_FTR_SPLIT_ID_CACHE)
+END_FTR_SECTION_IFSET(CPU_FTR_UNIFIED_ID_CACHE)
 	mfspr	r3,SPRN_L1CSR1
 	ori	r3,r3,L1CSR1_ICFI|L1CSR1_ICLFR
 	mtspr	SPRN_L1CSR1,r3
@@ -355,7 +355,7 @@ END_FTR_SECTION_IFCLR(CPU_FTR_SPLIT_ID_C
 _GLOBAL(__flush_icache_range)
 BEGIN_FTR_SECTION
 	blr				/* for 601, do nothing */
-END_FTR_SECTION_IFCLR(CPU_FTR_SPLIT_ID_CACHE)
+END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
 	li	r5,L1_CACHE_BYTES-1
 	andc	r3,r3,r5
 	subf	r4,r3,r4
@@ -472,7 +472,7 @@ _GLOBAL(flush_dcache_all)
 _GLOBAL(__flush_dcache_icache)
 BEGIN_FTR_SECTION
 	blr					/* for 601, do nothing */
-END_FTR_SECTION_IFCLR(CPU_FTR_SPLIT_ID_CACHE)
+END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
 	rlwinm	r3,r3,0,0,19			/* Get page base address */
 	li	r4,4096/L1_CACHE_BYTES	/* Number of lines in a page */
 	mtctr	r4
@@ -500,7 +500,7 @@ END_FTR_SECTION_IFCLR(CPU_FTR_SPLIT_ID_C
 _GLOBAL(__flush_dcache_icache_phys)
 BEGIN_FTR_SECTION
 	blr					/* for 601, do nothing */
-END_FTR_SECTION_IFCLR(CPU_FTR_SPLIT_ID_CACHE)
+END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
 	mfmsr	r10
 	rlwinm	r0,r10,0,28,26			/* clear DR */
 	mtmsr	r0
Index: working-2.6/arch/ppc/kernel/setup.c
===================================================================
--- working-2.6.orig/arch/ppc/kernel/setup.c	2007-02-14 10:58:22.000000000 +1100
+++ working-2.6/arch/ppc/kernel/setup.c	2007-05-30 16:35:31.000000000 +1000
@@ -526,7 +526,7 @@ void __init setup_arch(char **cmdline_p)
 	 * Systems with OF can look in the properties on the cpu node(s)
 	 * for a possibly more accurate value.
 	 */
-	if (cpu_has_feature(CPU_FTR_SPLIT_ID_CACHE)) {
+	if (! cpu_has_feature(CPU_FTR_UNIFIED_ID_CACHE)) {
 		dcache_bsize = cur_cpu_spec->dcache_bsize;
 		icache_bsize = cur_cpu_spec->icache_bsize;
 		ucache_bsize = 0;

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

^ permalink raw reply

* Device tree aware EMAC driver
From: David Gibson @ 2007-05-30  6:17 UTC (permalink / raw)
  To: linuxppc-dev

This is BenH's rewritten, device tree aware driver for the IBM/AMCC
EMAC, ethernet MAC controller ASIC found on various 4xx CPUs and also
the Axon bridge.
	- Updated to build on current kernels
	- Removed device_type matching requirement on MAL and ZMII, to
match current best practice of omitting device_type unless a
well-defined class binding exists.
	- Added documentation to booting-without-of.txt for the EMAC
binding.

Signed-off-by: David Gibson <david@gibson.dropbear.id.au>

Download from:

http://ozlabs.org/~dgibson/home/emac/powerpc-emac-new-20070530.patch

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

^ permalink raw reply

* Re: [PATCH v2]: Fix e500 v2 core reboot bug
From: Zang Roy-r61911 @ 2007-05-30  5:46 UTC (permalink / raw)
  To: Kumar Gala; +Cc: linuxppc-dev list, Paul Mackerras
In-Reply-To: <A78C881D-26C3-4545-85CA-80C05085C039@kernel.crashing.org>

On Wed, 2007-05-30 at 10:40, Kumar Gala wrote:
> On May 29, 2007, at 9:34 PM, Zang Roy-r61911 wrote:
> 
> > On Wed, 2007-05-30 at 03:29, Kumar Gala wrote:
> >> On May 28, 2007, at 9:36 PM, Zang Roy-r61911 wrote:
> >>
> >>> Fix the e500 v2 core reset bug.
> >>> For e500 v2 core, a new reset control register is added to
> >>> reset the core.
> >>> On 85xx CDS board with e500 v2 core, normal reboot code will
> >>> induce DDR block in u-boot. This patch fixes this bug. It is
> >>> also tested on legacy e500 v1 core.
> >>
> >> what happens on an e500 based 85xx system?
> >
> > Without this patch on MPC8548CDS board, after key in "reboot"
> command,
> > the u-boot will hang at DDR init. See the following log without this
> > patch:
> 
> Sorry I meant what happens on a e500 v1 based 85xx system w/this
> patch.

E500 V1 core can boot up normally with/without this patch. Such as
8555CDS system.

> 
> - k
> 
> >
> > --- log start ---
> > ~ # uname -a
> > Linux mpc8548cds 2.6.22-rc2-g843b8c89-dirty #5 Tue May 29 16:37:21
> CST
> > 2007 ppc
> > unknown
> > ~ # reboot
> > ~ # Stopping the boa webserver:
> > Stopping the port mapper:
> > Stopping inetd:
> > Syncing hardware clock to system time
> > hwclock: Could not set the RTC time: Invalid argument
> > Unmounting filesystems
> > umount: Cannot open /proc/mounts
> > The system is going down NOW !!
> > Sending SIGTERM to all processes.
> > Please stand by while rebooting the system.
> > Restarting system.
> >
> >
> > U-Boot 1.1.6-gcd32691c-dirty (Apr  2 2007 - 17:42:01)
> >
> > CPU:   8548_E, Version: 2.0, (0x80390020)
> > Core:  E500, Version: 2.0, (0x80210020)
> > Clock Configuration:
> >        CPU: 990 MHz, CCB: 396 MHz,
> >        DDR: 198 MHz, LBC:  49 MHz
> > L1:    D-cache 32 kB enabled
> >        I-cache 32 kB enabled
> > Board: CDS Version 0x13, PCI Slot 1
> > CPU Board Revision 114.121 (0x7279)
> >     PCI1: 32 bit, 33 MHz, async
> >     PCI2: disabled
> > I2C:   ready
> > DRAM:  Initializing
> >     SDRAM: 64 MB
> >     DDR: 256 MB
> >
> > --- log end --
> >
> > This patch has been tested on 8548/55 CDS board and 8540/60 ADS
> board.
> >
> >> I'm not terrible happy with blindly writing to rstcr.
> >>
> > I can understand you.
> > But I jut want to make things simple and workable.
> > Any idea?
> 
> one idea would be for us to add a property on the soc node.   
> Something like has-rstcr or something similar in a guts node?
I have seen your suggestion before to add a property in device tree.
But I still think the current implementation is simple.
Anyway, I can try your suggestion.
Thanks.
Roy 

^ permalink raw reply

* Re: Saving to 32 bits of GPRs in signal context
From: Kumar Gala @ 2007-05-30  5:32 UTC (permalink / raw)
  To: Paul Mackerras
  Cc: Ulrich Weigand, Steve Munroe, Anton Blanchard, linuxppc-dev list
In-Reply-To: <18012.61822.197988.279764@cargo.ozlabs.ibm.com>


On May 29, 2007, at 10:37 PM, Paul Mackerras wrote:

> Steve Munroe writes:
>
>> But unless you take the time to write it up like a full ABI change  
>> you are
>> never sure that it IS compatible. And any change to the size/shape of
>> ucontext_t is an ABI change.
>
> There is no change to the size or shape of the ucontext_t.  There is
> no change to the ABI at all, in the sense that everything that is
> currently guaranteed by the ABI is still guaranteed.  An extra
> guarantee is added: the top 32 bits of the GPRs will not change
> unpredictably as long as you don't call a function and don't use
> setcontext or swapcontext to return from a signal handler.
>
> I think actually it would be useful to have the saving/restoring of
> the high 32 bits controlled by a prctl, so that programs have to ask
> explicitly for the new behaviour (and programs that don't want to use
> the high 32 bits don't incur the extra overhead).

I like this, it means we can error if HW doesn't support it and  
requires applications to do something specific to enable the feature.

- k

^ permalink raw reply

* Re: Saving to 32 bits of GPRs in signal context
From: Kumar Gala @ 2007-05-30  5:31 UTC (permalink / raw)
  To: Steve Munroe
  Cc: linuxppc-dev list, Ulrich Weigand, Paul Mackerras,
	Anton Blanchard, Olof Johansson
In-Reply-To: <OFD102D897.20376982-ON862572EB.000F677F-862572EB.000FF942@us.ibm.com>


On May 29, 2007, at 9:54 PM, Steve Munroe wrote:

>
> Kumar Gala <galak@kernel.crashing.org> wrote on 05/29/2007 07:43:05  
> PM:
>
>>
>> On May 29, 2007, at 6:46 PM, Olof Johansson wrote:
>>
>>> On Wed, May 30, 2007 at 07:32:33AM +1000, Benjamin Herrenschmidt
>>> wrote:
>>>> On Tue, 2007-05-29 at 08:10 -0500, Kumar Gala wrote:
>>>>> This is all problematic since some 64-bit implementations may not
>>>>> guarantee the upper bits are valid when in 32-bit mode.  Look  
>>>>> at the
>>>>> 'Computation Modes' section in the architecture specs 2.03 or
>>>>> greater
>>>>> for embedded processors.
>>>>
>>>> Yuck. Well, we might need to export a spearate CPU feature bit to
>>>> indicate that it's the case then.
>>>
>>> No need for a new bit, you should be able to key off of  
>>> PPC_FEATURE_64
>>> && !PPC_FEATURE_BOOKE.
>>
>> Nope, the architecture allows embedded to behave like server parts
>> and support the full 64-bit registers.  We really should have a new
>> feature bit so that if someone has an implementation of an embedded
>> part that supports the functionality, they get the benefit.
>>
> When such exists we can add a bit, until then we can wait. The current
> 32-bit AT_HWCAP is almost full. so we should not allocate bits on
> speculation.

Understandable.. dare I ask about a few of the current AT_HWCAPs we  
do have:

#define PPC_FEATURE_POWER4              0x00080000
#define PPC_FEATURE_POWER5              0x00040000
#define PPC_FEATURE_POWER5_PLUS         0x00020000
#define PPC_FEATURE_ARCH_2_05           0x00001000
#define PPC_FEATURE_PA6T                0x00000800
#define PPC_FEATURE_POWER6_EXT          0x00000200

What exactly are we using these for?  Can we not use platform for  
some of these?

- k

^ permalink raw reply

* [Patch ] Kexec Kdump support for POWER6
From: Sachin P. Sant @ 2007-05-30  5:20 UTC (permalink / raw)
  To: Paul Mackerras; +Cc: linuxppc-dev

[-- Attachment #1: Type: text/plain, Size: 103 bytes --]

Paul, here is the final version of the patch with all review
comments incorporated. 

Thanks
-Sachin



[-- Attachment #2: kexec-kdump-support-on-POWER6 --]
[-- Type: text/plain, Size: 3011 bytes --]

* On Power machines supporting VRMA, Kexec/Kdump does not work.
* Hypervisor stores VRMA mapping used by the OS, in the hpte hash tables.
* Make sure these hpte entries are left untouched.
*
* This patch also adds plpar_pte_read_raw() on the lines of
* plpar_pte_remove_raw().

Signed-off-by : Sachin Sant <sachinp@in.ibm.com>
Signed-off-by : Mohan Kumar M <mohan@in.ibm.com>
---

diff -Naurp a/arch/powerpc/platforms/pseries/lpar.c b/arch/powerpc/platforms/pseries/lpar.c
--- a/arch/powerpc/platforms/pseries/lpar.c	2007-05-19 09:36:17.000000000 +0530
+++ b/arch/powerpc/platforms/pseries/lpar.c	2007-05-29 10:45:34.000000000 +0530
@@ -373,12 +373,23 @@ static void pSeries_lpar_hptab_clear(voi
 {
 	unsigned long size_bytes = 1UL << ppc64_pft_size;
 	unsigned long hpte_count = size_bytes >> 4;
-	unsigned long dummy1, dummy2;
+	unsigned long dummy1, dummy2, dword0;
+	long lpar_rc;
 	int i;
 
 	/* TODO: Use bulk call */
-	for (i = 0; i < hpte_count; i++)
-		plpar_pte_remove_raw(0, i, 0, &dummy1, &dummy2);
+	for (i = 0; i < hpte_count; i++) {
+		/* dont remove HPTEs with VRMA mappings */
+		lpar_rc = plpar_pte_remove_raw(H_ANDCOND, i, HPTE_V_1TB_SEG,
+						&dummy1, &dummy2);
+		if (lpar_rc == H_NOT_FOUND) {
+			lpar_rc = plpar_pte_read_raw(0, i, &dword0, &dummy1);
+			if (!lpar_rc && ((dword0 & HPTE_V_VRMA_MASK)
+				!= HPTE_V_VRMA_MASK))
+				/* Can be hpte for 1TB Seg. So remove it */
+				plpar_pte_remove_raw(0, i, 0, &dummy1, &dummy2);
+		}
+	}
 }
 
 /*
diff -Naurp a/arch/powerpc/platforms/pseries/plpar_wrappers.h b/arch/powerpc/platforms/pseries/plpar_wrappers.h
--- a/arch/powerpc/platforms/pseries/plpar_wrappers.h	2007-05-19 09:36:17.000000000 +0530
+++ b/arch/powerpc/platforms/pseries/plpar_wrappers.h	2007-05-25 12:20:38.000000000 +0530
@@ -108,6 +108,21 @@ static inline long plpar_pte_read(unsign
 	return rc;
 }
 
+/* plpar_pte_read_raw can be called in real mode. It calls plpar_hcall_raw */
+static inline long plpar_pte_read_raw(unsigned long flags, unsigned long ptex,
+		unsigned long *old_pteh_ret, unsigned long *old_ptel_ret)
+{
+	long rc;
+	unsigned long retbuf[PLPAR_HCALL_BUFSIZE];
+
+	rc = plpar_hcall_raw(H_READ, retbuf, flags, ptex);
+
+	*old_pteh_ret = retbuf[0];
+	*old_ptel_ret = retbuf[1];
+
+	return rc;
+}
+
 static inline long plpar_pte_protect(unsigned long flags, unsigned long ptex,
 		unsigned long avpn)
 {
diff -Naurp a/include/asm-powerpc/mmu-hash64.h b/include/asm-powerpc/mmu-hash64.h
--- a/include/asm-powerpc/mmu-hash64.h	2007-05-19 09:36:17.000000000 +0530
+++ b/include/asm-powerpc/mmu-hash64.h	2007-05-29 10:46:22.000000000 +0530
@@ -94,6 +94,9 @@ extern char initial_stab[];
 #define HPTE_R_C		ASM_CONST(0x0000000000000080)
 #define HPTE_R_R		ASM_CONST(0x0000000000000100)
 
+#define HPTE_V_1TB_SEG          ASM_CONST(0x4000000000000000)
+#define HPTE_V_VRMA_MASK        ASM_CONST(0x4001ffffff000000)
+
 /* Values for PP (assumes Ks=0, Kp=1) */
 /* pp0 will always be 0 for linux     */
 #define PP_RWXX	0	/* Supervisor read/write, User none */

^ permalink raw reply

* Re: [RFC/PATCH 5/5] powerpc: Allow ptrace write to pt_regs trap
From: Benjamin Herrenschmidt @ 2007-05-30  4:33 UTC (permalink / raw)
  To: Ulrich Weigand; +Cc: linuxppc-dev, Paul Mackerras, Anton Blanchard
In-Reply-To: <OFF7AF7C86.A40E5407-ON422572EA.00560C99-422572EA.00563CD2@de.ibm.com>


> This doesn't look sufficient.  If you want GDB to use the save/ 
> restore style means of handling interrupted calls (like i386), 
> at the very least we also need the capability to *write* the 
> orig_gpr3 field, which is currently prohibited.  (I don't know 
> why this is case, though.) 

Ok, I found it... put_reg doesn't filter it out but the caller does.
Fixing that too.

Ben.

^ permalink raw reply

* Re: Saving to 32 bits of GPRs in signal context
From: Paul Mackerras @ 2007-05-30  3:37 UTC (permalink / raw)
  To: Steve Munroe; +Cc: Ulrich Weigand, linuxppc-dev list, Anton Blanchard
In-Reply-To: <OF611013C9.F9C3C2DB-ON862572EA.0050F570-862572EA.005197A3@us.ibm.com>

Steve Munroe writes:

> But unless you take the time to write it up like a full ABI change you are
> never sure that it IS compatible. And any change to the size/shape of
> ucontext_t is an ABI change.

There is no change to the size or shape of the ucontext_t.  There is
no change to the ABI at all, in the sense that everything that is
currently guaranteed by the ABI is still guaranteed.  An extra
guarantee is added: the top 32 bits of the GPRs will not change
unpredictably as long as you don't call a function and don't use
setcontext or swapcontext to return from a signal handler.

I think actually it would be useful to have the saving/restoring of
the high 32 bits controlled by a prctl, so that programs have to ask
explicitly for the new behaviour (and programs that don't want to use
the high 32 bits don't incur the extra overhead).

Paul.

^ permalink raw reply

* Re: Saving to 32 bits of GPRs in signal context
From: Steve Munroe @ 2007-05-30  2:54 UTC (permalink / raw)
  To: Kumar Gala
  Cc: linuxppc-dev list, Ulrich Weigand, Paul Mackerras,
	Anton Blanchard, Olof Johansson
In-Reply-To: <16FB57DB-8E02-4F7D-A7B5-BF9719A61BC6@kernel.crashing.org>


Kumar Gala <galak@kernel.crashing.org> wrote on 05/29/2007 07:43:05 PM:

>
> On May 29, 2007, at 6:46 PM, Olof Johansson wrote:
>
> > On Wed, May 30, 2007 at 07:32:33AM +1000, Benjamin Herrenschmidt
> > wrote:
> >> On Tue, 2007-05-29 at 08:10 -0500, Kumar Gala wrote:
> >>> This is all problematic since some 64-bit implementations may not
> >>> guarantee the upper bits are valid when in 32-bit mode.  Look at the
> >>> 'Computation Modes' section in the architecture specs 2.03 or
> >>> greater
> >>> for embedded processors.
> >>
> >> Yuck. Well, we might need to export a spearate CPU feature bit to
> >> indicate that it's the case then.
> >
> > No need for a new bit, you should be able to key off of PPC_FEATURE_64
> > && !PPC_FEATURE_BOOKE.
>
> Nope, the architecture allows embedded to behave like server parts
> and support the full 64-bit registers.  We really should have a new
> feature bit so that if someone has an implementation of an embedded
> part that supports the functionality, they get the benefit.
>
When such exists we can add a bit, until then we can wait. The current
32-bit AT_HWCAP is almost full. so we should not allocate bits on
speculation.

Steven J. Munroe
Linux on Power Toolchain Architect
IBM Corporation, Linux Technology Center

^ permalink raw reply

* Re: [PATCH v2]: Fix e500 v2 core reboot bug
From: Kumar Gala @ 2007-05-30  2:40 UTC (permalink / raw)
  To: Zang Roy-r61911; +Cc: linuxppc-dev list, Paul Mackerras
In-Reply-To: <1180492466.12577.6.camel@localhost.localdomain>


On May 29, 2007, at 9:34 PM, Zang Roy-r61911 wrote:

> On Wed, 2007-05-30 at 03:29, Kumar Gala wrote:
>> On May 28, 2007, at 9:36 PM, Zang Roy-r61911 wrote:
>>
>>> Fix the e500 v2 core reset bug.
>>> For e500 v2 core, a new reset control register is added to
>>> reset the core.
>>> On 85xx CDS board with e500 v2 core, normal reboot code will
>>> induce DDR block in u-boot. This patch fixes this bug. It is
>>> also tested on legacy e500 v1 core.
>>
>> what happens on an e500 based 85xx system?
>
> Without this patch on MPC8548CDS board, after key in "reboot" command,
> the u-boot will hang at DDR init. See the following log without this
> patch:

Sorry I meant what happens on a e500 v1 based 85xx system w/this patch.

- k

>
> --- log start ---
> ~ # uname -a
> Linux mpc8548cds 2.6.22-rc2-g843b8c89-dirty #5 Tue May 29 16:37:21 CST
> 2007 ppc
> unknown
> ~ # reboot
> ~ # Stopping the boa webserver:
> Stopping the port mapper:
> Stopping inetd:
> Syncing hardware clock to system time
> hwclock: Could not set the RTC time: Invalid argument
> Unmounting filesystems
> umount: Cannot open /proc/mounts
> The system is going down NOW !!
> Sending SIGTERM to all processes.
> Please stand by while rebooting the system.
> Restarting system.
>
>
> U-Boot 1.1.6-gcd32691c-dirty (Apr  2 2007 - 17:42:01)
>
> CPU:   8548_E, Version: 2.0, (0x80390020)
> Core:  E500, Version: 2.0, (0x80210020)
> Clock Configuration:
>        CPU: 990 MHz, CCB: 396 MHz,
>        DDR: 198 MHz, LBC:  49 MHz
> L1:    D-cache 32 kB enabled
>        I-cache 32 kB enabled
> Board: CDS Version 0x13, PCI Slot 1
> CPU Board Revision 114.121 (0x7279)
>     PCI1: 32 bit, 33 MHz, async
>     PCI2: disabled
> I2C:   ready
> DRAM:  Initializing
>     SDRAM: 64 MB
>     DDR: 256 MB
>
> --- log end --
>
> This patch has been tested on 8548/55 CDS board and 8540/60 ADS board.
>
>> I'm not terrible happy with blindly writing to rstcr.
>>
> I can understand you.
> But I jut want to make things simple and workable.
> Any idea?

one idea would be for us to add a property on the soc node.   
Something like has-rstcr or something similar in a guts node?

- k

^ permalink raw reply

* Re: [PATCH v2]: Fix e500 v2 core reboot bug
From: Zang Roy-r61911 @ 2007-05-30  2:34 UTC (permalink / raw)
  To: Kumar Gala; +Cc: linuxppc-dev list, Paul Mackerras
In-Reply-To: <BA0C2035-FCAD-4B34-A622-F79432079F10@kernel.crashing.org>

On Wed, 2007-05-30 at 03:29, Kumar Gala wrote:
> On May 28, 2007, at 9:36 PM, Zang Roy-r61911 wrote:
> 
> > Fix the e500 v2 core reset bug.
> > For e500 v2 core, a new reset control register is added to
> > reset the core.
> > On 85xx CDS board with e500 v2 core, normal reboot code will
> > induce DDR block in u-boot. This patch fixes this bug. It is
> > also tested on legacy e500 v1 core.
> 
> what happens on an e500 based 85xx system?

Without this patch on MPC8548CDS board, after key in "reboot" command,
the u-boot will hang at DDR init. See the following log without this
patch:

--- log start ---
~ # uname -a
Linux mpc8548cds 2.6.22-rc2-g843b8c89-dirty #5 Tue May 29 16:37:21 CST
2007 ppc
unknown
~ # reboot
~ # Stopping the boa webserver:
Stopping the port mapper:
Stopping inetd:
Syncing hardware clock to system time
hwclock: Could not set the RTC time: Invalid argument
Unmounting filesystems
umount: Cannot open /proc/mounts
The system is going down NOW !!
Sending SIGTERM to all processes.
Please stand by while rebooting the system.
Restarting system.


U-Boot 1.1.6-gcd32691c-dirty (Apr  2 2007 - 17:42:01)

CPU:   8548_E, Version: 2.0, (0x80390020)
Core:  E500, Version: 2.0, (0x80210020)
Clock Configuration:
       CPU: 990 MHz, CCB: 396 MHz,
       DDR: 198 MHz, LBC:  49 MHz
L1:    D-cache 32 kB enabled
       I-cache 32 kB enabled
Board: CDS Version 0x13, PCI Slot 1
CPU Board Revision 114.121 (0x7279)
    PCI1: 32 bit, 33 MHz, async
    PCI2: disabled
I2C:   ready
DRAM:  Initializing
    SDRAM: 64 MB
    DDR: 256 MB

--- log end --

This patch has been tested on 8548/55 CDS board and 8540/60 ADS board.

> I'm not terrible happy with blindly writing to rstcr.
> 
I can understand you.
But I jut want to make things simple and workable.
Any idea?
Roy

^ permalink raw reply

* RE: [PATCH 5/5] Set IDE in ULI1575 to not native mode.
From: Zhang Wei-r63237 @ 2007-05-30  2:25 UTC (permalink / raw)
  To: Kumar Gala; +Cc: linuxppc-dev, paulus
In-Reply-To: <A5691757-8218-489B-B809-DE44F81EA5C8@kernel.crashing.org>

Hi,

> > Set IDE in ULI1575 to not 100% native mode, which forces
> > the IDE driver to probe the irq itself.
> >
> > Signed-off-by: Zhang Wei <wei.zhang@freescale.com>
>=20
> What causes this to be needed?
>=20

If the driver does not probe the irq itself, the driver will get wrong
irq for lagecy IDE device.

Thanks!
Wei.

^ permalink raw reply

* Consolidate cuboot initialization code
From: David Gibson @ 2007-05-30  2:01 UTC (permalink / raw)
  To: Paul Mackerras; +Cc: linuxppc-dev

The various cuboot platforms (i.e. pre-device tree aware u-boot for
83xx, 85xx and Ebony) share a certain amount of code for parsing the
boot parameters.  To a certain extent that's inevitable, since they
platforms have different definitions of the bd_t structure.  However,
with some macro work and a helper function, this patch improves the
situation a bit.

In the process, this fixes a bug on Ebony, which was incorrectly
handling the parameters passed form u-boot for the command line (the
bug was copied from 83xx and 85xx which have subsequently been fixed).

Signed-off-by: David Gibson <david@gibson.dropbear.id.au>

Index: working-2.6/arch/powerpc/boot/cuboot.c
===================================================================
--- /dev/null	1970-01-01 00:00:00.000000000 +0000
+++ working-2.6/arch/powerpc/boot/cuboot.c	2007-05-29 17:23:39.000000000 +1000
@@ -0,0 +1,35 @@
+/*
+ * Compatibility for old (not device tree aware) U-Boot versions
+ *
+ * Author: Scott Wood <scottwood@freescale.com>
+ * Consolidated using macros by David Gibson <david@gibson.dropbear.id.au>
+ *
+ * Copyright 2007 David Gibson, IBM Corporation.
+ * Copyright (c) 2007 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include "ops.h"
+#include "stdio.h"
+
+#include "ppcboot.h"
+
+extern char _end[];
+extern char _dtb_start[], _dtb_end[];
+
+void cuboot_init(unsigned long r4, unsigned long r5,
+		 unsigned long r6, unsigned long r7,
+		 unsigned long end_of_ram)
+{
+	unsigned long avail_ram = end_of_ram - (unsigned long)_end;
+
+	loader_info.initrd_addr = r4;
+	loader_info.initrd_size = r4 ? r5 - r4 : 0;
+	loader_info.cmdline = (char *)r6;
+	loader_info.cmdline_len = r7 - r6;
+
+	simple_alloc_init(_end, avail_ram - 1024*1024, 32, 64);
+}
Index: working-2.6/arch/powerpc/boot/cuboot-83xx.c
===================================================================
--- working-2.6.orig/arch/powerpc/boot/cuboot-83xx.c	2007-05-29 17:23:36.000000000 +1000
+++ working-2.6/arch/powerpc/boot/cuboot-83xx.c	2007-05-29 17:23:39.000000000 +1000
@@ -12,12 +12,12 @@
 
 #include "ops.h"
 #include "stdio.h"
+#include "cuboot.h"
 
 #define TARGET_83xx
 #include "ppcboot.h"
 
 static bd_t bd;
-extern char _end[];
 extern char _dtb_start[], _dtb_end[];
 
 static void platform_fixups(void)
@@ -52,16 +52,7 @@ static void platform_fixups(void)
 void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
                    unsigned long r6, unsigned long r7)
 {
-	unsigned long end_of_ram = bd.bi_memstart + bd.bi_memsize;
-	unsigned long avail_ram = end_of_ram - (unsigned long)_end;
-
-	memcpy(&bd, (bd_t *)r3, sizeof(bd));
-	loader_info.initrd_addr = r4;
-	loader_info.initrd_size = r4 ? r5 - r4 : 0;
-	loader_info.cmdline = (char *)r6;
-	loader_info.cmdline_len = r7 - r6;
-
-	simple_alloc_init(_end, avail_ram - 1024*1024, 32, 64);
+	CUBOOT_INIT();
 	ft_init(_dtb_start, _dtb_end - _dtb_start, 32);
 	serial_console_init();
 	platform_ops.fixups = platform_fixups;
Index: working-2.6/arch/powerpc/boot/cuboot-85xx.c
===================================================================
--- working-2.6.orig/arch/powerpc/boot/cuboot-85xx.c	2007-05-29 17:23:36.000000000 +1000
+++ working-2.6/arch/powerpc/boot/cuboot-85xx.c	2007-05-29 17:23:39.000000000 +1000
@@ -12,12 +12,12 @@
 
 #include "ops.h"
 #include "stdio.h"
+#include "cuboot.h"
 
 #define TARGET_85xx
 #include "ppcboot.h"
 
 static bd_t bd;
-extern char _end[];
 extern char _dtb_start[], _dtb_end[];
 
 static void platform_fixups(void)
@@ -53,16 +53,7 @@ static void platform_fixups(void)
 void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
                    unsigned long r6, unsigned long r7)
 {
-	unsigned long end_of_ram = bd.bi_memstart + bd.bi_memsize;
-	unsigned long avail_ram = end_of_ram - (unsigned long)_end;
-
-	memcpy(&bd, (bd_t *)r3, sizeof(bd));
-	loader_info.initrd_addr = r4;
-	loader_info.initrd_size = r4 ? r5 - r4 : 0;
-	loader_info.cmdline = (char *)r6;
-	loader_info.cmdline_len = r7 - r6;
-
-	simple_alloc_init(_end, avail_ram - 1024*1024, 32, 64);
+	CUBOOT_INIT();
 	ft_init(_dtb_start, _dtb_end - _dtb_start, 32);
 	serial_console_init();
 	platform_ops.fixups = platform_fixups;
Index: working-2.6/arch/powerpc/boot/cuboot.h
===================================================================
--- /dev/null	1970-01-01 00:00:00.000000000 +0000
+++ working-2.6/arch/powerpc/boot/cuboot.h	2007-05-29 17:23:39.000000000 +1000
@@ -0,0 +1,14 @@
+#ifndef _PPC_BOOT_CUBOOT_H_
+#define _PPC_BOOT_CUBOOT_H_
+
+void cuboot_init(unsigned long r4, unsigned long r5,
+		 unsigned long r6, unsigned long r7,
+		 unsigned long end_of_ram);
+
+#define CUBOOT_INIT() \
+	do { \
+		memcpy(&bd, (bd_t *)r3, sizeof(bd)); \
+		cuboot_init(r4, r5, r6, r7, bd.bi_memstart + bd.bi_memsize); \
+	} while (0)
+
+#endif /* _PPC_BOOT_CUBOOT_H_ */
Index: working-2.6/arch/powerpc/boot/cuboot-ebony.c
===================================================================
--- working-2.6.orig/arch/powerpc/boot/cuboot-ebony.c	2007-05-29 17:23:36.000000000 +1000
+++ working-2.6/arch/powerpc/boot/cuboot-ebony.c	2007-05-29 17:23:39.000000000 +1000
@@ -15,28 +15,16 @@
 #include "ops.h"
 #include "stdio.h"
 #include "44x.h"
+#include "cuboot.h"
 
 #define TARGET_44x
 #include "ppcboot.h"
 
 static bd_t bd;
-extern char _end[];
-
-BSS_STACK(4096);
 
 void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
                    unsigned long r6, unsigned long r7)
 {
-	unsigned long end_of_ram = bd.bi_memstart + bd.bi_memsize;
-	unsigned long avail_ram = end_of_ram - (unsigned long)_end;
-
-	memcpy(&bd, (bd_t *)r3, sizeof(bd));
-	loader_info.initrd_addr = r4;
-	loader_info.initrd_size = r4 ? r5 : 0;
-	loader_info.cmdline = (char *)r6;
-	loader_info.cmdline_len = r7 - r6;
-
-	simple_alloc_init(_end, avail_ram, 32, 64);
-
+	CUBOOT_INIT();
 	ebony_init(&bd.bi_enetaddr, &bd.bi_enet1addr);
 }
Index: working-2.6/arch/powerpc/boot/Makefile
===================================================================
--- working-2.6.orig/arch/powerpc/boot/Makefile	2007-05-29 17:23:53.000000000 +1000
+++ working-2.6/arch/powerpc/boot/Makefile	2007-05-29 17:24:16.000000000 +1000
@@ -44,7 +44,7 @@ $(addprefix $(obj)/,$(zlib) gunzip_util.
 src-wlib := string.S crt0.S stdio.c main.c flatdevtree.c flatdevtree_misc.c \
 		ns16550.c serial.c simple_alloc.c div64.S util.S \
 		gunzip_util.c elf_util.c $(zlib) devtree.c oflib.c ofconsole.c \
-		44x.c ebony.c mv64x60.c mpsc.c mv64x60_i2c.c
+		44x.c ebony.c mv64x60.c mpsc.c mv64x60_i2c.c cuboot.c
 src-plat := of.c cuboot-83xx.c cuboot-85xx.c holly.c \
 		cuboot-ebony.c treeboot-ebony.c prpmc2800.c
 src-boot := $(src-wlib) $(src-plat) empty.c

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

^ permalink raw reply

* Re: Fix problems with Holly's DT representation of ethernet PHYs
From: David Gibson @ 2007-05-30  1:26 UTC (permalink / raw)
  To: Segher Boessenkool; +Cc: Alexandre Bounine, Paul Mackerras, linuxppc-dev list
In-Reply-To: <c7c131c3a7fdf7727d9ea1e40775017a@kernel.crashing.org>

On Tue, May 29, 2007 at 08:43:38AM +0200, Segher Boessenkool wrote:
> > +		MDIO: mdio@6000 {
> >  			device_type = "mdio";
> > -			compatible = "tsi-ethernet";
> > +			compatible = "tsi-mdio";
> 
> Hrm, did I miss this before?  A more exact "compatible"
> property would be better ("tsi109-mdio" "tsi108-mdio" or
> something like that).

Hrm, yeah.  I thought about that, but left it as tsi-mdio to match the
other rather non-specific compatible properties ("tsi-ethernet",
"tsi-brige", "tsi-i2c" and so forth).

But I guess I'd better fix that too.  Next version of the patch fixes
a whole bunch of places to use tsi108/tsi109 compatible properties.

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

^ permalink raw reply

* Fix problems with device tree representation of TSI-1xx bridges
From: David Gibson @ 2007-05-30  1:37 UTC (permalink / raw)
  To: Paul Mackerras; +Cc: Alexandre Bounine, linuxppc-dev list

This patch fixes some problems with the way the some things
represented in the device tree for the Holly and Taiga boards.  This
means changes both to the dts files, and to the code which
instantiates the tsi108 ethernet platform devices based on the device
tree.

	- First, and most importantly, the ethernet PHYs are given
with an identical 'reg' property.  This reg currently encodes the
accessible register used to initiate mdio interaction with the PHYs,
rather than a meaningful address on the parent bus (mdio in this
case), which is incorrect.  Instead we give the address of these
registers as 'reg' in the mdio node itself, and encode the ID of each
phy in their 'reg' propertyies.
	- Currently the platform device constructor enables a
workaround in the tsi108 ethernet driver based on the compatible
property of the PHY.  This is incorrect, because the workaround in
question is necessary due to the board's wiring of the PHY, not the
model of PHY itself.  This patch alters the constructor to instead
enable the workaround based on a new special property in the PHY node.
	- The compatible properties on a number of nodes in the device
tree are insufficiently precise.  In particular the PHYs give only
"bcm54xx", which is broken, since there are many bcm54xx PHY models,
and they have differences which matter.  The mdio had a compatible
property of "tsi-ethernet" identical to the ethernet MAC nodes, which
doesn't make sense.  The ethernet, i2c, bridge and PCI nodes were
given only as "tsi-*" which is somewhat inprecise, we replace with
"tsi108-*" in the case of Taiga (which has a TSI108 bridge), and
"tsi109-*", "tsi108-*" in the case of Holly (which has a TSI109
bridge).
	- We remove some "model" properties from the ethernets on
Taiga board which were neither useful nor adequately precise.
	- On Holly we change to using a dtc label instead of a full
path to reference the MPIC node, which makes the dts a little more
readable.

Signed-off-by: David Gibson <david@gibson.dropbear.id.au>

Index: working-2.6/arch/powerpc/boot/dts/holly.dts
===================================================================
--- working-2.6.orig/arch/powerpc/boot/dts/holly.dts	2007-05-30 11:01:58.000000000 +1000
+++ working-2.6/arch/powerpc/boot/dts/holly.dts	2007-05-30 11:05:29.000000000 +1000
@@ -46,7 +46,7 @@
 
   	tsi109@c0000000 {
 		device_type = "tsi-bridge";
-		compatible = "tsi-bridge";
+		compatible = "tsi109-bridge", "tsi108-bridge";
 		#address-cells = <1>;
 		#size-cells = <1>;
 		ranges = <00000000 c0000000 00010000>;
@@ -54,52 +54,55 @@
 
 		i2c@7000 {
 			device_type = "i2c";
-			compatible  = "tsi-i2c";
-			interrupt-parent = < &/tsi109@c0000000/pic@7400 >;
+			compatible  = "tsi109-i2c", "tsi108-i2c";
+			interrupt-parent = <&MPIC>;
 			interrupts = <e 2>;
 			reg = <7000 400>;
 		};
 
-		mdio@6000 {
+		MDIO: mdio@6000 {
 			device_type = "mdio";
-			compatible = "tsi-ethernet";
+			compatible = "tsi109-mdio", "tsi108-mdio";
+			reg = <6000 50>;
+			#address-cells = <1>;
+			#size-cells = <0>;
 
-			PHY1: ethernet-phy@6000 {
-				device_type = "ethernet-phy";
-				compatible = "bcm54xx";
-				reg = <6000 50>;
-				phy-id = <1>;
+			PHY1: ethernet-phy@1 {
+				compatible = "bcm5461a";
+				reg = <1>;
+				txc-rxc-delay-disable;
 			};
 
-			PHY2: ethernet-phy@6400 {
-				device_type = "ethernet-phy";
-				compatible = "bcm54xx";
-				reg = <6000 50>;
-				phy-id = <2>;
+			PHY2: ethernet-phy@2 {
+				compatible = "bcm5461a";
+				reg = <2>;
+				txc-rxc-delay-disable;
 			};
 		};
 
 		ethernet@6200 {
 			device_type = "network";
-			compatible = "tsi-ethernet";
+			compatible = "tsi109-ethernet", "tsi108-ethernet";
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <6000 200>;
 			local-mac-address = [ 00 00 00 00 00 00 ];
-			interrupt-parent = < &/tsi109@c0000000/pic@7400 >;
+			interrupt-parent = <&MPIC>;
 			interrupts = <10 2>;
+			mdio-handle = <&MDIO>;
 			phy-handle = <&PHY1>;
 		};
 
 		ethernet@6600 {
 			device_type = "network";
-			compatible = "tsi-ethernet";
+			compatible = "tsi109-ethernet", "tsi108-ethernet";
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <6400 200>;
 			local-mac-address = [ 00 00 00 00 00 00 ];
-			interrupt-parent = < &/tsi109@c0000000/pic@7400 >;
+			interrupt-parent = <&MPIC>;
 			interrupts = <11 2>;
+			mdio-handle = <&MDIO>;
 			phy-handle = <&PHY2>;
 		};
 
@@ -110,7 +113,7 @@
 			virtual-reg = <c0007808>;
 			clock-frequency = <3F9C6000>;
 			current-speed = <1c200>;
-			interrupt-parent = < &/tsi109@c0000000/pic@7400 >;
+			interrupt-parent = <&MPIC>;
 			interrupts = <c 2>;
 		};
 
@@ -121,7 +124,7 @@
 			virtual-reg = <c0007c08>;
 			clock-frequency = <3F9C6000>;
 			current-speed = <1c200>;
-			interrupt-parent = < &/tsi109@c0000000/pic@7400 >;
+			interrupt-parent = <&MPIC>;
 			interrupts = <d 2>;
 		};
 
@@ -136,7 +139,7 @@
 
 		pci@1000 {
 			device_type = "pci";
-			compatible = "tsi109";
+			compatible = "tsi109-pci", "tsi108-pci";
 			#interrupt-cells = <1>;
 			#size-cells = <2>;
 			#address-cells = <3>;
@@ -150,7 +153,7 @@
 			ranges = <02000000 0 40000000 40000000 0 10000000
 				  01000000 0 00000000 7e000000 0 00010000>;
 			clock-frequency = <7f28154>;
-			interrupt-parent = < &/tsi109@c0000000/pic@7400 >;
+			interrupt-parent = <&MPIC>;
 			interrupts = <17 2>;
 			interrupt-map-mask = <f800 0 0 7>;
 			/*----------------------------------------------------+
@@ -186,7 +189,7 @@
  				#address-cells = <0>;
  				#interrupt-cells = <2>;
  				interrupts = <17 2>;
-				interrupt-parent = < &/tsi109@c0000000/pic@7400 >;
+				interrupt-parent = <&MPIC>;
 			};
 		};
 	};
Index: working-2.6/arch/powerpc/sysdev/tsi108_dev.c
===================================================================
--- working-2.6.orig/arch/powerpc/sysdev/tsi108_dev.c	2007-05-08 14:58:06.000000000 +1000
+++ working-2.6/arch/powerpc/sysdev/tsi108_dev.c	2007-05-30 11:08:38.000000000 +1000
@@ -72,12 +72,11 @@ static int __init tsi108_eth_of_init(voi
 	int ret;
 
 	for (np = NULL, i = 0;
-	     (np = of_find_compatible_node(np, "network", "tsi-ethernet")) != NULL;
+	     (np = of_find_compatible_node(np, "network", "tsi108-ethernet")) != NULL;
 	     i++) {
 		struct resource r[2];
-		struct device_node *phy;
+		struct device_node *phy, *mdio;
 		hw_info tsi_eth_data;
-		const unsigned int *id;
 		const unsigned int *phy_id;
 		const void *mac_addr;
 		const phandle *ph;
@@ -111,6 +110,13 @@ static int __init tsi108_eth_of_init(voi
 		if (mac_addr)
 			memcpy(tsi_eth_data.mac_addr, mac_addr, 6);
 
+		ph = of_get_property(np, "mdio-handle", NULL);
+		mdio = of_find_node_by_phandle(*ph);
+		ret = of_address_to_resource(mdio, 0, &res);
+		of_node_put(mdio);
+		if (ret)
+			goto unreg;
+
 		ph = of_get_property(np, "phy-handle", NULL);
 		phy = of_find_node_by_phandle(*ph);
 
@@ -119,20 +125,25 @@ static int __init tsi108_eth_of_init(voi
 			goto unreg;
 		}
 
-		id = of_get_property(phy, "reg", NULL);
-		phy_id = of_get_property(phy, "phy-id", NULL);
-		ret = of_address_to_resource(phy, 0, &res);
-		if (ret) {
-			of_node_put(phy);
-			goto unreg;
-		}
+		phy_id = of_get_property(phy, "reg", NULL);
+
 		tsi_eth_data.regs = r[0].start;
 		tsi_eth_data.phyregs = res.start;
 		tsi_eth_data.phy = *phy_id;
 		tsi_eth_data.irq_num = irq_of_parse_and_map(np, 0);
-		if (of_device_is_compatible(phy, "bcm54xx"))
+
+		/* Some boards with the TSI108 bridge (e.g. Holly)
+		 * have a miswiring of the ethernet PHYs which
+		 * requires a workaround.  The special
+		 * "txc-rxc-delay-disable" property enables this
+		 * workaround.  FIXME: Need to port the tsi108_eth
+		 * driver itself to phylib and use a non-misleading
+		 * name for the workaround flag - it's not actually to
+		 * do with the model of PHY in use */
+		if (of_get_property(phy, "txc-rxc-delay-disable", NULL))
 			tsi_eth_data.phy_type = TSI108_PHY_BCM54XX;
 		of_node_put(phy);
+
 		ret =
 		    platform_device_add_data(tsi_eth_dev, &tsi_eth_data,
 					     sizeof(hw_info));
Index: working-2.6/arch/powerpc/boot/dts/mpc7448hpc2.dts
===================================================================
--- working-2.6.orig/arch/powerpc/boot/dts/mpc7448hpc2.dts	2007-05-21 12:47:17.000000000 +1000
+++ working-2.6/arch/powerpc/boot/dts/mpc7448hpc2.dts	2007-05-30 11:04:05.000000000 +1000
@@ -45,7 +45,7 @@
 		#address-cells = <1>;
 		#size-cells = <1>;
 		#interrupt-cells = <2>;
-		device_type = "tsi-bridge";
+		device_type = "tsi108-bridge";
 		ranges = <00000000 c0000000 00010000>;
 		reg = <c0000000 00010000>;
 		bus-frequency = <0>;
@@ -55,27 +55,26 @@
 			interrupts = <E 0>;
 			reg = <7000 400>;
 			device_type = "i2c";
-			compatible  = "tsi-i2c";
+			compatible  = "tsi108-i2c";
 		};
 
-		mdio@6000 {
+		MDIO: mdio@6000 {
 			device_type = "mdio";
-			compatible = "tsi-ethernet";
+			compatible = "tsi108-mdio";
+			reg = <6000 50>;
+			#address-cells = <1>;
+			#size-cells = <0>;
 
-			phy8: ethernet-phy@6000 {
+			phy8: ethernet-phy@8 {
 				interrupt-parent = <&mpic>;
 				interrupts = <2 1>;
-				reg = <6000 50>;
-				phy-id = <8>;
-				device_type = "ethernet-phy";
+				reg = <8>;
 			};
 
-			phy9: ethernet-phy@6400 {
+			phy9: ethernet-phy@9 {
 				interrupt-parent = <&mpic>;
 				interrupts = <2 1>;
-				reg = <6000 50>;
-				phy-id = <9>;
-				device_type = "ethernet-phy";
+				reg = <9>;
 			};
 
 		};
@@ -83,12 +82,12 @@
 		ethernet@6200 {
 			#size-cells = <0>;
 			device_type = "network";
-			model = "TSI-ETH";
-			compatible = "tsi-ethernet";
+			compatible = "tsi108-ethernet";
 			reg = <6000 200>;
 			address = [ 00 06 D2 00 00 01 ];
 			interrupts = <10 2>;
 			interrupt-parent = <&mpic>;
+			mdio-handle = <&MDIO>;
 			phy-handle = <&phy8>;
 		};
 
@@ -96,12 +95,12 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			device_type = "network";
-			model = "TSI-ETH";
-			compatible = "tsi-ethernet";
+			compatible = "tsi108-ethernet";
 			reg = <6400 200>;
 			address = [ 00 06 D2 00 00 02 ];
 			interrupts = <11 2>;
 			interrupt-parent = <&mpic>;
+			mdio-handle = <&MDIO>;
 			phy-handle = <&phy9>;
 		};
 
@@ -135,7 +134,7 @@
                        	big-endian;
 		};
 		pci@1000 {
-			compatible = "tsi10x";
+			compatible = "tsi108-pci";
 			device_type = "pci";
 			#interrupt-cells = <1>;
 			#size-cells = <2>;


-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

^ permalink raw reply

* [PATCH] VIOTAPE:  Use designated initializers for fops member structures.
From: Stephen Rothwell @ 2007-05-30  1:29 UTC (permalink / raw)
  To: paulus; +Cc: Andrew Morton, ppc-dev, Robert P. J. Day
In-Reply-To: <Pine.LNX.4.64.0705281702300.16015@localhost.localdomain>

From: Robert P. J. Day <rpjday@mindspring.com>

Replace the old-style member initializers with the newer designated
initializers.

Signed-off-by: Robert P. J. Day <rpjday@mindspring.com>
Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
---
 drivers/char/viotape.c |   12 ++++++------
 1 files changed, 6 insertions(+), 6 deletions(-)

Paul, one for 2.6.23.
-- 
Cheers,
Stephen Rothwell                    sfr@canb.auug.org.au

diff --git a/drivers/char/viotape.c b/drivers/char/viotape.c
index 13faf8d..db57277 100644
--- a/drivers/char/viotape.c
+++ b/drivers/char/viotape.c
@@ -873,12 +873,12 @@ free_op:
 }
 
 const struct file_operations viotap_fops = {
-	owner: THIS_MODULE,
-	read: viotap_read,
-	write: viotap_write,
-	ioctl: viotap_ioctl,
-	open: viotap_open,
-	release: viotap_release,
+	.owner =	THIS_MODULE,
+	.read =		viotap_read,
+	.write =	viotap_write,
+	.ioctl =	viotap_ioctl,
+	.open =		viotap_open,
+	.release =	viotap_release,
 };
 
 /* Handle interrupt events for tape */
-- 
1.5.1.4

^ permalink raw reply related

* Re: AMD to ST migration issues
From: Michael Neuling @ 2007-05-30  0:57 UTC (permalink / raw)
  To: Narayanan, Ganesh; +Cc: linuxppc-dev
In-Reply-To: <7619F3097FAB384287CF636FF92D0CA109943577@exsvl01.hq.netapp.com>

> We have been using PPC with a AMD flash (Spansion S29GL128M) on it for
> our applications.  We are running Montavista linux on it.  Recently we
> replaced the AMD flash with ST flash (M29W128FH).  The u-boot boots up
> and during the kernel boot, I am getting the following error messages
> and the system doesn't boot after this:
> =20
> 
> jffs2_scan_eraseblock(): Magic bitmask 0x1985 not found at 0x00000000:
> 0x0020 instead
> jffs2_scan_eraseblock(): Magic bitmask 0x1985 not found at 0x0000001c:
> 0x2212 instead
> jffs2_scan_eraseblock(): Magic bitmask 0x1985 not found at 0x00000020:
> 0x0020 instead
> jffs2_scan_eraseblock(): Magic bitmask 0x1985 not found at 0x0000003c:
> 0x2212 instead
> jffs2_scan_eraseblock(): Magic bitmask 0x1985 not found at 0x00000040:
> 0x0020 instead
> jffs2_scan_eraseblock(): Magic bitmask 0x1985 not found at 0x0000005c:
> 0x2212 instead
> jffs2_scan_eraseblock(): Magic bitmask 0x1985 not found at 0x00000060:
> 0x0020 instead
> =20
> It would be really great if someone could let me know what is going
> wrong in this.

This might be better answered at the jffs2 list which is linked off
here:  http://sourceware.org/jffs2/ 

Mikey

^ permalink raw reply

* [PATCH/RFC 2/2] powerpc: BOOKE watchdog add panic and reboot handlers
From: Dave Jiang @ 2007-05-30  0:56 UTC (permalink / raw)
  To: galak; +Cc: linuxppc-dev, paulus

A reboot notifier handler and a panic notifier handler is added to the BOOKE
watchdog driver in order to address this watchdog in situations of panic calls
and kexec calls. 

The BOOKE watchdog cannot be disabled once it has been enabled. When a panic
handler is called, there's a possibility of a soft reboot or crash_kexec being
called. We need to make sure that the watchdog hardware reset does not happen
during those situations. The watchdog is configured so that it would timeout
after hopefully a reasonable amount of time (roughly 5mins + panic_timeout). 
This way we can proceed with the panic handler. If we hang for some reason 
during panic, the watchdog can still reset eventually.

When kexec happens, the reboot notifier is called. We set the watchdog to the
max value, which is 2^63 TB ticks on FSL BOOKE (or 2^29 on 440). This is the
best we can do to ensure that the watchdog does not go off until the new kernel
is able to re-initialize the watchdog timer.  

Signed-off-by: Dave Jiang <djiang@mvista.com>

---

 booke_wdt.c |  160 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++--
 1 file changed, 157 insertions(+), 3 deletions(-)

diff --git a/drivers/char/watchdog/booke_wdt.c b/drivers/char/watchdog/booke_wdt.c
index 0f5c77d..29e4f03 100644
--- a/drivers/char/watchdog/booke_wdt.c
+++ b/drivers/char/watchdog/booke_wdt.c
@@ -19,10 +19,12 @@
 #include <linux/miscdevice.h>
 #include <linux/notifier.h>
 #include <linux/watchdog.h>
+#include <linux/reboot.h>
 
 #include <asm/reg_booke.h>
 #include <asm/uaccess.h>
 #include <asm/system.h>
+#include <asm/time.h>
 
 /* If the kernel parameter wdt=1, the watchdog will be enabled at boot.
  * Also, the wdt_period sets the watchdog timer period timeout.
@@ -33,18 +35,36 @@
  */
 
 #ifdef	CONFIG_FSL_BOOKE
-#define WDT_PERIOD_DEFAULT 63	/* Ex. wdt_period=28 bus=333Mhz , reset=~40sec */
+/* Ex. wdt_period=28 bus=333Mhz , reset=~40sec */
+#define WDT_PERIOD_MAX		63
 #else
-#define WDT_PERIOD_DEFAULT 3	/* Refer to the PPC40x and PPC4xx manuals */
-#endif				/* for timing information */
+/* 
+ * Refer to the PPC40x and PPC4xx manuals
+ * for timing information 
+ */
+#define WDT_PERIOD_MAX		WP_2_29
+#endif				
+
+#define WDT_PERIOD_DEFAULT	WDT_PERIOD_MAX
 
 u32 booke_wdt_enabled = 0;
 u32 booke_wdt_period = WDT_PERIOD_DEFAULT;
 
 #ifdef	CONFIG_FSL_BOOKE
+
 #define WDTP(x)		((((63-x)&0x3)<<30)|(((63-x)&0x3c)<<15))
+#define WDTP_TO_NUM(x)	(63 - (((x >> 30) & 0x3) | (((x >> 17) & 0xf) << 2)))
+
+#ifdef TCR_WP_MASK
+#undef TCR_WP_MASK
+#define TCR_WP_MASK		WDTP(0)
+#endif
+
 #else
+
 #define WDTP(x)		(TCR_WP(x))
+#define WDTP_TO_NUM(x)		((x >> 30) & 0x3)
+
 #endif
 
 /*
@@ -56,6 +76,127 @@ static __inline__ void booke_wdt_ping(void)
 }
 
 /*
+ * wdog_reboot_handler:
+ */
+static int wdog_reboot_handler(struct notifier_block *this,
+				unsigned long	code,
+				void		*unused)
+{
+	static int reboot_event_handled = 0;
+	u32 val;
+
+	val = mfspr(SPRN_TCR);
+
+	if ((val & TCR_WRC(WRC_CHIP)) && !reboot_event_handled) {
+		reboot_event_handled = 1;
+
+		/*
+		 * we probably don't want a watchdog reset in the middle
+		 * of soft reboot, halt, or power off
+		 */
+		if ((code == SYS_RESTART) ||
+			(code == SYS_HALT) ||
+			(code == SYS_POWER_OFF)) {
+			/* clear the current time period */
+			val = val & ~TCR_WP_MASK;
+
+			booke_wdt_ping();
+			/* 
+			 * lets bump the timer up to max value to "disable"
+			 * the WDT
+			 */
+			val |= (TCR_WIE | TCR_WRC(WRC_CHIP) | 
+				WDTP(WDT_PERIOD_MAX));
+			mtspr(SPRN_TCR, val);
+		}
+	}
+	return NOTIFY_OK;
+}
+
+static struct notifier_block wdog_reboot_notifier = {
+	.notifier_call	= wdog_reboot_handler,
+	.next		= NULL,
+	.priority	= 0
+};
+
+/*
+ * the function takes timeout in seconds. 
+ * it looks at the timeout periods provided by the watchdog and matches
+ * to the next longest period
+ */
+#ifdef	CONFIG_FSL_BOOKE
+static int booke_wdt_match_period(int timeout)
+{
+	int i;
+	u64 val;
+
+	for (i=0; i < WDT_PERIOD_MAX; i++) {
+		val = 1ULL << i;
+		__div64_32(&val, tb_ticks_per_sec);
+		if(val >= timeout)
+			return i;
+	}
+
+	return WDT_PERIOD_MAX;
+}
+#else
+static int booke_wdt_match_period(int timeout)
+{
+	int i;
+	u32 val;
+
+	if (((1UL << 17) / tb_ticks_per_sec) >= timeout)
+		return WP_2_17;
+
+	if (((1UL << 21) / tb_ticks_per_sec) >= timeout)
+		return WP_2_21;
+
+	if (((1UL << 25) / tb_ticks_per_sec) >= timeout)
+		return WP_2_25;
+
+	return WP_2_29;
+}
+#endif	/* CONFIG_FSL_BOOKE */
+
+/*
+ * wdog_panic_handler:
+ */
+static int wdog_panic_handler(struct notifier_block *this,
+				unsigned long	event,
+				void		*unused)
+{
+	static int panic_event_handled = 0;
+	u32 val;
+
+	val = mfspr(SPRN_TCR);
+
+	if ((val & TCR_WRC(WRC_CHIP)) && !panic_event_handled) {
+		panic_event_handled = 1;
+
+		/* clear the current time period */
+		val = val & ~TCR_WP_MASK;
+
+		booke_wdt_ping();
+		/* 
+		 * lets bump the timer up to ~5 mins plus panic_timeout 
+		 * to allow us to complete the panic and allow new kernel
+		 * to boot
+		 */
+		val |= (TCR_WIE | TCR_WRC(WRC_CHIP) |
+			WDTP(booke_wdt_match_period(300+panic_timeout)));
+		mtspr(SPRN_TCR, val);
+	}
+
+	return NOTIFY_OK;
+}
+
+static struct notifier_block wdog_panic_notifier = {
+	.notifier_call	= wdog_panic_handler,
+	.next		= NULL,
+	.priority	= 150
+};
+
+/*
  * booke_wdt_enable:
  */
 static __inline__ void booke_wdt_enable(void)
@@ -164,6 +305,9 @@ static struct miscdevice booke_wdt_miscdev = {
 static void __exit booke_wdt_exit(void)
 {
 	misc_deregister(&booke_wdt_miscdev);
+	atomic_notifier_chain_unregister(&panic_notifier_list,
+					&wdog_panic_notifier);
+	unregister_reboot_notifier(&wdog_reboot_notifier);
 }
 
 /*
@@ -172,6 +316,7 @@ static void __exit booke_wdt_exit(void)
 static int __init booke_wdt_init(void)
 {
 	int ret = 0;
+	u32 val;
 
 	printk (KERN_INFO "PowerPC Book-E Watchdog Timer Loaded\n");
 	ident.firmware_version = cur_cpu_spec->pvr_value;
@@ -188,6 +333,15 @@ static int __init booke_wdt_init(void)
 				booke_wdt_period);
 		booke_wdt_enable();
 	}
+	else {
+		val = mfspr(SPRN_TCR);
+		if (val & TCR_WRC(WRC_CHIP))
+			printk (KERN_WARNING "PowerPC Book-E Watchdog Timer previously Enabled (wdt_period=%d)\n", WDTP_TO_NUM(val));
+	}
+
+	register_reboot_notifier(&wdog_reboot_notifier);
+	atomic_notifier_chain_register(&panic_notifier_list,
+					&wdog_panic_notifier);
 
 	return ret;
 }

^ permalink raw reply related

* Re: [RFC/PATCH 4/5] powerpc: Make syscall restart code more common
From: Stephen Rothwell @ 2007-05-30  0:53 UTC (permalink / raw)
  To: Benjamin Herrenschmidt
  Cc: linuxppc-dev, ulrich.weigand, Paul Mackerras, Christoph Hellwig,
	Anton Blanchard
In-Reply-To: <1180438885.19517.157.camel@localhost.localdomain>

[-- Attachment #1: Type: text/plain, Size: 515 bytes --]

On Tue, 29 May 2007 21:41:25 +1000 Benjamin Herrenschmidt <benh@kernel.crashing.org> wrote:
>
> I've been thinking about doing that too. In fact, some of the
> ptrace-common.h stuff should probably be turned back into ptrace.c too
> for the same reason. I'm still toying with that part of the designm but
> yeah, I think that's something to do.

Yeah, I think having ptrace{,_32,_64}.c makes more sense as well.

--
Cheers,
Stephen Rothwell                    sfr@canb.auug.org.au
http://www.canb.auug.org.au/~sfr/

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^ permalink raw reply

* [PATCH/RFC 1/2] powerpc: BOOKE watchdog handler dump additional info
From: Dave Jiang @ 2007-05-30  0:53 UTC (permalink / raw)
  To: galak; +Cc: linuxppc-dev, paulus

Have the watchdog handler to call die(). This allows some system information
such as registers, stack dump, and etc to be displayed. The die() handler
should handle the situation appropriately (i.e. kill process, call panic, 
or call crash_kexec)

The follow on patch will address any issues in regards to watchdog following the
call of panic. 

We have to keep the watchdog interrupt enabled because die() can just kill a
process and return the system to a running state instead of panic(). 
This will allow us to catch any new watchdog timeout exceptions if the system 
hangs again.

Signed-off-by: Dave Jiang <djiang@mvista.com>

---

 traps.c |    3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c
index bf6445a..837f742 100644
--- a/arch/powerpc/kernel/traps.c
+++ b/arch/powerpc/kernel/traps.c
@@ -1095,8 +1095,7 @@ void unrecoverable_exception(struct pt_regs *regs)
 void __attribute__ ((weak)) WatchdogHandler(struct pt_regs *regs)
 {
 	/* Generic WatchdogHandler, implement your own */
-	mtspr(SPRN_TCR, mfspr(SPRN_TCR)&(~TCR_WIE));
-	return;
+	die("PowerPC Book-E Watchdog Exception", regs, SIGSEGV);
 }
 
 void WatchdogException(struct pt_regs *regs)

^ permalink raw reply related

* Re: Saving to 32 bits of GPRs in signal context
From: Kumar Gala @ 2007-05-30  0:43 UTC (permalink / raw)
  To: Olof Johansson
  Cc: Ulrich Weigand, Steve Munroe, linuxppc-dev list, Paul Mackerras,
	Anton Blanchard
In-Reply-To: <20070529234655.GA32367@lixom.net>


On May 29, 2007, at 6:46 PM, Olof Johansson wrote:

> On Wed, May 30, 2007 at 07:32:33AM +1000, Benjamin Herrenschmidt  
> wrote:
>> On Tue, 2007-05-29 at 08:10 -0500, Kumar Gala wrote:
>>> This is all problematic since some 64-bit implementations may not
>>> guarantee the upper bits are valid when in 32-bit mode.  Look at the
>>> 'Computation Modes' section in the architecture specs 2.03 or
>>> greater
>>> for embedded processors.
>>
>> Yuck. Well, we might need to export a spearate CPU feature bit to
>> indicate that it's the case then.
>
> No need for a new bit, you should be able to key off of PPC_FEATURE_64
> && !PPC_FEATURE_BOOKE.

Nope, the architecture allows embedded to behave like server parts  
and support the full 64-bit registers.  We really should have a new  
feature bit so that if someone has an implementation of an embedded  
part that supports the functionality, they get the benefit.

- k

^ permalink raw reply

* Re: [PATCH] fix compile warning in pseries xics
From: Michael Ellerman @ 2007-05-30  0:28 UTC (permalink / raw)
  To: Olof Johansson; +Cc: linuxppc-dev, Michael Neuling, paulus
In-Reply-To: <20070529142715.GA29108@lixom.net>

[-- Attachment #1: Type: text/plain, Size: 1380 bytes --]

On Tue, 2007-05-29 at 09:27 -0500, Olof Johansson wrote:
> On Tue, May 29, 2007 at 05:01:52PM +1000, Michael Neuling wrote:
> > @@ -762,11 +763,12 @@ void xics_request_IPIs(void)
> >  	 */
> >  	set_irq_handler(ipi, handle_percpu_irq);
> >  	if (firmware_has_feature(FW_FEATURE_LPAR))
> > -		request_irq(ipi, xics_ipi_action_lpar, IRQF_DISABLED,
> > -			    "IPI", NULL);
> > +		rc = request_irq(ipi, xics_ipi_action_lpar, IRQF_DISABLED,
> > +				"IPI", NULL);
> >  	else
> > -		request_irq(ipi, xics_ipi_action_direct, IRQF_DISABLED,
> > -			    "IPI", NULL);
> > +		rc = request_irq(ipi, xics_ipi_action_direct, IRQF_DISABLED,
> > +				"IPI", NULL);
> > +	BUG_ON(rc);
> 
> Is this late enough during boot that you actually get useful information
> out of a BUG()?  It might be better to spit out an error and keep on
> going if that's the case (I'm afraid I don't have hardware at hand to
> test with right now).

It's way late:

start_kernel()
  rest_init()
    kernel_init()
      smp_prepare_cpus()
        smp_ops->probe()
          smp_xics_probe()
            xics_request_IPIs()

cheers

-- 
Michael Ellerman
OzLabs, IBM Australia Development Lab

wwweb: http://michael.ellerman.id.au
phone: +61 2 6212 1183 (tie line 70 21183)

We do not inherit the earth from our ancestors,
we borrow it from our children. - S.M.A.R.T Person

[-- Attachment #2: This is a digitally signed message part --]
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^ permalink raw reply

* Re: Saving to 32 bits of GPRs in signal context
From: Olof Johansson @ 2007-05-29 23:46 UTC (permalink / raw)
  To: Benjamin Herrenschmidt
  Cc: Ulrich Weigand, Steve Munroe, linuxppc-dev list, Paul Mackerras,
	Anton Blanchard
In-Reply-To: <1180474353.19517.190.camel@localhost.localdomain>

On Wed, May 30, 2007 at 07:32:33AM +1000, Benjamin Herrenschmidt wrote:
> On Tue, 2007-05-29 at 08:10 -0500, Kumar Gala wrote:
> > This is all problematic since some 64-bit implementations may not  
> > guarantee the upper bits are valid when in 32-bit mode.  Look at the  
> > 'Computation Modes' section in the architecture specs 2.03 or
> > greater  
> > for embedded processors. 
> 
> Yuck. Well, we might need to export a spearate CPU feature bit to
> indicate that it's the case then.

No need for a new bit, you should be able to key off of PPC_FEATURE_64
&& !PPC_FEATURE_BOOKE.


-Olof

^ permalink raw reply


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