* Re: [RFC/PATCH 4/4] Add support for MSI on Axon-based Cell systems
From: Segher Boessenkool @ 2007-06-08 20:06 UTC (permalink / raw)
To: Arnd Bergmann; +Cc: linuxppc-dev
In-Reply-To: <200706082201.26308.arnd@arndb.de>
>> That wasn't my question though?
>
> Sorry, I misread this. The of_node_get is done because we keep
> a reference to the device node in the axon_msic struct. There is
> no module_exit function in the driver that could clean up the
> axon_msic, so we must never have an of_node_put as far as I
> understand.
>>>>>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 if =
(axon_msi_setup_one(of_node_get(node)) =3D=3D 0)
>>>>>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 found++;
What if axon_msi_setup_one() returns an error? Sounds
to me like the get() should be inside that function no
matter what?
If the reference counting isn't obvious, it is obviously
wrong ;-)
Segher
^ permalink raw reply
* Re: [RFC/PATCH 4/4] Add support for MSI on Axon-based Cell systems
From: Arnd Bergmann @ 2007-06-08 20:01 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <65a522813f1b95748a3acc0c05e0285c@kernel.crashing.org>
On Friday 08 June 2007, Segher Boessenkool wrote:
> >> So where is the of_node_put() done for the of_node_get()
> >> inside the loop?
> >
> > of_find_compatible_node does an of_node_put() on the device_node
> > that you pass in as the 'from' argument. In the last step, 'node'
> > is set to NULL and we put the previous element.
>
> That wasn't my question though?
Sorry, I misread this. The of_node_get is done because we keep
a reference to the device node in the axon_msic struct. There is
no module_exit function in the driver that could clean up the
axon_msic, so we must never have an of_node_put as far as I
understand.
Arnd <><
^ permalink raw reply
* Re: [RFC/PATCH 4/4] Add support for MSI on Axon-based Cell systems
From: Segher Boessenkool @ 2007-06-08 19:59 UTC (permalink / raw)
To: Segher Boessenkool; +Cc: linuxppc-dev, Arnd Bergmann
In-Reply-To: <65a522813f1b95748a3acc0c05e0285c@kernel.crashing.org>
>>>>>> + =A0 =A0 =A0 for_each_compatible_node(node, NULL, =
"ibm,axon-msic") {
>>>>>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 if =
(axon_msi_setup_one(of_node_get(node)) =3D=3D 0)
>>>>>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 found++;
>>>>>> + =A0 =A0 =A0 }
>>>>>> + =A0 =A0 =A0 of_node_put(node);
>>>
>>> So where is the of_node_put() done for the of_node_get()
>>> inside the loop?
>>
>> of_find_compatible_node does an of_node_put() on the device_node
>> that you pass in as the 'from' argument. In the last step, 'node'
>> is set to NULL and we put the previous element.
>
> That wasn't my question though?
Oh wait. You're saying for_each_compatible_node() does
a put() on all nodes it traverses, but no get()? Ouch!
Segher
^ permalink raw reply
* Re: [RFC/PATCH 4/4] Add support for MSI on Axon-based Cell systems
From: Segher Boessenkool @ 2007-06-08 19:36 UTC (permalink / raw)
To: Arnd Bergmann; +Cc: linuxppc-dev
In-Reply-To: <200706082126.23435.arnd@arndb.de>
>>>>> + =A0 =A0 =A0 for_each_compatible_node(node, NULL, =
"ibm,axon-msic") {
>>>>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 if =
(axon_msi_setup_one(of_node_get(node)) =3D=3D 0)
>>>>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 found++;
>>>>> + =A0 =A0 =A0 }
>>>>> + =A0 =A0 =A0 of_node_put(node);
>>
>> So where is the of_node_put() done for the of_node_get()
>> inside the loop?
>
> of_find_compatible_node does an of_node_put() on the device_node
> that you pass in as the 'from' argument. In the last step, 'node'
> is set to NULL and we put the previous element.
That wasn't my question though?
Segher
^ permalink raw reply
* Re: [PATCH 1/3] [PATCH i386] during VM oom condition, kill all threads in process group
From: Andrew Morton @ 2007-06-08 19:32 UTC (permalink / raw)
To: will_schmidt
Cc: linuxppc-dev, Eric W. Biederman, Oleg Nesterov, Anton Blanchard,
linux-kernel
In-Reply-To: <1181330358.21409.31.camel@farscape.rchland.ibm.com>
On Fri, 08 Jun 2007 14:19:18 -0500
Will Schmidt <will_schmidt@vnet.ibm.com> wrote:
> > > > zap_other_threads() requires tasklist_lock.
>
> Yup, I missed that. Thanks for pointing it out.
>
> > > >
> > > > If we're going to do this then we should probably create some new function
> > > > (with a better name) which takes tasklsit_lock and then calls
> > > > zap_other_threads().
>
> I expect this will be a write_lock_irq() since zap_other_threads will be
> doing a bit more than just reading the task info.
No, I think read_lock() will be sufficient.
In fact, it's probably the case that rcu_read_lock() is now sufficient
locking coverage for zap_other_threads() (cc's people).
It had better be, because do_group_exit() forgot to take tasklist_lock. It
is perhaps relying upon spin_lock()'s hidden rcu_read_lock() properties
without so much as a code comment, which would be somewhat nasty of it.
You could perhaps just call do_group_exit() from within the fault handler,
btw.
> This will be down in a do-page-fault failure path (see
> arch/*/mm/fault.c). I wonder if calling write_lock is going to be safe,
> or if its possible to get into a deadlock? i.e. should I branch back up
> to the survive: label if I can't take the lock? Would that even be
> sufficient? or is it not an issue here?
You can take the lock in the fault handler. Nobody should be getting
pagefaults while holding tasklist_lock. (Well, a vmalloc fault might, but
that's a special-case which doesn't allocate memory or anything like that).
^ permalink raw reply
* Re: [RFC/PATCH 4/4] Add support for MSI on Axon-based Cell systems
From: Arnd Bergmann @ 2007-06-08 19:26 UTC (permalink / raw)
To: Segher Boessenkool; +Cc: linuxppc-dev
In-Reply-To: <cc1d6d368ded181bbbdad8e4f4cb37ae@kernel.crashing.org>
On Friday 08 June 2007, Segher Boessenkool wrote:
> >>> + =A0 =A0 =A0 for_each_compatible_node(node, NULL, "ibm,axon-msic") {
> >>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 if (axon_msi_setup_one(of_node_get(node=
)) =3D=3D 0)
> >>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 found++;
> >>> + =A0 =A0 =A0 }
> >>> + =A0 =A0 =A0 of_node_put(node);
>=20
> So where is the of_node_put() done for the of_node_get()
> inside the loop?
of_find_compatible_node does an of_node_put() on the device_node
that you pass in as the 'from' argument. In the last step, 'node'
is set to NULL and we put the previous element.
Arnd <><
^ permalink raw reply
* Re: [PATCH 1/3] [PATCH i386] during VM oom condition, kill all threads in process group
From: Will Schmidt @ 2007-06-08 19:19 UTC (permalink / raw)
To: Andrew Morton; +Cc: linuxppc-dev, Anton Blanchard, linux-kernel
In-Reply-To: <20070607171018.d51fc5da.akpm@linux-foundation.org>
On Thu, 2007-06-07 at 17:10 -0700, Andrew Morton wrote:
> On Thu, 7 Jun 2007 18:16:21 -0500
> Anton Blanchard <anton@samba.org> wrote:
>
> >
> > Hi,
> >
> > > zap_other_threads() requires tasklist_lock.
Yup, I missed that. Thanks for pointing it out.
> > >
> > > If we're going to do this then we should probably create some new function
> > > (with a better name) which takes tasklsit_lock and then calls
> > > zap_other_threads().
I expect this will be a write_lock_irq() since zap_other_threads will be
doing a bit more than just reading the task info.
This will be down in a do-page-fault failure path (see
arch/*/mm/fault.c). I wonder if calling write_lock is going to be safe,
or if its possible to get into a deadlock? i.e. should I branch back up
to the survive: label if I can't take the lock? Would that even be
sufficient? or is it not an issue here?
> > >
> > > Does this patch fix any observed-in-the-real-world problem? If so, please
> > > describe it.
> >
> > Yeah we have had complaints where threaded apps have only one thread
> > shot down instead of the entire process. This leaves the application in
> > a bad state, whereas if it had been killed cleanly the application could
> > have restarted.
> >
> > My understanding is that fatal signals should kill all threads in the
> > group.
> >
>
> OK, well could we please get all that info appropriatelt captured in #2's
> changelog?
Yup, next spin I'll add more to the changelog.
>
> Other architectures will probably need to implement this.
-Will
^ permalink raw reply
* Re: [PATCH] powerpc: Add Marvell mv64x60 udbg putc/getc functions
From: Dale Farnsworth @ 2007-06-08 17:20 UTC (permalink / raw)
To: Michael Ellerman; +Cc: linuxppc-dev, Paul Mackerras
In-Reply-To: <1181268915.6026.5.camel@concordia.ozlabs.ibm.com>
On Fri, Jun 08, 2007 at 12:15:15PM +1000, Michael Ellerman wrote:
> On Wed, 2007-06-06 at 10:29 -0700, Dale Farnsworth wrote:
> > On Wed, Jun 06, 2007 at 04:06:05PM +1000, Paul Mackerras wrote:
> > > Dale Farnsworth writes:
> > >
> > > > Paul, this patch is unchanged from the one I posted 10 days ago.
> > > > At that time, I saw no discussion, other than Mark's ACK. I'd
> > > > argue that this is a bugfix, and hope that it could go into 2.6.22.
> > >
> > > Um, it seems rather large, and in particular adds a fair bit of
> > > completely new code. Is there a simpler way of getting to an
> > > acceptable point - e.g. just not use the udbg console on these boards?
> >
> > Yeah, that was the first approach I took. Unfortunately, currently the
> > udbg console is included unconditionally on arch/powerpc. I created the
> > patch below to conditionalize the use of udbg console. I thought it a
> > bit risky for 2.6.22, but I think it's the right approach long term.
> >
> > > If we don't have udbg support for them then the udbg console would
> > > seem a bit pointless, no?
> >
> > There is value in that with the udbg console we do see console output
> > much earlier. While there's some new code (I didn't think it was all
> > that much), the impact is limited to the single platform now using the
> > mv64x60 console port, the prpmc2800.
>
> You don't select PPC_UDBG for any of the cell platforms, which AFAICT
> means you'll break early debugging on those.
Actually, I do select PPC_UDBG for PPC_IBM_CELL_BLADE (via
PPC_UDBG_16550) and for PPC_CELLEB (via PPC_UDBG_BEAT). I couldn't
figure out which console PPC_PS3 uses, but that support is noted as
incomplete, so I didn't spend much time researching it.
Still, it's difficult to be sure I caught them all; that's why I
decided to defer the patch until the next merge window.
> I think you should be able to do this in terms of
> CONFIG_PPC_EARLY_DEBUG, which already exists.
Nope. Many platforms use the udbg console early on without enabling
CONFIG_PPC_EARLY_DEBUG.
-Dale
^ permalink raw reply
* RE: [PATCH] Fix drivers/rtc/Kconfig for powerpc
From: Loeliger Jon-LOELIGER @ 2007-06-08 14:14 UTC (permalink / raw)
To: David Gibson; +Cc: a.zummo, rtc-linux, linuxppc-dev
In-Reply-To: <20070607233431.GA17298@localhost.localdomain>
>=20
> Sure. This patch is so simple though, I think it could go straight to
> Andrew Morton.
That was one of my suggestions! :-)
jdl
^ permalink raw reply
* Re: a question on "iowrite32()"
From: Ming Liu @ 2007-06-08 13:51 UTC (permalink / raw)
To: arnd; +Cc: domen.puncer, linuxppc-embedded
In-Reply-To: <200706071609.19399.arnd@arndb.de>
Dear Arnd,
I have turned to use out_be32. My system works quite well now. Thanks for
your suggestions. :)
BR
Ming
>From: Arnd Bergmann <arnd@arndb.de>
>To: "Ming Liu" <eemingliu@hotmail.com>
>CC: domen.puncer@telargo.com, linuxppc-embedded@ozlabs.org
>Subject: Re: a question on "iowrite32()"
>Date: Thu, 7 Jun 2007 16:09:18 +0200
>
>On Thursday 07 June 2007, Ming Liu wrote:
> > >Since of_iomap() is rather new and hardly used by any drivers, we
> > >could still redefine it so that you would use iowrite32{,be}() instead
> > >of out_{be,le}32, but currently that doesn't work.
> >
> > So if I am correct, your suggestion is to use iowrite32be() in my
device
> > driver, right?
>
>What I was saying is that iowrite32be is broken for other reasons, as it
>is only defined for PCI and ISA devices and you should _not_ use it,
>even if it solves the endianess problem.
>
>What you should use is out_be32().
>
> > However, I cannot find such a function defined in my 2.6.10 kernel.
> > Isn't iowrite32be() a standard IO function like iowrite32(), or there
is
> > a patch to export this function?
>
>It's a standard function, is was added less than two years ago.
>You should really consider upgrading to a recent kernel version for
>a number of reasons, but they are all unrelated to your current problem
;-)
>
> Arnd <><
_________________________________________________________________
享用世界上最大的电子邮件系统― MSN Hotmail。 http://www.hotmail.com
^ permalink raw reply
* Re: [PATCH 4/6] 82xx: Add the support of Wind River SBC PowerQUICCII 82xx
From: Kumar Gala @ 2007-06-08 12:45 UTC (permalink / raw)
To: Mark Zhan; +Cc: linuxppc-dev@ozlabs.org, paulus@samba.org
In-Reply-To: <1181292962.11341.17.camel@mark>
On Jun 8, 2007, at 3:56 AM, Mark Zhan wrote:
> Add the support of ST M48T59 RTC chip driver for SBC PowerQUICCII 82xx
> board
Again, this should via got the RTC subsystem maintainer.
- k
^ permalink raw reply
* Re: [PATCH 1/6] 82xx: Add the support of Wind River SBC PowerQUICCII 82xx
From: Kumar Gala @ 2007-06-08 12:43 UTC (permalink / raw)
To: Mark Zhan; +Cc: linuxppc-dev@ozlabs.org, paulus@samba.org
In-Reply-To: <1181292534.11341.9.camel@mark>
On Jun 8, 2007, at 3:48 AM, Mark Zhan wrote:
> Current MII bitbang bus driver hard-codes the phy mask of mii_bus to
> ~0x09, which is actually specific for the FSL boards. This patch will
> make the bitbang driver to generate MII bus phy_mask dynamically.
Your patch subject's should be unique in a patch series, they all
shouldn't be 'add support for ...'
Also, this patch should be going via netdev and probably CC'd to
Vitaly Bordug.
- k
^ permalink raw reply
* [PATCH 2/6] 82xx: Add the support of Wind River SBC PowerQUICCII 82xx
From: Mark Zhan @ 2007-06-08 8:51 UTC (permalink / raw)
To: paulus@samba.org; +Cc: linuxppc-dev@ozlabs.org
Make some common mpc82xx platform hook functions be shared by different
82xx boards.
Signed-off-by: Mark Zhan <rongkai.zhan@windriver.com>
---
b/arch/powerpc/platforms/82xx/mpc82xx.c | 28 +++++++++++++++++---
b/arch/powerpc/platforms/82xx/mpc82xx_ads.c | 38
++++++----------------------
b/arch/powerpc/platforms/82xx/pq2ads.h | 2 -
b/include/asm-powerpc/mpc8260.h | 5 +++
4 files changed, 38 insertions(+), 35 deletions(-)
diff --git a/arch/powerpc/platforms/82xx/mpc82xx.c
b/arch/powerpc/platforms/82xx/mpc82xx.c
index cc9900d..0623c54 100644
--- a/arch/powerpc/platforms/82xx/mpc82xx.c
+++ b/arch/powerpc/platforms/82xx/mpc82xx.c
@@ -50,8 +50,6 @@ #include <linux/fs_enet_pd.h>
#include <sysdev/fsl_soc.h>
#include <sysdev/cpm2_pic.h>
-#include "pq2ads.h"
-
static int __init get_freq(char *name, unsigned long *val)
{
struct device_node *cpu;
@@ -74,7 +72,7 @@ static int __init get_freq(char *name, u
return found;
}
-void __init m82xx_calibrate_decr(void)
+void __init mpc82xx_calibrate_decr(void)
{
ppc_tb_freq = 125000000;
if (!get_freq("bus-frequency", &ppc_tb_freq)) {
@@ -88,7 +86,7 @@ void __init m82xx_calibrate_decr(void)
"(not found)\n");
}
-void mpc82xx_ads_show_cpuinfo(struct seq_file *m)
+void mpc82xx_show_cpuinfo(struct seq_file *m)
{
uint pvid, svid, phid1;
uint memsize = total_memory;
@@ -108,3 +106,25 @@ void mpc82xx_ads_show_cpuinfo(struct seq
/* Display the amount of memory */
seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
}
+
+#define RMR_CSRE 0x00000001
+
+void mpc82xx_restart(char *cmd)
+{
+ __volatile__ unsigned char dummy;
+
+ local_irq_disable();
+ ((cpm2_map_t *) cpm2_immr)->im_clkrst.car_rmr |= RMR_CSRE;
+
+ /* Clear the ME,EE,IR & DR bits in MSR to cause checkstop */
+ mtmsr(mfmsr() & ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR));
+ dummy = ((cpm2_map_t *) cpm2_immr)->im_clkrst.res[0];
+ printk("Restart failed\n");
+ while (1) ;
+}
+
+void mpc82xx_halt(void)
+{
+ local_irq_disable();
+ while (1) ;
+}
diff --git a/arch/powerpc/platforms/82xx/mpc82xx_ads.c
b/arch/powerpc/platforms/82xx/mpc82xx_ads.c
index 47cb09f..4fec1ce 100644
--- a/arch/powerpc/platforms/82xx/mpc82xx_ads.c
+++ b/arch/powerpc/platforms/82xx/mpc82xx_ads.c
@@ -611,35 +611,15 @@ static int __init mpc82xx_ads_probe(void
return 1;
}
-#define RMR_CSRE 0x00000001
-static void m82xx_restart(char *cmd)
-{
- __volatile__ unsigned char dummy;
-
- local_irq_disable();
- ((cpm2_map_t *) cpm2_immr)->im_clkrst.car_rmr |= RMR_CSRE;
-
- /* Clear the ME,EE,IR & DR bits in MSR to cause checkstop */
- mtmsr(mfmsr() & ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR));
- dummy = ((cpm2_map_t *) cpm2_immr)->im_clkrst.res[0];
- printk("Restart failed\n");
- while (1) ;
-}
-
-static void m82xx_halt(void)
-{
- local_irq_disable();
- while (1) ;
-}
-
define_machine(mpc82xx_ads)
{
- .name = "MPC82xx ADS",
- .probe = mpc82xx_ads_probe,
- .setup_arch = mpc82xx_ads_setup_arch,
- .init_IRQ = mpc82xx_ads_pic_init,
- .show_cpuinfo = mpc82xx_ads_show_cpuinfo,
- .get_irq = cpm2_get_irq,
- .calibrate_decr = m82xx_calibrate_decr,
- .restart = m82xx_restart,.halt = m82xx_halt,
+ .name = "MPC82xx ADS",
+ .probe = mpc82xx_ads_probe,
+ .setup_arch = mpc82xx_ads_setup_arch,
+ .init_IRQ = mpc82xx_ads_pic_init,
+ .show_cpuinfo = mpc82xx_show_cpuinfo,
+ .get_irq = cpm2_get_irq,
+ .calibrate_decr = mpc82xx_calibrate_decr,
+ .restart = mpc82xx_restart,
+ .halt = mpc82xx_halt,
};
diff --git a/arch/powerpc/platforms/82xx/pq2ads.h
b/arch/powerpc/platforms/82xx/pq2ads.h
index 5b5cca6..d83def1 100644
--- a/arch/powerpc/platforms/82xx/pq2ads.h
+++ b/arch/powerpc/platforms/82xx/pq2ads.h
@@ -59,8 +59,6 @@ #define SIU_INT_SCC3 ((uint)0x2a+CPM_IR
#define SIU_INT_SCC4 ((uint)0x2b+CPM_IRQ_OFFSET)
void m82xx_pci_init_irq(void);
-void mpc82xx_ads_show_cpuinfo(struct seq_file*);
-void m82xx_calibrate_decr(void);
#endif /* __MACH_ADS8260_DEFS */
#endif /* __KERNEL__ */
diff --git a/include/asm-powerpc/mpc8260.h
b/include/asm-powerpc/mpc8260.h
index e0d4807..e058e9e 100644
--- a/include/asm-powerpc/mpc8260.h
+++ b/include/asm-powerpc/mpc8260.h
@@ -19,6 +19,11 @@ #ifdef CONFIG_PCI_8260
#include <platforms/82xx/m82xx_pci.h>
#endif
+extern void mpc82xx_show_cpuinfo(struct seq_file *);
+extern void mpc82xx_calibrate_decr(void);
+extern void mpc82xx_restart(char *cmd);
+extern void mpc82xx_halt(void);
+
#endif /* CONFIG_8260 */
#endif /* !__ASM_POWERPC_MPC8260_H__ */
#endif /* __KERNEL__ */
^ permalink raw reply related
* [PATCH 1/6] 82xx: Add the support of Wind River SBC PowerQUICCII 82xx
From: Mark Zhan @ 2007-06-08 8:48 UTC (permalink / raw)
To: paulus@samba.org; +Cc: linuxppc-dev@ozlabs.org
Current MII bitbang bus driver hard-codes the phy mask of mii_bus to
~0x09, which is actually specific for the FSL boards. This patch will
make the bitbang driver to generate MII bus phy_mask dynamically.
Signed-off-by: Mark Zhan <rongkai.zhan@windriver.com>
---
b/drivers/net/fs_enet/mii-bitbang.c | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/net/fs_enet/mii-bitbang.c
b/drivers/net/fs_enet/mii-bitbang.c
index d384010..3732d69 100644
--- a/drivers/net/fs_enet/mii-bitbang.c
+++ b/drivers/net/fs_enet/mii-bitbang.c
@@ -315,7 +315,7 @@ static int __devinit fs_enet_mdio_probe(
struct fs_mii_bb_platform_info *pdata;
struct mii_bus *new_bus;
struct bb_info *bitbang;
- int err = 0;
+ int i, err = 0;
if (NULL == dev)
return -EINVAL;
@@ -336,14 +336,17 @@ static int __devinit fs_enet_mdio_probe(
new_bus->reset = &fs_enet_mii_bb_reset,
new_bus->id = pdev->id;
- new_bus->phy_mask = ~0x9;
pdata = (struct fs_mii_bb_platform_info *)pdev->dev.platform_data;
-
if (NULL == pdata) {
printk(KERN_ERR "gfar mdio %d: Missing platform data!\n", pdev->id);
return -ENODEV;
}
+ new_bus->phy_mask = 0xFFFFFFFF;
+ for (i = 0; i < PHY_MAX_ADDR; i++)
+ if (pdata->irq[i] != -1)
+ new_bus->phy_mask &= ~(1 << i);
+
/*set up workspace*/
fs_mii_bitbang_init(bitbang, pdata);
^ permalink raw reply related
* [PATCH 2/6] 82xx: Add the support of Wind River SBC PowerQUICCII 82xx
From: Mark Zhan @ 2007-06-08 12:19 UTC (permalink / raw)
To: paulus@samba.org; +Cc: linuxppc-dev@ozlabs.org
Make some common mpc82xx platform hook functions be shared by different
82xx boards.
Signed-off-by: Mark Zhan <rongkai.zhan@windriver.com>
---
b/arch/powerpc/platforms/82xx/mpc82xx.c | 28 +++++++++++++++++---
b/arch/powerpc/platforms/82xx/mpc82xx_ads.c | 38
++++++----------------------
b/arch/powerpc/platforms/82xx/pq2ads.h | 2 -
b/include/asm-powerpc/mpc8260.h | 5 +++
4 files changed, 38 insertions(+), 35 deletions(-)
diff --git a/arch/powerpc/platforms/82xx/mpc82xx.c
b/arch/powerpc/platforms/82xx/mpc82xx.c
index cc9900d..0623c54 100644
--- a/arch/powerpc/platforms/82xx/mpc82xx.c
+++ b/arch/powerpc/platforms/82xx/mpc82xx.c
@@ -50,8 +50,6 @@ #include <linux/fs_enet_pd.h>
#include <sysdev/fsl_soc.h>
#include <sysdev/cpm2_pic.h>
-#include "pq2ads.h"
-
static int __init get_freq(char *name, unsigned long *val)
{
struct device_node *cpu;
@@ -74,7 +72,7 @@ static int __init get_freq(char *name, u
return found;
}
-void __init m82xx_calibrate_decr(void)
+void __init mpc82xx_calibrate_decr(void)
{
ppc_tb_freq = 125000000;
if (!get_freq("bus-frequency", &ppc_tb_freq)) {
@@ -88,7 +86,7 @@ void __init m82xx_calibrate_decr(void)
"(not found)\n");
}
-void mpc82xx_ads_show_cpuinfo(struct seq_file *m)
+void mpc82xx_show_cpuinfo(struct seq_file *m)
{
uint pvid, svid, phid1;
uint memsize = total_memory;
@@ -108,3 +106,25 @@ void mpc82xx_ads_show_cpuinfo(struct seq
/* Display the amount of memory */
seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
}
+
+#define RMR_CSRE 0x00000001
+
+void mpc82xx_restart(char *cmd)
+{
+ __volatile__ unsigned char dummy;
+
+ local_irq_disable();
+ ((cpm2_map_t *) cpm2_immr)->im_clkrst.car_rmr |= RMR_CSRE;
+
+ /* Clear the ME,EE,IR & DR bits in MSR to cause checkstop */
+ mtmsr(mfmsr() & ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR));
+ dummy = ((cpm2_map_t *) cpm2_immr)->im_clkrst.res[0];
+ printk("Restart failed\n");
+ while (1) ;
+}
+
+void mpc82xx_halt(void)
+{
+ local_irq_disable();
+ while (1) ;
+}
diff --git a/arch/powerpc/platforms/82xx/mpc82xx_ads.c
b/arch/powerpc/platforms/82xx/mpc82xx_ads.c
index 47cb09f..4fec1ce 100644
--- a/arch/powerpc/platforms/82xx/mpc82xx_ads.c
+++ b/arch/powerpc/platforms/82xx/mpc82xx_ads.c
@@ -611,35 +611,15 @@ static int __init mpc82xx_ads_probe(void
return 1;
}
-#define RMR_CSRE 0x00000001
-static void m82xx_restart(char *cmd)
-{
- __volatile__ unsigned char dummy;
-
- local_irq_disable();
- ((cpm2_map_t *) cpm2_immr)->im_clkrst.car_rmr |= RMR_CSRE;
-
- /* Clear the ME,EE,IR & DR bits in MSR to cause checkstop */
- mtmsr(mfmsr() & ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR));
- dummy = ((cpm2_map_t *) cpm2_immr)->im_clkrst.res[0];
- printk("Restart failed\n");
- while (1) ;
-}
-
-static void m82xx_halt(void)
-{
- local_irq_disable();
- while (1) ;
-}
-
define_machine(mpc82xx_ads)
{
- .name = "MPC82xx ADS",
- .probe = mpc82xx_ads_probe,
- .setup_arch = mpc82xx_ads_setup_arch,
- .init_IRQ = mpc82xx_ads_pic_init,
- .show_cpuinfo = mpc82xx_ads_show_cpuinfo,
- .get_irq = cpm2_get_irq,
- .calibrate_decr = m82xx_calibrate_decr,
- .restart = m82xx_restart,.halt = m82xx_halt,
+ .name = "MPC82xx ADS",
+ .probe = mpc82xx_ads_probe,
+ .setup_arch = mpc82xx_ads_setup_arch,
+ .init_IRQ = mpc82xx_ads_pic_init,
+ .show_cpuinfo = mpc82xx_show_cpuinfo,
+ .get_irq = cpm2_get_irq,
+ .calibrate_decr = mpc82xx_calibrate_decr,
+ .restart = mpc82xx_restart,
+ .halt = mpc82xx_halt,
};
diff --git a/arch/powerpc/platforms/82xx/pq2ads.h
b/arch/powerpc/platforms/82xx/pq2ads.h
index 5b5cca6..d83def1 100644
--- a/arch/powerpc/platforms/82xx/pq2ads.h
+++ b/arch/powerpc/platforms/82xx/pq2ads.h
@@ -59,8 +59,6 @@ #define SIU_INT_SCC3 ((uint)0x2a+CPM_IR
#define SIU_INT_SCC4 ((uint)0x2b+CPM_IRQ_OFFSET)
void m82xx_pci_init_irq(void);
-void mpc82xx_ads_show_cpuinfo(struct seq_file*);
-void m82xx_calibrate_decr(void);
#endif /* __MACH_ADS8260_DEFS */
#endif /* __KERNEL__ */
diff --git a/include/asm-powerpc/mpc8260.h
b/include/asm-powerpc/mpc8260.h
index e0d4807..e058e9e 100644
--- a/include/asm-powerpc/mpc8260.h
+++ b/include/asm-powerpc/mpc8260.h
@@ -19,6 +19,11 @@ #ifdef CONFIG_PCI_8260
#include <platforms/82xx/m82xx_pci.h>
#endif
+extern void mpc82xx_show_cpuinfo(struct seq_file *);
+extern void mpc82xx_calibrate_decr(void);
+extern void mpc82xx_restart(char *cmd);
+extern void mpc82xx_halt(void);
+
#endif /* CONFIG_8260 */
#endif /* !__ASM_POWERPC_MPC8260_H__ */
#endif /* __KERNEL__ */
^ permalink raw reply related
* [PATCH 1/6] 82xx: Add the support of Wind River SBC PowerQUICCII 82xx
From: Mark Zhan @ 2007-06-08 12:19 UTC (permalink / raw)
To: paulus@samba.org; +Cc: linuxppc-dev@ozlabs.org
Current MII bitbang bus driver hard-codes the phy mask of mii_bus to
~0x09, which is actually specific for the FSL boards. This patch will
make the bitbang driver to generate MII bus phy_mask dynamically.
Signed-off-by: Mark Zhan <rongkai.zhan@windriver.com>
---
b/drivers/net/fs_enet/mii-bitbang.c | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/net/fs_enet/mii-bitbang.c
b/drivers/net/fs_enet/mii-bitbang.c
index d384010..3732d69 100644
--- a/drivers/net/fs_enet/mii-bitbang.c
+++ b/drivers/net/fs_enet/mii-bitbang.c
@@ -315,7 +315,7 @@ static int __devinit fs_enet_mdio_probe(
struct fs_mii_bb_platform_info *pdata;
struct mii_bus *new_bus;
struct bb_info *bitbang;
- int err = 0;
+ int i, err = 0;
if (NULL == dev)
return -EINVAL;
@@ -336,14 +336,17 @@ static int __devinit fs_enet_mdio_probe(
new_bus->reset = &fs_enet_mii_bb_reset,
new_bus->id = pdev->id;
- new_bus->phy_mask = ~0x9;
pdata = (struct fs_mii_bb_platform_info *)pdev->dev.platform_data;
-
if (NULL == pdata) {
printk(KERN_ERR "gfar mdio %d: Missing platform data!\n", pdev->id);
return -ENODEV;
}
+ new_bus->phy_mask = 0xFFFFFFFF;
+ for (i = 0; i < PHY_MAX_ADDR; i++)
+ if (pdata->irq[i] != -1)
+ new_bus->phy_mask &= ~(1 << i);
+
/*set up workspace*/
fs_mii_bitbang_init(bitbang, pdata);
^ permalink raw reply related
* porting problem for MPC860
From: Barisa kisku @ 2007-06-08 10:48 UTC (permalink / raw)
To: linuxppc-dev
Hi,
I am new to embedded system.And i am trying port
linux-2.6.20 in a custom board to learn about
porting and Linux OS.
I have used following version of various codes.
U-Boot : 1.1.6
Linux : 2.6.20
cross-compiler - gcc-4.1.1
System details :
custom board(near to MBX board)
MPC860 processor
4MB Flash
8MB SRAM
Kernel image(uIamge) at moment compiled for default
MBX configuration.
Linux kernel(uImage) is loaded by U-Boot on SRAM.Then
we tried to boot linux using BOOTM command.Then we
tried to see the flow execution by using Emulator.
Following piece of codes is from
arch/ppc/kernel/head_8xx.S file.
--------------------------------------------------
.globl __start
__start:
mr r31,r3 /* save parameters */
mr r30,r4
mr r29,r5
mr r28,r6
mr r27,r7
/* We have to turn on the MMU right away
so we get cache modes
* set correctly.
*/
bl initial_mmu
:
:
:
turn_on_mmu:
mfmsr r0
ori r0,r0,MSR_DR|MSR_IR
mtspr SPRN_SRR1,r0
sync
isync
:
:
initial_mmu:
tlbia /* Invalidate all TLB entries */
#ifdef CONFIG_PIN_TLB
lis r8, MI_RSV4I@h
ori r8, r8, 0x1c00
#else
li r8, 0
#endif
mtspr SPRN_MI_CTR, r8 /* Set instruction MMU
control */
#ifdef CONFIG_PIN_TLB
lis r10, (MD_RSV4I | MD_RESETVAL)@h
ori r10, r10, 0x1c00
mr r8, r10
#else
lis r10, MD_RESETVAL@h
#endif
#ifndef CONFIG_8xx_COPYBACK
oris r10, r10, MD_WTDEF@h
mtspr SPRN_MD_CTR, r10 /* set data TLB
control */
/* Now map the lower 8 Meg into the TLBs. For
this quick hack,
* we can load the instruction and data TLB
registers with the
* same values.
*/
lis r8, KERNELBASE@h /* Create vaddr for
TLB */
ori r8, r8, MI_EVALID /* Mark it valid */
mtspr SPRN_MI_EPN, r8
mtspr SPRN_MD_EPN, r8
li r8, MI_PS8MEG /* Set 8M byte page */
ori r8, r8, MI_SVALID /* Make it valid */
mtspr SPRN_MI_TWC, r8
mtspr SPRN_MD_TWC, r8
li r8, MI_BOOTINIT /* Create RPN for
address 0 */
mtspr SPRN_MI_RPN, r8 /* Store TLB entry
*/
mtspr SPRN_MD_RPN, r8
lis r8, MI_Kp@h /* Set the protection mode
*/
mtspr SPRN_MI_AP, r8
mtspr SPRN_MD_AP, r8
/* Map another 8 MByte at the IMMR to get the
processor
* internal registers (among other things).
*/
#ifdef CONFIG_PIN_TLB
addi r10, r10, 0x0100
mtspr SPRN_MD_CTR, r10
#endif
mfspr r9, 638 /* Get current IMMR */
andis. r9, r9, 0xff80 /* Get 8Mbyte boundary
*/
mr r8, r9 /* Create vaddr for TLB */
ori r8, r8, MD_EVALID /* Mark it valid */
mtspr SPRN_MD_EPN, r8
li r8, MD_PS8MEG /* Set 8M byte page */
ori r8, r8, MD_SVALID /* Make it valid
*/
***********----------------**************************
UPTO THIS POINT ALL THE REGISTER/SPECIAL
REGISTER(SPR) ARE GETTING UPDATED BY THE DESIRED
VALUE.
BUT FOLLOWING STATEMENTS ARE NOT WORKING PROPERLY.
***************-----------------------------------***
mtspr SPRN_MD_TWC, r8
mr r8, r9 /* Create paddr for TLB */
ori r8, r8, MI_BOOTINIT|0x2 /* Inhibit
cache -- Cort */
mtspr SPRN_MD_RPN, r8
:
:
:
HASHDEFS are as follows :
MD_PS8MEG --0x0000000c
MD_EVALID --0x00000200
MD_SVALID --0x00000001
KERNELBASE --0xc0000000
MI_BOOTINIT --0x000001fd
MI_EVALID ----0x00000200
MI_SVALID ----0x00000001
MI_Kp -------0x40000000
MD_RESETVAL---0x04000000
CONFIG_PIN_TLB is not defined for my configuration
CONFIG_8xx_COPYBACK is definedfor my configuration.
Please help me in finding out the problem
And same board is working with other OS(e.g ECOS)
ported by other person.
thanks,
Barisa Kisku
Looking for people who are YOUR TYPE? Find them at in.groups.yahoo.com
^ permalink raw reply
* [PATCH 6/6] 82xx: Add the support of Wind River SBC PowerQUICCII 82xx
From: Mark Zhan @ 2007-06-08 8:58 UTC (permalink / raw)
To: paulus@samba.org; +Cc: linuxppc-dev@ozlabs.org
Add defconfig for Wind River SBC PowerQUICCII 82xx board
Signed-off-by: Mark Zhan <rongkai.zhan@windriver.com>
---
b/arch/powerpc/configs/sbcpq2_defconfig | 917
++++++++++++++++++++++++++++++++
1 file changed, 917 insertions(+)
diff --git a/arch/powerpc/configs/sbcpq2_defconfig
b/arch/powerpc/configs/sbcpq2_defconfig
new file mode 100644
index 0000000..36ff83c
--- /dev/null
+++ b/arch/powerpc/configs/sbcpq2_defconfig
@@ -0,0 +1,917 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.22-rc3
+# Thu Jun 7 16:15:43 2007
+#
+# CONFIG_PPC64 is not set
+CONFIG_PPC32=y
+CONFIG_PPC_MERGE=y
+CONFIG_MMU=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_IRQ_PER_CPU=y
+CONFIG_RWSEM_XCHGADD_ALGORITHM=y
+CONFIG_ARCH_HAS_ILOG2_U32=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+CONFIG_PPC=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_GENERIC_NVRAM=y
+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+CONFIG_ARCH_MAY_HAVE_PC_FDC=y
+CONFIG_PPC_OF=y
+# CONFIG_PPC_UDBG_16550 is not set
+# CONFIG_GENERIC_TBSYNC is not set
+CONFIG_AUDIT_ARCH=y
+CONFIG_GENERIC_BUG=y
+CONFIG_DEFAULT_UIMAGE=y
+
+#
+# Processor support
+#
+# CONFIG_CLASSIC32 is not set
+CONFIG_PPC_82xx=y
+# CONFIG_PPC_83xx is not set
+# CONFIG_PPC_85xx is not set
+# CONFIG_PPC_86xx is not set
+# CONFIG_PPC_8xx is not set
+# CONFIG_40x is not set
+# CONFIG_44x is not set
+# CONFIG_E200 is not set
+CONFIG_6xx=y
+CONFIG_PPC_FPU=y
+# CONFIG_PPC_DCR_NATIVE is not set
+# CONFIG_PPC_DCR_MMIO is not set
+CONFIG_PPC_STD_MMU=y
+CONFIG_PPC_STD_MMU_32=y
+# CONFIG_PPC_MM_SLICES is not set
+# CONFIG_SMP is not set
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+
+#
+# General setup
+#
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+# CONFIG_IPC_NS is not set
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_UTS_NS is not set
+# CONFIG_AUDIT is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_RELAY=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+CONFIG_KALLSYMS_ALL=y
+CONFIG_KALLSYMS_EXTRA_PASS=y
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+
+#
+# Loadable module support
+#
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
+
+#
+# Block layer
+#
+CONFIG_BLOCK=y
+CONFIG_LBD=y
+CONFIG_BLK_DEV_IO_TRACE=y
+CONFIG_LSF=y
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+CONFIG_DEFAULT_AS=y
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="anticipatory"
+
+#
+# Platform support
+#
+# CONFIG_PPC_MPC52xx is not set
+# CONFIG_PPC_MPC5200 is not set
+# CONFIG_PPC_CELL is not set
+# CONFIG_PPC_CELL_NATIVE is not set
+# CONFIG_MPC82xx_ADS is not set
+CONFIG_SBCPQ2=y
+# CONFIG_PQ2ADS is not set
+CONFIG_8260=y
+# CONFIG_MPIC is not set
+# CONFIG_MPIC_WEIRD is not set
+# CONFIG_PPC_I8259 is not set
+# CONFIG_PPC_RTAS is not set
+# CONFIG_MMIO_NVRAM is not set
+# CONFIG_PPC_MPC106 is not set
+# CONFIG_PPC_970_NAP is not set
+# CONFIG_PPC_INDIRECT_IO is not set
+# CONFIG_GENERIC_IOMAP is not set
+# CONFIG_CPU_FREQ is not set
+CONFIG_CPM2=y
+
+#
+# Kernel options
+#
+# CONFIG_HIGHMEM is not set
+# CONFIG_HZ_100 is not set
+CONFIG_HZ_250=y
+# CONFIG_HZ_300 is not set
+# CONFIG_HZ_1000 is not set
+CONFIG_HZ=250
+# CONFIG_PREEMPT_NONE is not set
+# CONFIG_PREEMPT_VOLUNTARY is not set
+CONFIG_PREEMPT=y
+CONFIG_PREEMPT_BKL=y
+CONFIG_BINFMT_ELF=y
+CONFIG_BINFMT_MISC=y
+CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_ARCH_POPULATES_NODE_MAP=y
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_PROC_DEVICETREE=y
+# CONFIG_CMDLINE_BOOL is not set
+# CONFIG_PM is not set
+CONFIG_SECCOMP=y
+# CONFIG_WANT_DEVICE_TREE is not set
+CONFIG_ISA_DMA_API=y
+
+#
+# Bus options
+#
+CONFIG_ZONE_DMA=y
+CONFIG_FSL_SOC=y
+# CONFIG_PCI is not set
+# CONFIG_PCI_DOMAINS is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+
+#
+# PCCARD (PCMCIA/CardBus) support
+#
+# CONFIG_PCCARD is not set
+
+#
+# Advanced setup
+#
+# CONFIG_ADVANCED_OPTIONS is not set
+
+#
+# Default settings for advanced configuration options are used
+#
+CONFIG_HIGHMEM_START=0xfe000000
+CONFIG_LOWMEM_SIZE=0x30000000
+CONFIG_KERNEL_START=0xc0000000
+CONFIG_TASK_SIZE=0x80000000
+CONFIG_BOOT_LOAD=0x00400000
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+CONFIG_SYN_COOKIES=y
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IP_VS is not set
+# CONFIG_IPV6 is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+# CONFIG_NETWORK_SECMARK is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+
+#
+# Core Netfilter Configuration
+#
+# CONFIG_NETFILTER_NETLINK is not set
+# CONFIG_NF_CONNTRACK_ENABLED is not set
+# CONFIG_NF_CONNTRACK is not set
+# CONFIG_NETFILTER_XTABLES is not set
+
+#
+# IP: Netfilter Configuration
+#
+# CONFIG_IP_NF_QUEUE is not set
+# CONFIG_IP_NF_IPTABLES is not set
+# CONFIG_IP_NF_ARPTABLES is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_MAC80211 is not set
+# CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_FW_LOADER is not set
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+
+#
+# Connector - unified userspace <-> kernelspace linker
+#
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+CONFIG_MTD_CFI_I4=y
+# CONFIG_MTD_CFI_I8 is not set
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PHYSMAP is not set
+# CONFIG_MTD_PHYSMAP_OF is not set
+# CONFIG_MTD_SBC8240 is not set
+CONFIG_MTD_WRSBC8260=y
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+# CONFIG_MTD_NAND is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Plug and Play support
+#
+# CONFIG_PNPACPI is not set
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=4096
+CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+
+#
+# Misc devices
+#
+# CONFIG_BLINK is not set
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_ATA is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+CONFIG_MACINTOSH_DRIVERS=y
+# CONFIG_MAC_EMUMOUSEBTN is not set
+# CONFIG_WINDFARM is not set
+
+#
+# Network device support
+#
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+# CONFIG_SMSC_PHY is not set
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_FIXED_PHY is not set
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+CONFIG_FS_ENET=y
+# CONFIG_FS_ENET_HAS_SCC is not set
+CONFIG_FS_ENET_HAS_FCC=y
+CONFIG_NETDEV_1000=y
+CONFIG_NETDEV_10000=y
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_SHAPER is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# Telephony Support
+#
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+# CONFIG_INPUT is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_UARTLITE is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_SERIAL_CPM=y
+CONFIG_SERIAL_CPM_CONSOLE=y
+# CONFIG_SERIAL_CPM_SCC1 is not set
+# CONFIG_SERIAL_CPM_SCC2 is not set
+# CONFIG_SERIAL_CPM_SCC3 is not set
+# CONFIG_SERIAL_CPM_SCC4 is not set
+CONFIG_SERIAL_CPM_SMC1=y
+CONFIG_SERIAL_CPM_SMC2=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+
+#
+# IPMI
+#
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_HW_RANDOM=y
+CONFIG_NVRAM=y
+CONFIG_GEN_RTC=y
+# CONFIG_GEN_RTC_X is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+
+#
+# TPM devices
+#
+# CONFIG_TCG_TPM is not set
+# CONFIG_I2C is not set
+
+#
+# SPI support
+#
+# CONFIG_SPI is not set
+# CONFIG_SPI_MASTER is not set
+
+#
+# Dallas's 1-wire bus
+#
+# CONFIG_W1 is not set
+# CONFIG_HWMON is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_SM501 is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+CONFIG_DAB=y
+
+#
+# Graphics support
+#
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+# CONFIG_VGASTATE is not set
+# CONFIG_FB is not set
+# CONFIG_FB_IBM_GXT4500 is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+# CONFIG_USB_ARCH_HAS_HCD is not set
+# CONFIG_USB_ARCH_HAS_OHCI is not set
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+
+#
+# USB Gadget Support
+#
+CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_PXA2XX is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_AT91 is not set
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+# CONFIG_USB_GADGET_DUALSPEED is not set
+# CONFIG_MMC is not set
+
+#
+# LED devices
+#
+# CONFIG_NEW_LEDS is not set
+
+#
+# LED drivers
+#
+
+#
+# LED Triggers
+#
+
+#
+# InfiniBand support
+#
+
+#
+# EDAC - error detection and reporting (RAS) (EXPERIMENTAL)
+#
+
+#
+# Real Time Clock
+#
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+
+#
+# SPI RTC drivers
+#
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+CONFIG_RTC_DRV_M48T59=y
+
+#
+# DMA Engine support
+#
+# CONFIG_DMA_ENGINE is not set
+
+#
+# DMA Clients
+#
+
+#
+# DMA Devices
+#
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_EXT4DEV_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_DNOTIFY is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_RAMFS=y
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+CONFIG_JFFS2_SUMMARY=y
+CONFIG_JFFS2_FS_XATTR=y
+CONFIG_JFFS2_FS_POSIX_ACL=y
+CONFIG_JFFS2_FS_SECURITY=y
+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
+CONFIG_JFFS2_ZLIB=y
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+# CONFIG_JFFS2_CMODE_NONE is not set
+CONFIG_JFFS2_CMODE_PRIORITY=y
+# CONFIG_JFFS2_CMODE_SIZE is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+
+#
+# Network File Systems
+#
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_NFS_V3_ACL=y
+# CONFIG_NFS_V4 is not set
+# CONFIG_NFS_DIRECTIO is not set
+# CONFIG_NFSD is not set
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_ACL_SUPPORT=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_SUNRPC_BIND34 is not set
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+# CONFIG_9P_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+
+#
+# Native Language Support
+#
+# CONFIG_NLS is not set
+
+#
+# Distributed Lock Manager
+#
+# CONFIG_DLM is not set
+# CONFIG_UCC_SLOW is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_CRC_CCITT=y
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+
+#
+# Instrumentation Support
+#
+# CONFIG_PROFILING is not set
+# CONFIG_KPROBES is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+# CONFIG_DETECT_SOFTLOCKUP is not set
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_FORCED_INLINING is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_DEBUG_STACKOVERFLOW is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_DEBUG_PAGEALLOC is not set
+# CONFIG_DEBUGGER is not set
+# CONFIG_KGDB_CONSOLE is not set
+# CONFIG_BDI_SWITCH is not set
+# CONFIG_BOOTX_TEXT is not set
+# CONFIG_PPC_EARLY_DEBUG is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+
+#
+# Cryptographic options
+#
+# CONFIG_CRYPTO is not set
^ permalink raw reply related
* [PATCH 5/6]: 82xx: Add the support of Wind River SBC PowerQUICCII 82xx
From: Mark Zhan @ 2007-06-08 8:57 UTC (permalink / raw)
To: paulus@samba.org; +Cc: linuxppc-dev@ozlabs.org
This patch adds the powerpc support to Wind River SBC PowerQUICCII 82xx
board.
Signed-off-by: Mark Zhan <rongkai.zhan@windriver.com>
---
b/arch/powerpc/boot/dts/sbcpq2.dts | 191 ++++++++++++++++++++
b/arch/powerpc/platforms/82xx/Kconfig | 10 +
b/arch/powerpc/platforms/82xx/Makefile | 5
b/arch/powerpc/platforms/82xx/sbcpq2.c | 306
+++++++++++++++++++++++++++++++++
b/arch/powerpc/platforms/82xx/sbcpq2.h | 118 ++++++++++++
b/drivers/mtd/maps/Kconfig | 2
b/include/asm-powerpc/mpc8260.h | 4
7 files changed, 633 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/platforms/82xx/Kconfig
b/arch/powerpc/platforms/82xx/Kconfig
index de7fce9..74322f1 100644
--- a/arch/powerpc/platforms/82xx/Kconfig
+++ b/arch/powerpc/platforms/82xx/Kconfig
@@ -13,6 +13,16 @@ config MPC82xx_ADS
help
This option enables support for the MPC8272 ADS board
+config SBCPQ2
+ bool "Wind River SBC PowerQUICCII 82xx"
+ select DEFAULT_UIMAGE
+ select 8260
+ select CPM2
+ select FSL_SOC
+ help
+ This option enables support for Wind River SBC PowerQUICCII 82xx,
+ which is a single-board computer with MPC82xx CPU.
+
endchoice
config PQ2ADS
diff --git a/arch/powerpc/platforms/82xx/Makefile
b/arch/powerpc/platforms/82xx/Makefile
index d9fd4c8..d75181c 100644
--- a/arch/powerpc/platforms/82xx/Makefile
+++ b/arch/powerpc/platforms/82xx/Makefile
@@ -1,5 +1,6 @@
#
# Makefile for the PowerPC 82xx linux kernel.
#
-obj-$(CONFIG_PPC_82xx) += mpc82xx.o
-obj-$(CONFIG_MPC82xx_ADS) += mpc82xx_ads.o
+obj-$(CONFIG_PPC_82xx) += mpc82xx.o
+obj-$(CONFIG_MPC82xx_ADS) += mpc82xx_ads.o
+obj-$(CONFIG_SBCPQ2) += sbcpq2.o
diff --git a/arch/powerpc/platforms/82xx/sbcpq2.c
b/arch/powerpc/platforms/82xx/sbcpq2.c
new file mode 100644
index 0000000..c459be4
--- /dev/null
+++ b/arch/powerpc/platforms/82xx/sbcpq2.c
@@ -0,0 +1,306 @@
+/*
+ * sbcpq2.c: The platform support for Wind River SBC PowerQUICCII 82xx
+ *
+ * Copyright 2007, Wind River Systems, Inc.
+ *
+ * Author: Mark Zhan <rongkai.zhan@windriver.com>
+ *
+ * This program is free software; you can redistribute it and/or
modify it
+ * under the terms of the GNU General Public License as published by
the
+ * Free Software Foundation; either version 2 of the License, or (at
your
+ * option) any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/reboot.h>
+#include <linux/pci.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <linux/rtc.h>
+#include <linux/console.h>
+#include <linux/delay.h>
+#include <linux/seq_file.h>
+#include <linux/fsl_devices.h>
+#include <linux/fs_uart_pd.h>
+#include <linux/fs_enet_pd.h>
+
+#include <asm/prom.h>
+#include <asm/machdep.h>
+#include <asm/io.h>
+#include <asm/pci-bridge.h>
+#include <asm/mpc8260.h>
+#include <asm/cpm2.h>
+#include <sysdev/cpm2_pic.h>
+#include <asm/udbg.h>
+#include <asm/i8259.h>
+#include <asm/fs_pd.h>
+
+static struct resource m48t59_resources[] = {
+ {
+ .start = SBCPQ2_RTC_BASE,
+ .end = SBCPQ2_RTC_BASE + SBCPQ2_RTC_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = SBCPQ2_M48T59_IRQ,
+ .end = SBCPQ2_M48T59_IRQ,
+ .flags = IORESOURCE_IRQ,
+ },
+ { },
+};
+
+static struct platform_device m48t59_rtc = {
+ .name = "rtc-m48t59",
+ .id = 0,
+ .num_resources = 2,
+ .resource = m48t59_resources,
+};
+
+static struct platform_device *sbcpq2_devices[] __initdata = {
+ &m48t59_rtc,
+};
+
+/**
+ * sbcpq2_pdev_init - Register the platform device for sbcpq2 board
+ */
+static int __init sbcpq2_platdev_init(void)
+{
+ struct irq_desc *desc = irq_desc + SBCPQ2_M48T59_IRQ;
+
+ /* Install a dummy irq chip for M48T59 RTC irq */
+ if (desc->chip == &no_irq_chip)
+ set_irq_handler(SBCPQ2_M48T59_IRQ, desc->handle_irq);
+
+ /* Register all platform devices for sbcpq2 */
+ platform_add_devices(sbcpq2_devices, ARRAY_SIZE(sbcpq2_devices));
+ return 0;
+}
+arch_initcall(sbcpq2_platdev_init);
+
+/*
+ * For SBCPQ2 board, the interrupt of M48T59 RTC chip
+ * will generate a machine check exception. We use a
+ * fake irq to give the platform machine_check_exception() hook
+ * a chance to call the driver ISR. If IRQ_HANDLED is returned,
+ * then we will survive from the machine check exception.
+ */
+static int sbcpq2_mach_check(struct pt_regs *regs)
+{
+ int recover = 0;
+ struct irq_desc *desc = irq_desc + SBCPQ2_M48T59_IRQ;
+ struct irqaction *action = desc->action;
+
+ while (action && (action->dev_id != &m48t59_rtc))
+ action = action->next;
+
+ /* Try to call m48t59 RTC driver ISR */
+ if (action && action->handler)
+ recover = action->handler(SBCPQ2_M48T59_IRQ, &m48t59_rtc);
+
+ return recover;
+}
+
+void init_fcc_ioports(struct fs_platform_info *fpi)
+{
+ iop_cpm2_t *iop;
+ int fcc_no, target;
+ unsigned int tempval;
+
+ iop = &cpm2_immr->im_ioport;
+ fcc_no = fs_get_fcc_index(fpi->fs_no);
+ switch (fcc_no) {
+ case 0:
+ /* Configure port A and C pins for FCC1 Ethernet. */
+ tempval = in_be32(&iop->iop_pdira);
+ tempval &= ~PA1_DIRA0;
+ tempval |= PA1_DIRA1;
+ out_be32(&iop->iop_pdira, tempval);
+
+ tempval = in_be32(&iop->iop_psora);
+ tempval &= ~PA1_PSORA0;
+ tempval |= PA1_PSORA1;
+ out_be32(&iop->iop_psora, tempval);
+
+ setbits32(&iop->iop_ppara, (PA1_DIRA0 | PA1_DIRA1));
+ target = CPM_CLK_FCC1;
+ break;
+ case 1:
+ /* Configure port B and C pins for FCC Ethernet. */
+ tempval = in_be32(&iop->iop_pdirb);
+ tempval &= ~PB2_DIRB0;
+ tempval |= PB2_DIRB1;
+ out_be32(&iop->iop_pdirb, tempval);
+
+ tempval = in_be32(&iop->iop_psorb);
+ tempval &= ~PB2_PSORB0;
+ tempval |= PB2_PSORB1;
+ out_be32(&iop->iop_psorb, tempval);
+
+ setbits32(&iop->iop_pparb, (PB2_DIRB0 | PB2_DIRB1));
+ target = CPM_CLK_FCC2;
+ break;
+ case 2:
+ /* Configure port B and C pins for FCC Ethernet. */
+ tempval = in_be32(&iop->iop_pdirb);
+ tempval &= ~PB3_DIRB0;
+ tempval |= PB3_DIRB1;
+ out_be32(&iop->iop_pdirb, tempval);
+
+ tempval = in_be32(&iop->iop_psorb);
+ tempval &= ~PB3_PSORB0;
+ tempval |= PB3_PSORB1;
+ out_be32(&iop->iop_psorb, tempval);
+
+ setbits32(&iop->iop_pparb, (PB3_DIRB0 | PB3_DIRB1));
+
+ tempval = in_be32(&iop->iop_pdirc);
+ tempval |= PC3_TXDAT;
+ out_be32(&iop->iop_pdirc, tempval);
+
+ tempval = in_be32(&iop->iop_psorc);
+ tempval &= ~PC3_TXDAT;
+ out_be32(&iop->iop_psorc, tempval);
+
+ setbits32(&iop->iop_pparc, PC3_TXDAT);
+ target = CPM_CLK_FCC3;
+ break;
+ default:
+ printk(KERN_DEBUG "Invalid FCC number %d\n", fcc_no);
+ return;
+ } /* switch (fcc_no) */
+
+ /* Alter clocks of port C */
+ tempval = PC_CLK(fpi->clk_rx - 8) | PC_CLK(fpi->clk_tx - 8);
+ clrbits32(&iop->iop_psorc, tempval);
+ clrbits32(&iop->iop_pdirc, tempval);
+ setbits32(&iop->iop_pparc, tempval);
+
+ /* configure clock routining */
+ cpm2_clk_setup(target, fpi->clk_rx, CPM_CLK_RX);
+ cpm2_clk_setup(target, fpi->clk_tx, CPM_CLK_TX);
+}
+
+static void __init sbcpq2_init_IRQ(void)
+{
+ struct device_node *np;
+ struct resource res;
+
+ np = of_find_compatible_node(NULL, "cpm-pic", "CPM2");
+ if (np == NULL) {
+ printk(KERN_ERR "PIC init: can not find cpm-pic node\n");
+ return;
+ }
+ if (of_address_to_resource(np, 0, &res)) {
+ printk(KERN_ERR "PIC init: invalid resource\n");
+ of_node_put(np);
+ return;
+ }
+
+ /* Init CPM2 interrupt controller */
+ cpm2_pic_init(np);
+
+ /* Initialize the default interrupt mapping priorities,
+ * in case the boot rom changed something on us.
+ */
+ cpm2_immr->im_intctl.ic_siprr = 0x05309770;
+
+ of_node_put(np);
+}
+
+/**
+ * sbcpq2_setup_arch - the board-level setup routine
+ */
+static void __init sbcpq2_setup_arch(void)
+{
+ struct device_node *np;
+ volatile memctl_cpm2_t *mc;
+ unsigned char * eeprom_base;
+ int i = 0;
+
+#ifdef CONFIG_CPM2
+ cpm2_reset();
+#endif
+
+ /*
+ * Make sure that we have the right CS# setting
+ */
+ mc = &cpm2_immr->im_memctl;
+
+ /* Boot Flash is the on-board flash */
+ mc->memc_br0 = (SBCPQ2_BOOT_FLASH_BASE & 0xFFFF8000) | 0x0801;
+ mc->memc_or0 = 0xFFE00896;
+
+ /* CS5 for EEPROM, visionPORT, User Swith, Status, i8259 and LED */
+ mc->memc_br5 = (SBCPQ2_EEPROM_BASE & 0xFFFF8000) | 0x0801;
+ mc->memc_or5 = 0xFFFF0856;
+
+ /* CS11 for RTC */
+ mc->memc_br11 = (SBCPQ2_RTC_BASE & 0xFFFF8000) | 0x0801;
+ mc->memc_or11 = 0xFFFF8836;
+
+ /*
+ * Fixup the MAC address in DevTree Blob, with the MAC address
+ * in EEPROM.
+ */
+ eeprom_base = ioremap(SBCPQ2_EEPROM_BASE, SBCPQ2_EEPROM_SIZE);
+ if (eeprom_base == NULL)
+ return;
+
+ for (np = NULL, i = 0;
+ (np = of_find_compatible_node(np, "network", "fs_enet")) != NULL;
+ i++) {
+ char *model, *macaddr;
+ const unsigned int *id;
+ int j = 0, eeprom_ofs = 0;
+
+ model = (char *)of_get_property(np, "model", NULL);
+ if (!model)
+ continue;
+
+ id = of_get_property(np, "device-id", NULL);
+ if (!id)
+ continue;
+
+ macaddr = (unsigned char *)of_get_mac_address(np);
+ if (!macaddr)
+ continue;
+
+ if (strstr(model, "FCC"))
+ eeprom_ofs = SBCPQ2_FCC1_MACADDR_OFS;
+ else if (strstr(model, "SCC"))
+ eeprom_ofs = SBCPQ2_SCC1_MACADDR_OFS;
+ eeprom_ofs += ((*id) - 1) * 6;
+
+ for (j = 0; j < 6; j++)
+ *(macaddr + j) = *(eeprom_base + eeprom_ofs + j);
+ }
+ iounmap(eeprom_base);
+}
+
+/*
+ * Called very early, device-tree isn't unflattened
+ */
+static int __init sbcpq2_probe(void)
+{
+ /* We always match for now, eventually we should look at
+ * the flat dev tree to ensure this is the board we are
+ * supposed to run on
+ */
+ return 1;
+}
+
+define_machine(sbcpq2)
+{
+ .name = CPUINFO_MACHINE,
+ .probe = sbcpq2_probe,
+ .setup_arch = sbcpq2_setup_arch,
+ .init_IRQ = sbcpq2_init_IRQ,
+ .show_cpuinfo = mpc82xx_show_cpuinfo,
+ .get_irq = cpm2_get_irq,
+ .calibrate_decr = mpc82xx_calibrate_decr,
+ .restart = mpc82xx_restart,
+ .halt = mpc82xx_halt,
+ .machine_check_exception = sbcpq2_mach_check,
+};
diff --git a/arch/powerpc/platforms/82xx/sbcpq2.h
b/arch/powerpc/platforms/82xx/sbcpq2.h
new file mode 100644
index 0000000..77b7ca6
--- /dev/null
+++ b/arch/powerpc/platforms/82xx/sbcpq2.h
@@ -0,0 +1,118 @@
+/*
+ * sbcpq2.h: the header file for Wind River SBC PowerQUICCII 82xx
+ *
+ * Copyright (C) 2007, Wind River Systems, Inc.
+ * Mark Zhan, <rongkai.zhan@windriver.com>
+ *
+ * This program is free software; you can redistribute it and/or
modify it
+ * under the terms of the GNU General Public License as published by
the
+ * Free Software Foundation; either version 2 of the License, or (at
your
+ * option) any later version.
+ */
+
+#ifndef __MACH_SBCPQ2_H
+#define __MACH_SBCPQ2_H
+
+#include <asm/ppcboot.h>
+
+/* For our show_cpuinfo hooks. */
+#define CPUINFO_VENDOR "Wind River"
+#define CPUINFO_MACHINE "SBC PowerQUICCII 82xx"
+
+/*
+ * Wind River SBC PowerQUICCII 82xx Physical Memory Map (CS0 for
OnBoard Flash)
+ *
+ * 0x00000000 - 0x07FFFFFF CS2, 128 MB DIMM SDRAM
+ * 0x08000000 - 0x0FFFFFFF CS3, 128 MB DIMM SDRAM
+ * 0x12000000 - 0x12100000 CS8, ATM
+ * 0x20000000 - 0x20FFFFFF CS4, 16 MB Local Bus SDRAM
+ * 0x21000000 - 0x21001FFF CS7, Control EPLD
+ * 0x22000000 - 0x22001FFF CS5, 8KB EEPROM
+ * 0x22002000 - 0x22003FFF CS5, visionPORT
+ * 0x22004000 - 0x22005FFF CS5, User Switches
+ * 0x22006000 - 0x22007FFF CS5, STATUS
+ * 0x22008000 - 0x22009FFF CS5, i8259 interrupt controller
+ * 0x2200A000 - 0x2200BFFF CS5, LED (Seven Segment Display)
+ * 0x80000000 - 0x80001FFF CS11, RTC
+ * 0xE0000000 - 0xE3FFFFFF CS6, 64 MB DIMM Flash
+ * 0xE4000000 - 0xE7FFFFFF CS1, 64 MB DIMM Flash
+ * 0xFE000000 - 0xFFFFFFFF CS0, 2 MB Boot Flash
+ * 0xF0000000 - 0xF0020000 MPC82xx Internal Registers Space
+ */
+#define SBCPQ2_SDRAM_BASE 0x00000000
+#define SBCPQ2_SDRAM_SIZE 0x10000000
+
+#define SBCPQ2_LOCAL_SDRAM_BASE 0x20000000
+#define SBCPQ2_LOCAL_SDRAM_SIZE 0x1000000
+
+#define SBCPQ2_EPLD_BASE 0x21000000
+#define SBCPQ2_EPLD_SIZE 0x2000
+
+#define SBCPQ2_EEPROM_BASE 0x22000000
+#define SBCPQ2_EEPROM_SIZE 0x2000
+
+/* User Switches SW5 */
+#define SBCPQ2_USER_SW_BASE 0x22004000
+#define SBCPQ2_USER_SW_SIZE 0x2000
+
+#define SBCPQ2_STATUS_BASE 0x22006000
+#define SBCPQ2_STATUS_SIZE 0x2000
+
+#define SBCPQ2_I8259_BASE 0x22008000
+#define SBCPQ2_I8259_SIZE 0x2000
+
+/* Seven Segment Display LED D46 */
+#define SBCPQ2_LED_BASE 0x2200A000
+#define SBCPQ2_LED_SIZE 0x2000
+
+#define SBCPQ2_RTC_BASE 0x80000000
+#define SBCPQ2_RTC_SIZE 0x2000
+
+#define SBCPQ2_BOOT_FLASH_BASE 0xFE000000
+#define SBCPQ2_BOOT_FLASH_SIZE 0x00200000
+
+#define SBCPQ2_DIMM_FLASH_BASE 0xE0000000
+#define SBCPQ2_DIMM_FLASH_SIZE 0x04000000
+
+#define CPM_MAP_ADDR 0xF0000000
+#define CPM_IRQ_OFFSET 0
+
+/*
+ * The offset of ethernet MAC addr within EEPROM
+ */
+#define SBCPQ2_FCC1_MACADDR_OFS 0x60
+#define SBCPQ2_FCC2_MACADDR_OFS 0x66
+#define SBCPQ2_FCC3_MACADDR_OFS 0x72
+#define SBCPQ2_SCC1_MACADDR_OFS 0x78
+
+/*
+ * The interrupt of M48T59 RTC chip will generate
+ * a machine check exception. We use a fake irq
+ * to get the platform machine_check_exception() hook
+ * have a chance to call the driver ISR.
+ */
+#define SBCPQ2_M48T59_IRQ (NR_IRQS-1)
+
+/*
+ * The following IRQs are routed to i8259 PIC.
+ *
+ * NOTE: i8259 PIC is cascaded to SIU_INT_IRQ6 of CPM2 interrupt
controller
+ */
+#define SBCPQ2_PC_IRQA (NR_SIU_INTS+0)
+#define SBCPQ2_PC_IRQB (NR_SIU_INTS+1)
+#define SBCPQ2_MPC185_IRQ (NR_SIU_INTS+2)
+#define SBCPQ2_ATM_IRQ (NR_SIU_INTS+3)
+#define SBCPQ2_PIRQA (NR_SIU_INTS+4)
+#define SBCPQ2_PIRQB (NR_SIU_INTS+5)
+#define SBCPQ2_PIRQC (NR_SIU_INTS+6)
+#define SBCPQ2_PIRQD (NR_SIU_INTS+7)
+
+/* cpm serial driver works with constants below */
+#define SIU_INT_SMC1 ((uint)0x04+CPM_IRQ_OFFSET)
+#define SIU_INT_SMC2 ((uint)0x05+CPM_IRQ_OFFSET)
+#define SIU_INT_SCC1 ((uint)0x28+CPM_IRQ_OFFSET)
+#define SIU_INT_SCC2 ((uint)0x29+CPM_IRQ_OFFSET)
+#define SIU_INT_SCC3 ((uint)0x2a+CPM_IRQ_OFFSET)
+#define SIU_INT_SCC4 ((uint)0x2b+CPM_IRQ_OFFSET)
+
+#endif /* __MACH_SBCPQ2_H */
diff --git a/arch/powerpc/boot/dts/sbcpq2.dts
b/arch/powerpc/boot/dts/sbcpq2.dts
new file mode 100644
index 0000000..cdcf780
--- /dev/null
+++ b/arch/powerpc/boot/dts/sbcpq2.dts
@@ -0,0 +1,191 @@
+/*
+ * Wind River SBC PowerQUICCII 82xx Device Tree Source
+ *
+ * Copyright 2007, Wind River Systems, Inc.
+ * Mark Zhan <rongkai.zhan@windriver.com>
+ *
+ * This program is free software; you can redistribute it and/or
modify it
+ * under the terms of the GNU General Public License as published by
the
+ * Free Software Foundation; either version 2 of the License, or (at
your
+ * option) any later version.
+ *
+ * Build with: dtc -f -I dts -O dtb -o sbcpq2.dtb -V 16 sbcpq2.dts
+ */
+
+/ {
+ model = "SBCPQ2";
+ compatible = "mpc82xx";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ linux,phandle = <100>;
+
+ cpus {
+ #cpus = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ linux,phandle = <200>;
+
+ PowerPC,8260@0 {
+ device_type = "cpu";
+ reg = <0>;
+ d-cache-line-size = <20>; // 32 bytes
+ i-cache-line-size = <20>; // 32 bytes
+ d-cache-size = <4000>; // L1, 16K
+ i-cache-size = <4000>; // L1, 16K
+ timebase-frequency = <0>; /* = (bus-frequency / 4) */
+ bus-frequency = <0>; /* = bd->bi_busfreq */
+ clock-frequency = <0>; /* = bd->bi_intfreq = gd->cpu_clk */
+ 32-bit;
+ linux,phandle = <201>;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ linux,phandle = <300>;
+ /* 256MB DIMM SDRAM & 16MB Local Bus SDRAM */
+ reg = <00000000 10000000 20000000 01000000>;
+ };
+
+ soc8260@f0000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ #interrupt-cells = <2>;
+ device_type = "soc";
+ ranges = <00000000 f0000000 00020000>;
+ reg = <f0000000 00020000>;
+ bus-frequency = <0>; /* from u-boot */
+
+ cpm@f0000000 {
+ linux,phandle = <f0000000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ #interrupt-cells = <2>;
+ device_type = "cpm";
+ model = "CPM2";
+ ranges = <00000000 00000000 00020000>;
+ reg = <0 00020000>;
+ command-proc = <0>; /* from u-boot */
+ brg-frequency = <0>; /* from u-boot */
+ cpm_clk = <0>; /* from u-boot */
+
+ smc@11a80 {
+ device_type = "serial";
+ compatible = "cpm_uart";
+ model = "SMC";
+ device-id = <1>;
+ reg = <11a80 10 0 40>;
+ rx-clock = <1>;
+ tx-clock = <1>;
+ interrupts = <4 2>;
+ interrupt-parent = <10c00>;
+ current-speed = <1c200>;
+ };
+
+ smc@11a90 {
+ device_type = "serial";
+ compatible = "cpm_uart";
+ model = "SMC";
+ device-id = <2>;
+ reg = <11a90 10 40 40>;
+ rx-clock = <2>;
+ tx-clock = <2>;
+ interrupts = <5 2>;
+ interrupt-parent = <10c00>;
+ current-speed = <1c200>;
+ };
+
+ fcc@11300 {
+ device_type = "network";
+ compatible = "fs_enet";
+ model = "FCC";
+ device-id = <1>;
+ reg = <11300 20 8400 100 11380 30>;
+ mac-address = [ 00 11 2F 99 43 54 ];
+ interrupts = <20 2>;
+ interrupt-parent = <10c00>;
+ phy-handle = <2452000>;
+ /* should be the index of cpm_clk */
+ rx-clock = <11>; /* CPM_CLK9 = 0x11 */
+ tx-clock = <12>; /* CPM_CLK10 = 0x12 */
+ };
+
+ fcc@11320 {
+ device_type = "network";
+ compatible = "fs_enet";
+ model = "FCC";
+ device-id = <2>;
+ reg = <11320 20 8500 100 113b0 30>;
+ mac-address = [ 00 11 2F 99 43 55 ];
+ interrupts = <21 2>;
+ interrupt-parent = <10c00>;
+ phy-handle = <2452001>;
+ rx-clock = <15>; /* CPM_CLK13 = 0x15 */
+ tx-clock = <16>; /* CPM_CLK14 = 0x16 */
+ };
+
+ fcc@11340 {
+ device_type = "network";
+ compatible = "fs_enet";
+ model = "FCC";
+ device-id = <3>;
+ reg = <11340 20 8600 100 113e0 30>;
+ mac-address = [ 00 11 2F 99 43 56 ];
+ interrupts = <22 2>;
+ interrupt-parent = <10c00>;
+ phy-handle = <2452002>;
+ rx-clock = <17>; /* CPM_CLK15 = 0x17 */
+ tx-clock = <18>; /* CPM_CLK16 = 0x18 */
+ };
+
+ };
+
+ mdio@0 {
+ device_type = "mdio";
+ compatible = "fs_enet";
+ reg = <0 0>;
+ linux,phandle = <24520>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethernet-phy@0 {
+ linux,phandle = <2452000>;
+ interrupt-parent = <10c00>;
+ interrupts = <17 2>;
+ reg = <0>;
+ /* MDIO: PC9, MDC: PC10, delay 1 usec */
+ bitbang = [ 09 09 0a 02 02 01 ];
+ device_type = "ethernet-phy";
+ };
+
+ ethernet-phy@1 {
+ linux,phandle = <2452001>;
+ interrupt-parent = <10c00>;
+ interrupts = <17 2>;
+ bitbang = [ 09 09 0a 02 02 01 ];
+ reg = <1>;
+ device_type = "ethernet-phy";
+ };
+
+ ethernet-phy@2 {
+ linux,phandle = <2452002>;
+ interrupt-parent = <10c00>;
+ interrupts = <17 2>;
+ bitbang = [ 09 09 0a 02 02 01 ];
+ reg = <2>;
+ device_type = "ethernet-phy";
+ };
+ };
+
+ interrupt-controller@10c00 {
+ linux,phandle = <10c00>;
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ reg = <10c00 80>;
+ built-in;
+ device_type = "cpm-pic";
+ compatible = "CPM2";
+ };
+ };
+};
diff --git a/drivers/mtd/maps/Kconfig b/drivers/mtd/maps/Kconfig
index b665e4a..90feeeb 100644
--- a/drivers/mtd/maps/Kconfig
+++ b/drivers/mtd/maps/Kconfig
@@ -566,7 +566,7 @@ config MTD_UCLINUX
config MTD_WRSBC8260
tristate "Map driver for WindRiver PowerQUICC II MPC82xx board"
- depends on (SBC82xx || SBC8560)
+ depends on (SBC82xx || SBC8560 || SBCPQ2)
select MTD_PARTITIONS
select MTD_MAP_BANK_WIDTH_4
select MTD_MAP_BANK_WIDTH_1
diff --git a/include/asm-powerpc/mpc8260.h
b/include/asm-powerpc/mpc8260.h
index e058e9e..097ddf4 100644
--- a/include/asm-powerpc/mpc8260.h
+++ b/include/asm-powerpc/mpc8260.h
@@ -15,6 +15,10 @@ #if defined(CONFIG_PQ2ADS) || defined (C
#include <platforms/82xx/pq2ads.h>
#endif
+#ifdef CONFIG_SBCPQ2
+#include <platforms/82xx/sbcpq2.h>
+#endif
+
#ifdef CONFIG_PCI_8260
#include <platforms/82xx/m82xx_pci.h>
#endif
^ permalink raw reply related
* [PATCH 4/6] 82xx: Add the support of Wind River SBC PowerQUICCII 82xx
From: Mark Zhan @ 2007-06-08 8:56 UTC (permalink / raw)
To: paulus@samba.org; +Cc: linuxppc-dev@ozlabs.org
Add the support of ST M48T59 RTC chip driver for SBC PowerQUICCII 82xx
board
Signed-off-by: Mark Zhan <rongkai.zhan@windriver.com>
---
b/drivers/rtc/Kconfig | 10 +
b/drivers/rtc/Makefile | 1
b/drivers/rtc/rtc-m48t59.c | 360
+++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 371 insertions(+)
diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index 4e4c10a..ca6a064 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -329,6 +329,16 @@ config RTC_DRV_S3C
This driver can also be build as a module. If so, the module
will be called rtc-s3c.
+config RTC_DRV_M48T59
+ tristate "ST M48T59"
+ depends on RTC_CLASS
+ help
+ If you say Y here you will get support for the
+ ST M48T59 RTC chip.
+
+ This driver can also be built as a module, if so, the module
+ will be called "rtc-m48t59".
+
config RTC_DRV_EP93XX
tristate "Cirrus Logic EP93XX"
depends on RTC_CLASS && ARCH_EP93XX
diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
index a1afbc2..70ba581 100644
--- a/drivers/rtc/Makefile
+++ b/drivers/rtc/Makefile
@@ -41,3 +41,4 @@ obj-$(CONFIG_RTC_DRV_V3020) += rtc-v3020
obj-$(CONFIG_RTC_DRV_AT91RM9200)+= rtc-at91rm9200.o
obj-$(CONFIG_RTC_DRV_SH) += rtc-sh.o
obj-$(CONFIG_RTC_DRV_BFIN) += rtc-bfin.o
+obj-$(CONFIG_RTC_DRV_M48T59) += rtc-m48t59.o
diff --git a/drivers/rtc/rtc-m48t59.c b/drivers/rtc/rtc-m48t59.c
new file mode 100644
index 0000000..0737827
--- /dev/null
+++ b/drivers/rtc/rtc-m48t59.c
@@ -0,0 +1,360 @@
+/*
+ * ST M48T59 RTC driver
+ *
+ * Copyright (c) 2007 Wind River Systems, Inc.
+ *
+ * Author: Mark Zhan <rongkai.zhan@windriver.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/rtc.h>
+#include <linux/platform_device.h>
+#include <linux/bcd.h>
+
+#define DEBUG_M48T59 1
+
+#ifdef DEBUG_M48T59
+#define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: "fmt,
__FUNCTION__, ##args)
+#else
+#define DPRINTK(fmt, args...)
+#endif
+
+#define M48T59_YEAR 0x1fff
+#define M48T59_MONTH 0x1ffe
+#define M48T59_MDAY 0x1ffd /* Day of Month */
+#define M48T59_WDAY 0x1ffc /* Day of Week */
+#define M48T59_HOUR 0x1ffb
+#define M48T59_MIN 0x1ffa
+#define M48T59_SEC 0x1ff9
+#define M48T59_CNTL 0x1ff8
+#define M48T59_WATCHDOG 0x1ff7
+#define M48T59_INTR 0x1ff6
+#define M48T59_ALARM_DATE 0x1ff5
+#define M48T59_ALARM_HOUR 0x1ff4
+#define M48T59_ALARM_MIN 0x1ff3
+#define M48T59_ALARM_SEC 0x1ff2
+#define M48T59_UNUSED 0x1ff1
+#define M48T59_FLAGS 0x1ff0
+
+#define M48T59_WDAY_CB 0x20 /* Century Bit */
+#define M48T59_WDAY_CEB 0x10 /* Century Enable Bit */
+
+#define M48T59_CNTL_READ 0x40;
+#define M48T59_CNTL_WRITE 0x80;
+
+#define M48T59_FLAGS_WDT 0x80 /* watchdog timer expired */
+#define M48T59_FLAGS_AF 0x40 /* alarm */
+#define M48T59_FLAGS_BF 0x10 /* low battery */
+
+#define M48T59_INTR_AFE 0x80 /* Alarm Interrupt Enable */
+#define M48T59_INTR_ABE 0x20
+
+static unsigned char * m48t59_vbase = NULL;
+static unsigned int m48t59_irq = -1;
+
+#define M48T59_READ(reg) readb(m48t59_vbase+reg)
+#define M48T59_WRITE(val, reg) writeb((val), (m48t59_vbase+reg))
+
+/**
+ * NOTE: M48T59 only uses BCD mode
+ */
+static int m48t59_rtc_read_time(struct device *dev, struct rtc_time
*tm)
+{
+ unsigned char val;
+
+ /* Issue the READ command */
+ M48T59_WRITE((M48T59_READ(M48T59_CNTL) | 0x40), M48T59_CNTL);
+
+ tm->tm_year = BCD2BIN(M48T59_READ(M48T59_YEAR));
+ /* tm_mon is 0-11 */
+ tm->tm_mon = BCD2BIN(M48T59_READ(M48T59_MONTH)) - 1;
+ tm->tm_mday = BCD2BIN(M48T59_READ(M48T59_MDAY));
+
+ val = M48T59_READ(M48T59_WDAY);
+ if ((val & M48T59_WDAY_CEB) && (val & M48T59_WDAY_CB)) {
+ DPRINTK("Century bit is enabled\n");
+ tm->tm_year += 100; /* one century */
+ }
+
+ tm->tm_wday = BCD2BIN(val & 0x07);
+ tm->tm_hour = BCD2BIN(M48T59_READ(M48T59_HOUR) & 0x3F);
+ tm->tm_min = BCD2BIN(M48T59_READ(M48T59_MIN) & 0x7F);
+ tm->tm_sec = BCD2BIN(M48T59_READ(M48T59_SEC) & 0x7F);
+
+ /* Clear the READ bit to restore the update */
+ M48T59_WRITE((M48T59_READ(M48T59_CNTL) & ~0x40), M48T59_CNTL);
+
+ DPRINTK("RTC read time %04d-%02d-%02d %02d/%02d/%02d\n",
+ tm->tm_year + 1900, tm->tm_mon, tm->tm_mday,
+ tm->tm_hour, tm->tm_min, tm->tm_sec);
+ return 0;
+}
+
+static int m48t59_rtc_set_time(struct device *dev, struct rtc_time *tm)
+{
+ unsigned char val = 0;
+
+ DPRINTK("RTC set time %04d-%02d-%02d %02d/%02d/%02d\n",
+ tm->tm_year + 1900, tm->tm_mon, tm->tm_mday,
+ tm->tm_hour, tm->tm_min, tm->tm_sec);
+
+ /* Issue the WRITE command */
+ M48T59_WRITE((M48T59_READ(M48T59_CNTL) | 0x80), M48T59_CNTL);
+
+ M48T59_WRITE((BIN2BCD(tm->tm_sec) & 0x7F), M48T59_SEC);
+ M48T59_WRITE((BIN2BCD(tm->tm_min) & 0x7F), M48T59_MIN);
+ M48T59_WRITE((BIN2BCD(tm->tm_hour) & 0x3F), M48T59_HOUR);
+ M48T59_WRITE((BIN2BCD(tm->tm_mday) & 0x3F), M48T59_MDAY);
+ /* tm_mon is 0-11 */
+ M48T59_WRITE((BIN2BCD(tm->tm_mon + 1) & 0x1F), M48T59_MONTH);
+ M48T59_WRITE(BIN2BCD(tm->tm_year % 100), M48T59_YEAR);
+
+ if (tm->tm_year/100)
+ val = (M48T59_WDAY_CEB | M48T59_WDAY_CB);
+ val |= (BIN2BCD(tm->tm_wday) & 0x07);
+ M48T59_WRITE(val, M48T59_WDAY);
+
+ /* update ended */
+ M48T59_WRITE((M48T59_READ(M48T59_CNTL) & ~0x80), M48T59_CNTL);
+
+ return 0;
+}
+
+/*
+ * Read alarm time and date in RTC
+ */
+static int m48t59_rtc_readalarm(struct device *dev, struct rtc_wkalrm
*alrm)
+{
+ unsigned char val;
+ struct rtc_time *tm = &alrm->time;
+
+ /* If no irq, we don't support ALARM */
+ if (m48t59_irq == -1)
+ return -EIO;
+
+ /* Issue the READ command */
+ M48T59_WRITE((M48T59_READ(M48T59_CNTL) | 0x40), M48T59_CNTL);
+
+ tm->tm_year = BCD2BIN(M48T59_READ(M48T59_YEAR));
+ /* tm_mon is 0-11 */
+ tm->tm_mon = BCD2BIN(M48T59_READ(M48T59_MONTH)) - 1;
+
+ val = M48T59_READ(M48T59_WDAY);
+ if ((val & M48T59_WDAY_CEB) && (val & M48T59_WDAY_CB))
+ tm->tm_year += 100; /* one century */
+
+ tm->tm_mday = BCD2BIN(M48T59_READ(M48T59_ALARM_DATE));
+ tm->tm_hour = BCD2BIN(M48T59_READ(M48T59_ALARM_HOUR));
+ tm->tm_min = BCD2BIN(M48T59_READ(M48T59_ALARM_MIN));
+ tm->tm_sec = BCD2BIN(M48T59_READ(M48T59_ALARM_SEC));
+
+ /* Clear the READ bit to restore the update */
+ M48T59_WRITE((M48T59_READ(M48T59_CNTL) & ~0x40), M48T59_CNTL);
+
+ DPRINTK("RTC read alarm time %04d-%02d-%02d %02d/%02d/%02d\n",
+ tm->tm_year + 1900, tm->tm_mon, tm->tm_mday,
+ tm->tm_hour, tm->tm_min, tm->tm_sec);
+ return 0;
+}
+
+/*
+ * Set alarm time and date in RTC
+ */
+static int m48t59_rtc_setalarm(struct device *dev, struct rtc_wkalrm
*alrm)
+{
+ struct rtc_time *tm = &alrm->time;
+ unsigned char mday, hour, min, sec;
+
+ if (m48t59_irq == -1)
+ return -EIO;
+
+ /*
+ * 0xff means "always match"
+ */
+ mday = tm->tm_mday;
+ mday = (mday >= 1 && mday <= 31) ? BIN2BCD(mday) : 0xff;
+ if (mday == 0xff)
+ mday = M48T59_READ(M48T59_MDAY);
+
+ hour = tm->tm_hour;
+ hour = (hour < 24) ? BIN2BCD(hour) : 0x00;
+
+ min = tm->tm_min;
+ min = (min < 60) ? BIN2BCD(min) : 0x00;
+
+ sec = tm->tm_sec;
+ sec = (sec < 60) ? BIN2BCD(sec) : 0x00;
+
+ /* Issue the WRITE command */
+ M48T59_WRITE((M48T59_READ(M48T59_CNTL) | 0x80), M48T59_CNTL);
+
+ M48T59_WRITE(mday, M48T59_ALARM_DATE);
+ M48T59_WRITE(hour, M48T59_ALARM_HOUR);
+ M48T59_WRITE(min, M48T59_ALARM_MIN);
+ M48T59_WRITE(sec, M48T59_ALARM_SEC);
+
+ /* update ended */
+ M48T59_WRITE((M48T59_READ(M48T59_CNTL) & ~0x80), M48T59_CNTL);
+
+ DPRINTK("RTC set alarm time %04d-%02d-%02d %02d/%02d/%02d\n",
+ tm->tm_year + 1900, tm->tm_mon, tm->tm_mday,
+ tm->tm_hour, tm->tm_min, tm->tm_sec);
+ return 0;
+}
+
+/*
+ * Handle commands from user-space
+ */
+static int m48t59_rtc_ioctl(struct device *dev, unsigned int cmd,
+ unsigned long arg)
+{
+ int ret = 0;
+
+ switch (cmd) {
+ case RTC_AIE_OFF: /* alarm interrupt off */
+ M48T59_WRITE(0x00, M48T59_INTR);
+ break;
+ case RTC_AIE_ON: /* alarm interrupt on */
+ M48T59_WRITE(M48T59_INTR_AFE, M48T59_INTR);
+ break;
+ default:
+ ret = -ENOIOCTLCMD;
+ break;
+ }
+
+ return ret;
+}
+
+static int m48t59_rtc_proc(struct device *dev, struct seq_file *seq)
+{
+ unsigned char val;
+
+ val = M48T59_READ(M48T59_FLAGS);
+ seq_printf(seq, "battery\t\t: %s\n",
+ (val & M48T59_FLAGS_BF) ? "low" : "normal");
+
+ return 0;
+}
+
+/*
+ * IRQ handler for the RTC
+ */
+static irqreturn_t m48t59_rtc_interrupt(int irq, void *dev_id)
+{
+ unsigned char flags;
+ struct platform_device *pdev = (struct platform_device *)dev_id;
+ struct rtc_device *rdev;
+
+ flags = M48T59_READ(M48T59_FLAGS);
+ if (flags & M48T59_FLAGS_AF) {
+ rdev = (struct rtc_device *)platform_get_drvdata(pdev);
+ rtc_update_irq(rdev, 1, (RTC_AF | RTC_IRQF));
+ return IRQ_HANDLED;
+ }
+
+ return IRQ_NONE;
+}
+
+static const struct rtc_class_ops m48t59_rtc_ops = {
+ .ioctl = m48t59_rtc_ioctl,
+ .read_time = m48t59_rtc_read_time,
+ .set_time = m48t59_rtc_set_time,
+ .read_alarm = m48t59_rtc_readalarm,
+ .set_alarm = m48t59_rtc_setalarm,
+ .proc = m48t59_rtc_proc,
+};
+
+static int __devinit m48t59_rtc_probe(struct platform_device *pdev)
+{
+ struct resource *res;
+ struct rtc_device *rtc_dev;
+ int ret = 0;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res)
+ return -ENODEV;
+
+ m48t59_vbase = ioremap(res->start, (res->end - res->start + 1));
+ if (!m48t59_vbase)
+ return -ENOMEM;
+
+ res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+ if (res)
+ m48t59_irq = res->start;
+
+ if (m48t59_irq != -1) {
+ ret = request_irq(m48t59_irq, m48t59_rtc_interrupt,
+ IRQF_SHARED, "rtc-m48t59", pdev);
+ if (ret)
+ goto err_unmap;
+ }
+
+ rtc_dev = rtc_device_register("m48t59", &pdev->dev,
+ &m48t59_rtc_ops, THIS_MODULE);
+ if (IS_ERR(rtc_dev)) {
+ ret = PTR_ERR(rtc_dev);
+ goto err_freeirq;
+ }
+
+ platform_set_drvdata(pdev, rtc_dev);
+ return 0;
+
+err_freeirq:
+ if (m48t59_irq != -1)
+ free_irq(m48t59_irq, pdev);
+err_unmap:
+ iounmap(m48t59_vbase);
+ return ret;
+}
+
+static int __devexit m48t59_rtc_remove(struct platform_device *pdev)
+{
+ struct rtc_device *rtc = platform_get_drvdata(pdev);
+
+ if (rtc)
+ rtc_device_unregister(rtc);
+
+ platform_set_drvdata(pdev, NULL);
+
+ if (m48t59_vbase)
+ iounmap(m48t59_vbase);
+ m48t59_vbase = NULL;
+
+ if (m48t59_irq != -1)
+ free_irq(m48t59_irq, pdev);
+ m48t59_irq = -1;
+ return 0;
+}
+
+static struct platform_driver m48t59_rtc_platform_driver = {
+ .driver = {
+ .name = "rtc-m48t59",
+ .owner = THIS_MODULE,
+ },
+ .probe = m48t59_rtc_probe,
+ .remove = __devexit_p(m48t59_rtc_remove),
+};
+
+static int __init m48t59_rtc_init(void)
+{
+ return platform_driver_register(&m48t59_rtc_platform_driver);
+}
+
+static void __exit m48t59_rtc_exit(void)
+{
+ platform_driver_unregister(&m48t59_rtc_platform_driver);
+}
+
+module_init(m48t59_rtc_init);
+module_exit(m48t59_rtc_exit);
+
+MODULE_AUTHOR("Mark Zhan <rongkai.zhan@windriver.com>");
+MODULE_DESCRIPTION("M48T59 RTC driver");
+MODULE_LICENSE("GPL");
^ permalink raw reply related
* [PATCH 3/6] 82xx: Add the support of Wind River SBC PowerQUICCII 82xx
From: Mark Zhan @ 2007-06-08 8:54 UTC (permalink / raw)
To: paulus@samba.org; +Cc: linuxppc-dev@ozlabs.org
This patch fixes the following problems:
(1) The bus_id fs_enet device should be the same with its associated phy
device bus_id, which is the combination of mdio bus ID and phy_addr,
otherwise fs_enet driver will not be able to attach to its PHY device.
MDIO bus ID is equal to fs_enet platform device ID.
(2) The phy irq map should not be hardcoded. It should match the PHY
address provided by the platform DevTree Blob.
(3) Add the support of CPM2 SMC serial.
Signed-off-by: Mark Zhan <rongkai.zhan@windriver.com>
---
b/arch/powerpc/sysdev/fsl_soc.c | 49
++++++++++++++++++++--------------------
1 file changed, 25 insertions(+), 24 deletions(-)
diff --git a/arch/powerpc/sysdev/fsl_soc.c
b/arch/powerpc/sysdev/fsl_soc.c
index cad1757..fe40c86 100644
--- a/arch/powerpc/sysdev/fsl_soc.c
+++ b/arch/powerpc/sysdev/fsl_soc.c
@@ -689,7 +689,8 @@ static int __init fs_enet_of_init(void)
fs_enet_data.cp_block = CPM_CR_FCC_SBLOCK(fcc_index);
snprintf((char*)&bus_id[(*id)], BUS_ID_SIZE, "%x:%02x",
- (u32)res.start, fs_enet_data.phy_addr);
+ fs_enet_dev->id, fs_enet_data.phy_addr);
+
fs_enet_data.bus_id = (char*)&bus_id[(*id)];
fs_enet_data.init_ioports = init_fcc_ioports;
@@ -716,11 +717,9 @@ static int __init fs_enet_of_init(void)
fs_enet_mdio_bb_data.delay =
mdio_bb_prop[5];
- fs_enet_mdio_bb_data.irq[0] = phy_irq[0];
- fs_enet_mdio_bb_data.irq[1] = -1;
- fs_enet_mdio_bb_data.irq[2] = -1;
- fs_enet_mdio_bb_data.irq[3] = phy_irq[0];
- fs_enet_mdio_bb_data.irq[31] = -1;
+ memset(fs_enet_mdio_bb_data.irq, -1,
+ sizeof(fs_enet_mdio_bb_data.irq));
+ fs_enet_mdio_bb_data.irq[(*phy_addr)] = phy_irq[0];
fs_enet_mdio_bb_data.mdio_dat.offset =
(u32)&cpm2_immr->im_ioport.iop_pdatc;
@@ -757,8 +756,8 @@ err:
arch_initcall(fs_enet_of_init);
-static const char scc_regs[] = "regs";
-static const char scc_pram[] = "pram";
+static const char cpm_uart_regs[] = "regs";
+static const char cpm_uart_pram[] = "pram";
static int __init cpm_uart_of_init(void)
{
@@ -775,38 +774,42 @@ static int __init cpm_uart_of_init(void)
const int *id;
const char *model;
+ cpm_uart_dev = NULL;
memset(r, 0, sizeof(r));
memset(&cpm_uart_data, 0, sizeof(cpm_uart_data));
ret = of_address_to_resource(np, 0, &r[0]);
if (ret)
goto err;
-
- r[0].name = scc_regs;
+ r[0].name = cpm_uart_regs;
ret = of_address_to_resource(np, 1, &r[1]);
if (ret)
goto err;
- r[1].name = scc_pram;
+ r[1].name = cpm_uart_pram;
of_irq_to_resource(np, 0, &r[2]);
- cpm_uart_dev =
- platform_device_register_simple("fsl-cpm-scc:uart", i, &r[0], 3);
-
- if (IS_ERR(cpm_uart_dev)) {
- ret = PTR_ERR(cpm_uart_dev);
- goto err;
- }
-
id = of_get_property(np, "device-id", NULL);
cpm_uart_data.fs_no = *id;
model = of_get_property(np, "model", NULL);
strcpy(cpm_uart_data.fs_type, model);
- cpm_uart_data.uart_clk = ppc_proc_freq;
+ if (strstr(model, "SMC")) {
+ cpm_uart_dev = platform_device_register_simple("fsl-cpm-smc:uart",
+ i, &r[0], 3);
+ } else if (strstr(model, "SCC")) {
+ cpm_uart_dev = platform_device_register_simple("fsl-cpm-scc:uart",
+ i, &r[0], 3);
+ }
+
+ if (IS_ERR(cpm_uart_dev)) {
+ ret = PTR_ERR(cpm_uart_dev);
+ goto err;
+ }
+ cpm_uart_data.uart_clk = ppc_proc_freq;
cpm_uart_data.tx_num_fifo = 4;
cpm_uart_data.tx_buf_size = 32;
cpm_uart_data.rx_num_fifo = 4;
@@ -816,10 +819,8 @@ static int __init cpm_uart_of_init(void)
cpm_uart_data.clk_tx = *((u32 *)of_get_property(np,
"tx-clock", NULL));
- ret =
- platform_device_add_data(cpm_uart_dev, &cpm_uart_data,
- sizeof(struct
- fs_uart_platform_info));
+ ret = platform_device_add_data(cpm_uart_dev, &cpm_uart_data,
+ sizeof(struct fs_uart_platform_info));
if (ret)
goto unreg;
}
^ permalink raw reply related
* Re: [RFC/PATCH 4/4] Add support for MSI on Axon-based Cell systems
From: Segher Boessenkool @ 2007-06-08 8:47 UTC (permalink / raw)
To: michael; +Cc: linuxppc-dev, Arnd Bergmann
In-Reply-To: <1181271180.6026.10.camel@concordia.ozlabs.ibm.com>
>>> + for_each_compatible_node(node, NULL, "ibm,axon-msic") {
>>> + if (axon_msi_setup_one(of_node_get(node)) == 0)
>>> + found++;
>>> + }
>>> + of_node_put(node);
So where is the of_node_put() done for the of_node_get()
inside the loop?
Segher
^ permalink raw reply
* Re: [PATCH 2/8] Add uli1575 pci-bridge sector to MPC8641HPCN dts file.
From: Benjamin Herrenschmidt @ 2007-06-08 8:32 UTC (permalink / raw)
To: Segher Boessenkool; +Cc: linuxppc-dev@ozlabs.org
In-Reply-To: <71535aedbbc915db81f6c7486db3257f@kernel.crashing.org>
On Fri, 2007-06-08 at 10:29 +0200, Segher Boessenkool wrote:
> > Hrm... does the interrupt-map include the bus number for you ? They
> > generally don't ...
>
> Any interrupt mapping should serve one interrupt domain
> only. For a PCI bus, that bus is that domain, so all
> bus#s in the interrupt-map should be identical.
>
> Now you can cheat and have one interrupt-map handle
> mappings for several PCI busses (in the same PCI domain).
> Whenever this works at all, it is not by design, and
> results in a huge mess and various (little) problems.
Agreed.
Ben.
^ permalink raw reply
* Re: [PATCH 2/8] Add uli1575 pci-bridge sector to MPC8641HPCN dts file.
From: Segher Boessenkool @ 2007-06-08 8:29 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev@ozlabs.org
In-Reply-To: <1181254330.14818.71.camel@localhost.localdomain>
>> Right. Unless there's an interrupt mapping, which has to include
>> the
>> bus number in the filter. When that happens, parsing the interrupt
>> map for the i8259's mapping fails because its address doesn't match.
>
> Hrm... does the interrupt-map include the bus number for you ? They
> generally don't ...
Any interrupt mapping should serve one interrupt domain
only. For a PCI bus, that bus is that domain, so all
bus#s in the interrupt-map should be identical.
Now you can cheat and have one interrupt-map handle
mappings for several PCI busses (in the same PCI domain).
Whenever this works at all, it is not by design, and
results in a huge mess and various (little) problems.
Just don't :-)
Segher
^ permalink raw reply
* Re: [PATCH] Fix the LPC47M192 SuperIO on the MPC8641 HPCN
From: Segher Boessenkool @ 2007-06-08 8:22 UTC (permalink / raw)
To: Andy Fleming; +Cc: linuxppc-dev, paulus, Arnd Bergmann
In-Reply-To: <FF15186D-1D92-422E-AC6C-3127F6116C79@freescale.com>
>>> I suppose I could create a device node for the Super I/O config
>>> registers and use those instead of hardcoding it here.
>>
>> I'd just hide it all, do this setup in the firmware,
>> where it belongs, and don't expose the superio config
>> in the device tree.
>
> No more. No more firmware-only initializations.
This setup is very board specific, and the board cannot
reasonably work without that setup being done right. You
really want to push _that_ into Linux? Alternatively,
you could put it into the device tree, but that doesn't
help anything either.
> It sounds great, in principle, until you actually have to figure out
> why someone's setup isn't working. I'm tired of having to see if the
> dts, u-boot, and Linux are in sync. If Linux wants to use a device, I
> think it's not unreasonable to have it setup the device itself. That
> way, Linux can do whatever it wants with the device, and not have to
> rely on U-Boot (or some other firmware) setting up the appropriate
> bits.
There is one and only one way to set up the superio for
a certain board (assuming the legacy I/O and IRQ values
are considered fixed values).
> Please...no. What happens next is that we find a small bug that
> requires we modify U-Boot to do the initialization slightly
> differently, and then requires Linux to act slightly differently.
This is equivalent to needing a board-level fix really.
Segher
^ permalink raw reply
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