* Re: [PATCH 00/13] IB/ehca: eHCA2 enablement & some fixes
From: Joachim Fenkes @ 2007-07-10 13:20 UTC (permalink / raw)
To: Roland Dreier
Cc: LKML, LinuxPPC-Dev, Christoph Raisch, OF-General, Stefan Roscher
In-Reply-To: <adak5t9w7kx.fsf@cisco.com>
Roland Dreier <rdreier@cisco.com> wrote on 10.07.2007 00:11:42:
> thanks, I applied these for 2.6.23 and fixed a bunch of minor things
> that scripts/checkpatch.pl complained about (since I was in a mood to
> do mindless things).
Thanks! Both for the quick merge and for the fixes!
> In the future please run that yourself and clean
> up the obvious things. I generally don't worry about the 80 column
> stuff, but it will catch most whitespace problems and tell you that
> foo(x,y) should be foo(x, y) etc. So you don't have to completely
> silence the script but at least take a look at the output.
Didn't know about that script before, so thanks for the pointer!
I'll be sure to pass the next set of patches through it.
Joachim
^ permalink raw reply
* Re: [PATCH v2][POWERPC] document ipic level/sense info
From: Segher Boessenkool @ 2007-07-10 13:21 UTC (permalink / raw)
To: Grant Likely; +Cc: Stuart Yoder, paulus, linuxppc-dev
In-Reply-To: <fa686aa40707091548h5182d6d0r900afc1f35d4f80f@mail.gmail.com>
>> +Sense and level information follows the Linux convention
>> +(specified in include/linux/interrupt.h) and should be encoded
>> +as follows:
>> +
>> + 2 = high to low edge sensitive type enabled
>> + 8 = active low level sensitive type enabled
> ... but it is probably worthwhile commentting that sense types 1 & 4
> are not supported; just to fill in the obvious gaps. :-)
Same for sense types 0, 3, 5, 6, ...
Just name the sense types 0 and 1, similar to what all other
OF interrupt controller bindings do.
Segher
^ permalink raw reply
* Re: [kernel-2.6.19]Marvell GT-64260 and Ethernet
From: Dale Farnsworth @ 2007-07-10 13:22 UTC (permalink / raw)
To: psyphi, Linuxppc-embedded
In-Reply-To: <13b81f0c0707092336r5c7f4996u6f9c73d95c63bdc6@mail.gmail.com>
> I'm porting a Linux kernel 2.6.19 on a PowerPC 750 FX board.
> My Linux runs completely except for Ethernet. I don't find any Ethernet
> driver for my bridge. Do you know if there is an Ethernet driver for the
> Marvell GT-64260 bridge for PowerPC processor. I found a GT-64260 ethernet
> driver in the kernel 2.4.34 for MIPS processor, will it be possible to port
> it in a 2.6 kernel?
I believe that Steve Hill <sjhill@realitydiluted.com> has patched
the mv643xx_eth driver to work with the 64260 and plans to submit
the patches.
-Dale
^ permalink raw reply
* Re: [kernel-2.6.19]Marvell GT-64260 and Ethernet
From: ThomasB @ 2007-07-10 13:41 UTC (permalink / raw)
To: Dale Farnsworth; +Cc: Linuxppc-embedded
In-Reply-To: <20070710132207.12018.qmail@farnsworth.org>
[-- Attachment #1: Type: text/plain, Size: 621 bytes --]
>Isn't the ethernet the same on the 64260, 64360, 64460?
>
> There's definitely a driver for 6436x and above..
I just try it, it doesn't work, I receive without end the message:
mv643xx PHY read timeout, port 0
> I believe that Steve Hill <sjhill@realitydiluted.com> has patched
> the mv643xx_eth driver to work with the 64260 and plans to submit
> the patches.
That's means the patch isn't yet ready?
I will try to contact him.
It's nevertheless odd, I read about a file named gt64260_eth.c during my
search on the internet.But I wasn't able to find it :(.
Thanks for you help
--
ThomasB
http://psyphi.zeblog.com/
[-- Attachment #2: Type: text/html, Size: 820 bytes --]
^ permalink raw reply
* Re: [PATCH 06/13] IB/ehca: Set SEND_GRH flag for all non-LL UD QPs on eHCA2
From: Christoph Raisch @ 2007-07-10 16:35 UTC (permalink / raw)
To: Roland Dreier
Cc: Joachim Fenkes, LKML, LinuxPPC-Dev, OF-General, Stefan Roscher
In-Reply-To: <adazm25w998.fsf@cisco.com>
> What decides if a QP is LL or not?
>
> - R.
Currently we use a high bit in the QP type, which is not how we want to
keep it permanently.
What would you suggest, add two additional LL QP types, or change something
more fundamental
in libibverbs and kernel ib core?
We think we can get along quite well with the existing parameters in the
current create QP.
The current user-kernel interface is ok for these new QPs for post_send +
post_recv,
but unfortunately the libibverbs userspace calls don't match exactly how
the LL queues are to be used.
We would need something like the LL QP interface in libehca in libibverbs
to keep that interface generic.
We didn't see a usage yet for LL QP in kernel, so maybe we should continue
that
discussion on general@openfabrics only.
We could provide example code in libehca/samples if needed.
Gruss / Regards
Christoph + Nam
^ permalink raw reply
* Re: [kernel-2.6.19]Marvell GT-64260 and Ethernet
From: Dale Farnsworth @ 2007-07-10 13:50 UTC (permalink / raw)
To: ThomasB; +Cc: Linuxppc-embedded
In-Reply-To: <13b81f0c0707100641i56e08bd3n7c7911782a81628a@mail.gmail.com>
On Tue, Jul 10, 2007 at 03:41:25PM +0200, ThomasB wrote:
> It's nevertheless odd, I read about a file named gt64260_eth.c during my
> search on the internet.But I wasn't able to find it :(.
It was in the (now obsolete) linuxppc_2_4_devel kernel. I can send
you a copy, but a merged mv64x60 driver will be much better.
-Dale
^ permalink raw reply
* Re: [kernel-2.6.19]Marvell GT-64260 and Ethernet
From: Mark A. Greer @ 2007-07-10 13:51 UTC (permalink / raw)
To: ThomasB; +Cc: Linuxppc-embedded
In-Reply-To: <13b81f0c0707100641i56e08bd3n7c7911782a81628a@mail.gmail.com>
On Tue, Jul 10, 2007 at 03:41:25PM +0200, ThomasB wrote:
> >Isn't the ethernet the same on the 64260, 64360, 64460?
> >
> >There's definitely a driver for 6436x and above..
>
> I just try it, it doesn't work, I receive without end the message:
> mv643xx PHY read timeout, port 0
>
> >I believe that Steve Hill <sjhill@realitydiluted.com> has patched
> >the mv643xx_eth driver to work with the 64260 and plans to submit
> >the patches.
> That's means the patch isn't yet ready?
It probably means you don't something set up for whatever PHY you're
using.
> I will try to contact him.
A good idea.
> It's nevertheless odd, I read about a file named gt64260_eth.c during my
> search on the internet.But I wasn't able to find it :(.
There was one for 2.4 that was in the ppc devel tree but it never went
mainline. Hopefully, Steve can help you from here.
Mark
^ permalink raw reply
* Re: [PATCH 2/4] Add dma sector to mpc8641hpcn board dts
From: Segher Boessenkool @ 2007-07-10 13:55 UTC (permalink / raw)
To: Zhang Wei; +Cc: linuxppc-dev, paulus
In-Reply-To: <11840606621515-git-send-email-wei.zhang@freescale.com>
> + dma@21000{
> + compatible = "fsl,mpc8xxx-dma";
Please use a real name, not this "xxx" stuff.
> + reg = <21000 100>;
> + ranges = <0 21000 1000>;
These overlap, that can't be right; it is just begging for
trouble.
> + ch0@100{
> + reg = <100 80>;
> + extended;
I think you want a little more detailed property name
than "extended" here?
Segher
^ permalink raw reply
* Re: [PATCH 2/4] Add dma sector to mpc8641hpcn board dts
From: Segher Boessenkool @ 2007-07-10 13:57 UTC (permalink / raw)
To: Zhang Wei; +Cc: linuxppc-dev, paulus
In-Reply-To: <11840606621515-git-send-email-wei.zhang@freescale.com>
> + dma@21000{
"dma-controller" btw. And a space before the "{" (here and
elsewhere) :-)
Segher
^ permalink raw reply
* Re: [PATCH 1/4] Add DMA sector to Documentation/powerpc/booting-without-of.txt file.
From: Segher Boessenkool @ 2007-07-10 14:01 UTC (permalink / raw)
To: Zhang Wei; +Cc: linuxppc-dev, paulus
In-Reply-To: <11840606624025-git-send-email-wei.zhang@freescale.com>
> + k) DMA
> +
> + This sector define DMA for dma-engine driver of Freescale
It's called a "device node" or "node", not a "sector".
> + - compatible : Should be "fsl,mpc8xxx-dma"
Should _include_, not should _be_. And none of this xxx
business, of course.
> + - extended : Set the DMA channel to work at extended chain mode.
> + If not set, the DMA channel will work at basic
> + chain mode.
Call it "extended-chain-mode", perhaps?
> + - reserved : Reserve the DMA channel to device.
What does this do? Reserve it for what device, and where?
The OS driver?
Segher
^ permalink raw reply
* MPC82xx ADS SCC ports initialisation
From: Laurent Pinchart @ 2007-07-10 14:19 UTC (permalink / raw)
To: linuxppc-embedded; +Cc: vbordug
Hi everybody,
while checking the availability of MPC8260 support in ARCH=powerpc, I ran
across a possible issue in SCC ports initialisation for the MPC82xx ADS
boards.
init_scc1_uart_ioports and init_scc4_uart_ioports in
arch/powerpc/platforms/mpc82xx/mpx82xx_ads.c use the following code to
configure the SCC clocks:
clrbits32(&immap->im_cpmux.cmx_scr, (0x00000007 << (4 - data->clk_tx)));
clrbits32(&immap->im_cpmux.cmx_scr, (0x00000038 << (4 - data->clk_rx)));
setbits32(&immap->im_cpmux.cmx_scr,
((data->clk_tx - 1) << (4 - data->clk_tx)));
setbits32(&immap->im_cpmux.cmx_scr,
((data->clk_rx - 1) << (4 - data->clk_rx)));
The shift right-hand operand doesn't seem to be correct. Could anyone confirm
this ? If my assumption is right, could anyone tell me if the MPC82xx
processors are actually supported by the powerpc architecture, or if the
MPC82xx ADS code is just a non-functional work in progress.
I also noticed that U-Boot doesn't have flatten device tree support for the
MPC82xx family. There seem to be still a lot of work to do to support the
MPC82xx in the powerpc tree, and the effort is much bigger than just porting
a board from ppc to powerpc.
Laurent Pinchart
^ permalink raw reply
* Re: [PATCH 2.6.21-rt2] PowerPC: decrementer clockevent driver
From: Segher Boessenkool @ 2007-07-10 14:24 UTC (permalink / raw)
To: Gabriel Paubert; +Cc: Thomas Gleixner, mingo, linux-kernel, linuxppc-dev
In-Reply-To: <20070710105212.GA14682@iram.es>
> This scales with the number of processors since there is one
> decrementer per core (is it per thread on SMT chips?
> I don't know).
One per core.
Segher
^ permalink raw reply
* Re: [PATCH] Fix the PCI-Ex link training bug on MPC8641HPCN board.
From: Kumar Gala @ 2007-07-10 14:36 UTC (permalink / raw)
To: Zhang Wei; +Cc: linuxppc-dev, paulus
In-Reply-To: <11840492523488-git-send-email-wei.zhang@freescale.com>
On Jul 10, 2007, at 1:34 AM, Zhang Wei wrote:
> If the PCI-Ex hose link training is failed, the kernel will halt at
> the
> PCI scan process on MPC8641HPCN board.
>
> This patch will remove and free the hose from PCI host list if the
> PCI hose link training is failed.
>
> Signed-off-by: Zhang Wei <wei.zhang@freescale.com>
Thanks. Going to roll this into the work Roy's been doing to make
PCI code work across 85xx/86xx.
- k
> ---
> arch/powerpc/platforms/86xx/pci.c | 4 +++-
> 1 files changed, 3 insertions(+), 1 deletions(-)
>
> diff --git a/arch/powerpc/platforms/86xx/pci.c b/arch/powerpc/
> platforms/86xx/pci.c
> index 73cd5b0..0b7835c 100644
> --- a/arch/powerpc/platforms/86xx/pci.c
> +++ b/arch/powerpc/platforms/86xx/pci.c
> @@ -210,8 +210,10 @@ int __init mpc86xx_add_bridge(struct
> device_node *dev)
>
> /* Probe the hose link training status */
> early_read_config_word(hose, 0, 0, PCIE_LTSSM, &val);
> - if (val < PCIE_LTSSM_L0)
> + if (val < PCIE_LTSSM_L0) {
> + pcibios_free_controller(hose);
> return -ENXIO;
> + }
>
> /* Setup the PCIE host controller. */
> mpc86xx_setup_pcie(hose, rsrc.start, rsrc.end - rsrc.start + 1);
> --
> 1.5.1
^ permalink raw reply
* RE: [PATCH v2][POWERPC] document ipic level/sense info
From: Yoder Stuart-B08248 @ 2007-07-10 14:36 UTC (permalink / raw)
To: Segher Boessenkool, Grant Likely; +Cc: linuxppc-dev, paulus
In-Reply-To: <A9B90D06-77BD-49B5-8D2D-300641A973BC@kernel.crashing.org>
=20
> -----Original Message-----
> From: Segher Boessenkool [mailto:segher@kernel.crashing.org]=20
> Sent: Tuesday, July 10, 2007 8:21 AM
> To: Grant Likely
> Cc: Yoder Stuart-B08248; linuxppc-dev@ozlabs.org; paulus@samba.org
> Subject: Re: [PATCH v2][POWERPC] document ipic level/sense info
>=20
> >> +Sense and level information follows the Linux convention
> >> +(specified in include/linux/interrupt.h) and should be encoded
> >> +as follows:
> >> +
> >> + 2 =3D high to low edge sensitive type enabled
> >> + 8 =3D active low level sensitive type enabled
>=20
> > ... but it is probably worthwhile commentting that sense types 1 & 4
> > are not supported; just to fill in the obvious gaps. :-)
>=20
> Same for sense types 0, 3, 5, 6, ...
>=20
> Just name the sense types 0 and 1, similar to what all other
> OF interrupt controller bindings do.
Actually, all I am trying to do with this patch is document the
current state of things. The 2/8 sense type usage has been that
way for a long time, and I'll defer to the 83xx maintainers
if they see any value in changing it.
Right now there are many DTS files with level/sense set to values
like 8 and no indication anywhere where those values came from.
Stuart
^ permalink raw reply
* Re: [PATCH v2][POWERPC] document ipic level/sense info
From: Kumar Gala @ 2007-07-10 14:40 UTC (permalink / raw)
To: Segher Boessenkool; +Cc: Stuart Yoder, paulus, linuxppc-dev
In-Reply-To: <A9B90D06-77BD-49B5-8D2D-300641A973BC@kernel.crashing.org>
On Jul 10, 2007, at 8:21 AM, Segher Boessenkool wrote:
>>> +Sense and level information follows the Linux convention
>>> +(specified in include/linux/interrupt.h) and should be encoded
>>> +as follows:
>>> +
>>> + 2 = high to low edge sensitive type enabled
>>> + 8 = active low level sensitive type enabled
>
>> ... but it is probably worthwhile commentting that sense types 1 & 4
>> are not supported; just to fill in the obvious gaps. :-)
>
> Same for sense types 0, 3, 5, 6, ...
>
> Just name the sense types 0 and 1, similar to what all other
> OF interrupt controller bindings do.
I'm not really keen on changing the values at this point. I think we
are stuck with them.
- k
^ permalink raw reply
* [PATCH 1/1] powerpc: Add H_ILLAN_ATTRIBUTES
From: Brian King @ 2007-07-10 14:41 UTC (permalink / raw)
To: paulus; +Cc: brking, linuxppc-dev
Adds the H_ILLAN_ATTRIBUTES hcall
Signed-off-by: Brian King <brking@linux.vnet.ibm.com>
---
linux-2.6-bjking1/include/asm-powerpc/hvcall.h | 1 +
1 file changed, 1 insertion(+)
diff -puN include/asm-powerpc/hvcall.h~powerpc_illan_attrs include/asm-powerpc/hvcall.h
--- linux-2.6/include/asm-powerpc/hvcall.h~powerpc_illan_attrs 2007-07-10 09:37:57.000000000 -0500
+++ linux-2.6-bjking1/include/asm-powerpc/hvcall.h 2007-07-10 09:37:57.000000000 -0500
@@ -206,6 +206,7 @@
#define H_FREE_LOGICAL_LAN_BUFFER 0x1D4
#define H_QUERY_INT_STATE 0x1E4
#define H_POLL_PENDING 0x1D8
+#define H_ILLAN_ATTRIBUTES 0x244
#define H_JOIN 0x298
#define H_VASI_STATE 0x2A4
#define H_ENABLE_CRQ 0x2B0
_
^ permalink raw reply
* [PATCH v3][POWERPC] document ipic level/sense info
From: Stuart Yoder @ 2007-07-10 14:51 UTC (permalink / raw)
To: paulus; +Cc: linuxppc-dev
document level/sense encoding info for IPIC
interrupt controllers
Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com>
---
Documentation/powerpc/booting-without-of.txt | 19 ++++++++++++++++++-
1 files changed, 18 insertions(+), 1 deletions(-)
diff --git a/Documentation/powerpc/booting-without-of.txt b/Documentation/powerpc/booting-without-of.txt
index c169299..e7a465c 100644
--- a/Documentation/powerpc/booting-without-of.txt
+++ b/Documentation/powerpc/booting-without-of.txt
@@ -50,13 +50,14 @@ Table of Contents
g) Freescale SOC SEC Security Engines
h) Board Control and Status (BCSR)
i) Freescale QUICC Engine module (QE)
- g) Flash chip nodes
+ j) Flash chip nodes
VII - Specifying interrupt information for devices
1) interrupts property
2) interrupt-parent property
3) OpenPIC Interrupt Controllers
4) ISA Interrupt Controllers
+ 5) IPIC Interrupt Controllers
Appendix A - Sample SOC node for MPC8540
@@ -1878,6 +1879,22 @@ encodings listed below:
2 = high to low edge sensitive type enabled
3 = low to high edge sensitive type enabled
+5) Freescale IPIC Interrupt Controllers
+---------------------------------------
+
+IPIC interrupt controllers are specific to Freescale 83xx
+SOCs. Two cells are required to encode interrupt information.
+The first cell defines the interrupt number. The second cell
+defines the sense and level information.
+
+Sense and level information follows the Linux convention
+(specified in include/linux/interrupt.h) and should be encoded
+as follows:
+
+ 2 = high to low edge sense type enabled
+ 8 = active low level sense type enabled
+
+Note: other level/sense types (0,1,4, etc) are not supported.
Appendix A - Sample SOC node for MPC8540
========================================
--
1.5.0.3
^ permalink raw reply related
* Re: [PATCH] xilinxfb: Parameterize xilinxfb platform device registration
From: Grant Likely @ 2007-07-10 14:56 UTC (permalink / raw)
To: Andrei Konovalov; +Cc: linuxppc-dev, paulus
In-Reply-To: <46934496.40805@ru.mvista.com>
On 7/10/07, Andrei Konovalov <akonovalov@ru.mvista.com> wrote:
> Grant Likely wrote:
> > From: Grant Likely <grant.likely@secretlab.ca>
> >
> > This patch allows multiple xilinxfb devices to be registered and used
> >
> > Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
> > cc: Andrei Konovalov <akonovalov@ru.mvista.com>
> > ---
>
> Looks OK for me.
Paulus, can you please pick this one up?
Thanks,
g.
--
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.
grant.likely@secretlab.ca
(403) 399-0195
^ permalink raw reply
* Re: [PATCH v3][POWERPC] document ipic level/sense info
From: Grant Likely @ 2007-07-10 15:03 UTC (permalink / raw)
To: Stuart Yoder; +Cc: linuxppc-dev, paulus
In-Reply-To: <200707101451.l6AEp9A3019214@ld0164-tx32.am.freescale.net>
On 7/10/07, Stuart Yoder <b08248@freescale.com> wrote:
> document level/sense encoding info for IPIC
> interrupt controllers
>
> Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com>
> ---
> + 2 = high to low edge sense type enabled
> + 8 = active low level sense type enabled
> +
> +Note: other level/sense types (0,1,4, etc) are not supported.
Perfect! :-)
Acked-by: Grant Likely <grant.likely@secretlab.ca>
--
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.
grant.likely@secretlab.ca
(403) 399-0195
^ permalink raw reply
* [PATCH] Consolidate mm_context_t definition in mmu.h
From: Josh Boyer @ 2007-07-10 15:01 UTC (permalink / raw)
To: paulus; +Cc: linuxppc-dev, david
All of the platforms except PPC64 share a common mm_context_t definition.
Defining it in mmu.h avoids duplicating it in the platform specific mmu
header files.
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
---
include/asm-powerpc/mmu-44x.h | 5 -----
include/asm-powerpc/mmu-8xx.h | 4 ----
include/asm-powerpc/mmu-fsl-booke.h | 4 ----
include/asm-powerpc/mmu-hash32.h | 5 -----
include/asm-powerpc/mmu-hash64.h | 16 ----------------
include/asm-powerpc/mmu.h | 28 ++++++++++++++++++++++++++++
6 files changed, 28 insertions(+), 34 deletions(-)
--- linux-2.6.orig/include/asm-powerpc/mmu-44x.h
+++ linux-2.6/include/asm-powerpc/mmu-44x.h
@@ -55,11 +55,6 @@
typedef unsigned long long phys_addr_t;
-typedef struct {
- unsigned long id;
- unsigned long vdso_base;
-} mm_context_t;
-
#endif /* !__ASSEMBLY__ */
#ifndef CONFIG_PPC_EARLY_DEBUG_44x
--- linux-2.6.orig/include/asm-powerpc/mmu-8xx.h
+++ linux-2.6/include/asm-powerpc/mmu-8xx.h
@@ -138,10 +138,6 @@
#ifndef __ASSEMBLY__
typedef unsigned long phys_addr_t;
-typedef struct {
- unsigned long id;
- unsigned long vdso_base;
-} mm_context_t;
#endif /* !__ASSEMBLY__ */
#endif /* _ASM_POWERPC_MMU_8XX_H_ */
--- linux-2.6.orig/include/asm-powerpc/mmu-fsl-booke.h
+++ linux-2.6/include/asm-powerpc/mmu-fsl-booke.h
@@ -79,10 +79,6 @@ typedef unsigned long phys_addr_t;
typedef unsigned long long phys_addr_t;
#endif
-typedef struct {
- unsigned long id;
- unsigned long vdso_base;
-} mm_context_t;
#endif /* !__ASSEMBLY__ */
#endif /* _ASM_POWERPC_MMU_FSL_BOOKE_H_ */
--- linux-2.6.orig/include/asm-powerpc/mmu-hash32.h
+++ linux-2.6/include/asm-powerpc/mmu-hash32.h
@@ -79,11 +79,6 @@ struct hash_pte {
unsigned long pp:2; /* Page protection */
};
-typedef struct {
- unsigned long id;
- unsigned long vdso_base;
-} mm_context_t;
-
typedef unsigned long phys_addr_t;
#endif /* !__ASSEMBLY__ */
--- linux-2.6.orig/include/asm-powerpc/mmu-hash64.h
+++ linux-2.6/include/asm-powerpc/mmu-hash64.h
@@ -359,22 +359,6 @@ extern void stab_initialize(unsigned lon
#ifndef __ASSEMBLY__
-typedef unsigned long mm_context_id_t;
-
-typedef struct {
- mm_context_id_t id;
- u16 user_psize; /* page size index */
-
-#ifdef CONFIG_PPC_MM_SLICES
- u64 low_slices_psize; /* SLB page size encodings */
- u64 high_slices_psize; /* 4 bits per slice for now */
-#else
- u16 sllp; /* SLB page size encoding */
-#endif
- unsigned long vdso_base;
-} mm_context_t;
-
-
static inline unsigned long vsid_scramble(unsigned long protovsid)
{
#if 0
--- linux-2.6.orig/include/asm-powerpc/mmu.h
+++ linux-2.6/include/asm-powerpc/mmu.h
@@ -19,5 +19,33 @@
# include <asm/mmu-8xx.h>
#endif
+#ifndef __ASSEMBLY__
+
+#ifdef CONFIG_PPC64
+typedef unsigned long mm_context_id_t;
+
+typedef struct {
+ mm_context_id_t id;
+ u16 user_psize; /* page size index */
+
+#ifdef CONFIG_PPC_MM_SLICES
+ u64 low_slices_psize; /* SLB page size encodings */
+ u64 high_slices_psize; /* 4 bits per slice for now */
+#else
+ u16 sllp; /* SLB page size encoding */
+#endif
+ unsigned long vdso_base;
+} mm_context_t;
+
+#else /* !CONFIG_PPC64 */
+
+typedef struct {
+ unsigned long id;
+ unsigned long vdso_base;
+} mm_context_t;
+
+#endif /* CONFIG_PPC64 */
+#endif /* !__ASSEMBLY__ */
+
#endif /* __KERNEL__ */
#endif /* _ASM_POWERPC_MMU_H_ */
^ permalink raw reply
* [patch 0/6] Unify the PCI/PCI Express support for 83xx/85xx/86xx
From: Zang Roy-r61911 @ 2007-07-10 15:50 UTC (permalink / raw)
To: Kumar Gala, Paul Mackerras; +Cc: linuxppc-dev list
This series of patches do:
(1) unify the PCI/PCI express support
for 83xx/85xx/86xx.
(2) Add basic PCI Express support for mpc8548 Rev 2.0
board.
(3) Add basic PCI support for mpc8568mds board.
The patches have been tested on 8548 rev2.0 with Arcadia 3.1
board, mpc8568mds board and 8641HPCN board.
Some of them have been in the tree on opensource.freescale.com.
I regenerated them based on my previous patches and comments.
The baseline is Kumar's current tree for paulus.
The VIA support on CDS board and PCI/E support for
8544DS board will be in next series of patches :-).
^ permalink raw reply
* [patch 1/6] Create common fsl pci/e files based on 86xx platform
From: Zang Roy-r61911 @ 2007-07-10 15:51 UTC (permalink / raw)
To: Kumar Gala, Paul Mackerras; +Cc: linuxppc-dev list
From: Roy Zang <tie-fei.zang@freescale.com>
Move
arch/powerpc/platforms/86xx/pci.c -> arch/powerpc/sysdev/fsl_pci.c
arch/powerpc/sysdev/fsl_pcie.h -> arch/powerpc/sysdev/fsl_pci.h
as the base to unify 83xx/85xx/86xx pci and pcie.
Add CONFIG_FSL_PCI to build fsl_pci.c for Freescale pci and pcie option.
The code is still work for 86xx platform.
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
---
arch/powerpc/Kconfig | 4 +
arch/powerpc/platforms/86xx/Kconfig | 1 +
arch/powerpc/platforms/86xx/Makefile | 1 -
arch/powerpc/platforms/86xx/pci.c | 238 ----------------------------------
arch/powerpc/sysdev/Makefile | 1 +
arch/powerpc/sysdev/fsl_pci.c | 238 ++++++++++++++++++++++++++++++++++
arch/powerpc/sysdev/fsl_pci.h | 94 +++++++++++++
arch/powerpc/sysdev/fsl_pcie.h | 94 -------------
8 files changed, 338 insertions(+), 333 deletions(-)
delete mode 100644 arch/powerpc/platforms/86xx/pci.c
create mode 100644 arch/powerpc/sysdev/fsl_pci.c
create mode 100644 arch/powerpc/sysdev/fsl_pci.h
delete mode 100644 arch/powerpc/sysdev/fsl_pcie.h
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index cbfbd98..8c780bf 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -419,6 +419,10 @@ config SBUS
config FSL_SOC
bool
+config FSL_PCI
+ bool
+ depends on PPC_86xx
+
# Yes MCA RS/6000s exist but Linux-PPC does not currently support any
config MCA
bool
diff --git a/arch/powerpc/platforms/86xx/Kconfig b/arch/powerpc/platforms/86xx/Kconfig
index 0faebfd..c848173 100644
--- a/arch/powerpc/platforms/86xx/Kconfig
+++ b/arch/powerpc/platforms/86xx/Kconfig
@@ -16,6 +16,7 @@ config MPC8641
bool
select PPC_INDIRECT_PCI
select PPC_INDIRECT_PCI_BE
+ select FSL_PCI
select PPC_UDBG_16550
select MPIC
default y if MPC8641_HPCN
diff --git a/arch/powerpc/platforms/86xx/Makefile b/arch/powerpc/platforms/86xx/Makefile
index 418fd8f..3376c77 100644
--- a/arch/powerpc/platforms/86xx/Makefile
+++ b/arch/powerpc/platforms/86xx/Makefile
@@ -4,4 +4,3 @@
obj-$(CONFIG_SMP) += mpc86xx_smp.o
obj-$(CONFIG_MPC8641_HPCN) += mpc86xx_hpcn.o
-obj-$(CONFIG_PCI) += pci.o
diff --git a/arch/powerpc/platforms/86xx/pci.c b/arch/powerpc/platforms/86xx/pci.c
deleted file mode 100644
index 73cd5b0..0000000
--- a/arch/powerpc/platforms/86xx/pci.c
+++ /dev/null
@@ -1,238 +0,0 @@
-/*
- * MPC86XX pci setup code
- *
- * Recode: ZHANG WEI <wei.zhang@freescale.com>
- * Initial author: Xianghua Xiao <x.xiao@freescale.com>
- *
- * Copyright 2006 Freescale Semiconductor Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- */
-
-#include <linux/types.h>
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/pci.h>
-#include <linux/serial.h>
-
-#include <asm/system.h>
-#include <asm/atomic.h>
-#include <asm/io.h>
-#include <asm/prom.h>
-#include <asm/pci-bridge.h>
-#include <sysdev/fsl_soc.h>
-#include <sysdev/fsl_pcie.h>
-
-#include "mpc86xx.h"
-
-#undef DEBUG
-
-#ifdef DEBUG
-#define DBG(fmt, args...) printk(KERN_ERR "%s: " fmt, __FUNCTION__, ## args)
-#else
-#define DBG(fmt, args...)
-#endif
-
-struct pcie_outbound_window_regs {
- uint pexotar; /* 0x.0 - PCI Express outbound translation address register */
- uint pexotear; /* 0x.4 - PCI Express outbound translation extended address register */
- uint pexowbar; /* 0x.8 - PCI Express outbound window base address register */
- char res1[4];
- uint pexowar; /* 0x.10 - PCI Express outbound window attributes register */
- char res2[12];
-};
-
-struct pcie_inbound_window_regs {
- uint pexitar; /* 0x.0 - PCI Express inbound translation address register */
- char res1[4];
- uint pexiwbar; /* 0x.8 - PCI Express inbound window base address register */
- uint pexiwbear; /* 0x.c - PCI Express inbound window base extended address register */
- uint pexiwar; /* 0x.10 - PCI Express inbound window attributes register */
- char res2[12];
-};
-
-static void __init setup_pcie_atmu(struct pci_controller *hose, struct resource *rsrc)
-{
- volatile struct ccsr_pex *pcie;
- volatile struct pcie_outbound_window_regs *pcieow;
- volatile struct pcie_inbound_window_regs *pcieiw;
- int i = 0;
-
- DBG("PCIE memory map start 0x%x, size 0x%x\n", rsrc->start,
- rsrc->end - rsrc->start + 1);
- pcie = ioremap(rsrc->start, rsrc->end - rsrc->start + 1);
-
- /* Disable all windows (except pexowar0 since its ignored) */
- pcie->pexowar1 = 0;
- pcie->pexowar2 = 0;
- pcie->pexowar3 = 0;
- pcie->pexowar4 = 0;
- pcie->pexiwar1 = 0;
- pcie->pexiwar2 = 0;
- pcie->pexiwar3 = 0;
-
- pcieow = (struct pcie_outbound_window_regs *)&pcie->pexotar1;
- pcieiw = (struct pcie_inbound_window_regs *)&pcie->pexitar1;
-
- /* Setup outbound MEM window */
- for(i = 0; i < 3; i++)
- if (hose->mem_resources[i].flags & IORESOURCE_MEM){
- DBG("PCIE MEM resource start 0x%08x, size 0x%08x.\n",
- hose->mem_resources[i].start,
- hose->mem_resources[i].end
- - hose->mem_resources[i].start + 1);
- pcieow->pexotar = (hose->mem_resources[i].start) >> 12
- & 0x000fffff;
- pcieow->pexotear = 0;
- pcieow->pexowbar = (hose->mem_resources[i].start) >> 12
- & 0x000fffff;
- /* Enable, Mem R/W */
- pcieow->pexowar = 0x80044000 |
- (__ilog2(hose->mem_resources[i].end
- - hose->mem_resources[i].start + 1)
- - 1);
- pcieow++;
- }
-
- /* Setup outbound IO window */
- if (hose->io_resource.flags & IORESOURCE_IO){
- DBG("PCIE IO resource start 0x%08x, size 0x%08x, phy base 0x%08x.\n",
- hose->io_resource.start,
- hose->io_resource.end - hose->io_resource.start + 1,
- hose->io_base_phys);
- pcieow->pexotar = (hose->io_resource.start) >> 12 & 0x000fffff;
- pcieow->pexotear = 0;
- pcieow->pexowbar = (hose->io_base_phys) >> 12 & 0x000fffff;
- /* Enable, IO R/W */
- pcieow->pexowar = 0x80088000 | (__ilog2(hose->io_resource.end
- - hose->io_resource.start + 1) - 1);
- }
-
- /* Setup 2G inbound Memory Window @ 0 */
- pcieiw->pexitar = 0x00000000;
- pcieiw->pexiwbar = 0x00000000;
- /* Enable, Prefetch, Local Mem, Snoop R/W, 2G */
- pcieiw->pexiwar = 0xa0f5501e;
-}
-
-static void __init
-mpc86xx_setup_pcie(struct pci_controller *hose, u32 pcie_offset, u32 pcie_size)
-{
- u16 cmd;
-
- DBG("PCIE host controller register offset 0x%08x, size 0x%08x.\n",
- pcie_offset, pcie_size);
-
- early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd);
- cmd |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY
- | PCI_COMMAND_IO;
- early_write_config_word(hose, 0, 0, PCI_COMMAND, cmd);
-
- early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80);
-}
-
-static void __devinit quirk_fsl_pcie_transparent(struct pci_dev *dev)
-{
- struct resource *res;
- int i, res_idx = PCI_BRIDGE_RESOURCES;
- struct pci_controller *hose;
-
- /*
- * Make the bridge be transparent.
- */
- dev->transparent = 1;
-
- hose = pci_bus_to_host(dev->bus);
- if (!hose) {
- printk(KERN_ERR "Can't find hose for bus %d\n",
- dev->bus->number);
- return;
- }
-
- if (hose->io_resource.flags) {
- res = &dev->resource[res_idx++];
- res->start = hose->io_resource.start;
- res->end = hose->io_resource.end;
- res->flags = hose->io_resource.flags;
- }
-
- for (i = 0; i < 3; i++) {
- res = &dev->resource[res_idx + i];
- res->start = hose->mem_resources[i].start;
- res->end = hose->mem_resources[i].end;
- res->flags = hose->mem_resources[i].flags;
- }
-}
-
-
-DECLARE_PCI_FIXUP_EARLY(0x1957, 0x7010, quirk_fsl_pcie_transparent);
-DECLARE_PCI_FIXUP_EARLY(0x1957, 0x7011, quirk_fsl_pcie_transparent);
-
-#define PCIE_LTSSM 0x404 /* PCIe Link Training and Status */
-#define PCIE_LTSSM_L0 0x16 /* L0 state */
-
-int __init mpc86xx_add_bridge(struct device_node *dev)
-{
- int len;
- struct pci_controller *hose;
- struct resource rsrc;
- const int *bus_range;
- int has_address = 0;
- int primary = 0;
- u16 val;
-
- DBG("Adding PCIE host bridge %s\n", dev->full_name);
-
- /* Fetch host bridge registers address */
- has_address = (of_address_to_resource(dev, 0, &rsrc) == 0);
-
- /* Get bus range if any */
- bus_range = of_get_property(dev, "bus-range", &len);
- if (bus_range == NULL || len < 2 * sizeof(int))
- printk(KERN_WARNING "Can't get bus-range for %s, assume"
- " bus 0\n", dev->full_name);
-
- pci_assign_all_buses = 1;
- hose = pcibios_alloc_controller(dev);
- if (!hose)
- return -ENOMEM;
-
- hose->indirect_type = PPC_INDIRECT_TYPE_EXT_REG |
- PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS;
-
- hose->first_busno = bus_range ? bus_range[0] : 0x0;
- hose->last_busno = bus_range ? bus_range[1] : 0xff;
-
- setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4);
-
- /* Probe the hose link training status */
- early_read_config_word(hose, 0, 0, PCIE_LTSSM, &val);
- if (val < PCIE_LTSSM_L0)
- return -ENXIO;
-
- /* Setup the PCIE host controller. */
- mpc86xx_setup_pcie(hose, rsrc.start, rsrc.end - rsrc.start + 1);
-
- if ((rsrc.start & 0xfffff) == 0x8000)
- primary = 1;
-
- printk(KERN_INFO "Found MPC86xx PCIE host bridge at 0x%08lx. "
- "Firmware bus number: %d->%d\n",
- (unsigned long) rsrc.start,
- hose->first_busno, hose->last_busno);
-
- DBG(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
- hose, hose->cfg_addr, hose->cfg_data);
-
- /* Interpret the "ranges" property */
- /* This also maps the I/O region and sets isa_io/mem_base */
- pci_process_bridge_OF_ranges(hose, dev, primary);
-
- /* Setup PEX window registers */
- setup_pcie_atmu(hose, &rsrc);
-
- return 0;
-}
diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile
index 7d8ac1b..0a9ae95 100644
--- a/arch/powerpc/sysdev/Makefile
+++ b/arch/powerpc/sysdev/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_PPC_PMI) += pmi.o
obj-$(CONFIG_U3_DART) += dart_iommu.o
obj-$(CONFIG_MMIO_NVRAM) += mmio_nvram.o
obj-$(CONFIG_FSL_SOC) += fsl_soc.o
+obj-$(CONFIG_FSL_PCI) += fsl_pci.o
obj-$(CONFIG_TSI108_BRIDGE) += tsi108_pci.o tsi108_dev.o
obj-$(CONFIG_QUICC_ENGINE) += qe_lib/
mv64x60-$(CONFIG_PCI) += mv64x60_pci.o
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
new file mode 100644
index 0000000..24ba1b6
--- /dev/null
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -0,0 +1,238 @@
+/*
+ * MPC86XX pci setup code
+ *
+ * Recode: ZHANG WEI <wei.zhang@freescale.com>
+ * Initial author: Xianghua Xiao <x.xiao@freescale.com>
+ *
+ * Copyright 2006 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/types.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/pci.h>
+#include <linux/serial.h>
+
+#include <asm/system.h>
+#include <asm/atomic.h>
+#include <asm/io.h>
+#include <asm/prom.h>
+#include <asm/pci-bridge.h>
+#include <sysdev/fsl_soc.h>
+#include <sysdev/fsl_pci.h>
+
+#include "../platforms/86xx/mpc86xx.h"
+
+#undef DEBUG
+
+#ifdef DEBUG
+#define DBG(fmt, args...) printk(KERN_ERR "%s: " fmt, __FUNCTION__, ## args)
+#else
+#define DBG(fmt, args...)
+#endif
+
+struct pcie_outbound_window_regs {
+ uint pexotar; /* 0x.0 - PCI Express outbound translation address register */
+ uint pexotear; /* 0x.4 - PCI Express outbound translation extended address register */
+ uint pexowbar; /* 0x.8 - PCI Express outbound window base address register */
+ char res1[4];
+ uint pexowar; /* 0x.10 - PCI Express outbound window attributes register */
+ char res2[12];
+};
+
+struct pcie_inbound_window_regs {
+ uint pexitar; /* 0x.0 - PCI Express inbound translation address register */
+ char res1[4];
+ uint pexiwbar; /* 0x.8 - PCI Express inbound window base address register */
+ uint pexiwbear; /* 0x.c - PCI Express inbound window base extended address register */
+ uint pexiwar; /* 0x.10 - PCI Express inbound window attributes register */
+ char res2[12];
+};
+
+static void __init setup_pcie_atmu(struct pci_controller *hose, struct resource *rsrc)
+{
+ volatile struct ccsr_pex *pcie;
+ volatile struct pcie_outbound_window_regs *pcieow;
+ volatile struct pcie_inbound_window_regs *pcieiw;
+ int i = 0;
+
+ DBG("PCIE memory map start 0x%x, size 0x%x\n", rsrc->start,
+ rsrc->end - rsrc->start + 1);
+ pcie = ioremap(rsrc->start, rsrc->end - rsrc->start + 1);
+
+ /* Disable all windows (except pexowar0 since its ignored) */
+ pcie->pexowar1 = 0;
+ pcie->pexowar2 = 0;
+ pcie->pexowar3 = 0;
+ pcie->pexowar4 = 0;
+ pcie->pexiwar1 = 0;
+ pcie->pexiwar2 = 0;
+ pcie->pexiwar3 = 0;
+
+ pcieow = (struct pcie_outbound_window_regs *)&pcie->pexotar1;
+ pcieiw = (struct pcie_inbound_window_regs *)&pcie->pexitar1;
+
+ /* Setup outbound MEM window */
+ for(i = 0; i < 3; i++)
+ if (hose->mem_resources[i].flags & IORESOURCE_MEM){
+ DBG("PCIE MEM resource start 0x%08x, size 0x%08x.\n",
+ hose->mem_resources[i].start,
+ hose->mem_resources[i].end
+ - hose->mem_resources[i].start + 1);
+ pcieow->pexotar = (hose->mem_resources[i].start) >> 12
+ & 0x000fffff;
+ pcieow->pexotear = 0;
+ pcieow->pexowbar = (hose->mem_resources[i].start) >> 12
+ & 0x000fffff;
+ /* Enable, Mem R/W */
+ pcieow->pexowar = 0x80044000 |
+ (__ilog2(hose->mem_resources[i].end
+ - hose->mem_resources[i].start + 1)
+ - 1);
+ pcieow++;
+ }
+
+ /* Setup outbound IO window */
+ if (hose->io_resource.flags & IORESOURCE_IO){
+ DBG("PCIE IO resource start 0x%08x, size 0x%08x, phy base 0x%08x.\n",
+ hose->io_resource.start,
+ hose->io_resource.end - hose->io_resource.start + 1,
+ hose->io_base_phys);
+ pcieow->pexotar = (hose->io_resource.start) >> 12 & 0x000fffff;
+ pcieow->pexotear = 0;
+ pcieow->pexowbar = (hose->io_base_phys) >> 12 & 0x000fffff;
+ /* Enable, IO R/W */
+ pcieow->pexowar = 0x80088000 | (__ilog2(hose->io_resource.end
+ - hose->io_resource.start + 1) - 1);
+ }
+
+ /* Setup 2G inbound Memory Window @ 0 */
+ pcieiw->pexitar = 0x00000000;
+ pcieiw->pexiwbar = 0x00000000;
+ /* Enable, Prefetch, Local Mem, Snoop R/W, 2G */
+ pcieiw->pexiwar = 0xa0f5501e;
+}
+
+static void __init
+mpc86xx_setup_pcie(struct pci_controller *hose, u32 pcie_offset, u32 pcie_size)
+{
+ u16 cmd;
+
+ DBG("PCIE host controller register offset 0x%08x, size 0x%08x.\n",
+ pcie_offset, pcie_size);
+
+ early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd);
+ cmd |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY
+ | PCI_COMMAND_IO;
+ early_write_config_word(hose, 0, 0, PCI_COMMAND, cmd);
+
+ early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80);
+}
+
+static void __devinit quirk_fsl_pcie_transparent(struct pci_dev *dev)
+{
+ struct resource *res;
+ int i, res_idx = PCI_BRIDGE_RESOURCES;
+ struct pci_controller *hose;
+
+ /*
+ * Make the bridge be transparent.
+ */
+ dev->transparent = 1;
+
+ hose = pci_bus_to_host(dev->bus);
+ if (!hose) {
+ printk(KERN_ERR "Can't find hose for bus %d\n",
+ dev->bus->number);
+ return;
+ }
+
+ if (hose->io_resource.flags) {
+ res = &dev->resource[res_idx++];
+ res->start = hose->io_resource.start;
+ res->end = hose->io_resource.end;
+ res->flags = hose->io_resource.flags;
+ }
+
+ for (i = 0; i < 3; i++) {
+ res = &dev->resource[res_idx + i];
+ res->start = hose->mem_resources[i].start;
+ res->end = hose->mem_resources[i].end;
+ res->flags = hose->mem_resources[i].flags;
+ }
+}
+
+
+DECLARE_PCI_FIXUP_EARLY(0x1957, 0x7010, quirk_fsl_pcie_transparent);
+DECLARE_PCI_FIXUP_EARLY(0x1957, 0x7011, quirk_fsl_pcie_transparent);
+
+#define PCIE_LTSSM 0x404 /* PCIe Link Training and Status */
+#define PCIE_LTSSM_L0 0x16 /* L0 state */
+
+int __init mpc86xx_add_bridge(struct device_node *dev)
+{
+ int len;
+ struct pci_controller *hose;
+ struct resource rsrc;
+ const int *bus_range;
+ int has_address = 0;
+ int primary = 0;
+ u16 val;
+
+ DBG("Adding PCIE host bridge %s\n", dev->full_name);
+
+ /* Fetch host bridge registers address */
+ has_address = (of_address_to_resource(dev, 0, &rsrc) == 0);
+
+ /* Get bus range if any */
+ bus_range = of_get_property(dev, "bus-range", &len);
+ if (bus_range == NULL || len < 2 * sizeof(int))
+ printk(KERN_WARNING "Can't get bus-range for %s, assume"
+ " bus 0\n", dev->full_name);
+
+ pci_assign_all_buses = 1;
+ hose = pcibios_alloc_controller(dev);
+ if (!hose)
+ return -ENOMEM;
+
+ hose->indirect_type = PPC_INDIRECT_TYPE_EXT_REG |
+ PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS;
+
+ hose->first_busno = bus_range ? bus_range[0] : 0x0;
+ hose->last_busno = bus_range ? bus_range[1] : 0xff;
+
+ setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4);
+
+ /* Probe the hose link training status */
+ early_read_config_word(hose, 0, 0, PCIE_LTSSM, &val);
+ if (val < PCIE_LTSSM_L0)
+ return -ENXIO;
+
+ /* Setup the PCIE host controller. */
+ mpc86xx_setup_pcie(hose, rsrc.start, rsrc.end - rsrc.start + 1);
+
+ if ((rsrc.start & 0xfffff) == 0x8000)
+ primary = 1;
+
+ printk(KERN_INFO "Found MPC86xx PCIE host bridge at 0x%08lx. "
+ "Firmware bus number: %d->%d\n",
+ (unsigned long) rsrc.start,
+ hose->first_busno, hose->last_busno);
+
+ DBG(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
+ hose, hose->cfg_addr, hose->cfg_data);
+
+ /* Interpret the "ranges" property */
+ /* This also maps the I/O region and sets isa_io/mem_base */
+ pci_process_bridge_OF_ranges(hose, dev, primary);
+
+ /* Setup PEX window registers */
+ setup_pcie_atmu(hose, &rsrc);
+
+ return 0;
+}
diff --git a/arch/powerpc/sysdev/fsl_pci.h b/arch/powerpc/sysdev/fsl_pci.h
new file mode 100644
index 0000000..8d9779c
--- /dev/null
+++ b/arch/powerpc/sysdev/fsl_pci.h
@@ -0,0 +1,94 @@
+/*
+ * MPC85xx/86xx PCI Express structure define
+ *
+ * Copyright 2007 Freescale Semiconductor, Inc
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ */
+
+#ifdef __KERNEL__
+#ifndef __POWERPC_FSL_PCIE_H
+#define __POWERPC_FSL_PCIE_H
+
+/* PCIE Express IO block registers in 85xx/86xx */
+
+struct ccsr_pex {
+ __be32 __iomem pex_config_addr; /* 0x.000 - PCI Express Configuration Address Register */
+ __be32 __iomem pex_config_data; /* 0x.004 - PCI Express Configuration Data Register */
+ u8 __iomem res1[4];
+ __be32 __iomem pex_otb_cpl_tor; /* 0x.00c - PCI Express Outbound completion timeout register */
+ __be32 __iomem pex_conf_tor; /* 0x.010 - PCI Express configuration timeout register */
+ u8 __iomem res2[12];
+ __be32 __iomem pex_pme_mes_dr; /* 0x.020 - PCI Express PME and message detect register */
+ __be32 __iomem pex_pme_mes_disr; /* 0x.024 - PCI Express PME and message disable register */
+ __be32 __iomem pex_pme_mes_ier; /* 0x.028 - PCI Express PME and message interrupt enable register */
+ __be32 __iomem pex_pmcr; /* 0x.02c - PCI Express power management command register */
+ u8 __iomem res3[3024];
+ __be32 __iomem pexotar0; /* 0x.c00 - PCI Express outbound translation address register 0 */
+ __be32 __iomem pexotear0; /* 0x.c04 - PCI Express outbound translation extended address register 0*/
+ u8 __iomem res4[8];
+ __be32 __iomem pexowar0; /* 0x.c10 - PCI Express outbound window attributes register 0*/
+ u8 __iomem res5[12];
+ __be32 __iomem pexotar1; /* 0x.c20 - PCI Express outbound translation address register 1 */
+ __be32 __iomem pexotear1; /* 0x.c24 - PCI Express outbound translation extended address register 1*/
+ __be32 __iomem pexowbar1; /* 0x.c28 - PCI Express outbound window base address register 1*/
+ u8 __iomem res6[4];
+ __be32 __iomem pexowar1; /* 0x.c30 - PCI Express outbound window attributes register 1*/
+ u8 __iomem res7[12];
+ __be32 __iomem pexotar2; /* 0x.c40 - PCI Express outbound translation address register 2 */
+ __be32 __iomem pexotear2; /* 0x.c44 - PCI Express outbound translation extended address register 2*/
+ __be32 __iomem pexowbar2; /* 0x.c48 - PCI Express outbound window base address register 2*/
+ u8 __iomem res8[4];
+ __be32 __iomem pexowar2; /* 0x.c50 - PCI Express outbound window attributes register 2*/
+ u8 __iomem res9[12];
+ __be32 __iomem pexotar3; /* 0x.c60 - PCI Express outbound translation address register 3 */
+ __be32 __iomem pexotear3; /* 0x.c64 - PCI Express outbound translation extended address register 3*/
+ __be32 __iomem pexowbar3; /* 0x.c68 - PCI Express outbound window base address register 3*/
+ u8 __iomem res10[4];
+ __be32 __iomem pexowar3; /* 0x.c70 - PCI Express outbound window attributes register 3*/
+ u8 __iomem res11[12];
+ __be32 __iomem pexotar4; /* 0x.c80 - PCI Express outbound translation address register 4 */
+ __be32 __iomem pexotear4; /* 0x.c84 - PCI Express outbound translation extended address register 4*/
+ __be32 __iomem pexowbar4; /* 0x.c88 - PCI Express outbound window base address register 4*/
+ u8 __iomem res12[4];
+ __be32 __iomem pexowar4; /* 0x.c90 - PCI Express outbound window attributes register 4*/
+ u8 __iomem res13[12];
+ u8 __iomem res14[256];
+ __be32 __iomem pexitar3; /* 0x.da0 - PCI Express inbound translation address register 3 */
+ u8 __iomem res15[4];
+ __be32 __iomem pexiwbar3; /* 0x.da8 - PCI Express inbound window base address register 3 */
+ __be32 __iomem pexiwbear3; /* 0x.dac - PCI Express inbound window base extended address register 3 */
+ __be32 __iomem pexiwar3; /* 0x.db0 - PCI Express inbound window attributes register 3 */
+ u8 __iomem res16[12];
+ __be32 __iomem pexitar2; /* 0x.dc0 - PCI Express inbound translation address register 2 */
+ u8 __iomem res17[4];
+ __be32 __iomem pexiwbar2; /* 0x.dc8 - PCI Express inbound window base address register 2 */
+ __be32 __iomem pexiwbear2; /* 0x.dcc - PCI Express inbound window base extended address register 2 */
+ __be32 __iomem pexiwar2; /* 0x.dd0 - PCI Express inbound window attributes register 2 */
+ u8 __iomem res18[12];
+ __be32 __iomem pexitar1; /* 0x.de0 - PCI Express inbound translation address register 2 */
+ u8 __iomem res19[4];
+ __be32 __iomem pexiwbar1; /* 0x.de8 - PCI Express inbound window base address register 2 */
+ __be32 __iomem pexiwbear1; /* 0x.dec - PCI Express inbound window base extended address register 2 */
+ __be32 __iomem pexiwar1; /* 0x.df0 - PCI Express inbound window attributes register 2 */
+ u8 __iomem res20[12];
+ __be32 __iomem pex_err_dr; /* 0x.e00 - PCI Express error detect register */
+ u8 __iomem res21[4];
+ __be32 __iomem pex_err_en; /* 0x.e08 - PCI Express error interrupt enable register */
+ u8 __iomem res22[4];
+ __be32 __iomem pex_err_disr; /* 0x.e10 - PCI Express error disable register */
+ u8 __iomem res23[12];
+ __be32 __iomem pex_err_cap_stat; /* 0x.e20 - PCI Express error capture status register */
+ u8 __iomem res24[4];
+ __be32 __iomem pex_err_cap_r0; /* 0x.e28 - PCI Express error capture register 0 */
+ __be32 __iomem pex_err_cap_r1; /* 0x.e2c - PCI Express error capture register 0 */
+ __be32 __iomem pex_err_cap_r2; /* 0x.e30 - PCI Express error capture register 0 */
+ __be32 __iomem pex_err_cap_r3; /* 0x.e34 - PCI Express error capture register 0 */
+};
+
+#endif /* __POWERPC_FSL_PCIE_H */
+#endif /* __KERNEL__ */
diff --git a/arch/powerpc/sysdev/fsl_pcie.h b/arch/powerpc/sysdev/fsl_pcie.h
deleted file mode 100644
index 8d9779c..0000000
--- a/arch/powerpc/sysdev/fsl_pcie.h
+++ /dev/null
@@ -1,94 +0,0 @@
-/*
- * MPC85xx/86xx PCI Express structure define
- *
- * Copyright 2007 Freescale Semiconductor, Inc
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- */
-
-#ifdef __KERNEL__
-#ifndef __POWERPC_FSL_PCIE_H
-#define __POWERPC_FSL_PCIE_H
-
-/* PCIE Express IO block registers in 85xx/86xx */
-
-struct ccsr_pex {
- __be32 __iomem pex_config_addr; /* 0x.000 - PCI Express Configuration Address Register */
- __be32 __iomem pex_config_data; /* 0x.004 - PCI Express Configuration Data Register */
- u8 __iomem res1[4];
- __be32 __iomem pex_otb_cpl_tor; /* 0x.00c - PCI Express Outbound completion timeout register */
- __be32 __iomem pex_conf_tor; /* 0x.010 - PCI Express configuration timeout register */
- u8 __iomem res2[12];
- __be32 __iomem pex_pme_mes_dr; /* 0x.020 - PCI Express PME and message detect register */
- __be32 __iomem pex_pme_mes_disr; /* 0x.024 - PCI Express PME and message disable register */
- __be32 __iomem pex_pme_mes_ier; /* 0x.028 - PCI Express PME and message interrupt enable register */
- __be32 __iomem pex_pmcr; /* 0x.02c - PCI Express power management command register */
- u8 __iomem res3[3024];
- __be32 __iomem pexotar0; /* 0x.c00 - PCI Express outbound translation address register 0 */
- __be32 __iomem pexotear0; /* 0x.c04 - PCI Express outbound translation extended address register 0*/
- u8 __iomem res4[8];
- __be32 __iomem pexowar0; /* 0x.c10 - PCI Express outbound window attributes register 0*/
- u8 __iomem res5[12];
- __be32 __iomem pexotar1; /* 0x.c20 - PCI Express outbound translation address register 1 */
- __be32 __iomem pexotear1; /* 0x.c24 - PCI Express outbound translation extended address register 1*/
- __be32 __iomem pexowbar1; /* 0x.c28 - PCI Express outbound window base address register 1*/
- u8 __iomem res6[4];
- __be32 __iomem pexowar1; /* 0x.c30 - PCI Express outbound window attributes register 1*/
- u8 __iomem res7[12];
- __be32 __iomem pexotar2; /* 0x.c40 - PCI Express outbound translation address register 2 */
- __be32 __iomem pexotear2; /* 0x.c44 - PCI Express outbound translation extended address register 2*/
- __be32 __iomem pexowbar2; /* 0x.c48 - PCI Express outbound window base address register 2*/
- u8 __iomem res8[4];
- __be32 __iomem pexowar2; /* 0x.c50 - PCI Express outbound window attributes register 2*/
- u8 __iomem res9[12];
- __be32 __iomem pexotar3; /* 0x.c60 - PCI Express outbound translation address register 3 */
- __be32 __iomem pexotear3; /* 0x.c64 - PCI Express outbound translation extended address register 3*/
- __be32 __iomem pexowbar3; /* 0x.c68 - PCI Express outbound window base address register 3*/
- u8 __iomem res10[4];
- __be32 __iomem pexowar3; /* 0x.c70 - PCI Express outbound window attributes register 3*/
- u8 __iomem res11[12];
- __be32 __iomem pexotar4; /* 0x.c80 - PCI Express outbound translation address register 4 */
- __be32 __iomem pexotear4; /* 0x.c84 - PCI Express outbound translation extended address register 4*/
- __be32 __iomem pexowbar4; /* 0x.c88 - PCI Express outbound window base address register 4*/
- u8 __iomem res12[4];
- __be32 __iomem pexowar4; /* 0x.c90 - PCI Express outbound window attributes register 4*/
- u8 __iomem res13[12];
- u8 __iomem res14[256];
- __be32 __iomem pexitar3; /* 0x.da0 - PCI Express inbound translation address register 3 */
- u8 __iomem res15[4];
- __be32 __iomem pexiwbar3; /* 0x.da8 - PCI Express inbound window base address register 3 */
- __be32 __iomem pexiwbear3; /* 0x.dac - PCI Express inbound window base extended address register 3 */
- __be32 __iomem pexiwar3; /* 0x.db0 - PCI Express inbound window attributes register 3 */
- u8 __iomem res16[12];
- __be32 __iomem pexitar2; /* 0x.dc0 - PCI Express inbound translation address register 2 */
- u8 __iomem res17[4];
- __be32 __iomem pexiwbar2; /* 0x.dc8 - PCI Express inbound window base address register 2 */
- __be32 __iomem pexiwbear2; /* 0x.dcc - PCI Express inbound window base extended address register 2 */
- __be32 __iomem pexiwar2; /* 0x.dd0 - PCI Express inbound window attributes register 2 */
- u8 __iomem res18[12];
- __be32 __iomem pexitar1; /* 0x.de0 - PCI Express inbound translation address register 2 */
- u8 __iomem res19[4];
- __be32 __iomem pexiwbar1; /* 0x.de8 - PCI Express inbound window base address register 2 */
- __be32 __iomem pexiwbear1; /* 0x.dec - PCI Express inbound window base extended address register 2 */
- __be32 __iomem pexiwar1; /* 0x.df0 - PCI Express inbound window attributes register 2 */
- u8 __iomem res20[12];
- __be32 __iomem pex_err_dr; /* 0x.e00 - PCI Express error detect register */
- u8 __iomem res21[4];
- __be32 __iomem pex_err_en; /* 0x.e08 - PCI Express error interrupt enable register */
- u8 __iomem res22[4];
- __be32 __iomem pex_err_disr; /* 0x.e10 - PCI Express error disable register */
- u8 __iomem res23[12];
- __be32 __iomem pex_err_cap_stat; /* 0x.e20 - PCI Express error capture status register */
- u8 __iomem res24[4];
- __be32 __iomem pex_err_cap_r0; /* 0x.e28 - PCI Express error capture register 0 */
- __be32 __iomem pex_err_cap_r1; /* 0x.e2c - PCI Express error capture register 0 */
- __be32 __iomem pex_err_cap_r2; /* 0x.e30 - PCI Express error capture register 0 */
- __be32 __iomem pex_err_cap_r3; /* 0x.e34 - PCI Express error capture register 0 */
-};
-
-#endif /* __POWERPC_FSL_PCIE_H */
-#endif /* __KERNEL__ */
--
1.5.1
^ permalink raw reply related
* [patch 2/6] Rewrite Freescale pci/pcie routing for 85xx/86xx pci/pcie controller
From: Zang Roy-r61911 @ 2007-07-10 15:51 UTC (permalink / raw)
To: Kumar Gala, Paul Mackerras; +Cc: linuxppc-dev list
From: Roy Zang <tie-fei.zang@freescale.com>
Rewrite Freescale pci/pcie routing for 83xx/85xx/86xx pci/pcie
controller.
The routing are common for 83xx/85xx/86xx pci/pcie host.
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
---
arch/powerpc/sysdev/fsl_pci.c | 244 ++++++++++++++++++-----------------------
arch/powerpc/sysdev/fsl_pci.h | 143 +++++++++++-------------
2 files changed, 172 insertions(+), 215 deletions(-)
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index 24ba1b6..5e15cfc 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -1,136 +1,98 @@
/*
- * MPC86XX pci setup code
+ * MPC85xx/86xx PCI/PCIE support routing.
*
- * Recode: ZHANG WEI <wei.zhang@freescale.com>
- * Initial author: Xianghua Xiao <x.xiao@freescale.com>
+ * Copyright 2007 Freescale Semiconductor, Inc
*
- * Copyright 2006 Freescale Semiconductor Inc.
+ * Initial author: Xianghua Xiao <x.xiao@freescale.com>
+ * Recode: ZHANG WEI <wei.zhang@freescale.com>
+ * Rewrite the routing for Frescale PCI and PCI Express
+ * Roy Zang <tie-fei.zang@freescale.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
-
-#include <linux/types.h>
-#include <linux/module.h>
-#include <linux/init.h>
+#include <linux/kernel.h>
#include <linux/pci.h>
-#include <linux/serial.h>
+#include <linux/delay.h>
+#include <linux/string.h>
+#include <linux/init.h>
+#include <linux/bootmem.h>
-#include <asm/system.h>
-#include <asm/atomic.h>
#include <asm/io.h>
#include <asm/prom.h>
#include <asm/pci-bridge.h>
+#include <asm/machdep.h>
#include <sysdev/fsl_soc.h>
#include <sysdev/fsl_pci.h>
-#include "../platforms/86xx/mpc86xx.h"
-
-#undef DEBUG
-
-#ifdef DEBUG
-#define DBG(fmt, args...) printk(KERN_ERR "%s: " fmt, __FUNCTION__, ## args)
-#else
-#define DBG(fmt, args...)
-#endif
-
-struct pcie_outbound_window_regs {
- uint pexotar; /* 0x.0 - PCI Express outbound translation address register */
- uint pexotear; /* 0x.4 - PCI Express outbound translation extended address register */
- uint pexowbar; /* 0x.8 - PCI Express outbound window base address register */
- char res1[4];
- uint pexowar; /* 0x.10 - PCI Express outbound window attributes register */
- char res2[12];
-};
-
-struct pcie_inbound_window_regs {
- uint pexitar; /* 0x.0 - PCI Express inbound translation address register */
- char res1[4];
- uint pexiwbar; /* 0x.8 - PCI Express inbound window base address register */
- uint pexiwbear; /* 0x.c - PCI Express inbound window base extended address register */
- uint pexiwar; /* 0x.10 - PCI Express inbound window attributes register */
- char res2[12];
-};
-
-static void __init setup_pcie_atmu(struct pci_controller *hose, struct resource *rsrc)
+/* atmu setup for fsl pci/pcie controller */
+void __init setup_pci_atmu(struct pci_controller *hose, struct resource *rsrc)
{
- volatile struct ccsr_pex *pcie;
- volatile struct pcie_outbound_window_regs *pcieow;
- volatile struct pcie_inbound_window_regs *pcieiw;
- int i = 0;
+ struct ccsr_pci __iomem *pci;
+ int i;
- DBG("PCIE memory map start 0x%x, size 0x%x\n", rsrc->start,
+ pr_debug("PCI memory map start 0x%x, size 0x%x\n", rsrc->start,
rsrc->end - rsrc->start + 1);
- pcie = ioremap(rsrc->start, rsrc->end - rsrc->start + 1);
-
- /* Disable all windows (except pexowar0 since its ignored) */
- pcie->pexowar1 = 0;
- pcie->pexowar2 = 0;
- pcie->pexowar3 = 0;
- pcie->pexowar4 = 0;
- pcie->pexiwar1 = 0;
- pcie->pexiwar2 = 0;
- pcie->pexiwar3 = 0;
-
- pcieow = (struct pcie_outbound_window_regs *)&pcie->pexotar1;
- pcieiw = (struct pcie_inbound_window_regs *)&pcie->pexitar1;
-
- /* Setup outbound MEM window */
- for(i = 0; i < 3; i++)
- if (hose->mem_resources[i].flags & IORESOURCE_MEM){
- DBG("PCIE MEM resource start 0x%08x, size 0x%08x.\n",
- hose->mem_resources[i].start,
- hose->mem_resources[i].end
- - hose->mem_resources[i].start + 1);
- pcieow->pexotar = (hose->mem_resources[i].start) >> 12
- & 0x000fffff;
- pcieow->pexotear = 0;
- pcieow->pexowbar = (hose->mem_resources[i].start) >> 12
- & 0x000fffff;
- /* Enable, Mem R/W */
- pcieow->pexowar = 0x80044000 |
- (__ilog2(hose->mem_resources[i].end
- - hose->mem_resources[i].start + 1)
- - 1);
- pcieow++;
- }
-
- /* Setup outbound IO window */
- if (hose->io_resource.flags & IORESOURCE_IO){
- DBG("PCIE IO resource start 0x%08x, size 0x%08x, phy base 0x%08x.\n",
- hose->io_resource.start,
- hose->io_resource.end - hose->io_resource.start + 1,
- hose->io_base_phys);
- pcieow->pexotar = (hose->io_resource.start) >> 12 & 0x000fffff;
- pcieow->pexotear = 0;
- pcieow->pexowbar = (hose->io_base_phys) >> 12 & 0x000fffff;
- /* Enable, IO R/W */
- pcieow->pexowar = 0x80088000 | (__ilog2(hose->io_resource.end
- - hose->io_resource.start + 1) - 1);
- }
-
- /* Setup 2G inbound Memory Window @ 0 */
- pcieiw->pexitar = 0x00000000;
- pcieiw->pexiwbar = 0x00000000;
- /* Enable, Prefetch, Local Mem, Snoop R/W, 2G */
- pcieiw->pexiwar = 0xa0f5501e;
+ pci = ioremap(rsrc->start, rsrc->end - rsrc->start + 1);
+
+ /* Disable all windows (except powar0 since its ignored) */
+ for(i = 1; i < 5; i++)
+ out_be32(&pci->pow[i].powar, 0);
+ for(i = 0; i < 3; i++)
+ out_be32(&pci->piw[i].piwar, 0);
+
+ /* Setup outbound MEM window */
+ for(i = 0; i < 3; i++)
+ if (hose->mem_resources[i].flags & IORESOURCE_MEM){
+ pr_debug("PCI MEM resource start 0x%08x, size 0x%08x.\n",
+ hose->mem_resources[i].start,
+ hose->mem_resources[i].end
+ - hose->mem_resources[i].start + 1);
+ out_be32(&pci->pow[i+1].potar,
+ (hose->mem_resources[i].start >> 12)
+ & 0x000fffff);
+ out_be32(&pci->pow[i+1].potear, 0);
+ out_be32(&pci->pow[i+1].powbar,
+ (hose->mem_resources[i].start >> 12)
+ & 0x000fffff);
+ /* Enable, Mem R/W */
+ out_be32(&pci->pow[i+1].powar, 0x80044000
+ | (__ilog2(hose->mem_resources[i].end
+ - hose->mem_resources[i].start + 1) - 1));
+ }
+
+ /* Setup outbound IO window */
+ if (hose->io_resource.flags & IORESOURCE_IO){
+ pr_debug("PCI IO resource start 0x%08x, size 0x%08x, phy base 0x%08x.\n",
+ hose->io_resource.start,
+ hose->io_resource.end - hose->io_resource.start + 1,
+ hose->io_base_phys);
+ out_be32(&pci->pow[i+1].potar, (hose->io_resource.start >> 12)
+ & 0x000fffff);
+ out_be32(&pci->pow[i+1].potear, 0);
+ out_be32(&pci->pow[i+1].powbar, (hose->io_base_phys >> 12)
+ & 0x000fffff);
+ /* Enable, IO R/W */
+ out_be32(&pci->pow[i+1].powar, 0x80088000
+ | (__ilog2(hose->io_resource.end
+ - hose->io_resource.start + 1) - 1));
+ }
+
+ /* Setup 2G inbound Memory Window @ 1 */
+ out_be32(&pci->piw[2].pitar, 0x00000000);
+ out_be32(&pci->piw[2].piwbar,0x00000000);
+ out_be32(&pci->piw[2].piwar, PIWAR_2G);
}
-static void __init
-mpc86xx_setup_pcie(struct pci_controller *hose, u32 pcie_offset, u32 pcie_size)
+void __init setup_pci_cmd(struct pci_controller *hose)
{
u16 cmd;
-
- DBG("PCIE host controller register offset 0x%08x, size 0x%08x.\n",
- pcie_offset, pcie_size);
-
early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd);
cmd |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY
- | PCI_COMMAND_IO;
+ | PCI_COMMAND_IO;
early_write_config_word(hose, 0, 0, PCI_COMMAND, cmd);
-
early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80);
}
@@ -167,72 +129,76 @@ static void __devinit quirk_fsl_pcie_transparent(struct pci_dev *dev)
}
}
+int __init fsl_pcie_check_link(struct pci_controller *hose)
+{
+ u16 val;
+ early_read_config_word(hose, 0, 0, PCIE_LTSSM, &val);
+ if (val < PCIE_LTSSM_L0)
+ return 1;
+ return 0;
+}
-DECLARE_PCI_FIXUP_EARLY(0x1957, 0x7010, quirk_fsl_pcie_transparent);
-DECLARE_PCI_FIXUP_EARLY(0x1957, 0x7011, quirk_fsl_pcie_transparent);
-
-#define PCIE_LTSSM 0x404 /* PCIe Link Training and Status */
-#define PCIE_LTSSM_L0 0x16 /* L0 state */
-
-int __init mpc86xx_add_bridge(struct device_node *dev)
+int __init fsl_add_bridge(struct device_node *dev, int is_primary)
{
int len;
struct pci_controller *hose;
struct resource rsrc;
const int *bus_range;
- int has_address = 0;
- int primary = 0;
- u16 val;
- DBG("Adding PCIE host bridge %s\n", dev->full_name);
+ pr_debug("Adding PCI host bridge %s\n", dev->full_name);
/* Fetch host bridge registers address */
- has_address = (of_address_to_resource(dev, 0, &rsrc) == 0);
+ if (of_address_to_resource(dev, 0, &rsrc)) {
+ printk(KERN_WARNING "Can't get pci register base!");
+ return -ENOMEM;
+ }
/* Get bus range if any */
bus_range = of_get_property(dev, "bus-range", &len);
if (bus_range == NULL || len < 2 * sizeof(int))
printk(KERN_WARNING "Can't get bus-range for %s, assume"
- " bus 0\n", dev->full_name);
+ " bus 0\n", dev->full_name);
pci_assign_all_buses = 1;
hose = pcibios_alloc_controller(dev);
if (!hose)
return -ENOMEM;
- hose->indirect_type = PPC_INDIRECT_TYPE_EXT_REG |
- PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS;
-
hose->first_busno = bus_range ? bus_range[0] : 0x0;
hose->last_busno = bus_range ? bus_range[1] : 0xff;
- setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4);
-
- /* Probe the hose link training status */
- early_read_config_word(hose, 0, 0, PCIE_LTSSM, &val);
- if (val < PCIE_LTSSM_L0)
- return -ENXIO;
+ /* check PCI express bridge */
+ if (of_device_is_compatible(dev, "fsl,mpc85xx-pciex") ||
+ of_device_is_compatible(dev, "fsl,mpc86xx-pciex"))
+ hose->indirect_type = PPC_INDIRECT_TYPE_EXT_REG |
+ PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS;
- /* Setup the PCIE host controller. */
- mpc86xx_setup_pcie(hose, rsrc.start, rsrc.end - rsrc.start + 1);
+ setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4);
+ setup_pci_cmd(hose);
- if ((rsrc.start & 0xfffff) == 0x8000)
- primary = 1;
+ /* check PCI express link status */
+ if (of_device_is_compatible(dev, "fsl,mpc85xx-pciex") ||
+ of_device_is_compatible(dev, "fsl,mpc86xx-pciex"))
+ if (fsl_pcie_check_link(hose))
+ return -ENXIO;
- printk(KERN_INFO "Found MPC86xx PCIE host bridge at 0x%08lx. "
- "Firmware bus number: %d->%d\n",
- (unsigned long) rsrc.start,
- hose->first_busno, hose->last_busno);
+ printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx."
+ "Firmware bus number: %d->%d\n",
+ (unsigned long long)rsrc.start, hose->first_busno,
+ hose->last_busno);
- DBG(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
+ pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
hose, hose->cfg_addr, hose->cfg_data);
/* Interpret the "ranges" property */
/* This also maps the I/O region and sets isa_io/mem_base */
- pci_process_bridge_OF_ranges(hose, dev, primary);
+ pci_process_bridge_OF_ranges(hose, dev, is_primary);
/* Setup PEX window registers */
- setup_pcie_atmu(hose, &rsrc);
+ setup_pci_atmu(hose, &rsrc);
return 0;
}
+
+DECLARE_PCI_FIXUP_EARLY(0x1957, 0x7010, quirk_fsl_pcie_transparent);
+DECLARE_PCI_FIXUP_EARLY(0x1957, 0x7011, quirk_fsl_pcie_transparent);
diff --git a/arch/powerpc/sysdev/fsl_pci.h b/arch/powerpc/sysdev/fsl_pci.h
index 8d9779c..91f94de 100644
--- a/arch/powerpc/sysdev/fsl_pci.h
+++ b/arch/powerpc/sysdev/fsl_pci.h
@@ -11,84 +11,75 @@
*/
#ifdef __KERNEL__
-#ifndef __POWERPC_FSL_PCIE_H
-#define __POWERPC_FSL_PCIE_H
+#ifndef __POWERPC_FSL_PCI_H
+#define __POWERPC_FSL_PCI_H
-/* PCIE Express IO block registers in 85xx/86xx */
+#define PCIE_LTSSM 0x04000004 /* PCIE Link Training and Status */
+#define PCIE_LTSSM_L0 0x16 /* L0 state */
+#define PIWAR_2G 0xa0f5501e /* Enable, Prefetch, Local Mem, Snoop R/W, 2G */
-struct ccsr_pex {
- __be32 __iomem pex_config_addr; /* 0x.000 - PCI Express Configuration Address Register */
- __be32 __iomem pex_config_data; /* 0x.004 - PCI Express Configuration Data Register */
- u8 __iomem res1[4];
- __be32 __iomem pex_otb_cpl_tor; /* 0x.00c - PCI Express Outbound completion timeout register */
- __be32 __iomem pex_conf_tor; /* 0x.010 - PCI Express configuration timeout register */
- u8 __iomem res2[12];
- __be32 __iomem pex_pme_mes_dr; /* 0x.020 - PCI Express PME and message detect register */
- __be32 __iomem pex_pme_mes_disr; /* 0x.024 - PCI Express PME and message disable register */
- __be32 __iomem pex_pme_mes_ier; /* 0x.028 - PCI Express PME and message interrupt enable register */
- __be32 __iomem pex_pmcr; /* 0x.02c - PCI Express power management command register */
- u8 __iomem res3[3024];
- __be32 __iomem pexotar0; /* 0x.c00 - PCI Express outbound translation address register 0 */
- __be32 __iomem pexotear0; /* 0x.c04 - PCI Express outbound translation extended address register 0*/
- u8 __iomem res4[8];
- __be32 __iomem pexowar0; /* 0x.c10 - PCI Express outbound window attributes register 0*/
- u8 __iomem res5[12];
- __be32 __iomem pexotar1; /* 0x.c20 - PCI Express outbound translation address register 1 */
- __be32 __iomem pexotear1; /* 0x.c24 - PCI Express outbound translation extended address register 1*/
- __be32 __iomem pexowbar1; /* 0x.c28 - PCI Express outbound window base address register 1*/
- u8 __iomem res6[4];
- __be32 __iomem pexowar1; /* 0x.c30 - PCI Express outbound window attributes register 1*/
- u8 __iomem res7[12];
- __be32 __iomem pexotar2; /* 0x.c40 - PCI Express outbound translation address register 2 */
- __be32 __iomem pexotear2; /* 0x.c44 - PCI Express outbound translation extended address register 2*/
- __be32 __iomem pexowbar2; /* 0x.c48 - PCI Express outbound window base address register 2*/
- u8 __iomem res8[4];
- __be32 __iomem pexowar2; /* 0x.c50 - PCI Express outbound window attributes register 2*/
- u8 __iomem res9[12];
- __be32 __iomem pexotar3; /* 0x.c60 - PCI Express outbound translation address register 3 */
- __be32 __iomem pexotear3; /* 0x.c64 - PCI Express outbound translation extended address register 3*/
- __be32 __iomem pexowbar3; /* 0x.c68 - PCI Express outbound window base address register 3*/
- u8 __iomem res10[4];
- __be32 __iomem pexowar3; /* 0x.c70 - PCI Express outbound window attributes register 3*/
- u8 __iomem res11[12];
- __be32 __iomem pexotar4; /* 0x.c80 - PCI Express outbound translation address register 4 */
- __be32 __iomem pexotear4; /* 0x.c84 - PCI Express outbound translation extended address register 4*/
- __be32 __iomem pexowbar4; /* 0x.c88 - PCI Express outbound window base address register 4*/
- u8 __iomem res12[4];
- __be32 __iomem pexowar4; /* 0x.c90 - PCI Express outbound window attributes register 4*/
- u8 __iomem res13[12];
- u8 __iomem res14[256];
- __be32 __iomem pexitar3; /* 0x.da0 - PCI Express inbound translation address register 3 */
- u8 __iomem res15[4];
- __be32 __iomem pexiwbar3; /* 0x.da8 - PCI Express inbound window base address register 3 */
- __be32 __iomem pexiwbear3; /* 0x.dac - PCI Express inbound window base extended address register 3 */
- __be32 __iomem pexiwar3; /* 0x.db0 - PCI Express inbound window attributes register 3 */
- u8 __iomem res16[12];
- __be32 __iomem pexitar2; /* 0x.dc0 - PCI Express inbound translation address register 2 */
- u8 __iomem res17[4];
- __be32 __iomem pexiwbar2; /* 0x.dc8 - PCI Express inbound window base address register 2 */
- __be32 __iomem pexiwbear2; /* 0x.dcc - PCI Express inbound window base extended address register 2 */
- __be32 __iomem pexiwar2; /* 0x.dd0 - PCI Express inbound window attributes register 2 */
- u8 __iomem res18[12];
- __be32 __iomem pexitar1; /* 0x.de0 - PCI Express inbound translation address register 2 */
- u8 __iomem res19[4];
- __be32 __iomem pexiwbar1; /* 0x.de8 - PCI Express inbound window base address register 2 */
- __be32 __iomem pexiwbear1; /* 0x.dec - PCI Express inbound window base extended address register 2 */
- __be32 __iomem pexiwar1; /* 0x.df0 - PCI Express inbound window attributes register 2 */
- u8 __iomem res20[12];
- __be32 __iomem pex_err_dr; /* 0x.e00 - PCI Express error detect register */
- u8 __iomem res21[4];
- __be32 __iomem pex_err_en; /* 0x.e08 - PCI Express error interrupt enable register */
- u8 __iomem res22[4];
- __be32 __iomem pex_err_disr; /* 0x.e10 - PCI Express error disable register */
- u8 __iomem res23[12];
- __be32 __iomem pex_err_cap_stat; /* 0x.e20 - PCI Express error capture status register */
- u8 __iomem res24[4];
- __be32 __iomem pex_err_cap_r0; /* 0x.e28 - PCI Express error capture register 0 */
- __be32 __iomem pex_err_cap_r1; /* 0x.e2c - PCI Express error capture register 0 */
- __be32 __iomem pex_err_cap_r2; /* 0x.e30 - PCI Express error capture register 0 */
- __be32 __iomem pex_err_cap_r3; /* 0x.e34 - PCI Express error capture register 0 */
+/* PCI/PCI Express outbound window reg */
+struct pci_outbound_window_regs {
+ __be32 potar; /* 0x.0 - Outbound translation address register */
+ __be32 potear; /* 0x.4 - Outbound translation extended address register */
+ __be32 powbar; /* 0x.8 - Outbound window base address register */
+ u8 res1[4];
+ __be32 powar; /* 0x.10 - Outbound window attributes register */
+ u8 res2[12];
};
-#endif /* __POWERPC_FSL_PCIE_H */
+/* PCI/PCI Express inbound window reg */
+struct pci_inbound_window_regs {
+ __be32 pitar; /* 0x.0 - Inbound translation address register */
+ u8 res1[4];
+ __be32 piwbar; /* 0x.8 - Inbound window base address register */
+ __be32 piwbear; /* 0x.c - Inbound window base extended address register */
+ __be32 piwar; /* 0x.10 - Inbound window attributes register */
+ u8 res2[12];
+};
+
+/* PCI/PCI Express IO block registers for 85xx/86xx */
+struct ccsr_pci {
+ __be32 config_addr; /* 0x.000 - PCI/PCIE Configuration Address Register */
+ __be32 config_data; /* 0x.004 - PCI/PCIE Configuration Data Register */
+ __be32 int_ack; /* 0x.008 - PCI Interrupt Acknowledge Register */
+ __be32 pex_otb_cpl_tor; /* 0x.00c - PCIE Outbound completion timeout register */
+ __be32 pex_conf_tor; /* 0x.010 - PCIE configuration timeout register */
+ u8 res2[12];
+ __be32 pex_pme_mes_dr; /* 0x.020 - PCIE PME and message detect register */
+ __be32 pex_pme_mes_disr; /* 0x.024 - PCIE PME and message disable register */
+ __be32 pex_pme_mes_ier; /* 0x.028 - PCIE PME and message interrupt enable register */
+ __be32 pex_pmcr; /* 0x.02c - PCIE power management command register */
+ u8 res3[3024];
+/* PCI/PCI Express outbound window 0-4
+ * Window 0 is the default window and is the only window enabled upon reset.
+ * The default outbound register set is used when a transaction misses
+ * in all of the other outbound windows.
+ */
+ struct pci_outbound_window_regs pow[5];
+
+ u8 res14[256];
+
+/* PCI/PCI Express inbound window 3-1
+ * inbound window 1 supports only a 32-bit base address and does not
+ * define an inbound window base extended address register.
+ */
+ struct pci_inbound_window_regs piw[3];
+
+ __be32 pex_err_dr; /* 0x.e00 - PCI/PCIE error detect register */
+ u8 res21[4];
+ __be32 pex_err_en; /* 0x.e08 - PCI/PCIE error interrupt enable register */
+ u8 res22[4];
+ __be32 pex_err_disr; /* 0x.e10 - PCI/PCIE error disable register */
+ u8 res23[12];
+ __be32 pex_err_cap_stat; /* 0x.e20 - PCI/PCIE error capture status register */
+ u8 res24[4];
+ __be32 pex_err_cap_r0; /* 0x.e28 - PCIE error capture register 0 */
+ __be32 pex_err_cap_r1; /* 0x.e2c - PCIE error capture register 0 */
+ __be32 pex_err_cap_r2; /* 0x.e30 - PCIE error capture register 0 */
+ __be32 pex_err_cap_r3; /* 0x.e34 - PCIE error capture register 0 */
+};
+
+int __init fsl_add_bridge(struct device_node *dev, int is_primary);
+#endif /* __POWERPC_FSL_PCI_H */
#endif /* __KERNEL__ */
--
1.5.1
^ permalink raw reply related
* Re: xilinx gpio in kernel 2.6
From: Mirek23 @ 2007-07-10 15:52 UTC (permalink / raw)
To: linuxppc-embedded
In-Reply-To: <10285090.post@talk.nabble.com>
Hi All,
After some time I have found the way how to deal with GPIO driver from the
user space:
First you have to mknod xgpio under /dev :
crw-rw-rw- 1 root root 10, 185 Jun 1 13:59 /dev/xgpio
Example program below shows how to read from the GPIO channel.
To write to the channel change the call:
ioctl(fgpio,XGPIO_IN,&sGpioData); to ioctl(fgpio,XGPIO_OUT,&sGpioData);
#include <stdlib.h>
#include <stdio.h>
#include <sys/ioctl.h>
#include <fcntl.h>
#include <linux/xgpio_ioctl.h>
main(){
int fgpio =0;
struct xgpio_ioctl_data sGpioData;
/* {
__u32 device;
__u32 mask;
__u32 data;
}*/
sGpioData.device=0; /* N=0,1,2,3-> GPIO DEV NR 2*N (Lower 32 bit part
)
2*N+1 (Upper 32 bit part
)*/
sGpioData.mask=0xffffffff;
sGpioData.data=0x55555555;
fgpio = open ("/dev/xgpio",O_RDWR);
if( fgpio != -1){
ioctl(fgpio,XGPIO_IN,&sGpioData);//pointer here to xgpio_ioctl_data
printf("Dip Swich readout 0x%X\n",sGpioData.data);
}
else
printf("Can not open GPIO\n");
close(fgpio);
}// end main
--
View this message in context: http://www.nabble.com/xilinx-gpio-in-kernel-2.6-tf3670122.html#a11523745
Sent from the linuxppc-embedded mailing list archive at Nabble.com.
^ permalink raw reply
* [patch 3/6] Add 8548 CDS PCI express controller node and PCI-X device node
From: Zang Roy-r61911 @ 2007-07-10 15:52 UTC (permalink / raw)
To: Kumar Gala, Paul Mackerras; +Cc: linuxppc-dev list
From: Roy Zang <tie-fei.zang@freescale.com>
Add 8548 CDS PCI express controller node and PCI-X device node.
The current dts file is suitable for 8548 Rev 2.0 board with
Arcadia 3.1.
This kind of board combination is the most popular.
Indentify pci, pcie host by compatible property "fsl,mpc85xx-pci"
and "fsl, mpc85xx-pciex".
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
---
arch/powerpc/boot/dts/mpc8548cds.dts | 156 +++++++++++++++++++++++-----------
1 files changed, 105 insertions(+), 51 deletions(-)
diff --git a/arch/powerpc/boot/dts/mpc8548cds.dts b/arch/powerpc/boot/dts/mpc8548cds.dts
index 9d0b84b..d60821b 100644
--- a/arch/powerpc/boot/dts/mpc8548cds.dts
+++ b/arch/powerpc/boot/dts/mpc8548cds.dts
@@ -1,5 +1,5 @@
/*
- * MPC8555 CDS Device Tree Source
+ * MPC8548 CDS Device Tree Source
*
* Copyright 2006 Freescale Semiconductor Inc.
*
@@ -186,67 +186,96 @@
pci1: pci@8000 {
interrupt-map-mask = <1f800 0 0 7>;
interrupt-map = <
+ /* IDSEL 0x4 (PCIX Slot 2) */
+ 02000 0 0 1 &mpic 0 1
+ 02000 0 0 2 &mpic 1 1
+ 02000 0 0 3 &mpic 2 1
+ 02000 0 0 4 &mpic 3 1
+
+ /* IDSEL 0x5 (PCIX Slot 3) */
+ 02800 0 0 1 &mpic 1 1
+ 02800 0 0 2 &mpic 2 1
+ 02800 0 0 3 &mpic 3 1
+ 02800 0 0 4 &mpic 0 1
+
+ /* IDSEL 0x6 (PCIX Slot 4) */
+ 03000 0 0 1 &mpic 2 1
+ 03000 0 0 2 &mpic 3 1
+ 03000 0 0 3 &mpic 0 1
+ 03000 0 0 4 &mpic 1 1
+
+ /* IDSEL 0x8 (PCIX Slot 5) */
+ 04000 0 0 1 &mpic 0 1
+ 04000 0 0 2 &mpic 1 1
+ 04000 0 0 3 &mpic 2 1
+ 04000 0 0 4 &mpic 3 1
+
+ /* IDSEL 0xC (Tsi310 bridge) */
+ 06000 0 0 1 &mpic 0 1
+ 06000 0 0 2 &mpic 1 1
+ 06000 0 0 3 &mpic 2 1
+ 06000 0 0 4 &mpic 3 1
+
+ /* IDSEL 0x14 (Slot 2) */
+ 0a000 0 0 1 &mpic 0 1
+ 0a000 0 0 2 &mpic 1 1
+ 0a000 0 0 3 &mpic 2 1
+ 0a000 0 0 4 &mpic 3 1
+
+ /* IDSEL 0x15 (Slot 3) */
+ 0a800 0 0 1 &mpic 1 1
+ 0a800 0 0 2 &mpic 2 1
+ 0a800 0 0 3 &mpic 3 1
+ 0a800 0 0 4 &mpic 0 1
+
+ /* IDSEL 0x16 (Slot 4) */
+ 0b000 0 0 1 &mpic 2 1
+ 0b000 0 0 2 &mpic 3 1
+ 0b000 0 0 3 &mpic 0 1
+ 0b000 0 0 4 &mpic 1 1
+
+ /* IDSEL 0x18 (Slot 5) */
+ 0c000 0 0 1 &mpic 0 1
+ 0c000 0 0 2 &mpic 1 1
+ 0c000 0 0 3 &mpic 2 1
+ 0c000 0 0 4 &mpic 3 1
+
+ /* IDSEL 0x1C (Tsi310 bridge PCI primary) */
+ 0E000 0 0 1 &mpic 0 1
+ 0E000 0 0 2 &mpic 1 1
+ 0E000 0 0 3 &mpic 2 1
+ 0E000 0 0 4 &mpic 3 1
+
+ /* bus 1 , idsel 0x2 Tsi310 bridge secondary */
+ 11000 0 0 1 &mpic 2 1
+ 11000 0 0 2 &mpic 3 1
+ 11000 0 0 3 &mpic 0 1
+ 11000 0 0 4 &mpic 1 1
+
+ /* VIA chip */
+ 12000 0 0 1 &mpic 0 1
+ 12000 0 0 2 &mpic 1 1
+ 12000 0 0 3 &mpic 2 1
+ 12000 0 0 4 &mpic 3 1>;
- /* IDSEL 0x10 */
- 08000 0 0 1 &mpic 0 1
- 08000 0 0 2 &mpic 1 1
- 08000 0 0 3 &mpic 2 1
- 08000 0 0 4 &mpic 3 1
-
- /* IDSEL 0x11 */
- 08800 0 0 1 &mpic 0 1
- 08800 0 0 2 &mpic 1 1
- 08800 0 0 3 &mpic 2 1
- 08800 0 0 4 &mpic 3 1
-
- /* IDSEL 0x12 (Slot 1) */
- 09000 0 0 1 &mpic 0 1
- 09000 0 0 2 &mpic 1 1
- 09000 0 0 3 &mpic 2 1
- 09000 0 0 4 &mpic 3 1
-
- /* IDSEL 0x13 (Slot 2) */
- 09800 0 0 1 &mpic 1 1
- 09800 0 0 2 &mpic 2 1
- 09800 0 0 3 &mpic 3 1
- 09800 0 0 4 &mpic 0 1
-
- /* IDSEL 0x14 (Slot 3) */
- 0a000 0 0 1 &mpic 2 1
- 0a000 0 0 2 &mpic 3 1
- 0a000 0 0 3 &mpic 0 1
- 0a000 0 0 4 &mpic 1 1
-
- /* IDSEL 0x15 (Slot 4) */
- 0a800 0 0 1 &mpic 3 1
- 0a800 0 0 2 &mpic 0 1
- 0a800 0 0 3 &mpic 1 1
- 0a800 0 0 4 &mpic 2 1
-
- /* Bus 1 (Tundra Bridge) */
- /* IDSEL 0x12 (ISA bridge) */
- 19000 0 0 1 &mpic 0 1
- 19000 0 0 2 &mpic 1 1
- 19000 0 0 3 &mpic 2 1
- 19000 0 0 4 &mpic 3 1>;
interrupt-parent = <&mpic>;
interrupts = <18 2>;
bus-range = <0 0>;
- ranges = <02000000 0 80000000 80000000 0 20000000
- 01000000 0 00000000 e2000000 0 00100000>;
+ ranges = <02000000 0 80000000 80000000 0 10000000
+ 01000000 0 00000000 e2000000 0 00800000>;
clock-frequency = <3f940aa>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <8000 1000>;
- compatible = "85xx";
+ compatible = "fsl,mpc85xx-pci","85xx";
device_type = "pci";
- i8259@19000 {
+ i8259@4 {
clock-frequency = <0>;
interrupt-controller;
device_type = "interrupt-controller";
- reg = <19000 0 0 0 1>;
+ reg = <12000 0 0 0 1>;
#address-cells = <0>;
#interrupt-cells = <2>;
built-in;
@@ -266,17 +295,42 @@
a800 0 0 2 &mpic b 1
a800 0 0 3 &mpic b 1
a800 0 0 4 &mpic b 1>;
+
interrupt-parent = <&mpic>;
interrupts = <19 2>;
bus-range = <0 0>;
- ranges = <02000000 0 a0000000 a0000000 0 20000000
- 01000000 0 00000000 e3000000 0 00100000>;
+ ranges = <02000000 0 90000000 90000000 0 10000000
+ 01000000 0 00000000 e2800000 0 00800000>;
clock-frequency = <3f940aa>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <9000 1000>;
- compatible = "85xx";
+ compatible = "fsl,mpc85xx-pci","85xx";
+ device_type = "pci";
+ };
+ /* PCI Express */
+ pci@a000 {
+ interrupt-map-mask = <f800 0 0 7>;
+ interrupt-map = <
+
+ /* IDSEL 0x0 (PEX) */
+ 00000 0 0 1 &mpic 0 1
+ 00000 0 0 2 &mpic 1 0
+ 00000 0 0 3 &mpic 2 0
+ 00000 0 0 4 &mpic 3 0>;
+
+ interrupt-parent = <&mpic>;
+ interrupts = <1a 2>;
+ bus-range = <0 ff>;
+ ranges = <02000000 0 a0000000 a0000000 0 20000000
+ 01000000 0 00000000 e3000000 0 08000000>;
+ clock-frequency = <1fca055>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <a000 1000>;
+ compatible = "fsl,mpc86xx-pciex","86xx";
device_type = "pci";
};
--
1.5.1
^ permalink raw reply related
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