* Re: 2.6.23-rc6-mm1 -- powerpc link failure
From: Andy Whitcroft @ 2007-09-19 16:52 UTC (permalink / raw)
To: Segher Boessenkool; +Cc: linuxppc-dev, Andrew Morton, linux-kernel
In-Reply-To: <24129b460390d93b37ee4cf21d6a5db1@kernel.crashing.org>
On Wed, Sep 19, 2007 at 06:36:29PM +0200, Segher Boessenkool wrote:
> >I am seeing this strange link error from a PowerMac G5 (powerpc):
> >
> > [...]
> > KSYM .tmp_kallsyms2.S
> > AS .tmp_kallsyms2.o
> > LD vmlinux.o
> > ld: dynreloc miscount for fs/built-in.o, section .opd
> > ld: can not edit opd Bad value
> > make: *** [vmlinux.o] Error 1
> >
> >Compiler version below.
>
> It's an ld error, could you show us your ld version instead? And
> please try with current mainline ld, too?
root@elm3b19:~# ld -v
GNU ld version 2.16.91 20060118 Debian GNU/Linux
Getting the compiler suite changed on here is going to be a lot
tricker. One of the reasons we keep it back there is those versions
are supposed to be supported and we want to test those combinations.
-apw
^ permalink raw reply
* Re: [PATCH 2/3] usb: ehci-ppc-of dts bindings.
From: Segher Boessenkool @ 2007-09-19 16:50 UTC (permalink / raw)
To: Valentine Barshak; +Cc: linuxppc-dev, linux-usb-devel
In-Reply-To: <46F1299A.1000508@ru.mvista.com>
>>> + Required properties:
>>> + - device_type : should be "usb".
>> No device_type please. The published USB binding doesn't define
>> one on purpose.
>
> Could you please, explain why?
> Sorry, I don't think I get the concept of device description here.
"device_type" is meant to be used only by OF for determining the OF
programming model for a device. No such thing has been defined for
USB busses, so the USB binding does not define a "device_type" either.
Nothing in a flat device tree should ever define a device_type, except
perhaps for compatibility with legacy kernel code.
>>> + - compatible : should be "ehci".
>> Just "ehci" isn't enough -- compare to OHCI, which is the name for
>> a kind of USB host controller as well as for a kind of Firewire
>> host controller.
>
> Actually, I though device type="usb" + compatible="ehci" would be
> enough.
"compatible" values are their own namespace, you should in principle
be able to find a driver for a device with them without having to look
at other properties.
>> Maybe "usb-ehci" is best -- can anyone think of a better name?
>
> Again, why not type="usb", compatible="ehci"?
Because an OF client (i.e., the Linux kernel) is not supposed to use
"device_type" at all for its own driver matching.
>>> + - interrupts : <a b> where a is the interrupt number and b is a
>>> + field that represents an encoding of the sense and level
>>> + information for the interrupt.
>> This is incorrect; not all interrupt domains use two cells, and
>> not all that do have this meaning for those cells.
>
> Well, this was just copied from other descriptions in
> Documentation/powerpc/booting-without-of.txt
> Do we need to fix them all?
Sounds like it, yes.
>>> + If device registers are implemented in big endian mode, the device
>>> + node should have "big-endian" property.
>>> + If controller implementation operates with big endian descriptors,
>>> + compatible should also have "ehci-be-desc"
>> Ah, I understand what this is about, finally.
>> Don't put this in "compatible"; instead, do a "big-endian-descriptors"
>> property similar to the "big-endian" property. That last one should
>> maybe be "big-endian-registers" here then, to avoid confusion.
>> Or make "big-endian" mean both big-endian registers *and* big-endian
>> descriptors.
>
> But doesn't "big-endian" property actually mean "big-endian-registers"?
> Do we have to overload property meaning in this case?
It doesn't *have* a standard meaning, it is defined per device binding
that uses it. Just make it mean whatever is most logical for this
device.
>> I have no opinion which is best; it depends on what configurations
>> actually exist, and how popular those are.
Segher
^ permalink raw reply
* Re: [PATCH net-2.6.24] eHEA: poll function update for new NAPI scheme
From: David Miller @ 2007-09-19 16:47 UTC (permalink / raw)
To: ossthema; +Cc: tklein, themann, netdev, linux-kernel, linuxppc-dev, raisch,
meder
In-Reply-To: <200709191740.30640.ossthema@de.ibm.com>
From: Jan-Bernd Themann <ossthema@de.ibm.com>
Date: Wed, 19 Sep 2007 17:40:30 +0200
> Update of ehea_poll function to work with new NAPI scheme.
>
> Signed-off-by: Jan-Bernd Themann <themann@de.ibm.com>
Applied, thanks.
^ permalink raw reply
* [PATCH] qe: miscellaneous code improvements and fixes to the QE library
From: Timur Tabi @ 2007-09-19 16:38 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Timur Tabi
This patch makes numerous miscellaneous code improvements to the QE library.
1. Remove struct ucc_common and merge ucc_init_guemr() into ucc_set_type()
(every caller of ucc_init_guemr() also calls ucc_set_type()). Modify all
callers of ucc_set_type() accordingly.
2. Remove the unused enum ucc_pram_initial_offset.
3. Refactor qe_setbrg(), also implement work-around for errata QE_General4.
4. Several printk() calls were missing the terminating \n.
5. Add __iomem where needed.
6. In ucc_slow_init() the RBASE and TBASE registers in the PRAM were programmed
with the wrong value.
7. Add the protocol type to struct us_info and updated ucc_slow_init() to
use it, instead of always programming QE_CR_PROTOCOL_UNSPECIFIED.
8. Rename ucc_slow_restart_x() to ucc_slow_restart_tx()
9. Add several macros in qe.h (mostly for slow UCC support, but also to
standardize some naming convention) and remove several unused macros.
10. Update ucc_geth.c to use the new macros.
11. Add ucc_slow_info.protocol to specify which QE_CR_PROTOCOL_xxx protcol
to use when initializing the UCC in ucc_slow_init().
12. Rename ucc_slow_pram.rfcr to rbmr and ucc_slow_pram.tfcr to tbmr, since
these are the real names of the registers.
Signed-off-by: Timur Tabi <timur@freescale.com>
---
This patch applies on top of Anton Vorontsov's patch "ucc_geth: fix compilation",
which has been applied to the netdev tree, but not the powerpc tree.
arch/powerpc/sysdev/qe_lib/qe.c | 35 ++++--
arch/powerpc/sysdev/qe_lib/qe_ic.c | 2 -
arch/powerpc/sysdev/qe_lib/qe_io.c | 35 ++---
arch/powerpc/sysdev/qe_lib/ucc.c | 68 ++++++----
arch/powerpc/sysdev/qe_lib/ucc_fast.c | 127 ++++++++---------
arch/powerpc/sysdev/qe_lib/ucc_slow.c | 48 +++----
drivers/net/ucc_geth.c | 2 +-
include/asm-powerpc/immap_qe.h | 23 +--
include/asm-powerpc/qe.h | 243 +++++++++++++++++++++++----------
include/asm-powerpc/ucc.h | 24 +---
include/asm-powerpc/ucc_slow.h | 9 +-
11 files changed, 346 insertions(+), 270 deletions(-)
diff --git a/arch/powerpc/sysdev/qe_lib/qe.c b/arch/powerpc/sysdev/qe_lib/qe.c
index 90f8740..3220c28 100644
--- a/arch/powerpc/sysdev/qe_lib/qe.c
+++ b/arch/powerpc/sysdev/qe_lib/qe.c
@@ -141,7 +141,7 @@ EXPORT_SYMBOL(qe_issue_cmd);
* 16 BRGs, which can be connected to the QE channels or output
* as clocks. The BRGs are in two different block of internal
* memory mapped space.
- * The baud rate clock is the system clock divided by something.
+ * The BRG clock is the QE clock divided by 2.
* It was set up long ago during the initial boot phase and is
* is given to us.
* Baud rate clocks are zero-based in the driver code (as that maps
@@ -165,26 +165,39 @@ unsigned int get_brg_clk(void)
return brg_clk;
}
-/* This function is used by UARTS, or anything else that uses a 16x
- * oversampled clock.
+/* Program the BRG to the given sampling rate and multiplier
+ *
+ * @brg: the BRG, 1-16
+ * @rate: the desired sampling rate
+ * @multiplier: corresponds to the value programmed in GUMR_L[RDCR] or
+ * GUMR_L[TDCR]. E.g., if this BRG is the RX clock, and GUMR_L[RDCR]=01,
+ * then 'multiplier' should be 8.
+ *
+ * Also note that the value programmed into the BRGC register must be even.
*/
-void qe_setbrg(u32 brg, u32 rate)
+void qe_setbrg(unsigned int brg, unsigned int rate, unsigned int multiplier)
{
volatile u32 *bp;
u32 divisor, tempval;
- int div16 = 0;
+ u32 div16 = 0;
- bp = &qe_immr->brg.brgc[brg];
+ bp = &qe_immr->brg.brgc[brg - 1];
+
+ divisor = get_brg_clk() / (rate * multiplier);
- divisor = (get_brg_clk() / rate);
if (divisor > QE_BRGC_DIVISOR_MAX + 1) {
- div16 = 1;
+ div16 = QE_BRGC_DIV16;
divisor /= 16;
}
- tempval = ((divisor - 1) << QE_BRGC_DIVISOR_SHIFT) | QE_BRGC_ENABLE;
- if (div16)
- tempval |= QE_BRGC_DIV16;
+ /* Errata QE_General4, which affects some MPC832x and MPC836x SOCs, says
+ that the BRG divisor must be even if you're not using divide-by-16
+ mode. */
+ if (!div16 && (divisor & 1))
+ divisor++;
+
+ tempval = ((divisor - 1) << QE_BRGC_DIVISOR_SHIFT) |
+ QE_BRGC_ENABLE | div16;
out_be32(bp, tempval);
}
diff --git a/arch/powerpc/sysdev/qe_lib/qe_ic.c b/arch/powerpc/sysdev/qe_lib/qe_ic.c
index 55e6f39..9a2d1ed 100644
--- a/arch/powerpc/sysdev/qe_lib/qe_ic.c
+++ b/arch/powerpc/sysdev/qe_lib/qe_ic.c
@@ -405,8 +405,6 @@ void __init qe_ic_init(struct device_node *node, unsigned int flags)
set_irq_data(qe_ic->virq_high, qe_ic);
set_irq_chained_handler(qe_ic->virq_high, qe_ic_cascade_high);
}
-
- printk("QEIC (%d IRQ sources) at %p\n", NR_QE_IC_INTS, qe_ic->regs);
}
void qe_ic_set_highest_priority(unsigned int virq, int high)
diff --git a/arch/powerpc/sysdev/qe_lib/qe_io.c b/arch/powerpc/sysdev/qe_lib/qe_io.c
index e32b45b..a114cb0 100644
--- a/arch/powerpc/sysdev/qe_lib/qe_io.c
+++ b/arch/powerpc/sysdev/qe_lib/qe_io.c
@@ -195,29 +195,22 @@ EXPORT_SYMBOL(par_io_of_config);
#ifdef DEBUG
static void dump_par_io(void)
{
- int i;
+ unsigned int i;
- printk(KERN_INFO "PAR IO registars:\n");
- printk(KERN_INFO "Base address: 0x%08x\n", (u32) par_io);
+ printk(KERN_INFO "%s: par_io=%p\n", __FUNCTION__, par_io);
for (i = 0; i < num_par_io_ports; i++) {
- printk(KERN_INFO "cpodr[%d] : addr - 0x%08x, val - 0x%08x\n",
- i, (u32) & par_io[i].cpodr,
- in_be32(&par_io[i].cpodr));
- printk(KERN_INFO "cpdata[%d]: addr - 0x%08x, val - 0x%08x\n",
- i, (u32) & par_io[i].cpdata,
- in_be32(&par_io[i].cpdata));
- printk(KERN_INFO "cpdir1[%d]: addr - 0x%08x, val - 0x%08x\n",
- i, (u32) & par_io[i].cpdir1,
- in_be32(&par_io[i].cpdir1));
- printk(KERN_INFO "cpdir2[%d]: addr - 0x%08x, val - 0x%08x\n",
- i, (u32) & par_io[i].cpdir2,
- in_be32(&par_io[i].cpdir2));
- printk(KERN_INFO "cppar1[%d]: addr - 0x%08x, val - 0x%08x\n",
- i, (u32) & par_io[i].cppar1,
- in_be32(&par_io[i].cppar1));
- printk(KERN_INFO "cppar2[%d]: addr - 0x%08x, val - 0x%08x\n",
- i, (u32) & par_io[i].cppar2,
- in_be32(&par_io[i].cppar2));
+ printk(KERN_INFO " cpodr[%u]=%08x\n", i,
+ in_be32(&par_io[i].cpodr));
+ printk(KERN_INFO " cpdata[%u]=%08x\n", i,
+ in_be32(&par_io[i].cpdata));
+ printk(KERN_INFO " cpdir1[%u]=%08x\n", i,
+ in_be32(&par_io[i].cpdir1));
+ printk(KERN_INFO " cpdir2[%u]=%08x\n", i,
+ in_be32(&par_io[i].cpdir2));
+ printk(KERN_INFO " cppar1[%u]=%08x\n", i,
+ in_be32(&par_io[i].cppar1));
+ printk(KERN_INFO " cppar2[%u]=%08x\n", i,
+ in_be32(&par_io[i].cppar2));
}
}
diff --git a/arch/powerpc/sysdev/qe_lib/ucc.c b/arch/powerpc/sysdev/qe_lib/ucc.c
index f970e54..517cc95 100644
--- a/arch/powerpc/sysdev/qe_lib/ucc.c
+++ b/arch/powerpc/sysdev/qe_lib/ucc.c
@@ -43,43 +43,57 @@ int ucc_set_qe_mux_mii_mng(int ucc_num)
}
EXPORT_SYMBOL(ucc_set_qe_mux_mii_mng);
-int ucc_set_type(int ucc_num, struct ucc_common *regs,
- enum ucc_speed_type speed)
+/* Configure the UCC to either Slow or Fast.
+ *
+ * A given UCC can be figured to support either "slow" devices (e.g. UART)
+ * or "fast" devices (e.g. Ethernet).
+ *
+ * 'ucc_num' is the UCC number, from 0 - 7.
+ *
+ * This function also sets the UCC_GUEMR_SET_RESERVED3 bit because that bit
+ * must always be set to 1.
+ */
+int ucc_set_type(unsigned int ucc_num, enum ucc_speed_type speed)
{
- u8 guemr = 0;
+ u8 __iomem *p_guemr;
+ u8 mode; /* The GUEMR register mode bits */
- /* check if the UCC number is in range. */
- if ((ucc_num > UCC_MAX_NUM - 1) || (ucc_num < 0))
+ /* The GUEMR register is at the same location for both slow and fast
+ devices, so we just use uccX.slow.guemr. */
+ switch (ucc_num) {
+ case 0: p_guemr = &qe_immr->ucc1.slow.guemr;
+ break;
+ case 1: p_guemr = &qe_immr->ucc2.slow.guemr;
+ break;
+ case 2: p_guemr = &qe_immr->ucc3.slow.guemr;
+ break;
+ case 3: p_guemr = &qe_immr->ucc4.slow.guemr;
+ break;
+ case 4: p_guemr = &qe_immr->ucc5.slow.guemr;
+ break;
+ case 5: p_guemr = &qe_immr->ucc6.slow.guemr;
+ break;
+ case 6: p_guemr = &qe_immr->ucc7.slow.guemr;
+ break;
+ case 7: p_guemr = &qe_immr->ucc8.slow.guemr;
+ break;
+ default:
return -EINVAL;
+ }
- guemr = regs->guemr;
- guemr &= ~(UCC_GUEMR_MODE_MASK_RX | UCC_GUEMR_MODE_MASK_TX);
switch (speed) {
case UCC_SPEED_TYPE_SLOW:
- guemr |= (UCC_GUEMR_MODE_SLOW_RX | UCC_GUEMR_MODE_SLOW_TX);
+ mode = UCC_GUEMR_MODE_SLOW_RX | UCC_GUEMR_MODE_SLOW_TX;
break;
case UCC_SPEED_TYPE_FAST:
- guemr |= (UCC_GUEMR_MODE_FAST_RX | UCC_GUEMR_MODE_FAST_TX);
+ mode = UCC_GUEMR_MODE_FAST_RX | UCC_GUEMR_MODE_FAST_TX;
break;
default:
return -EINVAL;
}
- regs->guemr = guemr;
- return 0;
-}
-
-int ucc_init_guemr(struct ucc_common *regs)
-{
- u8 guemr = 0;
-
- if (!regs)
- return -EINVAL;
-
- /* Set bit 3 (which is reserved in the GUEMR register) to 1 */
- guemr = UCC_GUEMR_SET_RESERVED3;
-
- regs->guemr = guemr;
+ out_8(p_guemr, (in_8(p_guemr) & ~UCC_GUEMR_MODE_MASK) |
+ UCC_GUEMR_SET_RESERVED3 | mode);
return 0;
}
@@ -160,7 +174,7 @@ int ucc_set_qe_mux_rxtx(int ucc_num, enum qe_clock clock, enum comm_dir mode)
if (!((mode == COMM_DIR_RX) || (mode == COMM_DIR_TX))) {
printk(KERN_ERR
- "ucc_set_qe_mux_rxtx: bad comm mode type passed.");
+ "ucc_set_qe_mux_rxtx: bad comm mode type passed.\n");
return -EINVAL;
}
@@ -235,8 +249,8 @@ int ucc_set_qe_mux_rxtx(int ucc_num, enum qe_clock clock, enum comm_dir mode)
}
if (source == -1) {
- printk(KERN_ERR
- "ucc_set_qe_mux_rxtx: Bad combination of clock and UCC.");
+ printk(KERN_ERR "%s: Bad combination of clock and UCC.\n",
+ __FUNCTION__);
return -ENOENT;
}
diff --git a/arch/powerpc/sysdev/qe_lib/ucc_fast.c b/arch/powerpc/sysdev/qe_lib/ucc_fast.c
index 3df202e..3223acb 100644
--- a/arch/powerpc/sysdev/qe_lib/ucc_fast.c
+++ b/arch/powerpc/sysdev/qe_lib/ucc_fast.c
@@ -30,46 +30,45 @@
void ucc_fast_dump_regs(struct ucc_fast_private * uccf)
{
- printk(KERN_INFO "UCC%d Fast registers:", uccf->uf_info->ucc_num);
- printk(KERN_INFO "Base address: 0x%08x", (u32) uccf->uf_regs);
-
- printk(KERN_INFO "gumr : addr - 0x%08x, val - 0x%08x",
- (u32) & uccf->uf_regs->gumr, in_be32(&uccf->uf_regs->gumr));
- printk(KERN_INFO "upsmr : addr - 0x%08x, val - 0x%08x",
- (u32) & uccf->uf_regs->upsmr, in_be32(&uccf->uf_regs->upsmr));
- printk(KERN_INFO "utodr : addr - 0x%08x, val - 0x%04x",
- (u32) & uccf->uf_regs->utodr, in_be16(&uccf->uf_regs->utodr));
- printk(KERN_INFO "udsr : addr - 0x%08x, val - 0x%04x",
- (u32) & uccf->uf_regs->udsr, in_be16(&uccf->uf_regs->udsr));
- printk(KERN_INFO "ucce : addr - 0x%08x, val - 0x%08x",
- (u32) & uccf->uf_regs->ucce, in_be32(&uccf->uf_regs->ucce));
- printk(KERN_INFO "uccm : addr - 0x%08x, val - 0x%08x",
- (u32) & uccf->uf_regs->uccm, in_be32(&uccf->uf_regs->uccm));
- printk(KERN_INFO "uccs : addr - 0x%08x, val - 0x%02x",
- (u32) & uccf->uf_regs->uccs, uccf->uf_regs->uccs);
- printk(KERN_INFO "urfb : addr - 0x%08x, val - 0x%08x",
- (u32) & uccf->uf_regs->urfb, in_be32(&uccf->uf_regs->urfb));
- printk(KERN_INFO "urfs : addr - 0x%08x, val - 0x%04x",
- (u32) & uccf->uf_regs->urfs, in_be16(&uccf->uf_regs->urfs));
- printk(KERN_INFO "urfet : addr - 0x%08x, val - 0x%04x",
- (u32) & uccf->uf_regs->urfet, in_be16(&uccf->uf_regs->urfet));
- printk(KERN_INFO "urfset: addr - 0x%08x, val - 0x%04x",
- (u32) & uccf->uf_regs->urfset,
- in_be16(&uccf->uf_regs->urfset));
- printk(KERN_INFO "utfb : addr - 0x%08x, val - 0x%08x",
- (u32) & uccf->uf_regs->utfb, in_be32(&uccf->uf_regs->utfb));
- printk(KERN_INFO "utfs : addr - 0x%08x, val - 0x%04x",
- (u32) & uccf->uf_regs->utfs, in_be16(&uccf->uf_regs->utfs));
- printk(KERN_INFO "utfet : addr - 0x%08x, val - 0x%04x",
- (u32) & uccf->uf_regs->utfet, in_be16(&uccf->uf_regs->utfet));
- printk(KERN_INFO "utftt : addr - 0x%08x, val - 0x%04x",
- (u32) & uccf->uf_regs->utftt, in_be16(&uccf->uf_regs->utftt));
- printk(KERN_INFO "utpt : addr - 0x%08x, val - 0x%04x",
- (u32) & uccf->uf_regs->utpt, in_be16(&uccf->uf_regs->utpt));
- printk(KERN_INFO "urtry : addr - 0x%08x, val - 0x%08x",
- (u32) & uccf->uf_regs->urtry, in_be32(&uccf->uf_regs->urtry));
- printk(KERN_INFO "guemr : addr - 0x%08x, val - 0x%02x",
- (u32) & uccf->uf_regs->guemr, uccf->uf_regs->guemr);
+ printk(KERN_INFO "UCC%u Fast registers:\n", uccf->uf_info->ucc_num);
+ printk(KERN_INFO "Base address: 0x%p\n", uccf->uf_regs);
+
+ printk(KERN_INFO "gumr : addr=0x%p, val=0x%08x\n",
+ &uccf->uf_regs->gumr, in_be32(&uccf->uf_regs->gumr));
+ printk(KERN_INFO "upsmr : addr=0x%p, val=0x%08x\n",
+ &uccf->uf_regs->upsmr, in_be32(&uccf->uf_regs->upsmr));
+ printk(KERN_INFO "utodr : addr=0x%p, val=0x%04x\n",
+ &uccf->uf_regs->utodr, in_be16(&uccf->uf_regs->utodr));
+ printk(KERN_INFO "udsr : addr=0x%p, val=0x%04x\n",
+ &uccf->uf_regs->udsr, in_be16(&uccf->uf_regs->udsr));
+ printk(KERN_INFO "ucce : addr=0x%p, val=0x%08x\n",
+ &uccf->uf_regs->ucce, in_be32(&uccf->uf_regs->ucce));
+ printk(KERN_INFO "uccm : addr=0x%p, val=0x%08x\n",
+ &uccf->uf_regs->uccm, in_be32(&uccf->uf_regs->uccm));
+ printk(KERN_INFO "uccs : addr=0x%p, val=0x%02x\n",
+ &uccf->uf_regs->uccs, uccf->uf_regs->uccs);
+ printk(KERN_INFO "urfb : addr=0x%p, val=0x%08x\n",
+ &uccf->uf_regs->urfb, in_be32(&uccf->uf_regs->urfb));
+ printk(KERN_INFO "urfs : addr=0x%p, val=0x%04x\n",
+ &uccf->uf_regs->urfs, in_be16(&uccf->uf_regs->urfs));
+ printk(KERN_INFO "urfet : addr=0x%p, val=0x%04x\n",
+ &uccf->uf_regs->urfet, in_be16(&uccf->uf_regs->urfet));
+ printk(KERN_INFO "urfset: addr=0x%p, val=0x%04x\n",
+ &uccf->uf_regs->urfset, in_be16(&uccf->uf_regs->urfset));
+ printk(KERN_INFO "utfb : addr=0x%p, val=0x%08x\n",
+ &uccf->uf_regs->utfb, in_be32(&uccf->uf_regs->utfb));
+ printk(KERN_INFO "utfs : addr=0x%p, val=0x%04x\n",
+ &uccf->uf_regs->utfs, in_be16(&uccf->uf_regs->utfs));
+ printk(KERN_INFO "utfet : addr=0x%p, val=0x%04x\n",
+ &uccf->uf_regs->utfet, in_be16(&uccf->uf_regs->utfet));
+ printk(KERN_INFO "utftt : addr=0x%p, val=0x%04x\n",
+ &uccf->uf_regs->utftt, in_be16(&uccf->uf_regs->utftt));
+ printk(KERN_INFO "utpt : addr=0x%p, val=0x%04x\n",
+ &uccf->uf_regs->utpt, in_be16(&uccf->uf_regs->utpt));
+ printk(KERN_INFO "urtry : addr=0x%p, val=0x%08x\n",
+ &uccf->uf_regs->urtry, in_be32(&uccf->uf_regs->urtry));
+ printk(KERN_INFO "guemr : addr=0x%p, val=0x%02x\n",
+ &uccf->uf_regs->guemr, uccf->uf_regs->guemr);
}
EXPORT_SYMBOL(ucc_fast_dump_regs);
@@ -149,55 +148,57 @@ int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** ucc
/* check if the UCC port number is in range. */
if ((uf_info->ucc_num < 0) || (uf_info->ucc_num > UCC_MAX_NUM - 1)) {
- printk(KERN_ERR "%s: illegal UCC number", __FUNCTION__);
+ printk(KERN_ERR "%s: illegal UCC number\n", __FUNCTION__);
return -EINVAL;
}
/* Check that 'max_rx_buf_length' is properly aligned (4). */
if (uf_info->max_rx_buf_length & (UCC_FAST_MRBLR_ALIGNMENT - 1)) {
- printk(KERN_ERR "%s: max_rx_buf_length not aligned", __FUNCTION__);
+ printk(KERN_ERR "%s: max_rx_buf_length not aligned\n",
+ __FUNCTION__);
return -EINVAL;
}
/* Validate Virtual Fifo register values */
if (uf_info->urfs < UCC_FAST_URFS_MIN_VAL) {
- printk(KERN_ERR "%s: urfs is too small", __FUNCTION__);
+ printk(KERN_ERR "%s: urfs is too small\n", __FUNCTION__);
return -EINVAL;
}
if (uf_info->urfs & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) {
- printk(KERN_ERR "%s: urfs is not aligned", __FUNCTION__);
+ printk(KERN_ERR "%s: urfs is not aligned\n", __FUNCTION__);
return -EINVAL;
}
if (uf_info->urfet & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) {
- printk(KERN_ERR "%s: urfet is not aligned.", __FUNCTION__);
+ printk(KERN_ERR "%s: urfet is not aligned.\n", __FUNCTION__);
return -EINVAL;
}
if (uf_info->urfset & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) {
- printk(KERN_ERR "%s: urfset is not aligned", __FUNCTION__);
+ printk(KERN_ERR "%s: urfset is not aligned\n", __FUNCTION__);
return -EINVAL;
}
if (uf_info->utfs & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) {
- printk(KERN_ERR "%s: utfs is not aligned", __FUNCTION__);
+ printk(KERN_ERR "%s: utfs is not aligned\n", __FUNCTION__);
return -EINVAL;
}
if (uf_info->utfet & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) {
- printk(KERN_ERR "%s: utfet is not aligned", __FUNCTION__);
+ printk(KERN_ERR "%s: utfet is not aligned\n", __FUNCTION__);
return -EINVAL;
}
if (uf_info->utftt & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) {
- printk(KERN_ERR "%s: utftt is not aligned", __FUNCTION__);
+ printk(KERN_ERR "%s: utftt is not aligned\n", __FUNCTION__);
return -EINVAL;
}
uccf = kzalloc(sizeof(struct ucc_fast_private), GFP_KERNEL);
if (!uccf) {
- printk(KERN_ERR "%s: Cannot allocate private data", __FUNCTION__);
+ printk(KERN_ERR "%s: Cannot allocate private data\n",
+ __FUNCTION__);
return -ENOMEM;
}
@@ -206,7 +207,7 @@ int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** ucc
/* Set the PHY base address */
uccf->uf_regs = ioremap(uf_info->regs, sizeof(struct ucc_fast));
if (uccf->uf_regs == NULL) {
- printk(KERN_ERR "%s: Cannot map UCC registers", __FUNCTION__);
+ printk(KERN_ERR "%s: Cannot map UCC registers\n", __FUNCTION__);
return -ENOMEM;
}
@@ -226,18 +227,10 @@ int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** ucc
uccf->rx_discarded = 0;
#endif /* STATISTICS */
- /* Init Guemr register */
- if ((ret = ucc_init_guemr((struct ucc_common *) (uf_regs)))) {
- printk(KERN_ERR "%s: cannot init GUEMR", __FUNCTION__);
- ucc_fast_free(uccf);
- return ret;
- }
-
/* Set UCC to fast type */
- if ((ret = ucc_set_type(uf_info->ucc_num,
- (struct ucc_common *) (uf_regs),
- UCC_SPEED_TYPE_FAST))) {
- printk(KERN_ERR "%s: cannot set UCC type", __FUNCTION__);
+ ret = ucc_set_type(uf_info->ucc_num, UCC_SPEED_TYPE_FAST);
+ if (ret) {
+ printk(KERN_ERR "%s: cannot set UCC type\n", __FUNCTION__);
ucc_fast_free(uccf);
return ret;
}
@@ -276,7 +269,8 @@ int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** ucc
uccf->ucc_fast_tx_virtual_fifo_base_offset =
qe_muram_alloc(uf_info->utfs, UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT);
if (IS_ERR_VALUE(uccf->ucc_fast_tx_virtual_fifo_base_offset)) {
- printk(KERN_ERR "%s: cannot allocate MURAM for TX FIFO", __FUNCTION__);
+ printk(KERN_ERR "%s: cannot allocate MURAM for TX FIFO\n",
+ __FUNCTION__);
uccf->ucc_fast_tx_virtual_fifo_base_offset = 0;
ucc_fast_free(uccf);
return -ENOMEM;
@@ -288,7 +282,8 @@ int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** ucc
UCC_FAST_RECEIVE_VIRTUAL_FIFO_SIZE_FUDGE_FACTOR,
UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT);
if (IS_ERR_VALUE(uccf->ucc_fast_rx_virtual_fifo_base_offset)) {
- printk(KERN_ERR "%s: cannot allocate MURAM for RX FIFO", __FUNCTION__);
+ printk(KERN_ERR "%s: cannot allocate MURAM for RX FIFO\n",
+ __FUNCTION__);
uccf->ucc_fast_rx_virtual_fifo_base_offset = 0;
ucc_fast_free(uccf);
return -ENOMEM;
@@ -318,7 +313,7 @@ int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** ucc
if ((uf_info->rx_clock != QE_CLK_NONE) &&
ucc_set_qe_mux_rxtx(uf_info->ucc_num, uf_info->rx_clock,
COMM_DIR_RX)) {
- printk(KERN_ERR "%s: illegal value for RX clock",
+ printk(KERN_ERR "%s: illegal value for RX clock\n",
__FUNCTION__);
ucc_fast_free(uccf);
return -EINVAL;
@@ -327,7 +322,7 @@ int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** ucc
if ((uf_info->tx_clock != QE_CLK_NONE) &&
ucc_set_qe_mux_rxtx(uf_info->ucc_num, uf_info->tx_clock,
COMM_DIR_TX)) {
- printk(KERN_ERR "%s: illegal value for TX clock",
+ printk(KERN_ERR "%s: illegal value for TX clock\n",
__FUNCTION__);
ucc_fast_free(uccf);
return -EINVAL;
diff --git a/arch/powerpc/sysdev/qe_lib/ucc_slow.c b/arch/powerpc/sysdev/qe_lib/ucc_slow.c
index 1f65c26..0174b3a 100644
--- a/arch/powerpc/sysdev/qe_lib/ucc_slow.c
+++ b/arch/powerpc/sysdev/qe_lib/ucc_slow.c
@@ -115,11 +115,15 @@ void ucc_slow_disable(struct ucc_slow_private * uccs, enum comm_dir mode)
out_be32(&us_regs->gumr_l, gumr_l);
}
+/* Initialize the UCC for Slow operations
+ *
+ * The caller should initialize the following us_info
+ */
int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** uccs_ret)
{
struct ucc_slow_private *uccs;
u32 i;
- struct ucc_slow *us_regs;
+ struct ucc_slow __iomem *us_regs;
u32 gumr;
struct qe_bd *bd;
u32 id;
@@ -131,7 +135,7 @@ int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** ucc
/* check if the UCC port number is in range. */
if ((us_info->ucc_num < 0) || (us_info->ucc_num > UCC_MAX_NUM - 1)) {
- printk(KERN_ERR "%s: illegal UCC number", __FUNCTION__);
+ printk(KERN_ERR "%s: illegal UCC number\n", __FUNCTION__);
return -EINVAL;
}
@@ -143,13 +147,14 @@ int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** ucc
*/
if ((!us_info->rfw) &&
(us_info->max_rx_buf_length & (UCC_SLOW_MRBLR_ALIGNMENT - 1))) {
- printk(KERN_ERR "max_rx_buf_length not aligned.");
+ printk(KERN_ERR "max_rx_buf_length not aligned.\n");
return -EINVAL;
}
uccs = kzalloc(sizeof(struct ucc_slow_private), GFP_KERNEL);
if (!uccs) {
- printk(KERN_ERR "%s: Cannot allocate private data", __FUNCTION__);
+ printk(KERN_ERR "%s: Cannot allocate private data\n",
+ __FUNCTION__);
return -ENOMEM;
}
@@ -158,7 +163,7 @@ int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** ucc
/* Set the PHY base address */
uccs->us_regs = ioremap(us_info->regs, sizeof(struct ucc_slow));
if (uccs->us_regs == NULL) {
- printk(KERN_ERR "%s: Cannot map UCC registers", __FUNCTION__);
+ printk(KERN_ERR "%s: Cannot map UCC registers\n", __FUNCTION__);
return -ENOMEM;
}
@@ -182,22 +187,14 @@ int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** ucc
return -ENOMEM;
}
id = ucc_slow_get_qe_cr_subblock(us_info->ucc_num);
- qe_issue_cmd(QE_ASSIGN_PAGE_TO_DEVICE, id, QE_CR_PROTOCOL_UNSPECIFIED,
+ qe_issue_cmd(QE_ASSIGN_PAGE_TO_DEVICE, id, us_info->protocol,
uccs->us_pram_offset);
uccs->us_pram = qe_muram_addr(uccs->us_pram_offset);
- /* Init Guemr register */
- if ((ret = ucc_init_guemr((struct ucc_common *) us_regs))) {
- printk(KERN_ERR "%s: cannot init GUEMR", __FUNCTION__);
- ucc_slow_free(uccs);
- return ret;
- }
-
/* Set UCC to slow type */
- if ((ret = ucc_set_type(us_info->ucc_num,
- (struct ucc_common *) us_regs,
- UCC_SPEED_TYPE_SLOW))) {
+ ret = ucc_set_type(us_info->ucc_num, UCC_SPEED_TYPE_SLOW);
+ if (ret) {
printk(KERN_ERR "%s: cannot set UCC type", __FUNCTION__);
ucc_slow_free(uccs);
return ret;
@@ -212,7 +209,8 @@ int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** ucc
qe_muram_alloc(us_info->rx_bd_ring_len * sizeof(struct qe_bd),
QE_ALIGNMENT_OF_BD);
if (IS_ERR_VALUE(uccs->rx_base_offset)) {
- printk(KERN_ERR "%s: cannot allocate RX BDs", __FUNCTION__);
+ printk(KERN_ERR "%s: cannot allocate %u RX BDs\n", __FUNCTION__,
+ us_info->rx_bd_ring_len);
uccs->rx_base_offset = 0;
ucc_slow_free(uccs);
return -ENOMEM;
@@ -292,12 +290,12 @@ int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** ucc
/* if the data is in cachable memory, the 'global' */
/* in the function code should be set. */
- uccs->us_pram->tfcr = uccs->us_pram->rfcr =
- us_info->data_mem_part | QE_BMR_BYTE_ORDER_BO_MOT;
+ uccs->us_pram->tbmr = UCC_BMR_BO_BE;
+ uccs->us_pram->rbmr = UCC_BMR_BO_BE;
/* rbase, tbase are offsets from MURAM base */
- out_be16(&uccs->us_pram->rbase, uccs->us_pram_offset);
- out_be16(&uccs->us_pram->tbase, uccs->us_pram_offset);
+ out_be16(&uccs->us_pram->rbase, uccs->rx_base_offset);
+ out_be16(&uccs->us_pram->tbase, uccs->tx_base_offset);
/* Mux clocking */
/* Grant Support */
@@ -311,7 +309,7 @@ int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** ucc
/* Rx clock routing */
if (ucc_set_qe_mux_rxtx(us_info->ucc_num, us_info->rx_clock,
COMM_DIR_RX)) {
- printk(KERN_ERR "%s: illegal value for RX clock",
+ printk(KERN_ERR "%s: illegal value for RX clock\n",
__FUNCTION__);
ucc_slow_free(uccs);
return -EINVAL;
@@ -319,7 +317,7 @@ int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** ucc
/* Tx clock routing */
if (ucc_set_qe_mux_rxtx(us_info->ucc_num, us_info->tx_clock,
COMM_DIR_TX)) {
- printk(KERN_ERR "%s: illegal value for TX clock",
+ printk(KERN_ERR "%s: illegal value for TX clock\n",
__FUNCTION__);
ucc_slow_free(uccs);
return -EINVAL;
@@ -343,8 +341,8 @@ int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** ucc
command = QE_INIT_TX;
else
command = QE_INIT_RX; /* We know at least one is TRUE */
- id = ucc_slow_get_qe_cr_subblock(us_info->ucc_num);
- qe_issue_cmd(command, id, QE_CR_PROTOCOL_UNSPECIFIED, 0);
+
+ qe_issue_cmd(command, id, us_info->protocol, 0);
*uccs_ret = uccs;
return 0;
diff --git a/drivers/net/ucc_geth.c b/drivers/net/ucc_geth.c
index 9a38dfe..96ebdf7 100644
--- a/drivers/net/ucc_geth.c
+++ b/drivers/net/ucc_geth.c
@@ -2919,7 +2919,7 @@ static int ucc_geth_startup(struct ucc_geth_private *ugeth)
test = in_be16(&ugeth->p_tx_glbl_pram->temoder);
/* Function code register value to be used later */
- function_code = QE_BMR_BYTE_ORDER_BO_MOT | UCC_FAST_FUNCTION_CODE_GBL;
+ function_code = UCC_BMR_BO_BE | UCC_BMR_GBL;
/* Required for QE */
/* function code register */
diff --git a/include/asm-powerpc/immap_qe.h b/include/asm-powerpc/immap_qe.h
index 1020b7f..0a0644b 100644
--- a/include/asm-powerpc/immap_qe.h
+++ b/include/asm-powerpc/immap_qe.h
@@ -260,7 +260,6 @@ struct ucc_slow {
__be16 utpt;
u8 res4[0x52];
u8 guemr; /* UCC general extended mode register */
- u8 res5[0x200 - 0x091];
} __attribute__ ((packed));
/* QE UCC Fast */
@@ -293,21 +292,13 @@ struct ucc_fast {
__be32 urtry; /* UCC retry counter register */
u8 res8[0x4C];
u8 guemr; /* UCC general extended mode register */
- u8 res9[0x100 - 0x091];
-} __attribute__ ((packed));
-
-/* QE UCC */
-struct ucc_common {
- u8 res1[0x90];
- u8 guemr;
- u8 res2[0x200 - 0x091];
} __attribute__ ((packed));
struct ucc {
union {
struct ucc_slow slow;
struct ucc_fast fast;
- struct ucc_common common;
+ u8 res[0x200]; /* UCC blocks are 512 bytes each */
};
} __attribute__ ((packed));
@@ -406,7 +397,7 @@ struct dbg {
/* RISC Special Registers (Trap and Breakpoint) */
struct rsp {
- u8 fixme[0x100];
+ u32 reg[0x40]; /* 64 32-bit registers */
} __attribute__ ((packed));
struct qe_immap {
@@ -435,11 +426,13 @@ struct qe_immap {
u8 res13[0x600];
struct upc upc2; /* MultiPHY UTOPIA POS Ctrlr 2*/
struct sdma sdma; /* SDMA */
- struct dbg dbg; /* Debug Space */
- struct rsp rsp[0x2]; /* RISC Special Registers
+ struct dbg dbg; /* 0x104080 - 0x1040FF
+ Debug Space */
+ struct rsp rsp[0x2]; /* 0x104100 - 0x1042FF
+ RISC Special Registers
(Trap and Breakpoint) */
- u8 res14[0x300];
- u8 res15[0x3A00];
+ u8 res14[0x300]; /* 0x104300 - 0x1045FF */
+ u8 res15[0x3A00]; /* 0x104600 - 0x107FFF */
u8 res16[0x8000]; /* 0x108000 - 0x110000 */
u8 muram[0xC000]; /* 0x110000 - 0x11C000
Multi-user RAM */
diff --git a/include/asm-powerpc/qe.h b/include/asm-powerpc/qe.h
index 9d304b1..a92e07a 100644
--- a/include/asm-powerpc/qe.h
+++ b/include/asm-powerpc/qe.h
@@ -35,7 +35,7 @@ extern int par_io_of_config(struct device_node *np);
/* QE internal API */
int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input);
-void qe_setbrg(u32 brg, u32 rate);
+void qe_setbrg(unsigned int brg, unsigned int rate, unsigned int multiplier);
int qe_get_snum(void);
void qe_put_snum(u8 snum);
unsigned long qe_muram_alloc(int size, int align);
@@ -46,14 +46,28 @@ void *qe_muram_addr(unsigned long offset);
/* Buffer descriptors */
struct qe_bd {
- u16 status;
- u16 length;
- u32 buf;
+ __be16 status;
+ __be16 length;
+ __be32 buf;
} __attribute__ ((packed));
#define BD_STATUS_MASK 0xffff0000
#define BD_LENGTH_MASK 0x0000ffff
+#define BD_SC_EMPTY 0x8000 /* Receive is empty */
+#define BD_SC_READY 0x8000 /* Transmit is ready */
+#define BD_SC_WRAP 0x2000 /* Last buffer descriptor */
+#define BD_SC_INTRPT 0x1000 /* Interrupt on change */
+#define BD_SC_LAST 0x0800 /* Last buffer in frame */
+#define BD_SC_CM 0x0200 /* Continous mode */
+#define BD_SC_ID 0x0100 /* Rec'd too many idles */
+#define BD_SC_P 0x0100 /* xmt preamble */
+#define BD_SC_BR 0x0020 /* Break received */
+#define BD_SC_FR 0x0010 /* Framing error */
+#define BD_SC_PR 0x0008 /* Parity error */
+#define BD_SC_OV 0x0002 /* Overrun */
+#define BD_SC_CD 0x0001 /* ?? */
+
/* Alignment */
#define QE_INTR_TABLE_ALIGN 16 /* ??? */
#define QE_ALIGNMENT_OF_BD 8
@@ -266,15 +280,12 @@ enum qe_clock {
/* QE CECR Protocol - For non-MCC, specifies mode for QE CECR command */
#define QE_CR_PROTOCOL_UNSPECIFIED 0x00 /* For all other protocols */
#define QE_CR_PROTOCOL_HDLC_TRANSPARENT 0x00
+#define QE_CR_PROTOCOL_QMC 0x02
+#define QE_CR_PROTOCOL_UART 0x04
#define QE_CR_PROTOCOL_ATM_POS 0x0A
#define QE_CR_PROTOCOL_ETHERNET 0x0C
#define QE_CR_PROTOCOL_L2_SWITCH 0x0D
-/* BMR byte order */
-#define QE_BMR_BYTE_ORDER_BO_PPC 0x08 /* powerpc little endian */
-#define QE_BMR_BYTE_ORDER_BO_MOT 0x10 /* motorola big endian */
-#define QE_BMR_BYTE_ORDER_BO_MAX 0x18
-
/* BRG configuration register */
#define QE_BRGC_ENABLE 0x00010000
#define QE_BRGC_DIVISOR_SHIFT 1
@@ -321,41 +332,41 @@ enum qe_clock {
#define UPGCR_ADDR 0x10000000 /* Master MPHY Addr multiplexing */
#define UPGCR_DIAG 0x01000000 /* Diagnostic mode */
-/* UCC */
+/* UCC GUEMR register */
#define UCC_GUEMR_MODE_MASK_RX 0x02
-#define UCC_GUEMR_MODE_MASK_TX 0x01
#define UCC_GUEMR_MODE_FAST_RX 0x02
-#define UCC_GUEMR_MODE_FAST_TX 0x01
#define UCC_GUEMR_MODE_SLOW_RX 0x00
+#define UCC_GUEMR_MODE_MASK_TX 0x01
+#define UCC_GUEMR_MODE_FAST_TX 0x01
#define UCC_GUEMR_MODE_SLOW_TX 0x00
+#define UCC_GUEMR_MODE_MASK (UCC_GUEMR_MODE_MASK_RX | UCC_GUEMR_MODE_MASK_TX)
#define UCC_GUEMR_SET_RESERVED3 0x10 /* Bit 3 in the guemr is reserved but
must be set 1 */
/* structure representing UCC SLOW parameter RAM */
struct ucc_slow_pram {
- u16 rbase; /* RX BD base address */
- u16 tbase; /* TX BD base address */
- u8 rfcr; /* Rx function code */
- u8 tfcr; /* Tx function code */
- u16 mrblr; /* Rx buffer length */
- u32 rstate; /* Rx internal state */
- u32 rptr; /* Rx internal data pointer */
- u16 rbptr; /* rb BD Pointer */
- u16 rcount; /* Rx internal byte count */
- u32 rtemp; /* Rx temp */
- u32 tstate; /* Tx internal state */
- u32 tptr; /* Tx internal data pointer */
- u16 tbptr; /* Tx BD pointer */
- u16 tcount; /* Tx byte count */
- u32 ttemp; /* Tx temp */
- u32 rcrc; /* temp receive CRC */
- u32 tcrc; /* temp transmit CRC */
+ __be16 rbase; /* RX BD base address */
+ __be16 tbase; /* TX BD base address */
+ u8 rbmr; /* RX bus mode register (same as CPM's RFCR) */
+ u8 tbmr; /* TX bus mode register (same as CPM's TFCR) */
+ __be16 mrblr; /* Rx buffer length */
+ __be32 rstate; /* Rx internal state */
+ __be32 rptr; /* Rx internal data pointer */
+ __be16 rbptr; /* rb BD Pointer */
+ __be16 rcount; /* Rx internal byte count */
+ __be32 rtemp; /* Rx temp */
+ __be32 tstate; /* Tx internal state */
+ __be32 tptr; /* Tx internal data pointer */
+ __be16 tbptr; /* Tx BD pointer */
+ __be16 tcount; /* Tx byte count */
+ __be32 ttemp; /* Tx temp */
+ __be32 rcrc; /* temp receive CRC */
+ __be32 tcrc; /* temp transmit CRC */
} __attribute__ ((packed));
/* General UCC SLOW Mode Register (GUMRH & GUMRL) */
-#define UCC_SLOW_GUMR_H_CRC16 0x00004000
-#define UCC_SLOW_GUMR_H_CRC16CCITT 0x00000000
-#define UCC_SLOW_GUMR_H_CRC32CCITT 0x00008000
+#define UCC_SLOW_GUMR_H_SAM_QMC 0x00000000
+#define UCC_SLOW_GUMR_H_SAM_SATM 0x00008000
#define UCC_SLOW_GUMR_H_REVD 0x00002000
#define UCC_SLOW_GUMR_H_TRX 0x00001000
#define UCC_SLOW_GUMR_H_TTX 0x00000800
@@ -375,9 +386,33 @@ struct ucc_slow_pram {
#define UCC_SLOW_GUMR_L_TCI 0x10000000
#define UCC_SLOW_GUMR_L_RINV 0x02000000
#define UCC_SLOW_GUMR_L_TINV 0x01000000
-#define UCC_SLOW_GUMR_L_TEND 0x00020000
+#define UCC_SLOW_GUMR_L_TEND 0x00040000
+#define UCC_SLOW_GUMR_L_TDCR_MASK 0x00030000
+#define UCC_SLOW_GUMR_L_TDCR_32 0x00030000
+#define UCC_SLOW_GUMR_L_TDCR_16 0x00020000
+#define UCC_SLOW_GUMR_L_TDCR_8 0x00010000
+#define UCC_SLOW_GUMR_L_TDCR_1 0x00000000
+#define UCC_SLOW_GUMR_L_RDCR_MASK 0x0000c000
+#define UCC_SLOW_GUMR_L_RDCR_32 0x0000c000
+#define UCC_SLOW_GUMR_L_RDCR_16 0x00008000
+#define UCC_SLOW_GUMR_L_RDCR_8 0x00004000
+#define UCC_SLOW_GUMR_L_RDCR_1 0x00000000
+#define UCC_SLOW_GUMR_L_RENC_NRZI 0x00000800
+#define UCC_SLOW_GUMR_L_RENC_NRZ 0x00000000
+#define UCC_SLOW_GUMR_L_TENC_NRZI 0x00000100
+#define UCC_SLOW_GUMR_L_TENC_NRZ 0x00000000
+#define UCC_SLOW_GUMR_L_DIAG_MASK 0x000000c0
+#define UCC_SLOW_GUMR_L_DIAG_LE 0x000000c0
+#define UCC_SLOW_GUMR_L_DIAG_ECHO 0x00000080
+#define UCC_SLOW_GUMR_L_DIAG_LOOP 0x00000040
+#define UCC_SLOW_GUMR_L_DIAG_NORM 0x00000000
#define UCC_SLOW_GUMR_L_ENR 0x00000020
#define UCC_SLOW_GUMR_L_ENT 0x00000010
+#define UCC_SLOW_GUMR_L_MODE_MASK 0x0000000F
+#define UCC_SLOW_GUMR_L_MODE_BISYNC 0x00000008
+#define UCC_SLOW_GUMR_L_MODE_AHDLC 0x00000006
+#define UCC_SLOW_GUMR_L_MODE_UART 0x00000004
+#define UCC_SLOW_GUMR_L_MODE_QMC 0x00000002
/* General UCC FAST Mode Register */
#define UCC_FAST_GUMR_TCI 0x20000000
@@ -394,53 +429,111 @@ struct ucc_slow_pram {
#define UCC_FAST_GUMR_ENR 0x00000020
#define UCC_FAST_GUMR_ENT 0x00000010
-/* Slow UCC Event Register (UCCE) */
-#define UCC_SLOW_UCCE_GLR 0x1000
-#define UCC_SLOW_UCCE_GLT 0x0800
-#define UCC_SLOW_UCCE_DCC 0x0400
-#define UCC_SLOW_UCCE_FLG 0x0200
-#define UCC_SLOW_UCCE_AB 0x0200
-#define UCC_SLOW_UCCE_IDLE 0x0100
-#define UCC_SLOW_UCCE_GRA 0x0080
-#define UCC_SLOW_UCCE_TXE 0x0010
-#define UCC_SLOW_UCCE_RXF 0x0008
-#define UCC_SLOW_UCCE_CCR 0x0008
-#define UCC_SLOW_UCCE_RCH 0x0008
-#define UCC_SLOW_UCCE_BSY 0x0004
-#define UCC_SLOW_UCCE_TXB 0x0002
-#define UCC_SLOW_UCCE_TX 0x0002
-#define UCC_SLOW_UCCE_RX 0x0001
-#define UCC_SLOW_UCCE_GOV 0x0001
-#define UCC_SLOW_UCCE_GUN 0x0002
-#define UCC_SLOW_UCCE_GINT 0x0004
-#define UCC_SLOW_UCCE_IQOV 0x0008
-
-#define UCC_SLOW_UCCE_HDLC_SET (UCC_SLOW_UCCE_TXE | UCC_SLOW_UCCE_BSY | \
- UCC_SLOW_UCCE_GRA | UCC_SLOW_UCCE_TXB | UCC_SLOW_UCCE_RXF | \
- UCC_SLOW_UCCE_DCC | UCC_SLOW_UCCE_GLT | UCC_SLOW_UCCE_GLR)
-#define UCC_SLOW_UCCE_ENET_SET (UCC_SLOW_UCCE_TXE | UCC_SLOW_UCCE_BSY | \
- UCC_SLOW_UCCE_GRA | UCC_SLOW_UCCE_TXB | UCC_SLOW_UCCE_RXF)
-#define UCC_SLOW_UCCE_TRANS_SET (UCC_SLOW_UCCE_TXE | UCC_SLOW_UCCE_BSY | \
- UCC_SLOW_UCCE_GRA | UCC_SLOW_UCCE_TX | UCC_SLOW_UCCE_RX | \
- UCC_SLOW_UCCE_DCC | UCC_SLOW_UCCE_GLT | UCC_SLOW_UCCE_GLR)
-#define UCC_SLOW_UCCE_UART_SET (UCC_SLOW_UCCE_BSY | UCC_SLOW_UCCE_GRA | \
- UCC_SLOW_UCCE_TXB | UCC_SLOW_UCCE_TX | UCC_SLOW_UCCE_RX | \
- UCC_SLOW_UCCE_GLT | UCC_SLOW_UCCE_GLR)
-#define UCC_SLOW_UCCE_QMC_SET (UCC_SLOW_UCCE_IQOV | UCC_SLOW_UCCE_GINT | \
- UCC_SLOW_UCCE_GUN | UCC_SLOW_UCCE_GOV)
-
-#define UCC_SLOW_UCCE_OTHER (UCC_SLOW_UCCE_TXE | UCC_SLOW_UCCE_BSY | \
- UCC_SLOW_UCCE_GRA | UCC_SLOW_UCCE_DCC | UCC_SLOW_UCCE_GLT | \
- UCC_SLOW_UCCE_GLR)
-
-#define UCC_SLOW_INTR_TX UCC_SLOW_UCCE_TXB
-#define UCC_SLOW_INTR_RX (UCC_SLOW_UCCE_RXF | UCC_SLOW_UCCE_RX)
-#define UCC_SLOW_INTR (UCC_SLOW_INTR_TX | UCC_SLOW_INTR_RX)
+/* UART Slow UCC Event Register (UCCE) */
+#define UCC_UART_UCCE_AB 0x0200
+#define UCC_UART_UCCE_IDLE 0x0100
+#define UCC_UART_UCCE_GRA 0x0080
+#define UCC_UART_UCCE_BRKE 0x0040
+#define UCC_UART_UCCE_BRKS 0x0020
+#define UCC_UART_UCCE_CCR 0x0008
+#define UCC_UART_UCCE_BSY 0x0004
+#define UCC_UART_UCCE_TX 0x0002
+#define UCC_UART_UCCE_RX 0x0001
+
+/* HDLC Slow UCC Event Register (UCCE) */
+#define UCC_HDLC_UCCE_GLR 0x1000
+#define UCC_HDLC_UCCE_GLT 0x0800
+#define UCC_HDLC_UCCE_IDLE 0x0100
+#define UCC_HDLC_UCCE_BRKE 0x0040
+#define UCC_HDLC_UCCE_BRKS 0x0020
+#define UCC_HDLC_UCCE_TXE 0x0010
+#define UCC_HDLC_UCCE_RXF 0x0008
+#define UCC_HDLC_UCCE_BSY 0x0004
+#define UCC_HDLC_UCCE_TXB 0x0002
+#define UCC_HDLC_UCCE_RXB 0x0001
+
+/* BISYNC Slow UCC Event Register (UCCE) */
+#define UCC_BISYNC_UCCE_GRA 0x0080
+#define UCC_BISYNC_UCCE_TXE 0x0010
+#define UCC_BISYNC_UCCE_RCH 0x0008
+#define UCC_BISYNC_UCCE_BSY 0x0004
+#define UCC_BISYNC_UCCE_TXB 0x0002
+#define UCC_BISYNC_UCCE_RXB 0x0001
+
+/* Gigabit Ethernet Fast UCC Event Register (UCCE) */
+#define UCC_GETH_UCCE_MPD 0x80000000
+#define UCC_GETH_UCCE_SCAR 0x40000000
+#define UCC_GETH_UCCE_GRA 0x20000000
+#define UCC_GETH_UCCE_CBPR 0x10000000
+#define UCC_GETH_UCCE_BSY 0x08000000
+#define UCC_GETH_UCCE_RXC 0x04000000
+#define UCC_GETH_UCCE_TXC 0x02000000
+#define UCC_GETH_UCCE_TXE 0x01000000
+#define UCC_GETH_UCCE_TXB7 0x00800000
+#define UCC_GETH_UCCE_TXB6 0x00400000
+#define UCC_GETH_UCCE_TXB5 0x00200000
+#define UCC_GETH_UCCE_TXB4 0x00100000
+#define UCC_GETH_UCCE_TXB3 0x00080000
+#define UCC_GETH_UCCE_TXB2 0x00040000
+#define UCC_GETH_UCCE_TXB1 0x00020000
+#define UCC_GETH_UCCE_TXB0 0x00010000
+#define UCC_GETH_UCCE_RXB7 0x00008000
+#define UCC_GETH_UCCE_RXB6 0x00004000
+#define UCC_GETH_UCCE_RXB5 0x00002000
+#define UCC_GETH_UCCE_RXB4 0x00001000
+#define UCC_GETH_UCCE_RXB3 0x00000800
+#define UCC_GETH_UCCE_RXB2 0x00000400
+#define UCC_GETH_UCCE_RXB1 0x00000200
+#define UCC_GETH_UCCE_RXB0 0x00000100
+#define UCC_GETH_UCCE_RXF7 0x00000080
+#define UCC_GETH_UCCE_RXF6 0x00000040
+#define UCC_GETH_UCCE_RXF5 0x00000020
+#define UCC_GETH_UCCE_RXF4 0x00000010
+#define UCC_GETH_UCCE_RXF3 0x00000008
+#define UCC_GETH_UCCE_RXF2 0x00000004
+#define UCC_GETH_UCCE_RXF1 0x00000002
+#define UCC_GETH_UCCE_RXF0 0x00000001
+
+/* UPSMR, when used as a UART */
+#define UCC_UART_UPSMR_FLC 0x8000
+#define UCC_UART_UPSMR_SL 0x4000
+#define UCC_UART_UPSMR_CL_MASK 0x3000
+#define UCC_UART_UPSMR_CL_8 0x3000
+#define UCC_UART_UPSMR_CL_7 0x2000
+#define UCC_UART_UPSMR_CL_6 0x1000
+#define UCC_UART_UPSMR_CL_5 0x0000
+#define UCC_UART_UPSMR_UM_MASK 0x0c00
+#define UCC_UART_UPSMR_UM_NORMAL 0x0000
+#define UCC_UART_UPSMR_UM_MAN_MULTI 0x0400
+#define UCC_UART_UPSMR_UM_AUTO_MULTI 0x0c00
+#define UCC_UART_UPSMR_FRZ 0x0200
+#define UCC_UART_UPSMR_RZS 0x0100
+#define UCC_UART_UPSMR_SYN 0x0080
+#define UCC_UART_UPSMR_DRT 0x0040
+#define UCC_UART_UPSMR_PEN 0x0010
+#define UCC_UART_UPSMR_RPM_MASK 0x000c
+#define UCC_UART_UPSMR_RPM_ODD 0x0000
+#define UCC_UART_UPSMR_RPM_LOW 0x0004
+#define UCC_UART_UPSMR_RPM_EVEN 0x0008
+#define UCC_UART_UPSMR_RPM_HIGH 0x000C
+#define UCC_UART_UPSMR_TPM_MASK 0x0003
+#define UCC_UART_UPSMR_TPM_ODD 0x0000
+#define UCC_UART_UPSMR_TPM_LOW 0x0001
+#define UCC_UART_UPSMR_TPM_EVEN 0x0002
+#define UCC_UART_UPSMR_TPM_HIGH 0x0003
/* UCC Transmit On Demand Register (UTODR) */
#define UCC_SLOW_TOD 0x8000
#define UCC_FAST_TOD 0x8000
+/* UCC Bus Mode Register masks */
+/* Not to be confused with the Bundle Mode Register */
+#define UCC_BMR_GBL 0x20
+#define UCC_BMR_BO_BE 0x10
+#define UCC_BMR_CETM 0x04
+#define UCC_BMR_DTB 0x02
+#define UCC_BMR_BDB 0x01
+
/* Function code masks */
#define FC_GBL 0x20
#define FC_DTB_LCL 0x02
diff --git a/include/asm-powerpc/ucc.h b/include/asm-powerpc/ucc.h
index afe3076..f96ea54 100644
--- a/include/asm-powerpc/ucc.h
+++ b/include/asm-powerpc/ucc.h
@@ -28,35 +28,13 @@ enum ucc_speed_type {
UCC_SPEED_TYPE_FAST, UCC_SPEED_TYPE_SLOW
};
-/* Initial UCCs Parameter RAM address relative to: MEM_MAP_BASE (IMMR).
-*/
-enum ucc_pram_initial_offset {
- UCC_PRAM_OFFSET_UCC1 = 0x8400,
- UCC_PRAM_OFFSET_UCC2 = 0x8500,
- UCC_PRAM_OFFSET_UCC3 = 0x8600,
- UCC_PRAM_OFFSET_UCC4 = 0x9000,
- UCC_PRAM_OFFSET_UCC5 = 0x8000,
- UCC_PRAM_OFFSET_UCC6 = 0x8100,
- UCC_PRAM_OFFSET_UCC7 = 0x8200,
- UCC_PRAM_OFFSET_UCC8 = 0x8300
-};
-
/* ucc_set_type
* Sets UCC to slow or fast mode.
*
* ucc_num - (In) number of UCC (0-7).
- * regs - (In) pointer to registers base for the UCC.
* speed - (In) slow or fast mode for UCC.
*/
-int ucc_set_type(int ucc_num, struct ucc_common *regs,
- enum ucc_speed_type speed);
-
-/* ucc_init_guemr
- * Init the Guemr register.
- *
- * regs - (In) pointer to registers base for the UCC.
- */
-int ucc_init_guemr(struct ucc_common *regs);
+int ucc_set_type(unsigned int ucc_num, enum ucc_speed_type speed);
int ucc_set_qe_mux_mii_mng(int ucc_num);
diff --git a/include/asm-powerpc/ucc_slow.h b/include/asm-powerpc/ucc_slow.h
index fdaac9d..0980e6a 100644
--- a/include/asm-powerpc/ucc_slow.h
+++ b/include/asm-powerpc/ucc_slow.h
@@ -148,9 +148,10 @@ enum ucc_slow_diag_mode {
struct ucc_slow_info {
int ucc_num;
+ int protocol; /* QE_CR_PROTOCOL_xxx */
enum qe_clock rx_clock;
enum qe_clock tx_clock;
- u32 regs;
+ phys_addr_t regs;
int irq;
u16 uccm_mask;
int data_mem_part;
@@ -186,7 +187,7 @@ struct ucc_slow_info {
struct ucc_slow_private {
struct ucc_slow_info *us_info;
- struct ucc_slow *us_regs; /* a pointer to memory map of UCC regs */
+ struct ucc_slow __iomem *us_regs; /* Ptr to memory map of UCC regs */
struct ucc_slow_pram *us_pram; /* a pointer to the parameter RAM */
u32 us_pram_offset;
int enabled_tx; /* Whether channel is enabled for Tx (ENT) */
@@ -277,12 +278,12 @@ void ucc_slow_graceful_stop_tx(struct ucc_slow_private * uccs);
*/
void ucc_slow_stop_tx(struct ucc_slow_private * uccs);
-/* ucc_slow_restart_x
+/* ucc_slow_restart_tx
* Restarts transmitting on a specified slow UCC.
*
* uccs - (In) pointer to the slow UCC structure.
*/
-void ucc_slow_restart_x(struct ucc_slow_private * uccs);
+void ucc_slow_restart_tx(struct ucc_slow_private *uccs);
u32 ucc_slow_get_qe_cr_subblock(int uccs_num);
--
1.5.2.4
^ permalink raw reply related
* Re: 2.6.23-rc6-mm1 -- powerpc link failure
From: Segher Boessenkool @ 2007-09-19 16:36 UTC (permalink / raw)
To: Andy Whitcroft; +Cc: linuxppc-dev, Andrew Morton, linux-kernel
In-Reply-To: <20070919092848.GG973@shadowen.org>
> I am seeing this strange link error from a PowerMac G5 (powerpc):
>
> [...]
> KSYM .tmp_kallsyms2.S
> AS .tmp_kallsyms2.o
> LD vmlinux.o
> ld: dynreloc miscount for fs/built-in.o, section .opd
> ld: can not edit opd Bad value
> make: *** [vmlinux.o] Error 1
>
> Compiler version below.
It's an ld error, could you show us your ld version instead? And
please try with current mainline ld, too?
Segher
^ permalink raw reply
* RE: U-Boot problems with MPC8272ADS
From: Manil Gaouar @ 2007-09-19 16:23 UTC (permalink / raw)
To: linuxppc-embedded
Hi all,
I have been trying many things to solve this problem, I found using a
JTAG that U-Boot is running from flash so my JP9 jumper should stay in
BCSR.
I still can not have display on my com port, do you know what I have to
check more in the U-Boot code to make sure the come port is enabled? Is
there a test I can do?
Since I don't have a display, I want to put in my env var in U-Boot the
ip=3D..., BootCmd=3D..., so it will look like something like this:
bootcmd=3Dset ipaddr 192.168.1.123;tftp 0x10200000 uImage;bootm=20
bootargs=3Droot=3D/dev/nfs nfsroot=3D192.168.1.125:/nfs
ip=3D192.168.1.123::192.168.1.125:::eth0:off console=3DttyS0
Is those commands have to be written in /include/configs/stamp.h?
Thx for any help...
-----Original Message-----
From: linuxppc-embedded-bounces+mgaouar=3Dsolacom.com@ozlabs.org
[mailto:linuxppc-embedded-bounces+mgaouar=3Dsolacom.com@ozlabs.org] On
Behalf Of linuxppc-embedded-request@ozlabs.org
Sent: Thursday, September 13, 2007 3:55 PM
To: linuxppc-embedded@ozlabs.org
Subject: Linuxppc-embedded Digest, Vol 37, Issue 27
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Today's Topics:
1. U-Boot problems with MPC8272ADS (Manil Gaouar)
----------------------------------------------------------------------
Message: 1
Date: Thu, 13 Sep 2007 15:55:05 -0400
From: "Manil Gaouar" <mgaouar@solacom.com>
Subject: U-Boot problems with MPC8272ADS
To: <linuxppc-embedded@ozlabs.org>
Message-ID:
<9A1468054ED2FD40907CC3B2C1871D400106CC84@hermes.versatel.com>
Content-Type: text/plain; charset=3D"us-ascii"
Hi all,
=20
I have a MPC8272ADS evaluation board from Motorolla. I am trying to run
U-Boot and Linux kernel 2.6 on it. I am using the 4.1 ELDK, U-Boot from
the git repos, and Linux kernel 2.6 from git repos.
=20
I am burning U-Boot into the flash using a BDI2000.
=20
My problem is:=20
=20
1- When burning the U-Boot and setting the jumper JP9 in BSCR
everything works fine, I reboot the board and the memory at 0xfff00000
is locked which probably means that U-Boot is running, but I have no
display on my serial link (running cu S0@115200).
2- When I put the jumper JP6 in memory position the card keeps
resetting and I have a message error if I connect the BDI to the board
saying:
=20
- TARGET: processing user reset request
- BDI asserts HRESET
- Reset JTAG controller passed
- Bypass check: 0x00000001 =3D> 0x00000001
- JTAG exists check passed
- COP status is 0x7D
- Check running state failed
- TARGET: Target PVR is 0x80822014
*** TARGET: resetting target failed
# PPC: unexpected response from target
- TARGET: target will be restarted in 10 sec
8272>
=20
And it keeps resetting and same message again and again.
=20
Here is my BDI CFG file:
=20
; bdiGDB configuration file for MPC8272ADS board
; ----------------------------------------------
[INIT]
; init core register
WREG MSR 0x00001002 ;MSR : ME,RI
WM32 0x0F010004 0xFFFFFFC3 ;SYPCR: disable watchdog
WM32 0x0F0101A8 0x04700000 ;IMMR : internal space @
0x04700000
WM32 0x04710024 0x100C0000 ;BCR : Single PQ2, ..
WM32 0x04710c94 0x00000001 ;RMR : checkstop reset
enable
; init memory controller
=20
WM32 0x04710104 0xFF800876 ;OR0: Flash 8MB, CS early
negate, 11 w.s., Timing relax
WM32 0x04710100 0xFF801801 ;BR0: Flash @0xFF800000,
32bit, no parity
WM32 0x0471010C 0xFFFF8010 ;OR1: BCSR 32KB, all types
access, 1 w.s.
WM32 0x04710108 0x04501801 ;BR1: BCSR @0x04500000,
32bit, no parity
WM32 0x04710124 0xFFFF8866 ;OR4: EEPROM 32KB, all
types access, 6 w.s.
WM32 0x04710120 0xC2000801 ;BR4: EEPROM @0xC2000000,
8bit, no parity
; init SDRAM Init (PPC bus)
WM16 0x04710184 0x2800 ;MPTPR: Divide Bus clock
by 41
WM8 0x0471019C 0x13 ;PSRT : Divide MPTPR
output by 20
WM32 0x04710114 0xfe002ec0 ;OR2 : 32MB, 2 banks,
row start at A9, 11 rows
WM32 0x04710110 0x00000041 ;BR2 : SDRAM
@0x00000000, 64bit, no parity
WM32 0x04710190 0x824b36a3 ;PSDMR: Precharge all
banks
WM32 0x04710190 0xaa4b36a3
WM8 0x00000000 0x00 ;Access SDRAM
WM32 0x04710190 0x8a4b36a3 ;PSDMR: CBR Refresh
WM8 0x00000000 0xFF ;Access SDRAM
WM8 0x00000000 0xFF ;Access SDRAM
WM8 0x00000000 0xFF ;Access SDRAM
WM8 0x00000000 0xFF ;Access SDRAM
WM8 0x00000000 0xFF ;Access SDRAM
WM8 0x00000000 0xFF ;Access SDRAM
WM8 0x00000000 0xFF ;Access SDRAM
WM8 0x00000000 0xFF ;Access SDRAM
WM32 0x04710190 0x9a4b36a3 ;PSDMR: Mode Set
WM8 0x00000190 0x00 ;Access SDRAM
WM32 0x04710190 0xc24b36a3 ;PSDMR: enable refresh,
normal operation
[TARGET]
CPUTYPE 8272 ;the CPU type
JTAGCLOCK 0 ;use 16 MHz JTAG clock
POWERUP 7000 ;start delay after power-up detected in ms
BOOTADDR 0xfff00100 ;boot address used for start-up break
WORKSPACE 0x04700000 ;workspace in target RAM for fast
download
;MEMDELAY 2000 ;additional memory access delay
=20
[HOST]
IP 172.16.0.120
FILE u-boot.bin
FORMAT BIN
;FILE E:\temp\test16k.bin
;FORMAT BIN 0x04708000
LOAD MANUAL ;load code MANUAL or AUTO after reset
DEBUGPORT 2001
PROMPT 8272> ;new prompt for Telnet
;DUMP /home/solacom/bdi/dump.bin
[FLASH]
CHIPTYPE I28BX8 ; Flash type
CHIPSIZE 0x200000 ; Single chip size (2 Mbyte)
BUSWIDTH 32 ; total width for the whole SIMM
WORKSPACE 0x04700000 ;workspace in target RAM for fast
download
FILE /home/solacom/bdi/1MB_junk.bin
FORMAT BIN 0xFF800000
ERASE 0xFF800000 ;erase sector 4 of flash SIMM
ERASE 0xFF840000 ;erase sector 5 of flash SIMM
ERASE 0xFF880000 ;erase sector 6 of flash SIMM
ERASE 0xFF8C0000 ;erase sector 7 of flash SIMM
[REGS]
DMM1 0x04700000
FILE reg8272.def
=20
Here are the commands I used to upload the U-Boot:
=20
8272>unlock
8272>erase
8272>erase 0xfff00000
8272>prog 0xfff00000 u-boot.bin
The prgrammation goes fine.
When I do a 8272>md 0xfff00000 I have the same data as the beginning of
the u-boot.bin, which means that my upload is correct.
=20
Can you help me on this please? My TEXT_BASE is 0xFFF00000 which means
u-boot run from flash, but putting JP9 means running from RAM right?
=20
I am confused about this, I've read a tutorial www.jungo.com/openrg/doc/
4.7/installation_guide/pdf/ppc.pdf and followed their steps to start
U-Boot, but I can not see the U_Boot prompt, may be U-Boot is not
running, I have no clue...Can we know when U-Boot is not running without
display?
=20
Thx for any help...
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^ permalink raw reply
* Re: [PATCH 2/5] Implement generic time of day clocksource for powerpc machines.
From: Daniel Walker @ 2007-09-19 15:43 UTC (permalink / raw)
To: Tony Breeds
Cc: linuxppc-dev, Thomas Gleixner, Paul Mackerras, Realtime Kernel,
johnstul
In-Reply-To: <20070919064947.4B5A1399910@thor>
On Wed, 2007-09-19 at 16:49 +1000, Tony Breeds wrote:
> +/* clocksource code */
> +/* FIXME: provide an RTC clocksource /or/ use a better name */
> +static cycle_t timebase_read(void)
> +{
> + if (__USE_RTC())
> + return (cycle_t)get_rtc();
> + return (cycle_t)get_tb();
> +}
If you switch to the rtc do the shift and mult need to change?
> +void update_vsyscall(struct timespec *wall_time, struct clocksource
> *clock)
> +{
> + u64 t2x, stamp_xsec;
> +
> + if (__USE_RTC() || clock != &clocksource_timebase)
> + return;
> +
> + /* Make userspace gettimeofday spin until we're done. */
> + ++vdso_data->tb_update_count;
> + smp_mb();
> +
> + /* XXX this assumes clock->shift == 22 */
> + /* 4611686018 ~= 2^(20+64-22) / 1e9 */
> + t2x = (u64) clock->mult * 4611686018ULL;
It might make the code more readable if you put that constant into a
macro that gives it a name.
Daniel
^ permalink raw reply
* [PATCH net-2.6.24] eHEA: poll function update for new NAPI scheme
From: Jan-Bernd Themann @ 2007-09-19 15:40 UTC (permalink / raw)
To: David Miller
Cc: Thomas Klein, Jan-Bernd Themann, netdev, linux-kernel, linux-ppc,
Christoph Raisch, Marcus Eder
Update of ehea_poll function to work with new NAPI scheme.
Signed-off-by: Jan-Bernd Themann <themann@de.ibm.com>
---
Hi David,
this patch is built upon the patches provided by Mel Gorman
(2.6.23-rc6-mm1: Build failure on ppc64 drivers/net/ehea/ehea_main.c)
and Roland Dreier
([PATCH net-2.6.24] Fix refcounting problem with netif_rx_reschedule())
drivers/net/ehea/ehea_main.c | 29 +++++++++++++++--------------
1 files changed, 15 insertions(+), 14 deletions(-)
diff --git a/drivers/net/ehea/ehea_main.c b/drivers/net/ehea/ehea_main.c
index c5fc0b1..1bb39a7 100644
--- a/drivers/net/ehea/ehea_main.c
+++ b/drivers/net/ehea/ehea_main.c
@@ -609,6 +609,7 @@ static struct ehea_cqe *ehea_proc_cqes(struct ehea_port_res *pr, int my_quota)
}
#define EHEA_NAPI_POLL_NUM_BEFORE_IRQ 16
+#define EHEA_POLL_MAX_CQES 65535
static int ehea_poll(struct napi_struct *napi, int budget)
{
@@ -616,15 +617,18 @@ static int ehea_poll(struct napi_struct *napi, int budget)
struct net_device *dev = pr->port->netdev;
struct ehea_cqe *cqe;
struct ehea_cqe *cqe_skb = NULL;
- int force_irq, wqe_index, rx;
-
- cqe = ehea_poll_rq1(pr->qp, &wqe_index);
- cqe_skb = ehea_poll_cq(pr->send_cq);
+ int force_irq, wqe_index;
+ int rx = 0;
force_irq = (pr->poll_counter > EHEA_NAPI_POLL_NUM_BEFORE_IRQ);
+ cqe_skb = ehea_proc_cqes(pr, EHEA_POLL_MAX_CQES);
+
+ if (!force_irq)
+ rx += ehea_proc_rwqes(dev, pr, budget - rx);
- if ((!cqe && !cqe_skb) || force_irq) {
+ while ((rx != budget) || force_irq) {
pr->poll_counter = 0;
+ force_irq = 0;
netif_rx_complete(dev, napi);
ehea_reset_cq_ep(pr->recv_cq);
ehea_reset_cq_ep(pr->send_cq);
@@ -634,19 +638,16 @@ static int ehea_poll(struct napi_struct *napi, int budget)
cqe_skb = ehea_poll_cq(pr->send_cq);
if (!cqe && !cqe_skb)
- return 0;
+ return rx;
if (!netif_rx_reschedule(dev, napi))
- return 0;
- }
+ return rx;
- rx = ehea_proc_rwqes(dev, pr, budget);
- cqe = ehea_poll_rq1(pr->qp, &wqe_index);
- cqe_skb = ehea_proc_cqes(pr, 300);
-
- if (cqe || cqe_skb)
- pr->poll_counter++;
+ cqe_skb = ehea_proc_cqes(pr, EHEA_POLL_MAX_CQES);
+ rx += ehea_proc_rwqes(dev, pr, budget - rx);
+ }
+ pr->poll_counter++;
return rx;
}
--
1.5.2
^ permalink raw reply related
* Re: [PATCH] powerpc: Avoid pointless WARN_ON(irqs_disabled()) from panic codepath
From: Randy Dunlap @ 2007-09-19 15:29 UTC (permalink / raw)
To: Satyam Sharma
Cc: Mailing List, Kamalesh Babulal, linuxppc-dev, Paul Mackerras,
Linux
In-Reply-To: <alpine.LFD.0.999.0709191844360.7697@enigma.security.iitk.ac.in>
On Wed, 19 Sep 2007 19:15:00 +0530 (IST) Satyam Sharma wrote:
>
> In fact, it turns out OSDL's cross-compiler toolchains were built with
> crosstool itself. Should also add that those OSDL compilers are too old
> (gcc version 3.4.x-3.5.x mostly -- my build was totally spammed with those
> "+m" in asm constraints related warnings), so I'll try and build a few
> more recent ones (at least for the more popular platforms) over the
> weekend too.
Hi,
Please let us know if/when you have newer cross-compiler tarballs
available.
Thanks.
---
~Randy
^ permalink raw reply
* Re: Eth1 init and link status
From: Jeyner Gil Caga @ 2007-09-19 15:35 UTC (permalink / raw)
To: - Reyneke; +Cc: linuxppc-embedded
In-Reply-To: <BAY101-F3306F36C70FAA4D450C466BEB90@phx.gbl>
[-- Attachment #1: Type: text/plain, Size: 1552 bytes --]
In you statement, initialise correctly (i.e. receive and transmit), did you
use like ping or ftp to do it?
What do you mean by the word initialise?
Are you saying that after Linux has completely booted up:
1. you have one computer pinging to eth0 and you can ping eth0?
2. if eth0 is connected to the network, you use the same computer to ping
eth1 and you can ping eth1?
3. while you are pinging eth1 and you disconnect eth0 from the network,you
can not ping eth1?
On 9/19/07, - Reyneke <reynekejunk@hotmail.com> wrote:
>
> HI,
>
> We've run into a bit of an odd problem and we are not sure where to go and
> look for the cause.
>
> We have some 440EPx based hardware with two GIG-Ethernet ports using RGMII
> and 2x ET1011C PHY's. Problem is that eth1 will only initialise correctly
> (i.e. receive and transmit) if eth0 has a link. Eth0 always work OK,
> regardless of eth1 status. Eth1 will work OK if eth0 has a link (i.e.
> initialised) at time of setup. Once initialised, eth0 status is
> irrelevant.
> All this is during Linux boot process.
>
> Any ideas?
>
> We can access PHY registers via u-boot (mii commands). Same 1Gig link
> speed
> is used on both ports. Linux kernel is 2.6.19.
>
> Regards
> Jan Reyneke
>
> _________________________________________________________________
> Can you see your house from the sky? Try Live Search Maps
> http://maps.live.com
>
> _______________________________________________
> Linuxppc-embedded mailing list
> Linuxppc-embedded@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-embedded
>
[-- Attachment #2: Type: text/html, Size: 2098 bytes --]
^ permalink raw reply
* Re: cuImage generation
From: Gerhard Pircher @ 2007-09-19 15:25 UTC (permalink / raw)
To: Peter Korsgaard, scottwood; +Cc: linuxppc-dev
In-Reply-To: <87lkb2lm14.fsf@macbook.be.48ers.dk>
-------- Original-Nachricht --------
> Datum: Wed, 19 Sep 2007 17:20:23 +0200
> Von: Peter Korsgaard <jacmet@sunsite.dk>
> An: Scott Wood <scottwood@freescale.com>
> CC: Gerhard Pircher <gerhard_pircher@gmx.net>, linuxppc-dev@ozlabs.org
> Betreff: Re: cuImage generation
> >>>>> "Scott" == Scott Wood <scottwood@freescale.com> writes:
>
> Scott> On Wed, Sep 19, 2007 at 04:53:14PM +0200, Peter Korsgaard wrote:
> >> How is it supposed to work now cuImage no longer is in BOOT_TARGETS?
> >> What make target are you supposed to work. It works if I add
> >> cuImage.83xx to BOOT_TARGETS and call make cuImage.83xx, but that can
> >> hardly be the correct way?
>
> Scott> Ah, OK -- you need to type make zImage, not make uImage.
>
> Ahh, I got fooled by the platform selecting DEFAULT_UIMAGE - Thanks!
I also thought I have to use "make uImage", because of DEFAULT_UIMAGE.
Thanks!
Gerhard
--
Psssst! Schon vom neuen GMX MultiMessenger gehört?
Der kanns mit allen: http://www.gmx.net/de/go/multimessenger
^ permalink raw reply
* Re: cuImage generation
From: Peter Korsgaard @ 2007-09-19 15:20 UTC (permalink / raw)
To: Scott Wood; +Cc: linuxppc-dev
In-Reply-To: <20070919150134.GA8249@ld0162-tx32.am.freescale.net>
>>>>> "Scott" == Scott Wood <scottwood@freescale.com> writes:
Scott> On Wed, Sep 19, 2007 at 04:53:14PM +0200, Peter Korsgaard wrote:
>> How is it supposed to work now cuImage no longer is in BOOT_TARGETS?
>> What make target are you supposed to work. It works if I add
>> cuImage.83xx to BOOT_TARGETS and call make cuImage.83xx, but that can
>> hardly be the correct way?
Scott> Ah, OK -- you need to type make zImage, not make uImage.
Ahh, I got fooled by the platform selecting DEFAULT_UIMAGE - Thanks!
--
Bye, Peter Korsgaard
^ permalink raw reply
* RE: [PATCH] phy: export phy_mii_ioctl
From: Pedro Luis D. L. @ 2007-09-19 15:11 UTC (permalink / raw)
To: linuxppc-embedded
In-Reply-To: <200709191651.47768.jbe@pengutronix.de>
>Pedro,
>=20
>On Wednesday 19 September 2007 13:38, Pedro Luis D. L. wrote:
>> I=B4m using an specific pcm030.dts oftree that works for the 2.6.20 kern=
el.
>> I=B4m not quite familiar with the oftree stuff, but I thought it should =
work
>> also for the 2.6.22.6. Is there any other dts file? Where can I find it?
>=20
>dts patch sent offline.
Thanks for the patch, Juergen. Received and applied, but still doesn't boot=
.
I=B4m starting to suspect there should be something else...
Pedro.
>Juergen
>--=20
>Dipl.-Ing. Juergen Beisert | http://www.pengutronix.de
> Pengutronix - Linux Solutions for Science and Industry
> Handelsregister: Amtsgericht Hildesheim, HRA 2686
> Vertretung Sued/Muenchen, Germany
> Phone: +49-8766-939 228 | Fax: +49-5121-206917-9
_________________________________________________________________
Consigue el nuevo Windows Live Messenger
http://get.live.com/messenger/overview=
^ permalink raw reply
* Re: Configuration-Problem ext-interrupt on mpc52xx
From: Grant Likely @ 2007-09-19 15:09 UTC (permalink / raw)
To: S. Fricke; +Cc: linuxppc-dev
In-Reply-To: <20070919115952.GF5682@sfrouter>
On 9/19/07, S. Fricke <silvio.fricke@googlemail.com> wrote:
> Hi,
>
> how can i configure an "ext interrupt" to high-level? I want a interruption on
> IRQ2, but I checked with an oscilloscope that the pin has a low state and I
> needs a high state.
>
> I have tried, after I got the irq (with irq_of_parse_and_map), set it with
>
> set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH);
>
> But I think it is a system-configuration (irq_desc) and no
> device-configuration.
You shouldn't need to do this. You set your sense level in the device tree.
>From your previous email, your device node looks like this:
> intpin@0 {
> interrupt-parent = <500>;
> interrupts = <1 2 2>;
> };
Which is IRQ2, EDGE_FALLING.
If you change your interrupts property to <1 2 0>, then your sense is
set to LEVEL_HIGH. (Seriously, you need to read the interrupts
section of Documentation/powerpc/mpc52xx-device-tree-bindings.txt.)
g.
--
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.
grant.likely@secretlab.ca
(403) 399-0195
^ permalink raw reply
* Re: cuImage generation
From: Scott Wood @ 2007-09-19 15:01 UTC (permalink / raw)
To: Peter Korsgaard; +Cc: linuxppc-dev
In-Reply-To: <87ps0elnad.fsf@macbook.be.48ers.dk>
On Wed, Sep 19, 2007 at 04:53:14PM +0200, Peter Korsgaard wrote:
> How is it supposed to work now cuImage no longer is in BOOT_TARGETS?
> What make target are you supposed to work. It works if I add
> cuImage.83xx to BOOT_TARGETS and call make cuImage.83xx, but that can
> hardly be the correct way?
Ah, OK -- you need to type make zImage, not make uImage.
-Scott
^ permalink raw reply
* Re: Configuration-Problem ext-interrupt on mpc52xx
From: Juergen Beisert @ 2007-09-19 14:54 UTC (permalink / raw)
To: linuxppc-dev, S. Fricke
In-Reply-To: <20070919115952.GF5682@sfrouter>
[-- Attachment #1: Type: text/plain, Size: 798 bytes --]
Silvio,
On Wednesday 19 September 2007 13:59, S. Fricke wrote:
> how can i configure an "ext interrupt" to high-level? I want a interruption
> on IRQ2, but I checked with an oscilloscope that the pin has a low state
> and I needs a high state.
>
> I have tried, after I got the irq (with irq_of_parse_and_map), set it with
>
> set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH);
>
> But I think it is a system-configuration (irq_desc) and no
> device-configuration.
Try with the attached patch.
Regards,
Juergen
--
Dipl.-Ing. Juergen Beisert | http://www.pengutronix.de
Pengutronix - Linux Solutions for Science and Industry
Handelsregister: Amtsgericht Hildesheim, HRA 2686
Vertretung Sued/Muenchen, Germany
Phone: +49-8766-939 228 | Fax: +49-5121-206917-9
[-- Attachment #2: mpc52xx_extirq_set_type.diff --]
[-- Type: text/x-diff, Size: 1586 bytes --]
---
arch/powerpc/platforms/52xx/mpc52xx_pic.c | 38 ++++++++++++++++++++++++++++++
1 file changed, 38 insertions(+)
Index: arch/powerpc/platforms/52xx/mpc52xx_pic.c
===================================================================
--- arch/powerpc/platforms/52xx/mpc52xx_pic.c.orig
+++ arch/powerpc/platforms/52xx/mpc52xx_pic.c
@@ -25,6 +25,7 @@
#include <linux/stddef.h>
#include <linux/delay.h>
#include <linux/irq.h>
+#include <linux/interrupt.h>
#include <linux/hardirq.h>
#include <asm/io.h>
@@ -107,11 +108,48 @@ static void mpc52xx_extirq_ack(unsigned
io_be_setbit(&intr->ctrl, 27-l2irq);
}
+static int mpc52xx_extirq_set_type(unsigned int virq, unsigned int flow_type)
+{
+ u32 ctrl_reg, type;
+ int irq;
+ int l2irq;
+
+ irq = irq_map[virq].hwirq;
+ l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
+
+ pr_debug("%s: irq=%x. l2=%d flow_type=%d\n", __func__, irq, l2irq, flow_type);
+
+ switch (flow_type) {
+ case IRQF_TRIGGER_HIGH:
+ type = 0;
+ break;
+ case IRQF_TRIGGER_RISING:
+ type = 1;
+ break;
+ case IRQF_TRIGGER_FALLING:
+ type = 2;
+ break;
+ case IRQF_TRIGGER_LOW:
+ type = 3;
+ break;
+ default:
+ type = 0;
+ }
+
+ ctrl_reg = in_be32(&intr->ctrl);
+ ctrl_reg &= ~(0x3 << (22 - (l2irq * 2)));
+ ctrl_reg |= (type << (22 - (l2irq * 2)));
+ out_be32(&intr->ctrl, ctrl_reg);
+
+ return 0;
+}
+
static struct irq_chip mpc52xx_extirq_irqchip = {
.typename = " MPC52xx IRQ[0-3] ",
.mask = mpc52xx_extirq_mask,
.unmask = mpc52xx_extirq_unmask,
.ack = mpc52xx_extirq_ack,
+ .set_type = mpc52xx_extirq_set_type,
};
/*
^ permalink raw reply
* Re: cuImage generation
From: Peter Korsgaard @ 2007-09-19 14:53 UTC (permalink / raw)
To: Scott Wood; +Cc: linuxppc-dev
In-Reply-To: <20070919141953.GB8023@ld0162-tx32.am.freescale.net>
>>>>> "Scott" == Scott Wood <scottwood@freescale.com> writes:
Scott> On Wed, Sep 19, 2007 at 09:28:31AM +0200, Gerhard Pircher wrote:
>> I tried to compile a 2.6.23-rc6 kernel yesterday, but wasn't able to get a
>> cuImage.<platform) out of it (only the uImage file was generated). My
>> platform config defines DEFAULT_UIMAGE and WANT_DEVICE_TREE. Do I need to
>> generate it manually or is there a makefile where I have to specify it?
>> Naturally I added my cuboot wrapper code to the arch/powerpc/boot/Makefile.
I have the same problem here..
Scott> Did you specify a device tree to use in CONFIG_DEVICE_TREE?
Yes.
% grep TREE .config
CONFIG_PROC_DEVICETREE=y
CONFIG_WANT_DEVICE_TREE=y
CONFIG_DEVICE_TREE="mpc8349emitx.dts"
How is it supposed to work now cuImage no longer is in BOOT_TARGETS?
What make target are you supposed to work. It works if I add
cuImage.83xx to BOOT_TARGETS and call make cuImage.83xx, but that can
hardly be the correct way?
--
Bye, Peter Korsgaard
^ permalink raw reply
* Re: [PATCH] phy: export phy_mii_ioctl
From: Juergen Beisert @ 2007-09-19 14:51 UTC (permalink / raw)
To: linuxppc-embedded
In-Reply-To: <BLU106-W94EC8F5D652CCD450801ACAB90@phx.gbl>
Pedro,
On Wednesday 19 September 2007 13:38, Pedro Luis D. L. wrote:
> I=B4m using an specific pcm030.dts oftree that works for the 2.6.20 kerne=
l.
> I=B4m not quite familiar with the oftree stuff, but I thought it should w=
ork
> also for the 2.6.22.6. Is there any other dts file? Where can I find it?
dts patch sent offline.
Juergen
=2D-=20
Dipl.-Ing. Juergen Beisert | http://www.pengutronix.de
=A0Pengutronix - Linux Solutions for Science and Industry
=A0 Handelsregister: Amtsgericht Hildesheim, HRA 2686
=A0 =A0 =A0 Vertretung Sued/Muenchen, Germany
Phone: +49-8766-939 228 | Fax: +49-5121-206917-9
^ permalink raw reply
* Re: PSC in UART mode on TQM5200S
From: Leopold Stotch @ 2007-09-19 14:50 UTC (permalink / raw)
To: Grant Likely; +Cc: linuxppc-embedded
In-Reply-To: <fa686aa40709190733ufd38f1fx7771bd0e98376081@mail.gmail.com>
Thanks, i'll try the both ways.
I'm still afraid of killing factory UBoot without
BDI2000 or working X30 jumper :-)
On 9/19/07, Grant Likely <grant.likely@secretlab.ca> wrote:
> On 9/19/07, Leopold Stotch <l.butterz@gmail.com> wrote:
> > Thank you for the answer, Grant !
> > I knew nothing about port_config register before your answer :-(
> > I haven't changed any processor registers yet
> > because i'm still searching where i can do this.
> > Can you tell me, is it UBoot specific or kernel specific or both ?
> > And i already know about MPC5200's device tree in 2.6.x kernel but not in
> > 2.4.x...
>
> It is best to do it in u-boot; but if you cannot (or don't want to)
> change your u-boot image, then you can fix up the port_config value
> during early kernel boot.
>
> Cheers,
> g.
>
> --
> Grant Likely, B.Sc., P.Eng.
> Secret Lab Technologies Ltd.
> grant.likely@secretlab.ca
> (403) 399-0195
>
--
Best regards,
Leopold Stotch
^ permalink raw reply
* Re: [NEWBIE] Interrupt-problem mpc5200
From: Grant Likely @ 2007-09-19 14:31 UTC (permalink / raw)
To: S. Fricke; +Cc: linuxppc-dev
In-Reply-To: <20070919071643.GE5682@sfrouter>
On 9/19/07, S. Fricke <silvio.fricke@googlemail.com> wrote:
> OK, my dts is now:
>
> / {
> /* ... */
> soc5200@f0000000 {
> /* ... */
> intpin@0 {
> interrupt-parent = <500>;
> interrupts = <1 2 2>;
> };
> /* ... */
> };
> /* ... */
> };
Note: your intpin node does not (and probably should not) need to be a
child of the soc node.
Cheers,
g.
--
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.
grant.likely@secretlab.ca
(403) 399-0195
^ permalink raw reply
* RE: [PATCH] phy: export phy_mii_ioctl
From: Pedro Luis D. L. @ 2007-09-19 14:31 UTC (permalink / raw)
To: linuxppc-embedded
In-Reply-To: <9e4733910709190656w3e979191mcd0d0776d46283cf@mail.gmail.com>
On 9/19/07, Jon Smirl wrote:
>On 9/19/07, Pedro Luis D. L. wrote:
>>
>> Hello Jon,
>> I=B4m also working with a Phytec pcm030, but I can=B4t get it booted...
>> Which kernel are you using?
>> I tried to apply the 7 bestcomm patches from Sylvain and patch over thes=
e with this new ones that Domen released.
>> The base kernel I=B4m using is 2.6.22.6 from kernel.org.
>> Although I used the patch that creates pcm030.c in arch/platforms/52xx/ =
and compiled using this file, it gets halted at booting time.
>>
>> Bytes transferred =3D 5091 (13e3 hex)
>> ## Booting image at 00500000 ...
>> Image Name: Linux-2.6.22.6
>> Created: 2007-09-19 8:53:02 UTC
>> Image Type: PowerPC Linux Kernel Image (gzip compressed)
>> Data Size: 1196911 Bytes =3D 1.1 MB
>> Load Address: 00000000
>> Entry Point: 00000000
>> Verifying Checksum ... OK
>> Uncompressing Kernel Image ... OK
>> Booting using flat device tree at 0x400000
>>
>> (No more output and boot is halted)
>=20
=20
I checked that and both are the same:
In pcm030.c:
static int __init pcm030_probe(void)
{
unsigned long node =3D of_get_flat_dt_root();
if (!of_flat_dt_is_compatible(node, "pcm030"))
return 0;
return 1;
}
define_machine(pcm030) {
.name =3D "pcm030",
.probe =3D pcm030_probe,
.setup_arch =3D pcm030_setup_arch,
.restart =3D mpc52xx_restart,
.init =3D pcm030_init,
.init_IRQ =3D mpc52xx_init_irq,
.get_irq =3D mpc52xx_get_irq,
.show_cpuinfo =3D pcm030_show_cpuinfo,
.calibrate_decr =3D generic_calibrate_decr,
};
in pcm030.dts:
model =3D "pcm030";
compatible =3D "pcm030\0mpc5200b\0mpc52xx";
#address-cells =3D ;
#size-cells =3D ;
And it still doesn=B4t boot...
I know it sounds hard, but... Can I skip the "if (!of_flat_dt_is_compatible=
(node, "pcm030"))" line?
This pcm030.c and pcm030.dts files work and boot with 2.6.20 kernel...
Pedro Dominguez
=20
_________________________________________________________________
Consigue el nuevo Windows Live Messenger
http://get.live.com/messenger/overview=
^ permalink raw reply
* Re: cuImage generation
From: Scott Wood @ 2007-09-19 14:19 UTC (permalink / raw)
To: Gerhard Pircher; +Cc: linuxppc-dev
In-Reply-To: <20070919072831.322800@gmx.net>
On Wed, Sep 19, 2007 at 09:28:31AM +0200, Gerhard Pircher wrote:
> I tried to compile a 2.6.23-rc6 kernel yesterday, but wasn't able to get a
> cuImage.<platform) out of it (only the uImage file was generated). My
> platform config defines DEFAULT_UIMAGE and WANT_DEVICE_TREE. Do I need to
> generate it manually or is there a makefile where I have to specify it?
> Naturally I added my cuboot wrapper code to the arch/powerpc/boot/Makefile.
Did you specify a device tree to use in CONFIG_DEVICE_TREE?
-Scott
^ permalink raw reply
* Re: Where did the fs_enet patches go?
From: Scott Wood @ 2007-09-19 14:18 UTC (permalink / raw)
To: Esben Haabendal; +Cc: LinuxPPC-dev
In-Reply-To: <8406613ce51e309ebffa430dcec8bbf6@127.0.0.1>
On Wed, Sep 19, 2007 at 10:25:40AM +0200, Esben Haabendal wrote:
> Most of it is at least ack'ed by Jeff. But he did not seem to like
> the generic bitbanged MDIO library.
> Scott, what is the plan with that part? I need it :-)
Ask Jeff. :-)
He asked for examples of clients of the bitbang library, and I provided
them... he never responded.
-Scott
^ permalink raw reply
* Re: Eth1 init and link status
From: Josh Boyer @ 2007-09-19 14:02 UTC (permalink / raw)
To: - Reyneke; +Cc: linuxppc-embedded
In-Reply-To: <BAY101-F3306F36C70FAA4D450C466BEB90@phx.gbl>
On Wed, 19 Sep 2007 13:54:35 +0000
"- Reyneke" <reynekejunk@hotmail.com> wrote:
> HI,
>
> We've run into a bit of an odd problem and we are not sure where to go and
> look for the cause.
>
> We have some 440EPx based hardware with two GIG-Ethernet ports using RGMII
> and 2x ET1011C PHY's. Problem is that eth1 will only initialise correctly
> (i.e. receive and transmit) if eth0 has a link. Eth0 always work OK,
> regardless of eth1 status. Eth1 will work OK if eth0 has a link (i.e.
> initialised) at time of setup. Once initialised, eth0 status is irrelevant.
> All this is during Linux boot process.
>
> Any ideas?
>
> We can access PHY registers via u-boot (mii commands). Same 1Gig link speed
> is used on both ports. Linux kernel is 2.6.19.
Where did you get your kernel from? 2.6.19 doesn't have any 440EPx
support in it. Maybe you should ask your vendor.
josh
^ permalink raw reply
* Re: [PATCH] phy: export phy_mii_ioctl
From: Jon Smirl @ 2007-09-19 13:56 UTC (permalink / raw)
To: Pedro Luis D. L.; +Cc: netdev, Domen Puncer, linuxppc-embedded
In-Reply-To: <BLU106-W49D16A32DDFE2611E15371CAB90@phx.gbl>
On 9/19/07, Pedro Luis D. L. <carcadiz@hotmail.com> wrote:
>
> Hello Jon,
> I=B4m also working with a Phytec pcm030, but I can=B4t get it booted...
> Which kernel are you using?
> I tried to apply the 7 bestcomm patches from Sylvain and patch over these=
with this new ones that Domen released.
> The base kernel I=B4m using is 2.6.22.6 from kernel.org.
> Although I used the patch that creates pcm030.c in arch/platforms/52xx/ a=
nd compiled using this file, it gets halted at booting time.
>
> Bytes transferred =3D 5091 (13e3 hex)
> ## Booting image at 00500000 ...
> Image Name: Linux-2.6.22.6
> Created: 2007-09-19 8:53:02 UTC
> Image Type: PowerPC Linux Kernel Image (gzip compressed)
> Data Size: 1196911 Bytes =3D 1.1 MB
> Load Address: 00000000
> Entry Point: 00000000
> Verifying Checksum ... OK
> Uncompressing Kernel Image ... OK
> Booting using flat device tree at 0x400000
>
> (No more output and boot is halted)
The root name of your device tree needs to match the name in pcm030.c
pcm030_probe(void). If they don't match this happens.
--=20
Jon Smirl
jonsmirl@gmail.com
^ permalink raw reply
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